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targets/TARGET_Maxim/TARGET_MAX32630/device/pmu_regs.h@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
157:ff67d9f36b67 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the PMU Module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-10 19:24:21 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24667 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _MXC_PMU_REGS_H_
<> 157:ff67d9f36b67 44 #define _MXC_PMU_REGS_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 #include <stdint.h>
<> 157:ff67d9f36b67 47
<> 157:ff67d9f36b67 48 #ifdef __cplusplus
<> 157:ff67d9f36b67 49 extern "C" {
<> 157:ff67d9f36b67 50 #endif
<> 157:ff67d9f36b67 51
<> 157:ff67d9f36b67 52 ///@cond
<> 157:ff67d9f36b67 53 /*
<> 157:ff67d9f36b67 54 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 55 */
<> 157:ff67d9f36b67 56 #ifndef __IO
<> 157:ff67d9f36b67 57 #define __IO volatile
<> 157:ff67d9f36b67 58 #endif
<> 157:ff67d9f36b67 59 #ifndef __I
<> 157:ff67d9f36b67 60 #define __I volatile const
<> 157:ff67d9f36b67 61 #endif
<> 157:ff67d9f36b67 62 #ifndef __O
<> 157:ff67d9f36b67 63 #define __O volatile
<> 157:ff67d9f36b67 64 #endif
<> 157:ff67d9f36b67 65 #ifndef __RO
<> 157:ff67d9f36b67 66 #define __RO volatile const
<> 157:ff67d9f36b67 67 #endif
<> 157:ff67d9f36b67 68 ///@endcond
<> 157:ff67d9f36b67 69
<> 157:ff67d9f36b67 70 /*
<> 157:ff67d9f36b67 71 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 157:ff67d9f36b67 72 access to each register in module.
<> 157:ff67d9f36b67 73 */
<> 157:ff67d9f36b67 74 /**
<> 157:ff67d9f36b67 75 * @ingroup pmuGroup
<> 157:ff67d9f36b67 76 * @defgroup pmu_registers Registers
<> 157:ff67d9f36b67 77 * @brief Registers, Bit Masks and Bit Positions for the PMU Module.
<> 157:ff67d9f36b67 78 * @{
<> 157:ff67d9f36b67 79 */
<> 157:ff67d9f36b67 80 /**
<> 157:ff67d9f36b67 81 * Structure type for the PMU Registers
<> 157:ff67d9f36b67 82 */
<> 157:ff67d9f36b67 83 typedef struct {
<> 157:ff67d9f36b67 84 __IO uint32_t dscadr; /**< <tt>\b 0x0000:</tt> PMU Channel Next Descriptor Address */
<> 157:ff67d9f36b67 85 __IO uint32_t cfg; /**< <tt>\b 0x0004:</tt> PMU Channel Configuration */
<> 157:ff67d9f36b67 86 __IO uint32_t loop; /**< <tt>\b 0x0008:</tt> PMU Channel Loop Counters */
<> 157:ff67d9f36b67 87 __RO uint32_t rsv00C[5]; /**< <tt>\b 0x000C-0x001C:</tt> RESERVED */
<> 157:ff67d9f36b67 88 } mxc_pmu_regs_t;
<> 157:ff67d9f36b67 89 /**@} end of group pmu_registers */
<> 157:ff67d9f36b67 90
<> 157:ff67d9f36b67 91 /*
<> 157:ff67d9f36b67 92 Register offsets for module PMU.
<> 157:ff67d9f36b67 93 */
<> 157:ff67d9f36b67 94 /**
<> 157:ff67d9f36b67 95 * @ingroup pmu_registers
<> 157:ff67d9f36b67 96 * @defgroup PMU_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 97 * @brief PMU Register Offsets from the PMU Base Peripheral Address.
<> 157:ff67d9f36b67 98 * @{
<> 157:ff67d9f36b67 99 */
<> 157:ff67d9f36b67 100 #define MXC_R_PMU_OFFS_DSCADR ((uint32_t)0x00000000UL) /**< Offset from the PMU Base Address: <tt>\b 0x0000</tt>*/
<> 157:ff67d9f36b67 101 #define MXC_R_PMU_OFFS_CFG ((uint32_t)0x00000004UL) /**< Offset from the PMU Base Address: <tt>\b 0x0004</tt>*/
<> 157:ff67d9f36b67 102 #define MXC_R_PMU_OFFS_LOOP ((uint32_t)0x00000008UL) /**< Offset from the PMU Base Address: <tt>\b 0x0008</tt>*/
<> 157:ff67d9f36b67 103 /**@} end of group PMU_Register_Offsets */
<> 157:ff67d9f36b67 104
<> 157:ff67d9f36b67 105 /*
<> 157:ff67d9f36b67 106 Field positions and masks for module PMU.
<> 157:ff67d9f36b67 107 */
<> 157:ff67d9f36b67 108 ///@cond
<> 157:ff67d9f36b67 109 #define MXC_F_PMU_CFG_ENABLE_POS 0
<> 157:ff67d9f36b67 110 #define MXC_F_PMU_CFG_ENABLE ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_ENABLE_POS))
<> 157:ff67d9f36b67 111 #define MXC_F_PMU_CFG_LL_STOPPED_POS 2
<> 157:ff67d9f36b67 112 #define MXC_F_PMU_CFG_LL_STOPPED ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_LL_STOPPED_POS))
<> 157:ff67d9f36b67 113 #define MXC_F_PMU_CFG_MANUAL_POS 3
<> 157:ff67d9f36b67 114 #define MXC_F_PMU_CFG_MANUAL ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_MANUAL_POS))
<> 157:ff67d9f36b67 115 #define MXC_F_PMU_CFG_BUS_ERROR_POS 4
<> 157:ff67d9f36b67 116 #define MXC_F_PMU_CFG_BUS_ERROR ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_BUS_ERROR_POS))
<> 157:ff67d9f36b67 117 #define MXC_F_PMU_CFG_TO_STAT_POS 6
<> 157:ff67d9f36b67 118 #define MXC_F_PMU_CFG_TO_STAT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_TO_STAT_POS))
<> 157:ff67d9f36b67 119 #define MXC_F_PMU_CFG_TO_SEL_POS 11
<> 157:ff67d9f36b67 120 #define MXC_F_PMU_CFG_TO_SEL ((uint32_t)(0x00000007UL << MXC_F_PMU_CFG_TO_SEL_POS))
<> 157:ff67d9f36b67 121 #define MXC_F_PMU_CFG_PS_SEL_POS 14
<> 157:ff67d9f36b67 122 #define MXC_F_PMU_CFG_PS_SEL ((uint32_t)(0x00000003UL << MXC_F_PMU_CFG_PS_SEL_POS))
<> 157:ff67d9f36b67 123 #define MXC_F_PMU_CFG_INTERRUPT_POS 16
<> 157:ff67d9f36b67 124 #define MXC_F_PMU_CFG_INTERRUPT ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INTERRUPT_POS))
<> 157:ff67d9f36b67 125 #define MXC_F_PMU_CFG_INT_EN_POS 17
<> 157:ff67d9f36b67 126 #define MXC_F_PMU_CFG_INT_EN ((uint32_t)(0x00000001UL << MXC_F_PMU_CFG_INT_EN_POS))
<> 157:ff67d9f36b67 127 #define MXC_F_PMU_CFG_BURST_SIZE_POS 24
<> 157:ff67d9f36b67 128 #define MXC_F_PMU_CFG_BURST_SIZE ((uint32_t)(0x0000001FUL << MXC_F_PMU_CFG_BURST_SIZE_POS))
<> 157:ff67d9f36b67 129
<> 157:ff67d9f36b67 130 #define MXC_F_PMU_LOOP_COUNTER_0_POS 0
<> 157:ff67d9f36b67 131 #define MXC_F_PMU_LOOP_COUNTER_0 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_0_POS))
<> 157:ff67d9f36b67 132 #define MXC_F_PMU_LOOP_COUNTER_1_POS 16
<> 157:ff67d9f36b67 133 #define MXC_F_PMU_LOOP_COUNTER_1 ((uint32_t)(0x0000FFFFUL << MXC_F_PMU_LOOP_COUNTER_1_POS))
<> 157:ff67d9f36b67 134
<> 157:ff67d9f36b67 135 /*
<> 157:ff67d9f36b67 136 Field values
<> 157:ff67d9f36b67 137 */
<> 157:ff67d9f36b67 138
<> 157:ff67d9f36b67 139 #define MXC_V_PMU_CFG_TO_SEL_TICKS_4 ((uint32_t)(0x00000000UL))
<> 157:ff67d9f36b67 140 #define MXC_V_PMU_CFG_TO_SEL_TICKS_8 ((uint32_t)(0x00000001UL))
<> 157:ff67d9f36b67 141 #define MXC_V_PMU_CFG_TO_SEL_TICKS_16 ((uint32_t)(0x00000002UL))
<> 157:ff67d9f36b67 142 #define MXC_V_PMU_CFG_TO_SEL_TICKS_32 ((uint32_t)(0x00000003UL))
<> 157:ff67d9f36b67 143 #define MXC_V_PMU_CFG_TO_SEL_TICKS_64 ((uint32_t)(0x00000004UL))
<> 157:ff67d9f36b67 144 #define MXC_V_PMU_CFG_TO_SEL_TICKS_128 ((uint32_t)(0x00000005UL))
<> 157:ff67d9f36b67 145 #define MXC_V_PMU_CFG_TO_SEL_TICKS_256 ((uint32_t)(0x00000006UL))
<> 157:ff67d9f36b67 146 #define MXC_V_PMU_CFG_TO_SEL_TICKS_512 ((uint32_t)(0x00000007UL))
<> 157:ff67d9f36b67 147
<> 157:ff67d9f36b67 148 #define MXC_V_PMU_CFG_PS_SEL_DISABLE ((uint32_t)(0x00000000UL))
<> 157:ff67d9f36b67 149 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_8 ((uint32_t)(0x00000001UL))
<> 157:ff67d9f36b67 150 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_16 ((uint32_t)(0x00000002UL))
<> 157:ff67d9f36b67 151 #define MXC_V_PMU_CFG_PS_SEL_DIV_2_24 ((uint32_t)(0x00000003UL))
<> 157:ff67d9f36b67 152
<> 157:ff67d9f36b67 153 /* Op codes */
<> 157:ff67d9f36b67 154 #define PMU_MOVE_OP 0
<> 157:ff67d9f36b67 155 #define PMU_WRITE_OP 1
<> 157:ff67d9f36b67 156 #define PMU_WAIT_OP 2
<> 157:ff67d9f36b67 157 #define PMU_JUMP_OP 3
<> 157:ff67d9f36b67 158 #define PMU_LOOP_OP 4
<> 157:ff67d9f36b67 159 #define PMU_POLL_OP 5
<> 157:ff67d9f36b67 160 #define PMU_BRANCH_OP 6
<> 157:ff67d9f36b67 161 #define PMU_TRANSFER_OP 7
<> 157:ff67d9f36b67 162
<> 157:ff67d9f36b67 163 /* Bit values used in all decroptiors */
<> 157:ff67d9f36b67 164 #define PMU_NO_INTERRUPT 0 /**< Interrupt flag is NOT set at end of channel execution */
<> 157:ff67d9f36b67 165 #define PMU_INTERRUPT 1 /**< Interrupt flag is set at end of channel execution */
<> 157:ff67d9f36b67 166
<> 157:ff67d9f36b67 167 #define PMU_NO_STOP 0 /**< Do not stop channel after this descriptor ends */
<> 157:ff67d9f36b67 168 #define PMU_STOP 1 /**< Halt PMU channel after this descriptor ends */
<> 157:ff67d9f36b67 169
<> 157:ff67d9f36b67 170 /* Interrupt and Stop bit positions */
<> 157:ff67d9f36b67 171 #define PMU_INT_POS 3
<> 157:ff67d9f36b67 172 #define PMU_STOP_POS 4
<> 157:ff67d9f36b67 173
<> 157:ff67d9f36b67 174 /* MOVE descriptor bit values */
<> 157:ff67d9f36b67 175 #define PMU_MOVE_READ_8_BIT 0 /**< Read size = 8 */
<> 157:ff67d9f36b67 176 #define PMU_MOVE_READ_16_BIT 1 /**< Read size = 16 */
<> 157:ff67d9f36b67 177 #define PMU_MOVE_READ_32_BIT 2 /**< Read size = 32 */
<> 157:ff67d9f36b67 178
<> 157:ff67d9f36b67 179 #define PMU_MOVE_READ_NO_INC 0 /**< read address not incremented */
<> 157:ff67d9f36b67 180 #define PMU_MOVE_READ_INC 1 /**< Auto-Increment read address */
<> 157:ff67d9f36b67 181
<> 157:ff67d9f36b67 182 #define PMU_MOVE_WRITE_8_BIT 0 /**< Write Size = 8 */
<> 157:ff67d9f36b67 183 #define PMU_MOVE_WRITE_16_BIT 1 /**< Write Size = 16 */
<> 157:ff67d9f36b67 184 #define PMU_MOVE_WRITE_32_BIT 2 /**< Write Size = 32 */
<> 157:ff67d9f36b67 185
<> 157:ff67d9f36b67 186 #define PMU_MOVE_WRITE_NO_INC 0 /**< Write address not incremented */
<> 157:ff67d9f36b67 187 #define PMU_MOVE_WRITE_INC 1 /**< Auto_Increment write address */
<> 157:ff67d9f36b67 188
<> 157:ff67d9f36b67 189 #define PMU_MOVE_NO_CONT 0 /**< MOVE does not rely on previous MOVE */
<> 157:ff67d9f36b67 190 #define PMU_MOVE_CONT 1 /**< MOVE continues from read/write address and INC values defined in previous MOVE */
<> 157:ff67d9f36b67 191
<> 157:ff67d9f36b67 192 /* MOVE bit positions */
<> 157:ff67d9f36b67 193 #define PMU_MOVE_READS_POS 5
<> 157:ff67d9f36b67 194 #define PMU_MOVE_READI_POS 7
<> 157:ff67d9f36b67 195 #define PMU_MOVE_WRITES_POS 8
<> 157:ff67d9f36b67 196 #define PMU_MOVE_WRITEI_POS 10
<> 157:ff67d9f36b67 197 #define PMU_MOVE_CONT_POS 11
<> 157:ff67d9f36b67 198 #define PMU_MOVE_LEN_POS 12
<> 157:ff67d9f36b67 199
<> 157:ff67d9f36b67 200 /* WRITE descriptor bit values */
<> 157:ff67d9f36b67 201 #define PMU_WRITE_MASKED_WRITE_VALUE 0 /**< Value = READ_VALUE & (~WRITE_MASK) | WRITE_VALUE */
<> 157:ff67d9f36b67 202 #define PMU_WRITE_PLUS_1 1 /**< Value = READ_VALUE + 1 */
<> 157:ff67d9f36b67 203 #define PMU_WRITE_MINUS_1 2 /**< Value = READ_VALUE - 1 */
<> 157:ff67d9f36b67 204 #define PMU_WRITE_SHIFT_RT_1 3 /**< Value = READ_VALUE >> 1 */
<> 157:ff67d9f36b67 205 #define PMU_WRITE_SHIFT_LT_1 4 /**< Value = READ_VALUE << 1 */
<> 157:ff67d9f36b67 206 #define PMU_WRITE_ROTATE_RT_1 5 /**< Value = READ_VALUE rotated right by 1 (bit 0 becomes bit 31) */
<> 157:ff67d9f36b67 207 #define PMU_WRITE_ROTATE_LT_1 6 /**< Value = READ_VALUE rotated left by 1 (bit 31 becomes bit 0) */
<> 157:ff67d9f36b67 208 #define PMU_WRITE_NOT_READ_VAL 7 /**< Value = ~READ_VALUE */
<> 157:ff67d9f36b67 209 #define PMU_WRITE_XOR_MASK 8 /**< Value = READ_VALUE XOR WRITE_MASK */
<> 157:ff67d9f36b67 210 #define PMU_WRITE_OR_MASK 9 /**< Value = READ_VALUE | WRITE_MASK */
<> 157:ff67d9f36b67 211 #define PMU_WRITE_AND_MASK 10 /**< Value = READ_VALUE & WRITE_MASK */
<> 157:ff67d9f36b67 212
<> 157:ff67d9f36b67 213 /* WRITE bit positions */
<> 157:ff67d9f36b67 214 #define PMU_WRITE_METHOD_POS 8
<> 157:ff67d9f36b67 215
<> 157:ff67d9f36b67 216 /* WAIT descriptor bit values */
<> 157:ff67d9f36b67 217 #define PMU_WAIT_SEL_0 0 /**< Select the interrupt source */
<> 157:ff67d9f36b67 218 #define PMU_WAIT_SEL_1 1
<> 157:ff67d9f36b67 219
<> 157:ff67d9f36b67 220 /* WAIT bit positions */
<> 157:ff67d9f36b67 221 #define PMU_WAIT_WAIT_POS 5
<> 157:ff67d9f36b67 222 #define PMU_WAIT_SEL_POS 6
<> 157:ff67d9f36b67 223
<> 157:ff67d9f36b67 224 /* LOOP descriptor bit values */
<> 157:ff67d9f36b67 225 #define PMU_LOOP_SEL_COUNTER0 0 /**< select Counter0 to count down from */
<> 157:ff67d9f36b67 226 #define PMU_LOOP_SEL_COUNTER1 1 /**< select Counter1 to count down from */
<> 157:ff67d9f36b67 227
<> 157:ff67d9f36b67 228 /* LOOP bit positions */
<> 157:ff67d9f36b67 229 #define PMU_LOOP_SEL_COUNTER_POS 5
<> 157:ff67d9f36b67 230
<> 157:ff67d9f36b67 231 /* POLL descriptor bit values */
<> 157:ff67d9f36b67 232 #define PMU_POLL_OR 0 /**< polling ends when at least one mask bit matches expected data */
<> 157:ff67d9f36b67 233 #define PMU_POLL_AND 1 /**< polling ends when all mask bits matches expected data */
<> 157:ff67d9f36b67 234
<> 157:ff67d9f36b67 235 /* POLL bit positions */
<> 157:ff67d9f36b67 236 #define PMU_POLL_AND_POS 7
<> 157:ff67d9f36b67 237
<> 157:ff67d9f36b67 238 /* BRANCH descriptor bit values */
<> 157:ff67d9f36b67 239 #define PMU_BRANCH_OR 0 /**< branch when any mask bit = or != expected data (based on = or != branch type) */
<> 157:ff67d9f36b67 240 #define PMU_BRANCH_AND 1 /**< branch when all mask bit = or != expected data (based on = or != branch type) */
<> 157:ff67d9f36b67 241
<> 157:ff67d9f36b67 242 #define PMU_BRANCH_TYPE_NOT_EQUAL 0 /**< Branch when polled data != expected data */
<> 157:ff67d9f36b67 243 #define PMU_BRANCH_TYPE_EQUAL 1 /**< Branch when polled data = expected data */
<> 157:ff67d9f36b67 244 #define PMU_BRANCH_TYPE_LESS_OR_EQUAL 2 /**< Branch when polled data <= expected data */
<> 157:ff67d9f36b67 245 #define PMU_BRANCH_TYPE_GREAT_OR_EQUAL 3 /**< Branch when polled data >= expected data */
<> 157:ff67d9f36b67 246 #define PMU_BRANCH_TYPE_LESSER 4 /**< Branch when polled data < expected data */
<> 157:ff67d9f36b67 247 #define PMU_BRANCH_TYPE_GREATER 5 /**< Branch when polled data > expected data */
<> 157:ff67d9f36b67 248
<> 157:ff67d9f36b67 249 /* BRANCH bit positions */
<> 157:ff67d9f36b67 250 #define PMU_BRANCH_AND_POS 7
<> 157:ff67d9f36b67 251 #define PMU_BRANCH_TYPE_POS 8
<> 157:ff67d9f36b67 252
<> 157:ff67d9f36b67 253 /* TRANSFER descriptor bit values */
<> 157:ff67d9f36b67 254 #define PMU_TX_READ_8_BIT 0 /**< Read size = 8 */
<> 157:ff67d9f36b67 255 #define PMU_TX_READ_16_BIT 1 /**< Read size = 16 */
<> 157:ff67d9f36b67 256 #define PMU_TX_READ_32_BIT 2 /**< Read size = 32 */
<> 157:ff67d9f36b67 257
<> 157:ff67d9f36b67 258 #define PMU_TX_READ_NO_INC 0 /**< read address not incremented */
<> 157:ff67d9f36b67 259 #define PMU_TX_READ_INC 1 /**< Auto-Increment read address */
<> 157:ff67d9f36b67 260
<> 157:ff67d9f36b67 261 #define PMU_TX_WRITE_8_BIT 0 /**< Write Size = 8 */
<> 157:ff67d9f36b67 262 #define PMU_TX_WRITE_16_BIT 1 /**< Write Size = 16 */
<> 157:ff67d9f36b67 263 #define PMU_TX_WRITE_32_BIT 2 /**< Write Size = 32 */
<> 157:ff67d9f36b67 264
<> 157:ff67d9f36b67 265 #define PMU_TX_WRITE_NO_INC 0 /**< Write address not incremented */
<> 157:ff67d9f36b67 266 #define PMU_TX_WRITE_INC 1 /**< Auto_Increment write address */
<> 157:ff67d9f36b67 267
<> 157:ff67d9f36b67 268 /* TRANSFER bit positions */
<> 157:ff67d9f36b67 269 #define PMU_TX_READS_POS 5
<> 157:ff67d9f36b67 270 #define PMU_TX_READI_POS 7
<> 157:ff67d9f36b67 271 #define PMU_TX_WRITES_POS 8
<> 157:ff67d9f36b67 272 #define PMU_TX_WRITEI_POS 10
<> 157:ff67d9f36b67 273 #define PMU_TX_LEN_POS 12
<> 157:ff67d9f36b67 274 #define PMU_TX_BS_POS 26
<> 157:ff67d9f36b67 275
<> 157:ff67d9f36b67 276 /* PMU interrupt sources for the WAIT opcode */
<> 157:ff67d9f36b67 277 #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
<> 157:ff67d9f36b67 278 #define PMU_WAIT_IRQ_MASK1_SEL0_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
<> 157:ff67d9f36b67 279 #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
<> 157:ff67d9f36b67 280 #define PMU_WAIT_IRQ_MASK1_SEL0_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
<> 157:ff67d9f36b67 281 #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
<> 157:ff67d9f36b67 282 #define PMU_WAIT_IRQ_MASK1_SEL0_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
<> 157:ff67d9f36b67 283 #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
<> 157:ff67d9f36b67 284 #define PMU_WAIT_IRQ_MASK1_SEL0_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
<> 157:ff67d9f36b67 285 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
<> 157:ff67d9f36b67 286 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
<> 157:ff67d9f36b67 287 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
<> 157:ff67d9f36b67 288 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
<> 157:ff67d9f36b67 289 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
<> 157:ff67d9f36b67 290 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
<> 157:ff67d9f36b67 291 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
<> 157:ff67d9f36b67 292 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
<> 157:ff67d9f36b67 293 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 16))
<> 157:ff67d9f36b67 294 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 17))
<> 157:ff67d9f36b67 295 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 18))
<> 157:ff67d9f36b67 296 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 19))
<> 157:ff67d9f36b67 297 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI0_TX_RX_STALLED ((uint32_t)(0x00000001UL << 20))
<> 157:ff67d9f36b67 298 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI1_TX_RX_STALLED ((uint32_t)(0x00000001UL << 21))
<> 157:ff67d9f36b67 299 #define PMU_WAIT_IRQ_MASK1_SEL0_SPI2_TX_RX_STALLED ((uint32_t)(0x00000001UL << 22))
<> 157:ff67d9f36b67 300 #define PMU_WAIT_IRQ_MASK1_SEL0_SPIB ((uint32_t)(0x00000001UL << 23))
<> 157:ff67d9f36b67 301 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM0_DONE ((uint32_t)(0x00000001UL << 24))
<> 157:ff67d9f36b67 302 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM1_DONE ((uint32_t)(0x00000001UL << 25))
<> 157:ff67d9f36b67 303 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CM2_DONE ((uint32_t)(0x00000001UL << 26))
<> 157:ff67d9f36b67 304 #define PMU_WAIT_IRQ_MASK1_SEL0_I2CS ((uint32_t)(0x00000001UL << 27))
<> 157:ff67d9f36b67 305 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_DONE ((uint32_t)(0x00000001UL << 28))
<> 157:ff67d9f36b67 306 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_READY ((uint32_t)(0x00000001UL << 29))
<> 157:ff67d9f36b67 307 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_HI ((uint32_t)(0x00000001UL << 30))
<> 157:ff67d9f36b67 308 #define PMU_WAIT_IRQ_MASK1_SEL0_ADC_LOW ((uint32_t)(0x00000001UL << 31))
<> 157:ff67d9f36b67 309 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP0 ((uint32_t)(0x00000001UL << 0))
<> 157:ff67d9f36b67 310 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_COMP1 ((uint32_t)(0x00000001UL << 1))
<> 157:ff67d9f36b67 311 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_PRESCALE ((uint32_t)(0x00000001UL << 2))
<> 157:ff67d9f36b67 312 #define PMU_WAIT_IRQ_MASK2_SEL0_RTC_OVERFLOW ((uint32_t)(0x00000001UL << 3))
<> 157:ff67d9f36b67 313 #define PMU_WAIT_IRQ_MASK2_SEL0_PT0_DISABLED ((uint32_t)(0x00000001UL << 4))
<> 157:ff67d9f36b67 314 #define PMU_WAIT_IRQ_MASK2_SEL0_PT1_DISABLED ((uint32_t)(0x00000001UL << 5))
<> 157:ff67d9f36b67 315 #define PMU_WAIT_IRQ_MASK2_SEL0_PT2_DISABLED ((uint32_t)(0x00000001UL << 6))
<> 157:ff67d9f36b67 316 #define PMU_WAIT_IRQ_MASK2_SEL0_PT3_DISABLED ((uint32_t)(0x00000001UL << 7))
<> 157:ff67d9f36b67 317 #define PMU_WAIT_IRQ_MASK2_SEL0_PT4_DISABLED ((uint32_t)(0x00000001UL << 8))
<> 157:ff67d9f36b67 318 #define PMU_WAIT_IRQ_MASK2_SEL0_PT5_DISABLED ((uint32_t)(0x00000001UL << 9))
<> 157:ff67d9f36b67 319 #define PMU_WAIT_IRQ_MASK2_SEL0_PT6_DISABLED ((uint32_t)(0x00000001UL << 10))
<> 157:ff67d9f36b67 320 #define PMU_WAIT_IRQ_MASK2_SEL0_PT7_DISABLED ((uint32_t)(0x00000001UL << 11))
<> 157:ff67d9f36b67 321 #define PMU_WAIT_IRQ_MASK2_SEL0_PT8_DISABLED ((uint32_t)(0x00000001UL << 12))
<> 157:ff67d9f36b67 322 #define PMU_WAIT_IRQ_MASK2_SEL0_PT9_DISABLED ((uint32_t)(0x00000001UL << 13))
<> 157:ff67d9f36b67 323 #define PMU_WAIT_IRQ_MASK2_SEL0_PT10_DISABLED ((uint32_t)(0x00000001UL << 14))
<> 157:ff67d9f36b67 324 #define PMU_WAIT_IRQ_MASK2_SEL0_PT11_DISABLED ((uint32_t)(0x00000001UL << 15))
<> 157:ff67d9f36b67 325 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR0 ((uint32_t)(0x00000001UL << 16))
<> 157:ff67d9f36b67 326 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR1 ((uint32_t)(0x00000001UL << 17))
<> 157:ff67d9f36b67 327 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR2 ((uint32_t)(0x00000001UL << 18))
<> 157:ff67d9f36b67 328 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR3 ((uint32_t)(0x00000001UL << 19))
<> 157:ff67d9f36b67 329 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR4 ((uint32_t)(0x00000001UL << 20))
<> 157:ff67d9f36b67 330 #define PMU_WAIT_IRQ_MASK2_SEL0_TMR5 ((uint32_t)(0x00000001UL << 21))
<> 157:ff67d9f36b67 331 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO0 ((uint32_t)(0x00000001UL << 22))
<> 157:ff67d9f36b67 332 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO1 ((uint32_t)(0x00000001UL << 23))
<> 157:ff67d9f36b67 333 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO2 ((uint32_t)(0x00000001UL << 24))
<> 157:ff67d9f36b67 334 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO3 ((uint32_t)(0x00000001UL << 25))
<> 157:ff67d9f36b67 335 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO4 ((uint32_t)(0x00000001UL << 26))
<> 157:ff67d9f36b67 336 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO5 ((uint32_t)(0x00000001UL << 27))
<> 157:ff67d9f36b67 337 #define PMU_WAIT_IRQ_MASK2_SEL0_GPIO6 ((uint32_t)(0x00000001UL << 28))
<> 157:ff67d9f36b67 338 #define PMU_WAIT_IRQ_MASK2_SEL0_AES ((uint32_t)(0x00000001UL << 29))
<> 157:ff67d9f36b67 339 #define PMU_WAIT_IRQ_MASK2_SEL0_MAA_DONE ((uint32_t)(0x00000001UL << 30))
<> 157:ff67d9f36b67 340 #define PMU_WAIT_IRQ_MASK2_SEL0_OWM ((uint32_t)(0x00000001UL << 31))
<> 157:ff67d9f36b67 341 #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO7 ((uint32_t)(0x00000001UL << 0))
<> 157:ff67d9f36b67 342 #define PMU_WAIT_IRQ_MASK1_SEL1_GPIO8 ((uint32_t)(0x00000001UL << 1))
<> 157:ff67d9f36b67 343 #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_DISABLED ((uint32_t)(0x00000001UL << 2))
<> 157:ff67d9f36b67 344 #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_DISABLED ((uint32_t)(0x00000001UL << 3))
<> 157:ff67d9f36b67 345 #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_DISABLED ((uint32_t)(0x00000001UL << 4))
<> 157:ff67d9f36b67 346 #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_DISABLED ((uint32_t)(0x00000001UL << 5))
<> 157:ff67d9f36b67 347 #define PMU_WAIT_IRQ_MASK1_SEL1_PT0_INT ((uint32_t)(0x00000001UL << 6))
<> 157:ff67d9f36b67 348 #define PMU_WAIT_IRQ_MASK1_SEL1_PT1_INT ((uint32_t)(0x00000001UL << 7))
<> 157:ff67d9f36b67 349 #define PMU_WAIT_IRQ_MASK1_SEL1_PT2_INT ((uint32_t)(0x00000001UL << 8))
<> 157:ff67d9f36b67 350 #define PMU_WAIT_IRQ_MASK1_SEL1_PT3_INT ((uint32_t)(0x00000001UL << 9))
<> 157:ff67d9f36b67 351 #define PMU_WAIT_IRQ_MASK1_SEL1_PT4_INT ((uint32_t)(0x00000001UL << 10))
<> 157:ff67d9f36b67 352 #define PMU_WAIT_IRQ_MASK1_SEL1_PT5_INT ((uint32_t)(0x00000001UL << 11))
<> 157:ff67d9f36b67 353 #define PMU_WAIT_IRQ_MASK1_SEL1_PT6_INT ((uint32_t)(0x00000001UL << 12))
<> 157:ff67d9f36b67 354 #define PMU_WAIT_IRQ_MASK1_SEL1_PT7_INT ((uint32_t)(0x00000001UL << 13))
<> 157:ff67d9f36b67 355 #define PMU_WAIT_IRQ_MASK1_SEL1_PT8_INT ((uint32_t)(0x00000001UL << 14))
<> 157:ff67d9f36b67 356 #define PMU_WAIT_IRQ_MASK1_SEL1_PT9_INT ((uint32_t)(0x00000001UL << 15))
<> 157:ff67d9f36b67 357 #define PMU_WAIT_IRQ_MASK1_SEL1_PT10_INT ((uint32_t)(0x00000001UL << 16))
<> 157:ff67d9f36b67 358 #define PMU_WAIT_IRQ_MASK1_SEL1_PT11_INT ((uint32_t)(0x00000001UL << 17))
<> 157:ff67d9f36b67 359 #define PMU_WAIT_IRQ_MASK1_SEL1_PT12_INT ((uint32_t)(0x00000001UL << 18))
<> 157:ff67d9f36b67 360 #define PMU_WAIT_IRQ_MASK1_SEL1_PT13_INT ((uint32_t)(0x00000001UL << 19))
<> 157:ff67d9f36b67 361 #define PMU_WAIT_IRQ_MASK1_SEL1_PT14_INT ((uint32_t)(0x00000001UL << 20))
<> 157:ff67d9f36b67 362 #define PMU_WAIT_IRQ_MASK1_SEL1_PT15_INT ((uint32_t)(0x00000001UL << 21))
<> 157:ff67d9f36b67 363 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 22))
<> 157:ff67d9f36b67 364 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 23))
<> 157:ff67d9f36b67 365 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_TX_NO_DATA ((uint32_t)(0x00000001UL << 24))
<> 157:ff67d9f36b67 366 #define PMU_WAIT_IRQ_MASK1_SEL1_SPIS_RX_DATA_LOST ((uint32_t)(0x00000001UL << 25))
<> 157:ff67d9f36b67 367 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI0_TX_READY ((uint32_t)(0x00000001UL << 26))
<> 157:ff67d9f36b67 368 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI1_TX_READY ((uint32_t)(0x00000001UL << 27))
<> 157:ff67d9f36b67 369 #define PMU_WAIT_IRQ_MASK1_SEL1_SPI2_TX_READY ((uint32_t)(0x00000001UL << 28))
<> 157:ff67d9f36b67 370 #define PMU_WAIT_IRQ_MASK1_SEL1_UART0_TX_DONE ((uint32_t)(0x00000001UL << 29))
<> 157:ff67d9f36b67 371 #define PMU_WAIT_IRQ_MASK1_SEL1_UART1_TX_DONE ((uint32_t)(0x00000001UL << 30))
<> 157:ff67d9f36b67 372 #define PMU_WAIT_IRQ_MASK1_SEL1_UART2_TX_DONE ((uint32_t)(0x00000001UL << 31))
<> 157:ff67d9f36b67 373 #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_TX_DONE ((uint32_t)(0x00000001UL << 0))
<> 157:ff67d9f36b67 374 #define PMU_WAIT_IRQ_MASK2_SEL1_UART0_RX_DATA_READY ((uint32_t)(0x00000001UL << 1))
<> 157:ff67d9f36b67 375 #define PMU_WAIT_IRQ_MASK2_SEL1_UART1_RX_DATA_READY ((uint32_t)(0x00000001UL << 2))
<> 157:ff67d9f36b67 376 #define PMU_WAIT_IRQ_MASK2_SEL1_UART2_RX_DATA_READY ((uint32_t)(0x00000001UL << 3))
<> 157:ff67d9f36b67 377 #define PMU_WAIT_IRQ_MASK2_SEL1_UART3_RX_DATA_READY ((uint32_t)(0x00000001UL << 4))
<> 157:ff67d9f36b67 378
<> 157:ff67d9f36b67 379 /* PMU interrupt sources for the TRANSFER opcode */
<> 157:ff67d9f36b67 380 #define PMU_TRANSFER_IRQ_UART0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 0))
<> 157:ff67d9f36b67 381 #define PMU_TRANSFER_IRQ_UART0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 1))
<> 157:ff67d9f36b67 382 #define PMU_TRANSFER_IRQ_UART1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 2))
<> 157:ff67d9f36b67 383 #define PMU_TRANSFER_IRQ_UART1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 3))
<> 157:ff67d9f36b67 384 #define PMU_TRANSFER_IRQ_UART2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 4))
<> 157:ff67d9f36b67 385 #define PMU_TRANSFER_IRQ_UART2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 5))
<> 157:ff67d9f36b67 386 #define PMU_TRANSFER_IRQ_UART3_TX_FIFO_AE ((uint32_t)(0x00000001UL << 6))
<> 157:ff67d9f36b67 387 #define PMU_TRANSFER_IRQ_UART3_RX_FIFO_AF ((uint32_t)(0x00000001UL << 7))
<> 157:ff67d9f36b67 388 #define PMU_TRANSFER_IRQ_SPI0_TX_FIFO_AE ((uint32_t)(0x00000001UL << 8))
<> 157:ff67d9f36b67 389 #define PMU_TRANSFER_IRQ_SPI0_RX_FIFO_AF ((uint32_t)(0x00000001UL << 9))
<> 157:ff67d9f36b67 390 #define PMU_TRANSFER_IRQ_SPI1_TX_FIFO_AE ((uint32_t)(0x00000001UL << 10))
<> 157:ff67d9f36b67 391 #define PMU_TRANSFER_IRQ_SPI1_RX_FIFO_AF ((uint32_t)(0x00000001UL << 11))
<> 157:ff67d9f36b67 392 #define PMU_TRANSFER_IRQ_SPI2_TX_FIFO_AE ((uint32_t)(0x00000001UL << 12))
<> 157:ff67d9f36b67 393 #define PMU_TRANSFER_IRQ_SPI2_RX_FIFO_AF ((uint32_t)(0x00000001UL << 13))
<> 157:ff67d9f36b67 394 #define PMU_TRANSFER_IRQ_I2CM0_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 14))
<> 157:ff67d9f36b67 395 #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 15))
<> 157:ff67d9f36b67 396 #define PMU_TRANSFER_IRQ_I2CM0_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 16))
<> 157:ff67d9f36b67 397 #define PMU_TRANSFER_IRQ_I2CM1_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 17))
<> 157:ff67d9f36b67 398 #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 18))
<> 157:ff67d9f36b67 399 #define PMU_TRANSFER_IRQ_I2CM1_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 19))
<> 157:ff67d9f36b67 400 #define PMU_TRANSFER_IRQ_I2CM2_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << 20))
<> 157:ff67d9f36b67 401 #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << 21))
<> 157:ff67d9f36b67 402 #define PMU_TRANSFER_IRQ_I2CM2_RX_FIFO_FULL ((uint32_t)(0x00000001UL << 22))
<> 157:ff67d9f36b67 403 #define PMU_TRANSFER_IRQ_SPIS_TX_FIFO_AE ((uint32_t)(0x00000001UL << 23))
<> 157:ff67d9f36b67 404 #define PMU_TRANSFER_IRQ_SPIS_RX_FIFO_AF ((uint32_t)(0x00000001UL << 24))
<> 157:ff67d9f36b67 405 ///@endcond
<> 157:ff67d9f36b67 406 #ifdef __cplusplus
<> 157:ff67d9f36b67 407 }
<> 157:ff67d9f36b67 408 #endif
<> 157:ff67d9f36b67 409
<> 157:ff67d9f36b67 410 #endif /* _MXC_PMU_REGS_H_ */
<> 157:ff67d9f36b67 411