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targets/TARGET_Maxim/TARGET_MAX32630/device/gpio_regs.h@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
157:ff67d9f36b67 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-10 18:56:06 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24659 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _MXC_GPIO_REGS_H_
<> 157:ff67d9f36b67 44 #define _MXC_GPIO_REGS_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /* **** Includes **** */
<> 157:ff67d9f36b67 47 #include <stdint.h>
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 #ifdef __cplusplus
<> 157:ff67d9f36b67 50 extern "C" {
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 ///@cond
<> 157:ff67d9f36b67 54 /*
<> 157:ff67d9f36b67 55 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 56 */
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 ///@endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /* **** Definitions **** */
<> 157:ff67d9f36b67 72
<> 157:ff67d9f36b67 73 /**
<> 157:ff67d9f36b67 74 * @ingroup gpio
<> 157:ff67d9f36b67 75 * @defgroup gpio_registers Registers
<> 157:ff67d9f36b67 76 * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module.
<> 157:ff67d9f36b67 77 * @{
<> 157:ff67d9f36b67 78 */
<> 157:ff67d9f36b67 79
<> 157:ff67d9f36b67 80 /*
<> 157:ff67d9f36b67 81 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 157:ff67d9f36b67 82 access to each register in module.
<> 157:ff67d9f36b67 83 */
<> 157:ff67d9f36b67 84
<> 157:ff67d9f36b67 85 /**
<> 157:ff67d9f36b67 86 * Structure type to access the GPIO Registers
<> 157:ff67d9f36b67 87 */
<> 157:ff67d9f36b67 88 typedef struct {
<> 157:ff67d9f36b67 89 __IO uint32_t rst_mode[16]; /**< <tt>\b 0x0000-0x003C</tt> GPIO_RST_MODE_P[0..15] Registers - Power-On Reset Output Drive Mode */
<> 157:ff67d9f36b67 90 __IO uint32_t free[16]; /**< <tt>\b 0x0040-0x007C</tt> GPIO_FREE_P[0..15] Registers - Free for GPIO Operation Flags */
<> 157:ff67d9f36b67 91 __IO uint32_t out_mode[16]; /**< <tt>\b 0x0080-0x00BC</tt> GPIO_OUT_MODE_P[0..15] Registers - Output Drive Mode */
<> 157:ff67d9f36b67 92 __IO uint32_t out_val[16]; /**< <tt>\b 0x00C0-0x00FC</tt> GPIO_OUT_VAL_P[0..15] Registers - GPIO Output Value */
<> 157:ff67d9f36b67 93 __IO uint32_t func_sel[16]; /**< <tt>\b 0x0100-0x013C</tt> GPIO_FUNC_SEL_P[0..15] Registers - GPIO Function Select */
<> 157:ff67d9f36b67 94 __IO uint32_t in_mode[16]; /**< <tt>\b 0x0140-0x017C</tt> GPIO_IN_MODE_P[0..15] Registers - GPIO Input Monitoring Mode */
<> 157:ff67d9f36b67 95 __IO uint32_t in_val[16]; /**< <tt>\b 0x0180-0x01BC</tt> GPIO_IN_VAL_P[0..15] Registers - GPIO Input Value */
<> 157:ff67d9f36b67 96 __IO uint32_t int_mode[16]; /**< <tt>\b 0x01C0-0x01FC</tt> GPIO_INT_MODE_P[0..15] Registers - Interrupt Detection Mode */
<> 157:ff67d9f36b67 97 __IO uint32_t intfl[16]; /**< <tt>\b 0x0200-0x023C</tt> GPIO_INTFL_P[0..15] Registers - Interrupt Flags */
<> 157:ff67d9f36b67 98 __IO uint32_t inten[16]; /**< <tt>\b 0x0240-0x027C</tt> GPIO_INTEN_P[0..15] Registers - Interrupt Enables */
<> 157:ff67d9f36b67 99 } mxc_gpio_regs_t;
<> 157:ff67d9f36b67 100 /**@} end of gpio_registers group */
<> 157:ff67d9f36b67 101
<> 157:ff67d9f36b67 102 /*
<> 157:ff67d9f36b67 103 Register offsets for module GPIO.
<> 157:ff67d9f36b67 104 */
<> 157:ff67d9f36b67 105 /**
<> 157:ff67d9f36b67 106 * @ingroup gpio_registers
<> 157:ff67d9f36b67 107 * @defgroup GPIO_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 108 * @brief GPIO Register Offsets from the GPIO Base Address.
<> 157:ff67d9f36b67 109 * @{
<> 157:ff67d9f36b67 110 */
<> 157:ff67d9f36b67 111 /**
<> 157:ff67d9f36b67 112 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 113 * @defgroup gpio_rst_mode_offsets Registers GPIO_RST_MODE_P[0..15] Offsets
<> 157:ff67d9f36b67 114 * @brief GPIO_RST_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 115 * @{
<> 157:ff67d9f36b67 116 */
<> 157:ff67d9f36b67 117 #define MXC_R_GPIO_OFFS_RST_MODE_P0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 118 #define MXC_R_GPIO_OFFS_RST_MODE_P1 ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt>\b 0x0004</tt> */
<> 157:ff67d9f36b67 119 #define MXC_R_GPIO_OFFS_RST_MODE_P2 ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt>\b 0x0008</tt> */
<> 157:ff67d9f36b67 120 #define MXC_R_GPIO_OFFS_RST_MODE_P3 ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt>\b 0x000C</tt> */
<> 157:ff67d9f36b67 121 #define MXC_R_GPIO_OFFS_RST_MODE_P4 ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt>\b 0x0010</tt> */
<> 157:ff67d9f36b67 122 #define MXC_R_GPIO_OFFS_RST_MODE_P5 ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt>\b 0x0014</tt> */
<> 157:ff67d9f36b67 123 #define MXC_R_GPIO_OFFS_RST_MODE_P6 ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt>\b 0x0018</tt> */
<> 157:ff67d9f36b67 124 #define MXC_R_GPIO_OFFS_RST_MODE_P7 ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt>\b 0x001C</tt> */
<> 157:ff67d9f36b67 125 #define MXC_R_GPIO_OFFS_RST_MODE_P8 ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt>\b 0x0020</tt> */
<> 157:ff67d9f36b67 126 #define MXC_R_GPIO_OFFS_RST_MODE_P9 ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt>\b 0x0024</tt> */
<> 157:ff67d9f36b67 127 #define MXC_R_GPIO_OFFS_RST_MODE_P10 ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt>\b 0x0028</tt> */
<> 157:ff67d9f36b67 128 #define MXC_R_GPIO_OFFS_RST_MODE_P11 ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt>\b 0x002C</tt> */
<> 157:ff67d9f36b67 129 #define MXC_R_GPIO_OFFS_RST_MODE_P12 ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt>\b 0x0030</tt> */
<> 157:ff67d9f36b67 130 #define MXC_R_GPIO_OFFS_RST_MODE_P13 ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt>\b 0x0034</tt> */
<> 157:ff67d9f36b67 131 #define MXC_R_GPIO_OFFS_RST_MODE_P14 ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt>\b 0x0038</tt> */
<> 157:ff67d9f36b67 132 #define MXC_R_GPIO_OFFS_RST_MODE_P15 ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt>\b 0x003C</tt> */
<> 157:ff67d9f36b67 133 /**@} end of gpio_rst_mode group */
<> 157:ff67d9f36b67 134 /**
<> 157:ff67d9f36b67 135 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 136 * @defgroup gpio_free_offsets Registers GPIO_FREE_P[0..15] Offsets
<> 157:ff67d9f36b67 137 * @brief GPIO_FREE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 138 * @{
<> 157:ff67d9f36b67 139 */
<> 157:ff67d9f36b67 140 #define MXC_R_GPIO_OFFS_FREE_P0 ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt>\b 0x0040</tt> */
<> 157:ff67d9f36b67 141 #define MXC_R_GPIO_OFFS_FREE_P1 ((uint32_t)0x00000044UL) /**< Offset from GPIO Base Address: <tt>\b 0x0044</tt> */
<> 157:ff67d9f36b67 142 #define MXC_R_GPIO_OFFS_FREE_P2 ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt>\b 0x0048</tt> */
<> 157:ff67d9f36b67 143 #define MXC_R_GPIO_OFFS_FREE_P3 ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt>\b 0x004C</tt> */
<> 157:ff67d9f36b67 144 #define MXC_R_GPIO_OFFS_FREE_P4 ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt>\b 0x0050</tt> */
<> 157:ff67d9f36b67 145 #define MXC_R_GPIO_OFFS_FREE_P5 ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt>\b 0x0054</tt> */
<> 157:ff67d9f36b67 146 #define MXC_R_GPIO_OFFS_FREE_P6 ((uint32_t)0x00000058UL) /**< Offset from GPIO Base Address: <tt>\b 0x0058</tt> */
<> 157:ff67d9f36b67 147 #define MXC_R_GPIO_OFFS_FREE_P7 ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt>\b 0x005C</tt> */
<> 157:ff67d9f36b67 148 #define MXC_R_GPIO_OFFS_FREE_P8 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt>\b 0x0060</tt> */
<> 157:ff67d9f36b67 149 #define MXC_R_GPIO_OFFS_FREE_P9 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt>\b 0x0064</tt> */
<> 157:ff67d9f36b67 150 #define MXC_R_GPIO_OFFS_FREE_P10 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt>\b 0x0068</tt> */
<> 157:ff67d9f36b67 151 #define MXC_R_GPIO_OFFS_FREE_P11 ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt>\b 0x006C</tt> */
<> 157:ff67d9f36b67 152 #define MXC_R_GPIO_OFFS_FREE_P12 ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt>\b 0x0070</tt> */
<> 157:ff67d9f36b67 153 #define MXC_R_GPIO_OFFS_FREE_P13 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt>\b 0x0074</tt> */
<> 157:ff67d9f36b67 154 #define MXC_R_GPIO_OFFS_FREE_P14 ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt>\b 0x0078</tt> */
<> 157:ff67d9f36b67 155 #define MXC_R_GPIO_OFFS_FREE_P15 ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt>\b 0x007C</tt> */
<> 157:ff67d9f36b67 156 /**@} end of gpio_free group */
<> 157:ff67d9f36b67 157 /**
<> 157:ff67d9f36b67 158 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 159 * @defgroup gpio_out_mode_offsets GPIO_OUT_MODE_P[0..15] Registers
<> 157:ff67d9f36b67 160 * @brief GPIO_OUT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 161 * @{
<> 157:ff67d9f36b67 162 */
<> 157:ff67d9f36b67 163 #define MXC_R_GPIO_OFFS_OUT_MODE_P0 ((uint32_t)0x00000080UL) /**< Offset from GPIO Base Address: <tt>\b 0x0080</tt> */
<> 157:ff67d9f36b67 164 #define MXC_R_GPIO_OFFS_OUT_MODE_P1 ((uint32_t)0x00000084UL) /**< Offset from GPIO Base Address: <tt>\b 0x0084</tt> */
<> 157:ff67d9f36b67 165 #define MXC_R_GPIO_OFFS_OUT_MODE_P2 ((uint32_t)0x00000088UL) /**< Offset from GPIO Base Address: <tt>\b 0x0088</tt> */
<> 157:ff67d9f36b67 166 #define MXC_R_GPIO_OFFS_OUT_MODE_P3 ((uint32_t)0x0000008CUL) /**< Offset from GPIO Base Address: <tt>\b 0x008C</tt> */
<> 157:ff67d9f36b67 167 #define MXC_R_GPIO_OFFS_OUT_MODE_P4 ((uint32_t)0x00000090UL) /**< Offset from GPIO Base Address: <tt>\b 0x0090</tt> */
<> 157:ff67d9f36b67 168 #define MXC_R_GPIO_OFFS_OUT_MODE_P5 ((uint32_t)0x00000094UL) /**< Offset from GPIO Base Address: <tt>\b 0x0094</tt> */
<> 157:ff67d9f36b67 169 #define MXC_R_GPIO_OFFS_OUT_MODE_P6 ((uint32_t)0x00000098UL) /**< Offset from GPIO Base Address: <tt>\b 0x0098</tt> */
<> 157:ff67d9f36b67 170 #define MXC_R_GPIO_OFFS_OUT_MODE_P7 ((uint32_t)0x0000009CUL) /**< Offset from GPIO Base Address: <tt>\b 0x009C</tt> */
<> 157:ff67d9f36b67 171 #define MXC_R_GPIO_OFFS_OUT_MODE_P8 ((uint32_t)0x000000A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A0</tt> */
<> 157:ff67d9f36b67 172 #define MXC_R_GPIO_OFFS_OUT_MODE_P9 ((uint32_t)0x000000A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A4</tt> */
<> 157:ff67d9f36b67 173 #define MXC_R_GPIO_OFFS_OUT_MODE_P10 ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00A8</tt> */
<> 157:ff67d9f36b67 174 #define MXC_R_GPIO_OFFS_OUT_MODE_P11 ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x00AC</tt> */
<> 157:ff67d9f36b67 175 #define MXC_R_GPIO_OFFS_OUT_MODE_P12 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B0</tt> */
<> 157:ff67d9f36b67 176 #define MXC_R_GPIO_OFFS_OUT_MODE_P13 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B4</tt> */
<> 157:ff67d9f36b67 177 #define MXC_R_GPIO_OFFS_OUT_MODE_P14 ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00B8</tt> */
<> 157:ff67d9f36b67 178 #define MXC_R_GPIO_OFFS_OUT_MODE_P15 ((uint32_t)0x000000BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00BC</tt> */
<> 157:ff67d9f36b67 179 /**@} end of gpio_out_mode group */
<> 157:ff67d9f36b67 180 /**
<> 157:ff67d9f36b67 181 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 182 * @defgroup gpio_out_val_offsets GPIO_OUT_VAL_P[0..15] Registers
<> 157:ff67d9f36b67 183 * @brief GPIO_OUT_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 184 * @{
<> 157:ff67d9f36b67 185 */
<> 157:ff67d9f36b67 186 #define MXC_R_GPIO_OFFS_OUT_VAL_P0 ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C0</tt> */
<> 157:ff67d9f36b67 187 #define MXC_R_GPIO_OFFS_OUT_VAL_P1 ((uint32_t)0x000000C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C4</tt> */
<> 157:ff67d9f36b67 188 #define MXC_R_GPIO_OFFS_OUT_VAL_P2 ((uint32_t)0x000000C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00C8</tt> */
<> 157:ff67d9f36b67 189 #define MXC_R_GPIO_OFFS_OUT_VAL_P3 ((uint32_t)0x000000CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00CC</tt> */
<> 157:ff67d9f36b67 190 #define MXC_R_GPIO_OFFS_OUT_VAL_P4 ((uint32_t)0x000000D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D0</tt> */
<> 157:ff67d9f36b67 191 #define MXC_R_GPIO_OFFS_OUT_VAL_P5 ((uint32_t)0x000000D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D4</tt> */
<> 157:ff67d9f36b67 192 #define MXC_R_GPIO_OFFS_OUT_VAL_P6 ((uint32_t)0x000000D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00D8</tt> */
<> 157:ff67d9f36b67 193 #define MXC_R_GPIO_OFFS_OUT_VAL_P7 ((uint32_t)0x000000DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00DC</tt> */
<> 157:ff67d9f36b67 194 #define MXC_R_GPIO_OFFS_OUT_VAL_P8 ((uint32_t)0x000000E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E0</tt> */
<> 157:ff67d9f36b67 195 #define MXC_R_GPIO_OFFS_OUT_VAL_P9 ((uint32_t)0x000000E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E4</tt> */
<> 157:ff67d9f36b67 196 #define MXC_R_GPIO_OFFS_OUT_VAL_P10 ((uint32_t)0x000000E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00E8</tt> */
<> 157:ff67d9f36b67 197 #define MXC_R_GPIO_OFFS_OUT_VAL_P11 ((uint32_t)0x000000ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x00EC</tt> */
<> 157:ff67d9f36b67 198 #define MXC_R_GPIO_OFFS_OUT_VAL_P12 ((uint32_t)0x000000F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F0</tt> */
<> 157:ff67d9f36b67 199 #define MXC_R_GPIO_OFFS_OUT_VAL_P13 ((uint32_t)0x000000F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F4</tt> */
<> 157:ff67d9f36b67 200 #define MXC_R_GPIO_OFFS_OUT_VAL_P14 ((uint32_t)0x000000F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x00F8</tt> */
<> 157:ff67d9f36b67 201 #define MXC_R_GPIO_OFFS_OUT_VAL_P15 ((uint32_t)0x000000FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x00FC</tt> */
<> 157:ff67d9f36b67 202 /**@} end of gpio_out_val group */
<> 157:ff67d9f36b67 203 /**
<> 157:ff67d9f36b67 204 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 205 * @defgroup gpio_func_sel_offsets GPIO_FUNC_SEL_P[0..15] Registers
<> 157:ff67d9f36b67 206 * @brief GPIO_FUNC_SEL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 207 * @{
<> 157:ff67d9f36b67 208 */
<> 157:ff67d9f36b67 209 #define MXC_R_GPIO_OFFS_FUNC_SEL_P0 ((uint32_t)0x00000100UL) /**< Offset from GPIO Base Address: <tt>\b 0x0100</tt> */
<> 157:ff67d9f36b67 210 #define MXC_R_GPIO_OFFS_FUNC_SEL_P1 ((uint32_t)0x00000104UL) /**< Offset from GPIO Base Address: <tt>\b 0x0104</tt> */
<> 157:ff67d9f36b67 211 #define MXC_R_GPIO_OFFS_FUNC_SEL_P2 ((uint32_t)0x00000108UL) /**< Offset from GPIO Base Address: <tt>\b 0x0108</tt> */
<> 157:ff67d9f36b67 212 #define MXC_R_GPIO_OFFS_FUNC_SEL_P3 ((uint32_t)0x0000010CUL) /**< Offset from GPIO Base Address: <tt>\b 0x010C</tt> */
<> 157:ff67d9f36b67 213 #define MXC_R_GPIO_OFFS_FUNC_SEL_P4 ((uint32_t)0x00000110UL) /**< Offset from GPIO Base Address: <tt>\b 0x0110</tt> */
<> 157:ff67d9f36b67 214 #define MXC_R_GPIO_OFFS_FUNC_SEL_P5 ((uint32_t)0x00000114UL) /**< Offset from GPIO Base Address: <tt>\b 0x0114</tt> */
<> 157:ff67d9f36b67 215 #define MXC_R_GPIO_OFFS_FUNC_SEL_P6 ((uint32_t)0x00000118UL) /**< Offset from GPIO Base Address: <tt>\b 0x0118</tt> */
<> 157:ff67d9f36b67 216 #define MXC_R_GPIO_OFFS_FUNC_SEL_P7 ((uint32_t)0x0000011CUL) /**< Offset from GPIO Base Address: <tt>\b 0x011C</tt> */
<> 157:ff67d9f36b67 217 #define MXC_R_GPIO_OFFS_FUNC_SEL_P8 ((uint32_t)0x00000120UL) /**< Offset from GPIO Base Address: <tt>\b 0x0120</tt> */
<> 157:ff67d9f36b67 218 #define MXC_R_GPIO_OFFS_FUNC_SEL_P9 ((uint32_t)0x00000124UL) /**< Offset from GPIO Base Address: <tt>\b 0x0124</tt> */
<> 157:ff67d9f36b67 219 #define MXC_R_GPIO_OFFS_FUNC_SEL_P10 ((uint32_t)0x00000128UL) /**< Offset from GPIO Base Address: <tt>\b 0x0128</tt> */
<> 157:ff67d9f36b67 220 #define MXC_R_GPIO_OFFS_FUNC_SEL_P11 ((uint32_t)0x0000012CUL) /**< Offset from GPIO Base Address: <tt>\b 0x012C</tt> */
<> 157:ff67d9f36b67 221 #define MXC_R_GPIO_OFFS_FUNC_SEL_P12 ((uint32_t)0x00000130UL) /**< Offset from GPIO Base Address: <tt>\b 0x0130</tt> */
<> 157:ff67d9f36b67 222 #define MXC_R_GPIO_OFFS_FUNC_SEL_P13 ((uint32_t)0x00000134UL) /**< Offset from GPIO Base Address: <tt>\b 0x0134</tt> */
<> 157:ff67d9f36b67 223 #define MXC_R_GPIO_OFFS_FUNC_SEL_P14 ((uint32_t)0x00000138UL) /**< Offset from GPIO Base Address: <tt>\b 0x0138</tt> */
<> 157:ff67d9f36b67 224 #define MXC_R_GPIO_OFFS_FUNC_SEL_P15 ((uint32_t)0x0000013CUL) /**< Offset from GPIO Base Address: <tt>\b 0x013C</tt> */
<> 157:ff67d9f36b67 225 /**@} end of gpio_func_sel */
<> 157:ff67d9f36b67 226 /**
<> 157:ff67d9f36b67 227 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 228 * @defgroup gpio_in_mode_offsets GPIO_IN_MODE_P[0..15] Registers
<> 157:ff67d9f36b67 229 * @brief GPIO_IN_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 230 * @{
<> 157:ff67d9f36b67 231 */
<> 157:ff67d9f36b67 232 #define MXC_R_GPIO_OFFS_IN_MODE_P0 ((uint32_t)0x00000140UL) /**< Offset from GPIO Base Address: <tt>\b 0x0140</tt> */
<> 157:ff67d9f36b67 233 #define MXC_R_GPIO_OFFS_IN_MODE_P1 ((uint32_t)0x00000144UL) /**< Offset from GPIO Base Address: <tt>\b 0x0144</tt> */
<> 157:ff67d9f36b67 234 #define MXC_R_GPIO_OFFS_IN_MODE_P2 ((uint32_t)0x00000148UL) /**< Offset from GPIO Base Address: <tt>\b 0x0148</tt> */
<> 157:ff67d9f36b67 235 #define MXC_R_GPIO_OFFS_IN_MODE_P3 ((uint32_t)0x0000014CUL) /**< Offset from GPIO Base Address: <tt>\b 0x014C</tt> */
<> 157:ff67d9f36b67 236 #define MXC_R_GPIO_OFFS_IN_MODE_P4 ((uint32_t)0x00000150UL) /**< Offset from GPIO Base Address: <tt>\b 0x0150</tt> */
<> 157:ff67d9f36b67 237 #define MXC_R_GPIO_OFFS_IN_MODE_P5 ((uint32_t)0x00000154UL) /**< Offset from GPIO Base Address: <tt>\b 0x0154</tt> */
<> 157:ff67d9f36b67 238 #define MXC_R_GPIO_OFFS_IN_MODE_P6 ((uint32_t)0x00000158UL) /**< Offset from GPIO Base Address: <tt>\b 0x0158</tt> */
<> 157:ff67d9f36b67 239 #define MXC_R_GPIO_OFFS_IN_MODE_P7 ((uint32_t)0x0000015CUL) /**< Offset from GPIO Base Address: <tt>\b 0x015C</tt> */
<> 157:ff67d9f36b67 240 #define MXC_R_GPIO_OFFS_IN_MODE_P8 ((uint32_t)0x00000160UL) /**< Offset from GPIO Base Address: <tt>\b 0x0160</tt> */
<> 157:ff67d9f36b67 241 #define MXC_R_GPIO_OFFS_IN_MODE_P9 ((uint32_t)0x00000164UL) /**< Offset from GPIO Base Address: <tt>\b 0x0164</tt> */
<> 157:ff67d9f36b67 242 #define MXC_R_GPIO_OFFS_IN_MODE_P10 ((uint32_t)0x00000168UL) /**< Offset from GPIO Base Address: <tt>\b 0x0168</tt> */
<> 157:ff67d9f36b67 243 #define MXC_R_GPIO_OFFS_IN_MODE_P11 ((uint32_t)0x0000016CUL) /**< Offset from GPIO Base Address: <tt>\b 0x016C</tt> */
<> 157:ff67d9f36b67 244 #define MXC_R_GPIO_OFFS_IN_MODE_P12 ((uint32_t)0x00000170UL) /**< Offset from GPIO Base Address: <tt>\b 0x0170</tt> */
<> 157:ff67d9f36b67 245 #define MXC_R_GPIO_OFFS_IN_MODE_P13 ((uint32_t)0x00000174UL) /**< Offset from GPIO Base Address: <tt>\b 0x0174</tt> */
<> 157:ff67d9f36b67 246 #define MXC_R_GPIO_OFFS_IN_MODE_P14 ((uint32_t)0x00000178UL) /**< Offset from GPIO Base Address: <tt>\b 0x0178</tt> */
<> 157:ff67d9f36b67 247 #define MXC_R_GPIO_OFFS_IN_MODE_P15 ((uint32_t)0x0000017CUL) /**< Offset from GPIO Base Address: <tt>\b 0x017C</tt> */
<> 157:ff67d9f36b67 248 /**@} end of gpio_in_mode group */
<> 157:ff67d9f36b67 249 /**
<> 157:ff67d9f36b67 250 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 251 * @defgroup gpio_in_val_offsets GPIO_IN_VAL_P[0..15] Registers
<> 157:ff67d9f36b67 252 * @brief GPIO_IN_VAL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 253 * @{
<> 157:ff67d9f36b67 254 */
<> 157:ff67d9f36b67 255 #define MXC_R_GPIO_OFFS_IN_VAL_P0 ((uint32_t)0x00000180UL) /**< Offset from GPIO Base Address: <tt>\b 0x0180</tt> */
<> 157:ff67d9f36b67 256 #define MXC_R_GPIO_OFFS_IN_VAL_P1 ((uint32_t)0x00000184UL) /**< Offset from GPIO Base Address: <tt>\b 0x0184</tt> */
<> 157:ff67d9f36b67 257 #define MXC_R_GPIO_OFFS_IN_VAL_P2 ((uint32_t)0x00000188UL) /**< Offset from GPIO Base Address: <tt>\b 0x0188</tt> */
<> 157:ff67d9f36b67 258 #define MXC_R_GPIO_OFFS_IN_VAL_P3 ((uint32_t)0x0000018CUL) /**< Offset from GPIO Base Address: <tt>\b 0x018C</tt> */
<> 157:ff67d9f36b67 259 #define MXC_R_GPIO_OFFS_IN_VAL_P4 ((uint32_t)0x00000190UL) /**< Offset from GPIO Base Address: <tt>\b 0x0190</tt> */
<> 157:ff67d9f36b67 260 #define MXC_R_GPIO_OFFS_IN_VAL_P5 ((uint32_t)0x00000194UL) /**< Offset from GPIO Base Address: <tt>\b 0x0194</tt> */
<> 157:ff67d9f36b67 261 #define MXC_R_GPIO_OFFS_IN_VAL_P6 ((uint32_t)0x00000198UL) /**< Offset from GPIO Base Address: <tt>\b 0x0198</tt> */
<> 157:ff67d9f36b67 262 #define MXC_R_GPIO_OFFS_IN_VAL_P7 ((uint32_t)0x0000019CUL) /**< Offset from GPIO Base Address: <tt>\b 0x019C</tt> */
<> 157:ff67d9f36b67 263 #define MXC_R_GPIO_OFFS_IN_VAL_P8 ((uint32_t)0x000001A0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A0</tt> */
<> 157:ff67d9f36b67 264 #define MXC_R_GPIO_OFFS_IN_VAL_P9 ((uint32_t)0x000001A4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A4</tt> */
<> 157:ff67d9f36b67 265 #define MXC_R_GPIO_OFFS_IN_VAL_P10 ((uint32_t)0x000001A8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01A8</tt> */
<> 157:ff67d9f36b67 266 #define MXC_R_GPIO_OFFS_IN_VAL_P11 ((uint32_t)0x000001ACUL) /**< Offset from GPIO Base Address: <tt>\b 0x01AC</tt> */
<> 157:ff67d9f36b67 267 #define MXC_R_GPIO_OFFS_IN_VAL_P12 ((uint32_t)0x000001B0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B0</tt> */
<> 157:ff67d9f36b67 268 #define MXC_R_GPIO_OFFS_IN_VAL_P13 ((uint32_t)0x000001B4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B4</tt> */
<> 157:ff67d9f36b67 269 #define MXC_R_GPIO_OFFS_IN_VAL_P14 ((uint32_t)0x000001B8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01B8</tt> */
<> 157:ff67d9f36b67 270 #define MXC_R_GPIO_OFFS_IN_VAL_P15 ((uint32_t)0x000001BCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01BC</tt> */
<> 157:ff67d9f36b67 271 /**@} end of gpio_in_val group */
<> 157:ff67d9f36b67 272 /**
<> 157:ff67d9f36b67 273 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 274 * @defgroup gpio_int_mode_offsets GPIO_INT_MODE_P[0..15] Registers
<> 157:ff67d9f36b67 275 * @brief GPIO_INT_MODE_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 276 * @{
<> 157:ff67d9f36b67 277 */
<> 157:ff67d9f36b67 278 #define MXC_R_GPIO_OFFS_INT_MODE_P0 ((uint32_t)0x000001C0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C0</tt> */
<> 157:ff67d9f36b67 279 #define MXC_R_GPIO_OFFS_INT_MODE_P1 ((uint32_t)0x000001C4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C4</tt> */
<> 157:ff67d9f36b67 280 #define MXC_R_GPIO_OFFS_INT_MODE_P2 ((uint32_t)0x000001C8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01C8</tt> */
<> 157:ff67d9f36b67 281 #define MXC_R_GPIO_OFFS_INT_MODE_P3 ((uint32_t)0x000001CCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01CC</tt> */
<> 157:ff67d9f36b67 282 #define MXC_R_GPIO_OFFS_INT_MODE_P4 ((uint32_t)0x000001D0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D0</tt> */
<> 157:ff67d9f36b67 283 #define MXC_R_GPIO_OFFS_INT_MODE_P5 ((uint32_t)0x000001D4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D4</tt> */
<> 157:ff67d9f36b67 284 #define MXC_R_GPIO_OFFS_INT_MODE_P6 ((uint32_t)0x000001D8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01D8</tt> */
<> 157:ff67d9f36b67 285 #define MXC_R_GPIO_OFFS_INT_MODE_P7 ((uint32_t)0x000001DCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01DC</tt> */
<> 157:ff67d9f36b67 286 #define MXC_R_GPIO_OFFS_INT_MODE_P8 ((uint32_t)0x000001E0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E0</tt> */
<> 157:ff67d9f36b67 287 #define MXC_R_GPIO_OFFS_INT_MODE_P9 ((uint32_t)0x000001E4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E4</tt> */
<> 157:ff67d9f36b67 288 #define MXC_R_GPIO_OFFS_INT_MODE_P10 ((uint32_t)0x000001E8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01E8</tt> */
<> 157:ff67d9f36b67 289 #define MXC_R_GPIO_OFFS_INT_MODE_P11 ((uint32_t)0x000001ECUL) /**< Offset from GPIO Base Address: <tt>\b 0x01EC</tt> */
<> 157:ff67d9f36b67 290 #define MXC_R_GPIO_OFFS_INT_MODE_P12 ((uint32_t)0x000001F0UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F0</tt> */
<> 157:ff67d9f36b67 291 #define MXC_R_GPIO_OFFS_INT_MODE_P13 ((uint32_t)0x000001F4UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F4</tt> */
<> 157:ff67d9f36b67 292 #define MXC_R_GPIO_OFFS_INT_MODE_P14 ((uint32_t)0x000001F8UL) /**< Offset from GPIO Base Address: <tt>\b 0x01F8</tt> */
<> 157:ff67d9f36b67 293 #define MXC_R_GPIO_OFFS_INT_MODE_P15 ((uint32_t)0x000001FCUL) /**< Offset from GPIO Base Address: <tt>\b 0x01FC</tt> */
<> 157:ff67d9f36b67 294 /**@} end of gpio_int_mode group */
<> 157:ff67d9f36b67 295 /**
<> 157:ff67d9f36b67 296 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 297 * @defgroup gpio_int_flag_offsets GPIO_INTFL_P[0..15] Registers
<> 157:ff67d9f36b67 298 * @brief GPIO_INTFL_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 299 * @{
<> 157:ff67d9f36b67 300 */
<> 157:ff67d9f36b67 301 #define MXC_R_GPIO_OFFS_INTFL_P0 ((uint32_t)0x00000200UL) /**< Offset from GPIO Base Address: <tt>\b 0x0200</tt> */
<> 157:ff67d9f36b67 302 #define MXC_R_GPIO_OFFS_INTFL_P1 ((uint32_t)0x00000204UL) /**< Offset from GPIO Base Address: <tt>\b 0x0204</tt> */
<> 157:ff67d9f36b67 303 #define MXC_R_GPIO_OFFS_INTFL_P2 ((uint32_t)0x00000208UL) /**< Offset from GPIO Base Address: <tt>\b 0x0208</tt> */
<> 157:ff67d9f36b67 304 #define MXC_R_GPIO_OFFS_INTFL_P3 ((uint32_t)0x0000020CUL) /**< Offset from GPIO Base Address: <tt>\b 0x020C</tt> */
<> 157:ff67d9f36b67 305 #define MXC_R_GPIO_OFFS_INTFL_P4 ((uint32_t)0x00000210UL) /**< Offset from GPIO Base Address: <tt>\b 0x0210</tt> */
<> 157:ff67d9f36b67 306 #define MXC_R_GPIO_OFFS_INTFL_P5 ((uint32_t)0x00000214UL) /**< Offset from GPIO Base Address: <tt>\b 0x0214</tt> */
<> 157:ff67d9f36b67 307 #define MXC_R_GPIO_OFFS_INTFL_P6 ((uint32_t)0x00000218UL) /**< Offset from GPIO Base Address: <tt>\b 0x0218</tt> */
<> 157:ff67d9f36b67 308 #define MXC_R_GPIO_OFFS_INTFL_P7 ((uint32_t)0x0000021CUL) /**< Offset from GPIO Base Address: <tt>\b 0x021C</tt> */
<> 157:ff67d9f36b67 309 #define MXC_R_GPIO_OFFS_INTFL_P8 ((uint32_t)0x00000220UL) /**< Offset from GPIO Base Address: <tt>\b 0x0220</tt> */
<> 157:ff67d9f36b67 310 #define MXC_R_GPIO_OFFS_INTFL_P9 ((uint32_t)0x00000224UL) /**< Offset from GPIO Base Address: <tt>\b 0x0224</tt> */
<> 157:ff67d9f36b67 311 #define MXC_R_GPIO_OFFS_INTFL_P10 ((uint32_t)0x00000228UL) /**< Offset from GPIO Base Address: <tt>\b 0x0228</tt> */
<> 157:ff67d9f36b67 312 #define MXC_R_GPIO_OFFS_INTFL_P11 ((uint32_t)0x0000022CUL) /**< Offset from GPIO Base Address: <tt>\b 0x022C</tt> */
<> 157:ff67d9f36b67 313 #define MXC_R_GPIO_OFFS_INTFL_P12 ((uint32_t)0x00000230UL) /**< Offset from GPIO Base Address: <tt>\b 0x0230</tt> */
<> 157:ff67d9f36b67 314 #define MXC_R_GPIO_OFFS_INTFL_P13 ((uint32_t)0x00000234UL) /**< Offset from GPIO Base Address: <tt>\b 0x0234</tt> */
<> 157:ff67d9f36b67 315 #define MXC_R_GPIO_OFFS_INTFL_P14 ((uint32_t)0x00000238UL) /**< Offset from GPIO Base Address: <tt>\b 0x0238</tt> */
<> 157:ff67d9f36b67 316 #define MXC_R_GPIO_OFFS_INTFL_P15 ((uint32_t)0x0000023CUL) /**< Offset from GPIO Base Address: <tt>\b 0x023C</tt> */
<> 157:ff67d9f36b67 317 /**@} end of gpio_int_flag group */
<> 157:ff67d9f36b67 318 /**
<> 157:ff67d9f36b67 319 * @ingroup GPIO_Register_Offsets
<> 157:ff67d9f36b67 320 * @defgroup gpio_int_enable_offsets GPIO_INTEN_P[0..15] Registers
<> 157:ff67d9f36b67 321 * @brief GPIO_INTEN_P[0..15] Register Offsets from the GPIO Base Peripheral Address.
<> 157:ff67d9f36b67 322 * @{
<> 157:ff67d9f36b67 323 */
<> 157:ff67d9f36b67 324 #define MXC_R_GPIO_OFFS_INTEN_P0 ((uint32_t)0x00000240UL) /**< Offset from GPIO Base Address: <tt>\b 0x0240</tt> */
<> 157:ff67d9f36b67 325 #define MXC_R_GPIO_OFFS_INTEN_P1 ((uint32_t)0x00000244UL) /**< Offset from GPIO Base Address: <tt>\b 0x0244</tt> */
<> 157:ff67d9f36b67 326 #define MXC_R_GPIO_OFFS_INTEN_P2 ((uint32_t)0x00000248UL) /**< Offset from GPIO Base Address: <tt>\b 0x0248</tt> */
<> 157:ff67d9f36b67 327 #define MXC_R_GPIO_OFFS_INTEN_P3 ((uint32_t)0x0000024CUL) /**< Offset from GPIO Base Address: <tt>\b 0x024C</tt> */
<> 157:ff67d9f36b67 328 #define MXC_R_GPIO_OFFS_INTEN_P4 ((uint32_t)0x00000250UL) /**< Offset from GPIO Base Address: <tt>\b 0x0250</tt> */
<> 157:ff67d9f36b67 329 #define MXC_R_GPIO_OFFS_INTEN_P5 ((uint32_t)0x00000254UL) /**< Offset from GPIO Base Address: <tt>\b 0x0254</tt> */
<> 157:ff67d9f36b67 330 #define MXC_R_GPIO_OFFS_INTEN_P6 ((uint32_t)0x00000258UL) /**< Offset from GPIO Base Address: <tt>\b 0x0258</tt> */
<> 157:ff67d9f36b67 331 #define MXC_R_GPIO_OFFS_INTEN_P7 ((uint32_t)0x0000025CUL) /**< Offset from GPIO Base Address: <tt>\b 0x025C</tt> */
<> 157:ff67d9f36b67 332 #define MXC_R_GPIO_OFFS_INTEN_P8 ((uint32_t)0x00000260UL) /**< Offset from GPIO Base Address: <tt>\b 0x0260</tt> */
<> 157:ff67d9f36b67 333 #define MXC_R_GPIO_OFFS_INTEN_P9 ((uint32_t)0x00000264UL) /**< Offset from GPIO Base Address: <tt>\b 0x0264</tt> */
<> 157:ff67d9f36b67 334 #define MXC_R_GPIO_OFFS_INTEN_P10 ((uint32_t)0x00000268UL) /**< Offset from GPIO Base Address: <tt>\b 0x0268</tt> */
<> 157:ff67d9f36b67 335 #define MXC_R_GPIO_OFFS_INTEN_P11 ((uint32_t)0x0000026CUL) /**< Offset from GPIO Base Address: <tt>\b 0x026C</tt> */
<> 157:ff67d9f36b67 336 #define MXC_R_GPIO_OFFS_INTEN_P12 ((uint32_t)0x00000270UL) /**< Offset from GPIO Base Address: <tt>\b 0x0270</tt> */
<> 157:ff67d9f36b67 337 #define MXC_R_GPIO_OFFS_INTEN_P13 ((uint32_t)0x00000274UL) /**< Offset from GPIO Base Address: <tt>\b 0x0274</tt> */
<> 157:ff67d9f36b67 338 #define MXC_R_GPIO_OFFS_INTEN_P14 ((uint32_t)0x00000278UL) /**< Offset from GPIO Base Address: <tt>\b 0x0278</tt> */
<> 157:ff67d9f36b67 339 #define MXC_R_GPIO_OFFS_INTEN_P15 ((uint32_t)0x0000027CUL) /**< Offset from GPIO Base Address: <tt>\b 0x027C</tt> */
<> 157:ff67d9f36b67 340 /**@}*/
<> 157:ff67d9f36b67 341 /**@} end of GPIO_Register_Offsets */
<> 157:ff67d9f36b67 342
<> 157:ff67d9f36b67 343 /*
<> 157:ff67d9f36b67 344 Field positions and masks for module GPIO.
<> 157:ff67d9f36b67 345 */
<> 157:ff67d9f36b67 346 /**
<> 157:ff67d9f36b67 347 * @ingroup gpio_registers
<> 157:ff67d9f36b67 348 * @defgroup GPIO_RST_MODE_Register GPIO_RST_MODE
<> 157:ff67d9f36b67 349 * @brief Field Positions and Bit Masks for the GPIO_RST_MODE register.
<> 157:ff67d9f36b67 350 * @{
<> 157:ff67d9f36b67 351 */
<> 157:ff67d9f36b67 352 #define MXC_F_GPIO_RST_MODE_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 353 #define MXC_F_GPIO_RST_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 354 #define MXC_F_GPIO_RST_MODE_PIN1_POS 4 /**< PIN1 Position */
<> 157:ff67d9f36b67 355 #define MXC_F_GPIO_RST_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 356 #define MXC_F_GPIO_RST_MODE_PIN2_POS 8 /**< PIN2 Position */
<> 157:ff67d9f36b67 357 #define MXC_F_GPIO_RST_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 358 #define MXC_F_GPIO_RST_MODE_PIN3_POS 12 /**< PIN3 Position */
<> 157:ff67d9f36b67 359 #define MXC_F_GPIO_RST_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 360 #define MXC_F_GPIO_RST_MODE_PIN4_POS 16 /**< PIN4 Position */
<> 157:ff67d9f36b67 361 #define MXC_F_GPIO_RST_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 362 #define MXC_F_GPIO_RST_MODE_PIN5_POS 20 /**< PIN5 Position */
<> 157:ff67d9f36b67 363 #define MXC_F_GPIO_RST_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 364 #define MXC_F_GPIO_RST_MODE_PIN6_POS 24 /**< PIN6 Position */
<> 157:ff67d9f36b67 365 #define MXC_F_GPIO_RST_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 366 #define MXC_F_GPIO_RST_MODE_PIN7_POS 28 /**< PIN7 Position */
<> 157:ff67d9f36b67 367 #define MXC_F_GPIO_RST_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_RST_MODE_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 368 /**@} end of group GPIO_FREE */
<> 157:ff67d9f36b67 369 /**
<> 157:ff67d9f36b67 370 * @ingroup gpio_registers
<> 157:ff67d9f36b67 371 * @defgroup GPIO_FREE_Register GPIO_FREE
<> 157:ff67d9f36b67 372 * @brief Field Positions and Bit Masks for the GPIO_FREE register.
<> 157:ff67d9f36b67 373 * @{
<> 157:ff67d9f36b67 374 */
<> 157:ff67d9f36b67 375 #define MXC_F_GPIO_FREE_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 376 #define MXC_F_GPIO_FREE_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 377 #define MXC_F_GPIO_FREE_PIN1_POS 1 /**< PIN1 Position */
<> 157:ff67d9f36b67 378 #define MXC_F_GPIO_FREE_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 379 #define MXC_F_GPIO_FREE_PIN2_POS 2 /**< PIN2 Position */
<> 157:ff67d9f36b67 380 #define MXC_F_GPIO_FREE_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 381 #define MXC_F_GPIO_FREE_PIN3_POS 3 /**< PIN3 Position */
<> 157:ff67d9f36b67 382 #define MXC_F_GPIO_FREE_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 383 #define MXC_F_GPIO_FREE_PIN4_POS 4 /**< PIN4 Position */
<> 157:ff67d9f36b67 384 #define MXC_F_GPIO_FREE_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 385 #define MXC_F_GPIO_FREE_PIN5_POS 5 /**< PIN5 Position */
<> 157:ff67d9f36b67 386 #define MXC_F_GPIO_FREE_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 387 #define MXC_F_GPIO_FREE_PIN6_POS 6 /**< PIN6 Position */
<> 157:ff67d9f36b67 388 #define MXC_F_GPIO_FREE_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 389 #define MXC_F_GPIO_FREE_PIN7_POS 7 /**< PIN7 Position */
<> 157:ff67d9f36b67 390 #define MXC_F_GPIO_FREE_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_FREE_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 391 /**@} end of group GPIO_FREE */
<> 157:ff67d9f36b67 392 /**
<> 157:ff67d9f36b67 393 * @ingroup gpio_registers
<> 157:ff67d9f36b67 394 * @defgroup GPIO_OUT_MODE_Register GPIO_OUT_MODE
<> 157:ff67d9f36b67 395 * @brief Field Positions and Bit Masks for the GPIO_OUT_MODE register.
<> 157:ff67d9f36b67 396 * @{
<> 157:ff67d9f36b67 397 */
<> 157:ff67d9f36b67 398 #define MXC_F_GPIO_OUT_MODE_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 399 #define MXC_F_GPIO_OUT_MODE_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 400 #define MXC_F_GPIO_OUT_MODE_PIN1_POS 4 /**< PIN1 Position */
<> 157:ff67d9f36b67 401 #define MXC_F_GPIO_OUT_MODE_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 402 #define MXC_F_GPIO_OUT_MODE_PIN2_POS 8 /**< PIN2 Position */
<> 157:ff67d9f36b67 403 #define MXC_F_GPIO_OUT_MODE_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 404 #define MXC_F_GPIO_OUT_MODE_PIN3_POS 12 /**< PIN3 Position */
<> 157:ff67d9f36b67 405 #define MXC_F_GPIO_OUT_MODE_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 406 #define MXC_F_GPIO_OUT_MODE_PIN4_POS 16 /**< PIN4 Position */
<> 157:ff67d9f36b67 407 #define MXC_F_GPIO_OUT_MODE_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 408 #define MXC_F_GPIO_OUT_MODE_PIN5_POS 20 /**< PIN5 Position */
<> 157:ff67d9f36b67 409 #define MXC_F_GPIO_OUT_MODE_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 410 #define MXC_F_GPIO_OUT_MODE_PIN6_POS 24 /**< PIN6 Position */
<> 157:ff67d9f36b67 411 #define MXC_F_GPIO_OUT_MODE_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 412 #define MXC_F_GPIO_OUT_MODE_PIN7_POS 28 /**< PIN7 Position */
<> 157:ff67d9f36b67 413 #define MXC_F_GPIO_OUT_MODE_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_OUT_MODE_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 414 /**@} end of group GPIO_OUT_MODE */
<> 157:ff67d9f36b67 415 /**
<> 157:ff67d9f36b67 416 * @ingroup gpio_registers
<> 157:ff67d9f36b67 417 * @defgroup GPIO_OUT_VAL_Register GPIO_OUT_VAL
<> 157:ff67d9f36b67 418 * @brief Field Positions and Bit Masks for the GPIO_OUT_VAL register.
<> 157:ff67d9f36b67 419 * @{
<> 157:ff67d9f36b67 420 */
<> 157:ff67d9f36b67 421 #define MXC_F_GPIO_OUT_VAL_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 422 #define MXC_F_GPIO_OUT_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 423 #define MXC_F_GPIO_OUT_VAL_PIN1_POS 1 /**< PIN1 Position */
<> 157:ff67d9f36b67 424 #define MXC_F_GPIO_OUT_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 425 #define MXC_F_GPIO_OUT_VAL_PIN2_POS 2 /**< PIN2 Position */
<> 157:ff67d9f36b67 426 #define MXC_F_GPIO_OUT_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 427 #define MXC_F_GPIO_OUT_VAL_PIN3_POS 3 /**< PIN3 Position */
<> 157:ff67d9f36b67 428 #define MXC_F_GPIO_OUT_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 429 #define MXC_F_GPIO_OUT_VAL_PIN4_POS 4 /**< PIN4 Position */
<> 157:ff67d9f36b67 430 #define MXC_F_GPIO_OUT_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 431 #define MXC_F_GPIO_OUT_VAL_PIN5_POS 5 /**< PIN5 Position */
<> 157:ff67d9f36b67 432 #define MXC_F_GPIO_OUT_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 433 #define MXC_F_GPIO_OUT_VAL_PIN6_POS 6 /**< PIN6 Position */
<> 157:ff67d9f36b67 434 #define MXC_F_GPIO_OUT_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 435 #define MXC_F_GPIO_OUT_VAL_PIN7_POS 7 /**< PIN7 Position */
<> 157:ff67d9f36b67 436 #define MXC_F_GPIO_OUT_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_OUT_VAL_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 437 /**@} end of group GPIO_OUT_VAL */
<> 157:ff67d9f36b67 438 /**
<> 157:ff67d9f36b67 439 * @ingroup gpio_registers
<> 157:ff67d9f36b67 440 * @defgroup GPIO_FUNC_SEL_Register GPIO_FUNC_SEL
<> 157:ff67d9f36b67 441 * @brief Field Positions and Bit Masks for the GPIO_FUNC_SEL register.
<> 157:ff67d9f36b67 442 * @{
<> 157:ff67d9f36b67 443 */
<> 157:ff67d9f36b67 444 #define MXC_F_GPIO_FUNC_SEL_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 445 #define MXC_F_GPIO_FUNC_SEL_PIN0 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 446 #define MXC_F_GPIO_FUNC_SEL_PIN1_POS 4 /**< PIN1 Position */
<> 157:ff67d9f36b67 447 #define MXC_F_GPIO_FUNC_SEL_PIN1 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 448 #define MXC_F_GPIO_FUNC_SEL_PIN2_POS 8 /**< PIN2 Position */
<> 157:ff67d9f36b67 449 #define MXC_F_GPIO_FUNC_SEL_PIN2 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 450 #define MXC_F_GPIO_FUNC_SEL_PIN3_POS 12 /**< PIN3 Position */
<> 157:ff67d9f36b67 451 #define MXC_F_GPIO_FUNC_SEL_PIN3 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 452 #define MXC_F_GPIO_FUNC_SEL_PIN4_POS 16 /**< PIN4 Position */
<> 157:ff67d9f36b67 453 #define MXC_F_GPIO_FUNC_SEL_PIN4 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 454 #define MXC_F_GPIO_FUNC_SEL_PIN5_POS 20 /**< PIN5 Position */
<> 157:ff67d9f36b67 455 #define MXC_F_GPIO_FUNC_SEL_PIN5 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 456 #define MXC_F_GPIO_FUNC_SEL_PIN6_POS 24 /**< PIN6 Position */
<> 157:ff67d9f36b67 457 #define MXC_F_GPIO_FUNC_SEL_PIN6 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 458 #define MXC_F_GPIO_FUNC_SEL_PIN7_POS 28 /**< PIN7 Position */
<> 157:ff67d9f36b67 459 #define MXC_F_GPIO_FUNC_SEL_PIN7 ((uint32_t)(0x0000000FUL << MXC_F_GPIO_FUNC_SEL_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 460 /**@} end of group GPIO_FUNC_SEL */
<> 157:ff67d9f36b67 461 /**
<> 157:ff67d9f36b67 462 * @ingroup gpio_registers
<> 157:ff67d9f36b67 463 * @defgroup GPIO_IN_MODE_Register GPIO_IN_MODE
<> 157:ff67d9f36b67 464 * @brief Field Positions and Bit Masks for the GPIO_IN_MODE register.
<> 157:ff67d9f36b67 465 * @{
<> 157:ff67d9f36b67 466 */
<> 157:ff67d9f36b67 467 #define MXC_F_GPIO_IN_MODE_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 468 #define MXC_F_GPIO_IN_MODE_PIN0 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 469 #define MXC_F_GPIO_IN_MODE_PIN1_POS 4 /**< PIN1 Position */
<> 157:ff67d9f36b67 470 #define MXC_F_GPIO_IN_MODE_PIN1 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 471 #define MXC_F_GPIO_IN_MODE_PIN2_POS 8 /**< PIN2 Position */
<> 157:ff67d9f36b67 472 #define MXC_F_GPIO_IN_MODE_PIN2 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 473 #define MXC_F_GPIO_IN_MODE_PIN3_POS 12 /**< PIN3 Position */
<> 157:ff67d9f36b67 474 #define MXC_F_GPIO_IN_MODE_PIN3 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 475 #define MXC_F_GPIO_IN_MODE_PIN4_POS 16 /**< PIN4 Position */
<> 157:ff67d9f36b67 476 #define MXC_F_GPIO_IN_MODE_PIN4 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 477 #define MXC_F_GPIO_IN_MODE_PIN5_POS 20 /**< PIN5 Position */
<> 157:ff67d9f36b67 478 #define MXC_F_GPIO_IN_MODE_PIN5 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 479 #define MXC_F_GPIO_IN_MODE_PIN6_POS 24 /**< PIN6 Position */
<> 157:ff67d9f36b67 480 #define MXC_F_GPIO_IN_MODE_PIN6 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 481 #define MXC_F_GPIO_IN_MODE_PIN7_POS 28 /**< PIN7 Position */
<> 157:ff67d9f36b67 482 #define MXC_F_GPIO_IN_MODE_PIN7 ((uint32_t)(0x00000003UL << MXC_F_GPIO_IN_MODE_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 483 /**@} end of group GPIO_IN_MODE */
<> 157:ff67d9f36b67 484 /**
<> 157:ff67d9f36b67 485 * @ingroup gpio_registers
<> 157:ff67d9f36b67 486 * @defgroup GPIO_IN_VAL_Register GPIO_IN_VAL
<> 157:ff67d9f36b67 487 * @brief Field Positions and Bit Masks for the GPIO_IN_VAL register.
<> 157:ff67d9f36b67 488 * @{
<> 157:ff67d9f36b67 489 */
<> 157:ff67d9f36b67 490 #define MXC_F_GPIO_IN_VAL_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 491 #define MXC_F_GPIO_IN_VAL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 492 #define MXC_F_GPIO_IN_VAL_PIN1_POS 1 /**< PIN1 Position */
<> 157:ff67d9f36b67 493 #define MXC_F_GPIO_IN_VAL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 494 #define MXC_F_GPIO_IN_VAL_PIN2_POS 2 /**< PIN2 Position */
<> 157:ff67d9f36b67 495 #define MXC_F_GPIO_IN_VAL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 496 #define MXC_F_GPIO_IN_VAL_PIN3_POS 3 /**< PIN3 Position */
<> 157:ff67d9f36b67 497 #define MXC_F_GPIO_IN_VAL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 498 #define MXC_F_GPIO_IN_VAL_PIN4_POS 4 /**< PIN4 Position */
<> 157:ff67d9f36b67 499 #define MXC_F_GPIO_IN_VAL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 500 #define MXC_F_GPIO_IN_VAL_PIN5_POS 5 /**< PIN5 Position */
<> 157:ff67d9f36b67 501 #define MXC_F_GPIO_IN_VAL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 502 #define MXC_F_GPIO_IN_VAL_PIN6_POS 6 /**< PIN6 Position */
<> 157:ff67d9f36b67 503 #define MXC_F_GPIO_IN_VAL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 504 #define MXC_F_GPIO_IN_VAL_PIN7_POS 7 /**< PIN7 Position */
<> 157:ff67d9f36b67 505 #define MXC_F_GPIO_IN_VAL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_IN_VAL_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 506 /**@} end of group GPIO_IN_VAL */
<> 157:ff67d9f36b67 507 /**
<> 157:ff67d9f36b67 508 * @ingroup gpio_registers
<> 157:ff67d9f36b67 509 * @defgroup GPIO_INT_MODE_Register GPIO_INT_MODE
<> 157:ff67d9f36b67 510 * @brief Field Positions and Bit Masks for the GPIO_INT_MODE register.
<> 157:ff67d9f36b67 511 * @{
<> 157:ff67d9f36b67 512 */
<> 157:ff67d9f36b67 513 #define MXC_F_GPIO_INT_MODE_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 514 #define MXC_F_GPIO_INT_MODE_PIN0 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 515 #define MXC_F_GPIO_INT_MODE_PIN1_POS 4 /**< PIN1 Position */
<> 157:ff67d9f36b67 516 #define MXC_F_GPIO_INT_MODE_PIN1 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 517 #define MXC_F_GPIO_INT_MODE_PIN2_POS 8 /**< PIN2 Position */
<> 157:ff67d9f36b67 518 #define MXC_F_GPIO_INT_MODE_PIN2 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 519 #define MXC_F_GPIO_INT_MODE_PIN3_POS 12 /**< PIN3 Position */
<> 157:ff67d9f36b67 520 #define MXC_F_GPIO_INT_MODE_PIN3 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 521 #define MXC_F_GPIO_INT_MODE_PIN4_POS 16 /**< PIN4 Position */
<> 157:ff67d9f36b67 522 #define MXC_F_GPIO_INT_MODE_PIN4 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 523 #define MXC_F_GPIO_INT_MODE_PIN5_POS 20 /**< PIN5 Position */
<> 157:ff67d9f36b67 524 #define MXC_F_GPIO_INT_MODE_PIN5 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 525 #define MXC_F_GPIO_INT_MODE_PIN6_POS 24 /**< PIN6 Position */
<> 157:ff67d9f36b67 526 #define MXC_F_GPIO_INT_MODE_PIN6 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 527 #define MXC_F_GPIO_INT_MODE_PIN7_POS 28 /**< PIN7 Position */
<> 157:ff67d9f36b67 528 #define MXC_F_GPIO_INT_MODE_PIN7 ((uint32_t)(0x00000007UL << MXC_F_GPIO_INT_MODE_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 529 /**@} end of group GPIO_INT_MODE */
<> 157:ff67d9f36b67 530 /**
<> 157:ff67d9f36b67 531 * @ingroup gpio_registers
<> 157:ff67d9f36b67 532 * @defgroup GPIO_INTFL_Register GPIO_INTFL
<> 157:ff67d9f36b67 533 * @brief Field Positions and Bit Masks for the GPIO_INTFL register.
<> 157:ff67d9f36b67 534 * @{
<> 157:ff67d9f36b67 535 */
<> 157:ff67d9f36b67 536 #define MXC_F_GPIO_INTFL_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 537 #define MXC_F_GPIO_INTFL_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 538 #define MXC_F_GPIO_INTFL_PIN1_POS 1 /**< PIN1 Position */
<> 157:ff67d9f36b67 539 #define MXC_F_GPIO_INTFL_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 540 #define MXC_F_GPIO_INTFL_PIN2_POS 2 /**< PIN2 Position */
<> 157:ff67d9f36b67 541 #define MXC_F_GPIO_INTFL_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 542 #define MXC_F_GPIO_INTFL_PIN3_POS 3 /**< PIN3 Position */
<> 157:ff67d9f36b67 543 #define MXC_F_GPIO_INTFL_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 544 #define MXC_F_GPIO_INTFL_PIN4_POS 4 /**< PIN4 Position */
<> 157:ff67d9f36b67 545 #define MXC_F_GPIO_INTFL_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 546 #define MXC_F_GPIO_INTFL_PIN5_POS 5 /**< PIN5 Position */
<> 157:ff67d9f36b67 547 #define MXC_F_GPIO_INTFL_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 548 #define MXC_F_GPIO_INTFL_PIN6_POS 6 /**< PIN6 Position */
<> 157:ff67d9f36b67 549 #define MXC_F_GPIO_INTFL_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 550 #define MXC_F_GPIO_INTFL_PIN7_POS 7 /**< PIN7 Position */
<> 157:ff67d9f36b67 551 #define MXC_F_GPIO_INTFL_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTFL_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 552 /**@} end of group GPIO_INTFL */
<> 157:ff67d9f36b67 553 /**
<> 157:ff67d9f36b67 554 * @ingroup gpio_registers
<> 157:ff67d9f36b67 555 * @defgroup GPIO_INTEN_Register GPIO_INTEN
<> 157:ff67d9f36b67 556 * @brief Field Positions and Bit Masks for the GPIO_INTEN register.
<> 157:ff67d9f36b67 557 * @{
<> 157:ff67d9f36b67 558 */
<> 157:ff67d9f36b67 559 #define MXC_F_GPIO_INTEN_PIN0_POS 0 /**< PIN0 Position */
<> 157:ff67d9f36b67 560 #define MXC_F_GPIO_INTEN_PIN0 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN0_POS)) /**< PIN0 Mask */
<> 157:ff67d9f36b67 561 #define MXC_F_GPIO_INTEN_PIN1_POS 1 /**< PIN1 Position */
<> 157:ff67d9f36b67 562 #define MXC_F_GPIO_INTEN_PIN1 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN1_POS)) /**< PIN1 Mask */
<> 157:ff67d9f36b67 563 #define MXC_F_GPIO_INTEN_PIN2_POS 2 /**< PIN2 Position */
<> 157:ff67d9f36b67 564 #define MXC_F_GPIO_INTEN_PIN2 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN2_POS)) /**< PIN2 Mask */
<> 157:ff67d9f36b67 565 #define MXC_F_GPIO_INTEN_PIN3_POS 3 /**< PIN3 Position */
<> 157:ff67d9f36b67 566 #define MXC_F_GPIO_INTEN_PIN3 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN3_POS)) /**< PIN3 Mask */
<> 157:ff67d9f36b67 567 #define MXC_F_GPIO_INTEN_PIN4_POS 4 /**< PIN4 Position */
<> 157:ff67d9f36b67 568 #define MXC_F_GPIO_INTEN_PIN4 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN4_POS)) /**< PIN4 Mask */
<> 157:ff67d9f36b67 569 #define MXC_F_GPIO_INTEN_PIN5_POS 5 /**< PIN5 Position */
<> 157:ff67d9f36b67 570 #define MXC_F_GPIO_INTEN_PIN5 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN5_POS)) /**< PIN5 Mask */
<> 157:ff67d9f36b67 571 #define MXC_F_GPIO_INTEN_PIN6_POS 6 /**< PIN6 Position */
<> 157:ff67d9f36b67 572 #define MXC_F_GPIO_INTEN_PIN6 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN6_POS)) /**< PIN6 Mask */
<> 157:ff67d9f36b67 573 #define MXC_F_GPIO_INTEN_PIN7_POS 7 /**< PIN7 Position */
<> 157:ff67d9f36b67 574 #define MXC_F_GPIO_INTEN_PIN7 ((uint32_t)(0x00000001UL << MXC_F_GPIO_INTEN_PIN7_POS)) /**< PIN7 Mask */
<> 157:ff67d9f36b67 575 /**@} end group GPIO_INTEN_Register */
<> 157:ff67d9f36b67 576
<> 157:ff67d9f36b67 577
<> 157:ff67d9f36b67 578 /*
<> 157:ff67d9f36b67 579 Field values and shifted values for module GPIO.
<> 157:ff67d9f36b67 580 */
<> 157:ff67d9f36b67 581 /**
<> 157:ff67d9f36b67 582 * @ingroup GPIO_RST_MODE_Register
<> 157:ff67d9f36b67 583 * @defgroup GPIO_RST_MODE_Values Reset Mode Values
<> 157:ff67d9f36b67 584 * @brief Mode Values for setting the GPIO_RST_MODE Field for different pad modes
<> 157:ff67d9f36b67 585 * @{
<> 157:ff67d9f36b67 586 */
<> 157:ff67d9f36b67 587 #define MXC_V_GPIO_RST_MODE_DRIVE_0 ((uint32_t)(0x00000000UL)) /**< DRIVE_0 */
<> 157:ff67d9f36b67 588 #define MXC_V_GPIO_RST_MODE_WEAK_PULLDOWN ((uint32_t)(0x00000001UL)) /**< WEAK_PULLDOWN */
<> 157:ff67d9f36b67 589 #define MXC_V_GPIO_RST_MODE_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< WEAK_PULLUP */
<> 157:ff67d9f36b67 590 #define MXC_V_GPIO_RST_MODE_DRIVE_1 ((uint32_t)(0x00000003UL)) /**< DRIVE_1 */
<> 157:ff67d9f36b67 591 #define MXC_V_GPIO_RST_MODE_HIGH_Z ((uint32_t)(0x00000004UL)) /**< HIGH_Z */
<> 157:ff67d9f36b67 592 /**@}*/
<> 157:ff67d9f36b67 593
<> 157:ff67d9f36b67 594 /**
<> 157:ff67d9f36b67 595 * @ingroup GPIO_FREE_Register
<> 157:ff67d9f36b67 596 * @defgroup GPIO_FREE_Values Reset Mode Values
<> 157:ff67d9f36b67 597 * @brief Mode Values for setting the GPIO_FREE to Available or Unavailable
<> 157:ff67d9f36b67 598 * @{
<> 157:ff67d9f36b67 599 */
<> 157:ff67d9f36b67 600 #define MXC_V_GPIO_FREE_NOT_AVAILABLE ((uint32_t)(0x00000000UL)) /**< GPIO Pin is Unavailable */
<> 157:ff67d9f36b67 601 #define MXC_V_GPIO_FREE_AVAILABLE ((uint32_t)(0x00000001UL)) /**< GPIO Pin is Available */
<> 157:ff67d9f36b67 602 /**@}*/
<> 157:ff67d9f36b67 603
<> 157:ff67d9f36b67 604 /**
<> 157:ff67d9f36b67 605 * @ingroup GPIO_FREE_Register
<> 157:ff67d9f36b67 606 * @defgroup GPIO_OUT_MODE_Values Output Mode Values
<> 157:ff67d9f36b67 607 * @brief GPIO_OUT_MODE values for setting the different port pin output modes
<> 157:ff67d9f36b67 608 * @{
<> 157:ff67d9f36b67 609 */
<> 157:ff67d9f36b67 610 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLUP ((uint32_t)(0x00000000UL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLUP */
<> 157:ff67d9f36b67 611 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN ((uint32_t)(0x00000001UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN */
<> 157:ff67d9f36b67 612 #define MXC_V_GPIO_OUT_MODE_OPEN_DRAIN_WEAK_PULLUP ((uint32_t)(0x00000002UL)) /**< See \MXIM_Device User Guide for details: OPEN_DRAIN_WEAK_PULLUP */
<> 157:ff67d9f36b67 613 #define MXC_V_GPIO_OUT_MODE_NORMAL_HIGH_Z ((uint32_t)(0x00000004UL)) /**< See \MXIM_Device User Guide for details: NORMAL_HIGH_Z */
<> 157:ff67d9f36b67 614 #define MXC_V_GPIO_OUT_MODE_NORMAL ((uint32_t)(0x00000005UL)) /**< See \MXIM_Device User Guide for details: NORMAL */
<> 157:ff67d9f36b67 615 #define MXC_V_GPIO_OUT_MODE_SLOW_HIGH_Z ((uint32_t)(0x00000006UL)) /**< See \MXIM_Device User Guide for details: SLOW_HIGH_Z */
<> 157:ff67d9f36b67 616 #define MXC_V_GPIO_OUT_MODE_SLOW_DRIVE ((uint32_t)(0x00000007UL)) /**< See \MXIM_Device User Guide for details: SLOW_DRIVE */
<> 157:ff67d9f36b67 617 #define MXC_V_GPIO_OUT_MODE_FAST_HIGH_Z ((uint32_t)(0x00000008UL)) /**< See \MXIM_Device User Guide for details: FAST_HIGH_Z */
<> 157:ff67d9f36b67 618 #define MXC_V_GPIO_OUT_MODE_FAST_DRIVE ((uint32_t)(0x00000009UL)) /**< See \MXIM_Device User Guide for details: FAST_DRIVE */
<> 157:ff67d9f36b67 619 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_WEAK_PULLDOWN ((uint32_t)(0x0000000AUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_WEAK_PULLDOWN */
<> 157:ff67d9f36b67 620 #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE ((uint32_t)(0x0000000BUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE */
<> 157:ff67d9f36b67 621 #define MXC_V_GPIO_OUT_MODE_OPEN_SOURCE_WEAK_PULLDOWN ((uint32_t)(0x0000000CUL)) /**< See \MXIM_Device User Guide for details: OPEN_SOURCE_WEAK_PULLDOWN */
<> 157:ff67d9f36b67 622 #define MXC_V_GPIO_OUT_MODE_HIGH_Z_INPUT_DISABLED ((uint32_t)(0x0000000FUL)) /**< See \MXIM_Device User Guide for details: HIGH_Z_INPUT_DISABLED */
<> 157:ff67d9f36b67 623 /**@}*/
<> 157:ff67d9f36b67 624
<> 157:ff67d9f36b67 625 /**
<> 157:ff67d9f36b67 626 * @ingroup GPIO_FUNC_SEL_Register
<> 157:ff67d9f36b67 627 * @defgroup GPIO_FUNC_SEL_Values Function type selection values
<> 157:ff67d9f36b67 628 * @brief Function selection values for the GPIO_FUNC_SEL Register.
<> 157:ff67d9f36b67 629 * @{
<> 157:ff67d9f36b67 630 */
<> 157:ff67d9f36b67 631 #define MXC_V_GPIO_FUNC_SEL_MODE_GPIO ((uint32_t)(0x00000000UL)) /**< Standard GPIO Mode */
<> 157:ff67d9f36b67 632 #define MXC_V_GPIO_FUNC_SEL_MODE_PT ((uint32_t)(0x00000001UL)) /**< Pulse Train Mode */
<> 157:ff67d9f36b67 633 #define MXC_V_GPIO_FUNC_SEL_MODE_TMR ((uint32_t)(0x00000002UL)) /**< Timer Mode */
<> 157:ff67d9f36b67 634 /**@}*/
<> 157:ff67d9f36b67 635
<> 157:ff67d9f36b67 636 /**
<> 157:ff67d9f36b67 637 * @ingroup GPIO_IN_MODE_Register
<> 157:ff67d9f36b67 638 * @defgroup GPIO_IN_MODE_Values Input mode selection values
<> 157:ff67d9f36b67 639 * @brief Input mode values for selecting the GPIO input mode.
<> 157:ff67d9f36b67 640 * @{
<> 157:ff67d9f36b67 641 */
<> 157:ff67d9f36b67 642 #define MXC_V_GPIO_IN_MODE_NORMAL ((uint32_t)(0x00000000UL)) /**< Normal Input Mode */
<> 157:ff67d9f36b67 643 #define MXC_V_GPIO_IN_MODE_INVERTED ((uint32_t)(0x00000001UL)) /**< Inverted Input Mode */
<> 157:ff67d9f36b67 644 #define MXC_V_GPIO_IN_MODE_ALWAYS_ZERO ((uint32_t)(0x00000002UL)) /**< Always reads 0 */
<> 157:ff67d9f36b67 645 #define MXC_V_GPIO_IN_MODE_ALWAYS_ONE ((uint32_t)(0x00000003UL)) /**< Always reads 1 */
<> 157:ff67d9f36b67 646 /**@}*/
<> 157:ff67d9f36b67 647
<> 157:ff67d9f36b67 648 /**
<> 157:ff67d9f36b67 649 * @ingroup GPIO_INT_MODE_Register
<> 157:ff67d9f36b67 650 * @defgroup GPIO_INT_MODE_Values Interrupt mode selection values
<> 157:ff67d9f36b67 651 * @brief Values for setting the interrupt mode of a GPIO input pin.
<> 157:ff67d9f36b67 652 * @{
<> 157:ff67d9f36b67 653 */
<> 157:ff67d9f36b67 654 #define MXC_V_GPIO_INT_MODE_DISABLE ((uint32_t)(0x00000000UL)) /**< Disable Interrupt for a given port pin */
<> 157:ff67d9f36b67 655 #define MXC_V_GPIO_INT_MODE_FALLING_EDGE ((uint32_t)(0x00000001UL)) /**< Interrupt on falling edge */
<> 157:ff67d9f36b67 656 #define MXC_V_GPIO_INT_MODE_RISING_EDGE ((uint32_t)(0x00000002UL)) /**< Interrupt on rising edge */
<> 157:ff67d9f36b67 657 #define MXC_V_GPIO_INT_MODE_ANY_EDGE ((uint32_t)(0x00000003UL)) /**< Interrupt on rising or falling edge */
<> 157:ff67d9f36b67 658 #define MXC_V_GPIO_INT_MODE_LOW_LVL ((uint32_t)(0x00000004UL)) /**< Interrupt on Low Level */
<> 157:ff67d9f36b67 659 #define MXC_V_GPIO_INT_MODE_HIGH_LVL ((uint32_t)(0x00000005UL)) /**< Interrupt on High Level */
<> 157:ff67d9f36b67 660 /**@}*/
<> 157:ff67d9f36b67 661
<> 157:ff67d9f36b67 662 /**@}*/
<> 157:ff67d9f36b67 663 #ifdef __cplusplus
<> 157:ff67d9f36b67 664 }
<> 157:ff67d9f36b67 665 #endif
<> 157:ff67d9f36b67 666
<> 157:ff67d9f36b67 667 #endif /* _MXC_GPIO_REGS_H_ */
<> 157:ff67d9f36b67 668