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targets/TARGET_Maxim/TARGET_MAX32630/device/spis_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5
<> 157:ff67d9f36b67 6 /* ****************************************************************************
<> 157:ff67d9f36b67 7 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 8 *
<> 157:ff67d9f36b67 9 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 10 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 11 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 13 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 14 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 15 *
<> 157:ff67d9f36b67 16 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 17 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 18 *
<> 157:ff67d9f36b67 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 22 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 23 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 25 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 26 *
<> 157:ff67d9f36b67 27 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 29 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 30 *
<> 157:ff67d9f36b67 31 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 32 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 33 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 34 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 35 * ownership rights.
<> 157:ff67d9f36b67 36 *
<> 157:ff67d9f36b67 37 * $Date: 2016-10-31 17:11:01 -0500 (Mon, 31 Oct 2016) $
<> 157:ff67d9f36b67 38 * $Revision: 24859 $
<> 157:ff67d9f36b67 39 *
<> 157:ff67d9f36b67 40 *************************************************************************** */
<> 157:ff67d9f36b67 41
<> 157:ff67d9f36b67 42 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 43 #ifndef _MXC_SPIS_REGS_H_
<> 157:ff67d9f36b67 44 #define _MXC_SPIS_REGS_H_
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /* **** Includes **** */
<> 157:ff67d9f36b67 47 #include <stdint.h>
<> 157:ff67d9f36b67 48
<> 157:ff67d9f36b67 49 #ifdef __cplusplus
<> 157:ff67d9f36b67 50 extern "C" {
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52
<> 157:ff67d9f36b67 53 ///@cond
<> 157:ff67d9f36b67 54 /*
<> 157:ff67d9f36b67 55 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 56 */
<> 157:ff67d9f36b67 57 #ifndef __IO
<> 157:ff67d9f36b67 58 #define __IO volatile
<> 157:ff67d9f36b67 59 #endif
<> 157:ff67d9f36b67 60 #ifndef __I
<> 157:ff67d9f36b67 61 #define __I volatile const
<> 157:ff67d9f36b67 62 #endif
<> 157:ff67d9f36b67 63 #ifndef __O
<> 157:ff67d9f36b67 64 #define __O volatile
<> 157:ff67d9f36b67 65 #endif
<> 157:ff67d9f36b67 66 #ifndef __RO
<> 157:ff67d9f36b67 67 #define __RO volatile const
<> 157:ff67d9f36b67 68 #endif
<> 157:ff67d9f36b67 69 ///@endcond
<> 157:ff67d9f36b67 70
<> 157:ff67d9f36b67 71 /**
<> 157:ff67d9f36b67 72 * @ingroup spis
<> 157:ff67d9f36b67 73 * @defgroup spis_registers Registers
<> 157:ff67d9f36b67 74 * @brief Registers, Bit Masks and Bit Positions for the SPIS Peripheral Module.
<> 157:ff67d9f36b67 75 * @{
<> 157:ff67d9f36b67 76 */
<> 157:ff67d9f36b67 77
<> 157:ff67d9f36b67 78 /**
<> 157:ff67d9f36b67 79 * Structure type to access the SPI Slave Peripheral Module Registers
<> 157:ff67d9f36b67 80 */
<> 157:ff67d9f36b67 81 typedef struct {
<> 157:ff67d9f36b67 82 __IO uint32_t gen_ctrl; /**< SPIS_GEN_CTRL Register - SPI Slave General Control Register */
<> 157:ff67d9f36b67 83 __IO uint32_t fifo_ctrl; /**< SPIS_FIFO_CTRL Register - SPI Slave FIFO Control Register */
<> 157:ff67d9f36b67 84 __IO uint32_t fifo_stat; /**< SPIS_FIFO_STAT Register - SPI Slave FIFO Status Register */
<> 157:ff67d9f36b67 85 __IO uint32_t intfl; /**< SPIS_INTFL Register - SPI Slave Interrupt Flags */
<> 157:ff67d9f36b67 86 __IO uint32_t inten; /**< SPIS_INTEN Register - SPI Slave Interrupt Enable/Disable Settings */
<> 157:ff67d9f36b67 87 } mxc_spis_regs_t;
<> 157:ff67d9f36b67 88
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90 /**
<> 157:ff67d9f36b67 91 * Structure type for the SPI Slave Transmit and Receive FIFOs.
<> 157:ff67d9f36b67 92 */
<> 157:ff67d9f36b67 93 typedef struct {
<> 157:ff67d9f36b67 94 union { /* 0x0000-0x07FC SPI Slave FIFO TX Write Space */
<> 157:ff67d9f36b67 95 __IO uint8_t tx_8[2048]; /**< 8-bit access to Transmit FIFO */
<> 157:ff67d9f36b67 96 __IO uint16_t tx_16[1024]; /**< 16-bit access to Transmit FIFO */
<> 157:ff67d9f36b67 97 __IO uint32_t tx_32[512]; /**< 32-bit access to Transmit FIFO */
<> 157:ff67d9f36b67 98 };
<> 157:ff67d9f36b67 99 union { /* 0x0800-0x0FFC SPI Slave FIFO RX Read Space */
<> 157:ff67d9f36b67 100 __IO uint8_t rx_8[2048]; /**< 8-bit access to Receive FIFO */
<> 157:ff67d9f36b67 101 __IO uint16_t rx_16[1024]; /**< 16-bit access to Receive FIFO */
<> 157:ff67d9f36b67 102 __IO uint32_t rx_32[512]; /**< 32-bit access to Receive FIFO */
<> 157:ff67d9f36b67 103 };
<> 157:ff67d9f36b67 104 } mxc_spis_fifo_regs_t;
<> 157:ff67d9f36b67 105 /**@} end of group spis_registers */
<> 157:ff67d9f36b67 106
<> 157:ff67d9f36b67 107 /*
<> 157:ff67d9f36b67 108 Register offsets for module SPIS.
<> 157:ff67d9f36b67 109 */
<> 157:ff67d9f36b67 110 /**
<> 157:ff67d9f36b67 111 * @ingroup spis_registers
<> 157:ff67d9f36b67 112 * @defgroup SPIS_Register_Offsets Register Offsets
<> 157:ff67d9f36b67 113 * @brief SPI Slave Register Offsets from the SPIS[n] Base Peripheral Address, where \c n \c = SPIS Instance Number.
<> 157:ff67d9f36b67 114 * @{
<> 157:ff67d9f36b67 115 */
<> 157:ff67d9f36b67 116 #define MXC_R_SPIS_OFFS_GEN_CTRL ((uint32_t)0x00000000UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0000</tt>*/
<> 157:ff67d9f36b67 117 #define MXC_R_SPIS_OFFS_FIFO_CTRL ((uint32_t)0x00000004UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0004</tt>*/
<> 157:ff67d9f36b67 118 #define MXC_R_SPIS_OFFS_FIFO_STAT ((uint32_t)0x00000008UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0008</tt>*/
<> 157:ff67d9f36b67 119 #define MXC_R_SPIS_OFFS_INTFL ((uint32_t)0x0000000CUL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x000C</tt>*/
<> 157:ff67d9f36b67 120 #define MXC_R_SPIS_OFFS_INTEN ((uint32_t)0x00000010UL) /**< /**< Offset from SPIS[n] Base Peripheral Address: <tt>\b 0x0010</tt>*/
<> 157:ff67d9f36b67 121 /**@} end of group SPIS_Register_Offsets*/
<> 157:ff67d9f36b67 122 /**
<> 157:ff67d9f36b67 123 * @ingroup spis_registers
<> 157:ff67d9f36b67 124 * @defgroup SPIS_FIFO_Offsets FIFO Offsets
<> 157:ff67d9f36b67 125 * @brief SPI Slave FIFO Offsets from the SPIS[n] Base FIFO Address, where \c n \c = SPIS Instance Number.
<> 157:ff67d9f36b67 126 * @{
<> 157:ff67d9f36b67 127 */
<> 157:ff67d9f36b67 128 #define MXC_R_SPIS_FIFO_OFFS_TX ((uint32_t)0x00000000UL) /**< Offset from SPIS[n] Base FIFO Address: <tt>\b 0x0000</tt> */
<> 157:ff67d9f36b67 129 #define MXC_R_SPIS_FIFO_OFFS_RX ((uint32_t)0x00000800UL) /**< Offset from SPIS[n] Base FIFO Address: <tt>\b 0x0800</tt> */
<> 157:ff67d9f36b67 130 /**@} end of group SPIS_FIFO_Offsets*/
<> 157:ff67d9f36b67 131
<> 157:ff67d9f36b67 132
<> 157:ff67d9f36b67 133 /*
<> 157:ff67d9f36b67 134 Field positions and masks for module SPIS.
<> 157:ff67d9f36b67 135 */
<> 157:ff67d9f36b67 136 /**
<> 157:ff67d9f36b67 137 * @ingroup spis_registers
<> 157:ff67d9f36b67 138 * @defgroup SPIS_GEN_CTRL_Register SPIS_GEN_CTRL
<> 157:ff67d9f36b67 139 * @brief Field Positions and Bit Masks for the SPIS_GEN_CTRL register
<> 157:ff67d9f36b67 140 * @{
<> 157:ff67d9f36b67 141 */
<> 157:ff67d9f36b67 142 #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS 0 /**< SPI_SLAVE_EN Position */
<> 157:ff67d9f36b67 143 #define MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN_POS)) /**< SPI_SLAVE_EN Mask */
<> 157:ff67d9f36b67 144 #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS 1 /**< TX_FIFO_EN Position */
<> 157:ff67d9f36b67 145 #define MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */
<> 157:ff67d9f36b67 146 #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS 2 /**< RX_FIFO_EN Position */
<> 157:ff67d9f36b67 147 #define MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */
<> 157:ff67d9f36b67 148 #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS 4 /**< DATA_WIDTH Position */
<> 157:ff67d9f36b67 149 #define MXC_F_SPIS_GEN_CTRL_DATA_WIDTH ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_DATA_WIDTH_POS)) /**< DATA_WIDTH Mask */
<> 157:ff67d9f36b67 150 #define MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS 16 /**< SPI_MODE Position */
<> 157:ff67d9f36b67 151 #define MXC_F_SPIS_GEN_CTRL_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIS_GEN_CTRL_SPI_MODE_POS)) /**< SPI_MODE Mask */
<> 157:ff67d9f36b67 152 #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS 20 /**< TX_CLK_INVERT Position */
<> 157:ff67d9f36b67 153 #define MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT ((uint32_t)(0x00000001UL << MXC_F_SPIS_GEN_CTRL_TX_CLK_INVERT_POS)) /**< TX_CLK_INVERT Mask */
<> 157:ff67d9f36b67 154 /**@} end of group SPIS_GEN_CTRL*/
<> 157:ff67d9f36b67 155 /**
<> 157:ff67d9f36b67 156 * @ingroup spis_registers
<> 157:ff67d9f36b67 157 * @defgroup SPIS_FIFO_CTRL_Register SPIS_FIFO_CTRL
<> 157:ff67d9f36b67 158 * @brief Field Positions and Bit Masks for the SPIS_FIFO_CTRL register
<> 157:ff67d9f36b67 159 * @{
<> 157:ff67d9f36b67 160 */
<> 157:ff67d9f36b67 161 #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< TX_FIFO_AE_LVL Position */
<> 157:ff67d9f36b67 162 #define MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< TX_FIFO_AE_LVL Mask */
<> 157:ff67d9f36b67 163 #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS 8 /**< RX_FIFO_AF_LVL Position */
<> 157:ff67d9f36b67 164 #define MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIS_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< RX_FIFO_AF_LVL Mask */
<> 157:ff67d9f36b67 165 /**@} end of group SPIS_FIFO_CTRL_Register*/
<> 157:ff67d9f36b67 166 /**
<> 157:ff67d9f36b67 167 * @ingroup spis_registers
<> 157:ff67d9f36b67 168 * @defgroup SPIS_FIFO_STAT_Register SPIS_FIFO_STAT
<> 157:ff67d9f36b67 169 * @brief Field Positions and Bit Masks for the SPIS_FIFO_STAT register
<> 157:ff67d9f36b67 170 * @{
<> 157:ff67d9f36b67 171 */
<> 157:ff67d9f36b67 172 #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS 0 /**< TX_FIFO_USED Position */
<> 157:ff67d9f36b67 173 #define MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS)) /**< TX_FIFO_USED Mask */
<> 157:ff67d9f36b67 174 #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS 8 /**< RX_FIFO_USED Position */
<> 157:ff67d9f36b67 175 #define MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS)) /**< RX_FIFO_USED Mask */
<> 157:ff67d9f36b67 176 /**@} end of group SPIS_FIFO_STAT_Register*/
<> 157:ff67d9f36b67 177 /**
<> 157:ff67d9f36b67 178 * @ingroup spis_registers
<> 157:ff67d9f36b67 179 * @defgroup SPIS_INTFL_Register SPIS_INTFL
<> 157:ff67d9f36b67 180 * @brief Field Positions and Bit Masks for the SPIS_INTFL register
<> 157:ff67d9f36b67 181 * @{
<> 157:ff67d9f36b67 182 */
<> 157:ff67d9f36b67 183 #define MXC_F_SPIS_INTFL_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */
<> 157:ff67d9f36b67 184 #define MXC_F_SPIS_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
<> 157:ff67d9f36b67 185 #define MXC_F_SPIS_INTFL_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */
<> 157:ff67d9f36b67 186 #define MXC_F_SPIS_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
<> 157:ff67d9f36b67 187 #define MXC_F_SPIS_INTFL_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */
<> 157:ff67d9f36b67 188 #define MXC_F_SPIS_INTFL_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */
<> 157:ff67d9f36b67 189 #define MXC_F_SPIS_INTFL_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */
<> 157:ff67d9f36b67 190 #define MXC_F_SPIS_INTFL_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */
<> 157:ff67d9f36b67 191 #define MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */
<> 157:ff67d9f36b67 192 #define MXC_F_SPIS_INTFL_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */
<> 157:ff67d9f36b67 193 #define MXC_F_SPIS_INTFL_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */
<> 157:ff67d9f36b67 194 #define MXC_F_SPIS_INTFL_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */
<> 157:ff67d9f36b67 195 #define MXC_F_SPIS_INTFL_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */
<> 157:ff67d9f36b67 196 #define MXC_F_SPIS_INTFL_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTFL_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */
<> 157:ff67d9f36b67 197 /**@} end of group SPIS_INTFL_Register*/
<> 157:ff67d9f36b67 198 /**
<> 157:ff67d9f36b67 199 * @ingroup spis_registers
<> 157:ff67d9f36b67 200 * @defgroup SPIS_INTEN_Register SPIS_INTEN
<> 157:ff67d9f36b67 201 * @brief Field Positions and Bit Masks for the SPIS_INTEN register
<> 157:ff67d9f36b67 202 * @{
<> 157:ff67d9f36b67 203 */
<> 157:ff67d9f36b67 204 #define MXC_F_SPIS_INTEN_TX_FIFO_AE_POS 0 /**< TX_FIFO_AE Position */
<> 157:ff67d9f36b67 205 #define MXC_F_SPIS_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_FIFO_AE_POS)) /**< TX_FIFO_AE Mask */
<> 157:ff67d9f36b67 206 #define MXC_F_SPIS_INTEN_RX_FIFO_AF_POS 1 /**< RX_FIFO_AF Position */
<> 157:ff67d9f36b67 207 #define MXC_F_SPIS_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_FIFO_AF_POS)) /**< RX_FIFO_AF Mask */
<> 157:ff67d9f36b67 208 #define MXC_F_SPIS_INTEN_TX_NO_DATA_POS 2 /**< TX_NO_DATA Position */
<> 157:ff67d9f36b67 209 #define MXC_F_SPIS_INTEN_TX_NO_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_NO_DATA_POS)) /**< TX_NO_DATA Mask */
<> 157:ff67d9f36b67 210 #define MXC_F_SPIS_INTEN_RX_LOST_DATA_POS 3 /**< RX_LOST_DATA Position */
<> 157:ff67d9f36b67 211 #define MXC_F_SPIS_INTEN_RX_LOST_DATA ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_RX_LOST_DATA_POS)) /**< RX_LOST_DATA Mask */
<> 157:ff67d9f36b67 212 #define MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS 4 /**< TX_UNDERFLOW Position */
<> 157:ff67d9f36b67 213 #define MXC_F_SPIS_INTEN_TX_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_TX_UNDERFLOW_POS)) /**< TX_UNDERFLOW Mask */
<> 157:ff67d9f36b67 214 #define MXC_F_SPIS_INTEN_SS_ASSERTED_POS 5 /**< SS_ASSERTED Position */
<> 157:ff67d9f36b67 215 #define MXC_F_SPIS_INTEN_SS_ASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_ASSERTED_POS)) /**< SS_ASSERTED Mask */
<> 157:ff67d9f36b67 216 #define MXC_F_SPIS_INTEN_SS_DEASSERTED_POS 6 /**< SS_DEASSERTED Position */
<> 157:ff67d9f36b67 217 #define MXC_F_SPIS_INTEN_SS_DEASSERTED ((uint32_t)(0x00000001UL << MXC_F_SPIS_INTEN_SS_DEASSERTED_POS)) /**< SS_DEASSERTED Mask */
<> 157:ff67d9f36b67 218 /**@} end of group SPIS_INTEN_Register*/
<> 157:ff67d9f36b67 219 #ifdef __cplusplus
<> 157:ff67d9f36b67 220 }
<> 157:ff67d9f36b67 221 #endif
<> 157:ff67d9f36b67 222
<> 157:ff67d9f36b67 223 #endif /* _MXC_SPIS_REGS_H_ */
<> 157:ff67d9f36b67 224