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targets/TARGET_Maxim/TARGET_MAX32630/device/ioman_regs.h@157:ff67d9f36b67, 2017-02-02 (annotated)

Committer:
<>
Date:
Thu Feb 02 17:01:33 2017 +0000
Revision:
157:ff67d9f36b67
This updates the lib to the mbed lib v135

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief IOMAN hardware register definitions.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5 /* *****************************************************************************
<> 157:ff67d9f36b67 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 7 *
<> 157:ff67d9f36b67 8 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 9 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 10 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 12 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 13 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 14 *
<> 157:ff67d9f36b67 15 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 16 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 17 *
<> 157:ff67d9f36b67 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 24 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 29 *
<> 157:ff67d9f36b67 30 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 31 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 32 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 34 * ownership rights.
<> 157:ff67d9f36b67 35 *
<> 157:ff67d9f36b67 36 * $Date: 2016-10-31 17:07:02 -0500 (Mon, 31 Oct 2016) $
<> 157:ff67d9f36b67 37 * $Revision: 24857 $
<> 157:ff67d9f36b67 38 *
<> 157:ff67d9f36b67 39 **************************************************************************** */
<> 157:ff67d9f36b67 40
<> 157:ff67d9f36b67 41 /* Define to prevent redundant inclusion. */
<> 157:ff67d9f36b67 42 #ifndef _MXC_IOMAN_REGS_H_
<> 157:ff67d9f36b67 43 #define _MXC_IOMAN_REGS_H_
<> 157:ff67d9f36b67 44
<> 157:ff67d9f36b67 45 /* **** Includes **** */
<> 157:ff67d9f36b67 46 #include <stdint.h>
<> 157:ff67d9f36b67 47
<> 157:ff67d9f36b67 48 #ifdef __cplusplus
<> 157:ff67d9f36b67 49 extern "C" {
<> 157:ff67d9f36b67 50 #endif
<> 157:ff67d9f36b67 51
<> 157:ff67d9f36b67 52 /*
<> 157:ff67d9f36b67 53 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 54 */
<> 157:ff67d9f36b67 55 ///@cond
<> 157:ff67d9f36b67 56 #ifndef __IO
<> 157:ff67d9f36b67 57 #define __IO volatile
<> 157:ff67d9f36b67 58 #endif
<> 157:ff67d9f36b67 59 #ifndef __I
<> 157:ff67d9f36b67 60 #define __I volatile const
<> 157:ff67d9f36b67 61 #endif
<> 157:ff67d9f36b67 62 #ifndef __O
<> 157:ff67d9f36b67 63 #define __O volatile
<> 157:ff67d9f36b67 64 #endif
<> 157:ff67d9f36b67 65 #ifndef __RO
<> 157:ff67d9f36b67 66 #define __RO volatile const
<> 157:ff67d9f36b67 67 #endif
<> 157:ff67d9f36b67 68 ///@endcond
<> 157:ff67d9f36b67 69
<> 157:ff67d9f36b67 70 /* **** Definitions **** */
<> 157:ff67d9f36b67 71 /**
<> 157:ff67d9f36b67 72 * Structure type for wakeup detection @b request for port 4, port 5, port 6 and port 7.
<> 157:ff67d9f36b67 73 */
<> 157:ff67d9f36b67 74 typedef struct {
<> 157:ff67d9f36b67 75 uint32_t wud_req_p4 : 8; /**< Port 4 wake-up detection @b request bit field. */
<> 157:ff67d9f36b67 76 uint32_t wud_req_p5 : 8; /**< Port 5 wake-up detection @b request bit field. */
<> 157:ff67d9f36b67 77 uint32_t wud_req_p6 : 8; /**< Port 6 wake-up detection @b request bit field. */
<> 157:ff67d9f36b67 78 uint32_t wud_req_p7 : 8; /**< Port 7 wake-up detection @b request bit field. */
<> 157:ff67d9f36b67 79 } mxc_ioman_wud_req1_t;
<> 157:ff67d9f36b67 80 /**
<> 157:ff67d9f36b67 81 * Structure type for wakeup detection @b acknowledgement for port 0, port 1, port 2 and port 3.
<> 157:ff67d9f36b67 82 */
<> 157:ff67d9f36b67 83 typedef struct {
<> 157:ff67d9f36b67 84 uint32_t wud_ack_p0 : 8; /**< Port 0 wake-up detection @b acknowledgement bit field. */
<> 157:ff67d9f36b67 85 uint32_t wud_ack_p1 : 8; /**< Port 1 wake-up detection @b acknowledgement bit field. */
<> 157:ff67d9f36b67 86 uint32_t wud_ack_p2 : 8; /**< Port 2 wake-up detection @b acknowledgement bit field. */
<> 157:ff67d9f36b67 87 uint32_t wud_ack_p3 : 8; /**< Port 3 wake-up detection @b acknowledgement bit field. */
<> 157:ff67d9f36b67 88 } mxc_ioman_wud_ack0_t;
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90 /**
<> 157:ff67d9f36b67 91 * @ingroup ioman
<> 157:ff67d9f36b67 92 * @defgroup ioman_req_ack_bit_fields IOMAN Bit Field Structures
<> 157:ff67d9f36b67 93 * @brief Bit Field Structes used to request and configure all I/O for all
<> 157:ff67d9f36b67 94 * port pins and peripherals with external I/O.
<> 157:ff67d9f36b67 95 * @{
<> 157:ff67d9f36b67 96 */
<> 157:ff67d9f36b67 97 typedef struct {
<> 157:ff67d9f36b67 98 uint32_t wud_req_p0 : 8; /**< Port 0 wake-up detection @b request bit field. */
<> 157:ff67d9f36b67 99 uint32_t wud_req_p1 : 8; /**< Port 1 wake-up detection @b request bit field. */
<> 157:ff67d9f36b67 100 uint32_t wud_req_p2 : 8; /**< Port 2 wake-up detection @b request bit field. */
<> 157:ff67d9f36b67 101 uint32_t wud_req_p3 : 8; /**< Port 3 wake-up detection @b request bit field. */
<> 157:ff67d9f36b67 102 } mxc_ioman_wud_req0_t;
<> 157:ff67d9f36b67 103 /**
<> 157:ff67d9f36b67 104 * Structure type for wakeup detection @b acknowledgement for port 4, port 5, port 6 and port 7.
<> 157:ff67d9f36b67 105 */
<> 157:ff67d9f36b67 106 typedef struct {
<> 157:ff67d9f36b67 107 uint32_t wud_ack_p4 : 8; /**< Port 4 wake-up detection @b acknowledgement bit field. */
<> 157:ff67d9f36b67 108 uint32_t wud_ack_p5 : 8; /**< Port 5 wake-up detection @b acknowledgement bit field. */
<> 157:ff67d9f36b67 109 uint32_t wud_ack_p6 : 8; /**< Port 6 wake-up detection @b acknowledgement bit field. */
<> 157:ff67d9f36b67 110 uint32_t wud_ack_p7 : 8; /**< Port 7 wake-up detection @b acknowledgement bit field. */
<> 157:ff67d9f36b67 111 } mxc_ioman_wud_ack1_t;
<> 157:ff67d9f36b67 112 /**
<> 157:ff67d9f36b67 113 * Structure type for analog input @b request for port 0, port 1, port 2 and port 3.
<> 157:ff67d9f36b67 114 */
<> 157:ff67d9f36b67 115 typedef struct {
<> 157:ff67d9f36b67 116 uint32_t ali_req_p0 : 8; /**< Port 0 analog input @b request bit field. */
<> 157:ff67d9f36b67 117 uint32_t ali_req_p1 : 8; /**< Port 1 analog input @b request bit field. */
<> 157:ff67d9f36b67 118 uint32_t ali_req_p2 : 8; /**< Port 2 analog input @b request bit field. */
<> 157:ff67d9f36b67 119 uint32_t ali_req_p3 : 8; /**< Port 3 analog input @b request bit field. */
<> 157:ff67d9f36b67 120 } mxc_ioman_ali_req0_t;
<> 157:ff67d9f36b67 121 /**
<> 157:ff67d9f36b67 122 * Structure type for analog input @b request for port 4, port 5, port 6 and port 7.
<> 157:ff67d9f36b67 123 */
<> 157:ff67d9f36b67 124 typedef struct {
<> 157:ff67d9f36b67 125 uint32_t ali_req_p4 : 8; /**< Port 4 analog input @b request bit field. */
<> 157:ff67d9f36b67 126 uint32_t ali_req_p5 : 8; /**< Port 5 analog input @b request bit field. */
<> 157:ff67d9f36b67 127 uint32_t ali_req_p6 : 8; /**< Port 6 analog input @b request bit field. */
<> 157:ff67d9f36b67 128 uint32_t ali_req_p7 : 8; /**< Port 7 analog input @b request bit field. */
<> 157:ff67d9f36b67 129 } mxc_ioman_ali_req1_t;
<> 157:ff67d9f36b67 130 /**
<> 157:ff67d9f36b67 131 * Structure type for analog input @b acknowledgement for port 0, port 1, port 2 and port 3.
<> 157:ff67d9f36b67 132 */
<> 157:ff67d9f36b67 133 typedef struct {
<> 157:ff67d9f36b67 134 uint32_t ali_ack_p0 : 8; /**< Port 0 analog input @b acknowledgement bit field. */
<> 157:ff67d9f36b67 135 uint32_t ali_ack_p1 : 8; /**< Port 1 analog input @b acknowledgement bit field. */
<> 157:ff67d9f36b67 136 uint32_t ali_ack_p2 : 8; /**< Port 2 analog input @b acknowledgement bit field. */
<> 157:ff67d9f36b67 137 uint32_t ali_ack_p3 : 8; /**< Port 3 analog input @b acknowledgement bit field. */
<> 157:ff67d9f36b67 138 } mxc_ioman_ali_ack0_t;
<> 157:ff67d9f36b67 139 /**
<> 157:ff67d9f36b67 140 * Structure type for analog input @b acknowledgement for port 4, port 5, port 6 and port 7.
<> 157:ff67d9f36b67 141 */
<> 157:ff67d9f36b67 142 typedef struct {
<> 157:ff67d9f36b67 143 uint32_t ali_ack_p4 : 8; /**< Port 4 analog input @b acknowledgement bit field. */
<> 157:ff67d9f36b67 144 uint32_t ali_ack_p5 : 8; /**< Port 5 analog input @b acknowledgement bit field. */
<> 157:ff67d9f36b67 145 uint32_t ali_ack_p6 : 8; /**< Port 6 analog input @b acknowledgement bit field. */
<> 157:ff67d9f36b67 146 uint32_t ali_ack_p7 : 8; /**< Port 7 analog input @b acknowledgement bit field. */
<> 157:ff67d9f36b67 147 } mxc_ioman_ali_ack1_t;
<> 157:ff67d9f36b67 148 /**
<> 157:ff67d9f36b67 149 * Structure type for SPI XIP configuration @b requests.
<> 157:ff67d9f36b67 150 */
<> 157:ff67d9f36b67 151 typedef struct {
<> 157:ff67d9f36b67 152 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 153 uint32_t core_io_req : 1; /**< Set to request the SPIX core external pins. */
<> 157:ff67d9f36b67 154 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 155 uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */
<> 157:ff67d9f36b67 156 uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */
<> 157:ff67d9f36b67 157 uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */
<> 157:ff67d9f36b67 158 uint32_t : 1; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 159 uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
<> 157:ff67d9f36b67 160 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 161 uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
<> 157:ff67d9f36b67 162 uint32_t : 15; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 163 } mxc_ioman_spix_req_t;
<> 157:ff67d9f36b67 164 /**
<> 157:ff67d9f36b67 165 * Structure type for SPI XIP configuration @b acknowledgements.
<> 157:ff67d9f36b67 166 */
<> 157:ff67d9f36b67 167 typedef struct {
<> 157:ff67d9f36b67 168 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 169 uint32_t core_io_ack : 1; /**< Is set if the request for the SPIX core external pins succeeded. */
<> 157:ff67d9f36b67 170 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 171 uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */
<> 157:ff67d9f36b67 172 uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */
<> 157:ff67d9f36b67 173 uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */
<> 157:ff67d9f36b67 174 uint32_t : 1; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 175 uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
<> 157:ff67d9f36b67 176 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 177 uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
<> 157:ff67d9f36b67 178 uint32_t : 15; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 179 } mxc_ioman_spix_ack_t;
<> 157:ff67d9f36b67 180 /**
<> 157:ff67d9f36b67 181 * Structure type for UART0 configuration @b requests.
<> 157:ff67d9f36b67 182 */
<> 157:ff67d9f36b67 183 typedef struct {
<> 157:ff67d9f36b67 184 uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */
<> 157:ff67d9f36b67 185 uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */
<> 157:ff67d9f36b67 186 uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */
<> 157:ff67d9f36b67 187 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 188 uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 189 uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 190 uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 191 uint32_t : 25; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 192 } mxc_ioman_uart0_req_t;
<> 157:ff67d9f36b67 193 /**
<> 157:ff67d9f36b67 194 * Structure type for UART0 configuration @b acknowledgements.
<> 157:ff67d9f36b67 195 */
<> 157:ff67d9f36b67 196 typedef struct {
<> 157:ff67d9f36b67 197 uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 198 uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 199 uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 200 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 201 uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 202 uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 203 uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 204 uint32_t : 25; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 205 } mxc_ioman_uart0_ack_t;
<> 157:ff67d9f36b67 206 /**
<> 157:ff67d9f36b67 207 * Structure type for UART1 configuration @b requests.
<> 157:ff67d9f36b67 208 */
<> 157:ff67d9f36b67 209 typedef struct {
<> 157:ff67d9f36b67 210 uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */
<> 157:ff67d9f36b67 211 uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */
<> 157:ff67d9f36b67 212 uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */
<> 157:ff67d9f36b67 213 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 214 uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 215 uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 216 uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 217 uint32_t : 25; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 218 } mxc_ioman_uart1_req_t;
<> 157:ff67d9f36b67 219 /**
<> 157:ff67d9f36b67 220 * Structure type for UART1 configuration @b acknowledgements.
<> 157:ff67d9f36b67 221 */
<> 157:ff67d9f36b67 222 typedef struct {
<> 157:ff67d9f36b67 223 uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 224 uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 225 uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 226 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 227 uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 228 uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 229 uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 230 uint32_t : 25; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 231 } mxc_ioman_uart1_ack_t;
<> 157:ff67d9f36b67 232 /**
<> 157:ff67d9f36b67 233 * Structure type for UART2 configuration @b requests.
<> 157:ff67d9f36b67 234 */
<> 157:ff67d9f36b67 235 typedef struct {
<> 157:ff67d9f36b67 236 uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */
<> 157:ff67d9f36b67 237 uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */
<> 157:ff67d9f36b67 238 uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */
<> 157:ff67d9f36b67 239 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 240 uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 241 uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 242 uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 243 uint32_t : 25; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 244 } mxc_ioman_uart2_req_t;
<> 157:ff67d9f36b67 245 /**
<> 157:ff67d9f36b67 246 * Structure type for UART2 configuration @b acknowledgements.
<> 157:ff67d9f36b67 247 */
<> 157:ff67d9f36b67 248 typedef struct {
<> 157:ff67d9f36b67 249 uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 250 uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 251 uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 252 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 253 uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 254 uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 255 uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 256 uint32_t : 25; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 257 } mxc_ioman_uart2_ack_t;
<> 157:ff67d9f36b67 258 /**
<> 157:ff67d9f36b67 259 * Structure type for UART3 configuration @b requests.
<> 157:ff67d9f36b67 260 */
<> 157:ff67d9f36b67 261 typedef struct {
<> 157:ff67d9f36b67 262 uint32_t io_map : 1; /**< Value for the desired pin mapping for the RX/TX pins. */
<> 157:ff67d9f36b67 263 uint32_t cts_map : 1; /**< Value for the desired pin mapping for the CTS pin. */
<> 157:ff67d9f36b67 264 uint32_t rts_map : 1; /**< Value for the desired pin mapping for the RTS pin. */
<> 157:ff67d9f36b67 265 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 266 uint32_t io_req : 1; /**< RX/TX pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 267 uint32_t cts_io_req : 1; /**< CTS pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 268 uint32_t rts_io_req : 1; /**< RTS pin mapping, set to @p 1 to request or @p 0 to release. */
<> 157:ff67d9f36b67 269 uint32_t : 25; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 270 } mxc_ioman_uart3_req_t;
<> 157:ff67d9f36b67 271 /**
<> 157:ff67d9f36b67 272 * Structure type for UART3 configuration @b acknowledgements.
<> 157:ff67d9f36b67 273 */
<> 157:ff67d9f36b67 274 typedef struct {
<> 157:ff67d9f36b67 275 uint32_t io_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 276 uint32_t cts_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 277 uint32_t rts_map : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 278 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 279 uint32_t io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 280 uint32_t cts_io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 281 uint32_t rts_io_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 282 uint32_t : 25; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 283 } mxc_ioman_uart3_ack_t;
<> 157:ff67d9f36b67 284 /**
<> 157:ff67d9f36b67 285 * Structure type for I2C Master 0 configuration @b requests.
<> 157:ff67d9f36b67 286 */
<> 157:ff67d9f36b67 287 typedef struct {
<> 157:ff67d9f36b67 288 uint32_t : 4; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 289 uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM0 pins. */
<> 157:ff67d9f36b67 290 uint32_t : 27; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 291 } mxc_ioman_i2cm0_req_t;
<> 157:ff67d9f36b67 292 /**
<> 157:ff67d9f36b67 293 * Structure type for I2C Master 0 configuration @b acknowledgements.
<> 157:ff67d9f36b67 294 */
<> 157:ff67d9f36b67 295 typedef struct {
<> 157:ff67d9f36b67 296 uint32_t : 4; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 297 uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 298 uint32_t : 27; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 299 } mxc_ioman_i2cm0_ack_t;
<> 157:ff67d9f36b67 300 /**
<> 157:ff67d9f36b67 301 * Structure type for I2C Master 1 configuration @b requests.
<> 157:ff67d9f36b67 302 */
<> 157:ff67d9f36b67 303 typedef struct {
<> 157:ff67d9f36b67 304 uint32_t io_sel : 2; /**< Value for the desired pin mapping for the I2CM1 CLK and Data pins. */
<> 157:ff67d9f36b67 305 uint32_t : 2; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 306 uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM1 pins. */
<> 157:ff67d9f36b67 307 uint32_t : 27; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 308 } mxc_ioman_i2cm1_req_t;
<> 157:ff67d9f36b67 309 /**
<> 157:ff67d9f36b67 310 * Structure type for I2C Master 1 configuration @b acknowledgements.
<> 157:ff67d9f36b67 311 */
<> 157:ff67d9f36b67 312 typedef struct {
<> 157:ff67d9f36b67 313 uint32_t io_sel : 2; /**< Non-zero if mapping request successful. */
<> 157:ff67d9f36b67 314 uint32_t : 2; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 315 uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 316 uint32_t : 27; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 317 } mxc_ioman_i2cm1_ack_t;
<> 157:ff67d9f36b67 318 /**
<> 157:ff67d9f36b67 319 * Structure type for I2C Master 2 configuration @b requests.
<> 157:ff67d9f36b67 320 */
<> 157:ff67d9f36b67 321 typedef struct {
<> 157:ff67d9f36b67 322 uint32_t io_sel : 2; /**< Value for the desired pin mapping for the I2CM2 CLK and Data pins. */
<> 157:ff67d9f36b67 323 uint32_t : 2; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 324 uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CM2 pins. */
<> 157:ff67d9f36b67 325 uint32_t : 27; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 326 } mxc_ioman_i2cm2_req_t;
<> 157:ff67d9f36b67 327 /**
<> 157:ff67d9f36b67 328 * Structure type for I2C Master 2 configuration @b acknowledgements.
<> 157:ff67d9f36b67 329 */
<> 157:ff67d9f36b67 330 typedef struct {
<> 157:ff67d9f36b67 331 uint32_t io_sel : 2; /**< Non-zero if mapping request successful. */
<> 157:ff67d9f36b67 332 uint32_t : 2; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 333 uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 334 uint32_t : 27; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 335 } mxc_ioman_i2cm2_ack_t;
<> 157:ff67d9f36b67 336 /**
<> 157:ff67d9f36b67 337 * Structure type for I2C Slave 0 configuration @b requests.
<> 157:ff67d9f36b67 338 */
<> 157:ff67d9f36b67 339 typedef struct {
<> 157:ff67d9f36b67 340 uint32_t io_sel : 3; /**< Value for the desired pin mapping for the I2CS0 CLK and Data pins. */
<> 157:ff67d9f36b67 341 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 342 uint32_t mapping_req : 1; /**< Value for the desired pin mapping for the I2CS0 pins. */
<> 157:ff67d9f36b67 343 uint32_t : 27; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 344 } mxc_ioman_i2cs_req_t;
<> 157:ff67d9f36b67 345 /**
<> 157:ff67d9f36b67 346 * Structure type for I2C Slave 0 configuration @b acknowledgements.
<> 157:ff67d9f36b67 347 */
<> 157:ff67d9f36b67 348 typedef struct {
<> 157:ff67d9f36b67 349 uint32_t io_sel : 3; /**< Non-zero if mapping request successful. */
<> 157:ff67d9f36b67 350 uint32_t : 1; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 351 uint32_t mapping_ack : 1; /**< Is set to @p 1 if request successful. */
<> 157:ff67d9f36b67 352 uint32_t : 27; /**< Reserved: Do No Modify. */
<> 157:ff67d9f36b67 353 } mxc_ioman_i2cs_ack_t;
<> 157:ff67d9f36b67 354 /**
<> 157:ff67d9f36b67 355 * Structure type for SPI Master 0 configuration @b requests.
<> 157:ff67d9f36b67 356 */
<> 157:ff67d9f36b67 357 typedef struct {
<> 157:ff67d9f36b67 358 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 359 uint32_t core_io_req : 1; /**< Set to request the SPIM0 core external pins. */
<> 157:ff67d9f36b67 360 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 361 uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */
<> 157:ff67d9f36b67 362 uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */
<> 157:ff67d9f36b67 363 uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */
<> 157:ff67d9f36b67 364 uint32_t ss3_io_req : 1; /**< Set to request slave select 3 active out. */
<> 157:ff67d9f36b67 365 uint32_t ss4_io_req : 1; /**< Set to request slave select 4 active out. */
<> 157:ff67d9f36b67 366 uint32_t : 7; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 367 uint32_t quad_io_req : 1; /**< Set to 1 to request Quad I/O for SPIM0. */
<> 157:ff67d9f36b67 368 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 369 uint32_t fast_mode : 1; /**< Set to request fast mode operation for SPIM0. */
<> 157:ff67d9f36b67 370 uint32_t : 7; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 371 } mxc_ioman_spim0_req_t;
<> 157:ff67d9f36b67 372 /**
<> 157:ff67d9f36b67 373 * Structure type for SPI Master 0 configuration @b acknowledgements.
<> 157:ff67d9f36b67 374 */
<> 157:ff67d9f36b67 375 typedef struct {
<> 157:ff67d9f36b67 376 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 377 uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM0 core external pins succeeded. */
<> 157:ff67d9f36b67 378 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 379 uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */
<> 157:ff67d9f36b67 380 uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */
<> 157:ff67d9f36b67 381 uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */
<> 157:ff67d9f36b67 382 uint32_t ss3_io_ack : 1; /**< Is set if the request for the slave select 3 active out succeeded. */
<> 157:ff67d9f36b67 383 uint32_t ss4_io_ack : 1; /**< Is set if the request for the slave select 4 active out succeeded. */
<> 157:ff67d9f36b67 384 uint32_t : 7; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 385 uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
<> 157:ff67d9f36b67 386 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 387 uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
<> 157:ff67d9f36b67 388 uint32_t : 7; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 389 } mxc_ioman_spim0_ack_t;
<> 157:ff67d9f36b67 390 /**
<> 157:ff67d9f36b67 391 * Structure type for SPI Master 1 configuration @b requests.
<> 157:ff67d9f36b67 392 */
<> 157:ff67d9f36b67 393 typedef struct {
<> 157:ff67d9f36b67 394 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 395 uint32_t core_io_req : 1; /**< Set to request the SPIM1 core external pins. */
<> 157:ff67d9f36b67 396 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 397 uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */
<> 157:ff67d9f36b67 398 uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */
<> 157:ff67d9f36b67 399 uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */
<> 157:ff67d9f36b67 400 uint32_t : 9; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 401 uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
<> 157:ff67d9f36b67 402 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 403 uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
<> 157:ff67d9f36b67 404 uint32_t : 7; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 405 } mxc_ioman_spim1_req_t;
<> 157:ff67d9f36b67 406 /**
<> 157:ff67d9f36b67 407 * Structure type for SPI Master 1 configuration @b acknowledgements.
<> 157:ff67d9f36b67 408 */
<> 157:ff67d9f36b67 409 typedef struct {
<> 157:ff67d9f36b67 410 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 411 uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM1 core external pins succeeded. */
<> 157:ff67d9f36b67 412 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 413 uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */
<> 157:ff67d9f36b67 414 uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */
<> 157:ff67d9f36b67 415 uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */
<> 157:ff67d9f36b67 416 uint32_t : 9; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 417 uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
<> 157:ff67d9f36b67 418 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 419 uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
<> 157:ff67d9f36b67 420 uint32_t : 7; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 421 } mxc_ioman_spim1_ack_t;
<> 157:ff67d9f36b67 422 /**
<> 157:ff67d9f36b67 423 * Structure type for SPI Master 2 configuration @b requests.
<> 157:ff67d9f36b67 424 */
<> 157:ff67d9f36b67 425 typedef struct {
<> 157:ff67d9f36b67 426 uint32_t mapping_req : 2; /**< Set to the desired port pin mapping for the SPIM2. */
<> 157:ff67d9f36b67 427 uint32_t : 2; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 428 uint32_t core_io_req : 1; /**< Set to request the SPIM2 core external pins. */
<> 157:ff67d9f36b67 429 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 430 uint32_t ss0_io_req : 1; /**< Set to request slave select 0 active out. */
<> 157:ff67d9f36b67 431 uint32_t ss1_io_req : 1; /**< Set to request slave select 1 active out. */
<> 157:ff67d9f36b67 432 uint32_t ss2_io_req : 1; /**< Set to request slave select 2 active out. */
<> 157:ff67d9f36b67 433 uint32_t : 5; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 434 uint32_t sr0_io_req : 1; /**< Set to 1 to request slave ready 0 input. */
<> 157:ff67d9f36b67 435 uint32_t sr1_io_req : 1; /**< Set to 1 to request slave ready 1 input. */
<> 157:ff67d9f36b67 436 uint32_t : 2; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 437 uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
<> 157:ff67d9f36b67 438 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 439 uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
<> 157:ff67d9f36b67 440 uint32_t : 7; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 441 } mxc_ioman_spim2_req_t;
<> 157:ff67d9f36b67 442 /**
<> 157:ff67d9f36b67 443 * Structure type for SPI Master 2 configuration @b acknowledgements.
<> 157:ff67d9f36b67 444 */
<> 157:ff67d9f36b67 445 typedef struct {
<> 157:ff67d9f36b67 446 uint32_t mapping_ack : 2; /**< Non-zero if mapping request successful. */
<> 157:ff67d9f36b67 447 uint32_t : 2; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 448 uint32_t core_io_ack : 1; /**< Is set if the request for the SPIM2 core external pins succeeded. */
<> 157:ff67d9f36b67 449 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 450 uint32_t ss0_io_ack : 1; /**< Is set if the request for the slave select 0 active out succeeded. */
<> 157:ff67d9f36b67 451 uint32_t ss1_io_ack : 1; /**< Is set if the request for the slave select 1 active out succeeded. */
<> 157:ff67d9f36b67 452 uint32_t ss2_io_ack : 1; /**< Is set if the request for the slave select 2 active out succeeded. */
<> 157:ff67d9f36b67 453 uint32_t : 5; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 454 uint32_t sr0_io_req : 1; /**< Is set if the request for the slave ready 0 active input succeeded. */
<> 157:ff67d9f36b67 455 uint32_t sr1_io_req : 1; /**< Is set if the request for the slave ready 1 active input succeeded. */
<> 157:ff67d9f36b67 456 uint32_t : 2; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 457 uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
<> 157:ff67d9f36b67 458 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 459 uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
<> 157:ff67d9f36b67 460 uint32_t : 7; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 461 } mxc_ioman_spim2_ack_t;
<> 157:ff67d9f36b67 462 /**
<> 157:ff67d9f36b67 463 * Structure type for SPI Bridge configuration @b requests.
<> 157:ff67d9f36b67 464 */
<> 157:ff67d9f36b67 465 typedef struct {
<> 157:ff67d9f36b67 466 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 467 uint32_t core_io_req : 1; /**< Set to request the SPIB core external pins. */
<> 157:ff67d9f36b67 468 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 469 uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
<> 157:ff67d9f36b67 470 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 471 uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
<> 157:ff67d9f36b67 472 uint32_t : 19; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 473 } mxc_ioman_spib_req_t;
<> 157:ff67d9f36b67 474 /**
<> 157:ff67d9f36b67 475 * Structure type for SPI Bridge configuration @b acknowledgements.
<> 157:ff67d9f36b67 476 */
<> 157:ff67d9f36b67 477 typedef struct {
<> 157:ff67d9f36b67 478 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 479 uint32_t core_io_ack : 1; /**< Non-zero if mapping request successful. */
<> 157:ff67d9f36b67 480 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 481 uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
<> 157:ff67d9f36b67 482 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 483 uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
<> 157:ff67d9f36b67 484 uint32_t : 19; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 485 } mxc_ioman_spib_ack_t;
<> 157:ff67d9f36b67 486 /**
<> 157:ff67d9f36b67 487 * Structure type for 1-Wire Master (OWM) configuration @b requests.
<> 157:ff67d9f36b67 488 */
<> 157:ff67d9f36b67 489 typedef struct {
<> 157:ff67d9f36b67 490 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 491 uint32_t mapping_req : 1; /**< Set to the desired port pin mapping for the 1-Wire Master. */
<> 157:ff67d9f36b67 492 uint32_t epu_io_req : 1; /**< Set to 1 to request External Pull-up for the 1-Wire Master. */
<> 157:ff67d9f36b67 493 uint32_t : 26; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 494 } mxc_ioman_owm_req_t;
<> 157:ff67d9f36b67 495 /**
<> 157:ff67d9f36b67 496 * Structure type for 1-Wire Master configuration @b acknowledgements.
<> 157:ff67d9f36b67 497 */
<> 157:ff67d9f36b67 498 typedef struct {
<> 157:ff67d9f36b67 499 uint32_t : 4; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 500 uint32_t mapping_ack : 1; /**< Non-zero if mapping request successful. */
<> 157:ff67d9f36b67 501 uint32_t epu_io_ack : 1; /**< Non-zero if external pull-up request successful. */
<> 157:ff67d9f36b67 502 uint32_t : 26; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 503 } mxc_ioman_owm_ack_t;
<> 157:ff67d9f36b67 504 /**
<> 157:ff67d9f36b67 505 * Structure type for SPI Slave configuration @b requests.
<> 157:ff67d9f36b67 506 */
<> 157:ff67d9f36b67 507 typedef struct {
<> 157:ff67d9f36b67 508 uint32_t mapping_req : 2; /**< Set to desired port pin mapping for the SPIS peripheral. */
<> 157:ff67d9f36b67 509 uint32_t : 2; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 510 uint32_t core_io_req : 1; /**< Set to 1 to request the I/O be assigned to the SPIS. */
<> 157:ff67d9f36b67 511 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 512 uint32_t quad_io_req : 1; /**< Set to request quad I/O operation. */
<> 157:ff67d9f36b67 513 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 514 uint32_t fast_mode : 1; /**< Set to request fast mode operation. */
<> 157:ff67d9f36b67 515 uint32_t : 19; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 516 } mxc_ioman_spis_req_t;
<> 157:ff67d9f36b67 517 /**
<> 157:ff67d9f36b67 518 * Structure type for SPI Slave configuration @b acknowledgements.
<> 157:ff67d9f36b67 519 */
<> 157:ff67d9f36b67 520 typedef struct {
<> 157:ff67d9f36b67 521 uint32_t mapping_ack : 2; /**< Non-zero if mapping request successful. */
<> 157:ff67d9f36b67 522 uint32_t : 2; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 523 uint32_t core_io_ack : 1; /**< Non-zero if core io request successful. */
<> 157:ff67d9f36b67 524 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 525 uint32_t quad_io_ack : 1; /**< Is set if the request for the quad I/O operation succeeded. */
<> 157:ff67d9f36b67 526 uint32_t : 3; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 527 uint32_t fast_mode : 1; /**< Is set if the request for fast mode operation succeeded. */
<> 157:ff67d9f36b67 528 uint32_t : 19; /**< Reserved: Do Not Modify. */
<> 157:ff67d9f36b67 529 } mxc_ioman_spis_ack_t;
<> 157:ff67d9f36b67 530 /**
<> 157:ff67d9f36b67 531 * Structure type to configure the I/O pad mode options.
<> 157:ff67d9f36b67 532 */
<> 157:ff67d9f36b67 533 typedef struct {
<> 157:ff67d9f36b67 534 uint32_t slow_mode : 1; /**< Slow mode I/O operation */
<> 157:ff67d9f36b67 535 uint32_t alt_rcvr_mode : 1; /**< Alternative receive mode. */
<> 157:ff67d9f36b67 536 uint32_t : 30; /**< Reserved: Do not modify. */
<> 157:ff67d9f36b67 537 } mxc_ioman_pad_mode_t;
<> 157:ff67d9f36b67 538 /**
<> 157:ff67d9f36b67 539 * Structure type for Wake-Up Detect (WUD) configuration @b requests.
<> 157:ff67d9f36b67 540 */
<> 157:ff67d9f36b67 541 typedef struct {
<> 157:ff67d9f36b67 542 uint32_t wud_req_p8 : 2; /**< Request bits for Wakeup Detect Mode requests for ports P0/P1/P2/P3. */
<> 157:ff67d9f36b67 543 uint32_t : 30; /**< Reserved: Do not modify. */
<> 157:ff67d9f36b67 544 } mxc_ioman_wud_req2_t;
<> 157:ff67d9f36b67 545 /**
<> 157:ff67d9f36b67 546 * Structure type for Wake-Up Detect (WUD) configuration @b acknowledgements.
<> 157:ff67d9f36b67 547 */
<> 157:ff67d9f36b67 548 typedef struct {
<> 157:ff67d9f36b67 549 uint32_t wud_ack_p8 : 2; /**< Acknowledgement bits for Wakeup Detect Mode requests for ports P0/P1/P2/P3. */
<> 157:ff67d9f36b67 550 uint32_t : 30; /**< Reserved: Do not modify. */
<> 157:ff67d9f36b67 551 } mxc_ioman_wud_ack2_t;
<> 157:ff67d9f36b67 552 /**
<> 157:ff67d9f36b67 553 * Structure type for Analog Wake-Up Detect (WUD) configuration @b requests.
<> 157:ff67d9f36b67 554 */
<> 157:ff67d9f36b67 555 typedef struct {
<> 157:ff67d9f36b67 556 uint32_t ali_req_p8 : 2; /**< Request bits for Analog Wakeup Detect Mode requests for ports P4/P5/P6/P7. */
<> 157:ff67d9f36b67 557 uint32_t : 30; /**< Reserved: Do not modify. */
<> 157:ff67d9f36b67 558 } mxc_ioman_ali_req2_t;
<> 157:ff67d9f36b67 559 /**
<> 157:ff67d9f36b67 560 * Structure type for Wake-Up Detect (WUD) configuration @b acknowledgements.
<> 157:ff67d9f36b67 561 */
<> 157:ff67d9f36b67 562 typedef struct {
<> 157:ff67d9f36b67 563 uint32_t ali_ack_p8 : 2; /**< Acknowledgement bits for Analog Wakeup Detect Mode requests for ports P4/P5/P6/P7. */
<> 157:ff67d9f36b67 564 uint32_t : 30; /**< Reserved: Do not modify. */
<> 157:ff67d9f36b67 565 } mxc_ioman_ali_ack2_t;
<> 157:ff67d9f36b67 566 /**@} end of group ioman_req_ack_bit_fields */
<> 157:ff67d9f36b67 567 /**
<> 157:ff67d9f36b67 568 * @ingroup ioman
<> 157:ff67d9f36b67 569 * @defgroup ioman_registers IOMAN Registers
<> 157:ff67d9f36b67 570 * @{
<> 157:ff67d9f36b67 571 * Structure type for the IOMAN Register Interface.
<> 157:ff67d9f36b67 572 * The table below shows the IOMAN Regsiter Offsets from the Base IOMAN Peripheral Address #MXC_BASE_IOMAN.
<> 157:ff67d9f36b67 573 */
<> 157:ff67d9f36b67 574 typedef struct {
<> 157:ff67d9f36b67 575 __IO uint32_t wud_req0; /**< Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3) */
<> 157:ff67d9f36b67 576 __IO uint32_t wud_req1; /**< Wakeup Detect Mode Request Register 1 (P4/P5/P6/P7) */
<> 157:ff67d9f36b67 577 __IO uint32_t wud_ack0; /**< Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3) */
<> 157:ff67d9f36b67 578 __IO uint32_t wud_ack1; /**< Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6/P7) */
<> 157:ff67d9f36b67 579 __IO uint32_t ali_req0; /**< Analog Input Request Register 0 (P0/P1/P2/P3) */
<> 157:ff67d9f36b67 580 __IO uint32_t ali_req1; /**< Analog Input Request Register 1 (P4/P5/P6/P7) */
<> 157:ff67d9f36b67 581 __IO uint32_t ali_ack0; /**< Analog Input Acknowledge Register 0 (P0/P1/P2/P3) */
<> 157:ff67d9f36b67 582 __IO uint32_t ali_ack1; /**< Analog Input Acknowledge Register 1 (P4/P5/P6/P7) */
<> 157:ff67d9f36b67 583 __IO uint32_t ali_connect0; /**< Analog I/O Connection Control Register 0 */
<> 157:ff67d9f36b67 584 __IO uint32_t ali_connect1; /**< Analog I/O Connection Control Register 1 */
<> 157:ff67d9f36b67 585 __IO uint32_t spix_req; /**< SPIX I/O Mode Request */
<> 157:ff67d9f36b67 586 __IO uint32_t spix_ack; /**< SPIX I/O Mode Acknowledge */
<> 157:ff67d9f36b67 587 __IO uint32_t uart0_req; /**< UART0 I/O Mode Request */
<> 157:ff67d9f36b67 588 __IO uint32_t uart0_ack; /**< UART0 I/O Mode Acknowledge */
<> 157:ff67d9f36b67 589 __IO uint32_t uart1_req; /**< UART1 I/O Mode Request */
<> 157:ff67d9f36b67 590 __IO uint32_t uart1_ack; /**< UART1 I/O Mode Acknowledge */
<> 157:ff67d9f36b67 591 __IO uint32_t uart2_req; /**< UART2 I/O Mode Request */
<> 157:ff67d9f36b67 592 __IO uint32_t uart2_ack; /**< UART2 I/O Mode Acknowledge */
<> 157:ff67d9f36b67 593 __IO uint32_t uart3_req; /**< UART3 I/O Mode Request */
<> 157:ff67d9f36b67 594 __IO uint32_t uart3_ack; /**< UART3 I/O Mode Acknowledge */
<> 157:ff67d9f36b67 595 __IO uint32_t i2cm0_req; /**< I2C Master 0 I/O Request */
<> 157:ff67d9f36b67 596 __IO uint32_t i2cm0_ack; /**< I2C Master 0 I/O Acknowledge */
<> 157:ff67d9f36b67 597 __IO uint32_t i2cm1_req; /**< I2C Master 1 I/O Request */
<> 157:ff67d9f36b67 598 __IO uint32_t i2cm1_ack; /**< I2C Master 1 I/O Acknowledge */
<> 157:ff67d9f36b67 599 __IO uint32_t i2cm2_req; /**< I2C Master 2 I/O Request */
<> 157:ff67d9f36b67 600 __IO uint32_t i2cm2_ack; /**< I2C Master 2 I/O Acknowledge */
<> 157:ff67d9f36b67 601 __IO uint32_t i2cs_req; /**< I2C Slave I/O Request */
<> 157:ff67d9f36b67 602 __IO uint32_t i2cs_ack; /**< I2C Slave I/O Acknowledge */
<> 157:ff67d9f36b67 603 __IO uint32_t spim0_req; /**< SPI Master 0 I/O Mode Request */
<> 157:ff67d9f36b67 604 __IO uint32_t spim0_ack; /**< SPI Master 0 I/O Mode Acknowledge */
<> 157:ff67d9f36b67 605 __IO uint32_t spim1_req; /**< SPI Master 1 I/O Mode Request */
<> 157:ff67d9f36b67 606 __IO uint32_t spim1_ack; /**< SPI Master 1 I/O Mode Acknowledge */
<> 157:ff67d9f36b67 607 __IO uint32_t spim2_req; /**< SPI Master 2 I/O Mode Request */
<> 157:ff67d9f36b67 608 __IO uint32_t spim2_ack; /**< SPI Master 2 I/O Mode Acknowledge */
<> 157:ff67d9f36b67 609 __IO uint32_t spib_req; /**< SPI Bridge I/O Mode Request */
<> 157:ff67d9f36b67 610 __IO uint32_t spib_ack; /**< SPI Bridge I/O Mode Acknowledge */
<> 157:ff67d9f36b67 611 __IO uint32_t owm_req; /**< 1-Wire Master I/O Mode Request */
<> 157:ff67d9f36b67 612 __IO uint32_t owm_ack; /**< 1-Wire Master I/O Mode Acknowledge */
<> 157:ff67d9f36b67 613 __IO uint32_t spis_req; /**< SPI Slave I/O Mode Request */
<> 157:ff67d9f36b67 614 __IO uint32_t spis_ack; /**< SPI Slave I/O Mode Acknowledge */
<> 157:ff67d9f36b67 615 __RO uint32_t rsv0A0[24]; /**< RESERVED: DO NOT MODIFY */
<> 157:ff67d9f36b67 616 __IO uint32_t use_vddioh_0; /**< Enable VDDIOH Register 0 */
<> 157:ff67d9f36b67 617 __IO uint32_t use_vddioh_1; /**< Enable VDDIOH Register 1 */
<> 157:ff67d9f36b67 618 __IO uint32_t use_vddioh_2; /**< Enable VDDIOH Register 2 */
<> 157:ff67d9f36b67 619 __RO uint32_t rsv10C; /**< RESERVED: DO NOT MODIFY */
<> 157:ff67d9f36b67 620 __IO uint32_t pad_mode; /**< Pad Mode Control Register */
<> 157:ff67d9f36b67 621 __RO uint32_t rsv114[27]; /**< RESERVED: DO NOT MODIFY */
<> 157:ff67d9f36b67 622 __IO uint32_t wud_req2; /**< Wakeup Detect Mode Request Register 2 (Port 8) */
<> 157:ff67d9f36b67 623 __RO uint32_t rsv184; /**< RESERVED: DO NOT MODIFY */
<> 157:ff67d9f36b67 624 __IO uint32_t wud_ack2; /**< Wakeup Detect Mode Acknowledge Register 2 (Port 8) */
<> 157:ff67d9f36b67 625 __RO uint32_t rsv18C; /**< RESERVED: DO NOT MODIFY */
<> 157:ff67d9f36b67 626 __IO uint32_t ali_req2; /**< Analog Input Request Register 2 (Port 8) */
<> 157:ff67d9f36b67 627 __RO uint32_t rsv194; /**< RESERVED: DO NOT MODIFY */
<> 157:ff67d9f36b67 628 __IO uint32_t ali_ack2; /**< Analog Input Acknowledge Register 2 (Port 8) */
<> 157:ff67d9f36b67 629 __RO uint32_t rsv19C; /**< RESERVED: DO NOT MODIFY */
<> 157:ff67d9f36b67 630 __IO uint32_t ali_connect2; /**< Analog I/O Connection Control Register 2 */
<> 157:ff67d9f36b67 631 } mxc_ioman_regs_t;
<> 157:ff67d9f36b67 632 /**@}*/
<> 157:ff67d9f36b67 633
<> 157:ff67d9f36b67 634 /*
<> 157:ff67d9f36b67 635 Register offsets for module IOMAN.
<> 157:ff67d9f36b67 636 */
<> 157:ff67d9f36b67 637 /**
<> 157:ff67d9f36b67 638 * @ingroup ioman_registers
<> 157:ff67d9f36b67 639 * @defgroup ioman_reg_offs IOMAN Register Offsets
<> 157:ff67d9f36b67 640 * @{
<> 157:ff67d9f36b67 641 * @details The @ref IOMAN_REGS_OFFS_TABLE "IOMAN Register Offset Table"
<> 157:ff67d9f36b67 642 * shows the register offsets for the IOMAN registers from the base
<> 157:ff67d9f36b67 643 * IOMAN peripheral address, #MXC_BASE_IOMAN.
<> 157:ff67d9f36b67 644 * @anchor IOMAN_REGS_OFFS_TABLE
<> 157:ff67d9f36b67 645 * | Register | Offset |
<> 157:ff67d9f36b67 646 * | :----------- | ------:|
<> 157:ff67d9f36b67 647 * | WUD_REQ0 | 0x0000 |
<> 157:ff67d9f36b67 648 * | WUD_REQ1 | 0x0004 |
<> 157:ff67d9f36b67 649 * | WUD_ACK0 | 0x0008 |
<> 157:ff67d9f36b67 650 * | WUD_ACK1 | 0x000C |
<> 157:ff67d9f36b67 651 * | ALI_REQ0 | 0x0010 |
<> 157:ff67d9f36b67 652 * | ALI_REQ1 | 0x0014 |
<> 157:ff67d9f36b67 653 * | ALI_ACK0 | 0x0018 |
<> 157:ff67d9f36b67 654 * | ALI_ACK1 | 0x001C |
<> 157:ff67d9f36b67 655 * | ALI_CONNECT0 | 0x0020 |
<> 157:ff67d9f36b67 656 * | ALI_CONNECT1 | 0x0024 |
<> 157:ff67d9f36b67 657 * | SPIX_REQ | 0x0028 |
<> 157:ff67d9f36b67 658 * | SPIX_ACK | 0x002C |
<> 157:ff67d9f36b67 659 * | UART0_REQ | 0x0030 |
<> 157:ff67d9f36b67 660 * | UART0_ACK | 0x0034 |
<> 157:ff67d9f36b67 661 * | UART1_REQ | 0x0038 |
<> 157:ff67d9f36b67 662 * | UART1_ACK | 0x003C |
<> 157:ff67d9f36b67 663 * | UART2_REQ | 0x0040 |
<> 157:ff67d9f36b67 664 * | UART2_ACK | 0x0044 |
<> 157:ff67d9f36b67 665 * | UART3_REQ | 0x0048 |
<> 157:ff67d9f36b67 666 * | UART3_ACK | 0x004C |
<> 157:ff67d9f36b67 667 * | I2CM0_REQ | 0x0050 |
<> 157:ff67d9f36b67 668 * | I2CM0_ACK | 0x0054 |
<> 157:ff67d9f36b67 669 * | I2CM1_REQ | 0x0058 |
<> 157:ff67d9f36b67 670 * | I2CM1_ACK | 0x005C |
<> 157:ff67d9f36b67 671 * | I2CM2_REQ | 0x0060 |
<> 157:ff67d9f36b67 672 * | I2CM2_ACK | 0x0064 |
<> 157:ff67d9f36b67 673 * | I2CS_REQ | 0x0068 |
<> 157:ff67d9f36b67 674 * | I2CS_ACK | 0x006C |
<> 157:ff67d9f36b67 675 * | SPIM0_REQ | 0x0070 |
<> 157:ff67d9f36b67 676 * | SPIM0_ACK | 0x0074 |
<> 157:ff67d9f36b67 677 * | SPIM1_REQ | 0x0078 |
<> 157:ff67d9f36b67 678 * | SPIM1_ACK | 0x007C |
<> 157:ff67d9f36b67 679 * | SPIM2_REQ | 0x0080 |
<> 157:ff67d9f36b67 680 * | SPIM2_ACK | 0x0084 |
<> 157:ff67d9f36b67 681 * | SPIB_REQ | 0x0088 |
<> 157:ff67d9f36b67 682 * | SPIB_ACK | 0x008C |
<> 157:ff67d9f36b67 683 * | OWM_REQ | 0x0090 |
<> 157:ff67d9f36b67 684 * | OWM_ACK | 0x0094 |
<> 157:ff67d9f36b67 685 * | SPIS_REQ | 0x0098 |
<> 157:ff67d9f36b67 686 * | SPIS_ACK | 0x009C |
<> 157:ff67d9f36b67 687 * | USE_VDDIOH_0 | 0x0100 |
<> 157:ff67d9f36b67 688 * | USE_VDDIOH_1 | 0x0104 |
<> 157:ff67d9f36b67 689 * | USE_VDDIOH_2 | 0x0108 |
<> 157:ff67d9f36b67 690 * | PAD_MODE | 0x0110 |
<> 157:ff67d9f36b67 691 * | WUD_REQ2 | 0x0180 |
<> 157:ff67d9f36b67 692 * | WUD_ACK2 | 0x0188 |
<> 157:ff67d9f36b67 693 * | ALI_REQ2 | 0x0190 |
<> 157:ff67d9f36b67 694 * | ALI_ACK2 | 0x0198 |
<> 157:ff67d9f36b67 695 * | ALI_CONNECT2 | 0x01A0 |
<> 157:ff67d9f36b67 696 */
<> 157:ff67d9f36b67 697 #define MXC_R_IOMAN_OFFS_WUD_REQ0 ((uint32_t)0x00000000UL) /**< WUD_REQ0 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 698 #define MXC_R_IOMAN_OFFS_WUD_REQ1 ((uint32_t)0x00000004UL) /**< WUD_REQ1 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 699 #define MXC_R_IOMAN_OFFS_WUD_ACK0 ((uint32_t)0x00000008UL) /**< WUD_ACK0 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 700 #define MXC_R_IOMAN_OFFS_WUD_ACK1 ((uint32_t)0x0000000CUL) /**< WUD_ACK1 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 701 #define MXC_R_IOMAN_OFFS_ALI_REQ0 ((uint32_t)0x00000010UL) /**< ALI_REQ0 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 702 #define MXC_R_IOMAN_OFFS_ALI_REQ1 ((uint32_t)0x00000014UL) /**< ALI_REQ1 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 703 #define MXC_R_IOMAN_OFFS_ALI_ACK0 ((uint32_t)0x00000018UL) /**< ALI_ACK0 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 704 #define MXC_R_IOMAN_OFFS_ALI_ACK1 ((uint32_t)0x0000001CUL) /**< ALI_ACK1 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 705 #define MXC_R_IOMAN_OFFS_ALI_CONNECT0 ((uint32_t)0x00000020UL) /**< ALI_CONNECT0 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 706 #define MXC_R_IOMAN_OFFS_ALI_CONNECT1 ((uint32_t)0x00000024UL) /**< ALI_CONNECT1 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 707 #define MXC_R_IOMAN_OFFS_SPIX_REQ ((uint32_t)0x00000028UL) /**< SPIX_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 708 #define MXC_R_IOMAN_OFFS_SPIX_ACK ((uint32_t)0x0000002CUL) /**< SPIX_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 709 #define MXC_R_IOMAN_OFFS_UART0_REQ ((uint32_t)0x00000030UL) /**< UART0_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 710 #define MXC_R_IOMAN_OFFS_UART0_ACK ((uint32_t)0x00000034UL) /**< UART0_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 711 #define MXC_R_IOMAN_OFFS_UART1_REQ ((uint32_t)0x00000038UL) /**< UART1_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 712 #define MXC_R_IOMAN_OFFS_UART1_ACK ((uint32_t)0x0000003CUL) /**< UART1_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 713 #define MXC_R_IOMAN_OFFS_UART2_REQ ((uint32_t)0x00000040UL) /**< UART2_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 714 #define MXC_R_IOMAN_OFFS_UART2_ACK ((uint32_t)0x00000044UL) /**< UART2_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 715 #define MXC_R_IOMAN_OFFS_UART3_REQ ((uint32_t)0x00000048UL) /**< UART3_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 716 #define MXC_R_IOMAN_OFFS_UART3_ACK ((uint32_t)0x0000004CUL) /**< UART3_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 717 #define MXC_R_IOMAN_OFFS_I2CM0_REQ ((uint32_t)0x00000050UL) /**< I2CM0_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 718 #define MXC_R_IOMAN_OFFS_I2CM0_ACK ((uint32_t)0x00000054UL) /**< I2CM0_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 719 #define MXC_R_IOMAN_OFFS_I2CM1_REQ ((uint32_t)0x00000058UL) /**< I2CM1_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 720 #define MXC_R_IOMAN_OFFS_I2CM1_ACK ((uint32_t)0x0000005CUL) /**< I2CM1_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 721 #define MXC_R_IOMAN_OFFS_I2CM2_REQ ((uint32_t)0x00000060UL) /**< I2CM2_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 722 #define MXC_R_IOMAN_OFFS_I2CM2_ACK ((uint32_t)0x00000064UL) /**< I2CM2_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 723 #define MXC_R_IOMAN_OFFS_I2CS_REQ ((uint32_t)0x00000068UL) /**< I2CS_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 724 #define MXC_R_IOMAN_OFFS_I2CS_ACK ((uint32_t)0x0000006CUL) /**< I2CS_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 725 #define MXC_R_IOMAN_OFFS_SPIM0_REQ ((uint32_t)0x00000070UL) /**< SPIM0_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 726 #define MXC_R_IOMAN_OFFS_SPIM0_ACK ((uint32_t)0x00000074UL) /**< SPIM0_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 727 #define MXC_R_IOMAN_OFFS_SPIM1_REQ ((uint32_t)0x00000078UL) /**< SPIM1_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 728 #define MXC_R_IOMAN_OFFS_SPIM1_ACK ((uint32_t)0x0000007CUL) /**< SPIM1_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 729 #define MXC_R_IOMAN_OFFS_SPIM2_REQ ((uint32_t)0x00000080UL) /**< SPIM2_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 730 #define MXC_R_IOMAN_OFFS_SPIM2_ACK ((uint32_t)0x00000084UL) /**< SPIM2_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 731 #define MXC_R_IOMAN_OFFS_SPIB_REQ ((uint32_t)0x00000088UL) /**< SPIB_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 732 #define MXC_R_IOMAN_OFFS_SPIB_ACK ((uint32_t)0x0000008CUL) /**< SPIB_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 733 #define MXC_R_IOMAN_OFFS_OWM_REQ ((uint32_t)0x00000090UL) /**< OWM_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 734 #define MXC_R_IOMAN_OFFS_OWM_ACK ((uint32_t)0x00000094UL) /**< OWM_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 735 #define MXC_R_IOMAN_OFFS_SPIS_REQ ((uint32_t)0x00000098UL) /**< SPIS_REQ Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 736 #define MXC_R_IOMAN_OFFS_SPIS_ACK ((uint32_t)0x0000009CUL) /**< SPIS_ACK Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 737 #define MXC_R_IOMAN_OFFS_USE_VDDIOH_0 ((uint32_t)0x00000100UL) /**< USE_VDDIOH_0 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 738 #define MXC_R_IOMAN_OFFS_USE_VDDIOH_1 ((uint32_t)0x00000104UL) /**< USE_VDDIOH_1 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 739 #define MXC_R_IOMAN_OFFS_USE_VDDIOH_2 ((uint32_t)0x00000108UL) /**< USE_VDDIOH_2 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 740 #define MXC_R_IOMAN_OFFS_PAD_MODE ((uint32_t)0x00000110UL) /**< PAD_MODE Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 741 #define MXC_R_IOMAN_OFFS_WUD_REQ2 ((uint32_t)0x00000180UL) /**< WUD_REQ2 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 742 #define MXC_R_IOMAN_OFFS_WUD_ACK2 ((uint32_t)0x00000188UL) /**< WUD_ACK2 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 743 #define MXC_R_IOMAN_OFFS_ALI_REQ2 ((uint32_t)0x00000190UL) /**< ALI_REQ2 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 744 #define MXC_R_IOMAN_OFFS_ALI_ACK2 ((uint32_t)0x00000198UL) /**< ALI_ACK2 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 745 #define MXC_R_IOMAN_OFFS_ALI_CONNECT2 ((uint32_t)0x000001A0UL) /**< ALI_CONNECT2 Register Offset from base IOMAN Peripheral Address. */
<> 157:ff67d9f36b67 746 /**@}*/
<> 157:ff67d9f36b67 747
<> 157:ff67d9f36b67 748 /*
<> 157:ff67d9f36b67 749 Field positions and masks for module IOMAN.
<> 157:ff67d9f36b67 750 */
<> 157:ff67d9f36b67 751 /**
<> 157:ff67d9f36b67 752 * @ingroup ioman_registers
<> 157:ff67d9f36b67 753 * @defgroup Bit and Field Positions Masks for the IOMAN Registers.
<> 157:ff67d9f36b67 754 * @{
<> 157:ff67d9f36b67 755 */
<> 157:ff67d9f36b67 756 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS 0
<> 157:ff67d9f36b67 757 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P0_POS))
<> 157:ff67d9f36b67 758 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS 8
<> 157:ff67d9f36b67 759 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P1_POS))
<> 157:ff67d9f36b67 760 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS 16
<> 157:ff67d9f36b67 761 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P2_POS))
<> 157:ff67d9f36b67 762 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS 24
<> 157:ff67d9f36b67 763 #define MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ0_WUD_REQ_P3_POS))
<> 157:ff67d9f36b67 764
<> 157:ff67d9f36b67 765 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS 0
<> 157:ff67d9f36b67 766 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P4_POS))
<> 157:ff67d9f36b67 767 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS 8
<> 157:ff67d9f36b67 768 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P5_POS))
<> 157:ff67d9f36b67 769 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS 16
<> 157:ff67d9f36b67 770 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P6_POS))
<> 157:ff67d9f36b67 771 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS 24
<> 157:ff67d9f36b67 772 #define MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_REQ1_WUD_REQ_P7_POS))
<> 157:ff67d9f36b67 773
<> 157:ff67d9f36b67 774 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS 0
<> 157:ff67d9f36b67 775 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P0_POS))
<> 157:ff67d9f36b67 776 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS 8
<> 157:ff67d9f36b67 777 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P1_POS))
<> 157:ff67d9f36b67 778 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS 16
<> 157:ff67d9f36b67 779 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P2_POS))
<> 157:ff67d9f36b67 780 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS 24
<> 157:ff67d9f36b67 781 #define MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK0_WUD_ACK_P3_POS))
<> 157:ff67d9f36b67 782
<> 157:ff67d9f36b67 783 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS 0
<> 157:ff67d9f36b67 784 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P4_POS))
<> 157:ff67d9f36b67 785 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS 8
<> 157:ff67d9f36b67 786 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P5_POS))
<> 157:ff67d9f36b67 787 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS 16
<> 157:ff67d9f36b67 788 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P6_POS))
<> 157:ff67d9f36b67 789 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS 24
<> 157:ff67d9f36b67 790 #define MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_WUD_ACK1_WUD_ACK_P7_POS))
<> 157:ff67d9f36b67 791
<> 157:ff67d9f36b67 792 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS 0
<> 157:ff67d9f36b67 793 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P0_POS))
<> 157:ff67d9f36b67 794 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS 8
<> 157:ff67d9f36b67 795 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P1_POS))
<> 157:ff67d9f36b67 796 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS 16
<> 157:ff67d9f36b67 797 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P2_POS))
<> 157:ff67d9f36b67 798 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS 24
<> 157:ff67d9f36b67 799 #define MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ0_ALI_REQ_P3_POS))
<> 157:ff67d9f36b67 800
<> 157:ff67d9f36b67 801 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS 0
<> 157:ff67d9f36b67 802 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P4_POS))
<> 157:ff67d9f36b67 803 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS 8
<> 157:ff67d9f36b67 804 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P5_POS))
<> 157:ff67d9f36b67 805 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS 16
<> 157:ff67d9f36b67 806 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P6_POS))
<> 157:ff67d9f36b67 807 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS 24
<> 157:ff67d9f36b67 808 #define MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_REQ1_ALI_REQ_P7_POS))
<> 157:ff67d9f36b67 809
<> 157:ff67d9f36b67 810 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS 0
<> 157:ff67d9f36b67 811 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P0_POS))
<> 157:ff67d9f36b67 812 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS 8
<> 157:ff67d9f36b67 813 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P1_POS))
<> 157:ff67d9f36b67 814 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS 16
<> 157:ff67d9f36b67 815 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P2_POS))
<> 157:ff67d9f36b67 816 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS 24
<> 157:ff67d9f36b67 817 #define MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK0_ALI_ACK_P3_POS))
<> 157:ff67d9f36b67 818
<> 157:ff67d9f36b67 819 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS 0
<> 157:ff67d9f36b67 820 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P4_POS))
<> 157:ff67d9f36b67 821 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS 8
<> 157:ff67d9f36b67 822 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P5_POS))
<> 157:ff67d9f36b67 823 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS 16
<> 157:ff67d9f36b67 824 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P6_POS))
<> 157:ff67d9f36b67 825 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS 24
<> 157:ff67d9f36b67 826 #define MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7 ((uint32_t)(0x000000FFUL << MXC_F_IOMAN_ALI_ACK1_ALI_ACK_P7_POS))
<> 157:ff67d9f36b67 827
<> 157:ff67d9f36b67 828 #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS 4
<> 157:ff67d9f36b67 829 #define MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_CORE_IO_REQ_POS))
<> 157:ff67d9f36b67 830 #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS 8
<> 157:ff67d9f36b67 831 #define MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS0_IO_REQ_POS))
<> 157:ff67d9f36b67 832 #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS 9
<> 157:ff67d9f36b67 833 #define MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS1_IO_REQ_POS))
<> 157:ff67d9f36b67 834 #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS 10
<> 157:ff67d9f36b67 835 #define MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_SS2_IO_REQ_POS))
<> 157:ff67d9f36b67 836 #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS 12
<> 157:ff67d9f36b67 837 #define MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_QUAD_IO_REQ_POS))
<> 157:ff67d9f36b67 838 #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS 16
<> 157:ff67d9f36b67 839 #define MXC_F_IOMAN_SPIX_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_REQ_FAST_MODE_POS))
<> 157:ff67d9f36b67 840
<> 157:ff67d9f36b67 841 #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS 4
<> 157:ff67d9f36b67 842 #define MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_CORE_IO_ACK_POS))
<> 157:ff67d9f36b67 843 #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS 8
<> 157:ff67d9f36b67 844 #define MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS0_IO_ACK_POS))
<> 157:ff67d9f36b67 845 #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS 9
<> 157:ff67d9f36b67 846 #define MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS1_IO_ACK_POS))
<> 157:ff67d9f36b67 847 #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS 10
<> 157:ff67d9f36b67 848 #define MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_SS2_IO_ACK_POS))
<> 157:ff67d9f36b67 849 #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS 12
<> 157:ff67d9f36b67 850 #define MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_QUAD_IO_ACK_POS))
<> 157:ff67d9f36b67 851 #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS 16
<> 157:ff67d9f36b67 852 #define MXC_F_IOMAN_SPIX_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIX_ACK_FAST_MODE_POS))
<> 157:ff67d9f36b67 853
<> 157:ff67d9f36b67 854 #define MXC_F_IOMAN_UART0_REQ_IO_MAP_POS 0
<> 157:ff67d9f36b67 855 #define MXC_F_IOMAN_UART0_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_MAP_POS))
<> 157:ff67d9f36b67 856 #define MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS 1
<> 157:ff67d9f36b67 857 #define MXC_F_IOMAN_UART0_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_MAP_POS))
<> 157:ff67d9f36b67 858 #define MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS 2
<> 157:ff67d9f36b67 859 #define MXC_F_IOMAN_UART0_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_MAP_POS))
<> 157:ff67d9f36b67 860 #define MXC_F_IOMAN_UART0_REQ_IO_REQ_POS 4
<> 157:ff67d9f36b67 861 #define MXC_F_IOMAN_UART0_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_IO_REQ_POS))
<> 157:ff67d9f36b67 862 #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS 5
<> 157:ff67d9f36b67 863 #define MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_CTS_IO_REQ_POS))
<> 157:ff67d9f36b67 864 #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS 6
<> 157:ff67d9f36b67 865 #define MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_REQ_RTS_IO_REQ_POS))
<> 157:ff67d9f36b67 866
<> 157:ff67d9f36b67 867 #define MXC_F_IOMAN_UART0_ACK_IO_MAP_POS 0
<> 157:ff67d9f36b67 868 #define MXC_F_IOMAN_UART0_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_MAP_POS))
<> 157:ff67d9f36b67 869 #define MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS 1
<> 157:ff67d9f36b67 870 #define MXC_F_IOMAN_UART0_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_MAP_POS))
<> 157:ff67d9f36b67 871 #define MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS 2
<> 157:ff67d9f36b67 872 #define MXC_F_IOMAN_UART0_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_MAP_POS))
<> 157:ff67d9f36b67 873 #define MXC_F_IOMAN_UART0_ACK_IO_ACK_POS 4
<> 157:ff67d9f36b67 874 #define MXC_F_IOMAN_UART0_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_IO_ACK_POS))
<> 157:ff67d9f36b67 875 #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS 5
<> 157:ff67d9f36b67 876 #define MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_CTS_IO_ACK_POS))
<> 157:ff67d9f36b67 877 #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS 6
<> 157:ff67d9f36b67 878 #define MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART0_ACK_RTS_IO_ACK_POS))
<> 157:ff67d9f36b67 879
<> 157:ff67d9f36b67 880 #define MXC_F_IOMAN_UART1_REQ_IO_MAP_POS 0
<> 157:ff67d9f36b67 881 #define MXC_F_IOMAN_UART1_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_MAP_POS))
<> 157:ff67d9f36b67 882 #define MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS 1
<> 157:ff67d9f36b67 883 #define MXC_F_IOMAN_UART1_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_MAP_POS))
<> 157:ff67d9f36b67 884 #define MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS 2
<> 157:ff67d9f36b67 885 #define MXC_F_IOMAN_UART1_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_MAP_POS))
<> 157:ff67d9f36b67 886 #define MXC_F_IOMAN_UART1_REQ_IO_REQ_POS 4
<> 157:ff67d9f36b67 887 #define MXC_F_IOMAN_UART1_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_IO_REQ_POS))
<> 157:ff67d9f36b67 888 #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS 5
<> 157:ff67d9f36b67 889 #define MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_CTS_IO_REQ_POS))
<> 157:ff67d9f36b67 890 #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS 6
<> 157:ff67d9f36b67 891 #define MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_REQ_RTS_IO_REQ_POS))
<> 157:ff67d9f36b67 892
<> 157:ff67d9f36b67 893 #define MXC_F_IOMAN_UART1_ACK_IO_MAP_POS 0
<> 157:ff67d9f36b67 894 #define MXC_F_IOMAN_UART1_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_MAP_POS))
<> 157:ff67d9f36b67 895 #define MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS 1
<> 157:ff67d9f36b67 896 #define MXC_F_IOMAN_UART1_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_MAP_POS))
<> 157:ff67d9f36b67 897 #define MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS 2
<> 157:ff67d9f36b67 898 #define MXC_F_IOMAN_UART1_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_MAP_POS))
<> 157:ff67d9f36b67 899 #define MXC_F_IOMAN_UART1_ACK_IO_ACK_POS 4
<> 157:ff67d9f36b67 900 #define MXC_F_IOMAN_UART1_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_IO_ACK_POS))
<> 157:ff67d9f36b67 901 #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS 5
<> 157:ff67d9f36b67 902 #define MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_CTS_IO_ACK_POS))
<> 157:ff67d9f36b67 903 #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS 6
<> 157:ff67d9f36b67 904 #define MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART1_ACK_RTS_IO_ACK_POS))
<> 157:ff67d9f36b67 905
<> 157:ff67d9f36b67 906 #define MXC_F_IOMAN_UART2_REQ_IO_MAP_POS 0
<> 157:ff67d9f36b67 907 #define MXC_F_IOMAN_UART2_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_MAP_POS))
<> 157:ff67d9f36b67 908 #define MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS 1
<> 157:ff67d9f36b67 909 #define MXC_F_IOMAN_UART2_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_MAP_POS))
<> 157:ff67d9f36b67 910 #define MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS 2
<> 157:ff67d9f36b67 911 #define MXC_F_IOMAN_UART2_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_MAP_POS))
<> 157:ff67d9f36b67 912 #define MXC_F_IOMAN_UART2_REQ_IO_REQ_POS 4
<> 157:ff67d9f36b67 913 #define MXC_F_IOMAN_UART2_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_IO_REQ_POS))
<> 157:ff67d9f36b67 914 #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS 5
<> 157:ff67d9f36b67 915 #define MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_CTS_IO_REQ_POS))
<> 157:ff67d9f36b67 916 #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS 6
<> 157:ff67d9f36b67 917 #define MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_REQ_RTS_IO_REQ_POS))
<> 157:ff67d9f36b67 918
<> 157:ff67d9f36b67 919 #define MXC_F_IOMAN_UART2_ACK_IO_MAP_POS 0
<> 157:ff67d9f36b67 920 #define MXC_F_IOMAN_UART2_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_MAP_POS))
<> 157:ff67d9f36b67 921 #define MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS 1
<> 157:ff67d9f36b67 922 #define MXC_F_IOMAN_UART2_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_MAP_POS))
<> 157:ff67d9f36b67 923 #define MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS 2
<> 157:ff67d9f36b67 924 #define MXC_F_IOMAN_UART2_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_MAP_POS))
<> 157:ff67d9f36b67 925 #define MXC_F_IOMAN_UART2_ACK_IO_ACK_POS 4
<> 157:ff67d9f36b67 926 #define MXC_F_IOMAN_UART2_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_IO_ACK_POS))
<> 157:ff67d9f36b67 927 #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS 5
<> 157:ff67d9f36b67 928 #define MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_CTS_IO_ACK_POS))
<> 157:ff67d9f36b67 929 #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS 6
<> 157:ff67d9f36b67 930 #define MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART2_ACK_RTS_IO_ACK_POS))
<> 157:ff67d9f36b67 931
<> 157:ff67d9f36b67 932 #define MXC_F_IOMAN_UART3_REQ_IO_MAP_POS 0
<> 157:ff67d9f36b67 933 #define MXC_F_IOMAN_UART3_REQ_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_MAP_POS))
<> 157:ff67d9f36b67 934 #define MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS 1
<> 157:ff67d9f36b67 935 #define MXC_F_IOMAN_UART3_REQ_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_MAP_POS))
<> 157:ff67d9f36b67 936 #define MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS 2
<> 157:ff67d9f36b67 937 #define MXC_F_IOMAN_UART3_REQ_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_MAP_POS))
<> 157:ff67d9f36b67 938 #define MXC_F_IOMAN_UART3_REQ_IO_REQ_POS 4
<> 157:ff67d9f36b67 939 #define MXC_F_IOMAN_UART3_REQ_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_IO_REQ_POS))
<> 157:ff67d9f36b67 940 #define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS 5
<> 157:ff67d9f36b67 941 #define MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_CTS_IO_REQ_POS))
<> 157:ff67d9f36b67 942 #define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS 6
<> 157:ff67d9f36b67 943 #define MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_REQ_RTS_IO_REQ_POS))
<> 157:ff67d9f36b67 944
<> 157:ff67d9f36b67 945 #define MXC_F_IOMAN_UART3_ACK_IO_MAP_POS 0
<> 157:ff67d9f36b67 946 #define MXC_F_IOMAN_UART3_ACK_IO_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_MAP_POS))
<> 157:ff67d9f36b67 947 #define MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS 1
<> 157:ff67d9f36b67 948 #define MXC_F_IOMAN_UART3_ACK_CTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_MAP_POS))
<> 157:ff67d9f36b67 949 #define MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS 2
<> 157:ff67d9f36b67 950 #define MXC_F_IOMAN_UART3_ACK_RTS_MAP ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_MAP_POS))
<> 157:ff67d9f36b67 951 #define MXC_F_IOMAN_UART3_ACK_IO_ACK_POS 4
<> 157:ff67d9f36b67 952 #define MXC_F_IOMAN_UART3_ACK_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_IO_ACK_POS))
<> 157:ff67d9f36b67 953 #define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS 5
<> 157:ff67d9f36b67 954 #define MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_CTS_IO_ACK_POS))
<> 157:ff67d9f36b67 955 #define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS 6
<> 157:ff67d9f36b67 956 #define MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_UART3_ACK_RTS_IO_ACK_POS))
<> 157:ff67d9f36b67 957
<> 157:ff67d9f36b67 958 #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS 4
<> 157:ff67d9f36b67 959 #define MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_REQ_MAPPING_REQ_POS))
<> 157:ff67d9f36b67 960
<> 157:ff67d9f36b67 961 #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS 4
<> 157:ff67d9f36b67 962 #define MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM0_ACK_MAPPING_ACK_POS))
<> 157:ff67d9f36b67 963
<> 157:ff67d9f36b67 964 #define MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS 0
<> 157:ff67d9f36b67 965 #define MXC_F_IOMAN_I2CM1_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_REQ_IO_SEL_POS))
<> 157:ff67d9f36b67 966 #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS 4
<> 157:ff67d9f36b67 967 #define MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_REQ_MAPPING_REQ_POS))
<> 157:ff67d9f36b67 968
<> 157:ff67d9f36b67 969 #define MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS 0
<> 157:ff67d9f36b67 970 #define MXC_F_IOMAN_I2CM1_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM1_ACK_IO_SEL_POS))
<> 157:ff67d9f36b67 971 #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS 4
<> 157:ff67d9f36b67 972 #define MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM1_ACK_MAPPING_ACK_POS))
<> 157:ff67d9f36b67 973
<> 157:ff67d9f36b67 974 #define MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS 0
<> 157:ff67d9f36b67 975 #define MXC_F_IOMAN_I2CM2_REQ_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_REQ_IO_SEL_POS))
<> 157:ff67d9f36b67 976 #define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS 4
<> 157:ff67d9f36b67 977 #define MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_REQ_MAPPING_REQ_POS))
<> 157:ff67d9f36b67 978
<> 157:ff67d9f36b67 979 #define MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS 0
<> 157:ff67d9f36b67 980 #define MXC_F_IOMAN_I2CM2_ACK_IO_SEL ((uint32_t)(0x00000003UL << MXC_F_IOMAN_I2CM2_ACK_IO_SEL_POS))
<> 157:ff67d9f36b67 981 #define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS 4
<> 157:ff67d9f36b67 982 #define MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CM2_ACK_MAPPING_ACK_POS))
<> 157:ff67d9f36b67 983
<> 157:ff67d9f36b67 984 #define MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS 0
<> 157:ff67d9f36b67 985 #define MXC_F_IOMAN_I2CS_REQ_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_REQ_IO_SEL_POS))
<> 157:ff67d9f36b67 986 #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS 4
<> 157:ff67d9f36b67 987 #define MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_REQ_MAPPING_REQ_POS))
<> 157:ff67d9f36b67 988
<> 157:ff67d9f36b67 989 #define MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS 0
<> 157:ff67d9f36b67 990 #define MXC_F_IOMAN_I2CS_ACK_IO_SEL ((uint32_t)(0x00000007UL << MXC_F_IOMAN_I2CS_ACK_IO_SEL_POS))
<> 157:ff67d9f36b67 991 #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS 4
<> 157:ff67d9f36b67 992 #define MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_I2CS_ACK_MAPPING_ACK_POS))
<> 157:ff67d9f36b67 993
<> 157:ff67d9f36b67 994 #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS 4
<> 157:ff67d9f36b67 995 #define MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_CORE_IO_REQ_POS))
<> 157:ff67d9f36b67 996 #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS 8
<> 157:ff67d9f36b67 997 #define MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS0_IO_REQ_POS))
<> 157:ff67d9f36b67 998 #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS 9
<> 157:ff67d9f36b67 999 #define MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS1_IO_REQ_POS))
<> 157:ff67d9f36b67 1000 #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS 10
<> 157:ff67d9f36b67 1001 #define MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS2_IO_REQ_POS))
<> 157:ff67d9f36b67 1002 #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS 11
<> 157:ff67d9f36b67 1003 #define MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS3_IO_REQ_POS))
<> 157:ff67d9f36b67 1004 #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS 12
<> 157:ff67d9f36b67 1005 #define MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_SS4_IO_REQ_POS))
<> 157:ff67d9f36b67 1006 #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS 20
<> 157:ff67d9f36b67 1007 #define MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_QUAD_IO_REQ_POS))
<> 157:ff67d9f36b67 1008 #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS 24
<> 157:ff67d9f36b67 1009 #define MXC_F_IOMAN_SPIM0_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_REQ_FAST_MODE_POS))
<> 157:ff67d9f36b67 1010
<> 157:ff67d9f36b67 1011 #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS 4
<> 157:ff67d9f36b67 1012 #define MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_CORE_IO_ACK_POS))
<> 157:ff67d9f36b67 1013 #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS 8
<> 157:ff67d9f36b67 1014 #define MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS0_IO_ACK_POS))
<> 157:ff67d9f36b67 1015 #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS 9
<> 157:ff67d9f36b67 1016 #define MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS1_IO_ACK_POS))
<> 157:ff67d9f36b67 1017 #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS 10
<> 157:ff67d9f36b67 1018 #define MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS2_IO_ACK_POS))
<> 157:ff67d9f36b67 1019 #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS 11
<> 157:ff67d9f36b67 1020 #define MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS3_IO_ACK_POS))
<> 157:ff67d9f36b67 1021 #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS 12
<> 157:ff67d9f36b67 1022 #define MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_SS4_IO_ACK_POS))
<> 157:ff67d9f36b67 1023 #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS 20
<> 157:ff67d9f36b67 1024 #define MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_QUAD_IO_ACK_POS))
<> 157:ff67d9f36b67 1025 #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS 24
<> 157:ff67d9f36b67 1026 #define MXC_F_IOMAN_SPIM0_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM0_ACK_FAST_MODE_POS))
<> 157:ff67d9f36b67 1027
<> 157:ff67d9f36b67 1028 #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS 4
<> 157:ff67d9f36b67 1029 #define MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_CORE_IO_REQ_POS))
<> 157:ff67d9f36b67 1030 #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS 8
<> 157:ff67d9f36b67 1031 #define MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS0_IO_REQ_POS))
<> 157:ff67d9f36b67 1032 #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS 9
<> 157:ff67d9f36b67 1033 #define MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS1_IO_REQ_POS))
<> 157:ff67d9f36b67 1034 #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS 10
<> 157:ff67d9f36b67 1035 #define MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_SS2_IO_REQ_POS))
<> 157:ff67d9f36b67 1036 #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS 20
<> 157:ff67d9f36b67 1037 #define MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_QUAD_IO_REQ_POS))
<> 157:ff67d9f36b67 1038 #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS 24
<> 157:ff67d9f36b67 1039 #define MXC_F_IOMAN_SPIM1_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_REQ_FAST_MODE_POS))
<> 157:ff67d9f36b67 1040
<> 157:ff67d9f36b67 1041 #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS 4
<> 157:ff67d9f36b67 1042 #define MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_CORE_IO_ACK_POS))
<> 157:ff67d9f36b67 1043 #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS 8
<> 157:ff67d9f36b67 1044 #define MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS0_IO_ACK_POS))
<> 157:ff67d9f36b67 1045 #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS 9
<> 157:ff67d9f36b67 1046 #define MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS1_IO_ACK_POS))
<> 157:ff67d9f36b67 1047 #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS 10
<> 157:ff67d9f36b67 1048 #define MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_SS2_IO_ACK_POS))
<> 157:ff67d9f36b67 1049 #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS 20
<> 157:ff67d9f36b67 1050 #define MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_QUAD_IO_ACK_POS))
<> 157:ff67d9f36b67 1051 #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS 24
<> 157:ff67d9f36b67 1052 #define MXC_F_IOMAN_SPIM1_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM1_ACK_FAST_MODE_POS))
<> 157:ff67d9f36b67 1053
<> 157:ff67d9f36b67 1054 #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS 0
<> 157:ff67d9f36b67 1055 #define MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_REQ_MAPPING_REQ_POS))
<> 157:ff67d9f36b67 1056 #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS 4
<> 157:ff67d9f36b67 1057 #define MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_CORE_IO_REQ_POS))
<> 157:ff67d9f36b67 1058 #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS 8
<> 157:ff67d9f36b67 1059 #define MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS0_IO_REQ_POS))
<> 157:ff67d9f36b67 1060 #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS 9
<> 157:ff67d9f36b67 1061 #define MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS1_IO_REQ_POS))
<> 157:ff67d9f36b67 1062 #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS 10
<> 157:ff67d9f36b67 1063 #define MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SS2_IO_REQ_POS))
<> 157:ff67d9f36b67 1064 #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS 16
<> 157:ff67d9f36b67 1065 #define MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR0_IO_REQ_POS))
<> 157:ff67d9f36b67 1066 #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS 17
<> 157:ff67d9f36b67 1067 #define MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_SR1_IO_REQ_POS))
<> 157:ff67d9f36b67 1068 #define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS 20
<> 157:ff67d9f36b67 1069 #define MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_QUAD_IO_REQ_POS))
<> 157:ff67d9f36b67 1070 #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS 24
<> 157:ff67d9f36b67 1071 #define MXC_F_IOMAN_SPIM2_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_REQ_FAST_MODE_POS))
<> 157:ff67d9f36b67 1072
<> 157:ff67d9f36b67 1073 #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS 0
<> 157:ff67d9f36b67 1074 #define MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIM2_ACK_MAPPING_ACK_POS))
<> 157:ff67d9f36b67 1075 #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS 4
<> 157:ff67d9f36b67 1076 #define MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_CORE_IO_ACK_POS))
<> 157:ff67d9f36b67 1077 #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS 8
<> 157:ff67d9f36b67 1078 #define MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS0_IO_ACK_POS))
<> 157:ff67d9f36b67 1079 #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS 9
<> 157:ff67d9f36b67 1080 #define MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS1_IO_ACK_POS))
<> 157:ff67d9f36b67 1081 #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS 10
<> 157:ff67d9f36b67 1082 #define MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SS2_IO_ACK_POS))
<> 157:ff67d9f36b67 1083 #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS 16
<> 157:ff67d9f36b67 1084 #define MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR0_IO_REQ_POS))
<> 157:ff67d9f36b67 1085 #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS 17
<> 157:ff67d9f36b67 1086 #define MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_SR1_IO_REQ_POS))
<> 157:ff67d9f36b67 1087 #define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS 20
<> 157:ff67d9f36b67 1088 #define MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_QUAD_IO_ACK_POS))
<> 157:ff67d9f36b67 1089 #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS 24
<> 157:ff67d9f36b67 1090 #define MXC_F_IOMAN_SPIM2_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIM2_ACK_FAST_MODE_POS))
<> 157:ff67d9f36b67 1091
<> 157:ff67d9f36b67 1092 #define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS 4
<> 157:ff67d9f36b67 1093 #define MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_CORE_IO_REQ_POS))
<> 157:ff67d9f36b67 1094 #define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS 8
<> 157:ff67d9f36b67 1095 #define MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_QUAD_IO_REQ_POS))
<> 157:ff67d9f36b67 1096 #define MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS 12
<> 157:ff67d9f36b67 1097 #define MXC_F_IOMAN_SPIB_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_REQ_FAST_MODE_POS))
<> 157:ff67d9f36b67 1098
<> 157:ff67d9f36b67 1099 #define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS 4
<> 157:ff67d9f36b67 1100 #define MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_CORE_IO_ACK_POS))
<> 157:ff67d9f36b67 1101 #define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS 8
<> 157:ff67d9f36b67 1102 #define MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_QUAD_IO_ACK_POS))
<> 157:ff67d9f36b67 1103 #define MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS 12
<> 157:ff67d9f36b67 1104 #define MXC_F_IOMAN_SPIB_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIB_ACK_FAST_MODE_POS))
<> 157:ff67d9f36b67 1105
<> 157:ff67d9f36b67 1106 #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS 4
<> 157:ff67d9f36b67 1107 #define MXC_F_IOMAN_OWM_REQ_MAPPING_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_MAPPING_REQ_POS))
<> 157:ff67d9f36b67 1108 #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS 5
<> 157:ff67d9f36b67 1109 #define MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_REQ_EPU_IO_REQ_POS))
<> 157:ff67d9f36b67 1110
<> 157:ff67d9f36b67 1111 #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS 4
<> 157:ff67d9f36b67 1112 #define MXC_F_IOMAN_OWM_ACK_MAPPING_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_MAPPING_ACK_POS))
<> 157:ff67d9f36b67 1113 #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS 5
<> 157:ff67d9f36b67 1114 #define MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_OWM_ACK_EPU_IO_ACK_POS))
<> 157:ff67d9f36b67 1115
<> 157:ff67d9f36b67 1116 #define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS 0
<> 157:ff67d9f36b67 1117 #define MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_REQ_MAPPING_REQ_POS))
<> 157:ff67d9f36b67 1118 #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS 4
<> 157:ff67d9f36b67 1119 #define MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_CORE_IO_REQ_POS))
<> 157:ff67d9f36b67 1120 #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS 8
<> 157:ff67d9f36b67 1121 #define MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_QUAD_IO_REQ_POS))
<> 157:ff67d9f36b67 1122 #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS 12
<> 157:ff67d9f36b67 1123 #define MXC_F_IOMAN_SPIS_REQ_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_REQ_FAST_MODE_POS))
<> 157:ff67d9f36b67 1124
<> 157:ff67d9f36b67 1125 #define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS 0
<> 157:ff67d9f36b67 1126 #define MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK ((uint32_t)(0x00000003UL << MXC_F_IOMAN_SPIS_ACK_MAPPING_ACK_POS))
<> 157:ff67d9f36b67 1127 #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS 4
<> 157:ff67d9f36b67 1128 #define MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_CORE_IO_ACK_POS))
<> 157:ff67d9f36b67 1129 #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS 8
<> 157:ff67d9f36b67 1130 #define MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_QUAD_IO_ACK_POS))
<> 157:ff67d9f36b67 1131 #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS 12
<> 157:ff67d9f36b67 1132 #define MXC_F_IOMAN_SPIS_ACK_FAST_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_SPIS_ACK_FAST_MODE_POS))
<> 157:ff67d9f36b67 1133
<> 157:ff67d9f36b67 1134 #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS 0
<> 157:ff67d9f36b67 1135 #define MXC_F_IOMAN_PAD_MODE_SLOW_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_SLOW_MODE_POS))
<> 157:ff67d9f36b67 1136 #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS 1
<> 157:ff67d9f36b67 1137 #define MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE ((uint32_t)(0x00000001UL << MXC_F_IOMAN_PAD_MODE_ALT_RCVR_MODE_POS))
<> 157:ff67d9f36b67 1138
<> 157:ff67d9f36b67 1139 #define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS 0
<> 157:ff67d9f36b67 1140 #define MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_REQ2_WUD_REQ_P8_POS))
<> 157:ff67d9f36b67 1141
<> 157:ff67d9f36b67 1142 #define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS 0
<> 157:ff67d9f36b67 1143 #define MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_WUD_ACK2_WUD_ACK_P8_POS))
<> 157:ff67d9f36b67 1144
<> 157:ff67d9f36b67 1145 #define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS 0
<> 157:ff67d9f36b67 1146 #define MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_REQ2_ALI_REQ_P8_POS))
<> 157:ff67d9f36b67 1147
<> 157:ff67d9f36b67 1148 #define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS 0
<> 157:ff67d9f36b67 1149 #define MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8 ((uint32_t)(0x00000003UL << MXC_F_IOMAN_ALI_ACK2_ALI_ACK_P8_POS))
<> 157:ff67d9f36b67 1150
<> 157:ff67d9f36b67 1151 /*
<> 157:ff67d9f36b67 1152 Generic field positions and masks
<> 157:ff67d9f36b67 1153 */
<> 157:ff67d9f36b67 1154 #define MXC_F_IOMAN_UART_REQ_IO_REQ MXC_F_IOMAN_UART0_REQ_IO_REQ
<> 157:ff67d9f36b67 1155 #define MXC_F_IOMAN_UART_ACK_IO_ACK MXC_F_IOMAN_UART0_ACK_IO_ACK
<> 157:ff67d9f36b67 1156 /**@}*/
<> 157:ff67d9f36b67 1157
<> 157:ff67d9f36b67 1158 #ifdef __cplusplus
<> 157:ff67d9f36b67 1159 }
<> 157:ff67d9f36b67 1160 #endif
<> 157:ff67d9f36b67 1161
<> 157:ff67d9f36b67 1162 #endif /* _MXC_IOMAN_REGS_H_ */
<> 157:ff67d9f36b67 1163