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targets/TARGET_ONSEMI/TARGET_NCS36510/device/NCS36510.h@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
149:156823d33999 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**************************************************************************/
<> 149:156823d33999 2 /**
<> 149:156823d33999 3 * @file NCS36510.h
<> 149:156823d33999 4 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
<> 149:156823d33999 5 * for CM3 Device Series
<> 149:156823d33999 6 * @version V1.05
<> 149:156823d33999 7 * @date 26. July 2011
<> 149:156823d33999 8 *
<> 149:156823d33999 9 * @note
<> 149:156823d33999 10 * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
<> 149:156823d33999 11 *
<> 149:156823d33999 12 * @par
<> 149:156823d33999 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
<> 149:156823d33999 14 * processor based microcontrollers. This file can be freely distributed
<> 149:156823d33999 15 * within development tools that are supporting such ARM based processors.
<> 149:156823d33999 16 *
<> 149:156823d33999 17 * @par
<> 149:156823d33999 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 149:156823d33999 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 149:156823d33999 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 149:156823d33999 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
<> 149:156823d33999 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 149:156823d33999 23 *
<> 149:156823d33999 24 ******************************************************************************/
<> 149:156823d33999 25
<> 149:156823d33999 26 #ifndef ARMCM3_H
<> 149:156823d33999 27 #define ARMCM3_H
<> 149:156823d33999 28
<> 149:156823d33999 29 /**
<> 149:156823d33999 30 * ==========================================================================
<> 149:156823d33999 31 * ---------- Interrupt Number Definition -----------------------------------
<> 149:156823d33999 32 * ==========================================================================
<> 149:156823d33999 33 */
<> 149:156823d33999 34 typedef enum IRQn {
<> 149:156823d33999 35 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
<> 149:156823d33999 36 NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M3 Non Maskable Interrupt */
<> 149:156823d33999 37 HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
<> 149:156823d33999 38 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
<> 149:156823d33999 39 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
<> 149:156823d33999 40 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
<> 149:156823d33999 41 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
<> 149:156823d33999 42 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
<> 149:156823d33999 43 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
<> 149:156823d33999 44 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
<> 149:156823d33999 45
<> 149:156823d33999 46 /****** ARMCM3 specific Interrupt Numbers ********************************************************/
<> 149:156823d33999 47 Tim0_IRQn = 0,
<> 149:156823d33999 48 Tim1_IRQn = 1,
<> 149:156823d33999 49 Tim2_IRQn = 2,
<> 149:156823d33999 50 Uart1_IRQn = 3,
<> 149:156823d33999 51 Spi_IRQn = 4,
<> 149:156823d33999 52 I2C_IRQn = 5,
<> 149:156823d33999 53 Gpio_IRQn = 6,
<> 149:156823d33999 54 Rtc_IRQn = 7,
<> 149:156823d33999 55 Flash_IRQn = 8,
<> 149:156823d33999 56 MacHw_IRQn = 9,
<> 149:156823d33999 57 Aes_IRQn = 10,
<> 149:156823d33999 58 Adc_IRQn = 11,
<> 149:156823d33999 59 ClockCal_IRQn = 12,
<> 149:156823d33999 60 Uart2_IRQn = 13,
<> 149:156823d33999 61 Uvi_IRQn = 14,
<> 149:156823d33999 62 Dma_IRQn = 15,
<> 149:156823d33999 63 DbgPwrUp_IRQn = 16,
<> 149:156823d33999 64 Spi2_IRQn = 17,
<> 149:156823d33999 65 I2C2_IRQn = 18,
<> 149:156823d33999 66 FVDDHComp_IRQn = 19
<> 149:156823d33999 67 } IRQn_Type;
<> 149:156823d33999 68
<> 149:156823d33999 69 /**
<> 149:156823d33999 70 * ==========================================================================
<> 149:156823d33999 71 * ----------- Processor and Core Peripheral Section ------------------------
<> 149:156823d33999 72 * ==========================================================================
<> 149:156823d33999 73 */
<> 149:156823d33999 74
<> 149:156823d33999 75 /** Configuration of the Cortex-M3 Processor and Core Peripherals */
<> 149:156823d33999 76 #define __CM3_REV 0x0201 /*!< Core Revision r2p1 */
<> 149:156823d33999 77 #define __MPU_PRESENT 1 /*!< MPU present or not */
<> 149:156823d33999 78 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
<> 149:156823d33999 79 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 149:156823d33999 80
<> 149:156823d33999 81 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_OFFSET 16
<> 149:156823d33999 82 //#define YOTTA_CFG_CMSIS_NVIC_USER_IRQ_NUMBER 20
<> 149:156823d33999 83 //#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
<> 149:156823d33999 84
<> 149:156823d33999 85 //#define YOTTA_CFG_CMSIS_NVIC_RAM_VECTOR_ADDRESS
<> 149:156823d33999 86 //#define YOTTA_CFG_CMSIS_NVIC_FLASH_VECTOR_ADDRESS 0x3000
<> 149:156823d33999 87
<> 149:156823d33999 88 #include <core_cm3.h> /* Cortex-M3 processor and core peripherals */
<> 149:156823d33999 89 #include "system_NCS36510.h" /* System Header */
<> 149:156823d33999 90
<> 149:156823d33999 91 #endif /* ARMCM3_H */