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targets/TARGET_Maxim/TARGET_MAX32630/device/pwrseq_regs.h@178:d650f5d4c87a, 2017-11-08 (annotated)

Committer:
AnnaBridge
Date:
Wed Nov 08 13:50:44 2017 +0000
Revision:
178:d650f5d4c87a
Parent:
157:ff67d9f36b67 
This updates the lib to the mbed lib v 155

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /*******************************************************************************
<> 157:ff67d9f36b67 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 3 *
<> 157:ff67d9f36b67 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 5 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 6 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 9 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 10 *
<> 157:ff67d9f36b67 11 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 12 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 13 *
<> 157:ff67d9f36b67 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 21 *
<> 157:ff67d9f36b67 22 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 24 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 28 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 30 * ownership rights.
<> 157:ff67d9f36b67 31 *
<> 157:ff67d9f36b67 32 * $Date: 2016-03-11 11:46:02 -0600 (Fri, 11 Mar 2016) $
<> 157:ff67d9f36b67 33 * $Revision: 21838 $
<> 157:ff67d9f36b67 34 *
<> 157:ff67d9f36b67 35 ******************************************************************************/
<> 157:ff67d9f36b67 36
<> 157:ff67d9f36b67 37 #ifndef _MXC_PWRSEQ_REGS_H_
<> 157:ff67d9f36b67 38 #define _MXC_PWRSEQ_REGS_H_
<> 157:ff67d9f36b67 39
<> 157:ff67d9f36b67 40 #ifdef __cplusplus
<> 157:ff67d9f36b67 41 extern "C" {
<> 157:ff67d9f36b67 42 #endif
<> 157:ff67d9f36b67 43
<> 157:ff67d9f36b67 44 #include <stdint.h>
<> 157:ff67d9f36b67 45
<> 157:ff67d9f36b67 46 /*
<> 157:ff67d9f36b67 47 If types are not defined elsewhere (CMSIS) define them here
<> 157:ff67d9f36b67 48 */
<> 157:ff67d9f36b67 49 #ifndef __IO
<> 157:ff67d9f36b67 50 #define __IO volatile
<> 157:ff67d9f36b67 51 #endif
<> 157:ff67d9f36b67 52 #ifndef __I
<> 157:ff67d9f36b67 53 #define __I volatile const
<> 157:ff67d9f36b67 54 #endif
<> 157:ff67d9f36b67 55 #ifndef __O
<> 157:ff67d9f36b67 56 #define __O volatile
<> 157:ff67d9f36b67 57 #endif
<> 157:ff67d9f36b67 58 #ifndef __RO
<> 157:ff67d9f36b67 59 #define __RO volatile const
<> 157:ff67d9f36b67 60 #endif
<> 157:ff67d9f36b67 61
<> 157:ff67d9f36b67 62
<> 157:ff67d9f36b67 63 /*
<> 157:ff67d9f36b67 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
<> 157:ff67d9f36b67 65 access to each register in module.
<> 157:ff67d9f36b67 66 */
<> 157:ff67d9f36b67 67
<> 157:ff67d9f36b67 68 /* Offset Register Description
<> 157:ff67d9f36b67 69 ============= ============================================================================ */
<> 157:ff67d9f36b67 70 typedef struct {
<> 157:ff67d9f36b67 71 __IO uint32_t reg0; /* 0x0000 Power Sequencer Control Register 0 */
<> 157:ff67d9f36b67 72 __IO uint32_t reg1; /* 0x0004 Power Sequencer Control Register 1 */
<> 157:ff67d9f36b67 73 __IO uint32_t reg2; /* 0x0008 Power Sequencer Control Register 2 */
<> 157:ff67d9f36b67 74 __IO uint32_t reg3; /* 0x000C Power Sequencer Control Register 3 */
<> 157:ff67d9f36b67 75 __IO uint32_t reg4; /* 0x0010 Power Sequencer Control Register 4 (Internal Test Only) */
<> 157:ff67d9f36b67 76 __IO uint32_t reg5; /* 0x0014 Power Sequencer Control Register 5 (Trim 0) */
<> 157:ff67d9f36b67 77 __IO uint32_t reg6; /* 0x0018 Power Sequencer Control Register 6 (Trim 1) */
<> 157:ff67d9f36b67 78 __IO uint32_t reg7; /* 0x001C Power Sequencer Control Register 7 (Trim 2) */
<> 157:ff67d9f36b67 79 __IO uint32_t flags; /* 0x0020 Power Sequencer Flags */
<> 157:ff67d9f36b67 80 __IO uint32_t msk_flags; /* 0x0024 Power Sequencer Flags Mask Register */
<> 157:ff67d9f36b67 81 __RO uint32_t rsv028; /* 0x0028 */
<> 157:ff67d9f36b67 82 __IO uint32_t wr_protect; /* 0x002C Critical Setting Write Protect Register */
<> 157:ff67d9f36b67 83 __IO uint32_t retn_ctrl0; /* 0x0030 Retention Control Register 0 */
<> 157:ff67d9f36b67 84 __IO uint32_t retn_ctrl1; /* 0x0034 Retention Control Register 1 */
<> 157:ff67d9f36b67 85 __IO uint32_t pwr_misc; /* 0x0038 Power Misc Controls */
<> 157:ff67d9f36b67 86 __IO uint32_t rtc_ctrl2; /* 0x003C RTC Misc Controls */
<> 157:ff67d9f36b67 87 } mxc_pwrseq_regs_t;
<> 157:ff67d9f36b67 88
<> 157:ff67d9f36b67 89
<> 157:ff67d9f36b67 90 /*
<> 157:ff67d9f36b67 91 Register offsets for module PWRSEQ.
<> 157:ff67d9f36b67 92 */
<> 157:ff67d9f36b67 93
<> 157:ff67d9f36b67 94 #define MXC_R_PWRSEQ_OFFS_REG0 ((uint32_t)0x00000000UL)
<> 157:ff67d9f36b67 95 #define MXC_R_PWRSEQ_OFFS_REG1 ((uint32_t)0x00000004UL)
<> 157:ff67d9f36b67 96 #define MXC_R_PWRSEQ_OFFS_REG2 ((uint32_t)0x00000008UL)
<> 157:ff67d9f36b67 97 #define MXC_R_PWRSEQ_OFFS_REG3 ((uint32_t)0x0000000CUL)
<> 157:ff67d9f36b67 98 #define MXC_R_PWRSEQ_OFFS_REG4 ((uint32_t)0x00000010UL)
<> 157:ff67d9f36b67 99 #define MXC_R_PWRSEQ_OFFS_REG5 ((uint32_t)0x00000014UL)
<> 157:ff67d9f36b67 100 #define MXC_R_PWRSEQ_OFFS_REG6 ((uint32_t)0x00000018UL)
<> 157:ff67d9f36b67 101 #define MXC_R_PWRSEQ_OFFS_REG7 ((uint32_t)0x0000001CUL)
<> 157:ff67d9f36b67 102 #define MXC_R_PWRSEQ_OFFS_FLAGS ((uint32_t)0x00000020UL)
<> 157:ff67d9f36b67 103 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS ((uint32_t)0x00000024UL)
<> 157:ff67d9f36b67 104 #define MXC_R_PWRSEQ_OFFS_WR_PROTECT ((uint32_t)0x0000002CUL)
<> 157:ff67d9f36b67 105 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL0 ((uint32_t)0x00000030UL)
<> 157:ff67d9f36b67 106 #define MXC_R_PWRSEQ_OFFS_RETN_CTRL1 ((uint32_t)0x00000034UL)
<> 157:ff67d9f36b67 107 #define MXC_R_PWRSEQ_OFFS_PWR_MISC ((uint32_t)0x00000038UL)
<> 157:ff67d9f36b67 108 #define MXC_R_PWRSEQ_OFFS_RTC_CTRL2 ((uint32_t)0x0000003CUL)
<> 157:ff67d9f36b67 109
<> 157:ff67d9f36b67 110
<> 157:ff67d9f36b67 111 /*
<> 157:ff67d9f36b67 112 Field positions and masks for module PWRSEQ.
<> 157:ff67d9f36b67 113 */
<> 157:ff67d9f36b67 114
<> 157:ff67d9f36b67 115 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS 0
<> 157:ff67d9f36b67 116 #define MXC_F_PWRSEQ_REG0_PWR_LP1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
<> 157:ff67d9f36b67 117 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS 1
<> 157:ff67d9f36b67 118 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
<> 157:ff67d9f36b67 119 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS 2
<> 157:ff67d9f36b67 120 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
<> 157:ff67d9f36b67 121 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS 3
<> 157:ff67d9f36b67 122 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_RUN_POS))
<> 157:ff67d9f36b67 123 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS 4
<> 157:ff67d9f36b67 124 #define MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FLASHEN_SLP_POS))
<> 157:ff67d9f36b67 125 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS 5
<> 157:ff67d9f36b67 126 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN_POS))
<> 157:ff67d9f36b67 127 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS 6
<> 157:ff67d9f36b67 128 #define MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP_POS))
<> 157:ff67d9f36b67 129 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS 7
<> 157:ff67d9f36b67 130 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
<> 157:ff67d9f36b67 131 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS 8
<> 157:ff67d9f36b67 132 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
<> 157:ff67d9f36b67 133 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS 9
<> 157:ff67d9f36b67 134 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
<> 157:ff67d9f36b67 135 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS 10
<> 157:ff67d9f36b67 136 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
<> 157:ff67d9f36b67 137 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS 11
<> 157:ff67d9f36b67 138 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
<> 157:ff67d9f36b67 139 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS 12
<> 157:ff67d9f36b67 140 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
<> 157:ff67d9f36b67 141 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS 13
<> 157:ff67d9f36b67 142 #define MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM12EN_RUN_POS))
<> 157:ff67d9f36b67 143 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS 15
<> 157:ff67d9f36b67 144 #define MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM18EN_RUN_POS))
<> 157:ff67d9f36b67 145 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS 17
<> 157:ff67d9f36b67 146 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
<> 157:ff67d9f36b67 147 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS 19
<> 157:ff67d9f36b67 148 #define MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM_VDDB_RUN_POS))
<> 157:ff67d9f36b67 149 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS 21
<> 157:ff67d9f36b67 150 #define MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMTVDD12EN_RUN_POS))
<> 157:ff67d9f36b67 151 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS 23
<> 157:ff67d9f36b67 152 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_RUN_POS))
<> 157:ff67d9f36b67 153 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS 24
<> 157:ff67d9f36b67 154 #define MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD12_SWEN_SLP_POS))
<> 157:ff67d9f36b67 155 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS 25
<> 157:ff67d9f36b67 156 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_RUN_POS))
<> 157:ff67d9f36b67 157 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS 26
<> 157:ff67d9f36b67 158 #define MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_VDD18_SWEN_SLP_POS))
<> 157:ff67d9f36b67 159 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS 27
<> 157:ff67d9f36b67 160 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_RUN_POS))
<> 157:ff67d9f36b67 161 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS 28
<> 157:ff67d9f36b67 162 #define MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_TVDD12_SWEN_SLP_POS))
<> 157:ff67d9f36b67 163 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS 29
<> 157:ff67d9f36b67 164 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_RUN_POS))
<> 157:ff67d9f36b67 165 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS 30
<> 157:ff67d9f36b67 166 #define MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RCEN_SLP_POS))
<> 157:ff67d9f36b67 167 #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS 31
<> 157:ff67d9f36b67 168 #define MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_OSC_SELECT_POS))
<> 157:ff67d9f36b67 169
<> 157:ff67d9f36b67 170 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS 0
<> 157:ff67d9f36b67 171 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH_POS))
<> 157:ff67d9f36b67 172 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS 1
<> 157:ff67d9f36b67 173 #define MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH_POS))
<> 157:ff67d9f36b67 174 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS 2
<> 157:ff67d9f36b67 175 #define MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE_POS))
<> 157:ff67d9f36b67 176 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS 3
<> 157:ff67d9f36b67 177 #define MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_DISCHARGE_EN_POS))
<> 157:ff67d9f36b67 178 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS 4
<> 157:ff67d9f36b67 179 #define MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TVDD12_WELL_POS))
<> 157:ff67d9f36b67 180 #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS 5
<> 157:ff67d9f36b67 181 #define MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SRAM_NWELL_SW_POS))
<> 157:ff67d9f36b67 182 #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS 6
<> 157:ff67d9f36b67 183 #define MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_AUTO_MBUS_GATE_POS))
<> 157:ff67d9f36b67 184 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS 8
<> 157:ff67d9f36b67 185 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIO_EN_RUN_POS))
<> 157:ff67d9f36b67 186 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS 10
<> 157:ff67d9f36b67 187 #define MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_SVM_VDDIOH_EN_RUN_POS))
<> 157:ff67d9f36b67 188 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS 12
<> 157:ff67d9f36b67 189 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V12_POS))
<> 157:ff67d9f36b67 190 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS 13
<> 157:ff67d9f36b67 191 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_VRTC_POS))
<> 157:ff67d9f36b67 192 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS 14
<> 157:ff67d9f36b67 193 #define MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_RETREG_SRC_V18_POS))
<> 157:ff67d9f36b67 194 #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS 16
<> 157:ff67d9f36b67 195 #define MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIO_EN_ISO_POR_POS))
<> 157:ff67d9f36b67 196 #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS 17
<> 157:ff67d9f36b67 197 #define MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_VDDIOH_EN_ISO_POR_POS))
<> 157:ff67d9f36b67 198 #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS 18
<> 157:ff67d9f36b67 199 #define MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP0_CORE_RESUME_EN_POS))
<> 157:ff67d9f36b67 200 #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS 19
<> 157:ff67d9f36b67 201 #define MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_LP1_CORE_RSTN_EN_POS))
<> 157:ff67d9f36b67 202
<> 157:ff67d9f36b67 203 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS 0
<> 157:ff67d9f36b67 204 #define MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD12_HYST_POS))
<> 157:ff67d9f36b67 205 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS 2
<> 157:ff67d9f36b67 206 #define MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDD18_HYST_POS))
<> 157:ff67d9f36b67 207 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS 4
<> 157:ff67d9f36b67 208 #define MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VRTC_HYST_POS))
<> 157:ff67d9f36b67 209 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS 6
<> 157:ff67d9f36b67 210 #define MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDB_HYST_POS))
<> 157:ff67d9f36b67 211 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS 8
<> 157:ff67d9f36b67 212 #define MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_TVDD12_HYST_POS))
<> 157:ff67d9f36b67 213 #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS 10
<> 157:ff67d9f36b67 214 #define MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIO_HYST_POS))
<> 157:ff67d9f36b67 215 #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS 12
<> 157:ff67d9f36b67 216 #define MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG2_PWR_VDDIOH_HYST_POS))
<> 157:ff67d9f36b67 217
<> 157:ff67d9f36b67 218 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS 0
<> 157:ff67d9f36b67 219 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
<> 157:ff67d9f36b67 220 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS 3
<> 157:ff67d9f36b67 221 #define MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FLTRROSEL_POS))
<> 157:ff67d9f36b67 222 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS 6
<> 157:ff67d9f36b67 223 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
<> 157:ff67d9f36b67 224 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS 8
<> 157:ff67d9f36b67 225 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
<> 157:ff67d9f36b67 226 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS 10
<> 157:ff67d9f36b67 227 #define MXC_F_PWRSEQ_REG3_PWR_FAILSEL ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_FAILSEL_POS))
<> 157:ff67d9f36b67 228 #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS 16
<> 157:ff67d9f36b67 229 #define MXC_F_PWRSEQ_REG3_PWR_RO_DIV ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_RO_DIV_POS))
<> 157:ff67d9f36b67 230 #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS 20
<> 157:ff67d9f36b67 231 #define MXC_F_PWRSEQ_REG3_PWR_RC_DIV ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_RC_DIV_POS))
<> 157:ff67d9f36b67 232
<> 157:ff67d9f36b67 233 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS 0
<> 157:ff67d9f36b67 234 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
<> 157:ff67d9f36b67 235 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS 1
<> 157:ff67d9f36b67 236 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
<> 157:ff67d9f36b67 237 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS 3
<> 157:ff67d9f36b67 238 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
<> 157:ff67d9f36b67 239 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS 4
<> 157:ff67d9f36b67 240 #define MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RO_TSTCLK_EN_POS))
<> 157:ff67d9f36b67 241 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS 5
<> 157:ff67d9f36b67 242 #define MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_NR_CLK_GATE_EN_POS))
<> 157:ff67d9f36b67 243 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS 6
<> 157:ff67d9f36b67 244 #define MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_EXT_CLK_IN_EN_POS))
<> 157:ff67d9f36b67 245 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS 7
<> 157:ff67d9f36b67 246 #define MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_PSEQ_32K_EN_POS))
<> 157:ff67d9f36b67 247 #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS 8
<> 157:ff67d9f36b67 248 #define MXC_F_PWRSEQ_REG4_PWR_RTC_MUX ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RTC_MUX_POS))
<> 157:ff67d9f36b67 249 #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS 9
<> 157:ff67d9f36b67 250 #define MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_RETREG_TRIM_LP1_EN_POS))
<> 157:ff67d9f36b67 251 #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS 10
<> 157:ff67d9f36b67 252 #define MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_XVR_TST_EN_POS))
<> 157:ff67d9f36b67 253
<> 157:ff67d9f36b67 254 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS 0
<> 157:ff67d9f36b67 255 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
<> 157:ff67d9f36b67 256 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS 9
<> 157:ff67d9f36b67 257 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_BIAS_POS))
<> 157:ff67d9f36b67 258 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS 15
<> 157:ff67d9f36b67 259 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0 ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_5_0_POS))
<> 157:ff67d9f36b67 260 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS 21
<> 157:ff67d9f36b67 261 #define MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_RTC_TRIM_POS))
<> 157:ff67d9f36b67 262 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS 25
<> 157:ff67d9f36b67 263 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6 ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG5_PWR_TRIM_RETREG_7_6_POS))
<> 157:ff67d9f36b67 264
<> 157:ff67d9f36b67 265 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS 0
<> 157:ff67d9f36b67 266 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
<> 157:ff67d9f36b67 267 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS 3
<> 157:ff67d9f36b67 268 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
<> 157:ff67d9f36b67 269 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS 7
<> 157:ff67d9f36b67 270 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
<> 157:ff67d9f36b67 271 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS 11
<> 157:ff67d9f36b67 272 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS))
<> 157:ff67d9f36b67 273 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS 20
<> 157:ff67d9f36b67 274 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC ((uint32_t)(0x000001FFUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_CRYPTO_OSC_POS))
<> 157:ff67d9f36b67 275
<> 157:ff67d9f36b67 276 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS 0
<> 157:ff67d9f36b67 277 #define MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG7_PWR_FLASH_PD_LOOKAHEAD_POS))
<> 157:ff67d9f36b67 278 #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS 16
<> 157:ff67d9f36b67 279 #define MXC_F_PWRSEQ_REG7_PWR_TRIM_RC ((uint32_t)(0x0000FFFFUL << MXC_F_PWRSEQ_REG7_PWR_TRIM_RC_POS))
<> 157:ff67d9f36b67 280
<> 157:ff67d9f36b67 281 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS 0
<> 157:ff67d9f36b67 282 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
<> 157:ff67d9f36b67 283 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS 1
<> 157:ff67d9f36b67 284 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
<> 157:ff67d9f36b67 285 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS 2
<> 157:ff67d9f36b67 286 #define MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POWER_FAIL_POS))
<> 157:ff67d9f36b67 287 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS 3
<> 157:ff67d9f36b67 288 #define MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BOOT_FAIL_POS))
<> 157:ff67d9f36b67 289 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS 4
<> 157:ff67d9f36b67 290 #define MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FLASH_DISCHARGE_POS))
<> 157:ff67d9f36b67 291 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS 5
<> 157:ff67d9f36b67 292 #define MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IOWAKEUP_POS))
<> 157:ff67d9f36b67 293 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS 6
<> 157:ff67d9f36b67 294 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD12_RST_BAD_POS))
<> 157:ff67d9f36b67 295 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS 7
<> 157:ff67d9f36b67 296 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD18_RST_BAD_POS))
<> 157:ff67d9f36b67 297 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS 8
<> 157:ff67d9f36b67 298 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_RST_BAD_POS))
<> 157:ff67d9f36b67 299 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS 9
<> 157:ff67d9f36b67 300 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDB_RST_BAD_POS))
<> 157:ff67d9f36b67 301 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS 10
<> 157:ff67d9f36b67 302 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_RST_BAD_POS))
<> 157:ff67d9f36b67 303 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
<> 157:ff67d9f36b67 304 #define MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
<> 157:ff67d9f36b67 305 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS 12
<> 157:ff67d9f36b67 306 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
<> 157:ff67d9f36b67 307 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS 13
<> 157:ff67d9f36b67 308 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
<> 157:ff67d9f36b67 309 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS 14
<> 157:ff67d9f36b67 310 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
<> 157:ff67d9f36b67 311 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS 15
<> 157:ff67d9f36b67 312 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
<> 157:ff67d9f36b67 313 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
<> 157:ff67d9f36b67 314 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
<> 157:ff67d9f36b67 315 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
<> 157:ff67d9f36b67 316 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
<> 157:ff67d9f36b67 317 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS 18
<> 157:ff67d9f36b67 318 #define MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_TVDD12_BAD_POS))
<> 157:ff67d9f36b67 319 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS 19
<> 157:ff67d9f36b67 320 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIO_RST_BAD_POS))
<> 157:ff67d9f36b67 321 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
<> 157:ff67d9f36b67 322 #define MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDDIOH_RST_BAD_POS))
<> 157:ff67d9f36b67 323 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
<> 157:ff67d9f36b67 324 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
<> 157:ff67d9f36b67 325 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
<> 157:ff67d9f36b67 326 #define MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
<> 157:ff67d9f36b67 327 #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
<> 157:ff67d9f36b67 328 #define MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
<> 157:ff67d9f36b67 329 #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
<> 157:ff67d9f36b67 330 #define MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
<> 157:ff67d9f36b67 331
<> 157:ff67d9f36b67 332 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS 1
<> 157:ff67d9f36b67 333 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
<> 157:ff67d9f36b67 334 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS 2
<> 157:ff67d9f36b67 335 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POWER_FAIL_POS))
<> 157:ff67d9f36b67 336 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS 3
<> 157:ff67d9f36b67 337 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BOOT_FAIL_POS))
<> 157:ff67d9f36b67 338 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS 4
<> 157:ff67d9f36b67 339 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_FLASH_DISCHARGE_POS))
<> 157:ff67d9f36b67 340 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS 5
<> 157:ff67d9f36b67 341 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IOWAKEUP_POS))
<> 157:ff67d9f36b67 342 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS 6
<> 157:ff67d9f36b67 343 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD12_RST_BAD_POS))
<> 157:ff67d9f36b67 344 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS 7
<> 157:ff67d9f36b67 345 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD18_RST_BAD_POS))
<> 157:ff67d9f36b67 346 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS 8
<> 157:ff67d9f36b67 347 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_RST_BAD_POS))
<> 157:ff67d9f36b67 348 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS 9
<> 157:ff67d9f36b67 349 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDB_RST_BAD_POS))
<> 157:ff67d9f36b67 350 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS 10
<> 157:ff67d9f36b67 351 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_RST_BAD_POS))
<> 157:ff67d9f36b67 352 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS 11
<> 157:ff67d9f36b67 353 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR18Z_FAIL_LATCH_POS))
<> 157:ff67d9f36b67 354 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS 12
<> 157:ff67d9f36b67 355 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
<> 157:ff67d9f36b67 356 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS 13
<> 157:ff67d9f36b67 357 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
<> 157:ff67d9f36b67 358 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS 14
<> 157:ff67d9f36b67 359 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
<> 157:ff67d9f36b67 360 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS 15
<> 157:ff67d9f36b67 361 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
<> 157:ff67d9f36b67 362 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS 16
<> 157:ff67d9f36b67 363 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
<> 157:ff67d9f36b67 364 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS 17
<> 157:ff67d9f36b67 365 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
<> 157:ff67d9f36b67 366 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS 18
<> 157:ff67d9f36b67 367 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_TVDD12_BAD_POS))
<> 157:ff67d9f36b67 368 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS 19
<> 157:ff67d9f36b67 369 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIO_RST_BAD_POS))
<> 157:ff67d9f36b67 370 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS 20
<> 157:ff67d9f36b67 371 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDDIOH_RST_BAD_POS))
<> 157:ff67d9f36b67 372 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS 21
<> 157:ff67d9f36b67 373 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIO_FAIL_POS))
<> 157:ff67d9f36b67 374 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS 22
<> 157:ff67d9f36b67 375 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_ISOZ_VDDIOH_FAIL_POS))
<> 157:ff67d9f36b67 376 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS 23
<> 157:ff67d9f36b67 377 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_NANORING_WAKEUP_FLAG_POS))
<> 157:ff67d9f36b67 378 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS 24
<> 157:ff67d9f36b67 379 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_WATCHDOG_RSTN_FLAG_POS))
<> 157:ff67d9f36b67 380
<> 157:ff67d9f36b67 381 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS 0
<> 157:ff67d9f36b67 382 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_SEQ_POS))
<> 157:ff67d9f36b67 383 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS 8
<> 157:ff67d9f36b67 384 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_WR_PROTECT_RTC_SEQ_POS))
<> 157:ff67d9f36b67 385 #define MXC_F_PWRSEQ_WR_PROTECT_RTC_POS 28
<> 157:ff67d9f36b67 386 #define MXC_F_PWRSEQ_WR_PROTECT_RTC ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_RTC_POS))
<> 157:ff67d9f36b67 387 #define MXC_F_PWRSEQ_WR_PROTECT_INFO_POS 29
<> 157:ff67d9f36b67 388 #define MXC_F_PWRSEQ_WR_PROTECT_INFO ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_INFO_POS))
<> 157:ff67d9f36b67 389 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS 30
<> 157:ff67d9f36b67 390 #define MXC_F_PWRSEQ_WR_PROTECT_BYPASS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_BYPASS_POS))
<> 157:ff67d9f36b67 391 #define MXC_F_PWRSEQ_WR_PROTECT_WP_POS 31
<> 157:ff67d9f36b67 392 #define MXC_F_PWRSEQ_WR_PROTECT_WP ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_WR_PROTECT_WP_POS))
<> 157:ff67d9f36b67 393
<> 157:ff67d9f36b67 394 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS 0
<> 157:ff67d9f36b67 395 #define MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RETN_CTRL_EN_POS))
<> 157:ff67d9f36b67 396 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS 1
<> 157:ff67d9f36b67 397 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_REL_CCG_EARLY_POS))
<> 157:ff67d9f36b67 398 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS 2
<> 157:ff67d9f36b67 399 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_USE_FLC_TWK_POS))
<> 157:ff67d9f36b67 400 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS 3
<> 157:ff67d9f36b67 401 #define MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RC_POLL_FLASH_POS))
<> 157:ff67d9f36b67 402 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS 4
<> 157:ff67d9f36b67 403 #define MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RETN_CTRL0_RESTORE_OVERRIDE_POS))
<> 157:ff67d9f36b67 404
<> 157:ff67d9f36b67 405 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS 0
<> 157:ff67d9f36b67 406 #define MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_RC_TWK_POS))
<> 157:ff67d9f36b67 407 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS 4
<> 157:ff67d9f36b67 408 #define MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_RETN_CTRL1_SRAM_FMS_POS))
<> 157:ff67d9f36b67 409
<> 157:ff67d9f36b67 410 #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS 0
<> 157:ff67d9f36b67 411 #define MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_PWR_MISC_INVERT_4_MASK_BITS_POS))
<> 157:ff67d9f36b67 412
<> 157:ff67d9f36b67 413 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS 0
<> 157:ff67d9f36b67 414 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_RD_POS))
<> 157:ff67d9f36b67 415 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS 1
<> 157:ff67d9f36b67 416 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_ASYNC_WR_POS))
<> 157:ff67d9f36b67 417 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS 2
<> 157:ff67d9f36b67 418 #define MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_TIMER_AUTO_UPDATE_POS))
<> 157:ff67d9f36b67 419 #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS 3
<> 157:ff67d9f36b67 420 #define MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_RTC_CTRL2_SSB_PERFORMANCE_POS))
<> 157:ff67d9f36b67 421 #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS 24
<> 157:ff67d9f36b67 422 #define MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_RTC_CTRL2_CFG_LOCK_POS))
<> 157:ff67d9f36b67 423
<> 157:ff67d9f36b67 424
<> 157:ff67d9f36b67 425
<> 157:ff67d9f36b67 426 #ifdef __cplusplus
<> 157:ff67d9f36b67 427 }
<> 157:ff67d9f36b67 428 #endif
<> 157:ff67d9f36b67 429
<> 157:ff67d9f36b67 430 #endif /* _MXC_PWRSEQ_REGS_H_ */
<> 157:ff67d9f36b67 431