sx1276.cpp

00001 /*
00002  / _____)             _              | |
00003 ( (____  _____ ____ _| |_ _____  ____| |__
00004  \____ \| ___ |    (_   _) ___ |/ ___)  _ \
00005  _____) ) ____| | | || |_| ____( (___| | | |
00006 (______/|_____)_|_|_| \__)_____)\____)_| |_|
00007     (C) 2014 Semtech
00008 
00009 Description: Actual implementation of a SX1276 radio, inherits Radio
00010 
00011 License: Revised BSD License, see LICENSE.TXT file include in the project
00012 
00013 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
00014 */
00015 
00016 /*
00017  * additional development to make it more generic across multiple OS versions
00018  * (c) 2017 Helmut Tschemernjak
00019  * 30826 Garbsen (Hannover) Germany
00020  */
00021 
00022 #include "sx1276.h"
00023 
00024 #include "main.h"
00025 
00026 
00027 
00028 const SX1276::BandwidthMap  SX1276::FskBandwidths[] =
00029 {
00030     { 2600  , 0x17 },   
00031     { 3100  , 0x0F },
00032     { 3900  , 0x07 },
00033     { 5200  , 0x16 },
00034     { 6300  , 0x0E },
00035     { 7800  , 0x06 },
00036     { 10400 , 0x15 },
00037     { 12500 , 0x0D },
00038     { 15600 , 0x05 },
00039     { 20800 , 0x14 },
00040     { 25000 , 0x0C },
00041     { 31300 , 0x04 },
00042     { 41700 , 0x13 },
00043     { 50000 , 0x0B },
00044     { 62500 , 0x03 },
00045     { 83333 , 0x12 },
00046     { 100000, 0x0A },
00047     { 125000, 0x02 },
00048     { 166700, 0x11 },
00049     { 200000, 0x09 },
00050     { 250000, 0x01 },
00051     { 300000, 0x00 }, // Invalid Bandwidth
00052 };
00053 
00054 const SX1276::BandwidthMap  SX1276::LoRaBandwidths[] =
00055 {
00056     {   7800, 0 }, //  7.8 kHz requires TCXO
00057     {  10400, 1 }, // 10.4 kHz requires TCXO
00058     {  15600, 2 }, // 15.6 kHz requires TCXO
00059     {  20800, 3 }, // 20.8 kHz requires TCXO
00060     {  31250, 4 }, // 31.25 kHz requires TCXO
00061     {  41700, 5 }, // 41.7 kHz requires TCXO
00062     {  62500, 6 }, // 62.5 kHz requires TCXO
00063     { 125000, 7 }, // 125 kHz the LoRa protocol default
00064     { 250000, 8 }, // 250 kHz
00065     { 500000, 9 }, // 500 kHz
00066     { 600000, 10 },  // Invalid Bandwidth, reserved
00067  };
00068 
00069 
00070 
00071 /*!
00072  * @brief Radio hardware registers initialization definition
00073  *
00074  * @remark Can be automatically generated by the SX1276 GUI (not yet implemented)
00075  */
00076 
00077 const SX1276::RadioRegisters  SX1276::RadioRegsInit[] = {
00078     { MODEM_FSK , REG_LNA                , 0x23 },
00079     { MODEM_FSK , REG_RXCONFIG           , 0x1E },
00080     { MODEM_FSK , REG_RSSICONFIG         , 0xD2 },
00081     { MODEM_FSK , REG_AFCFEI             , 0x01 },
00082     { MODEM_FSK , REG_PREAMBLEDETECT     , 0xAA },
00083     { MODEM_FSK , REG_OSC                , 0x07 },
00084     { MODEM_FSK , REG_SYNCCONFIG         , 0x12 },
00085     { MODEM_FSK , REG_SYNCVALUE1         , 0xC1 },
00086     { MODEM_FSK , REG_SYNCVALUE2         , 0x94 },
00087     { MODEM_FSK , REG_SYNCVALUE3         , 0xC1 },
00088     { MODEM_FSK , REG_PACKETCONFIG1      , 0xD8 },
00089     { MODEM_FSK , REG_FIFOTHRESH         , 0x8F },
00090     { MODEM_FSK , REG_IMAGECAL           , 0x02 },
00091     { MODEM_FSK , REG_DIOMAPPING1        , 0x00 },
00092     { MODEM_FSK , REG_DIOMAPPING2        , 0x30 },
00093     { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },
00094     
00095 };
00096 
00097 
00098 SX1276::SX1276( RadioEvents_t *events) : Radio ( events ), isRadioActive( false )
00099 {
00100     this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
00101     
00102     this->RadioEvents = events;
00103     
00104     this->dioIrq  = new DioIrqHandler [6];
00105 
00106     this->dioIrq [0] = &SX1276::OnDio0Irq;
00107     this->dioIrq [1] = &SX1276::OnDio1Irq;
00108     this->dioIrq [2] = &SX1276::OnDio2Irq;
00109     this->dioIrq [3] = &SX1276::OnDio3Irq;
00110     this->dioIrq [4] = &SX1276::OnDio4Irq;
00111     this->dioIrq [5] = NULL;
00112     
00113     this->settings.State = RF_IDLE;
00114 }
00115 
00116 SX1276::~SX1276( )
00117 {
00118     delete this->rxtxBuffer;
00119     delete this->dioIrq ;
00120 }
00121 
00122 bool SX1276::Init( RadioEvents_t *events )
00123 {
00124     if (Read(REG_VERSION) == 0x00)
00125         return false;
00126     
00127     this->RadioEvents = events;
00128     return true;
00129 }
00130 
00131 
00132 void SX1276::RadioRegistersInit( )
00133 {
00134     uint8_t i = 0;
00135     for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters  ); i++ )
00136     {
00137         SetModem( RadioRegsInit[i].Modem );
00138         Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
00139     }
00140 }
00141 
00142 
00143 RadioState SX1276::GetStatus ( void )
00144 {
00145     return this->settings.State;
00146 }
00147 
00148 void SX1276::SetChannel( uint32_t freq )
00149 {
00150     this->settings.Channel = freq;
00151     freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
00152     Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
00153     Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
00154     Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
00155 }
00156 
00157 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
00158 {
00159     int16_t rssi = 0;
00160 
00161     SetModem( modem );
00162 
00163     SetChannel( freq );
00164 
00165     SetOpMode( RF_OPMODE_RECEIVER );
00166 
00167     Sleep_ms( 1 );
00168 
00169     rssi = GetRssi( modem );
00170 
00171     Sleep( );
00172 
00173     if( rssi > rssiThresh )
00174     {
00175         return false;
00176     }
00177     return true;
00178 }
00179 
00180 uint32_t SX1276::Random( void )
00181 {
00182     uint8_t i;
00183     uint32_t rnd = 0;
00184 
00185     /*
00186      * Radio setup for random number generation
00187      */
00188     // Set LoRa modem ON
00189     SetModem( MODEM_LORA );
00190 
00191     // Disable LoRa modem interrupts
00192     Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
00193                   RFLR_IRQFLAGS_RXDONE |
00194                   RFLR_IRQFLAGS_PAYLOADCRCERROR |
00195                   RFLR_IRQFLAGS_VALIDHEADER |
00196                   RFLR_IRQFLAGS_TXDONE |
00197                   RFLR_IRQFLAGS_CADDONE |
00198                   RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00199                   RFLR_IRQFLAGS_CADDETECTED );
00200 
00201     // Set radio in continuous reception
00202     SetOpMode( RF_OPMODE_RECEIVER );
00203 
00204     for( i = 0; i < 32; i++ )
00205     {
00206         Sleep_ms( 1 );
00207         // Unfiltered RSSI value reading. Only takes the LSB value
00208         rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
00209     }
00210 
00211     Sleep( );
00212 
00213     return rnd;
00214 }
00215 
00216 /*!
00217  * Performs the Rx chain calibration for LF and HF bands
00218  * \remark Must be called just after the reset so all registers are at their
00219  *         default values
00220  */
00221 void SX1276::RxChainCalibration ( void )
00222 {
00223     uint8_t regPaConfigInitVal;
00224     uint32_t initialFreq;
00225 
00226     // Save context
00227     regPaConfigInitVal = this->Read( REG_PACONFIG );
00228     initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
00229                               ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
00230                               ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
00231 
00232     // Cut the PA just in case, RFO output, power = -1 dBm
00233     this->Write( REG_PACONFIG, 0x00 );
00234 
00235     // Launch Rx chain calibration for LF band
00236     Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
00237     while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
00238     {
00239     }
00240 
00241     // Sets a Frequency in HF band
00242     SetChannel( 868000000 );
00243 
00244     // Launch Rx chain calibration for HF band
00245     Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
00246     while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
00247     {
00248     }
00249 
00250     // Restore context
00251     this->Write( REG_PACONFIG, regPaConfigInitVal );
00252     SetChannel( initialFreq );
00253 }
00254 
00255 /*!
00256  * Returns the known FSK bandwidth registers value
00257  *
00258  * \param [IN] bandwidth Bandwidth value in Hz
00259  * \retval regValue Bandwidth register value.
00260  */
00261 uint8_t SX1276::GetFskBandwidthRegValue ( uint32_t bandwidth )
00262 {
00263     uint8_t i;
00264 
00265     for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( BandwidthMap  ) ) - 1; i++ )
00266     {
00267         if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
00268         {
00269             return FskBandwidths[i].RegValue;
00270         }
00271     }
00272     // ERROR: Value not found
00273     while( 1 );
00274 }
00275 
00276 /*!
00277  * Returns the known LoRa bandwidth registers value
00278  *
00279  * \param [IN] bandwidth Bandwidth value in Hz
00280  * \retval regValue Bandwidth register value.
00281  */
00282 uint8_t SX1276::GetLoRaBandwidthRegValue ( uint32_t bandwidth )
00283 {
00284     uint8_t i;
00285     
00286     for( i = 0; i < ( sizeof( LoRaBandwidths ) / sizeof( BandwidthMap  ) ) - 1; i++ )
00287     {
00288         if( ( bandwidth >= LoRaBandwidths[i].bandwidth ) && ( bandwidth < LoRaBandwidths[i + 1].bandwidth ) )
00289         {
00290             return LoRaBandwidths[i].RegValue;
00291         }
00292     }
00293     // ERROR: Value not found
00294     while( 1 );
00295 }
00296 
00297 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
00298                          uint32_t datarate, uint8_t coderate,
00299                          uint32_t bandwidthAfc, uint16_t preambleLen,
00300                          uint16_t symbTimeout, bool fixLen,
00301                          uint8_t payloadLen,
00302                          bool crcOn, bool freqHopOn, uint8_t hopPeriod,
00303                          bool iqInverted, bool rxContinuous )
00304 {
00305     SetModem( modem );
00306 
00307     switch( modem )
00308     {
00309     case MODEM_FSK:
00310         {
00311             this->settings.Fsk.Bandwidth = bandwidth;
00312             this->settings.Fsk.Datarate = datarate;
00313             this->settings.Fsk.BandwidthAfc = bandwidthAfc;
00314             this->settings.Fsk.FixLen = fixLen;
00315             this->settings.Fsk.PayloadLen = payloadLen;
00316             this->settings.Fsk.CrcOn = crcOn;
00317             this->settings.Fsk.IqInverted = iqInverted;
00318             this->settings.Fsk.RxContinuous = rxContinuous;
00319             this->settings.Fsk.PreambleLen = preambleLen;
00320             this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
00321 
00322 
00323             datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
00324             Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
00325             Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
00326 
00327             Write( REG_RXBW, GetFskBandwidthRegValue ( bandwidth ) );
00328             Write( REG_AFCBW, GetFskBandwidthRegValue ( bandwidthAfc ) );
00329 
00330             Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
00331             Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
00332 
00333             if( fixLen == 1 )
00334             {
00335                 Write( REG_PAYLOADLENGTH, payloadLen );
00336             }
00337             else
00338             {
00339                 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
00340             }
00341             
00342             Write( REG_PACKETCONFIG1,
00343                         ( Read( REG_PACKETCONFIG1 ) &
00344                            RF_PACKETCONFIG1_CRC_MASK &
00345                            RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
00346                            ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
00347                            ( crcOn << 4 ) );
00348             Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
00349         }
00350         break;
00351     case MODEM_LORA:
00352         {
00353             if (bandwidth > 11) // specified in Hz, needs mapping
00354                 bandwidth = GetLoRaBandwidthRegValue (bandwidth);
00355             if( bandwidth > LORA_BANKWIDTH_500kHz )
00356             {
00357                 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
00358                 while( 1 );
00359             }
00360             this->settings.LoRa.Bandwidth = bandwidth;
00361             this->settings.LoRa.Datarate = datarate;
00362             this->settings.LoRa.Coderate = coderate;
00363             this->settings.LoRa.PreambleLen = preambleLen;
00364             this->settings.LoRa.FixLen = fixLen;
00365             this->settings.LoRa.PayloadLen = payloadLen;
00366             this->settings.LoRa.CrcOn = crcOn;
00367             this->settings.LoRa.FreqHopOn = freqHopOn;
00368             this->settings.LoRa.HopPeriod = hopPeriod;
00369             this->settings.LoRa.IqInverted = iqInverted;
00370             this->settings.LoRa.RxContinuous = rxContinuous;
00371 
00372             if( datarate > LORA_SF12 )
00373             {
00374                 datarate = LORA_SF12;
00375             }
00376             else if( datarate < LORA_SF6 )
00377             {
00378                 datarate = LORA_SF6;
00379             }
00380 
00381             if( ( ( bandwidth == LORA_BANKWIDTH_125kHz ) && ( ( datarate == LORA_SF11 ) || ( datarate == LORA_SF12 ) ) ) ||
00382                 ( ( bandwidth == LORA_BANKWIDTH_250kHz ) && ( datarate == LORA_SF12 ) ) )
00383             {
00384                 this->settings.LoRa.LowDatarateOptimize = 0x01;
00385             }
00386             else
00387             {
00388                 this->settings.LoRa.LowDatarateOptimize = 0x00;
00389             }
00390 
00391             Write( REG_LR_MODEMCONFIG1,
00392                          ( Read( REG_LR_MODEMCONFIG1 ) &
00393                            RFLR_MODEMCONFIG1_BW_MASK &
00394                            RFLR_MODEMCONFIG1_CODINGRATE_MASK &
00395                            RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
00396                            ( bandwidth << 4 ) | ( coderate << 1 ) |
00397                            fixLen );
00398 
00399             Write( REG_LR_MODEMCONFIG2,
00400                          ( Read( REG_LR_MODEMCONFIG2 ) &
00401                            RFLR_MODEMCONFIG2_SF_MASK &
00402                            RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
00403                            RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
00404                            ( datarate << 4 ) | ( crcOn << 2 ) |
00405                            ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
00406 
00407             Write( REG_LR_MODEMCONFIG3,
00408                          ( Read( REG_LR_MODEMCONFIG3 ) &
00409                            RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
00410                            ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
00411 
00412             Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
00413 
00414             Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
00415             Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
00416 
00417             if( fixLen == 1 )
00418             {
00419                 Write( REG_LR_PAYLOADLENGTH, payloadLen );
00420             }
00421 
00422             if( this->settings.LoRa.FreqHopOn == true )
00423             {
00424                 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
00425                 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
00426             }
00427 
00428             if( ( bandwidth == LORA_BANKWIDTH_500kHz ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
00429             {
00430                 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
00431                 Write( REG_LR_TEST36, 0x02 );
00432                 Write( REG_LR_TEST3A, 0x64 );
00433             }
00434             else if( bandwidth == LORA_BANKWIDTH_500kHz )
00435             {
00436                 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
00437                 Write( REG_LR_TEST36, 0x02 );
00438                 Write( REG_LR_TEST3A, 0x7F );
00439             }
00440             else
00441             {
00442                 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
00443                 Write( REG_LR_TEST36, 0x03 );
00444             }
00445 
00446             if( datarate == LORA_SF6 )
00447             {
00448                 Write( REG_LR_DETECTOPTIMIZE,
00449                              ( Read( REG_LR_DETECTOPTIMIZE ) &
00450                                RFLR_DETECTIONOPTIMIZE_MASK ) |
00451                                RFLR_DETECTIONOPTIMIZE_SF6 );
00452                 Write( REG_LR_DETECTIONTHRESHOLD,
00453                              RFLR_DETECTIONTHRESH_SF6 );
00454             }
00455             else
00456             {
00457                 Write( REG_LR_DETECTOPTIMIZE,
00458                              ( Read( REG_LR_DETECTOPTIMIZE ) &
00459                              RFLR_DETECTIONOPTIMIZE_MASK ) |
00460                              RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
00461                 Write( REG_LR_DETECTIONTHRESHOLD,
00462                              RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
00463             }
00464         }
00465         break;
00466     }
00467 }
00468 
00469 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
00470                         uint32_t bandwidth, uint32_t datarate,
00471                         uint8_t coderate, uint16_t preambleLen,
00472                         bool fixLen, bool crcOn, bool freqHopOn,
00473                         uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
00474 {
00475     SetModem( modem );
00476     SetRfTxPower( power );
00477 
00478     switch( modem )
00479     {
00480     case MODEM_FSK:
00481         {
00482             this->settings.Fsk.Power = power;
00483             this->settings.Fsk.Fdev = fdev;
00484             this->settings.Fsk.Bandwidth = bandwidth;
00485             this->settings.Fsk.Datarate = datarate;
00486             this->settings.Fsk.PreambleLen = preambleLen;
00487             this->settings.Fsk.FixLen = fixLen;
00488             this->settings.Fsk.CrcOn = crcOn;
00489             this->settings.Fsk.IqInverted = iqInverted;
00490             this->settings.Fsk.TxTimeout = timeout;
00491 
00492             fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
00493             Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
00494             Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
00495 
00496             datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
00497             Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
00498             Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
00499 
00500             Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
00501             Write( REG_PREAMBLELSB, preambleLen & 0xFF );
00502 
00503             Write( REG_PACKETCONFIG1,
00504                          ( Read( REG_PACKETCONFIG1 ) &
00505                            RF_PACKETCONFIG1_CRC_MASK &
00506                            RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
00507                            ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
00508                            ( crcOn << 4 ) );
00509             Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
00510         }
00511         break;
00512     case MODEM_LORA:
00513         {
00514             this->settings.LoRa.Power = power;
00515             if (bandwidth > 11) // specified in Hz, needs mapping
00516                 bandwidth = GetLoRaBandwidthRegValue (bandwidth);
00517             if( bandwidth > LORA_BANKWIDTH_500kHz )
00518             {
00519                 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
00520                 while( 1 );
00521             }
00522             this->settings.LoRa.Bandwidth = bandwidth;
00523             this->settings.LoRa.Datarate = datarate;
00524             this->settings.LoRa.Coderate = coderate;
00525             this->settings.LoRa.PreambleLen = preambleLen;
00526             this->settings.LoRa.FixLen = fixLen;
00527             this->settings.LoRa.FreqHopOn = freqHopOn;
00528             this->settings.LoRa.HopPeriod = hopPeriod;
00529             this->settings.LoRa.CrcOn = crcOn;
00530             this->settings.LoRa.IqInverted = iqInverted;
00531             this->settings.LoRa.TxTimeout = timeout;
00532 
00533             if( datarate > LORA_SF12 )
00534             {
00535                 datarate = LORA_SF12;
00536             }
00537             else if( datarate < LORA_SF6 )
00538             {
00539                 datarate = LORA_SF6;
00540             }
00541             if( ( ( bandwidth == LORA_BANKWIDTH_125kHz ) && ( ( datarate == LORA_SF11 ) || ( datarate == LORA_SF12 ) ) ) ||
00542                 ( ( bandwidth == LORA_BANKWIDTH_250kHz ) && ( datarate == LORA_SF12 ) ) )
00543             {
00544                 this->settings.LoRa.LowDatarateOptimize = 0x01;
00545             }
00546             else
00547             {
00548                 this->settings.LoRa.LowDatarateOptimize = 0x00;
00549             }
00550 
00551             if( this->settings.LoRa.FreqHopOn == true )
00552             {
00553                 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
00554                 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
00555             }
00556 
00557             Write( REG_LR_MODEMCONFIG1,
00558                          ( Read( REG_LR_MODEMCONFIG1 ) &
00559                            RFLR_MODEMCONFIG1_BW_MASK &
00560                            RFLR_MODEMCONFIG1_CODINGRATE_MASK &
00561                            RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
00562                            ( bandwidth << 4 ) | ( coderate << 1 ) |
00563                            fixLen );
00564 
00565             Write( REG_LR_MODEMCONFIG2,
00566                          ( Read( REG_LR_MODEMCONFIG2 ) &
00567                            RFLR_MODEMCONFIG2_SF_MASK &
00568                            RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
00569                            ( datarate << 4 ) | ( crcOn << 2 ) );
00570 
00571             Write( REG_LR_MODEMCONFIG3,
00572                          ( Read( REG_LR_MODEMCONFIG3 ) &
00573                            RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
00574                            ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
00575 
00576             Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
00577             Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
00578 
00579             if( datarate == LORA_SF6 )
00580             {
00581                 Write( REG_LR_DETECTOPTIMIZE,
00582                              ( Read( REG_LR_DETECTOPTIMIZE ) &
00583                                RFLR_DETECTIONOPTIMIZE_MASK ) |
00584                                RFLR_DETECTIONOPTIMIZE_SF6 );
00585                 Write( REG_LR_DETECTIONTHRESHOLD,
00586                              RFLR_DETECTIONTHRESH_SF6 );
00587             }
00588             else
00589             {
00590                 Write( REG_LR_DETECTOPTIMIZE,
00591                              ( Read( REG_LR_DETECTOPTIMIZE ) &
00592                              RFLR_DETECTIONOPTIMIZE_MASK ) |
00593                              RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
00594                 Write( REG_LR_DETECTIONTHRESHOLD,
00595                              RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
00596             }
00597         }
00598         break;
00599     }
00600 }
00601 
00602 uint32_t SX1276::TimeOnAir( RadioModems_t modem, int16_t pktLen )
00603 {
00604     uint32_t airTime = 0;
00605 
00606     switch( modem )
00607     {
00608     case MODEM_FSK:
00609         {
00610             airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
00611                                      ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
00612                                      ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
00613                                      ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
00614                                      pktLen +
00615                                      ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
00616                                      this->settings.Fsk.Datarate ) * 1e3 );
00617         }
00618         break;
00619     case MODEM_LORA:
00620         {
00621             double bw = 0.0;
00622             // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
00623             switch( this->settings.LoRa.Bandwidth )
00624             {
00625             case LORA_BANKWIDTH_7kHz: // 7.8 kHz
00626                 bw = 78e2;
00627                 break;
00628             case LORA_BANKWIDTH_10kHz: // 10.4 kHz
00629                 bw = 104e2;
00630                 break;
00631             case LORA_BANKWIDTH_15kHz: // 15.6 kHz
00632                 bw = 156e2;
00633                 break;
00634             case LORA_BANKWIDTH_20kHz: // 20.8 kHz
00635                 bw = 208e2;
00636                 break;
00637             case LORA_BANKWIDTH_31kHz: // 31.25 kHz
00638                 bw = 312e2;
00639                 break;
00640             case LORA_BANKWIDTH_41kHz: // 41.7 kHz
00641                 bw = 414e2;
00642                 break;
00643             case LORA_BANKWIDTH_62kHz: // 62.5 kHz
00644                 bw = 625e2;
00645                 break;
00646             case LORA_BANKWIDTH_125kHz: // 125 kHz
00647                 bw = 125e3;
00648                 break;
00649             case LORA_BANKWIDTH_250kHz: // 250 kHz
00650                 bw = 250e3;
00651                 break;
00652             case LORA_BANKWIDTH_500kHz: // 500 kHz
00653                 bw = 500e3;
00654                 break;
00655             }
00656 
00657             // Symbol rate : time for one symbol (secs)
00658             double rs = bw / ( 1 << this->settings.LoRa.Datarate );
00659             double ts = 1 / rs;
00660             // time of preamble
00661             double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
00662             // Symbol length of payload and time
00663             double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
00664                                  28 + 16 * this->settings.LoRa.CrcOn -
00665                                  ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
00666                                  ( double )( 4 * ( this->settings.LoRa.Datarate -
00667                                  ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
00668                                  ( this->settings.LoRa.Coderate + 4 );
00669             double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
00670             double tPayload = nPayload * ts;
00671             // Time on air
00672             double tOnAir = tPreamble + tPayload;
00673             // return ms secs
00674             airTime = floor( tOnAir * 1e3 + 0.999 );
00675         }
00676         break;
00677     }
00678     return airTime;
00679 }
00680 
00681 void SX1276::Send( void *buffer, int16_t size, void *header, int16_t hsize )
00682 {
00683     uint32_t txTimeout = 0;
00684 
00685     switch( this->settings.Modem )
00686     {
00687     case MODEM_FSK:
00688         {
00689             this->settings.FskPacketHandler.NbBytes = 0;
00690             this->settings.FskPacketHandler.Size = size + hsize;
00691 
00692             if( this->settings.Fsk.FixLen == false )
00693             {
00694                 uint8_t tmpsize = size + hsize;
00695                 WriteFifo( ( uint8_t* )&tmpsize, 1 );
00696             }
00697             else
00698             {
00699                 Write( REG_PAYLOADLENGTH, size + hsize);
00700             }
00701 
00702             if( ( size + hsize > 0 ) && ( size + hsize <= 64 ) )
00703             {
00704                 this->settings.FskPacketHandler.ChunkSize = size + hsize;
00705             }
00706             else
00707             {
00708                 if (header) {
00709                     WriteFifo( header, hsize );
00710                     memcpy( rxtxBuffer, header, hsize );
00711                 }
00712                 memcpy( rxtxBuffer+hsize, (uint8_t *)buffer+hsize, size );
00713                 this->settings.FskPacketHandler.ChunkSize = 32;
00714             }
00715 
00716             // Write payload buffer
00717             if (header)
00718                 WriteFifo( header, hsize );
00719             WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
00720             this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
00721             txTimeout = this->settings.Fsk.TxTimeout;
00722         }
00723         break;
00724     case MODEM_LORA:
00725         {
00726             ser->printf("[SX1276] SX1276::Send MODEM_LORA\n\r");
00727             if( this->settings.LoRa.IqInverted == true )
00728             {
00729                 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
00730                 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
00731             }
00732             else
00733             {
00734                 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
00735                 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
00736             }
00737 
00738             this->settings.LoRaPacketHandler.Size = size + hsize;
00739 
00740             // Initializes the payload size
00741             Write( REG_LR_PAYLOADLENGTH, size + hsize);
00742 
00743             // Full buffer used for Tx
00744             Write( REG_LR_FIFOTXBASEADDR, 0 );
00745             Write( REG_LR_FIFOADDRPTR, 0 );
00746 
00747             // FIFO operations can not take place in Sleep mode
00748             if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
00749             {
00750                 Standby( );
00751                 Sleep_ms( 1 );
00752             }
00753             // Write payload buffer
00754             if (header)
00755                 WriteFifo( header, hsize );
00756             WriteFifo( buffer, size );
00757             txTimeout = this->settings.LoRa.TxTimeout;
00758         }
00759         break;
00760     }
00761 
00762     Tx( txTimeout );
00763 }
00764 
00765 void SX1276::Sleep( void )
00766 {
00767     SetTimeout(TXTimeoutTimer, NULL);
00768     SetTimeout(RXTimeoutTimer, NULL);
00769 
00770     SetOpMode( RF_OPMODE_SLEEP );
00771     this->settings.State = RF_IDLE;
00772 }
00773 
00774 void SX1276::Standby( void )
00775 {
00776     SetTimeout(TXTimeoutTimer, NULL);
00777     SetTimeout(RXTimeoutTimer, NULL);
00778 
00779     SetOpMode( RF_OPMODE_STANDBY );
00780     this->settings.State = RF_IDLE;
00781 }
00782 
00783 void SX1276::Rx( uint32_t timeout )
00784 {
00785     bool rxContinuous = false;
00786     
00787     switch( this->settings.Modem )
00788     {
00789     case MODEM_FSK:
00790         {
00791             rxContinuous = this->settings.Fsk.RxContinuous;
00792 
00793             // DIO0=PayloadReady
00794             // DIO1=FifoLevel
00795             // DIO2=SyncAddr
00796             // DIO3=FifoEmpty
00797             // DIO4=Preamble
00798             // DIO5=ModeReady
00799             Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
00800                                                                             RF_DIOMAPPING1_DIO1_MASK &
00801                                                                             RF_DIOMAPPING1_DIO2_MASK ) |
00802                                                                             RF_DIOMAPPING1_DIO0_00 |
00803                                                                             RF_DIOMAPPING1_DIO1_00 |
00804                                                                             RF_DIOMAPPING1_DIO2_11 );
00805 
00806             Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
00807                                                                             RF_DIOMAPPING2_MAP_MASK ) |
00808                                                                             RF_DIOMAPPING2_DIO4_11 |
00809                                                                             RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
00810 
00811             this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
00812 
00813             Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
00814 
00815             this->settings.FskPacketHandler.PreambleDetected = false;
00816             this->settings.FskPacketHandler.SyncWordDetected = false;
00817             this->settings.FskPacketHandler.NbBytes = 0;
00818             this->settings.FskPacketHandler.Size = 0;
00819         }
00820         break;
00821     case MODEM_LORA:
00822         {
00823             if( this->settings.LoRa.IqInverted == true )
00824             {
00825                 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
00826                 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
00827             }
00828             else
00829             {
00830                 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
00831                 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
00832             }
00833 
00834             // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
00835             if( this->settings.LoRa.Bandwidth < LORA_BANKWIDTH_500kHz )
00836             {
00837                 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
00838                 Write( REG_LR_TEST30, 0x00 );
00839                 switch( this->settings.LoRa.Bandwidth )
00840                 {
00841                 case LORA_BANKWIDTH_7kHz: // 7.8 kHz
00842                     Write( REG_LR_TEST2F, 0x48 );
00843                     SetChannel(this->settings.Channel + 7.81e3 );
00844                     break;
00845                 case LORA_BANKWIDTH_10kHz: // 10.4 kHz
00846                     Write( REG_LR_TEST2F, 0x44 );
00847                     SetChannel(this->settings.Channel + 10.42e3 );
00848                     break;
00849                 case LORA_BANKWIDTH_15kHz: // 15.6 kHz
00850                     Write( REG_LR_TEST2F, 0x44 );
00851                     SetChannel(this->settings.Channel + 15.62e3 );
00852                     break;
00853                 case LORA_BANKWIDTH_20kHz: // 20.8 kHz
00854                     Write( REG_LR_TEST2F, 0x44 );
00855                     SetChannel(this->settings.Channel + 20.83e3 );
00856                     break;
00857                 case LORA_BANKWIDTH_31kHz: // 31.25 kHz
00858                     Write( REG_LR_TEST2F, 0x44 );
00859                     SetChannel(this->settings.Channel + 31.25e3 );
00860                     break;
00861                 case LORA_BANKWIDTH_41kHz: // 41.4 kHz
00862                     Write( REG_LR_TEST2F, 0x44 );
00863                     SetChannel(this->settings.Channel + 41.67e3 );
00864                     break;
00865                 case LORA_BANKWIDTH_62kHz: // 62.5 kHz
00866                     Write( REG_LR_TEST2F, 0x40 );
00867                     break;
00868                 case LORA_BANKWIDTH_125kHz: // 125 kHz
00869                     Write( REG_LR_TEST2F, 0x40 );
00870                     break;
00871                 case LORA_BANKWIDTH_250kHz: // 250 kHz
00872                     Write( REG_LR_TEST2F, 0x40 );
00873                     break;
00874                 }
00875             }
00876             else
00877             {
00878                 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
00879             }
00880 
00881             rxContinuous = this->settings.LoRa.RxContinuous;
00882 
00883             if( this->settings.LoRa.FreqHopOn == true )
00884             {
00885                 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
00886                                                   //RFLR_IRQFLAGS_RXDONE |
00887                                                   //RFLR_IRQFLAGS_PAYLOADCRCERROR |
00888                                                   RFLR_IRQFLAGS_VALIDHEADER |
00889                                                   RFLR_IRQFLAGS_TXDONE |
00890                                                   RFLR_IRQFLAGS_CADDONE |
00891                                                   //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00892                                                   RFLR_IRQFLAGS_CADDETECTED );
00893 
00894                 // DIO0=RxDone, DIO2=FhssChangeChannel
00895                 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK  ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
00896             }
00897             else
00898             {
00899                 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
00900                                                   //RFLR_IRQFLAGS_RXDONE |
00901                                                   //RFLR_IRQFLAGS_PAYLOADCRCERROR |
00902                                                   RFLR_IRQFLAGS_VALIDHEADER |
00903                                                   RFLR_IRQFLAGS_TXDONE |
00904                                                   RFLR_IRQFLAGS_CADDONE |
00905                                                   RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00906                                                   RFLR_IRQFLAGS_CADDETECTED );
00907 
00908                 // DIO0=RxDone
00909                 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
00910             }
00911             Write( REG_LR_FIFORXBASEADDR, 0 );
00912             Write( REG_LR_FIFOADDRPTR, 0 );
00913         }
00914         break;
00915     }
00916     
00917     this->settings.State = RF_RX_RUNNING;
00918     if( timeout != 0 )
00919     {
00920         SetTimeout(RXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout * 1e3);
00921     }
00922 
00923     if( this->settings.Modem == MODEM_FSK )
00924     {
00925         SetOpMode( RF_OPMODE_RECEIVER );
00926 
00927         if( rxContinuous == false )
00928         {
00929             SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
00930         }
00931     }
00932     else
00933     {
00934         if( rxContinuous == true )
00935         {
00936             SetOpMode( RFLR_OPMODE_RECEIVER );
00937         }
00938         else
00939         {
00940             SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
00941         }
00942     }
00943 }
00944 
00945 bool SX1276::RxSignalPending()
00946 {
00947     if (this->settings.State != RF_RX_RUNNING)
00948         return false;
00949     
00950     switch( this->settings.Modem )
00951     {
00952         case MODEM_FSK:
00953             break;
00954         case MODEM_LORA:
00955             if (Read(REG_LR_MODEMSTAT) & (RFLR_MODEMSTAT_SIGNAL_DETECTED|RFLR_MODEMSTAT_SIGNAL_SYNCRONIZED|RFLR_MODEMSTAT_HEADERINFO_VALID|RFLR_MODEMSTAT_MODEM_CLEAR))
00956                 return true;
00957             break;
00958     }
00959     return false;
00960 }
00961 
00962 void SX1276::Tx( uint32_t timeout )
00963 {
00964 
00965     switch( this->settings.Modem )
00966     {
00967     case MODEM_FSK:
00968         {
00969             // DIO0=PacketSent
00970             // DIO1=FifoEmpty
00971             // DIO2=FifoFull
00972             // DIO3=FifoEmpty
00973             // DIO4=LowBat
00974             // DIO5=ModeReady
00975             Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
00976                                      RF_DIOMAPPING1_DIO1_MASK &
00977                                      RF_DIOMAPPING1_DIO2_MASK ) |
00978                                      RF_DIOMAPPING1_DIO1_01 );
00979 
00980             Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
00981                                                                             RF_DIOMAPPING2_MAP_MASK ) );
00982             this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
00983         }
00984         break;
00985     case MODEM_LORA:
00986         {
00987             if( this->settings.LoRa.FreqHopOn == true )
00988             {
00989                 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
00990                                                   RFLR_IRQFLAGS_RXDONE |
00991                                                   RFLR_IRQFLAGS_PAYLOADCRCERROR |
00992                                                   RFLR_IRQFLAGS_VALIDHEADER |
00993                                                   //RFLR_IRQFLAGS_TXDONE |
00994                                                   RFLR_IRQFLAGS_CADDONE |
00995                                                   //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
00996                                                   RFLR_IRQFLAGS_CADDETECTED );
00997 
00998                 // DIO0=TxDone, DIO2=FhssChangeChannel
00999                 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
01000             }
01001             else
01002             {
01003                 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
01004                                                   RFLR_IRQFLAGS_RXDONE |
01005                                                   RFLR_IRQFLAGS_PAYLOADCRCERROR |
01006                                                   RFLR_IRQFLAGS_VALIDHEADER |
01007                                                   //RFLR_IRQFLAGS_TXDONE |
01008                                                   RFLR_IRQFLAGS_CADDONE |
01009                                                   RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
01010                                                   RFLR_IRQFLAGS_CADDETECTED );
01011 
01012                 // DIO0=TxDone
01013                 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
01014             }
01015         }
01016         break;
01017     }
01018 
01019     this->settings.State = RF_TX_RUNNING;
01020     SetTimeout(TXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout * 1e3);
01021     SetOpMode( RF_OPMODE_TRANSMITTER );
01022 }
01023 
01024 void SX1276::StartCad( void )
01025 {
01026     switch( this->settings.Modem )
01027     {
01028     case MODEM_FSK:
01029         {
01030 
01031         }
01032         break;
01033     case MODEM_LORA:
01034         {
01035             Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
01036                                         RFLR_IRQFLAGS_RXDONE |
01037                                         RFLR_IRQFLAGS_PAYLOADCRCERROR |
01038                                         RFLR_IRQFLAGS_VALIDHEADER |
01039                                         RFLR_IRQFLAGS_TXDONE |
01040                                         //RFLR_IRQFLAGS_CADDONE |
01041                                         RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
01042                                         //RFLR_IRQFLAGS_CADDETECTED
01043                                         );
01044 
01045             // DIO3=CADDone
01046             Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
01047 
01048             this->settings.State = RF_CAD;
01049             SetOpMode( RFLR_OPMODE_CAD );
01050         }
01051         break;
01052     default:
01053         break;
01054     }
01055 }
01056 
01057 void SX1276::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
01058 {
01059     uint32_t timeout = ( uint32_t )( time * 1e6 );
01060     
01061     SetChannel( freq );
01062     
01063     SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
01064     
01065     Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
01066     // Disable radio interrupts
01067     Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
01068     Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
01069     
01070     this->settings.State = RF_TX_RUNNING;
01071     SetTimeout(TXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout);
01072     SetOpMode( RF_OPMODE_TRANSMITTER );
01073 }
01074 
01075 int16_t SX1276::MaxMTUSize( RadioModems_t modem )
01076 {
01077     int16_t mtuSize = 0;
01078     
01079     switch( modem )
01080     {
01081         case MODEM_FSK:
01082             mtuSize = RX_BUFFER_SIZE;
01083         case MODEM_LORA:
01084             mtuSize = RX_BUFFER_SIZE;
01085             break;
01086         default:
01087             mtuSize = -1;
01088             break;
01089     }
01090     return mtuSize;
01091 }
01092 
01093 int16_t SX1276::GetRssi( RadioModems_t modem )
01094 {
01095     int16_t rssi = 0;
01096 
01097     switch( modem )
01098     {
01099     case MODEM_FSK:
01100         rssi = -( Read( REG_RSSIVALUE ) >> 1 );
01101         break;
01102     case MODEM_LORA:
01103         if( this->settings.Channel > RF_MID_BAND_THRESH )
01104         {
01105             rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
01106         }
01107         else
01108         {
01109             rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
01110         }
01111         break;
01112     default:
01113         rssi = -1;
01114         break;
01115     }
01116     return rssi;
01117 }
01118 
01119 int32_t SX1276::GetFrequencyError(RadioModems_t modem )
01120 {
01121     int32_t val = 0;
01122     
01123     if (modem != MODEM_LORA)
01124         return 0;
01125     
01126     val = (Read(REG_LR_FEIMSB) & 0b1111) << 16; // high word, 4 valid bits only
01127     val |= ((Read(REG_LR_FEIMID) << 8) | Read(REG_LR_FEILSB)); // high byte, low byte
01128     if (val & 0x80000) //convert sign bit
01129         val |= 0xfff00000;
01130     
01131     int32_t bandwidth = 0;
01132     for (int i = 0; i < (int)(sizeof(LoRaBandwidths) / sizeof(BandwidthMap )) -1; i++ ) {
01133         if (LoRaBandwidths[i].RegValue == this->settings.LoRa.Bandwidth) {
01134             bandwidth = LoRaBandwidths[i].bandwidth;
01135             break;
01136         }
01137     }
01138     if (!bandwidth)
01139         return 0;
01140     
01141     float bandWidthkHz = (float)bandwidth/1000;
01142     
01143     int32_t hz = (((float)val * (float)(1<<24)) / ((float)XTAL_FREQ)) * (bandWidthkHz / 500.0);
01144         
01145     return hz;
01146 }
01147 
01148 
01149 void SX1276::SetOpMode( uint8_t opMode )
01150 {
01151     if( opMode == RF_OPMODE_SLEEP )
01152     {
01153         SetAntSwLowPower( true );
01154     }
01155     else
01156     {
01157         SetAntSwLowPower( false );
01158         SetAntSw( opMode );
01159     }
01160     Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
01161 }
01162 
01163 void SX1276::SetModem( RadioModems_t modem )
01164 {
01165     if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
01166     {
01167         this->settings.Modem = MODEM_LORA;
01168     }
01169     else
01170     {
01171         this->settings.Modem = MODEM_FSK;
01172     }
01173     
01174     if( this->settings.Modem == modem )
01175     {
01176         return;
01177     }
01178 
01179     this->settings.Modem = modem;
01180     switch( this->settings.Modem )
01181     {
01182     default:
01183     case MODEM_FSK:
01184         Sleep( );
01185         Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
01186     
01187         Write( REG_DIOMAPPING1, 0x00 );
01188         Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
01189         break;
01190     case MODEM_LORA:
01191         Sleep( );
01192         Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
01193 
01194         Write( REG_DIOMAPPING1, 0x00 );
01195         Write( REG_DIOMAPPING2, 0x00 );
01196         break;
01197     }
01198 }
01199 
01200 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
01201 {
01202     this->SetModem( modem );
01203 
01204     switch( modem )
01205     {
01206     case MODEM_FSK:
01207         if( this->settings.Fsk.FixLen == false )
01208         {
01209             this->Write( REG_PAYLOADLENGTH, max );
01210         }
01211         break;
01212     case MODEM_LORA:
01213         this->Write( REG_LR_PAYLOADMAXLENGTH, max );
01214         break;
01215     }
01216 }
01217 
01218 void SX1276::SetPublicNetwork( bool enable )
01219 {
01220     SetModem( MODEM_LORA );
01221     this->settings.LoRa.PublicNetwork = enable;
01222     if( enable == true )
01223     {
01224         // Change LoRa modem SyncWord
01225         Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
01226     }
01227     else
01228     {
01229         // Change LoRa modem SyncWord
01230         Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
01231     }
01232 }
01233 
01234 
01235 void SX1276::OnTimeoutIrq( void )
01236 {
01237     switch( this->settings.State )
01238     {
01239     case RF_RX_RUNNING:
01240         if( this->settings.Modem == MODEM_FSK )
01241         {
01242             this->settings.FskPacketHandler.PreambleDetected = false;
01243             this->settings.FskPacketHandler.SyncWordDetected = false;
01244             this->settings.FskPacketHandler.NbBytes = 0;
01245             this->settings.FskPacketHandler.Size = 0;
01246 
01247             // Clear Irqs
01248             Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
01249                                         RF_IRQFLAGS1_PREAMBLEDETECT |
01250                                         RF_IRQFLAGS1_SYNCADDRESSMATCH );
01251             Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
01252 
01253             if( this->settings.Fsk.RxContinuous == true )
01254             {
01255                 // Continuous mode restart Rx chain
01256                 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
01257                 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
01258             }
01259             else
01260             {
01261                 this->settings.State = RF_IDLE;
01262                 SetTimeout(RXTimeoutSyncWordTimer, NULL);
01263             }
01264         }
01265         if (this->RadioEvents && this->RadioEvents->RxTimeout)
01266         {
01267             this->RadioEvents->RxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
01268         }
01269         break;
01270     case RF_TX_RUNNING:
01271         // Tx timeout shouldn't happen.
01272         // But it has been observed that when it happens it is a result of a corrupted SPI transfer
01273         // it depends on the platform design.
01274         //
01275         // The workaround is to put the radio in a known state. Thus, we re-initialize it.
01276         // BEGIN WORKAROUND
01277 
01278         // Reset the radio
01279         Reset( );
01280 
01281         // Calibrate Rx chain
01282         RxChainCalibration ( );
01283 
01284         // Initialize radio default values
01285         SetOpMode( RF_OPMODE_SLEEP );
01286 
01287         RadioRegistersInit( );
01288 
01289         SetModem( MODEM_FSK );
01290 
01291         // Restore previous network type setting.
01292         SetPublicNetwork( this->settings.LoRa.PublicNetwork );
01293         // END WORKAROUND
01294             
01295         this->settings.State = RF_IDLE;
01296         if (this->RadioEvents && this->RadioEvents->TxTimeout)
01297         {
01298             this->RadioEvents->TxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
01299         }
01300         break;
01301     default:
01302         break;
01303     }
01304 }
01305 
01306 void SX1276::OnDio0Irq( void )
01307 {
01308     volatile uint8_t irqFlags = 0;
01309 
01310     switch( this->settings.State )
01311     {
01312         case RF_RX_RUNNING:
01313             //TimerStop( &RxTimeoutTimer );
01314             // RxDone interrupt
01315             switch( this->settings.Modem )
01316             {
01317             case MODEM_FSK:
01318                 if( this->settings.Fsk.CrcOn == true )
01319                 {
01320                     irqFlags = Read( REG_IRQFLAGS2 );
01321                     if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
01322                     {
01323                         // Clear Irqs
01324                         Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
01325                                                     RF_IRQFLAGS1_PREAMBLEDETECT |
01326                                                     RF_IRQFLAGS1_SYNCADDRESSMATCH );
01327                         Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
01328 
01329                         SetTimeout(RXTimeoutTimer, NULL);
01330 
01331                         if( this->settings.Fsk.RxContinuous == false )
01332                         {
01333                             SetTimeout(RXTimeoutSyncWordTimer, NULL);
01334                             this->settings.State = RF_IDLE;
01335                         }
01336                         else
01337                         {
01338                             // Continuous mode restart Rx chain
01339                             Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
01340                             SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
01341                         }
01342 
01343                         if (this->RadioEvents && this->RadioEvents->RxError)
01344                         {
01345                             this->RadioEvents->RxError(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
01346                         }
01347                         this->settings.FskPacketHandler.PreambleDetected = false;
01348                         this->settings.FskPacketHandler.SyncWordDetected = false;
01349                         this->settings.FskPacketHandler.NbBytes = 0;
01350                         this->settings.FskPacketHandler.Size = 0;
01351                         break;
01352                     }
01353                 }
01354 
01355                 // Read received packet size
01356                 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
01357                 {
01358                     if( this->settings.Fsk.FixLen == false )
01359                     {
01360                         ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
01361                     }
01362                     else
01363                     {
01364                         this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
01365                     }
01366                     ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01367                     this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01368                 }
01369                 else
01370                 {
01371                     ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01372                     this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01373                 }
01374 
01375                 SetTimeout(RXTimeoutTimer, NULL);
01376                     
01377                 if( this->settings.Fsk.RxContinuous == false )
01378                 {
01379                     this->settings.State = RF_IDLE;
01380                     SetTimeout(RXTimeoutSyncWordTimer, NULL);
01381                 }
01382                 else
01383                 {
01384                     // Continuous mode restart Rx chain
01385                     Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
01386                     SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
01387                 }
01388 
01389                 if (this->RadioEvents && this->RadioEvents->RxDone)
01390                 {
01391                     this->RadioEvents->RxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
01392                 }
01393                 this->settings.FskPacketHandler.PreambleDetected = false;
01394                 this->settings.FskPacketHandler.SyncWordDetected = false;
01395                 this->settings.FskPacketHandler.NbBytes = 0;
01396                 this->settings.FskPacketHandler.Size = 0;
01397                 break;
01398             case MODEM_LORA:
01399                 {
01400                     int8_t snr = 0;
01401 
01402                     // Clear Irq
01403                     Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
01404 
01405                     irqFlags = Read( REG_LR_IRQFLAGS );
01406                     if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
01407                     {
01408                         // Clear Irq
01409                         Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
01410 
01411                         if( this->settings.LoRa.RxContinuous == false )
01412                         {
01413                             this->settings.State = RF_IDLE;
01414                         }
01415                         SetTimeout(RXTimeoutTimer, NULL);
01416                         
01417                         if(this->RadioEvents && this->RadioEvents->RxError)
01418                         {
01419                             this->RadioEvents->RxError(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
01420                         }
01421                         break;
01422                     }
01423 
01424                     this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
01425                     if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
01426                     {
01427                         // Invert and divide by 4
01428                         snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
01429                         snr = -snr;
01430                     }
01431                     else
01432                     {
01433                         // Divide by 4
01434                         snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
01435                     }
01436 
01437                     int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
01438                     if( snr < 0 )
01439                     {
01440                         if( this->settings.Channel > RF_MID_BAND_THRESH )
01441                         {
01442                             this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
01443                                                                           snr;
01444                         }
01445                         else
01446                         {
01447                             this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
01448                                                                           snr;
01449                         }
01450                     }
01451                     else
01452                     {
01453                         if( this->settings.Channel > RF_MID_BAND_THRESH )
01454                         {
01455                             this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
01456                         }
01457                         else
01458                         {
01459                             this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
01460                         }
01461                     }
01462 
01463                     this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
01464                     ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
01465 
01466                     if( this->settings.LoRa.RxContinuous == false )
01467                     {
01468                         this->settings.State = RF_IDLE;
01469                     }
01470                     SetTimeout(RXTimeoutTimer, NULL);
01471                     
01472                     if(this->RadioEvents && this->RadioEvents->RxDone)
01473                     {
01474                         this->RadioEvents->RxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
01475                     }
01476                 }
01477                 break;
01478             default:
01479                 break;
01480             }
01481             break;
01482         case RF_TX_RUNNING:
01483             SetTimeout(TXTimeoutTimer, NULL);
01484             // TxDone interrupt
01485             switch( this->settings.Modem )
01486             {
01487             case MODEM_LORA:
01488                 // Clear Irq
01489                 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
01490                 // Intentional fall through
01491             case MODEM_FSK:
01492             default:
01493                 this->settings.State = RF_IDLE;
01494                 if (this->RadioEvents && this->RadioEvents->TxDone)
01495                 {
01496                     this->RadioEvents->TxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
01497                 }
01498                 break;
01499             }
01500             break;
01501         default:
01502             break;
01503     }
01504 }
01505 
01506 void SX1276::OnDio1Irq( void )
01507 {
01508     switch( this->settings.State )
01509     {
01510         case RF_RX_RUNNING:
01511             switch( this->settings.Modem )
01512             {
01513             case MODEM_FSK:
01514                 // FifoLevel interrupt
01515                 // Read received packet size
01516                 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
01517                 {
01518                     if( this->settings.Fsk.FixLen == false )
01519                     {
01520                         ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
01521                     }
01522                     else
01523                     {
01524                         this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
01525                     }
01526                 }
01527 
01528                 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
01529                 {
01530                     ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
01531                     this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
01532                 }
01533                 else
01534                 {
01535                     ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01536                     this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01537                 }
01538                 break;
01539             case MODEM_LORA:
01540                 // Sync time out
01541                 SetTimeout(RXTimeoutTimer, NULL);
01542                 // Clear Irq
01543                 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
01544 
01545                 this->settings.State = RF_IDLE;
01546                 if (this->RadioEvents &&  this->RadioEvents->RxTimeout)
01547                 {
01548                     this->RadioEvents->RxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
01549                 }
01550                 break;
01551             default:
01552                 break;
01553             }
01554             break;
01555         case RF_TX_RUNNING:
01556             switch( this->settings.Modem )
01557             {
01558             case MODEM_FSK:
01559                 // FifoEmpty interrupt
01560                 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
01561                 {
01562                     WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
01563                     this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
01564                 }
01565                 else
01566                 {
01567                     // Write the last chunk of data
01568                     WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
01569                     this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
01570                 }
01571                 break;
01572             case MODEM_LORA:
01573                 break;
01574             default:
01575                 break;
01576             }
01577             break;
01578         default:
01579             break;
01580     }
01581 }
01582 
01583 void SX1276::OnDio2Irq( void )
01584 {
01585     switch( this->settings.State )
01586     {
01587         case RF_RX_RUNNING:
01588             switch( this->settings.Modem )
01589             {
01590             case MODEM_FSK:
01591                 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
01592                 if( this->dioIrq [4] == NULL )
01593                 {
01594                     this->settings.FskPacketHandler.PreambleDetected = true;
01595                 }
01596 
01597                 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
01598                 {
01599                     SetTimeout(RXTimeoutSyncWordTimer, NULL);
01600                     
01601                     this->settings.FskPacketHandler.SyncWordDetected = true;
01602 
01603                     this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
01604 
01605                     this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
01606                                                                            ( uint16_t )Read( REG_AFCLSB ) ) *
01607                                                                            ( double )FREQ_STEP;
01608                     this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
01609                 }
01610                 break;
01611             case MODEM_LORA:
01612                 if( this->settings.LoRa.FreqHopOn == true )
01613                 {
01614                     // Clear Irq
01615                     Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
01616 
01617                     if (this->RadioEvents &&  this->RadioEvents->FhssChangeChannel)
01618                     {
01619                         this->RadioEvents->FhssChangeChannel(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
01620                     }
01621                 }
01622                 break;
01623             default:
01624                 break;
01625             }
01626             break;
01627         case RF_TX_RUNNING:
01628             switch( this->settings.Modem )
01629             {
01630             case MODEM_FSK:
01631                 break;
01632             case MODEM_LORA:
01633                 if( this->settings.LoRa.FreqHopOn == true )
01634                 {
01635                     // Clear Irq
01636                     Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
01637 
01638                     if (this->RadioEvents && this->RadioEvents->FhssChangeChannel)
01639                     {
01640                         this->RadioEvents->FhssChangeChannel(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
01641                     }
01642                 }
01643                 break;
01644             default:
01645                 break;
01646             }
01647             break;
01648         default:
01649             break;
01650     }
01651 }
01652 
01653 void SX1276::OnDio3Irq( void )
01654 {
01655     switch( this->settings.Modem )
01656     {
01657     case MODEM_FSK:
01658         break;
01659     case MODEM_LORA:
01660         if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
01661         {
01662             // Clear Irq
01663             Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
01664             if (this->RadioEvents && this->RadioEvents->CadDone)
01665             {
01666                 this->RadioEvents->CadDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, true );
01667             }
01668         }
01669         else
01670         {
01671             // Clear Irq
01672             Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
01673             if (this->RadioEvents && this->RadioEvents->CadDone)
01674             {
01675                 this->RadioEvents->CadDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, false );
01676             }
01677         }
01678         break;
01679     default:
01680         break;
01681     }
01682 }
01683 
01684 void SX1276::OnDio4Irq( void )
01685 {
01686     switch( this->settings.Modem )
01687     {
01688     case MODEM_FSK:
01689         {
01690             if( this->settings.FskPacketHandler.PreambleDetected == false )
01691             {
01692                 this->settings.FskPacketHandler.PreambleDetected = true;
01693             }
01694         }
01695         break;
01696     case MODEM_LORA:
01697         break;
01698     default:
01699         break;
01700     }
01701 }
01702 
01703 void SX1276::OnDio5Irq( void )
01704 {
01705     switch( this->settings.Modem )
01706     {
01707     case MODEM_FSK:
01708         break;
01709     case MODEM_LORA:
01710         break;
01711     default:
01712         break;
01713     }
01714 }