Yujing Qian
/
202hm2_master_monitor
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MKL46Z4.h
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00001 /* 00002 ** ################################################################### 00003 ** Processors: MKL46Z256VLH4 00004 ** MKL46Z128VLH4 00005 ** MKL46Z256VLL4 00006 ** MKL46Z128VLL4 00007 ** MKL46Z256VMC4 00008 ** MKL46Z128VMC4 00009 ** 00010 ** Compilers: ARM Compiler 00011 ** Freescale C/C++ for Embedded ARM 00012 ** GNU C Compiler 00013 ** IAR ANSI C/C++ Compiler for ARM 00014 ** 00015 ** Reference manual: KL46P121M48SF4RM, Rev.2, Dec 2012 00016 ** Version: rev. 2.2, 2013-04-12 00017 ** 00018 ** Abstract: 00019 ** CMSIS Peripheral Access Layer for MKL46Z4 00020 ** 00021 ** Copyright: 1997 - 2013 Freescale, Inc. All Rights Reserved. 00022 ** 00023 ** http: www.freescale.com 00024 ** mail: support@freescale.com 00025 ** 00026 ** Revisions: 00027 ** - rev. 1.0 (2012-10-16) 00028 ** Initial version. 00029 ** - rev. 2.0 (2012-12-12) 00030 ** Update to reference manual rev. 1. 00031 ** - rev. 2.1 (2013-04-05) 00032 ** Changed start of doxygen comment. 00033 ** - rev. 2.2 (2013-04-12) 00034 ** SystemInit function fixed for clock configuration 1. 00035 ** Name of the interrupt num. 31 updated to reflect proper function. 00036 ** 00037 ** ################################################################### 00038 */ 00039 00040 /*! 00041 * @file MKL46Z4.h 00042 * @version 2.2 00043 * @date 2013-04-12 00044 * @brief CMSIS Peripheral Access Layer for MKL46Z4 00045 * 00046 * CMSIS Peripheral Access Layer for MKL46Z4 00047 */ 00048 00049 #if !defined(MKL46Z4_H_) 00050 #define MKL46Z4_H_ /**< Symbol preventing repeated inclusion */ 00051 00052 /** Memory map major version (memory maps with equal major version number are 00053 * compatible) */ 00054 #define MCU_MEM_MAP_VERSION 0x0200u 00055 /** Memory map minor version */ 00056 #define MCU_MEM_MAP_VERSION_MINOR 0x0002u 00057 00058 00059 /* ---------------------------------------------------------------------------- 00060 -- Interrupt vector numbers 00061 ---------------------------------------------------------------------------- */ 00062 00063 /*! 00064 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 00065 * @{ 00066 */ 00067 00068 /** Interrupt Number Definitions */ 00069 typedef enum IRQn { 00070 /* Core interrupts */ 00071 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 00072 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 00073 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 00074 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 00075 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 00076 00077 /* Device specific interrupts */ 00078 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete/error interrupt */ 00079 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete/error interrupt */ 00080 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete/error interrupt */ 00081 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete/error interrupt */ 00082 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */ 00083 FTFA_IRQn = 5, /**< FTFA command complete/read collision interrupt */ 00084 LVD_LVW_IRQn = 6, /**< Low Voltage Detect, Low Voltage Warning */ 00085 LLW_IRQn = 7, /**< Low Leakage Wakeup */ 00086 I2C0_IRQn = 8, /**< I2C0 interrupt */ 00087 I2C1_IRQn = 9, /**< I2C0 interrupt 25 */ 00088 SPI0_IRQn = 10, /**< SPI0 interrupt */ 00089 SPI1_IRQn = 11, /**< SPI1 interrupt */ 00090 UART0_IRQn = 12, /**< UART0 status/error interrupt */ 00091 UART1_IRQn = 13, /**< UART1 status/error interrupt */ 00092 UART2_IRQn = 14, /**< UART2 status/error interrupt */ 00093 ADC0_IRQn = 15, /**< ADC0 interrupt */ 00094 CMP0_IRQn = 16, /**< CMP0 interrupt */ 00095 TPM0_IRQn = 17, /**< TPM0 fault, overflow and channels interrupt */ 00096 TPM1_IRQn = 18, /**< TPM1 fault, overflow and channels interrupt */ 00097 TPM2_IRQn = 19, /**< TPM2 fault, overflow and channels interrupt */ 00098 RTC_IRQn = 20, /**< RTC interrupt */ 00099 RTC_Seconds_IRQn = 21, /**< RTC seconds interrupt */ 00100 PIT_IRQn = 22, /**< PIT timer interrupt */ 00101 I2S0_IRQn = 23, /**< I2S0 transmit interrupt */ 00102 USB0_IRQn = 24, /**< USB0 interrupt */ 00103 DAC0_IRQn = 25, /**< DAC0 interrupt */ 00104 TSI0_IRQn = 26, /**< TSI0 interrupt */ 00105 MCG_IRQn = 27, /**< MCG interrupt */ 00106 LPTimer_IRQn = 28, /**< LPTimer interrupt */ 00107 LCD_IRQn = 29, /**< Segment LCD Interrupt */ 00108 PORTA_IRQn = 30, /**< Port A interrupt */ 00109 PORTC_PORTD_IRQn = 31 /**< Port C and port D interrupt */ 00110 } IRQn_Type; 00111 00112 /*! 00113 * @} 00114 */ /* end of group Interrupt_vector_numbers */ 00115 00116 00117 /* ---------------------------------------------------------------------------- 00118 -- Cortex M0 Core Configuration 00119 ---------------------------------------------------------------------------- */ 00120 00121 /*! 00122 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 00123 * @{ 00124 */ 00125 00126 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 00127 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 00128 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */ 00129 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 00130 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 00131 00132 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 00133 #include "system_MKL46Z4.h" /* Device specific configuration file */ 00134 00135 /*! 00136 * @} 00137 */ /* end of group Cortex_Core_Configuration */ 00138 00139 00140 /* ---------------------------------------------------------------------------- 00141 -- Device Peripheral Access Layer 00142 ---------------------------------------------------------------------------- */ 00143 00144 /*! 00145 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 00146 * @{ 00147 */ 00148 00149 00150 /* 00151 ** Start of section using anonymous unions 00152 */ 00153 00154 #if defined(__ARMCC_VERSION) 00155 #pragma push 00156 #pragma anon_unions 00157 #elif defined(__CWCC__) 00158 #pragma push 00159 #pragma cpp_extensions on 00160 #elif defined(__GNUC__) 00161 /* anonymous unions are enabled by default */ 00162 #elif defined(__IAR_SYSTEMS_ICC__) 00163 #pragma language=extended 00164 #else 00165 #error Not supported compiler type 00166 #endif 00167 00168 /* ---------------------------------------------------------------------------- 00169 -- ADC Peripheral Access Layer 00170 ---------------------------------------------------------------------------- */ 00171 00172 /*! 00173 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 00174 * @{ 00175 */ 00176 00177 /** ADC - Register Layout Typedef */ 00178 typedef struct { 00179 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 00180 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ 00181 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ 00182 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ 00183 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ 00184 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ 00185 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ 00186 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ 00187 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ 00188 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ 00189 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ 00190 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ 00191 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ 00192 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ 00193 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ 00194 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 00195 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 00196 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 00197 uint8_t RESERVED_0[4]; 00198 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ 00199 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ 00200 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ 00201 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ 00202 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ 00203 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ 00204 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ 00205 } ADC_Type; 00206 00207 /* ---------------------------------------------------------------------------- 00208 -- ADC Register Masks 00209 ---------------------------------------------------------------------------- */ 00210 00211 /*! 00212 * @addtogroup ADC_Register_Masks ADC Register Masks 00213 * @{ 00214 */ 00215 00216 /* SC1 Bit Fields */ 00217 #define ADC_SC1_ADCH_MASK 0x1Fu 00218 #define ADC_SC1_ADCH_SHIFT 0 00219 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK) 00220 #define ADC_SC1_DIFF_MASK 0x20u 00221 #define ADC_SC1_DIFF_SHIFT 5 00222 #define ADC_SC1_AIEN_MASK 0x40u 00223 #define ADC_SC1_AIEN_SHIFT 6 00224 #define ADC_SC1_COCO_MASK 0x80u 00225 #define ADC_SC1_COCO_SHIFT 7 00226 /* CFG1 Bit Fields */ 00227 #define ADC_CFG1_ADICLK_MASK 0x3u 00228 #define ADC_CFG1_ADICLK_SHIFT 0 00229 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK) 00230 #define ADC_CFG1_MODE_MASK 0xCu 00231 #define ADC_CFG1_MODE_SHIFT 2 00232 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK) 00233 #define ADC_CFG1_ADLSMP_MASK 0x10u 00234 #define ADC_CFG1_ADLSMP_SHIFT 4 00235 #define ADC_CFG1_ADIV_MASK 0x60u 00236 #define ADC_CFG1_ADIV_SHIFT 5 00237 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK) 00238 #define ADC_CFG1_ADLPC_MASK 0x80u 00239 #define ADC_CFG1_ADLPC_SHIFT 7 00240 /* CFG2 Bit Fields */ 00241 #define ADC_CFG2_ADLSTS_MASK 0x3u 00242 #define ADC_CFG2_ADLSTS_SHIFT 0 00243 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK) 00244 #define ADC_CFG2_ADHSC_MASK 0x4u 00245 #define ADC_CFG2_ADHSC_SHIFT 2 00246 #define ADC_CFG2_ADACKEN_MASK 0x8u 00247 #define ADC_CFG2_ADACKEN_SHIFT 3 00248 #define ADC_CFG2_MUXSEL_MASK 0x10u 00249 #define ADC_CFG2_MUXSEL_SHIFT 4 00250 /* R Bit Fields */ 00251 #define ADC_R_D_MASK 0xFFFFu 00252 #define ADC_R_D_SHIFT 0 00253 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK) 00254 /* CV1 Bit Fields */ 00255 #define ADC_CV1_CV_MASK 0xFFFFu 00256 #define ADC_CV1_CV_SHIFT 0 00257 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK) 00258 /* CV2 Bit Fields */ 00259 #define ADC_CV2_CV_MASK 0xFFFFu 00260 #define ADC_CV2_CV_SHIFT 0 00261 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK) 00262 /* SC2 Bit Fields */ 00263 #define ADC_SC2_REFSEL_MASK 0x3u 00264 #define ADC_SC2_REFSEL_SHIFT 0 00265 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK) 00266 #define ADC_SC2_DMAEN_MASK 0x4u 00267 #define ADC_SC2_DMAEN_SHIFT 2 00268 #define ADC_SC2_ACREN_MASK 0x8u 00269 #define ADC_SC2_ACREN_SHIFT 3 00270 #define ADC_SC2_ACFGT_MASK 0x10u 00271 #define ADC_SC2_ACFGT_SHIFT 4 00272 #define ADC_SC2_ACFE_MASK 0x20u 00273 #define ADC_SC2_ACFE_SHIFT 5 00274 #define ADC_SC2_ADTRG_MASK 0x40u 00275 #define ADC_SC2_ADTRG_SHIFT 6 00276 #define ADC_SC2_ADACT_MASK 0x80u 00277 #define ADC_SC2_ADACT_SHIFT 7 00278 /* SC3 Bit Fields */ 00279 #define ADC_SC3_AVGS_MASK 0x3u 00280 #define ADC_SC3_AVGS_SHIFT 0 00281 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK) 00282 #define ADC_SC3_AVGE_MASK 0x4u 00283 #define ADC_SC3_AVGE_SHIFT 2 00284 #define ADC_SC3_ADCO_MASK 0x8u 00285 #define ADC_SC3_ADCO_SHIFT 3 00286 #define ADC_SC3_CALF_MASK 0x40u 00287 #define ADC_SC3_CALF_SHIFT 6 00288 #define ADC_SC3_CAL_MASK 0x80u 00289 #define ADC_SC3_CAL_SHIFT 7 00290 /* OFS Bit Fields */ 00291 #define ADC_OFS_OFS_MASK 0xFFFFu 00292 #define ADC_OFS_OFS_SHIFT 0 00293 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK) 00294 /* PG Bit Fields */ 00295 #define ADC_PG_PG_MASK 0xFFFFu 00296 #define ADC_PG_PG_SHIFT 0 00297 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK) 00298 /* MG Bit Fields */ 00299 #define ADC_MG_MG_MASK 0xFFFFu 00300 #define ADC_MG_MG_SHIFT 0 00301 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK) 00302 /* CLPD Bit Fields */ 00303 #define ADC_CLPD_CLPD_MASK 0x3Fu 00304 #define ADC_CLPD_CLPD_SHIFT 0 00305 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK) 00306 /* CLPS Bit Fields */ 00307 #define ADC_CLPS_CLPS_MASK 0x3Fu 00308 #define ADC_CLPS_CLPS_SHIFT 0 00309 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK) 00310 /* CLP4 Bit Fields */ 00311 #define ADC_CLP4_CLP4_MASK 0x3FFu 00312 #define ADC_CLP4_CLP4_SHIFT 0 00313 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK) 00314 /* CLP3 Bit Fields */ 00315 #define ADC_CLP3_CLP3_MASK 0x1FFu 00316 #define ADC_CLP3_CLP3_SHIFT 0 00317 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK) 00318 /* CLP2 Bit Fields */ 00319 #define ADC_CLP2_CLP2_MASK 0xFFu 00320 #define ADC_CLP2_CLP2_SHIFT 0 00321 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK) 00322 /* CLP1 Bit Fields */ 00323 #define ADC_CLP1_CLP1_MASK 0x7Fu 00324 #define ADC_CLP1_CLP1_SHIFT 0 00325 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK) 00326 /* CLP0 Bit Fields */ 00327 #define ADC_CLP0_CLP0_MASK 0x3Fu 00328 #define ADC_CLP0_CLP0_SHIFT 0 00329 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK) 00330 /* CLMD Bit Fields */ 00331 #define ADC_CLMD_CLMD_MASK 0x3Fu 00332 #define ADC_CLMD_CLMD_SHIFT 0 00333 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK) 00334 /* CLMS Bit Fields */ 00335 #define ADC_CLMS_CLMS_MASK 0x3Fu 00336 #define ADC_CLMS_CLMS_SHIFT 0 00337 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK) 00338 /* CLM4 Bit Fields */ 00339 #define ADC_CLM4_CLM4_MASK 0x3FFu 00340 #define ADC_CLM4_CLM4_SHIFT 0 00341 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK) 00342 /* CLM3 Bit Fields */ 00343 #define ADC_CLM3_CLM3_MASK 0x1FFu 00344 #define ADC_CLM3_CLM3_SHIFT 0 00345 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK) 00346 /* CLM2 Bit Fields */ 00347 #define ADC_CLM2_CLM2_MASK 0xFFu 00348 #define ADC_CLM2_CLM2_SHIFT 0 00349 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK) 00350 /* CLM1 Bit Fields */ 00351 #define ADC_CLM1_CLM1_MASK 0x7Fu 00352 #define ADC_CLM1_CLM1_SHIFT 0 00353 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK) 00354 /* CLM0 Bit Fields */ 00355 #define ADC_CLM0_CLM0_MASK 0x3Fu 00356 #define ADC_CLM0_CLM0_SHIFT 0 00357 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK) 00358 00359 /*! 00360 * @} 00361 */ /* end of group ADC_Register_Masks */ 00362 00363 00364 /* ADC - Peripheral instance base addresses */ 00365 /** Peripheral ADC0 base address */ 00366 #define ADC0_BASE (0x4003B000u) 00367 /** Peripheral ADC0 base pointer */ 00368 #define ADC0 ((ADC_Type *)ADC0_BASE) 00369 /** Array initializer of ADC peripheral base pointers */ 00370 #define ADC_BASES { ADC0 } 00371 00372 /*! 00373 * @} 00374 */ /* end of group ADC_Peripheral_Access_Layer */ 00375 00376 00377 /* ---------------------------------------------------------------------------- 00378 -- CMP Peripheral Access Layer 00379 ---------------------------------------------------------------------------- */ 00380 00381 /*! 00382 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 00383 * @{ 00384 */ 00385 00386 /** CMP - Register Layout Typedef */ 00387 typedef struct { 00388 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 00389 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 00390 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 00391 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 00392 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 00393 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 00394 } CMP_Type; 00395 00396 /* ---------------------------------------------------------------------------- 00397 -- CMP Register Masks 00398 ---------------------------------------------------------------------------- */ 00399 00400 /*! 00401 * @addtogroup CMP_Register_Masks CMP Register Masks 00402 * @{ 00403 */ 00404 00405 /* CR0 Bit Fields */ 00406 #define CMP_CR0_HYSTCTR_MASK 0x3u 00407 #define CMP_CR0_HYSTCTR_SHIFT 0 00408 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK) 00409 #define CMP_CR0_FILTER_CNT_MASK 0x70u 00410 #define CMP_CR0_FILTER_CNT_SHIFT 4 00411 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK) 00412 /* CR1 Bit Fields */ 00413 #define CMP_CR1_EN_MASK 0x1u 00414 #define CMP_CR1_EN_SHIFT 0 00415 #define CMP_CR1_OPE_MASK 0x2u 00416 #define CMP_CR1_OPE_SHIFT 1 00417 #define CMP_CR1_COS_MASK 0x4u 00418 #define CMP_CR1_COS_SHIFT 2 00419 #define CMP_CR1_INV_MASK 0x8u 00420 #define CMP_CR1_INV_SHIFT 3 00421 #define CMP_CR1_PMODE_MASK 0x10u 00422 #define CMP_CR1_PMODE_SHIFT 4 00423 #define CMP_CR1_TRIGM_MASK 0x20u 00424 #define CMP_CR1_TRIGM_SHIFT 5 00425 #define CMP_CR1_WE_MASK 0x40u 00426 #define CMP_CR1_WE_SHIFT 6 00427 #define CMP_CR1_SE_MASK 0x80u 00428 #define CMP_CR1_SE_SHIFT 7 00429 /* FPR Bit Fields */ 00430 #define CMP_FPR_FILT_PER_MASK 0xFFu 00431 #define CMP_FPR_FILT_PER_SHIFT 0 00432 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK) 00433 /* SCR Bit Fields */ 00434 #define CMP_SCR_COUT_MASK 0x1u 00435 #define CMP_SCR_COUT_SHIFT 0 00436 #define CMP_SCR_CFF_MASK 0x2u 00437 #define CMP_SCR_CFF_SHIFT 1 00438 #define CMP_SCR_CFR_MASK 0x4u 00439 #define CMP_SCR_CFR_SHIFT 2 00440 #define CMP_SCR_IEF_MASK 0x8u 00441 #define CMP_SCR_IEF_SHIFT 3 00442 #define CMP_SCR_IER_MASK 0x10u 00443 #define CMP_SCR_IER_SHIFT 4 00444 #define CMP_SCR_DMAEN_MASK 0x40u 00445 #define CMP_SCR_DMAEN_SHIFT 6 00446 /* DACCR Bit Fields */ 00447 #define CMP_DACCR_VOSEL_MASK 0x3Fu 00448 #define CMP_DACCR_VOSEL_SHIFT 0 00449 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK) 00450 #define CMP_DACCR_VRSEL_MASK 0x40u 00451 #define CMP_DACCR_VRSEL_SHIFT 6 00452 #define CMP_DACCR_DACEN_MASK 0x80u 00453 #define CMP_DACCR_DACEN_SHIFT 7 00454 /* MUXCR Bit Fields */ 00455 #define CMP_MUXCR_MSEL_MASK 0x7u 00456 #define CMP_MUXCR_MSEL_SHIFT 0 00457 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK) 00458 #define CMP_MUXCR_PSEL_MASK 0x38u 00459 #define CMP_MUXCR_PSEL_SHIFT 3 00460 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK) 00461 #define CMP_MUXCR_PSTM_MASK 0x80u 00462 #define CMP_MUXCR_PSTM_SHIFT 7 00463 00464 /*! 00465 * @} 00466 */ /* end of group CMP_Register_Masks */ 00467 00468 00469 /* CMP - Peripheral instance base addresses */ 00470 /** Peripheral CMP0 base address */ 00471 #define CMP0_BASE (0x40073000u) 00472 /** Peripheral CMP0 base pointer */ 00473 #define CMP0 ((CMP_Type *)CMP0_BASE) 00474 /** Array initializer of CMP peripheral base pointers */ 00475 #define CMP_BASES { CMP0 } 00476 00477 /*! 00478 * @} 00479 */ /* end of group CMP_Peripheral_Access_Layer */ 00480 00481 00482 /* ---------------------------------------------------------------------------- 00483 -- DAC Peripheral Access Layer 00484 ---------------------------------------------------------------------------- */ 00485 00486 /*! 00487 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer 00488 * @{ 00489 */ 00490 00491 /** DAC - Register Layout Typedef */ 00492 typedef struct { 00493 struct { /* offset: 0x0, array step: 0x2 */ 00494 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ 00495 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ 00496 } DAT[2]; 00497 uint8_t RESERVED_0[28]; 00498 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ 00499 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ 00500 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ 00501 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ 00502 } DAC_Type; 00503 00504 /* ---------------------------------------------------------------------------- 00505 -- DAC Register Masks 00506 ---------------------------------------------------------------------------- */ 00507 00508 /*! 00509 * @addtogroup DAC_Register_Masks DAC Register Masks 00510 * @{ 00511 */ 00512 00513 /* DATL Bit Fields */ 00514 #define DAC_DATL_DATA0_MASK 0xFFu 00515 #define DAC_DATL_DATA0_SHIFT 0 00516 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK) 00517 /* DATH Bit Fields */ 00518 #define DAC_DATH_DATA1_MASK 0xFu 00519 #define DAC_DATH_DATA1_SHIFT 0 00520 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK) 00521 /* SR Bit Fields */ 00522 #define DAC_SR_DACBFRPBF_MASK 0x1u 00523 #define DAC_SR_DACBFRPBF_SHIFT 0 00524 #define DAC_SR_DACBFRPTF_MASK 0x2u 00525 #define DAC_SR_DACBFRPTF_SHIFT 1 00526 /* C0 Bit Fields */ 00527 #define DAC_C0_DACBBIEN_MASK 0x1u 00528 #define DAC_C0_DACBBIEN_SHIFT 0 00529 #define DAC_C0_DACBTIEN_MASK 0x2u 00530 #define DAC_C0_DACBTIEN_SHIFT 1 00531 #define DAC_C0_LPEN_MASK 0x8u 00532 #define DAC_C0_LPEN_SHIFT 3 00533 #define DAC_C0_DACSWTRG_MASK 0x10u 00534 #define DAC_C0_DACSWTRG_SHIFT 4 00535 #define DAC_C0_DACTRGSEL_MASK 0x20u 00536 #define DAC_C0_DACTRGSEL_SHIFT 5 00537 #define DAC_C0_DACRFS_MASK 0x40u 00538 #define DAC_C0_DACRFS_SHIFT 6 00539 #define DAC_C0_DACEN_MASK 0x80u 00540 #define DAC_C0_DACEN_SHIFT 7 00541 /* C1 Bit Fields */ 00542 #define DAC_C1_DACBFEN_MASK 0x1u 00543 #define DAC_C1_DACBFEN_SHIFT 0 00544 #define DAC_C1_DACBFMD_MASK 0x4u 00545 #define DAC_C1_DACBFMD_SHIFT 2 00546 #define DAC_C1_DMAEN_MASK 0x80u 00547 #define DAC_C1_DMAEN_SHIFT 7 00548 /* C2 Bit Fields */ 00549 #define DAC_C2_DACBFUP_MASK 0x1u 00550 #define DAC_C2_DACBFUP_SHIFT 0 00551 #define DAC_C2_DACBFRP_MASK 0x10u 00552 #define DAC_C2_DACBFRP_SHIFT 4 00553 00554 /*! 00555 * @} 00556 */ /* end of group DAC_Register_Masks */ 00557 00558 00559 /* DAC - Peripheral instance base addresses */ 00560 /** Peripheral DAC0 base address */ 00561 #define DAC0_BASE (0x4003F000u) 00562 /** Peripheral DAC0 base pointer */ 00563 #define DAC0 ((DAC_Type *)DAC0_BASE) 00564 /** Array initializer of DAC peripheral base pointers */ 00565 #define DAC_BASES { DAC0 } 00566 00567 /*! 00568 * @} 00569 */ /* end of group DAC_Peripheral_Access_Layer */ 00570 00571 00572 /* ---------------------------------------------------------------------------- 00573 -- DMA Peripheral Access Layer 00574 ---------------------------------------------------------------------------- */ 00575 00576 /*! 00577 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 00578 * @{ 00579 */ 00580 00581 /** DMA - Register Layout Typedef */ 00582 typedef struct { 00583 uint8_t RESERVED_0[256]; 00584 struct { /* offset: 0x100, array step: 0x10 */ 00585 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ 00586 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ 00587 union { /* offset: 0x108, array step: 0x10 */ 00588 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ 00589 struct { /* offset: 0x108, array step: 0x10 */ 00590 uint8_t RESERVED_0[3]; 00591 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ 00592 } DMA_DSR_ACCESS8BIT; 00593 }; 00594 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ 00595 } DMA[4]; 00596 } DMA_Type; 00597 00598 /* ---------------------------------------------------------------------------- 00599 -- DMA Register Masks 00600 ---------------------------------------------------------------------------- */ 00601 00602 /*! 00603 * @addtogroup DMA_Register_Masks DMA Register Masks 00604 * @{ 00605 */ 00606 00607 /* SAR Bit Fields */ 00608 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu 00609 #define DMA_SAR_SAR_SHIFT 0 00610 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK) 00611 /* DAR Bit Fields */ 00612 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu 00613 #define DMA_DAR_DAR_SHIFT 0 00614 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK) 00615 /* DSR_BCR Bit Fields */ 00616 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu 00617 #define DMA_DSR_BCR_BCR_SHIFT 0 00618 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK) 00619 #define DMA_DSR_BCR_DONE_MASK 0x1000000u 00620 #define DMA_DSR_BCR_DONE_SHIFT 24 00621 #define DMA_DSR_BCR_BSY_MASK 0x2000000u 00622 #define DMA_DSR_BCR_BSY_SHIFT 25 00623 #define DMA_DSR_BCR_REQ_MASK 0x4000000u 00624 #define DMA_DSR_BCR_REQ_SHIFT 26 00625 #define DMA_DSR_BCR_BED_MASK 0x10000000u 00626 #define DMA_DSR_BCR_BED_SHIFT 28 00627 #define DMA_DSR_BCR_BES_MASK 0x20000000u 00628 #define DMA_DSR_BCR_BES_SHIFT 29 00629 #define DMA_DSR_BCR_CE_MASK 0x40000000u 00630 #define DMA_DSR_BCR_CE_SHIFT 30 00631 /* DCR Bit Fields */ 00632 #define DMA_DCR_LCH2_MASK 0x3u 00633 #define DMA_DCR_LCH2_SHIFT 0 00634 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK) 00635 #define DMA_DCR_LCH1_MASK 0xCu 00636 #define DMA_DCR_LCH1_SHIFT 2 00637 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK) 00638 #define DMA_DCR_LINKCC_MASK 0x30u 00639 #define DMA_DCR_LINKCC_SHIFT 4 00640 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK) 00641 #define DMA_DCR_D_REQ_MASK 0x80u 00642 #define DMA_DCR_D_REQ_SHIFT 7 00643 #define DMA_DCR_DMOD_MASK 0xF00u 00644 #define DMA_DCR_DMOD_SHIFT 8 00645 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK) 00646 #define DMA_DCR_SMOD_MASK 0xF000u 00647 #define DMA_DCR_SMOD_SHIFT 12 00648 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK) 00649 #define DMA_DCR_START_MASK 0x10000u 00650 #define DMA_DCR_START_SHIFT 16 00651 #define DMA_DCR_DSIZE_MASK 0x60000u 00652 #define DMA_DCR_DSIZE_SHIFT 17 00653 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK) 00654 #define DMA_DCR_DINC_MASK 0x80000u 00655 #define DMA_DCR_DINC_SHIFT 19 00656 #define DMA_DCR_SSIZE_MASK 0x300000u 00657 #define DMA_DCR_SSIZE_SHIFT 20 00658 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK) 00659 #define DMA_DCR_SINC_MASK 0x400000u 00660 #define DMA_DCR_SINC_SHIFT 22 00661 #define DMA_DCR_EADREQ_MASK 0x800000u 00662 #define DMA_DCR_EADREQ_SHIFT 23 00663 #define DMA_DCR_AA_MASK 0x10000000u 00664 #define DMA_DCR_AA_SHIFT 28 00665 #define DMA_DCR_CS_MASK 0x20000000u 00666 #define DMA_DCR_CS_SHIFT 29 00667 #define DMA_DCR_ERQ_MASK 0x40000000u 00668 #define DMA_DCR_ERQ_SHIFT 30 00669 #define DMA_DCR_EINT_MASK 0x80000000u 00670 #define DMA_DCR_EINT_SHIFT 31 00671 00672 /*! 00673 * @} 00674 */ /* end of group DMA_Register_Masks */ 00675 00676 00677 /* DMA - Peripheral instance base addresses */ 00678 /** Peripheral DMA base address */ 00679 #define DMA_BASE (0x40008000u) 00680 /** Peripheral DMA base pointer */ 00681 #define DMA0 ((DMA_Type *)DMA_BASE) 00682 /** Array initializer of DMA peripheral base pointers */ 00683 #define DMA_BASES { DMA0 } 00684 00685 /*! 00686 * @} 00687 */ /* end of group DMA_Peripheral_Access_Layer */ 00688 00689 00690 /* ---------------------------------------------------------------------------- 00691 -- DMAMUX Peripheral Access Layer 00692 ---------------------------------------------------------------------------- */ 00693 00694 /*! 00695 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 00696 * @{ 00697 */ 00698 00699 /** DMAMUX - Register Layout Typedef */ 00700 typedef struct { 00701 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 00702 } DMAMUX_Type; 00703 00704 /* ---------------------------------------------------------------------------- 00705 -- DMAMUX Register Masks 00706 ---------------------------------------------------------------------------- */ 00707 00708 /*! 00709 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 00710 * @{ 00711 */ 00712 00713 /* CHCFG Bit Fields */ 00714 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu 00715 #define DMAMUX_CHCFG_SOURCE_SHIFT 0 00716 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK) 00717 #define DMAMUX_CHCFG_TRIG_MASK 0x40u 00718 #define DMAMUX_CHCFG_TRIG_SHIFT 6 00719 #define DMAMUX_CHCFG_ENBL_MASK 0x80u 00720 #define DMAMUX_CHCFG_ENBL_SHIFT 7 00721 00722 /*! 00723 * @} 00724 */ /* end of group DMAMUX_Register_Masks */ 00725 00726 00727 /* DMAMUX - Peripheral instance base addresses */ 00728 /** Peripheral DMAMUX0 base address */ 00729 #define DMAMUX0_BASE (0x40021000u) 00730 /** Peripheral DMAMUX0 base pointer */ 00731 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) 00732 /** Array initializer of DMAMUX peripheral base pointers */ 00733 #define DMAMUX_BASES { DMAMUX0 } 00734 00735 /*! 00736 * @} 00737 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 00738 00739 00740 /* ---------------------------------------------------------------------------- 00741 -- FGPIO Peripheral Access Layer 00742 ---------------------------------------------------------------------------- */ 00743 00744 /*! 00745 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 00746 * @{ 00747 */ 00748 00749 /** FGPIO - Register Layout Typedef */ 00750 typedef struct { 00751 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 00752 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 00753 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 00754 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 00755 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 00756 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 00757 } FGPIO_Type; 00758 00759 /* ---------------------------------------------------------------------------- 00760 -- FGPIO Register Masks 00761 ---------------------------------------------------------------------------- */ 00762 00763 /*! 00764 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 00765 * @{ 00766 */ 00767 00768 /* PDOR Bit Fields */ 00769 #define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu 00770 #define FGPIO_PDOR_PDO_SHIFT 0 00771 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK) 00772 /* PSOR Bit Fields */ 00773 #define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu 00774 #define FGPIO_PSOR_PTSO_SHIFT 0 00775 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK) 00776 /* PCOR Bit Fields */ 00777 #define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu 00778 #define FGPIO_PCOR_PTCO_SHIFT 0 00779 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK) 00780 /* PTOR Bit Fields */ 00781 #define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu 00782 #define FGPIO_PTOR_PTTO_SHIFT 0 00783 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK) 00784 /* PDIR Bit Fields */ 00785 #define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu 00786 #define FGPIO_PDIR_PDI_SHIFT 0 00787 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK) 00788 /* PDDR Bit Fields */ 00789 #define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu 00790 #define FGPIO_PDDR_PDD_SHIFT 0 00791 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK) 00792 00793 /*! 00794 * @} 00795 */ /* end of group FGPIO_Register_Masks */ 00796 00797 00798 /* FGPIO - Peripheral instance base addresses */ 00799 /** Peripheral FPTA base address */ 00800 #define FPTA_BASE (0xF80FF000u) 00801 /** Peripheral FPTA base pointer */ 00802 #define FPTA ((FGPIO_Type *)FPTA_BASE) 00803 /** Peripheral FPTB base address */ 00804 #define FPTB_BASE (0xF80FF040u) 00805 /** Peripheral FPTB base pointer */ 00806 #define FPTB ((FGPIO_Type *)FPTB_BASE) 00807 /** Peripheral FPTC base address */ 00808 #define FPTC_BASE (0xF80FF080u) 00809 /** Peripheral FPTC base pointer */ 00810 #define FPTC ((FGPIO_Type *)FPTC_BASE) 00811 /** Peripheral FPTD base address */ 00812 #define FPTD_BASE (0xF80FF0C0u) 00813 /** Peripheral FPTD base pointer */ 00814 #define FPTD ((FGPIO_Type *)FPTD_BASE) 00815 /** Peripheral FPTE base address */ 00816 #define FPTE_BASE (0xF80FF100u) 00817 /** Peripheral FPTE base pointer */ 00818 #define FPTE ((FGPIO_Type *)FPTE_BASE) 00819 /** Array initializer of FGPIO peripheral base pointers */ 00820 #define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE } 00821 00822 /*! 00823 * @} 00824 */ /* end of group FGPIO_Peripheral_Access_Layer */ 00825 00826 00827 /* ---------------------------------------------------------------------------- 00828 -- FTFA Peripheral Access Layer 00829 ---------------------------------------------------------------------------- */ 00830 00831 /*! 00832 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer 00833 * @{ 00834 */ 00835 00836 /** FTFA - Register Layout Typedef */ 00837 typedef struct { 00838 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 00839 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 00840 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 00841 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 00842 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 00843 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 00844 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 00845 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 00846 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 00847 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 00848 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 00849 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 00850 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 00851 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 00852 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 00853 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 00854 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 00855 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 00856 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 00857 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 00858 } FTFA_Type; 00859 00860 /* ---------------------------------------------------------------------------- 00861 -- FTFA Register Masks 00862 ---------------------------------------------------------------------------- */ 00863 00864 /*! 00865 * @addtogroup FTFA_Register_Masks FTFA Register Masks 00866 * @{ 00867 */ 00868 00869 /* FSTAT Bit Fields */ 00870 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u 00871 #define FTFA_FSTAT_MGSTAT0_SHIFT 0 00872 #define FTFA_FSTAT_FPVIOL_MASK 0x10u 00873 #define FTFA_FSTAT_FPVIOL_SHIFT 4 00874 #define FTFA_FSTAT_ACCERR_MASK 0x20u 00875 #define FTFA_FSTAT_ACCERR_SHIFT 5 00876 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u 00877 #define FTFA_FSTAT_RDCOLERR_SHIFT 6 00878 #define FTFA_FSTAT_CCIF_MASK 0x80u 00879 #define FTFA_FSTAT_CCIF_SHIFT 7 00880 /* FCNFG Bit Fields */ 00881 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u 00882 #define FTFA_FCNFG_ERSSUSP_SHIFT 4 00883 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u 00884 #define FTFA_FCNFG_ERSAREQ_SHIFT 5 00885 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u 00886 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6 00887 #define FTFA_FCNFG_CCIE_MASK 0x80u 00888 #define FTFA_FCNFG_CCIE_SHIFT 7 00889 /* FSEC Bit Fields */ 00890 #define FTFA_FSEC_SEC_MASK 0x3u 00891 #define FTFA_FSEC_SEC_SHIFT 0 00892 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK) 00893 #define FTFA_FSEC_FSLACC_MASK 0xCu 00894 #define FTFA_FSEC_FSLACC_SHIFT 2 00895 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK) 00896 #define FTFA_FSEC_MEEN_MASK 0x30u 00897 #define FTFA_FSEC_MEEN_SHIFT 4 00898 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK) 00899 #define FTFA_FSEC_KEYEN_MASK 0xC0u 00900 #define FTFA_FSEC_KEYEN_SHIFT 6 00901 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK) 00902 /* FOPT Bit Fields */ 00903 #define FTFA_FOPT_OPT_MASK 0xFFu 00904 #define FTFA_FOPT_OPT_SHIFT 0 00905 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK) 00906 /* FCCOB3 Bit Fields */ 00907 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu 00908 #define FTFA_FCCOB3_CCOBn_SHIFT 0 00909 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK) 00910 /* FCCOB2 Bit Fields */ 00911 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu 00912 #define FTFA_FCCOB2_CCOBn_SHIFT 0 00913 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK) 00914 /* FCCOB1 Bit Fields */ 00915 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu 00916 #define FTFA_FCCOB1_CCOBn_SHIFT 0 00917 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK) 00918 /* FCCOB0 Bit Fields */ 00919 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu 00920 #define FTFA_FCCOB0_CCOBn_SHIFT 0 00921 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK) 00922 /* FCCOB7 Bit Fields */ 00923 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu 00924 #define FTFA_FCCOB7_CCOBn_SHIFT 0 00925 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK) 00926 /* FCCOB6 Bit Fields */ 00927 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu 00928 #define FTFA_FCCOB6_CCOBn_SHIFT 0 00929 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK) 00930 /* FCCOB5 Bit Fields */ 00931 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu 00932 #define FTFA_FCCOB5_CCOBn_SHIFT 0 00933 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK) 00934 /* FCCOB4 Bit Fields */ 00935 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu 00936 #define FTFA_FCCOB4_CCOBn_SHIFT 0 00937 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK) 00938 /* FCCOBB Bit Fields */ 00939 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu 00940 #define FTFA_FCCOBB_CCOBn_SHIFT 0 00941 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK) 00942 /* FCCOBA Bit Fields */ 00943 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu 00944 #define FTFA_FCCOBA_CCOBn_SHIFT 0 00945 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK) 00946 /* FCCOB9 Bit Fields */ 00947 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu 00948 #define FTFA_FCCOB9_CCOBn_SHIFT 0 00949 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK) 00950 /* FCCOB8 Bit Fields */ 00951 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu 00952 #define FTFA_FCCOB8_CCOBn_SHIFT 0 00953 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK) 00954 /* FPROT3 Bit Fields */ 00955 #define FTFA_FPROT3_PROT_MASK 0xFFu 00956 #define FTFA_FPROT3_PROT_SHIFT 0 00957 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK) 00958 /* FPROT2 Bit Fields */ 00959 #define FTFA_FPROT2_PROT_MASK 0xFFu 00960 #define FTFA_FPROT2_PROT_SHIFT 0 00961 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK) 00962 /* FPROT1 Bit Fields */ 00963 #define FTFA_FPROT1_PROT_MASK 0xFFu 00964 #define FTFA_FPROT1_PROT_SHIFT 0 00965 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK) 00966 /* FPROT0 Bit Fields */ 00967 #define FTFA_FPROT0_PROT_MASK 0xFFu 00968 #define FTFA_FPROT0_PROT_SHIFT 0 00969 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK) 00970 00971 /*! 00972 * @} 00973 */ /* end of group FTFA_Register_Masks */ 00974 00975 00976 /* FTFA - Peripheral instance base addresses */ 00977 /** Peripheral FTFA base address */ 00978 #define FTFA_BASE (0x40020000u) 00979 /** Peripheral FTFA base pointer */ 00980 #define FTFA ((FTFA_Type *)FTFA_BASE) 00981 /** Array initializer of FTFA peripheral base pointers */ 00982 #define FTFA_BASES { FTFA } 00983 00984 /*! 00985 * @} 00986 */ /* end of group FTFA_Peripheral_Access_Layer */ 00987 00988 00989 /* ---------------------------------------------------------------------------- 00990 -- GPIO Peripheral Access Layer 00991 ---------------------------------------------------------------------------- */ 00992 00993 /*! 00994 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 00995 * @{ 00996 */ 00997 00998 /** GPIO - Register Layout Typedef */ 00999 typedef struct { 01000 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 01001 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 01002 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 01003 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 01004 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 01005 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 01006 } GPIO_Type; 01007 01008 /* ---------------------------------------------------------------------------- 01009 -- GPIO Register Masks 01010 ---------------------------------------------------------------------------- */ 01011 01012 /*! 01013 * @addtogroup GPIO_Register_Masks GPIO Register Masks 01014 * @{ 01015 */ 01016 01017 /* PDOR Bit Fields */ 01018 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu 01019 #define GPIO_PDOR_PDO_SHIFT 0 01020 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK) 01021 /* PSOR Bit Fields */ 01022 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu 01023 #define GPIO_PSOR_PTSO_SHIFT 0 01024 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK) 01025 /* PCOR Bit Fields */ 01026 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu 01027 #define GPIO_PCOR_PTCO_SHIFT 0 01028 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK) 01029 /* PTOR Bit Fields */ 01030 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu 01031 #define GPIO_PTOR_PTTO_SHIFT 0 01032 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK) 01033 /* PDIR Bit Fields */ 01034 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu 01035 #define GPIO_PDIR_PDI_SHIFT 0 01036 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK) 01037 /* PDDR Bit Fields */ 01038 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu 01039 #define GPIO_PDDR_PDD_SHIFT 0 01040 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK) 01041 01042 /*! 01043 * @} 01044 */ /* end of group GPIO_Register_Masks */ 01045 01046 01047 /* GPIO - Peripheral instance base addresses */ 01048 /** Peripheral PTA base address */ 01049 #define PTA_BASE (0x400FF000u) 01050 /** Peripheral PTA base pointer */ 01051 #define PTA ((GPIO_Type *)PTA_BASE) 01052 /** Peripheral PTB base address */ 01053 #define PTB_BASE (0x400FF040u) 01054 /** Peripheral PTB base pointer */ 01055 #define PTB ((GPIO_Type *)PTB_BASE) 01056 /** Peripheral PTC base address */ 01057 #define PTC_BASE (0x400FF080u) 01058 /** Peripheral PTC base pointer */ 01059 #define PTC ((GPIO_Type *)PTC_BASE) 01060 /** Peripheral PTD base address */ 01061 #define PTD_BASE (0x400FF0C0u) 01062 /** Peripheral PTD base pointer */ 01063 #define PTD ((GPIO_Type *)PTD_BASE) 01064 /** Peripheral PTE base address */ 01065 #define PTE_BASE (0x400FF100u) 01066 /** Peripheral PTE base pointer */ 01067 #define PTE ((GPIO_Type *)PTE_BASE) 01068 /** Array initializer of GPIO peripheral base pointers */ 01069 #define GPIO_BASES { PTA, PTB, PTC, PTD, PTE } 01070 01071 /*! 01072 * @} 01073 */ /* end of group GPIO_Peripheral_Access_Layer */ 01074 01075 01076 /* ---------------------------------------------------------------------------- 01077 -- I2C Peripheral Access Layer 01078 ---------------------------------------------------------------------------- */ 01079 01080 /*! 01081 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 01082 * @{ 01083 */ 01084 01085 /** I2C - Register Layout Typedef */ 01086 typedef struct { 01087 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 01088 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 01089 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 01090 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 01091 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 01092 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 01093 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */ 01094 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 01095 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 01096 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 01097 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 01098 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 01099 } I2C_Type; 01100 01101 /* ---------------------------------------------------------------------------- 01102 -- I2C Register Masks 01103 ---------------------------------------------------------------------------- */ 01104 01105 /*! 01106 * @addtogroup I2C_Register_Masks I2C Register Masks 01107 * @{ 01108 */ 01109 01110 /* A1 Bit Fields */ 01111 #define I2C_A1_AD_MASK 0xFEu 01112 #define I2C_A1_AD_SHIFT 1 01113 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK) 01114 /* F Bit Fields */ 01115 #define I2C_F_ICR_MASK 0x3Fu 01116 #define I2C_F_ICR_SHIFT 0 01117 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK) 01118 #define I2C_F_MULT_MASK 0xC0u 01119 #define I2C_F_MULT_SHIFT 6 01120 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK) 01121 /* C1 Bit Fields */ 01122 #define I2C_C1_DMAEN_MASK 0x1u 01123 #define I2C_C1_DMAEN_SHIFT 0 01124 #define I2C_C1_WUEN_MASK 0x2u 01125 #define I2C_C1_WUEN_SHIFT 1 01126 #define I2C_C1_RSTA_MASK 0x4u 01127 #define I2C_C1_RSTA_SHIFT 2 01128 #define I2C_C1_TXAK_MASK 0x8u 01129 #define I2C_C1_TXAK_SHIFT 3 01130 #define I2C_C1_TX_MASK 0x10u 01131 #define I2C_C1_TX_SHIFT 4 01132 #define I2C_C1_MST_MASK 0x20u 01133 #define I2C_C1_MST_SHIFT 5 01134 #define I2C_C1_IICIE_MASK 0x40u 01135 #define I2C_C1_IICIE_SHIFT 6 01136 #define I2C_C1_IICEN_MASK 0x80u 01137 #define I2C_C1_IICEN_SHIFT 7 01138 /* S Bit Fields */ 01139 #define I2C_S_RXAK_MASK 0x1u 01140 #define I2C_S_RXAK_SHIFT 0 01141 #define I2C_S_IICIF_MASK 0x2u 01142 #define I2C_S_IICIF_SHIFT 1 01143 #define I2C_S_SRW_MASK 0x4u 01144 #define I2C_S_SRW_SHIFT 2 01145 #define I2C_S_RAM_MASK 0x8u 01146 #define I2C_S_RAM_SHIFT 3 01147 #define I2C_S_ARBL_MASK 0x10u 01148 #define I2C_S_ARBL_SHIFT 4 01149 #define I2C_S_BUSY_MASK 0x20u 01150 #define I2C_S_BUSY_SHIFT 5 01151 #define I2C_S_IAAS_MASK 0x40u 01152 #define I2C_S_IAAS_SHIFT 6 01153 #define I2C_S_TCF_MASK 0x80u 01154 #define I2C_S_TCF_SHIFT 7 01155 /* D Bit Fields */ 01156 #define I2C_D_DATA_MASK 0xFFu 01157 #define I2C_D_DATA_SHIFT 0 01158 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK) 01159 /* C2 Bit Fields */ 01160 #define I2C_C2_AD_MASK 0x7u 01161 #define I2C_C2_AD_SHIFT 0 01162 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK) 01163 #define I2C_C2_RMEN_MASK 0x8u 01164 #define I2C_C2_RMEN_SHIFT 3 01165 #define I2C_C2_SBRC_MASK 0x10u 01166 #define I2C_C2_SBRC_SHIFT 4 01167 #define I2C_C2_HDRS_MASK 0x20u 01168 #define I2C_C2_HDRS_SHIFT 5 01169 #define I2C_C2_ADEXT_MASK 0x40u 01170 #define I2C_C2_ADEXT_SHIFT 6 01171 #define I2C_C2_GCAEN_MASK 0x80u 01172 #define I2C_C2_GCAEN_SHIFT 7 01173 /* FLT Bit Fields */ 01174 #define I2C_FLT_FLT_MASK 0x1Fu 01175 #define I2C_FLT_FLT_SHIFT 0 01176 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK) 01177 #define I2C_FLT_STOPIE_MASK 0x20u 01178 #define I2C_FLT_STOPIE_SHIFT 5 01179 #define I2C_FLT_STOPF_MASK 0x40u 01180 #define I2C_FLT_STOPF_SHIFT 6 01181 #define I2C_FLT_SHEN_MASK 0x80u 01182 #define I2C_FLT_SHEN_SHIFT 7 01183 /* RA Bit Fields */ 01184 #define I2C_RA_RAD_MASK 0xFEu 01185 #define I2C_RA_RAD_SHIFT 1 01186 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK) 01187 /* SMB Bit Fields */ 01188 #define I2C_SMB_SHTF2IE_MASK 0x1u 01189 #define I2C_SMB_SHTF2IE_SHIFT 0 01190 #define I2C_SMB_SHTF2_MASK 0x2u 01191 #define I2C_SMB_SHTF2_SHIFT 1 01192 #define I2C_SMB_SHTF1_MASK 0x4u 01193 #define I2C_SMB_SHTF1_SHIFT 2 01194 #define I2C_SMB_SLTF_MASK 0x8u 01195 #define I2C_SMB_SLTF_SHIFT 3 01196 #define I2C_SMB_TCKSEL_MASK 0x10u 01197 #define I2C_SMB_TCKSEL_SHIFT 4 01198 #define I2C_SMB_SIICAEN_MASK 0x20u 01199 #define I2C_SMB_SIICAEN_SHIFT 5 01200 #define I2C_SMB_ALERTEN_MASK 0x40u 01201 #define I2C_SMB_ALERTEN_SHIFT 6 01202 #define I2C_SMB_FACK_MASK 0x80u 01203 #define I2C_SMB_FACK_SHIFT 7 01204 /* A2 Bit Fields */ 01205 #define I2C_A2_SAD_MASK 0xFEu 01206 #define I2C_A2_SAD_SHIFT 1 01207 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK) 01208 /* SLTH Bit Fields */ 01209 #define I2C_SLTH_SSLT_MASK 0xFFu 01210 #define I2C_SLTH_SSLT_SHIFT 0 01211 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK) 01212 /* SLTL Bit Fields */ 01213 #define I2C_SLTL_SSLT_MASK 0xFFu 01214 #define I2C_SLTL_SSLT_SHIFT 0 01215 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK) 01216 01217 /*! 01218 * @} 01219 */ /* end of group I2C_Register_Masks */ 01220 01221 01222 /* I2C - Peripheral instance base addresses */ 01223 /** Peripheral I2C0 base address */ 01224 #define I2C0_BASE (0x40066000u) 01225 /** Peripheral I2C0 base pointer */ 01226 #define I2C0 ((I2C_Type *)I2C0_BASE) 01227 /** Peripheral I2C1 base address */ 01228 #define I2C1_BASE (0x40067000u) 01229 /** Peripheral I2C1 base pointer */ 01230 #define I2C1 ((I2C_Type *)I2C1_BASE) 01231 /** Array initializer of I2C peripheral base pointers */ 01232 #define I2C_BASES { I2C0, I2C1 } 01233 01234 /*! 01235 * @} 01236 */ /* end of group I2C_Peripheral_Access_Layer */ 01237 01238 01239 /* ---------------------------------------------------------------------------- 01240 -- I2S Peripheral Access Layer 01241 ---------------------------------------------------------------------------- */ 01242 01243 /*! 01244 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer 01245 * @{ 01246 */ 01247 01248 /** I2S - Register Layout Typedef */ 01249 typedef struct { 01250 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */ 01251 uint8_t RESERVED_0[4]; 01252 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */ 01253 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */ 01254 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */ 01255 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */ 01256 uint8_t RESERVED_1[8]; 01257 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ 01258 uint8_t RESERVED_2[60]; 01259 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ 01260 uint8_t RESERVED_3[28]; 01261 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */ 01262 uint8_t RESERVED_4[4]; 01263 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */ 01264 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */ 01265 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */ 01266 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */ 01267 uint8_t RESERVED_5[8]; 01268 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ 01269 uint8_t RESERVED_6[60]; 01270 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ 01271 uint8_t RESERVED_7[28]; 01272 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */ 01273 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */ 01274 } I2S_Type; 01275 01276 /* ---------------------------------------------------------------------------- 01277 -- I2S Register Masks 01278 ---------------------------------------------------------------------------- */ 01279 01280 /*! 01281 * @addtogroup I2S_Register_Masks I2S Register Masks 01282 * @{ 01283 */ 01284 01285 /* TCSR Bit Fields */ 01286 #define I2S_TCSR_FWDE_MASK 0x2u 01287 #define I2S_TCSR_FWDE_SHIFT 1 01288 #define I2S_TCSR_FWIE_MASK 0x200u 01289 #define I2S_TCSR_FWIE_SHIFT 9 01290 #define I2S_TCSR_FEIE_MASK 0x400u 01291 #define I2S_TCSR_FEIE_SHIFT 10 01292 #define I2S_TCSR_SEIE_MASK 0x800u 01293 #define I2S_TCSR_SEIE_SHIFT 11 01294 #define I2S_TCSR_WSIE_MASK 0x1000u 01295 #define I2S_TCSR_WSIE_SHIFT 12 01296 #define I2S_TCSR_FWF_MASK 0x20000u 01297 #define I2S_TCSR_FWF_SHIFT 17 01298 #define I2S_TCSR_FEF_MASK 0x40000u 01299 #define I2S_TCSR_FEF_SHIFT 18 01300 #define I2S_TCSR_SEF_MASK 0x80000u 01301 #define I2S_TCSR_SEF_SHIFT 19 01302 #define I2S_TCSR_WSF_MASK 0x100000u 01303 #define I2S_TCSR_WSF_SHIFT 20 01304 #define I2S_TCSR_SR_MASK 0x1000000u 01305 #define I2S_TCSR_SR_SHIFT 24 01306 #define I2S_TCSR_FR_MASK 0x2000000u 01307 #define I2S_TCSR_FR_SHIFT 25 01308 #define I2S_TCSR_BCE_MASK 0x10000000u 01309 #define I2S_TCSR_BCE_SHIFT 28 01310 #define I2S_TCSR_DBGE_MASK 0x20000000u 01311 #define I2S_TCSR_DBGE_SHIFT 29 01312 #define I2S_TCSR_STOPE_MASK 0x40000000u 01313 #define I2S_TCSR_STOPE_SHIFT 30 01314 #define I2S_TCSR_TE_MASK 0x80000000u 01315 #define I2S_TCSR_TE_SHIFT 31 01316 /* TCR2 Bit Fields */ 01317 #define I2S_TCR2_DIV_MASK 0xFFu 01318 #define I2S_TCR2_DIV_SHIFT 0 01319 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK) 01320 #define I2S_TCR2_BCD_MASK 0x1000000u 01321 #define I2S_TCR2_BCD_SHIFT 24 01322 #define I2S_TCR2_BCP_MASK 0x2000000u 01323 #define I2S_TCR2_BCP_SHIFT 25 01324 #define I2S_TCR2_CLKMODE_MASK 0xC000000u 01325 #define I2S_TCR2_CLKMODE_SHIFT 26 01326 #define I2S_TCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_CLKMODE_SHIFT))&I2S_TCR2_CLKMODE_MASK) 01327 /* TCR3 Bit Fields */ 01328 #define I2S_TCR3_WDFL_MASK 0x1u 01329 #define I2S_TCR3_WDFL_SHIFT 0 01330 #define I2S_TCR3_TCE_MASK 0x10000u 01331 #define I2S_TCR3_TCE_SHIFT 16 01332 /* TCR4 Bit Fields */ 01333 #define I2S_TCR4_FSD_MASK 0x1u 01334 #define I2S_TCR4_FSD_SHIFT 0 01335 #define I2S_TCR4_FSP_MASK 0x2u 01336 #define I2S_TCR4_FSP_SHIFT 1 01337 #define I2S_TCR4_FSE_MASK 0x8u 01338 #define I2S_TCR4_FSE_SHIFT 3 01339 #define I2S_TCR4_MF_MASK 0x10u 01340 #define I2S_TCR4_MF_SHIFT 4 01341 #define I2S_TCR4_SYWD_MASK 0x1F00u 01342 #define I2S_TCR4_SYWD_SHIFT 8 01343 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK) 01344 #define I2S_TCR4_FRSZ_MASK 0x10000u 01345 #define I2S_TCR4_FRSZ_SHIFT 16 01346 /* TCR5 Bit Fields */ 01347 #define I2S_TCR5_FBT_MASK 0x1F00u 01348 #define I2S_TCR5_FBT_SHIFT 8 01349 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK) 01350 #define I2S_TCR5_W0W_MASK 0x1F0000u 01351 #define I2S_TCR5_W0W_SHIFT 16 01352 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK) 01353 #define I2S_TCR5_WNW_MASK 0x1F000000u 01354 #define I2S_TCR5_WNW_SHIFT 24 01355 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK) 01356 /* TDR Bit Fields */ 01357 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu 01358 #define I2S_TDR_TDR_SHIFT 0 01359 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK) 01360 /* TMR Bit Fields */ 01361 #define I2S_TMR_TWM_MASK 0x3u 01362 #define I2S_TMR_TWM_SHIFT 0 01363 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK) 01364 /* RCSR Bit Fields */ 01365 #define I2S_RCSR_FWDE_MASK 0x2u 01366 #define I2S_RCSR_FWDE_SHIFT 1 01367 #define I2S_RCSR_FWIE_MASK 0x200u 01368 #define I2S_RCSR_FWIE_SHIFT 9 01369 #define I2S_RCSR_FEIE_MASK 0x400u 01370 #define I2S_RCSR_FEIE_SHIFT 10 01371 #define I2S_RCSR_SEIE_MASK 0x800u 01372 #define I2S_RCSR_SEIE_SHIFT 11 01373 #define I2S_RCSR_WSIE_MASK 0x1000u 01374 #define I2S_RCSR_WSIE_SHIFT 12 01375 #define I2S_RCSR_FWF_MASK 0x20000u 01376 #define I2S_RCSR_FWF_SHIFT 17 01377 #define I2S_RCSR_FEF_MASK 0x40000u 01378 #define I2S_RCSR_FEF_SHIFT 18 01379 #define I2S_RCSR_SEF_MASK 0x80000u 01380 #define I2S_RCSR_SEF_SHIFT 19 01381 #define I2S_RCSR_WSF_MASK 0x100000u 01382 #define I2S_RCSR_WSF_SHIFT 20 01383 #define I2S_RCSR_SR_MASK 0x1000000u 01384 #define I2S_RCSR_SR_SHIFT 24 01385 #define I2S_RCSR_FR_MASK 0x2000000u 01386 #define I2S_RCSR_FR_SHIFT 25 01387 #define I2S_RCSR_BCE_MASK 0x10000000u 01388 #define I2S_RCSR_BCE_SHIFT 28 01389 #define I2S_RCSR_DBGE_MASK 0x20000000u 01390 #define I2S_RCSR_DBGE_SHIFT 29 01391 #define I2S_RCSR_STOPE_MASK 0x40000000u 01392 #define I2S_RCSR_STOPE_SHIFT 30 01393 #define I2S_RCSR_RE_MASK 0x80000000u 01394 #define I2S_RCSR_RE_SHIFT 31 01395 /* RCR2 Bit Fields */ 01396 #define I2S_RCR2_DIV_MASK 0xFFu 01397 #define I2S_RCR2_DIV_SHIFT 0 01398 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK) 01399 #define I2S_RCR2_BCD_MASK 0x1000000u 01400 #define I2S_RCR2_BCD_SHIFT 24 01401 #define I2S_RCR2_BCP_MASK 0x2000000u 01402 #define I2S_RCR2_BCP_SHIFT 25 01403 #define I2S_RCR2_CLKMODE_MASK 0xC000000u 01404 #define I2S_RCR2_CLKMODE_SHIFT 26 01405 #define I2S_RCR2_CLKMODE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_CLKMODE_SHIFT))&I2S_RCR2_CLKMODE_MASK) 01406 /* RCR3 Bit Fields */ 01407 #define I2S_RCR3_WDFL_MASK 0x1u 01408 #define I2S_RCR3_WDFL_SHIFT 0 01409 #define I2S_RCR3_RCE_MASK 0x10000u 01410 #define I2S_RCR3_RCE_SHIFT 16 01411 /* RCR4 Bit Fields */ 01412 #define I2S_RCR4_FSD_MASK 0x1u 01413 #define I2S_RCR4_FSD_SHIFT 0 01414 #define I2S_RCR4_FSP_MASK 0x2u 01415 #define I2S_RCR4_FSP_SHIFT 1 01416 #define I2S_RCR4_FSE_MASK 0x8u 01417 #define I2S_RCR4_FSE_SHIFT 3 01418 #define I2S_RCR4_MF_MASK 0x10u 01419 #define I2S_RCR4_MF_SHIFT 4 01420 #define I2S_RCR4_SYWD_MASK 0x1F00u 01421 #define I2S_RCR4_SYWD_SHIFT 8 01422 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK) 01423 #define I2S_RCR4_FRSZ_MASK 0x10000u 01424 #define I2S_RCR4_FRSZ_SHIFT 16 01425 /* RCR5 Bit Fields */ 01426 #define I2S_RCR5_FBT_MASK 0x1F00u 01427 #define I2S_RCR5_FBT_SHIFT 8 01428 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK) 01429 #define I2S_RCR5_W0W_MASK 0x1F0000u 01430 #define I2S_RCR5_W0W_SHIFT 16 01431 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK) 01432 #define I2S_RCR5_WNW_MASK 0x1F000000u 01433 #define I2S_RCR5_WNW_SHIFT 24 01434 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK) 01435 /* RDR Bit Fields */ 01436 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu 01437 #define I2S_RDR_RDR_SHIFT 0 01438 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK) 01439 /* RMR Bit Fields */ 01440 #define I2S_RMR_RWM_MASK 0x3u 01441 #define I2S_RMR_RWM_SHIFT 0 01442 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK) 01443 /* MCR Bit Fields */ 01444 #define I2S_MCR_MICS_MASK 0x3000000u 01445 #define I2S_MCR_MICS_SHIFT 24 01446 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK) 01447 #define I2S_MCR_MOE_MASK 0x40000000u 01448 #define I2S_MCR_MOE_SHIFT 30 01449 #define I2S_MCR_DUF_MASK 0x80000000u 01450 #define I2S_MCR_DUF_SHIFT 31 01451 /* MDR Bit Fields */ 01452 #define I2S_MDR_DIVIDE_MASK 0xFFFu 01453 #define I2S_MDR_DIVIDE_SHIFT 0 01454 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK) 01455 #define I2S_MDR_FRACT_MASK 0xFF000u 01456 #define I2S_MDR_FRACT_SHIFT 12 01457 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK) 01458 01459 /*! 01460 * @} 01461 */ /* end of group I2S_Register_Masks */ 01462 01463 01464 /* I2S - Peripheral instance base addresses */ 01465 /** Peripheral I2S0 base address */ 01466 #define I2S0_BASE (0x4002F000u) 01467 /** Peripheral I2S0 base pointer */ 01468 #define I2S0 ((I2S_Type *)I2S0_BASE) 01469 /** Array initializer of I2S peripheral base pointers */ 01470 #define I2S_BASES { I2S0 } 01471 01472 /*! 01473 * @} 01474 */ /* end of group I2S_Peripheral_Access_Layer */ 01475 01476 01477 /* ---------------------------------------------------------------------------- 01478 -- LCD Peripheral Access Layer 01479 ---------------------------------------------------------------------------- */ 01480 01481 /*! 01482 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer 01483 * @{ 01484 */ 01485 01486 /** LCD - Register Layout Typedef */ 01487 typedef struct { 01488 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */ 01489 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */ 01490 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */ 01491 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */ 01492 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */ 01493 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */ 01494 union { /* offset: 0x20 */ 01495 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */ 01496 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */ 01497 }; 01498 } LCD_Type; 01499 01500 /* ---------------------------------------------------------------------------- 01501 -- LCD Register Masks 01502 ---------------------------------------------------------------------------- */ 01503 01504 /*! 01505 * @addtogroup LCD_Register_Masks LCD Register Masks 01506 * @{ 01507 */ 01508 01509 /* GCR Bit Fields */ 01510 #define LCD_GCR_DUTY_MASK 0x7u 01511 #define LCD_GCR_DUTY_SHIFT 0 01512 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK) 01513 #define LCD_GCR_LCLK_MASK 0x38u 01514 #define LCD_GCR_LCLK_SHIFT 3 01515 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK) 01516 #define LCD_GCR_SOURCE_MASK 0x40u 01517 #define LCD_GCR_SOURCE_SHIFT 6 01518 #define LCD_GCR_LCDEN_MASK 0x80u 01519 #define LCD_GCR_LCDEN_SHIFT 7 01520 #define LCD_GCR_LCDSTP_MASK 0x100u 01521 #define LCD_GCR_LCDSTP_SHIFT 8 01522 #define LCD_GCR_LCDDOZE_MASK 0x200u 01523 #define LCD_GCR_LCDDOZE_SHIFT 9 01524 #define LCD_GCR_FFR_MASK 0x400u 01525 #define LCD_GCR_FFR_SHIFT 10 01526 #define LCD_GCR_ALTSOURCE_MASK 0x800u 01527 #define LCD_GCR_ALTSOURCE_SHIFT 11 01528 #define LCD_GCR_ALTDIV_MASK 0x3000u 01529 #define LCD_GCR_ALTDIV_SHIFT 12 01530 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK) 01531 #define LCD_GCR_FDCIEN_MASK 0x4000u 01532 #define LCD_GCR_FDCIEN_SHIFT 14 01533 #define LCD_GCR_PADSAFE_MASK 0x8000u 01534 #define LCD_GCR_PADSAFE_SHIFT 15 01535 #define LCD_GCR_VSUPPLY_MASK 0x20000u 01536 #define LCD_GCR_VSUPPLY_SHIFT 17 01537 #define LCD_GCR_LADJ_MASK 0x300000u 01538 #define LCD_GCR_LADJ_SHIFT 20 01539 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK) 01540 #define LCD_GCR_CPSEL_MASK 0x800000u 01541 #define LCD_GCR_CPSEL_SHIFT 23 01542 #define LCD_GCR_RVTRIM_MASK 0xF000000u 01543 #define LCD_GCR_RVTRIM_SHIFT 24 01544 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK) 01545 #define LCD_GCR_RVEN_MASK 0x80000000u 01546 #define LCD_GCR_RVEN_SHIFT 31 01547 /* AR Bit Fields */ 01548 #define LCD_AR_BRATE_MASK 0x7u 01549 #define LCD_AR_BRATE_SHIFT 0 01550 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK) 01551 #define LCD_AR_BMODE_MASK 0x8u 01552 #define LCD_AR_BMODE_SHIFT 3 01553 #define LCD_AR_BLANK_MASK 0x20u 01554 #define LCD_AR_BLANK_SHIFT 5 01555 #define LCD_AR_ALT_MASK 0x40u 01556 #define LCD_AR_ALT_SHIFT 6 01557 #define LCD_AR_BLINK_MASK 0x80u 01558 #define LCD_AR_BLINK_SHIFT 7 01559 /* FDCR Bit Fields */ 01560 #define LCD_FDCR_FDPINID_MASK 0x3Fu 01561 #define LCD_FDCR_FDPINID_SHIFT 0 01562 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK) 01563 #define LCD_FDCR_FDBPEN_MASK 0x40u 01564 #define LCD_FDCR_FDBPEN_SHIFT 6 01565 #define LCD_FDCR_FDEN_MASK 0x80u 01566 #define LCD_FDCR_FDEN_SHIFT 7 01567 #define LCD_FDCR_FDSWW_MASK 0xE00u 01568 #define LCD_FDCR_FDSWW_SHIFT 9 01569 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK) 01570 #define LCD_FDCR_FDPRS_MASK 0x7000u 01571 #define LCD_FDCR_FDPRS_SHIFT 12 01572 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK) 01573 /* FDSR Bit Fields */ 01574 #define LCD_FDSR_FDCNT_MASK 0xFFu 01575 #define LCD_FDSR_FDCNT_SHIFT 0 01576 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK) 01577 #define LCD_FDSR_FDCF_MASK 0x8000u 01578 #define LCD_FDSR_FDCF_SHIFT 15 01579 /* PEN Bit Fields */ 01580 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu 01581 #define LCD_PEN_PEN_SHIFT 0 01582 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK) 01583 /* BPEN Bit Fields */ 01584 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu 01585 #define LCD_BPEN_BPEN_SHIFT 0 01586 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK) 01587 /* WF Bit Fields */ 01588 #define LCD_WF_WF0_MASK 0xFFu 01589 #define LCD_WF_WF0_SHIFT 0 01590 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK) 01591 #define LCD_WF_WF60_MASK 0xFFu 01592 #define LCD_WF_WF60_SHIFT 0 01593 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK) 01594 #define LCD_WF_WF56_MASK 0xFFu 01595 #define LCD_WF_WF56_SHIFT 0 01596 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK) 01597 #define LCD_WF_WF52_MASK 0xFFu 01598 #define LCD_WF_WF52_SHIFT 0 01599 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK) 01600 #define LCD_WF_WF4_MASK 0xFFu 01601 #define LCD_WF_WF4_SHIFT 0 01602 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK) 01603 #define LCD_WF_WF48_MASK 0xFFu 01604 #define LCD_WF_WF48_SHIFT 0 01605 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK) 01606 #define LCD_WF_WF44_MASK 0xFFu 01607 #define LCD_WF_WF44_SHIFT 0 01608 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK) 01609 #define LCD_WF_WF40_MASK 0xFFu 01610 #define LCD_WF_WF40_SHIFT 0 01611 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK) 01612 #define LCD_WF_WF8_MASK 0xFFu 01613 #define LCD_WF_WF8_SHIFT 0 01614 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK) 01615 #define LCD_WF_WF36_MASK 0xFFu 01616 #define LCD_WF_WF36_SHIFT 0 01617 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK) 01618 #define LCD_WF_WF32_MASK 0xFFu 01619 #define LCD_WF_WF32_SHIFT 0 01620 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK) 01621 #define LCD_WF_WF28_MASK 0xFFu 01622 #define LCD_WF_WF28_SHIFT 0 01623 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK) 01624 #define LCD_WF_WF12_MASK 0xFFu 01625 #define LCD_WF_WF12_SHIFT 0 01626 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK) 01627 #define LCD_WF_WF24_MASK 0xFFu 01628 #define LCD_WF_WF24_SHIFT 0 01629 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK) 01630 #define LCD_WF_WF20_MASK 0xFFu 01631 #define LCD_WF_WF20_SHIFT 0 01632 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK) 01633 #define LCD_WF_WF16_MASK 0xFFu 01634 #define LCD_WF_WF16_SHIFT 0 01635 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK) 01636 #define LCD_WF_WF5_MASK 0xFF00u 01637 #define LCD_WF_WF5_SHIFT 8 01638 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK) 01639 #define LCD_WF_WF49_MASK 0xFF00u 01640 #define LCD_WF_WF49_SHIFT 8 01641 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK) 01642 #define LCD_WF_WF45_MASK 0xFF00u 01643 #define LCD_WF_WF45_SHIFT 8 01644 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK) 01645 #define LCD_WF_WF61_MASK 0xFF00u 01646 #define LCD_WF_WF61_SHIFT 8 01647 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK) 01648 #define LCD_WF_WF25_MASK 0xFF00u 01649 #define LCD_WF_WF25_SHIFT 8 01650 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK) 01651 #define LCD_WF_WF17_MASK 0xFF00u 01652 #define LCD_WF_WF17_SHIFT 8 01653 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK) 01654 #define LCD_WF_WF41_MASK 0xFF00u 01655 #define LCD_WF_WF41_SHIFT 8 01656 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK) 01657 #define LCD_WF_WF13_MASK 0xFF00u 01658 #define LCD_WF_WF13_SHIFT 8 01659 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK) 01660 #define LCD_WF_WF57_MASK 0xFF00u 01661 #define LCD_WF_WF57_SHIFT 8 01662 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK) 01663 #define LCD_WF_WF53_MASK 0xFF00u 01664 #define LCD_WF_WF53_SHIFT 8 01665 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK) 01666 #define LCD_WF_WF37_MASK 0xFF00u 01667 #define LCD_WF_WF37_SHIFT 8 01668 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK) 01669 #define LCD_WF_WF9_MASK 0xFF00u 01670 #define LCD_WF_WF9_SHIFT 8 01671 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK) 01672 #define LCD_WF_WF1_MASK 0xFF00u 01673 #define LCD_WF_WF1_SHIFT 8 01674 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK) 01675 #define LCD_WF_WF29_MASK 0xFF00u 01676 #define LCD_WF_WF29_SHIFT 8 01677 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK) 01678 #define LCD_WF_WF33_MASK 0xFF00u 01679 #define LCD_WF_WF33_SHIFT 8 01680 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK) 01681 #define LCD_WF_WF21_MASK 0xFF00u 01682 #define LCD_WF_WF21_SHIFT 8 01683 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK) 01684 #define LCD_WF_WF26_MASK 0xFF0000u 01685 #define LCD_WF_WF26_SHIFT 16 01686 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK) 01687 #define LCD_WF_WF46_MASK 0xFF0000u 01688 #define LCD_WF_WF46_SHIFT 16 01689 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK) 01690 #define LCD_WF_WF6_MASK 0xFF0000u 01691 #define LCD_WF_WF6_SHIFT 16 01692 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK) 01693 #define LCD_WF_WF42_MASK 0xFF0000u 01694 #define LCD_WF_WF42_SHIFT 16 01695 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK) 01696 #define LCD_WF_WF18_MASK 0xFF0000u 01697 #define LCD_WF_WF18_SHIFT 16 01698 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK) 01699 #define LCD_WF_WF38_MASK 0xFF0000u 01700 #define LCD_WF_WF38_SHIFT 16 01701 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK) 01702 #define LCD_WF_WF22_MASK 0xFF0000u 01703 #define LCD_WF_WF22_SHIFT 16 01704 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK) 01705 #define LCD_WF_WF34_MASK 0xFF0000u 01706 #define LCD_WF_WF34_SHIFT 16 01707 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK) 01708 #define LCD_WF_WF50_MASK 0xFF0000u 01709 #define LCD_WF_WF50_SHIFT 16 01710 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK) 01711 #define LCD_WF_WF14_MASK 0xFF0000u 01712 #define LCD_WF_WF14_SHIFT 16 01713 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK) 01714 #define LCD_WF_WF54_MASK 0xFF0000u 01715 #define LCD_WF_WF54_SHIFT 16 01716 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK) 01717 #define LCD_WF_WF2_MASK 0xFF0000u 01718 #define LCD_WF_WF2_SHIFT 16 01719 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK) 01720 #define LCD_WF_WF58_MASK 0xFF0000u 01721 #define LCD_WF_WF58_SHIFT 16 01722 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK) 01723 #define LCD_WF_WF30_MASK 0xFF0000u 01724 #define LCD_WF_WF30_SHIFT 16 01725 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK) 01726 #define LCD_WF_WF62_MASK 0xFF0000u 01727 #define LCD_WF_WF62_SHIFT 16 01728 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK) 01729 #define LCD_WF_WF10_MASK 0xFF0000u 01730 #define LCD_WF_WF10_SHIFT 16 01731 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK) 01732 #define LCD_WF_WF63_MASK 0xFF000000u 01733 #define LCD_WF_WF63_SHIFT 24 01734 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK) 01735 #define LCD_WF_WF59_MASK 0xFF000000u 01736 #define LCD_WF_WF59_SHIFT 24 01737 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK) 01738 #define LCD_WF_WF55_MASK 0xFF000000u 01739 #define LCD_WF_WF55_SHIFT 24 01740 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK) 01741 #define LCD_WF_WF3_MASK 0xFF000000u 01742 #define LCD_WF_WF3_SHIFT 24 01743 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK) 01744 #define LCD_WF_WF51_MASK 0xFF000000u 01745 #define LCD_WF_WF51_SHIFT 24 01746 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK) 01747 #define LCD_WF_WF47_MASK 0xFF000000u 01748 #define LCD_WF_WF47_SHIFT 24 01749 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK) 01750 #define LCD_WF_WF43_MASK 0xFF000000u 01751 #define LCD_WF_WF43_SHIFT 24 01752 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK) 01753 #define LCD_WF_WF7_MASK 0xFF000000u 01754 #define LCD_WF_WF7_SHIFT 24 01755 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK) 01756 #define LCD_WF_WF39_MASK 0xFF000000u 01757 #define LCD_WF_WF39_SHIFT 24 01758 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK) 01759 #define LCD_WF_WF35_MASK 0xFF000000u 01760 #define LCD_WF_WF35_SHIFT 24 01761 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK) 01762 #define LCD_WF_WF31_MASK 0xFF000000u 01763 #define LCD_WF_WF31_SHIFT 24 01764 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK) 01765 #define LCD_WF_WF11_MASK 0xFF000000u 01766 #define LCD_WF_WF11_SHIFT 24 01767 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK) 01768 #define LCD_WF_WF27_MASK 0xFF000000u 01769 #define LCD_WF_WF27_SHIFT 24 01770 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK) 01771 #define LCD_WF_WF23_MASK 0xFF000000u 01772 #define LCD_WF_WF23_SHIFT 24 01773 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK) 01774 #define LCD_WF_WF19_MASK 0xFF000000u 01775 #define LCD_WF_WF19_SHIFT 24 01776 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK) 01777 #define LCD_WF_WF15_MASK 0xFF000000u 01778 #define LCD_WF_WF15_SHIFT 24 01779 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK) 01780 /* WF8B Bit Fields */ 01781 #define LCD_WF8B_BPALCD0_MASK 0x1u 01782 #define LCD_WF8B_BPALCD0_SHIFT 0 01783 #define LCD_WF8B_BPALCD63_MASK 0x1u 01784 #define LCD_WF8B_BPALCD63_SHIFT 0 01785 #define LCD_WF8B_BPALCD62_MASK 0x1u 01786 #define LCD_WF8B_BPALCD62_SHIFT 0 01787 #define LCD_WF8B_BPALCD61_MASK 0x1u 01788 #define LCD_WF8B_BPALCD61_SHIFT 0 01789 #define LCD_WF8B_BPALCD60_MASK 0x1u 01790 #define LCD_WF8B_BPALCD60_SHIFT 0 01791 #define LCD_WF8B_BPALCD59_MASK 0x1u 01792 #define LCD_WF8B_BPALCD59_SHIFT 0 01793 #define LCD_WF8B_BPALCD58_MASK 0x1u 01794 #define LCD_WF8B_BPALCD58_SHIFT 0 01795 #define LCD_WF8B_BPALCD57_MASK 0x1u 01796 #define LCD_WF8B_BPALCD57_SHIFT 0 01797 #define LCD_WF8B_BPALCD1_MASK 0x1u 01798 #define LCD_WF8B_BPALCD1_SHIFT 0 01799 #define LCD_WF8B_BPALCD56_MASK 0x1u 01800 #define LCD_WF8B_BPALCD56_SHIFT 0 01801 #define LCD_WF8B_BPALCD55_MASK 0x1u 01802 #define LCD_WF8B_BPALCD55_SHIFT 0 01803 #define LCD_WF8B_BPALCD54_MASK 0x1u 01804 #define LCD_WF8B_BPALCD54_SHIFT 0 01805 #define LCD_WF8B_BPALCD53_MASK 0x1u 01806 #define LCD_WF8B_BPALCD53_SHIFT 0 01807 #define LCD_WF8B_BPALCD52_MASK 0x1u 01808 #define LCD_WF8B_BPALCD52_SHIFT 0 01809 #define LCD_WF8B_BPALCD51_MASK 0x1u 01810 #define LCD_WF8B_BPALCD51_SHIFT 0 01811 #define LCD_WF8B_BPALCD50_MASK 0x1u 01812 #define LCD_WF8B_BPALCD50_SHIFT 0 01813 #define LCD_WF8B_BPALCD2_MASK 0x1u 01814 #define LCD_WF8B_BPALCD2_SHIFT 0 01815 #define LCD_WF8B_BPALCD49_MASK 0x1u 01816 #define LCD_WF8B_BPALCD49_SHIFT 0 01817 #define LCD_WF8B_BPALCD48_MASK 0x1u 01818 #define LCD_WF8B_BPALCD48_SHIFT 0 01819 #define LCD_WF8B_BPALCD47_MASK 0x1u 01820 #define LCD_WF8B_BPALCD47_SHIFT 0 01821 #define LCD_WF8B_BPALCD46_MASK 0x1u 01822 #define LCD_WF8B_BPALCD46_SHIFT 0 01823 #define LCD_WF8B_BPALCD45_MASK 0x1u 01824 #define LCD_WF8B_BPALCD45_SHIFT 0 01825 #define LCD_WF8B_BPALCD44_MASK 0x1u 01826 #define LCD_WF8B_BPALCD44_SHIFT 0 01827 #define LCD_WF8B_BPALCD43_MASK 0x1u 01828 #define LCD_WF8B_BPALCD43_SHIFT 0 01829 #define LCD_WF8B_BPALCD3_MASK 0x1u 01830 #define LCD_WF8B_BPALCD3_SHIFT 0 01831 #define LCD_WF8B_BPALCD42_MASK 0x1u 01832 #define LCD_WF8B_BPALCD42_SHIFT 0 01833 #define LCD_WF8B_BPALCD41_MASK 0x1u 01834 #define LCD_WF8B_BPALCD41_SHIFT 0 01835 #define LCD_WF8B_BPALCD40_MASK 0x1u 01836 #define LCD_WF8B_BPALCD40_SHIFT 0 01837 #define LCD_WF8B_BPALCD39_MASK 0x1u 01838 #define LCD_WF8B_BPALCD39_SHIFT 0 01839 #define LCD_WF8B_BPALCD38_MASK 0x1u 01840 #define LCD_WF8B_BPALCD38_SHIFT 0 01841 #define LCD_WF8B_BPALCD37_MASK 0x1u 01842 #define LCD_WF8B_BPALCD37_SHIFT 0 01843 #define LCD_WF8B_BPALCD36_MASK 0x1u 01844 #define LCD_WF8B_BPALCD36_SHIFT 0 01845 #define LCD_WF8B_BPALCD4_MASK 0x1u 01846 #define LCD_WF8B_BPALCD4_SHIFT 0 01847 #define LCD_WF8B_BPALCD35_MASK 0x1u 01848 #define LCD_WF8B_BPALCD35_SHIFT 0 01849 #define LCD_WF8B_BPALCD34_MASK 0x1u 01850 #define LCD_WF8B_BPALCD34_SHIFT 0 01851 #define LCD_WF8B_BPALCD33_MASK 0x1u 01852 #define LCD_WF8B_BPALCD33_SHIFT 0 01853 #define LCD_WF8B_BPALCD32_MASK 0x1u 01854 #define LCD_WF8B_BPALCD32_SHIFT 0 01855 #define LCD_WF8B_BPALCD31_MASK 0x1u 01856 #define LCD_WF8B_BPALCD31_SHIFT 0 01857 #define LCD_WF8B_BPALCD30_MASK 0x1u 01858 #define LCD_WF8B_BPALCD30_SHIFT 0 01859 #define LCD_WF8B_BPALCD29_MASK 0x1u 01860 #define LCD_WF8B_BPALCD29_SHIFT 0 01861 #define LCD_WF8B_BPALCD5_MASK 0x1u 01862 #define LCD_WF8B_BPALCD5_SHIFT 0 01863 #define LCD_WF8B_BPALCD28_MASK 0x1u 01864 #define LCD_WF8B_BPALCD28_SHIFT 0 01865 #define LCD_WF8B_BPALCD27_MASK 0x1u 01866 #define LCD_WF8B_BPALCD27_SHIFT 0 01867 #define LCD_WF8B_BPALCD26_MASK 0x1u 01868 #define LCD_WF8B_BPALCD26_SHIFT 0 01869 #define LCD_WF8B_BPALCD25_MASK 0x1u 01870 #define LCD_WF8B_BPALCD25_SHIFT 0 01871 #define LCD_WF8B_BPALCD24_MASK 0x1u 01872 #define LCD_WF8B_BPALCD24_SHIFT 0 01873 #define LCD_WF8B_BPALCD23_MASK 0x1u 01874 #define LCD_WF8B_BPALCD23_SHIFT 0 01875 #define LCD_WF8B_BPALCD22_MASK 0x1u 01876 #define LCD_WF8B_BPALCD22_SHIFT 0 01877 #define LCD_WF8B_BPALCD6_MASK 0x1u 01878 #define LCD_WF8B_BPALCD6_SHIFT 0 01879 #define LCD_WF8B_BPALCD21_MASK 0x1u 01880 #define LCD_WF8B_BPALCD21_SHIFT 0 01881 #define LCD_WF8B_BPALCD20_MASK 0x1u 01882 #define LCD_WF8B_BPALCD20_SHIFT 0 01883 #define LCD_WF8B_BPALCD19_MASK 0x1u 01884 #define LCD_WF8B_BPALCD19_SHIFT 0 01885 #define LCD_WF8B_BPALCD18_MASK 0x1u 01886 #define LCD_WF8B_BPALCD18_SHIFT 0 01887 #define LCD_WF8B_BPALCD17_MASK 0x1u 01888 #define LCD_WF8B_BPALCD17_SHIFT 0 01889 #define LCD_WF8B_BPALCD16_MASK 0x1u 01890 #define LCD_WF8B_BPALCD16_SHIFT 0 01891 #define LCD_WF8B_BPALCD15_MASK 0x1u 01892 #define LCD_WF8B_BPALCD15_SHIFT 0 01893 #define LCD_WF8B_BPALCD7_MASK 0x1u 01894 #define LCD_WF8B_BPALCD7_SHIFT 0 01895 #define LCD_WF8B_BPALCD14_MASK 0x1u 01896 #define LCD_WF8B_BPALCD14_SHIFT 0 01897 #define LCD_WF8B_BPALCD13_MASK 0x1u 01898 #define LCD_WF8B_BPALCD13_SHIFT 0 01899 #define LCD_WF8B_BPALCD12_MASK 0x1u 01900 #define LCD_WF8B_BPALCD12_SHIFT 0 01901 #define LCD_WF8B_BPALCD11_MASK 0x1u 01902 #define LCD_WF8B_BPALCD11_SHIFT 0 01903 #define LCD_WF8B_BPALCD10_MASK 0x1u 01904 #define LCD_WF8B_BPALCD10_SHIFT 0 01905 #define LCD_WF8B_BPALCD9_MASK 0x1u 01906 #define LCD_WF8B_BPALCD9_SHIFT 0 01907 #define LCD_WF8B_BPALCD8_MASK 0x1u 01908 #define LCD_WF8B_BPALCD8_SHIFT 0 01909 #define LCD_WF8B_BPBLCD1_MASK 0x2u 01910 #define LCD_WF8B_BPBLCD1_SHIFT 1 01911 #define LCD_WF8B_BPBLCD32_MASK 0x2u 01912 #define LCD_WF8B_BPBLCD32_SHIFT 1 01913 #define LCD_WF8B_BPBLCD30_MASK 0x2u 01914 #define LCD_WF8B_BPBLCD30_SHIFT 1 01915 #define LCD_WF8B_BPBLCD60_MASK 0x2u 01916 #define LCD_WF8B_BPBLCD60_SHIFT 1 01917 #define LCD_WF8B_BPBLCD24_MASK 0x2u 01918 #define LCD_WF8B_BPBLCD24_SHIFT 1 01919 #define LCD_WF8B_BPBLCD28_MASK 0x2u 01920 #define LCD_WF8B_BPBLCD28_SHIFT 1 01921 #define LCD_WF8B_BPBLCD23_MASK 0x2u 01922 #define LCD_WF8B_BPBLCD23_SHIFT 1 01923 #define LCD_WF8B_BPBLCD48_MASK 0x2u 01924 #define LCD_WF8B_BPBLCD48_SHIFT 1 01925 #define LCD_WF8B_BPBLCD10_MASK 0x2u 01926 #define LCD_WF8B_BPBLCD10_SHIFT 1 01927 #define LCD_WF8B_BPBLCD15_MASK 0x2u 01928 #define LCD_WF8B_BPBLCD15_SHIFT 1 01929 #define LCD_WF8B_BPBLCD36_MASK 0x2u 01930 #define LCD_WF8B_BPBLCD36_SHIFT 1 01931 #define LCD_WF8B_BPBLCD44_MASK 0x2u 01932 #define LCD_WF8B_BPBLCD44_SHIFT 1 01933 #define LCD_WF8B_BPBLCD62_MASK 0x2u 01934 #define LCD_WF8B_BPBLCD62_SHIFT 1 01935 #define LCD_WF8B_BPBLCD53_MASK 0x2u 01936 #define LCD_WF8B_BPBLCD53_SHIFT 1 01937 #define LCD_WF8B_BPBLCD22_MASK 0x2u 01938 #define LCD_WF8B_BPBLCD22_SHIFT 1 01939 #define LCD_WF8B_BPBLCD47_MASK 0x2u 01940 #define LCD_WF8B_BPBLCD47_SHIFT 1 01941 #define LCD_WF8B_BPBLCD33_MASK 0x2u 01942 #define LCD_WF8B_BPBLCD33_SHIFT 1 01943 #define LCD_WF8B_BPBLCD2_MASK 0x2u 01944 #define LCD_WF8B_BPBLCD2_SHIFT 1 01945 #define LCD_WF8B_BPBLCD49_MASK 0x2u 01946 #define LCD_WF8B_BPBLCD49_SHIFT 1 01947 #define LCD_WF8B_BPBLCD0_MASK 0x2u 01948 #define LCD_WF8B_BPBLCD0_SHIFT 1 01949 #define LCD_WF8B_BPBLCD55_MASK 0x2u 01950 #define LCD_WF8B_BPBLCD55_SHIFT 1 01951 #define LCD_WF8B_BPBLCD56_MASK 0x2u 01952 #define LCD_WF8B_BPBLCD56_SHIFT 1 01953 #define LCD_WF8B_BPBLCD21_MASK 0x2u 01954 #define LCD_WF8B_BPBLCD21_SHIFT 1 01955 #define LCD_WF8B_BPBLCD6_MASK 0x2u 01956 #define LCD_WF8B_BPBLCD6_SHIFT 1 01957 #define LCD_WF8B_BPBLCD29_MASK 0x2u 01958 #define LCD_WF8B_BPBLCD29_SHIFT 1 01959 #define LCD_WF8B_BPBLCD25_MASK 0x2u 01960 #define LCD_WF8B_BPBLCD25_SHIFT 1 01961 #define LCD_WF8B_BPBLCD8_MASK 0x2u 01962 #define LCD_WF8B_BPBLCD8_SHIFT 1 01963 #define LCD_WF8B_BPBLCD54_MASK 0x2u 01964 #define LCD_WF8B_BPBLCD54_SHIFT 1 01965 #define LCD_WF8B_BPBLCD38_MASK 0x2u 01966 #define LCD_WF8B_BPBLCD38_SHIFT 1 01967 #define LCD_WF8B_BPBLCD43_MASK 0x2u 01968 #define LCD_WF8B_BPBLCD43_SHIFT 1 01969 #define LCD_WF8B_BPBLCD20_MASK 0x2u 01970 #define LCD_WF8B_BPBLCD20_SHIFT 1 01971 #define LCD_WF8B_BPBLCD9_MASK 0x2u 01972 #define LCD_WF8B_BPBLCD9_SHIFT 1 01973 #define LCD_WF8B_BPBLCD7_MASK 0x2u 01974 #define LCD_WF8B_BPBLCD7_SHIFT 1 01975 #define LCD_WF8B_BPBLCD50_MASK 0x2u 01976 #define LCD_WF8B_BPBLCD50_SHIFT 1 01977 #define LCD_WF8B_BPBLCD40_MASK 0x2u 01978 #define LCD_WF8B_BPBLCD40_SHIFT 1 01979 #define LCD_WF8B_BPBLCD63_MASK 0x2u 01980 #define LCD_WF8B_BPBLCD63_SHIFT 1 01981 #define LCD_WF8B_BPBLCD26_MASK 0x2u 01982 #define LCD_WF8B_BPBLCD26_SHIFT 1 01983 #define LCD_WF8B_BPBLCD12_MASK 0x2u 01984 #define LCD_WF8B_BPBLCD12_SHIFT 1 01985 #define LCD_WF8B_BPBLCD19_MASK 0x2u 01986 #define LCD_WF8B_BPBLCD19_SHIFT 1 01987 #define LCD_WF8B_BPBLCD34_MASK 0x2u 01988 #define LCD_WF8B_BPBLCD34_SHIFT 1 01989 #define LCD_WF8B_BPBLCD39_MASK 0x2u 01990 #define LCD_WF8B_BPBLCD39_SHIFT 1 01991 #define LCD_WF8B_BPBLCD59_MASK 0x2u 01992 #define LCD_WF8B_BPBLCD59_SHIFT 1 01993 #define LCD_WF8B_BPBLCD61_MASK 0x2u 01994 #define LCD_WF8B_BPBLCD61_SHIFT 1 01995 #define LCD_WF8B_BPBLCD37_MASK 0x2u 01996 #define LCD_WF8B_BPBLCD37_SHIFT 1 01997 #define LCD_WF8B_BPBLCD31_MASK 0x2u 01998 #define LCD_WF8B_BPBLCD31_SHIFT 1 01999 #define LCD_WF8B_BPBLCD58_MASK 0x2u 02000 #define LCD_WF8B_BPBLCD58_SHIFT 1 02001 #define LCD_WF8B_BPBLCD18_MASK 0x2u 02002 #define LCD_WF8B_BPBLCD18_SHIFT 1 02003 #define LCD_WF8B_BPBLCD45_MASK 0x2u 02004 #define LCD_WF8B_BPBLCD45_SHIFT 1 02005 #define LCD_WF8B_BPBLCD27_MASK 0x2u 02006 #define LCD_WF8B_BPBLCD27_SHIFT 1 02007 #define LCD_WF8B_BPBLCD14_MASK 0x2u 02008 #define LCD_WF8B_BPBLCD14_SHIFT 1 02009 #define LCD_WF8B_BPBLCD51_MASK 0x2u 02010 #define LCD_WF8B_BPBLCD51_SHIFT 1 02011 #define LCD_WF8B_BPBLCD52_MASK 0x2u 02012 #define LCD_WF8B_BPBLCD52_SHIFT 1 02013 #define LCD_WF8B_BPBLCD4_MASK 0x2u 02014 #define LCD_WF8B_BPBLCD4_SHIFT 1 02015 #define LCD_WF8B_BPBLCD35_MASK 0x2u 02016 #define LCD_WF8B_BPBLCD35_SHIFT 1 02017 #define LCD_WF8B_BPBLCD17_MASK 0x2u 02018 #define LCD_WF8B_BPBLCD17_SHIFT 1 02019 #define LCD_WF8B_BPBLCD41_MASK 0x2u 02020 #define LCD_WF8B_BPBLCD41_SHIFT 1 02021 #define LCD_WF8B_BPBLCD11_MASK 0x2u 02022 #define LCD_WF8B_BPBLCD11_SHIFT 1 02023 #define LCD_WF8B_BPBLCD46_MASK 0x2u 02024 #define LCD_WF8B_BPBLCD46_SHIFT 1 02025 #define LCD_WF8B_BPBLCD57_MASK 0x2u 02026 #define LCD_WF8B_BPBLCD57_SHIFT 1 02027 #define LCD_WF8B_BPBLCD42_MASK 0x2u 02028 #define LCD_WF8B_BPBLCD42_SHIFT 1 02029 #define LCD_WF8B_BPBLCD5_MASK 0x2u 02030 #define LCD_WF8B_BPBLCD5_SHIFT 1 02031 #define LCD_WF8B_BPBLCD3_MASK 0x2u 02032 #define LCD_WF8B_BPBLCD3_SHIFT 1 02033 #define LCD_WF8B_BPBLCD16_MASK 0x2u 02034 #define LCD_WF8B_BPBLCD16_SHIFT 1 02035 #define LCD_WF8B_BPBLCD13_MASK 0x2u 02036 #define LCD_WF8B_BPBLCD13_SHIFT 1 02037 #define LCD_WF8B_BPCLCD10_MASK 0x4u 02038 #define LCD_WF8B_BPCLCD10_SHIFT 2 02039 #define LCD_WF8B_BPCLCD55_MASK 0x4u 02040 #define LCD_WF8B_BPCLCD55_SHIFT 2 02041 #define LCD_WF8B_BPCLCD2_MASK 0x4u 02042 #define LCD_WF8B_BPCLCD2_SHIFT 2 02043 #define LCD_WF8B_BPCLCD23_MASK 0x4u 02044 #define LCD_WF8B_BPCLCD23_SHIFT 2 02045 #define LCD_WF8B_BPCLCD48_MASK 0x4u 02046 #define LCD_WF8B_BPCLCD48_SHIFT 2 02047 #define LCD_WF8B_BPCLCD24_MASK 0x4u 02048 #define LCD_WF8B_BPCLCD24_SHIFT 2 02049 #define LCD_WF8B_BPCLCD60_MASK 0x4u 02050 #define LCD_WF8B_BPCLCD60_SHIFT 2 02051 #define LCD_WF8B_BPCLCD47_MASK 0x4u 02052 #define LCD_WF8B_BPCLCD47_SHIFT 2 02053 #define LCD_WF8B_BPCLCD22_MASK 0x4u 02054 #define LCD_WF8B_BPCLCD22_SHIFT 2 02055 #define LCD_WF8B_BPCLCD8_MASK 0x4u 02056 #define LCD_WF8B_BPCLCD8_SHIFT 2 02057 #define LCD_WF8B_BPCLCD21_MASK 0x4u 02058 #define LCD_WF8B_BPCLCD21_SHIFT 2 02059 #define LCD_WF8B_BPCLCD49_MASK 0x4u 02060 #define LCD_WF8B_BPCLCD49_SHIFT 2 02061 #define LCD_WF8B_BPCLCD25_MASK 0x4u 02062 #define LCD_WF8B_BPCLCD25_SHIFT 2 02063 #define LCD_WF8B_BPCLCD1_MASK 0x4u 02064 #define LCD_WF8B_BPCLCD1_SHIFT 2 02065 #define LCD_WF8B_BPCLCD20_MASK 0x4u 02066 #define LCD_WF8B_BPCLCD20_SHIFT 2 02067 #define LCD_WF8B_BPCLCD50_MASK 0x4u 02068 #define LCD_WF8B_BPCLCD50_SHIFT 2 02069 #define LCD_WF8B_BPCLCD19_MASK 0x4u 02070 #define LCD_WF8B_BPCLCD19_SHIFT 2 02071 #define LCD_WF8B_BPCLCD26_MASK 0x4u 02072 #define LCD_WF8B_BPCLCD26_SHIFT 2 02073 #define LCD_WF8B_BPCLCD59_MASK 0x4u 02074 #define LCD_WF8B_BPCLCD59_SHIFT 2 02075 #define LCD_WF8B_BPCLCD61_MASK 0x4u 02076 #define LCD_WF8B_BPCLCD61_SHIFT 2 02077 #define LCD_WF8B_BPCLCD46_MASK 0x4u 02078 #define LCD_WF8B_BPCLCD46_SHIFT 2 02079 #define LCD_WF8B_BPCLCD18_MASK 0x4u 02080 #define LCD_WF8B_BPCLCD18_SHIFT 2 02081 #define LCD_WF8B_BPCLCD5_MASK 0x4u 02082 #define LCD_WF8B_BPCLCD5_SHIFT 2 02083 #define LCD_WF8B_BPCLCD63_MASK 0x4u 02084 #define LCD_WF8B_BPCLCD63_SHIFT 2 02085 #define LCD_WF8B_BPCLCD27_MASK 0x4u 02086 #define LCD_WF8B_BPCLCD27_SHIFT 2 02087 #define LCD_WF8B_BPCLCD17_MASK 0x4u 02088 #define LCD_WF8B_BPCLCD17_SHIFT 2 02089 #define LCD_WF8B_BPCLCD51_MASK 0x4u 02090 #define LCD_WF8B_BPCLCD51_SHIFT 2 02091 #define LCD_WF8B_BPCLCD9_MASK 0x4u 02092 #define LCD_WF8B_BPCLCD9_SHIFT 2 02093 #define LCD_WF8B_BPCLCD54_MASK 0x4u 02094 #define LCD_WF8B_BPCLCD54_SHIFT 2 02095 #define LCD_WF8B_BPCLCD15_MASK 0x4u 02096 #define LCD_WF8B_BPCLCD15_SHIFT 2 02097 #define LCD_WF8B_BPCLCD16_MASK 0x4u 02098 #define LCD_WF8B_BPCLCD16_SHIFT 2 02099 #define LCD_WF8B_BPCLCD14_MASK 0x4u 02100 #define LCD_WF8B_BPCLCD14_SHIFT 2 02101 #define LCD_WF8B_BPCLCD32_MASK 0x4u 02102 #define LCD_WF8B_BPCLCD32_SHIFT 2 02103 #define LCD_WF8B_BPCLCD28_MASK 0x4u 02104 #define LCD_WF8B_BPCLCD28_SHIFT 2 02105 #define LCD_WF8B_BPCLCD53_MASK 0x4u 02106 #define LCD_WF8B_BPCLCD53_SHIFT 2 02107 #define LCD_WF8B_BPCLCD33_MASK 0x4u 02108 #define LCD_WF8B_BPCLCD33_SHIFT 2 02109 #define LCD_WF8B_BPCLCD0_MASK 0x4u 02110 #define LCD_WF8B_BPCLCD0_SHIFT 2 02111 #define LCD_WF8B_BPCLCD43_MASK 0x4u 02112 #define LCD_WF8B_BPCLCD43_SHIFT 2 02113 #define LCD_WF8B_BPCLCD7_MASK 0x4u 02114 #define LCD_WF8B_BPCLCD7_SHIFT 2 02115 #define LCD_WF8B_BPCLCD4_MASK 0x4u 02116 #define LCD_WF8B_BPCLCD4_SHIFT 2 02117 #define LCD_WF8B_BPCLCD34_MASK 0x4u 02118 #define LCD_WF8B_BPCLCD34_SHIFT 2 02119 #define LCD_WF8B_BPCLCD29_MASK 0x4u 02120 #define LCD_WF8B_BPCLCD29_SHIFT 2 02121 #define LCD_WF8B_BPCLCD45_MASK 0x4u 02122 #define LCD_WF8B_BPCLCD45_SHIFT 2 02123 #define LCD_WF8B_BPCLCD57_MASK 0x4u 02124 #define LCD_WF8B_BPCLCD57_SHIFT 2 02125 #define LCD_WF8B_BPCLCD42_MASK 0x4u 02126 #define LCD_WF8B_BPCLCD42_SHIFT 2 02127 #define LCD_WF8B_BPCLCD35_MASK 0x4u 02128 #define LCD_WF8B_BPCLCD35_SHIFT 2 02129 #define LCD_WF8B_BPCLCD13_MASK 0x4u 02130 #define LCD_WF8B_BPCLCD13_SHIFT 2 02131 #define LCD_WF8B_BPCLCD36_MASK 0x4u 02132 #define LCD_WF8B_BPCLCD36_SHIFT 2 02133 #define LCD_WF8B_BPCLCD30_MASK 0x4u 02134 #define LCD_WF8B_BPCLCD30_SHIFT 2 02135 #define LCD_WF8B_BPCLCD52_MASK 0x4u 02136 #define LCD_WF8B_BPCLCD52_SHIFT 2 02137 #define LCD_WF8B_BPCLCD58_MASK 0x4u 02138 #define LCD_WF8B_BPCLCD58_SHIFT 2 02139 #define LCD_WF8B_BPCLCD41_MASK 0x4u 02140 #define LCD_WF8B_BPCLCD41_SHIFT 2 02141 #define LCD_WF8B_BPCLCD37_MASK 0x4u 02142 #define LCD_WF8B_BPCLCD37_SHIFT 2 02143 #define LCD_WF8B_BPCLCD3_MASK 0x4u 02144 #define LCD_WF8B_BPCLCD3_SHIFT 2 02145 #define LCD_WF8B_BPCLCD12_MASK 0x4u 02146 #define LCD_WF8B_BPCLCD12_SHIFT 2 02147 #define LCD_WF8B_BPCLCD11_MASK 0x4u 02148 #define LCD_WF8B_BPCLCD11_SHIFT 2 02149 #define LCD_WF8B_BPCLCD38_MASK 0x4u 02150 #define LCD_WF8B_BPCLCD38_SHIFT 2 02151 #define LCD_WF8B_BPCLCD44_MASK 0x4u 02152 #define LCD_WF8B_BPCLCD44_SHIFT 2 02153 #define LCD_WF8B_BPCLCD31_MASK 0x4u 02154 #define LCD_WF8B_BPCLCD31_SHIFT 2 02155 #define LCD_WF8B_BPCLCD40_MASK 0x4u 02156 #define LCD_WF8B_BPCLCD40_SHIFT 2 02157 #define LCD_WF8B_BPCLCD62_MASK 0x4u 02158 #define LCD_WF8B_BPCLCD62_SHIFT 2 02159 #define LCD_WF8B_BPCLCD56_MASK 0x4u 02160 #define LCD_WF8B_BPCLCD56_SHIFT 2 02161 #define LCD_WF8B_BPCLCD39_MASK 0x4u 02162 #define LCD_WF8B_BPCLCD39_SHIFT 2 02163 #define LCD_WF8B_BPCLCD6_MASK 0x4u 02164 #define LCD_WF8B_BPCLCD6_SHIFT 2 02165 #define LCD_WF8B_BPDLCD47_MASK 0x8u 02166 #define LCD_WF8B_BPDLCD47_SHIFT 3 02167 #define LCD_WF8B_BPDLCD23_MASK 0x8u 02168 #define LCD_WF8B_BPDLCD23_SHIFT 3 02169 #define LCD_WF8B_BPDLCD48_MASK 0x8u 02170 #define LCD_WF8B_BPDLCD48_SHIFT 3 02171 #define LCD_WF8B_BPDLCD24_MASK 0x8u 02172 #define LCD_WF8B_BPDLCD24_SHIFT 3 02173 #define LCD_WF8B_BPDLCD15_MASK 0x8u 02174 #define LCD_WF8B_BPDLCD15_SHIFT 3 02175 #define LCD_WF8B_BPDLCD22_MASK 0x8u 02176 #define LCD_WF8B_BPDLCD22_SHIFT 3 02177 #define LCD_WF8B_BPDLCD60_MASK 0x8u 02178 #define LCD_WF8B_BPDLCD60_SHIFT 3 02179 #define LCD_WF8B_BPDLCD10_MASK 0x8u 02180 #define LCD_WF8B_BPDLCD10_SHIFT 3 02181 #define LCD_WF8B_BPDLCD21_MASK 0x8u 02182 #define LCD_WF8B_BPDLCD21_SHIFT 3 02183 #define LCD_WF8B_BPDLCD49_MASK 0x8u 02184 #define LCD_WF8B_BPDLCD49_SHIFT 3 02185 #define LCD_WF8B_BPDLCD1_MASK 0x8u 02186 #define LCD_WF8B_BPDLCD1_SHIFT 3 02187 #define LCD_WF8B_BPDLCD25_MASK 0x8u 02188 #define LCD_WF8B_BPDLCD25_SHIFT 3 02189 #define LCD_WF8B_BPDLCD20_MASK 0x8u 02190 #define LCD_WF8B_BPDLCD20_SHIFT 3 02191 #define LCD_WF8B_BPDLCD2_MASK 0x8u 02192 #define LCD_WF8B_BPDLCD2_SHIFT 3 02193 #define LCD_WF8B_BPDLCD55_MASK 0x8u 02194 #define LCD_WF8B_BPDLCD55_SHIFT 3 02195 #define LCD_WF8B_BPDLCD59_MASK 0x8u 02196 #define LCD_WF8B_BPDLCD59_SHIFT 3 02197 #define LCD_WF8B_BPDLCD5_MASK 0x8u 02198 #define LCD_WF8B_BPDLCD5_SHIFT 3 02199 #define LCD_WF8B_BPDLCD19_MASK 0x8u 02200 #define LCD_WF8B_BPDLCD19_SHIFT 3 02201 #define LCD_WF8B_BPDLCD6_MASK 0x8u 02202 #define LCD_WF8B_BPDLCD6_SHIFT 3 02203 #define LCD_WF8B_BPDLCD26_MASK 0x8u 02204 #define LCD_WF8B_BPDLCD26_SHIFT 3 02205 #define LCD_WF8B_BPDLCD0_MASK 0x8u 02206 #define LCD_WF8B_BPDLCD0_SHIFT 3 02207 #define LCD_WF8B_BPDLCD50_MASK 0x8u 02208 #define LCD_WF8B_BPDLCD50_SHIFT 3 02209 #define LCD_WF8B_BPDLCD46_MASK 0x8u 02210 #define LCD_WF8B_BPDLCD46_SHIFT 3 02211 #define LCD_WF8B_BPDLCD18_MASK 0x8u 02212 #define LCD_WF8B_BPDLCD18_SHIFT 3 02213 #define LCD_WF8B_BPDLCD61_MASK 0x8u 02214 #define LCD_WF8B_BPDLCD61_SHIFT 3 02215 #define LCD_WF8B_BPDLCD9_MASK 0x8u 02216 #define LCD_WF8B_BPDLCD9_SHIFT 3 02217 #define LCD_WF8B_BPDLCD17_MASK 0x8u 02218 #define LCD_WF8B_BPDLCD17_SHIFT 3 02219 #define LCD_WF8B_BPDLCD27_MASK 0x8u 02220 #define LCD_WF8B_BPDLCD27_SHIFT 3 02221 #define LCD_WF8B_BPDLCD53_MASK 0x8u 02222 #define LCD_WF8B_BPDLCD53_SHIFT 3 02223 #define LCD_WF8B_BPDLCD51_MASK 0x8u 02224 #define LCD_WF8B_BPDLCD51_SHIFT 3 02225 #define LCD_WF8B_BPDLCD54_MASK 0x8u 02226 #define LCD_WF8B_BPDLCD54_SHIFT 3 02227 #define LCD_WF8B_BPDLCD13_MASK 0x8u 02228 #define LCD_WF8B_BPDLCD13_SHIFT 3 02229 #define LCD_WF8B_BPDLCD16_MASK 0x8u 02230 #define LCD_WF8B_BPDLCD16_SHIFT 3 02231 #define LCD_WF8B_BPDLCD32_MASK 0x8u 02232 #define LCD_WF8B_BPDLCD32_SHIFT 3 02233 #define LCD_WF8B_BPDLCD14_MASK 0x8u 02234 #define LCD_WF8B_BPDLCD14_SHIFT 3 02235 #define LCD_WF8B_BPDLCD28_MASK 0x8u 02236 #define LCD_WF8B_BPDLCD28_SHIFT 3 02237 #define LCD_WF8B_BPDLCD43_MASK 0x8u 02238 #define LCD_WF8B_BPDLCD43_SHIFT 3 02239 #define LCD_WF8B_BPDLCD4_MASK 0x8u 02240 #define LCD_WF8B_BPDLCD4_SHIFT 3 02241 #define LCD_WF8B_BPDLCD45_MASK 0x8u 02242 #define LCD_WF8B_BPDLCD45_SHIFT 3 02243 #define LCD_WF8B_BPDLCD8_MASK 0x8u 02244 #define LCD_WF8B_BPDLCD8_SHIFT 3 02245 #define LCD_WF8B_BPDLCD62_MASK 0x8u 02246 #define LCD_WF8B_BPDLCD62_SHIFT 3 02247 #define LCD_WF8B_BPDLCD33_MASK 0x8u 02248 #define LCD_WF8B_BPDLCD33_SHIFT 3 02249 #define LCD_WF8B_BPDLCD34_MASK 0x8u 02250 #define LCD_WF8B_BPDLCD34_SHIFT 3 02251 #define LCD_WF8B_BPDLCD29_MASK 0x8u 02252 #define LCD_WF8B_BPDLCD29_SHIFT 3 02253 #define LCD_WF8B_BPDLCD58_MASK 0x8u 02254 #define LCD_WF8B_BPDLCD58_SHIFT 3 02255 #define LCD_WF8B_BPDLCD57_MASK 0x8u 02256 #define LCD_WF8B_BPDLCD57_SHIFT 3 02257 #define LCD_WF8B_BPDLCD42_MASK 0x8u 02258 #define LCD_WF8B_BPDLCD42_SHIFT 3 02259 #define LCD_WF8B_BPDLCD35_MASK 0x8u 02260 #define LCD_WF8B_BPDLCD35_SHIFT 3 02261 #define LCD_WF8B_BPDLCD52_MASK 0x8u 02262 #define LCD_WF8B_BPDLCD52_SHIFT 3 02263 #define LCD_WF8B_BPDLCD7_MASK 0x8u 02264 #define LCD_WF8B_BPDLCD7_SHIFT 3 02265 #define LCD_WF8B_BPDLCD36_MASK 0x8u 02266 #define LCD_WF8B_BPDLCD36_SHIFT 3 02267 #define LCD_WF8B_BPDLCD30_MASK 0x8u 02268 #define LCD_WF8B_BPDLCD30_SHIFT 3 02269 #define LCD_WF8B_BPDLCD41_MASK 0x8u 02270 #define LCD_WF8B_BPDLCD41_SHIFT 3 02271 #define LCD_WF8B_BPDLCD37_MASK 0x8u 02272 #define LCD_WF8B_BPDLCD37_SHIFT 3 02273 #define LCD_WF8B_BPDLCD44_MASK 0x8u 02274 #define LCD_WF8B_BPDLCD44_SHIFT 3 02275 #define LCD_WF8B_BPDLCD63_MASK 0x8u 02276 #define LCD_WF8B_BPDLCD63_SHIFT 3 02277 #define LCD_WF8B_BPDLCD38_MASK 0x8u 02278 #define LCD_WF8B_BPDLCD38_SHIFT 3 02279 #define LCD_WF8B_BPDLCD56_MASK 0x8u 02280 #define LCD_WF8B_BPDLCD56_SHIFT 3 02281 #define LCD_WF8B_BPDLCD40_MASK 0x8u 02282 #define LCD_WF8B_BPDLCD40_SHIFT 3 02283 #define LCD_WF8B_BPDLCD31_MASK 0x8u 02284 #define LCD_WF8B_BPDLCD31_SHIFT 3 02285 #define LCD_WF8B_BPDLCD12_MASK 0x8u 02286 #define LCD_WF8B_BPDLCD12_SHIFT 3 02287 #define LCD_WF8B_BPDLCD39_MASK 0x8u 02288 #define LCD_WF8B_BPDLCD39_SHIFT 3 02289 #define LCD_WF8B_BPDLCD3_MASK 0x8u 02290 #define LCD_WF8B_BPDLCD3_SHIFT 3 02291 #define LCD_WF8B_BPDLCD11_MASK 0x8u 02292 #define LCD_WF8B_BPDLCD11_SHIFT 3 02293 #define LCD_WF8B_BPELCD12_MASK 0x10u 02294 #define LCD_WF8B_BPELCD12_SHIFT 4 02295 #define LCD_WF8B_BPELCD39_MASK 0x10u 02296 #define LCD_WF8B_BPELCD39_SHIFT 4 02297 #define LCD_WF8B_BPELCD3_MASK 0x10u 02298 #define LCD_WF8B_BPELCD3_SHIFT 4 02299 #define LCD_WF8B_BPELCD38_MASK 0x10u 02300 #define LCD_WF8B_BPELCD38_SHIFT 4 02301 #define LCD_WF8B_BPELCD40_MASK 0x10u 02302 #define LCD_WF8B_BPELCD40_SHIFT 4 02303 #define LCD_WF8B_BPELCD37_MASK 0x10u 02304 #define LCD_WF8B_BPELCD37_SHIFT 4 02305 #define LCD_WF8B_BPELCD41_MASK 0x10u 02306 #define LCD_WF8B_BPELCD41_SHIFT 4 02307 #define LCD_WF8B_BPELCD36_MASK 0x10u 02308 #define LCD_WF8B_BPELCD36_SHIFT 4 02309 #define LCD_WF8B_BPELCD8_MASK 0x10u 02310 #define LCD_WF8B_BPELCD8_SHIFT 4 02311 #define LCD_WF8B_BPELCD35_MASK 0x10u 02312 #define LCD_WF8B_BPELCD35_SHIFT 4 02313 #define LCD_WF8B_BPELCD42_MASK 0x10u 02314 #define LCD_WF8B_BPELCD42_SHIFT 4 02315 #define LCD_WF8B_BPELCD34_MASK 0x10u 02316 #define LCD_WF8B_BPELCD34_SHIFT 4 02317 #define LCD_WF8B_BPELCD33_MASK 0x10u 02318 #define LCD_WF8B_BPELCD33_SHIFT 4 02319 #define LCD_WF8B_BPELCD11_MASK 0x10u 02320 #define LCD_WF8B_BPELCD11_SHIFT 4 02321 #define LCD_WF8B_BPELCD43_MASK 0x10u 02322 #define LCD_WF8B_BPELCD43_SHIFT 4 02323 #define LCD_WF8B_BPELCD32_MASK 0x10u 02324 #define LCD_WF8B_BPELCD32_SHIFT 4 02325 #define LCD_WF8B_BPELCD31_MASK 0x10u 02326 #define LCD_WF8B_BPELCD31_SHIFT 4 02327 #define LCD_WF8B_BPELCD44_MASK 0x10u 02328 #define LCD_WF8B_BPELCD44_SHIFT 4 02329 #define LCD_WF8B_BPELCD30_MASK 0x10u 02330 #define LCD_WF8B_BPELCD30_SHIFT 4 02331 #define LCD_WF8B_BPELCD29_MASK 0x10u 02332 #define LCD_WF8B_BPELCD29_SHIFT 4 02333 #define LCD_WF8B_BPELCD7_MASK 0x10u 02334 #define LCD_WF8B_BPELCD7_SHIFT 4 02335 #define LCD_WF8B_BPELCD45_MASK 0x10u 02336 #define LCD_WF8B_BPELCD45_SHIFT 4 02337 #define LCD_WF8B_BPELCD28_MASK 0x10u 02338 #define LCD_WF8B_BPELCD28_SHIFT 4 02339 #define LCD_WF8B_BPELCD2_MASK 0x10u 02340 #define LCD_WF8B_BPELCD2_SHIFT 4 02341 #define LCD_WF8B_BPELCD27_MASK 0x10u 02342 #define LCD_WF8B_BPELCD27_SHIFT 4 02343 #define LCD_WF8B_BPELCD46_MASK 0x10u 02344 #define LCD_WF8B_BPELCD46_SHIFT 4 02345 #define LCD_WF8B_BPELCD26_MASK 0x10u 02346 #define LCD_WF8B_BPELCD26_SHIFT 4 02347 #define LCD_WF8B_BPELCD10_MASK 0x10u 02348 #define LCD_WF8B_BPELCD10_SHIFT 4 02349 #define LCD_WF8B_BPELCD13_MASK 0x10u 02350 #define LCD_WF8B_BPELCD13_SHIFT 4 02351 #define LCD_WF8B_BPELCD25_MASK 0x10u 02352 #define LCD_WF8B_BPELCD25_SHIFT 4 02353 #define LCD_WF8B_BPELCD5_MASK 0x10u 02354 #define LCD_WF8B_BPELCD5_SHIFT 4 02355 #define LCD_WF8B_BPELCD24_MASK 0x10u 02356 #define LCD_WF8B_BPELCD24_SHIFT 4 02357 #define LCD_WF8B_BPELCD47_MASK 0x10u 02358 #define LCD_WF8B_BPELCD47_SHIFT 4 02359 #define LCD_WF8B_BPELCD23_MASK 0x10u 02360 #define LCD_WF8B_BPELCD23_SHIFT 4 02361 #define LCD_WF8B_BPELCD22_MASK 0x10u 02362 #define LCD_WF8B_BPELCD22_SHIFT 4 02363 #define LCD_WF8B_BPELCD48_MASK 0x10u 02364 #define LCD_WF8B_BPELCD48_SHIFT 4 02365 #define LCD_WF8B_BPELCD21_MASK 0x10u 02366 #define LCD_WF8B_BPELCD21_SHIFT 4 02367 #define LCD_WF8B_BPELCD49_MASK 0x10u 02368 #define LCD_WF8B_BPELCD49_SHIFT 4 02369 #define LCD_WF8B_BPELCD20_MASK 0x10u 02370 #define LCD_WF8B_BPELCD20_SHIFT 4 02371 #define LCD_WF8B_BPELCD19_MASK 0x10u 02372 #define LCD_WF8B_BPELCD19_SHIFT 4 02373 #define LCD_WF8B_BPELCD9_MASK 0x10u 02374 #define LCD_WF8B_BPELCD9_SHIFT 4 02375 #define LCD_WF8B_BPELCD50_MASK 0x10u 02376 #define LCD_WF8B_BPELCD50_SHIFT 4 02377 #define LCD_WF8B_BPELCD18_MASK 0x10u 02378 #define LCD_WF8B_BPELCD18_SHIFT 4 02379 #define LCD_WF8B_BPELCD6_MASK 0x10u 02380 #define LCD_WF8B_BPELCD6_SHIFT 4 02381 #define LCD_WF8B_BPELCD17_MASK 0x10u 02382 #define LCD_WF8B_BPELCD17_SHIFT 4 02383 #define LCD_WF8B_BPELCD51_MASK 0x10u 02384 #define LCD_WF8B_BPELCD51_SHIFT 4 02385 #define LCD_WF8B_BPELCD16_MASK 0x10u 02386 #define LCD_WF8B_BPELCD16_SHIFT 4 02387 #define LCD_WF8B_BPELCD56_MASK 0x10u 02388 #define LCD_WF8B_BPELCD56_SHIFT 4 02389 #define LCD_WF8B_BPELCD57_MASK 0x10u 02390 #define LCD_WF8B_BPELCD57_SHIFT 4 02391 #define LCD_WF8B_BPELCD52_MASK 0x10u 02392 #define LCD_WF8B_BPELCD52_SHIFT 4 02393 #define LCD_WF8B_BPELCD1_MASK 0x10u 02394 #define LCD_WF8B_BPELCD1_SHIFT 4 02395 #define LCD_WF8B_BPELCD58_MASK 0x10u 02396 #define LCD_WF8B_BPELCD58_SHIFT 4 02397 #define LCD_WF8B_BPELCD59_MASK 0x10u 02398 #define LCD_WF8B_BPELCD59_SHIFT 4 02399 #define LCD_WF8B_BPELCD53_MASK 0x10u 02400 #define LCD_WF8B_BPELCD53_SHIFT 4 02401 #define LCD_WF8B_BPELCD14_MASK 0x10u 02402 #define LCD_WF8B_BPELCD14_SHIFT 4 02403 #define LCD_WF8B_BPELCD0_MASK 0x10u 02404 #define LCD_WF8B_BPELCD0_SHIFT 4 02405 #define LCD_WF8B_BPELCD60_MASK 0x10u 02406 #define LCD_WF8B_BPELCD60_SHIFT 4 02407 #define LCD_WF8B_BPELCD15_MASK 0x10u 02408 #define LCD_WF8B_BPELCD15_SHIFT 4 02409 #define LCD_WF8B_BPELCD61_MASK 0x10u 02410 #define LCD_WF8B_BPELCD61_SHIFT 4 02411 #define LCD_WF8B_BPELCD54_MASK 0x10u 02412 #define LCD_WF8B_BPELCD54_SHIFT 4 02413 #define LCD_WF8B_BPELCD62_MASK 0x10u 02414 #define LCD_WF8B_BPELCD62_SHIFT 4 02415 #define LCD_WF8B_BPELCD63_MASK 0x10u 02416 #define LCD_WF8B_BPELCD63_SHIFT 4 02417 #define LCD_WF8B_BPELCD55_MASK 0x10u 02418 #define LCD_WF8B_BPELCD55_SHIFT 4 02419 #define LCD_WF8B_BPELCD4_MASK 0x10u 02420 #define LCD_WF8B_BPELCD4_SHIFT 4 02421 #define LCD_WF8B_BPFLCD13_MASK 0x20u 02422 #define LCD_WF8B_BPFLCD13_SHIFT 5 02423 #define LCD_WF8B_BPFLCD39_MASK 0x20u 02424 #define LCD_WF8B_BPFLCD39_SHIFT 5 02425 #define LCD_WF8B_BPFLCD55_MASK 0x20u 02426 #define LCD_WF8B_BPFLCD55_SHIFT 5 02427 #define LCD_WF8B_BPFLCD47_MASK 0x20u 02428 #define LCD_WF8B_BPFLCD47_SHIFT 5 02429 #define LCD_WF8B_BPFLCD63_MASK 0x20u 02430 #define LCD_WF8B_BPFLCD63_SHIFT 5 02431 #define LCD_WF8B_BPFLCD43_MASK 0x20u 02432 #define LCD_WF8B_BPFLCD43_SHIFT 5 02433 #define LCD_WF8B_BPFLCD5_MASK 0x20u 02434 #define LCD_WF8B_BPFLCD5_SHIFT 5 02435 #define LCD_WF8B_BPFLCD62_MASK 0x20u 02436 #define LCD_WF8B_BPFLCD62_SHIFT 5 02437 #define LCD_WF8B_BPFLCD14_MASK 0x20u 02438 #define LCD_WF8B_BPFLCD14_SHIFT 5 02439 #define LCD_WF8B_BPFLCD24_MASK 0x20u 02440 #define LCD_WF8B_BPFLCD24_SHIFT 5 02441 #define LCD_WF8B_BPFLCD54_MASK 0x20u 02442 #define LCD_WF8B_BPFLCD54_SHIFT 5 02443 #define LCD_WF8B_BPFLCD15_MASK 0x20u 02444 #define LCD_WF8B_BPFLCD15_SHIFT 5 02445 #define LCD_WF8B_BPFLCD32_MASK 0x20u 02446 #define LCD_WF8B_BPFLCD32_SHIFT 5 02447 #define LCD_WF8B_BPFLCD61_MASK 0x20u 02448 #define LCD_WF8B_BPFLCD61_SHIFT 5 02449 #define LCD_WF8B_BPFLCD25_MASK 0x20u 02450 #define LCD_WF8B_BPFLCD25_SHIFT 5 02451 #define LCD_WF8B_BPFLCD60_MASK 0x20u 02452 #define LCD_WF8B_BPFLCD60_SHIFT 5 02453 #define LCD_WF8B_BPFLCD41_MASK 0x20u 02454 #define LCD_WF8B_BPFLCD41_SHIFT 5 02455 #define LCD_WF8B_BPFLCD33_MASK 0x20u 02456 #define LCD_WF8B_BPFLCD33_SHIFT 5 02457 #define LCD_WF8B_BPFLCD53_MASK 0x20u 02458 #define LCD_WF8B_BPFLCD53_SHIFT 5 02459 #define LCD_WF8B_BPFLCD59_MASK 0x20u 02460 #define LCD_WF8B_BPFLCD59_SHIFT 5 02461 #define LCD_WF8B_BPFLCD0_MASK 0x20u 02462 #define LCD_WF8B_BPFLCD0_SHIFT 5 02463 #define LCD_WF8B_BPFLCD46_MASK 0x20u 02464 #define LCD_WF8B_BPFLCD46_SHIFT 5 02465 #define LCD_WF8B_BPFLCD58_MASK 0x20u 02466 #define LCD_WF8B_BPFLCD58_SHIFT 5 02467 #define LCD_WF8B_BPFLCD26_MASK 0x20u 02468 #define LCD_WF8B_BPFLCD26_SHIFT 5 02469 #define LCD_WF8B_BPFLCD36_MASK 0x20u 02470 #define LCD_WF8B_BPFLCD36_SHIFT 5 02471 #define LCD_WF8B_BPFLCD10_MASK 0x20u 02472 #define LCD_WF8B_BPFLCD10_SHIFT 5 02473 #define LCD_WF8B_BPFLCD52_MASK 0x20u 02474 #define LCD_WF8B_BPFLCD52_SHIFT 5 02475 #define LCD_WF8B_BPFLCD57_MASK 0x20u 02476 #define LCD_WF8B_BPFLCD57_SHIFT 5 02477 #define LCD_WF8B_BPFLCD27_MASK 0x20u 02478 #define LCD_WF8B_BPFLCD27_SHIFT 5 02479 #define LCD_WF8B_BPFLCD11_MASK 0x20u 02480 #define LCD_WF8B_BPFLCD11_SHIFT 5 02481 #define LCD_WF8B_BPFLCD56_MASK 0x20u 02482 #define LCD_WF8B_BPFLCD56_SHIFT 5 02483 #define LCD_WF8B_BPFLCD1_MASK 0x20u 02484 #define LCD_WF8B_BPFLCD1_SHIFT 5 02485 #define LCD_WF8B_BPFLCD8_MASK 0x20u 02486 #define LCD_WF8B_BPFLCD8_SHIFT 5 02487 #define LCD_WF8B_BPFLCD40_MASK 0x20u 02488 #define LCD_WF8B_BPFLCD40_SHIFT 5 02489 #define LCD_WF8B_BPFLCD51_MASK 0x20u 02490 #define LCD_WF8B_BPFLCD51_SHIFT 5 02491 #define LCD_WF8B_BPFLCD16_MASK 0x20u 02492 #define LCD_WF8B_BPFLCD16_SHIFT 5 02493 #define LCD_WF8B_BPFLCD45_MASK 0x20u 02494 #define LCD_WF8B_BPFLCD45_SHIFT 5 02495 #define LCD_WF8B_BPFLCD6_MASK 0x20u 02496 #define LCD_WF8B_BPFLCD6_SHIFT 5 02497 #define LCD_WF8B_BPFLCD17_MASK 0x20u 02498 #define LCD_WF8B_BPFLCD17_SHIFT 5 02499 #define LCD_WF8B_BPFLCD28_MASK 0x20u 02500 #define LCD_WF8B_BPFLCD28_SHIFT 5 02501 #define LCD_WF8B_BPFLCD42_MASK 0x20u 02502 #define LCD_WF8B_BPFLCD42_SHIFT 5 02503 #define LCD_WF8B_BPFLCD29_MASK 0x20u 02504 #define LCD_WF8B_BPFLCD29_SHIFT 5 02505 #define LCD_WF8B_BPFLCD50_MASK 0x20u 02506 #define LCD_WF8B_BPFLCD50_SHIFT 5 02507 #define LCD_WF8B_BPFLCD18_MASK 0x20u 02508 #define LCD_WF8B_BPFLCD18_SHIFT 5 02509 #define LCD_WF8B_BPFLCD34_MASK 0x20u 02510 #define LCD_WF8B_BPFLCD34_SHIFT 5 02511 #define LCD_WF8B_BPFLCD19_MASK 0x20u 02512 #define LCD_WF8B_BPFLCD19_SHIFT 5 02513 #define LCD_WF8B_BPFLCD2_MASK 0x20u 02514 #define LCD_WF8B_BPFLCD2_SHIFT 5 02515 #define LCD_WF8B_BPFLCD9_MASK 0x20u 02516 #define LCD_WF8B_BPFLCD9_SHIFT 5 02517 #define LCD_WF8B_BPFLCD3_MASK 0x20u 02518 #define LCD_WF8B_BPFLCD3_SHIFT 5 02519 #define LCD_WF8B_BPFLCD37_MASK 0x20u 02520 #define LCD_WF8B_BPFLCD37_SHIFT 5 02521 #define LCD_WF8B_BPFLCD49_MASK 0x20u 02522 #define LCD_WF8B_BPFLCD49_SHIFT 5 02523 #define LCD_WF8B_BPFLCD20_MASK 0x20u 02524 #define LCD_WF8B_BPFLCD20_SHIFT 5 02525 #define LCD_WF8B_BPFLCD44_MASK 0x20u 02526 #define LCD_WF8B_BPFLCD44_SHIFT 5 02527 #define LCD_WF8B_BPFLCD30_MASK 0x20u 02528 #define LCD_WF8B_BPFLCD30_SHIFT 5 02529 #define LCD_WF8B_BPFLCD21_MASK 0x20u 02530 #define LCD_WF8B_BPFLCD21_SHIFT 5 02531 #define LCD_WF8B_BPFLCD35_MASK 0x20u 02532 #define LCD_WF8B_BPFLCD35_SHIFT 5 02533 #define LCD_WF8B_BPFLCD4_MASK 0x20u 02534 #define LCD_WF8B_BPFLCD4_SHIFT 5 02535 #define LCD_WF8B_BPFLCD31_MASK 0x20u 02536 #define LCD_WF8B_BPFLCD31_SHIFT 5 02537 #define LCD_WF8B_BPFLCD48_MASK 0x20u 02538 #define LCD_WF8B_BPFLCD48_SHIFT 5 02539 #define LCD_WF8B_BPFLCD7_MASK 0x20u 02540 #define LCD_WF8B_BPFLCD7_SHIFT 5 02541 #define LCD_WF8B_BPFLCD22_MASK 0x20u 02542 #define LCD_WF8B_BPFLCD22_SHIFT 5 02543 #define LCD_WF8B_BPFLCD38_MASK 0x20u 02544 #define LCD_WF8B_BPFLCD38_SHIFT 5 02545 #define LCD_WF8B_BPFLCD12_MASK 0x20u 02546 #define LCD_WF8B_BPFLCD12_SHIFT 5 02547 #define LCD_WF8B_BPFLCD23_MASK 0x20u 02548 #define LCD_WF8B_BPFLCD23_SHIFT 5 02549 #define LCD_WF8B_BPGLCD14_MASK 0x40u 02550 #define LCD_WF8B_BPGLCD14_SHIFT 6 02551 #define LCD_WF8B_BPGLCD55_MASK 0x40u 02552 #define LCD_WF8B_BPGLCD55_SHIFT 6 02553 #define LCD_WF8B_BPGLCD63_MASK 0x40u 02554 #define LCD_WF8B_BPGLCD63_SHIFT 6 02555 #define LCD_WF8B_BPGLCD15_MASK 0x40u 02556 #define LCD_WF8B_BPGLCD15_SHIFT 6 02557 #define LCD_WF8B_BPGLCD62_MASK 0x40u 02558 #define LCD_WF8B_BPGLCD62_SHIFT 6 02559 #define LCD_WF8B_BPGLCD54_MASK 0x40u 02560 #define LCD_WF8B_BPGLCD54_SHIFT 6 02561 #define LCD_WF8B_BPGLCD61_MASK 0x40u 02562 #define LCD_WF8B_BPGLCD61_SHIFT 6 02563 #define LCD_WF8B_BPGLCD60_MASK 0x40u 02564 #define LCD_WF8B_BPGLCD60_SHIFT 6 02565 #define LCD_WF8B_BPGLCD59_MASK 0x40u 02566 #define LCD_WF8B_BPGLCD59_SHIFT 6 02567 #define LCD_WF8B_BPGLCD53_MASK 0x40u 02568 #define LCD_WF8B_BPGLCD53_SHIFT 6 02569 #define LCD_WF8B_BPGLCD58_MASK 0x40u 02570 #define LCD_WF8B_BPGLCD58_SHIFT 6 02571 #define LCD_WF8B_BPGLCD0_MASK 0x40u 02572 #define LCD_WF8B_BPGLCD0_SHIFT 6 02573 #define LCD_WF8B_BPGLCD57_MASK 0x40u 02574 #define LCD_WF8B_BPGLCD57_SHIFT 6 02575 #define LCD_WF8B_BPGLCD52_MASK 0x40u 02576 #define LCD_WF8B_BPGLCD52_SHIFT 6 02577 #define LCD_WF8B_BPGLCD7_MASK 0x40u 02578 #define LCD_WF8B_BPGLCD7_SHIFT 6 02579 #define LCD_WF8B_BPGLCD56_MASK 0x40u 02580 #define LCD_WF8B_BPGLCD56_SHIFT 6 02581 #define LCD_WF8B_BPGLCD6_MASK 0x40u 02582 #define LCD_WF8B_BPGLCD6_SHIFT 6 02583 #define LCD_WF8B_BPGLCD51_MASK 0x40u 02584 #define LCD_WF8B_BPGLCD51_SHIFT 6 02585 #define LCD_WF8B_BPGLCD16_MASK 0x40u 02586 #define LCD_WF8B_BPGLCD16_SHIFT 6 02587 #define LCD_WF8B_BPGLCD1_MASK 0x40u 02588 #define LCD_WF8B_BPGLCD1_SHIFT 6 02589 #define LCD_WF8B_BPGLCD17_MASK 0x40u 02590 #define LCD_WF8B_BPGLCD17_SHIFT 6 02591 #define LCD_WF8B_BPGLCD50_MASK 0x40u 02592 #define LCD_WF8B_BPGLCD50_SHIFT 6 02593 #define LCD_WF8B_BPGLCD18_MASK 0x40u 02594 #define LCD_WF8B_BPGLCD18_SHIFT 6 02595 #define LCD_WF8B_BPGLCD19_MASK 0x40u 02596 #define LCD_WF8B_BPGLCD19_SHIFT 6 02597 #define LCD_WF8B_BPGLCD8_MASK 0x40u 02598 #define LCD_WF8B_BPGLCD8_SHIFT 6 02599 #define LCD_WF8B_BPGLCD49_MASK 0x40u 02600 #define LCD_WF8B_BPGLCD49_SHIFT 6 02601 #define LCD_WF8B_BPGLCD20_MASK 0x40u 02602 #define LCD_WF8B_BPGLCD20_SHIFT 6 02603 #define LCD_WF8B_BPGLCD9_MASK 0x40u 02604 #define LCD_WF8B_BPGLCD9_SHIFT 6 02605 #define LCD_WF8B_BPGLCD21_MASK 0x40u 02606 #define LCD_WF8B_BPGLCD21_SHIFT 6 02607 #define LCD_WF8B_BPGLCD13_MASK 0x40u 02608 #define LCD_WF8B_BPGLCD13_SHIFT 6 02609 #define LCD_WF8B_BPGLCD48_MASK 0x40u 02610 #define LCD_WF8B_BPGLCD48_SHIFT 6 02611 #define LCD_WF8B_BPGLCD22_MASK 0x40u 02612 #define LCD_WF8B_BPGLCD22_SHIFT 6 02613 #define LCD_WF8B_BPGLCD5_MASK 0x40u 02614 #define LCD_WF8B_BPGLCD5_SHIFT 6 02615 #define LCD_WF8B_BPGLCD47_MASK 0x40u 02616 #define LCD_WF8B_BPGLCD47_SHIFT 6 02617 #define LCD_WF8B_BPGLCD23_MASK 0x40u 02618 #define LCD_WF8B_BPGLCD23_SHIFT 6 02619 #define LCD_WF8B_BPGLCD24_MASK 0x40u 02620 #define LCD_WF8B_BPGLCD24_SHIFT 6 02621 #define LCD_WF8B_BPGLCD25_MASK 0x40u 02622 #define LCD_WF8B_BPGLCD25_SHIFT 6 02623 #define LCD_WF8B_BPGLCD46_MASK 0x40u 02624 #define LCD_WF8B_BPGLCD46_SHIFT 6 02625 #define LCD_WF8B_BPGLCD26_MASK 0x40u 02626 #define LCD_WF8B_BPGLCD26_SHIFT 6 02627 #define LCD_WF8B_BPGLCD27_MASK 0x40u 02628 #define LCD_WF8B_BPGLCD27_SHIFT 6 02629 #define LCD_WF8B_BPGLCD10_MASK 0x40u 02630 #define LCD_WF8B_BPGLCD10_SHIFT 6 02631 #define LCD_WF8B_BPGLCD45_MASK 0x40u 02632 #define LCD_WF8B_BPGLCD45_SHIFT 6 02633 #define LCD_WF8B_BPGLCD28_MASK 0x40u 02634 #define LCD_WF8B_BPGLCD28_SHIFT 6 02635 #define LCD_WF8B_BPGLCD29_MASK 0x40u 02636 #define LCD_WF8B_BPGLCD29_SHIFT 6 02637 #define LCD_WF8B_BPGLCD4_MASK 0x40u 02638 #define LCD_WF8B_BPGLCD4_SHIFT 6 02639 #define LCD_WF8B_BPGLCD44_MASK 0x40u 02640 #define LCD_WF8B_BPGLCD44_SHIFT 6 02641 #define LCD_WF8B_BPGLCD30_MASK 0x40u 02642 #define LCD_WF8B_BPGLCD30_SHIFT 6 02643 #define LCD_WF8B_BPGLCD2_MASK 0x40u 02644 #define LCD_WF8B_BPGLCD2_SHIFT 6 02645 #define LCD_WF8B_BPGLCD31_MASK 0x40u 02646 #define LCD_WF8B_BPGLCD31_SHIFT 6 02647 #define LCD_WF8B_BPGLCD43_MASK 0x40u 02648 #define LCD_WF8B_BPGLCD43_SHIFT 6 02649 #define LCD_WF8B_BPGLCD32_MASK 0x40u 02650 #define LCD_WF8B_BPGLCD32_SHIFT 6 02651 #define LCD_WF8B_BPGLCD33_MASK 0x40u 02652 #define LCD_WF8B_BPGLCD33_SHIFT 6 02653 #define LCD_WF8B_BPGLCD42_MASK 0x40u 02654 #define LCD_WF8B_BPGLCD42_SHIFT 6 02655 #define LCD_WF8B_BPGLCD34_MASK 0x40u 02656 #define LCD_WF8B_BPGLCD34_SHIFT 6 02657 #define LCD_WF8B_BPGLCD11_MASK 0x40u 02658 #define LCD_WF8B_BPGLCD11_SHIFT 6 02659 #define LCD_WF8B_BPGLCD35_MASK 0x40u 02660 #define LCD_WF8B_BPGLCD35_SHIFT 6 02661 #define LCD_WF8B_BPGLCD12_MASK 0x40u 02662 #define LCD_WF8B_BPGLCD12_SHIFT 6 02663 #define LCD_WF8B_BPGLCD41_MASK 0x40u 02664 #define LCD_WF8B_BPGLCD41_SHIFT 6 02665 #define LCD_WF8B_BPGLCD36_MASK 0x40u 02666 #define LCD_WF8B_BPGLCD36_SHIFT 6 02667 #define LCD_WF8B_BPGLCD3_MASK 0x40u 02668 #define LCD_WF8B_BPGLCD3_SHIFT 6 02669 #define LCD_WF8B_BPGLCD37_MASK 0x40u 02670 #define LCD_WF8B_BPGLCD37_SHIFT 6 02671 #define LCD_WF8B_BPGLCD40_MASK 0x40u 02672 #define LCD_WF8B_BPGLCD40_SHIFT 6 02673 #define LCD_WF8B_BPGLCD38_MASK 0x40u 02674 #define LCD_WF8B_BPGLCD38_SHIFT 6 02675 #define LCD_WF8B_BPGLCD39_MASK 0x40u 02676 #define LCD_WF8B_BPGLCD39_SHIFT 6 02677 #define LCD_WF8B_BPHLCD63_MASK 0x80u 02678 #define LCD_WF8B_BPHLCD63_SHIFT 7 02679 #define LCD_WF8B_BPHLCD62_MASK 0x80u 02680 #define LCD_WF8B_BPHLCD62_SHIFT 7 02681 #define LCD_WF8B_BPHLCD61_MASK 0x80u 02682 #define LCD_WF8B_BPHLCD61_SHIFT 7 02683 #define LCD_WF8B_BPHLCD60_MASK 0x80u 02684 #define LCD_WF8B_BPHLCD60_SHIFT 7 02685 #define LCD_WF8B_BPHLCD59_MASK 0x80u 02686 #define LCD_WF8B_BPHLCD59_SHIFT 7 02687 #define LCD_WF8B_BPHLCD58_MASK 0x80u 02688 #define LCD_WF8B_BPHLCD58_SHIFT 7 02689 #define LCD_WF8B_BPHLCD57_MASK 0x80u 02690 #define LCD_WF8B_BPHLCD57_SHIFT 7 02691 #define LCD_WF8B_BPHLCD0_MASK 0x80u 02692 #define LCD_WF8B_BPHLCD0_SHIFT 7 02693 #define LCD_WF8B_BPHLCD56_MASK 0x80u 02694 #define LCD_WF8B_BPHLCD56_SHIFT 7 02695 #define LCD_WF8B_BPHLCD55_MASK 0x80u 02696 #define LCD_WF8B_BPHLCD55_SHIFT 7 02697 #define LCD_WF8B_BPHLCD54_MASK 0x80u 02698 #define LCD_WF8B_BPHLCD54_SHIFT 7 02699 #define LCD_WF8B_BPHLCD53_MASK 0x80u 02700 #define LCD_WF8B_BPHLCD53_SHIFT 7 02701 #define LCD_WF8B_BPHLCD52_MASK 0x80u 02702 #define LCD_WF8B_BPHLCD52_SHIFT 7 02703 #define LCD_WF8B_BPHLCD51_MASK 0x80u 02704 #define LCD_WF8B_BPHLCD51_SHIFT 7 02705 #define LCD_WF8B_BPHLCD50_MASK 0x80u 02706 #define LCD_WF8B_BPHLCD50_SHIFT 7 02707 #define LCD_WF8B_BPHLCD1_MASK 0x80u 02708 #define LCD_WF8B_BPHLCD1_SHIFT 7 02709 #define LCD_WF8B_BPHLCD49_MASK 0x80u 02710 #define LCD_WF8B_BPHLCD49_SHIFT 7 02711 #define LCD_WF8B_BPHLCD48_MASK 0x80u 02712 #define LCD_WF8B_BPHLCD48_SHIFT 7 02713 #define LCD_WF8B_BPHLCD47_MASK 0x80u 02714 #define LCD_WF8B_BPHLCD47_SHIFT 7 02715 #define LCD_WF8B_BPHLCD46_MASK 0x80u 02716 #define LCD_WF8B_BPHLCD46_SHIFT 7 02717 #define LCD_WF8B_BPHLCD45_MASK 0x80u 02718 #define LCD_WF8B_BPHLCD45_SHIFT 7 02719 #define LCD_WF8B_BPHLCD44_MASK 0x80u 02720 #define LCD_WF8B_BPHLCD44_SHIFT 7 02721 #define LCD_WF8B_BPHLCD43_MASK 0x80u 02722 #define LCD_WF8B_BPHLCD43_SHIFT 7 02723 #define LCD_WF8B_BPHLCD2_MASK 0x80u 02724 #define LCD_WF8B_BPHLCD2_SHIFT 7 02725 #define LCD_WF8B_BPHLCD42_MASK 0x80u 02726 #define LCD_WF8B_BPHLCD42_SHIFT 7 02727 #define LCD_WF8B_BPHLCD41_MASK 0x80u 02728 #define LCD_WF8B_BPHLCD41_SHIFT 7 02729 #define LCD_WF8B_BPHLCD40_MASK 0x80u 02730 #define LCD_WF8B_BPHLCD40_SHIFT 7 02731 #define LCD_WF8B_BPHLCD39_MASK 0x80u 02732 #define LCD_WF8B_BPHLCD39_SHIFT 7 02733 #define LCD_WF8B_BPHLCD38_MASK 0x80u 02734 #define LCD_WF8B_BPHLCD38_SHIFT 7 02735 #define LCD_WF8B_BPHLCD37_MASK 0x80u 02736 #define LCD_WF8B_BPHLCD37_SHIFT 7 02737 #define LCD_WF8B_BPHLCD36_MASK 0x80u 02738 #define LCD_WF8B_BPHLCD36_SHIFT 7 02739 #define LCD_WF8B_BPHLCD3_MASK 0x80u 02740 #define LCD_WF8B_BPHLCD3_SHIFT 7 02741 #define LCD_WF8B_BPHLCD35_MASK 0x80u 02742 #define LCD_WF8B_BPHLCD35_SHIFT 7 02743 #define LCD_WF8B_BPHLCD34_MASK 0x80u 02744 #define LCD_WF8B_BPHLCD34_SHIFT 7 02745 #define LCD_WF8B_BPHLCD33_MASK 0x80u 02746 #define LCD_WF8B_BPHLCD33_SHIFT 7 02747 #define LCD_WF8B_BPHLCD32_MASK 0x80u 02748 #define LCD_WF8B_BPHLCD32_SHIFT 7 02749 #define LCD_WF8B_BPHLCD31_MASK 0x80u 02750 #define LCD_WF8B_BPHLCD31_SHIFT 7 02751 #define LCD_WF8B_BPHLCD30_MASK 0x80u 02752 #define LCD_WF8B_BPHLCD30_SHIFT 7 02753 #define LCD_WF8B_BPHLCD29_MASK 0x80u 02754 #define LCD_WF8B_BPHLCD29_SHIFT 7 02755 #define LCD_WF8B_BPHLCD4_MASK 0x80u 02756 #define LCD_WF8B_BPHLCD4_SHIFT 7 02757 #define LCD_WF8B_BPHLCD28_MASK 0x80u 02758 #define LCD_WF8B_BPHLCD28_SHIFT 7 02759 #define LCD_WF8B_BPHLCD27_MASK 0x80u 02760 #define LCD_WF8B_BPHLCD27_SHIFT 7 02761 #define LCD_WF8B_BPHLCD26_MASK 0x80u 02762 #define LCD_WF8B_BPHLCD26_SHIFT 7 02763 #define LCD_WF8B_BPHLCD25_MASK 0x80u 02764 #define LCD_WF8B_BPHLCD25_SHIFT 7 02765 #define LCD_WF8B_BPHLCD24_MASK 0x80u 02766 #define LCD_WF8B_BPHLCD24_SHIFT 7 02767 #define LCD_WF8B_BPHLCD23_MASK 0x80u 02768 #define LCD_WF8B_BPHLCD23_SHIFT 7 02769 #define LCD_WF8B_BPHLCD22_MASK 0x80u 02770 #define LCD_WF8B_BPHLCD22_SHIFT 7 02771 #define LCD_WF8B_BPHLCD5_MASK 0x80u 02772 #define LCD_WF8B_BPHLCD5_SHIFT 7 02773 #define LCD_WF8B_BPHLCD21_MASK 0x80u 02774 #define LCD_WF8B_BPHLCD21_SHIFT 7 02775 #define LCD_WF8B_BPHLCD20_MASK 0x80u 02776 #define LCD_WF8B_BPHLCD20_SHIFT 7 02777 #define LCD_WF8B_BPHLCD19_MASK 0x80u 02778 #define LCD_WF8B_BPHLCD19_SHIFT 7 02779 #define LCD_WF8B_BPHLCD18_MASK 0x80u 02780 #define LCD_WF8B_BPHLCD18_SHIFT 7 02781 #define LCD_WF8B_BPHLCD17_MASK 0x80u 02782 #define LCD_WF8B_BPHLCD17_SHIFT 7 02783 #define LCD_WF8B_BPHLCD16_MASK 0x80u 02784 #define LCD_WF8B_BPHLCD16_SHIFT 7 02785 #define LCD_WF8B_BPHLCD15_MASK 0x80u 02786 #define LCD_WF8B_BPHLCD15_SHIFT 7 02787 #define LCD_WF8B_BPHLCD6_MASK 0x80u 02788 #define LCD_WF8B_BPHLCD6_SHIFT 7 02789 #define LCD_WF8B_BPHLCD14_MASK 0x80u 02790 #define LCD_WF8B_BPHLCD14_SHIFT 7 02791 #define LCD_WF8B_BPHLCD13_MASK 0x80u 02792 #define LCD_WF8B_BPHLCD13_SHIFT 7 02793 #define LCD_WF8B_BPHLCD12_MASK 0x80u 02794 #define LCD_WF8B_BPHLCD12_SHIFT 7 02795 #define LCD_WF8B_BPHLCD11_MASK 0x80u 02796 #define LCD_WF8B_BPHLCD11_SHIFT 7 02797 #define LCD_WF8B_BPHLCD10_MASK 0x80u 02798 #define LCD_WF8B_BPHLCD10_SHIFT 7 02799 #define LCD_WF8B_BPHLCD9_MASK 0x80u 02800 #define LCD_WF8B_BPHLCD9_SHIFT 7 02801 #define LCD_WF8B_BPHLCD8_MASK 0x80u 02802 #define LCD_WF8B_BPHLCD8_SHIFT 7 02803 #define LCD_WF8B_BPHLCD7_MASK 0x80u 02804 #define LCD_WF8B_BPHLCD7_SHIFT 7 02805 02806 /*! 02807 * @} 02808 */ /* end of group LCD_Register_Masks */ 02809 02810 02811 /* LCD - Peripheral instance base addresses */ 02812 /** Peripheral LCD base address */ 02813 #define LCD_BASE (0x40053000u) 02814 /** Peripheral LCD base pointer */ 02815 #define LCD ((LCD_Type *)LCD_BASE) 02816 /** Array initializer of LCD peripheral base pointers */ 02817 #define LCD_BASES { LCD } 02818 02819 /*! 02820 * @} 02821 */ /* end of group LCD_Peripheral_Access_Layer */ 02822 02823 02824 /* ---------------------------------------------------------------------------- 02825 -- LLWU Peripheral Access Layer 02826 ---------------------------------------------------------------------------- */ 02827 02828 /*! 02829 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 02830 * @{ 02831 */ 02832 02833 /** LLWU - Register Layout Typedef */ 02834 typedef struct { 02835 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 02836 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 02837 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 02838 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 02839 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ 02840 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ 02841 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ 02842 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ 02843 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ 02844 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ 02845 } LLWU_Type; 02846 02847 /* ---------------------------------------------------------------------------- 02848 -- LLWU Register Masks 02849 ---------------------------------------------------------------------------- */ 02850 02851 /*! 02852 * @addtogroup LLWU_Register_Masks LLWU Register Masks 02853 * @{ 02854 */ 02855 02856 /* PE1 Bit Fields */ 02857 #define LLWU_PE1_WUPE0_MASK 0x3u 02858 #define LLWU_PE1_WUPE0_SHIFT 0 02859 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK) 02860 #define LLWU_PE1_WUPE1_MASK 0xCu 02861 #define LLWU_PE1_WUPE1_SHIFT 2 02862 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK) 02863 #define LLWU_PE1_WUPE2_MASK 0x30u 02864 #define LLWU_PE1_WUPE2_SHIFT 4 02865 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK) 02866 #define LLWU_PE1_WUPE3_MASK 0xC0u 02867 #define LLWU_PE1_WUPE3_SHIFT 6 02868 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK) 02869 /* PE2 Bit Fields */ 02870 #define LLWU_PE2_WUPE4_MASK 0x3u 02871 #define LLWU_PE2_WUPE4_SHIFT 0 02872 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK) 02873 #define LLWU_PE2_WUPE5_MASK 0xCu 02874 #define LLWU_PE2_WUPE5_SHIFT 2 02875 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK) 02876 #define LLWU_PE2_WUPE6_MASK 0x30u 02877 #define LLWU_PE2_WUPE6_SHIFT 4 02878 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK) 02879 #define LLWU_PE2_WUPE7_MASK 0xC0u 02880 #define LLWU_PE2_WUPE7_SHIFT 6 02881 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK) 02882 /* PE3 Bit Fields */ 02883 #define LLWU_PE3_WUPE8_MASK 0x3u 02884 #define LLWU_PE3_WUPE8_SHIFT 0 02885 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK) 02886 #define LLWU_PE3_WUPE9_MASK 0xCu 02887 #define LLWU_PE3_WUPE9_SHIFT 2 02888 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK) 02889 #define LLWU_PE3_WUPE10_MASK 0x30u 02890 #define LLWU_PE3_WUPE10_SHIFT 4 02891 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK) 02892 #define LLWU_PE3_WUPE11_MASK 0xC0u 02893 #define LLWU_PE3_WUPE11_SHIFT 6 02894 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK) 02895 /* PE4 Bit Fields */ 02896 #define LLWU_PE4_WUPE12_MASK 0x3u 02897 #define LLWU_PE4_WUPE12_SHIFT 0 02898 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK) 02899 #define LLWU_PE4_WUPE13_MASK 0xCu 02900 #define LLWU_PE4_WUPE13_SHIFT 2 02901 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK) 02902 #define LLWU_PE4_WUPE14_MASK 0x30u 02903 #define LLWU_PE4_WUPE14_SHIFT 4 02904 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK) 02905 #define LLWU_PE4_WUPE15_MASK 0xC0u 02906 #define LLWU_PE4_WUPE15_SHIFT 6 02907 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK) 02908 /* ME Bit Fields */ 02909 #define LLWU_ME_WUME0_MASK 0x1u 02910 #define LLWU_ME_WUME0_SHIFT 0 02911 #define LLWU_ME_WUME1_MASK 0x2u 02912 #define LLWU_ME_WUME1_SHIFT 1 02913 #define LLWU_ME_WUME2_MASK 0x4u 02914 #define LLWU_ME_WUME2_SHIFT 2 02915 #define LLWU_ME_WUME3_MASK 0x8u 02916 #define LLWU_ME_WUME3_SHIFT 3 02917 #define LLWU_ME_WUME4_MASK 0x10u 02918 #define LLWU_ME_WUME4_SHIFT 4 02919 #define LLWU_ME_WUME5_MASK 0x20u 02920 #define LLWU_ME_WUME5_SHIFT 5 02921 #define LLWU_ME_WUME6_MASK 0x40u 02922 #define LLWU_ME_WUME6_SHIFT 6 02923 #define LLWU_ME_WUME7_MASK 0x80u 02924 #define LLWU_ME_WUME7_SHIFT 7 02925 /* F1 Bit Fields */ 02926 #define LLWU_F1_WUF0_MASK 0x1u 02927 #define LLWU_F1_WUF0_SHIFT 0 02928 #define LLWU_F1_WUF1_MASK 0x2u 02929 #define LLWU_F1_WUF1_SHIFT 1 02930 #define LLWU_F1_WUF2_MASK 0x4u 02931 #define LLWU_F1_WUF2_SHIFT 2 02932 #define LLWU_F1_WUF3_MASK 0x8u 02933 #define LLWU_F1_WUF3_SHIFT 3 02934 #define LLWU_F1_WUF4_MASK 0x10u 02935 #define LLWU_F1_WUF4_SHIFT 4 02936 #define LLWU_F1_WUF5_MASK 0x20u 02937 #define LLWU_F1_WUF5_SHIFT 5 02938 #define LLWU_F1_WUF6_MASK 0x40u 02939 #define LLWU_F1_WUF6_SHIFT 6 02940 #define LLWU_F1_WUF7_MASK 0x80u 02941 #define LLWU_F1_WUF7_SHIFT 7 02942 /* F2 Bit Fields */ 02943 #define LLWU_F2_WUF8_MASK 0x1u 02944 #define LLWU_F2_WUF8_SHIFT 0 02945 #define LLWU_F2_WUF9_MASK 0x2u 02946 #define LLWU_F2_WUF9_SHIFT 1 02947 #define LLWU_F2_WUF10_MASK 0x4u 02948 #define LLWU_F2_WUF10_SHIFT 2 02949 #define LLWU_F2_WUF11_MASK 0x8u 02950 #define LLWU_F2_WUF11_SHIFT 3 02951 #define LLWU_F2_WUF12_MASK 0x10u 02952 #define LLWU_F2_WUF12_SHIFT 4 02953 #define LLWU_F2_WUF13_MASK 0x20u 02954 #define LLWU_F2_WUF13_SHIFT 5 02955 #define LLWU_F2_WUF14_MASK 0x40u 02956 #define LLWU_F2_WUF14_SHIFT 6 02957 #define LLWU_F2_WUF15_MASK 0x80u 02958 #define LLWU_F2_WUF15_SHIFT 7 02959 /* F3 Bit Fields */ 02960 #define LLWU_F3_MWUF0_MASK 0x1u 02961 #define LLWU_F3_MWUF0_SHIFT 0 02962 #define LLWU_F3_MWUF1_MASK 0x2u 02963 #define LLWU_F3_MWUF1_SHIFT 1 02964 #define LLWU_F3_MWUF2_MASK 0x4u 02965 #define LLWU_F3_MWUF2_SHIFT 2 02966 #define LLWU_F3_MWUF3_MASK 0x8u 02967 #define LLWU_F3_MWUF3_SHIFT 3 02968 #define LLWU_F3_MWUF4_MASK 0x10u 02969 #define LLWU_F3_MWUF4_SHIFT 4 02970 #define LLWU_F3_MWUF5_MASK 0x20u 02971 #define LLWU_F3_MWUF5_SHIFT 5 02972 #define LLWU_F3_MWUF6_MASK 0x40u 02973 #define LLWU_F3_MWUF6_SHIFT 6 02974 #define LLWU_F3_MWUF7_MASK 0x80u 02975 #define LLWU_F3_MWUF7_SHIFT 7 02976 /* FILT1 Bit Fields */ 02977 #define LLWU_FILT1_FILTSEL_MASK 0xFu 02978 #define LLWU_FILT1_FILTSEL_SHIFT 0 02979 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK) 02980 #define LLWU_FILT1_FILTE_MASK 0x60u 02981 #define LLWU_FILT1_FILTE_SHIFT 5 02982 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK) 02983 #define LLWU_FILT1_FILTF_MASK 0x80u 02984 #define LLWU_FILT1_FILTF_SHIFT 7 02985 /* FILT2 Bit Fields */ 02986 #define LLWU_FILT2_FILTSEL_MASK 0xFu 02987 #define LLWU_FILT2_FILTSEL_SHIFT 0 02988 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK) 02989 #define LLWU_FILT2_FILTE_MASK 0x60u 02990 #define LLWU_FILT2_FILTE_SHIFT 5 02991 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK) 02992 #define LLWU_FILT2_FILTF_MASK 0x80u 02993 #define LLWU_FILT2_FILTF_SHIFT 7 02994 02995 /*! 02996 * @} 02997 */ /* end of group LLWU_Register_Masks */ 02998 02999 03000 /* LLWU - Peripheral instance base addresses */ 03001 /** Peripheral LLWU base address */ 03002 #define LLWU_BASE (0x4007C000u) 03003 /** Peripheral LLWU base pointer */ 03004 #define LLWU ((LLWU_Type *)LLWU_BASE) 03005 /** Array initializer of LLWU peripheral base pointers */ 03006 #define LLWU_BASES { LLWU } 03007 03008 /*! 03009 * @} 03010 */ /* end of group LLWU_Peripheral_Access_Layer */ 03011 03012 03013 /* ---------------------------------------------------------------------------- 03014 -- LPTMR Peripheral Access Layer 03015 ---------------------------------------------------------------------------- */ 03016 03017 /*! 03018 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 03019 * @{ 03020 */ 03021 03022 /** LPTMR - Register Layout Typedef */ 03023 typedef struct { 03024 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 03025 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 03026 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 03027 __I uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 03028 } LPTMR_Type; 03029 03030 /* ---------------------------------------------------------------------------- 03031 -- LPTMR Register Masks 03032 ---------------------------------------------------------------------------- */ 03033 03034 /*! 03035 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 03036 * @{ 03037 */ 03038 03039 /* CSR Bit Fields */ 03040 #define LPTMR_CSR_TEN_MASK 0x1u 03041 #define LPTMR_CSR_TEN_SHIFT 0 03042 #define LPTMR_CSR_TMS_MASK 0x2u 03043 #define LPTMR_CSR_TMS_SHIFT 1 03044 #define LPTMR_CSR_TFC_MASK 0x4u 03045 #define LPTMR_CSR_TFC_SHIFT 2 03046 #define LPTMR_CSR_TPP_MASK 0x8u 03047 #define LPTMR_CSR_TPP_SHIFT 3 03048 #define LPTMR_CSR_TPS_MASK 0x30u 03049 #define LPTMR_CSR_TPS_SHIFT 4 03050 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK) 03051 #define LPTMR_CSR_TIE_MASK 0x40u 03052 #define LPTMR_CSR_TIE_SHIFT 6 03053 #define LPTMR_CSR_TCF_MASK 0x80u 03054 #define LPTMR_CSR_TCF_SHIFT 7 03055 /* PSR Bit Fields */ 03056 #define LPTMR_PSR_PCS_MASK 0x3u 03057 #define LPTMR_PSR_PCS_SHIFT 0 03058 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK) 03059 #define LPTMR_PSR_PBYP_MASK 0x4u 03060 #define LPTMR_PSR_PBYP_SHIFT 2 03061 #define LPTMR_PSR_PRESCALE_MASK 0x78u 03062 #define LPTMR_PSR_PRESCALE_SHIFT 3 03063 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK) 03064 /* CMR Bit Fields */ 03065 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu 03066 #define LPTMR_CMR_COMPARE_SHIFT 0 03067 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK) 03068 /* CNR Bit Fields */ 03069 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu 03070 #define LPTMR_CNR_COUNTER_SHIFT 0 03071 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK) 03072 03073 /*! 03074 * @} 03075 */ /* end of group LPTMR_Register_Masks */ 03076 03077 03078 /* LPTMR - Peripheral instance base addresses */ 03079 /** Peripheral LPTMR0 base address */ 03080 #define LPTMR0_BASE (0x40040000u) 03081 /** Peripheral LPTMR0 base pointer */ 03082 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) 03083 /** Array initializer of LPTMR peripheral base pointers */ 03084 #define LPTMR_BASES { LPTMR0 } 03085 03086 /*! 03087 * @} 03088 */ /* end of group LPTMR_Peripheral_Access_Layer */ 03089 03090 03091 /* ---------------------------------------------------------------------------- 03092 -- MCG Peripheral Access Layer 03093 ---------------------------------------------------------------------------- */ 03094 03095 /*! 03096 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 03097 * @{ 03098 */ 03099 03100 /** MCG - Register Layout Typedef */ 03101 typedef struct { 03102 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 03103 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 03104 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 03105 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 03106 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ 03107 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 03108 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */ 03109 uint8_t RESERVED_0[1]; 03110 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 03111 uint8_t RESERVED_1[1]; 03112 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 03113 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 03114 __I uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ 03115 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ 03116 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */ 03117 __I uint8_t C10; /**< MCG Control 10 Register, offset: 0xF */ 03118 } MCG_Type; 03119 03120 /* ---------------------------------------------------------------------------- 03121 -- MCG Register Masks 03122 ---------------------------------------------------------------------------- */ 03123 03124 /*! 03125 * @addtogroup MCG_Register_Masks MCG Register Masks 03126 * @{ 03127 */ 03128 03129 /* C1 Bit Fields */ 03130 #define MCG_C1_IREFSTEN_MASK 0x1u 03131 #define MCG_C1_IREFSTEN_SHIFT 0 03132 #define MCG_C1_IRCLKEN_MASK 0x2u 03133 #define MCG_C1_IRCLKEN_SHIFT 1 03134 #define MCG_C1_IREFS_MASK 0x4u 03135 #define MCG_C1_IREFS_SHIFT 2 03136 #define MCG_C1_FRDIV_MASK 0x38u 03137 #define MCG_C1_FRDIV_SHIFT 3 03138 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK) 03139 #define MCG_C1_CLKS_MASK 0xC0u 03140 #define MCG_C1_CLKS_SHIFT 6 03141 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK) 03142 /* C2 Bit Fields */ 03143 #define MCG_C2_IRCS_MASK 0x1u 03144 #define MCG_C2_IRCS_SHIFT 0 03145 #define MCG_C2_LP_MASK 0x2u 03146 #define MCG_C2_LP_SHIFT 1 03147 #define MCG_C2_EREFS0_MASK 0x4u 03148 #define MCG_C2_EREFS0_SHIFT 2 03149 #define MCG_C2_HGO0_MASK 0x8u 03150 #define MCG_C2_HGO0_SHIFT 3 03151 #define MCG_C2_RANGE0_MASK 0x30u 03152 #define MCG_C2_RANGE0_SHIFT 4 03153 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK) 03154 #define MCG_C2_FCFTRIM_MASK 0x40u 03155 #define MCG_C2_FCFTRIM_SHIFT 6 03156 #define MCG_C2_LOCRE0_MASK 0x80u 03157 #define MCG_C2_LOCRE0_SHIFT 7 03158 /* C3 Bit Fields */ 03159 #define MCG_C3_SCTRIM_MASK 0xFFu 03160 #define MCG_C3_SCTRIM_SHIFT 0 03161 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK) 03162 /* C4 Bit Fields */ 03163 #define MCG_C4_SCFTRIM_MASK 0x1u 03164 #define MCG_C4_SCFTRIM_SHIFT 0 03165 #define MCG_C4_FCTRIM_MASK 0x1Eu 03166 #define MCG_C4_FCTRIM_SHIFT 1 03167 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK) 03168 #define MCG_C4_DRST_DRS_MASK 0x60u 03169 #define MCG_C4_DRST_DRS_SHIFT 5 03170 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK) 03171 #define MCG_C4_DMX32_MASK 0x80u 03172 #define MCG_C4_DMX32_SHIFT 7 03173 /* C5 Bit Fields */ 03174 #define MCG_C5_PRDIV0_MASK 0x1Fu 03175 #define MCG_C5_PRDIV0_SHIFT 0 03176 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK) 03177 #define MCG_C5_PLLSTEN0_MASK 0x20u 03178 #define MCG_C5_PLLSTEN0_SHIFT 5 03179 #define MCG_C5_PLLCLKEN0_MASK 0x40u 03180 #define MCG_C5_PLLCLKEN0_SHIFT 6 03181 /* C6 Bit Fields */ 03182 #define MCG_C6_VDIV0_MASK 0x1Fu 03183 #define MCG_C6_VDIV0_SHIFT 0 03184 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK) 03185 #define MCG_C6_CME0_MASK 0x20u 03186 #define MCG_C6_CME0_SHIFT 5 03187 #define MCG_C6_PLLS_MASK 0x40u 03188 #define MCG_C6_PLLS_SHIFT 6 03189 #define MCG_C6_LOLIE0_MASK 0x80u 03190 #define MCG_C6_LOLIE0_SHIFT 7 03191 /* S Bit Fields */ 03192 #define MCG_S_IRCST_MASK 0x1u 03193 #define MCG_S_IRCST_SHIFT 0 03194 #define MCG_S_OSCINIT0_MASK 0x2u 03195 #define MCG_S_OSCINIT0_SHIFT 1 03196 #define MCG_S_CLKST_MASK 0xCu 03197 #define MCG_S_CLKST_SHIFT 2 03198 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK) 03199 #define MCG_S_IREFST_MASK 0x10u 03200 #define MCG_S_IREFST_SHIFT 4 03201 #define MCG_S_PLLST_MASK 0x20u 03202 #define MCG_S_PLLST_SHIFT 5 03203 #define MCG_S_LOCK0_MASK 0x40u 03204 #define MCG_S_LOCK0_SHIFT 6 03205 #define MCG_S_LOLS_MASK 0x80u 03206 #define MCG_S_LOLS_SHIFT 7 03207 /* SC Bit Fields */ 03208 #define MCG_SC_LOCS0_MASK 0x1u 03209 #define MCG_SC_LOCS0_SHIFT 0 03210 #define MCG_SC_FCRDIV_MASK 0xEu 03211 #define MCG_SC_FCRDIV_SHIFT 1 03212 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK) 03213 #define MCG_SC_FLTPRSRV_MASK 0x10u 03214 #define MCG_SC_FLTPRSRV_SHIFT 4 03215 #define MCG_SC_ATMF_MASK 0x20u 03216 #define MCG_SC_ATMF_SHIFT 5 03217 #define MCG_SC_ATMS_MASK 0x40u 03218 #define MCG_SC_ATMS_SHIFT 6 03219 #define MCG_SC_ATME_MASK 0x80u 03220 #define MCG_SC_ATME_SHIFT 7 03221 /* ATCVH Bit Fields */ 03222 #define MCG_ATCVH_ATCVH_MASK 0xFFu 03223 #define MCG_ATCVH_ATCVH_SHIFT 0 03224 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK) 03225 /* ATCVL Bit Fields */ 03226 #define MCG_ATCVL_ATCVL_MASK 0xFFu 03227 #define MCG_ATCVL_ATCVL_SHIFT 0 03228 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK) 03229 /* C8 Bit Fields */ 03230 #define MCG_C8_LOLRE_MASK 0x40u 03231 #define MCG_C8_LOLRE_SHIFT 6 03232 03233 /*! 03234 * @} 03235 */ /* end of group MCG_Register_Masks */ 03236 03237 03238 /* MCG - Peripheral instance base addresses */ 03239 /** Peripheral MCG base address */ 03240 #define MCG_BASE (0x40064000u) 03241 /** Peripheral MCG base pointer */ 03242 #define MCG ((MCG_Type *)MCG_BASE) 03243 /** Array initializer of MCG peripheral base pointers */ 03244 #define MCG_BASES { MCG } 03245 03246 /*! 03247 * @} 03248 */ /* end of group MCG_Peripheral_Access_Layer */ 03249 03250 03251 /* ---------------------------------------------------------------------------- 03252 -- MCM Peripheral Access Layer 03253 ---------------------------------------------------------------------------- */ 03254 03255 /*! 03256 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 03257 * @{ 03258 */ 03259 03260 /** MCM - Register Layout Typedef */ 03261 typedef struct { 03262 uint8_t RESERVED_0[8]; 03263 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 03264 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 03265 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 03266 uint8_t RESERVED_1[48]; 03267 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 03268 } MCM_Type; 03269 03270 /* ---------------------------------------------------------------------------- 03271 -- MCM Register Masks 03272 ---------------------------------------------------------------------------- */ 03273 03274 /*! 03275 * @addtogroup MCM_Register_Masks MCM Register Masks 03276 * @{ 03277 */ 03278 03279 /* PLASC Bit Fields */ 03280 #define MCM_PLASC_ASC_MASK 0xFFu 03281 #define MCM_PLASC_ASC_SHIFT 0 03282 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK) 03283 /* PLAMC Bit Fields */ 03284 #define MCM_PLAMC_AMC_MASK 0xFFu 03285 #define MCM_PLAMC_AMC_SHIFT 0 03286 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK) 03287 /* PLACR Bit Fields */ 03288 #define MCM_PLACR_ARB_MASK 0x200u 03289 #define MCM_PLACR_ARB_SHIFT 9 03290 #define MCM_PLACR_CFCC_MASK 0x400u 03291 #define MCM_PLACR_CFCC_SHIFT 10 03292 #define MCM_PLACR_DFCDA_MASK 0x800u 03293 #define MCM_PLACR_DFCDA_SHIFT 11 03294 #define MCM_PLACR_DFCIC_MASK 0x1000u 03295 #define MCM_PLACR_DFCIC_SHIFT 12 03296 #define MCM_PLACR_DFCC_MASK 0x2000u 03297 #define MCM_PLACR_DFCC_SHIFT 13 03298 #define MCM_PLACR_EFDS_MASK 0x4000u 03299 #define MCM_PLACR_EFDS_SHIFT 14 03300 #define MCM_PLACR_DFCS_MASK 0x8000u 03301 #define MCM_PLACR_DFCS_SHIFT 15 03302 #define MCM_PLACR_ESFC_MASK 0x10000u 03303 #define MCM_PLACR_ESFC_SHIFT 16 03304 /* CPO Bit Fields */ 03305 #define MCM_CPO_CPOREQ_MASK 0x1u 03306 #define MCM_CPO_CPOREQ_SHIFT 0 03307 #define MCM_CPO_CPOACK_MASK 0x2u 03308 #define MCM_CPO_CPOACK_SHIFT 1 03309 #define MCM_CPO_CPOWOI_MASK 0x4u 03310 #define MCM_CPO_CPOWOI_SHIFT 2 03311 03312 /*! 03313 * @} 03314 */ /* end of group MCM_Register_Masks */ 03315 03316 03317 /* MCM - Peripheral instance base addresses */ 03318 /** Peripheral MCM base address */ 03319 #define MCM_BASE (0xF0003000u) 03320 /** Peripheral MCM base pointer */ 03321 #define MCM ((MCM_Type *)MCM_BASE) 03322 /** Array initializer of MCM peripheral base pointers */ 03323 #define MCM_BASES { MCM } 03324 03325 /*! 03326 * @} 03327 */ /* end of group MCM_Peripheral_Access_Layer */ 03328 03329 03330 /* ---------------------------------------------------------------------------- 03331 -- MTB Peripheral Access Layer 03332 ---------------------------------------------------------------------------- */ 03333 03334 /*! 03335 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 03336 * @{ 03337 */ 03338 03339 /** MTB - Register Layout Typedef */ 03340 typedef struct { 03341 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 03342 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 03343 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 03344 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 03345 uint8_t RESERVED_0[3824]; 03346 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 03347 uint8_t RESERVED_1[156]; 03348 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 03349 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 03350 uint8_t RESERVED_2[8]; 03351 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 03352 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 03353 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 03354 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 03355 uint8_t RESERVED_3[8]; 03356 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 03357 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 03358 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ 03359 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 03360 } MTB_Type; 03361 03362 /* ---------------------------------------------------------------------------- 03363 -- MTB Register Masks 03364 ---------------------------------------------------------------------------- */ 03365 03366 /*! 03367 * @addtogroup MTB_Register_Masks MTB Register Masks 03368 * @{ 03369 */ 03370 03371 /* POSITION Bit Fields */ 03372 #define MTB_POSITION_WRAP_MASK 0x4u 03373 #define MTB_POSITION_WRAP_SHIFT 2 03374 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u 03375 #define MTB_POSITION_POINTER_SHIFT 3 03376 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK) 03377 /* MASTER Bit Fields */ 03378 #define MTB_MASTER_MASK_MASK 0x1Fu 03379 #define MTB_MASTER_MASK_SHIFT 0 03380 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK) 03381 #define MTB_MASTER_TSTARTEN_MASK 0x20u 03382 #define MTB_MASTER_TSTARTEN_SHIFT 5 03383 #define MTB_MASTER_TSTOPEN_MASK 0x40u 03384 #define MTB_MASTER_TSTOPEN_SHIFT 6 03385 #define MTB_MASTER_SFRWPRIV_MASK 0x80u 03386 #define MTB_MASTER_SFRWPRIV_SHIFT 7 03387 #define MTB_MASTER_RAMPRIV_MASK 0x100u 03388 #define MTB_MASTER_RAMPRIV_SHIFT 8 03389 #define MTB_MASTER_HALTREQ_MASK 0x200u 03390 #define MTB_MASTER_HALTREQ_SHIFT 9 03391 #define MTB_MASTER_EN_MASK 0x80000000u 03392 #define MTB_MASTER_EN_SHIFT 31 03393 /* FLOW Bit Fields */ 03394 #define MTB_FLOW_AUTOSTOP_MASK 0x1u 03395 #define MTB_FLOW_AUTOSTOP_SHIFT 0 03396 #define MTB_FLOW_AUTOHALT_MASK 0x2u 03397 #define MTB_FLOW_AUTOHALT_SHIFT 1 03398 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u 03399 #define MTB_FLOW_WATERMARK_SHIFT 3 03400 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK) 03401 /* BASE Bit Fields */ 03402 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu 03403 #define MTB_BASE_BASEADDR_SHIFT 0 03404 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK) 03405 /* MODECTRL Bit Fields */ 03406 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu 03407 #define MTB_MODECTRL_MODECTRL_SHIFT 0 03408 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK) 03409 /* TAGSET Bit Fields */ 03410 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu 03411 #define MTB_TAGSET_TAGSET_SHIFT 0 03412 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK) 03413 /* TAGCLEAR Bit Fields */ 03414 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu 03415 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0 03416 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK) 03417 /* LOCKACCESS Bit Fields */ 03418 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu 03419 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0 03420 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK) 03421 /* LOCKSTAT Bit Fields */ 03422 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu 03423 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0 03424 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK) 03425 /* AUTHSTAT Bit Fields */ 03426 #define MTB_AUTHSTAT_BIT0_MASK 0x1u 03427 #define MTB_AUTHSTAT_BIT0_SHIFT 0 03428 #define MTB_AUTHSTAT_BIT1_MASK 0x2u 03429 #define MTB_AUTHSTAT_BIT1_SHIFT 1 03430 #define MTB_AUTHSTAT_BIT2_MASK 0x4u 03431 #define MTB_AUTHSTAT_BIT2_SHIFT 2 03432 #define MTB_AUTHSTAT_BIT3_MASK 0x8u 03433 #define MTB_AUTHSTAT_BIT3_SHIFT 3 03434 /* DEVICEARCH Bit Fields */ 03435 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu 03436 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0 03437 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK) 03438 /* DEVICECFG Bit Fields */ 03439 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu 03440 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0 03441 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK) 03442 /* DEVICETYPID Bit Fields */ 03443 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu 03444 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0 03445 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK) 03446 /* PERIPHID Bit Fields */ 03447 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu 03448 #define MTB_PERIPHID_PERIPHID_SHIFT 0 03449 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK) 03450 /* COMPID Bit Fields */ 03451 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu 03452 #define MTB_COMPID_COMPID_SHIFT 0 03453 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK) 03454 03455 /*! 03456 * @} 03457 */ /* end of group MTB_Register_Masks */ 03458 03459 03460 /* MTB - Peripheral instance base addresses */ 03461 /** Peripheral MTB base address */ 03462 #define MTB_BASE (0xF0000000u) 03463 /** Peripheral MTB base pointer */ 03464 #define MTB ((MTB_Type *)MTB_BASE) 03465 /** Array initializer of MTB peripheral base pointers */ 03466 #define MTB_BASES { MTB } 03467 03468 /*! 03469 * @} 03470 */ /* end of group MTB_Peripheral_Access_Layer */ 03471 03472 03473 /* ---------------------------------------------------------------------------- 03474 -- MTBDWT Peripheral Access Layer 03475 ---------------------------------------------------------------------------- */ 03476 03477 /*! 03478 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer 03479 * @{ 03480 */ 03481 03482 /** MTBDWT - Register Layout Typedef */ 03483 typedef struct { 03484 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 03485 uint8_t RESERVED_0[28]; 03486 struct { /* offset: 0x20, array step: 0x10 */ 03487 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 03488 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 03489 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 03490 uint8_t RESERVED_0[4]; 03491 } COMPARATOR[2]; 03492 uint8_t RESERVED_1[448]; 03493 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 03494 uint8_t RESERVED_2[3524]; 03495 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 03496 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 03497 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */ 03498 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 03499 } MTBDWT_Type; 03500 03501 /* ---------------------------------------------------------------------------- 03502 -- MTBDWT Register Masks 03503 ---------------------------------------------------------------------------- */ 03504 03505 /*! 03506 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 03507 * @{ 03508 */ 03509 03510 /* CTRL Bit Fields */ 03511 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu 03512 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0 03513 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK) 03514 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u 03515 #define MTBDWT_CTRL_NUMCMP_SHIFT 28 03516 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK) 03517 /* COMP Bit Fields */ 03518 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu 03519 #define MTBDWT_COMP_COMP_SHIFT 0 03520 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK) 03521 /* MASK Bit Fields */ 03522 #define MTBDWT_MASK_MASK_MASK 0x1Fu 03523 #define MTBDWT_MASK_MASK_SHIFT 0 03524 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK) 03525 /* FCT Bit Fields */ 03526 #define MTBDWT_FCT_FUNCTION_MASK 0xFu 03527 #define MTBDWT_FCT_FUNCTION_SHIFT 0 03528 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK) 03529 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u 03530 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8 03531 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u 03532 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10 03533 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK) 03534 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u 03535 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12 03536 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK) 03537 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u 03538 #define MTBDWT_FCT_MATCHED_SHIFT 24 03539 /* TBCTRL Bit Fields */ 03540 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u 03541 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0 03542 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u 03543 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1 03544 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u 03545 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28 03546 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK) 03547 /* DEVICECFG Bit Fields */ 03548 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu 03549 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0 03550 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK) 03551 /* DEVICETYPID Bit Fields */ 03552 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu 03553 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0 03554 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 03555 /* PERIPHID Bit Fields */ 03556 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu 03557 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0 03558 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK) 03559 /* COMPID Bit Fields */ 03560 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu 03561 #define MTBDWT_COMPID_COMPID_SHIFT 0 03562 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK) 03563 03564 /*! 03565 * @} 03566 */ /* end of group MTBDWT_Register_Masks */ 03567 03568 03569 /* MTBDWT - Peripheral instance base addresses */ 03570 /** Peripheral MTBDWT base address */ 03571 #define MTBDWT_BASE (0xF0001000u) 03572 /** Peripheral MTBDWT base pointer */ 03573 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) 03574 /** Array initializer of MTBDWT peripheral base pointers */ 03575 #define MTBDWT_BASES { MTBDWT } 03576 03577 /*! 03578 * @} 03579 */ /* end of group MTBDWT_Peripheral_Access_Layer */ 03580 03581 03582 /* ---------------------------------------------------------------------------- 03583 -- NV Peripheral Access Layer 03584 ---------------------------------------------------------------------------- */ 03585 03586 /*! 03587 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 03588 * @{ 03589 */ 03590 03591 /** NV - Register Layout Typedef */ 03592 typedef struct { 03593 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 03594 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 03595 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 03596 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 03597 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 03598 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 03599 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 03600 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 03601 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 03602 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 03603 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 03604 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 03605 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 03606 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 03607 } NV_Type; 03608 03609 /* ---------------------------------------------------------------------------- 03610 -- NV Register Masks 03611 ---------------------------------------------------------------------------- */ 03612 03613 /*! 03614 * @addtogroup NV_Register_Masks NV Register Masks 03615 * @{ 03616 */ 03617 03618 /* BACKKEY3 Bit Fields */ 03619 #define NV_BACKKEY3_KEY_MASK 0xFFu 03620 #define NV_BACKKEY3_KEY_SHIFT 0 03621 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK) 03622 /* BACKKEY2 Bit Fields */ 03623 #define NV_BACKKEY2_KEY_MASK 0xFFu 03624 #define NV_BACKKEY2_KEY_SHIFT 0 03625 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK) 03626 /* BACKKEY1 Bit Fields */ 03627 #define NV_BACKKEY1_KEY_MASK 0xFFu 03628 #define NV_BACKKEY1_KEY_SHIFT 0 03629 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK) 03630 /* BACKKEY0 Bit Fields */ 03631 #define NV_BACKKEY0_KEY_MASK 0xFFu 03632 #define NV_BACKKEY0_KEY_SHIFT 0 03633 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK) 03634 /* BACKKEY7 Bit Fields */ 03635 #define NV_BACKKEY7_KEY_MASK 0xFFu 03636 #define NV_BACKKEY7_KEY_SHIFT 0 03637 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK) 03638 /* BACKKEY6 Bit Fields */ 03639 #define NV_BACKKEY6_KEY_MASK 0xFFu 03640 #define NV_BACKKEY6_KEY_SHIFT 0 03641 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK) 03642 /* BACKKEY5 Bit Fields */ 03643 #define NV_BACKKEY5_KEY_MASK 0xFFu 03644 #define NV_BACKKEY5_KEY_SHIFT 0 03645 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK) 03646 /* BACKKEY4 Bit Fields */ 03647 #define NV_BACKKEY4_KEY_MASK 0xFFu 03648 #define NV_BACKKEY4_KEY_SHIFT 0 03649 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK) 03650 /* FPROT3 Bit Fields */ 03651 #define NV_FPROT3_PROT_MASK 0xFFu 03652 #define NV_FPROT3_PROT_SHIFT 0 03653 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK) 03654 /* FPROT2 Bit Fields */ 03655 #define NV_FPROT2_PROT_MASK 0xFFu 03656 #define NV_FPROT2_PROT_SHIFT 0 03657 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK) 03658 /* FPROT1 Bit Fields */ 03659 #define NV_FPROT1_PROT_MASK 0xFFu 03660 #define NV_FPROT1_PROT_SHIFT 0 03661 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK) 03662 /* FPROT0 Bit Fields */ 03663 #define NV_FPROT0_PROT_MASK 0xFFu 03664 #define NV_FPROT0_PROT_SHIFT 0 03665 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK) 03666 /* FSEC Bit Fields */ 03667 #define NV_FSEC_SEC_MASK 0x3u 03668 #define NV_FSEC_SEC_SHIFT 0 03669 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK) 03670 #define NV_FSEC_FSLACC_MASK 0xCu 03671 #define NV_FSEC_FSLACC_SHIFT 2 03672 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK) 03673 #define NV_FSEC_MEEN_MASK 0x30u 03674 #define NV_FSEC_MEEN_SHIFT 4 03675 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK) 03676 #define NV_FSEC_KEYEN_MASK 0xC0u 03677 #define NV_FSEC_KEYEN_SHIFT 6 03678 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK) 03679 /* FOPT Bit Fields */ 03680 #define NV_FOPT_LPBOOT0_MASK 0x1u 03681 #define NV_FOPT_LPBOOT0_SHIFT 0 03682 #define NV_FOPT_NMI_DIS_MASK 0x4u 03683 #define NV_FOPT_NMI_DIS_SHIFT 2 03684 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u 03685 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3 03686 #define NV_FOPT_LPBOOT1_MASK 0x10u 03687 #define NV_FOPT_LPBOOT1_SHIFT 4 03688 #define NV_FOPT_FAST_INIT_MASK 0x20u 03689 #define NV_FOPT_FAST_INIT_SHIFT 5 03690 03691 /*! 03692 * @} 03693 */ /* end of group NV_Register_Masks */ 03694 03695 03696 /* NV - Peripheral instance base addresses */ 03697 /** Peripheral FTFA_FlashConfig base address */ 03698 #define FTFA_FlashConfig_BASE (0x400u) 03699 /** Peripheral FTFA_FlashConfig base pointer */ 03700 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) 03701 /** Array initializer of NV peripheral base pointers */ 03702 #define NV_BASES { FTFA_FlashConfig } 03703 03704 /*! 03705 * @} 03706 */ /* end of group NV_Peripheral_Access_Layer */ 03707 03708 03709 /* ---------------------------------------------------------------------------- 03710 -- OSC Peripheral Access Layer 03711 ---------------------------------------------------------------------------- */ 03712 03713 /*! 03714 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 03715 * @{ 03716 */ 03717 03718 /** OSC - Register Layout Typedef */ 03719 typedef struct { 03720 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 03721 } OSC_Type; 03722 03723 /* ---------------------------------------------------------------------------- 03724 -- OSC Register Masks 03725 ---------------------------------------------------------------------------- */ 03726 03727 /*! 03728 * @addtogroup OSC_Register_Masks OSC Register Masks 03729 * @{ 03730 */ 03731 03732 /* CR Bit Fields */ 03733 #define OSC_CR_SC16P_MASK 0x1u 03734 #define OSC_CR_SC16P_SHIFT 0 03735 #define OSC_CR_SC8P_MASK 0x2u 03736 #define OSC_CR_SC8P_SHIFT 1 03737 #define OSC_CR_SC4P_MASK 0x4u 03738 #define OSC_CR_SC4P_SHIFT 2 03739 #define OSC_CR_SC2P_MASK 0x8u 03740 #define OSC_CR_SC2P_SHIFT 3 03741 #define OSC_CR_EREFSTEN_MASK 0x20u 03742 #define OSC_CR_EREFSTEN_SHIFT 5 03743 #define OSC_CR_ERCLKEN_MASK 0x80u 03744 #define OSC_CR_ERCLKEN_SHIFT 7 03745 03746 /*! 03747 * @} 03748 */ /* end of group OSC_Register_Masks */ 03749 03750 03751 /* OSC - Peripheral instance base addresses */ 03752 /** Peripheral OSC0 base address */ 03753 #define OSC0_BASE (0x40065000u) 03754 /** Peripheral OSC0 base pointer */ 03755 #define OSC0 ((OSC_Type *)OSC0_BASE) 03756 /** Array initializer of OSC peripheral base pointers */ 03757 #define OSC_BASES { OSC0 } 03758 03759 /*! 03760 * @} 03761 */ /* end of group OSC_Peripheral_Access_Layer */ 03762 03763 03764 /* ---------------------------------------------------------------------------- 03765 -- PIT Peripheral Access Layer 03766 ---------------------------------------------------------------------------- */ 03767 03768 /*! 03769 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 03770 * @{ 03771 */ 03772 03773 /** PIT - Register Layout Typedef */ 03774 typedef struct { 03775 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 03776 uint8_t RESERVED_0[220]; 03777 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ 03778 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ 03779 uint8_t RESERVED_1[24]; 03780 struct { /* offset: 0x100, array step: 0x10 */ 03781 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 03782 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 03783 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 03784 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 03785 } CHANNEL[2]; 03786 } PIT_Type; 03787 03788 /* ---------------------------------------------------------------------------- 03789 -- PIT Register Masks 03790 ---------------------------------------------------------------------------- */ 03791 03792 /*! 03793 * @addtogroup PIT_Register_Masks PIT Register Masks 03794 * @{ 03795 */ 03796 03797 /* MCR Bit Fields */ 03798 #define PIT_MCR_FRZ_MASK 0x1u 03799 #define PIT_MCR_FRZ_SHIFT 0 03800 #define PIT_MCR_MDIS_MASK 0x2u 03801 #define PIT_MCR_MDIS_SHIFT 1 03802 /* LTMR64H Bit Fields */ 03803 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu 03804 #define PIT_LTMR64H_LTH_SHIFT 0 03805 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK) 03806 /* LTMR64L Bit Fields */ 03807 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu 03808 #define PIT_LTMR64L_LTL_SHIFT 0 03809 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK) 03810 /* LDVAL Bit Fields */ 03811 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu 03812 #define PIT_LDVAL_TSV_SHIFT 0 03813 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK) 03814 /* CVAL Bit Fields */ 03815 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu 03816 #define PIT_CVAL_TVL_SHIFT 0 03817 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK) 03818 /* TCTRL Bit Fields */ 03819 #define PIT_TCTRL_TEN_MASK 0x1u 03820 #define PIT_TCTRL_TEN_SHIFT 0 03821 #define PIT_TCTRL_TIE_MASK 0x2u 03822 #define PIT_TCTRL_TIE_SHIFT 1 03823 #define PIT_TCTRL_CHN_MASK 0x4u 03824 #define PIT_TCTRL_CHN_SHIFT 2 03825 /* TFLG Bit Fields */ 03826 #define PIT_TFLG_TIF_MASK 0x1u 03827 #define PIT_TFLG_TIF_SHIFT 0 03828 03829 /*! 03830 * @} 03831 */ /* end of group PIT_Register_Masks */ 03832 03833 03834 /* PIT - Peripheral instance base addresses */ 03835 /** Peripheral PIT base address */ 03836 #define PIT_BASE (0x40037000u) 03837 /** Peripheral PIT base pointer */ 03838 #define PIT ((PIT_Type *)PIT_BASE) 03839 /** Array initializer of PIT peripheral base pointers */ 03840 #define PIT_BASES { PIT } 03841 03842 /*! 03843 * @} 03844 */ /* end of group PIT_Peripheral_Access_Layer */ 03845 03846 03847 /* ---------------------------------------------------------------------------- 03848 -- PMC Peripheral Access Layer 03849 ---------------------------------------------------------------------------- */ 03850 03851 /*! 03852 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 03853 * @{ 03854 */ 03855 03856 /** PMC - Register Layout Typedef */ 03857 typedef struct { 03858 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 03859 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 03860 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 03861 } PMC_Type; 03862 03863 /* ---------------------------------------------------------------------------- 03864 -- PMC Register Masks 03865 ---------------------------------------------------------------------------- */ 03866 03867 /*! 03868 * @addtogroup PMC_Register_Masks PMC Register Masks 03869 * @{ 03870 */ 03871 03872 /* LVDSC1 Bit Fields */ 03873 #define PMC_LVDSC1_LVDV_MASK 0x3u 03874 #define PMC_LVDSC1_LVDV_SHIFT 0 03875 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK) 03876 #define PMC_LVDSC1_LVDRE_MASK 0x10u 03877 #define PMC_LVDSC1_LVDRE_SHIFT 4 03878 #define PMC_LVDSC1_LVDIE_MASK 0x20u 03879 #define PMC_LVDSC1_LVDIE_SHIFT 5 03880 #define PMC_LVDSC1_LVDACK_MASK 0x40u 03881 #define PMC_LVDSC1_LVDACK_SHIFT 6 03882 #define PMC_LVDSC1_LVDF_MASK 0x80u 03883 #define PMC_LVDSC1_LVDF_SHIFT 7 03884 /* LVDSC2 Bit Fields */ 03885 #define PMC_LVDSC2_LVWV_MASK 0x3u 03886 #define PMC_LVDSC2_LVWV_SHIFT 0 03887 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK) 03888 #define PMC_LVDSC2_LVWIE_MASK 0x20u 03889 #define PMC_LVDSC2_LVWIE_SHIFT 5 03890 #define PMC_LVDSC2_LVWACK_MASK 0x40u 03891 #define PMC_LVDSC2_LVWACK_SHIFT 6 03892 #define PMC_LVDSC2_LVWF_MASK 0x80u 03893 #define PMC_LVDSC2_LVWF_SHIFT 7 03894 /* REGSC Bit Fields */ 03895 #define PMC_REGSC_BGBE_MASK 0x1u 03896 #define PMC_REGSC_BGBE_SHIFT 0 03897 #define PMC_REGSC_REGONS_MASK 0x4u 03898 #define PMC_REGSC_REGONS_SHIFT 2 03899 #define PMC_REGSC_ACKISO_MASK 0x8u 03900 #define PMC_REGSC_ACKISO_SHIFT 3 03901 #define PMC_REGSC_BGEN_MASK 0x10u 03902 #define PMC_REGSC_BGEN_SHIFT 4 03903 03904 /*! 03905 * @} 03906 */ /* end of group PMC_Register_Masks */ 03907 03908 03909 /* PMC - Peripheral instance base addresses */ 03910 /** Peripheral PMC base address */ 03911 #define PMC_BASE (0x4007D000u) 03912 /** Peripheral PMC base pointer */ 03913 #define PMC ((PMC_Type *)PMC_BASE) 03914 /** Array initializer of PMC peripheral base pointers */ 03915 #define PMC_BASES { PMC } 03916 03917 /*! 03918 * @} 03919 */ /* end of group PMC_Peripheral_Access_Layer */ 03920 03921 03922 /* ---------------------------------------------------------------------------- 03923 -- PORT Peripheral Access Layer 03924 ---------------------------------------------------------------------------- */ 03925 03926 /*! 03927 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 03928 * @{ 03929 */ 03930 03931 /** PORT - Register Layout Typedef */ 03932 typedef struct { 03933 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 03934 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 03935 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 03936 uint8_t RESERVED_0[24]; 03937 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 03938 } PORT_Type; 03939 03940 /* ---------------------------------------------------------------------------- 03941 -- PORT Register Masks 03942 ---------------------------------------------------------------------------- */ 03943 03944 /*! 03945 * @addtogroup PORT_Register_Masks PORT Register Masks 03946 * @{ 03947 */ 03948 03949 /* PCR Bit Fields */ 03950 #define PORT_PCR_PS_MASK 0x1u 03951 #define PORT_PCR_PS_SHIFT 0 03952 #define PORT_PCR_PE_MASK 0x2u 03953 #define PORT_PCR_PE_SHIFT 1 03954 #define PORT_PCR_SRE_MASK 0x4u 03955 #define PORT_PCR_SRE_SHIFT 2 03956 #define PORT_PCR_PFE_MASK 0x10u 03957 #define PORT_PCR_PFE_SHIFT 4 03958 #define PORT_PCR_DSE_MASK 0x40u 03959 #define PORT_PCR_DSE_SHIFT 6 03960 #define PORT_PCR_MUX_MASK 0x700u 03961 #define PORT_PCR_MUX_SHIFT 8 03962 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK) 03963 #define PORT_PCR_IRQC_MASK 0xF0000u 03964 #define PORT_PCR_IRQC_SHIFT 16 03965 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK) 03966 #define PORT_PCR_ISF_MASK 0x1000000u 03967 #define PORT_PCR_ISF_SHIFT 24 03968 /* GPCLR Bit Fields */ 03969 #define PORT_GPCLR_GPWD_MASK 0xFFFFu 03970 #define PORT_GPCLR_GPWD_SHIFT 0 03971 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK) 03972 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u 03973 #define PORT_GPCLR_GPWE_SHIFT 16 03974 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK) 03975 /* GPCHR Bit Fields */ 03976 #define PORT_GPCHR_GPWD_MASK 0xFFFFu 03977 #define PORT_GPCHR_GPWD_SHIFT 0 03978 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK) 03979 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u 03980 #define PORT_GPCHR_GPWE_SHIFT 16 03981 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK) 03982 /* ISFR Bit Fields */ 03983 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu 03984 #define PORT_ISFR_ISF_SHIFT 0 03985 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK) 03986 03987 /*! 03988 * @} 03989 */ /* end of group PORT_Register_Masks */ 03990 03991 03992 /* PORT - Peripheral instance base addresses */ 03993 /** Peripheral PORTA base address */ 03994 #define PORTA_BASE (0x40049000u) 03995 /** Peripheral PORTA base pointer */ 03996 #define PORTA ((PORT_Type *)PORTA_BASE) 03997 /** Peripheral PORTB base address */ 03998 #define PORTB_BASE (0x4004A000u) 03999 /** Peripheral PORTB base pointer */ 04000 #define PORTB ((PORT_Type *)PORTB_BASE) 04001 /** Peripheral PORTC base address */ 04002 #define PORTC_BASE (0x4004B000u) 04003 /** Peripheral PORTC base pointer */ 04004 #define PORTC ((PORT_Type *)PORTC_BASE) 04005 /** Peripheral PORTD base address */ 04006 #define PORTD_BASE (0x4004C000u) 04007 /** Peripheral PORTD base pointer */ 04008 #define PORTD ((PORT_Type *)PORTD_BASE) 04009 /** Peripheral PORTE base address */ 04010 #define PORTE_BASE (0x4004D000u) 04011 /** Peripheral PORTE base pointer */ 04012 #define PORTE ((PORT_Type *)PORTE_BASE) 04013 /** Array initializer of PORT peripheral base pointers */ 04014 #define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE } 04015 04016 /*! 04017 * @} 04018 */ /* end of group PORT_Peripheral_Access_Layer */ 04019 04020 04021 /* ---------------------------------------------------------------------------- 04022 -- RCM Peripheral Access Layer 04023 ---------------------------------------------------------------------------- */ 04024 04025 /*! 04026 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 04027 * @{ 04028 */ 04029 04030 /** RCM - Register Layout Typedef */ 04031 typedef struct { 04032 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 04033 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 04034 uint8_t RESERVED_0[2]; 04035 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 04036 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 04037 } RCM_Type; 04038 04039 /* ---------------------------------------------------------------------------- 04040 -- RCM Register Masks 04041 ---------------------------------------------------------------------------- */ 04042 04043 /*! 04044 * @addtogroup RCM_Register_Masks RCM Register Masks 04045 * @{ 04046 */ 04047 04048 /* SRS0 Bit Fields */ 04049 #define RCM_SRS0_WAKEUP_MASK 0x1u 04050 #define RCM_SRS0_WAKEUP_SHIFT 0 04051 #define RCM_SRS0_LVD_MASK 0x2u 04052 #define RCM_SRS0_LVD_SHIFT 1 04053 #define RCM_SRS0_LOC_MASK 0x4u 04054 #define RCM_SRS0_LOC_SHIFT 2 04055 #define RCM_SRS0_LOL_MASK 0x8u 04056 #define RCM_SRS0_LOL_SHIFT 3 04057 #define RCM_SRS0_WDOG_MASK 0x20u 04058 #define RCM_SRS0_WDOG_SHIFT 5 04059 #define RCM_SRS0_PIN_MASK 0x40u 04060 #define RCM_SRS0_PIN_SHIFT 6 04061 #define RCM_SRS0_POR_MASK 0x80u 04062 #define RCM_SRS0_POR_SHIFT 7 04063 /* SRS1 Bit Fields */ 04064 #define RCM_SRS1_LOCKUP_MASK 0x2u 04065 #define RCM_SRS1_LOCKUP_SHIFT 1 04066 #define RCM_SRS1_SW_MASK 0x4u 04067 #define RCM_SRS1_SW_SHIFT 2 04068 #define RCM_SRS1_MDM_AP_MASK 0x8u 04069 #define RCM_SRS1_MDM_AP_SHIFT 3 04070 #define RCM_SRS1_SACKERR_MASK 0x20u 04071 #define RCM_SRS1_SACKERR_SHIFT 5 04072 /* RPFC Bit Fields */ 04073 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u 04074 #define RCM_RPFC_RSTFLTSRW_SHIFT 0 04075 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK) 04076 #define RCM_RPFC_RSTFLTSS_MASK 0x4u 04077 #define RCM_RPFC_RSTFLTSS_SHIFT 2 04078 /* RPFW Bit Fields */ 04079 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu 04080 #define RCM_RPFW_RSTFLTSEL_SHIFT 0 04081 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK) 04082 04083 /*! 04084 * @} 04085 */ /* end of group RCM_Register_Masks */ 04086 04087 04088 /* RCM - Peripheral instance base addresses */ 04089 /** Peripheral RCM base address */ 04090 #define RCM_BASE (0x4007F000u) 04091 /** Peripheral RCM base pointer */ 04092 #define RCM ((RCM_Type *)RCM_BASE) 04093 /** Array initializer of RCM peripheral base pointers */ 04094 #define RCM_BASES { RCM } 04095 04096 /*! 04097 * @} 04098 */ /* end of group RCM_Peripheral_Access_Layer */ 04099 04100 04101 /* ---------------------------------------------------------------------------- 04102 -- ROM Peripheral Access Layer 04103 ---------------------------------------------------------------------------- */ 04104 04105 /*! 04106 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 04107 * @{ 04108 */ 04109 04110 /** ROM - Register Layout Typedef */ 04111 typedef struct { 04112 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 04113 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 04114 uint8_t RESERVED_0[4028]; 04115 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 04116 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 04117 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 04118 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 04119 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 04120 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 04121 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 04122 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 04123 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 04124 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 04125 } ROM_Type; 04126 04127 /* ---------------------------------------------------------------------------- 04128 -- ROM Register Masks 04129 ---------------------------------------------------------------------------- */ 04130 04131 /*! 04132 * @addtogroup ROM_Register_Masks ROM Register Masks 04133 * @{ 04134 */ 04135 04136 /* ENTRY Bit Fields */ 04137 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu 04138 #define ROM_ENTRY_ENTRY_SHIFT 0 04139 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK) 04140 /* TABLEMARK Bit Fields */ 04141 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu 04142 #define ROM_TABLEMARK_MARK_SHIFT 0 04143 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK) 04144 /* SYSACCESS Bit Fields */ 04145 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu 04146 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0 04147 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK) 04148 /* PERIPHID4 Bit Fields */ 04149 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu 04150 #define ROM_PERIPHID4_PERIPHID_SHIFT 0 04151 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK) 04152 /* PERIPHID5 Bit Fields */ 04153 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu 04154 #define ROM_PERIPHID5_PERIPHID_SHIFT 0 04155 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK) 04156 /* PERIPHID6 Bit Fields */ 04157 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu 04158 #define ROM_PERIPHID6_PERIPHID_SHIFT 0 04159 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK) 04160 /* PERIPHID7 Bit Fields */ 04161 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu 04162 #define ROM_PERIPHID7_PERIPHID_SHIFT 0 04163 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK) 04164 /* PERIPHID0 Bit Fields */ 04165 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu 04166 #define ROM_PERIPHID0_PERIPHID_SHIFT 0 04167 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK) 04168 /* PERIPHID1 Bit Fields */ 04169 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu 04170 #define ROM_PERIPHID1_PERIPHID_SHIFT 0 04171 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK) 04172 /* PERIPHID2 Bit Fields */ 04173 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu 04174 #define ROM_PERIPHID2_PERIPHID_SHIFT 0 04175 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK) 04176 /* PERIPHID3 Bit Fields */ 04177 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu 04178 #define ROM_PERIPHID3_PERIPHID_SHIFT 0 04179 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK) 04180 /* COMPID Bit Fields */ 04181 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu 04182 #define ROM_COMPID_COMPID_SHIFT 0 04183 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK) 04184 04185 /*! 04186 * @} 04187 */ /* end of group ROM_Register_Masks */ 04188 04189 04190 /* ROM - Peripheral instance base addresses */ 04191 /** Peripheral ROM base address */ 04192 #define ROM_BASE (0xF0002000u) 04193 /** Peripheral ROM base pointer */ 04194 #define ROM ((ROM_Type *)ROM_BASE) 04195 /** Array initializer of ROM peripheral base pointers */ 04196 #define ROM_BASES { ROM } 04197 04198 /*! 04199 * @} 04200 */ /* end of group ROM_Peripheral_Access_Layer */ 04201 04202 04203 /* ---------------------------------------------------------------------------- 04204 -- RTC Peripheral Access Layer 04205 ---------------------------------------------------------------------------- */ 04206 04207 /*! 04208 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 04209 * @{ 04210 */ 04211 04212 /** RTC - Register Layout Typedef */ 04213 typedef struct { 04214 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ 04215 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ 04216 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ 04217 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ 04218 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ 04219 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ 04220 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ 04221 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ 04222 } RTC_Type; 04223 04224 /* ---------------------------------------------------------------------------- 04225 -- RTC Register Masks 04226 ---------------------------------------------------------------------------- */ 04227 04228 /*! 04229 * @addtogroup RTC_Register_Masks RTC Register Masks 04230 * @{ 04231 */ 04232 04233 /* TSR Bit Fields */ 04234 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu 04235 #define RTC_TSR_TSR_SHIFT 0 04236 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK) 04237 /* TPR Bit Fields */ 04238 #define RTC_TPR_TPR_MASK 0xFFFFu 04239 #define RTC_TPR_TPR_SHIFT 0 04240 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK) 04241 /* TAR Bit Fields */ 04242 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu 04243 #define RTC_TAR_TAR_SHIFT 0 04244 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK) 04245 /* TCR Bit Fields */ 04246 #define RTC_TCR_TCR_MASK 0xFFu 04247 #define RTC_TCR_TCR_SHIFT 0 04248 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK) 04249 #define RTC_TCR_CIR_MASK 0xFF00u 04250 #define RTC_TCR_CIR_SHIFT 8 04251 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK) 04252 #define RTC_TCR_TCV_MASK 0xFF0000u 04253 #define RTC_TCR_TCV_SHIFT 16 04254 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK) 04255 #define RTC_TCR_CIC_MASK 0xFF000000u 04256 #define RTC_TCR_CIC_SHIFT 24 04257 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK) 04258 /* CR Bit Fields */ 04259 #define RTC_CR_SWR_MASK 0x1u 04260 #define RTC_CR_SWR_SHIFT 0 04261 #define RTC_CR_WPE_MASK 0x2u 04262 #define RTC_CR_WPE_SHIFT 1 04263 #define RTC_CR_SUP_MASK 0x4u 04264 #define RTC_CR_SUP_SHIFT 2 04265 #define RTC_CR_UM_MASK 0x8u 04266 #define RTC_CR_UM_SHIFT 3 04267 #define RTC_CR_OSCE_MASK 0x100u 04268 #define RTC_CR_OSCE_SHIFT 8 04269 #define RTC_CR_CLKO_MASK 0x200u 04270 #define RTC_CR_CLKO_SHIFT 9 04271 #define RTC_CR_SC16P_MASK 0x400u 04272 #define RTC_CR_SC16P_SHIFT 10 04273 #define RTC_CR_SC8P_MASK 0x800u 04274 #define RTC_CR_SC8P_SHIFT 11 04275 #define RTC_CR_SC4P_MASK 0x1000u 04276 #define RTC_CR_SC4P_SHIFT 12 04277 #define RTC_CR_SC2P_MASK 0x2000u 04278 #define RTC_CR_SC2P_SHIFT 13 04279 /* SR Bit Fields */ 04280 #define RTC_SR_TIF_MASK 0x1u 04281 #define RTC_SR_TIF_SHIFT 0 04282 #define RTC_SR_TOF_MASK 0x2u 04283 #define RTC_SR_TOF_SHIFT 1 04284 #define RTC_SR_TAF_MASK 0x4u 04285 #define RTC_SR_TAF_SHIFT 2 04286 #define RTC_SR_TCE_MASK 0x10u 04287 #define RTC_SR_TCE_SHIFT 4 04288 /* LR Bit Fields */ 04289 #define RTC_LR_TCL_MASK 0x8u 04290 #define RTC_LR_TCL_SHIFT 3 04291 #define RTC_LR_CRL_MASK 0x10u 04292 #define RTC_LR_CRL_SHIFT 4 04293 #define RTC_LR_SRL_MASK 0x20u 04294 #define RTC_LR_SRL_SHIFT 5 04295 #define RTC_LR_LRL_MASK 0x40u 04296 #define RTC_LR_LRL_SHIFT 6 04297 /* IER Bit Fields */ 04298 #define RTC_IER_TIIE_MASK 0x1u 04299 #define RTC_IER_TIIE_SHIFT 0 04300 #define RTC_IER_TOIE_MASK 0x2u 04301 #define RTC_IER_TOIE_SHIFT 1 04302 #define RTC_IER_TAIE_MASK 0x4u 04303 #define RTC_IER_TAIE_SHIFT 2 04304 #define RTC_IER_TSIE_MASK 0x10u 04305 #define RTC_IER_TSIE_SHIFT 4 04306 #define RTC_IER_WPON_MASK 0x80u 04307 #define RTC_IER_WPON_SHIFT 7 04308 04309 /*! 04310 * @} 04311 */ /* end of group RTC_Register_Masks */ 04312 04313 04314 /* RTC - Peripheral instance base addresses */ 04315 /** Peripheral RTC base address */ 04316 #define RTC_BASE (0x4003D000u) 04317 /** Peripheral RTC base pointer */ 04318 #define RTC ((RTC_Type *)RTC_BASE) 04319 /** Array initializer of RTC peripheral base pointers */ 04320 #define RTC_BASES { RTC } 04321 04322 /*! 04323 * @} 04324 */ /* end of group RTC_Peripheral_Access_Layer */ 04325 04326 04327 /* ---------------------------------------------------------------------------- 04328 -- SIM Peripheral Access Layer 04329 ---------------------------------------------------------------------------- */ 04330 04331 /*! 04332 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 04333 * @{ 04334 */ 04335 04336 /** SIM - Register Layout Typedef */ 04337 typedef struct { 04338 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 04339 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 04340 uint8_t RESERVED_0[4092]; 04341 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ 04342 uint8_t RESERVED_1[4]; 04343 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */ 04344 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ 04345 uint8_t RESERVED_2[4]; 04346 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ 04347 uint8_t RESERVED_3[8]; 04348 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 04349 uint8_t RESERVED_4[12]; 04350 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 04351 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 04352 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 04353 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 04354 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 04355 uint8_t RESERVED_5[4]; 04356 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 04357 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 04358 uint8_t RESERVED_6[4]; 04359 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 04360 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ 04361 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 04362 uint8_t RESERVED_7[156]; 04363 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */ 04364 __O uint32_t SRVCOP; /**< Service COP Register, offset: 0x1104 */ 04365 } SIM_Type; 04366 04367 /* ---------------------------------------------------------------------------- 04368 -- SIM Register Masks 04369 ---------------------------------------------------------------------------- */ 04370 04371 /*! 04372 * @addtogroup SIM_Register_Masks SIM Register Masks 04373 * @{ 04374 */ 04375 04376 /* SOPT1 Bit Fields */ 04377 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u 04378 #define SIM_SOPT1_OSC32KSEL_SHIFT 18 04379 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK) 04380 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u 04381 #define SIM_SOPT1_USBVSTBY_SHIFT 29 04382 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u 04383 #define SIM_SOPT1_USBSSTBY_SHIFT 30 04384 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u 04385 #define SIM_SOPT1_USBREGEN_SHIFT 31 04386 /* SOPT1CFG Bit Fields */ 04387 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u 04388 #define SIM_SOPT1CFG_URWE_SHIFT 24 04389 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u 04390 #define SIM_SOPT1CFG_UVSWE_SHIFT 25 04391 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u 04392 #define SIM_SOPT1CFG_USSWE_SHIFT 26 04393 /* SOPT2 Bit Fields */ 04394 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u 04395 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4 04396 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u 04397 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5 04398 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK) 04399 #define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u 04400 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16 04401 #define SIM_SOPT2_USBSRC_MASK 0x40000u 04402 #define SIM_SOPT2_USBSRC_SHIFT 18 04403 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u 04404 #define SIM_SOPT2_TPMSRC_SHIFT 24 04405 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK) 04406 #define SIM_SOPT2_UART0SRC_MASK 0xC000000u 04407 #define SIM_SOPT2_UART0SRC_SHIFT 26 04408 #define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK) 04409 /* SOPT4 Bit Fields */ 04410 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u 04411 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 04412 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK) 04413 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u 04414 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20 04415 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u 04416 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24 04417 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u 04418 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25 04419 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u 04420 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26 04421 /* SOPT5 Bit Fields */ 04422 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u 04423 #define SIM_SOPT5_UART0TXSRC_SHIFT 0 04424 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK) 04425 #define SIM_SOPT5_UART0RXSRC_MASK 0x4u 04426 #define SIM_SOPT5_UART0RXSRC_SHIFT 2 04427 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u 04428 #define SIM_SOPT5_UART1TXSRC_SHIFT 4 04429 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK) 04430 #define SIM_SOPT5_UART1RXSRC_MASK 0x40u 04431 #define SIM_SOPT5_UART1RXSRC_SHIFT 6 04432 #define SIM_SOPT5_UART0ODE_MASK 0x10000u 04433 #define SIM_SOPT5_UART0ODE_SHIFT 16 04434 #define SIM_SOPT5_UART1ODE_MASK 0x20000u 04435 #define SIM_SOPT5_UART1ODE_SHIFT 17 04436 #define SIM_SOPT5_UART2ODE_MASK 0x40000u 04437 #define SIM_SOPT5_UART2ODE_SHIFT 18 04438 /* SOPT7 Bit Fields */ 04439 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu 04440 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 04441 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK) 04442 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u 04443 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4 04444 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u 04445 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7 04446 /* SDID Bit Fields */ 04447 #define SIM_SDID_PINID_MASK 0xFu 04448 #define SIM_SDID_PINID_SHIFT 0 04449 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK) 04450 #define SIM_SDID_DIEID_MASK 0xF80u 04451 #define SIM_SDID_DIEID_SHIFT 7 04452 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK) 04453 #define SIM_SDID_REVID_MASK 0xF000u 04454 #define SIM_SDID_REVID_SHIFT 12 04455 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK) 04456 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u 04457 #define SIM_SDID_SRAMSIZE_SHIFT 16 04458 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK) 04459 #define SIM_SDID_SERIESID_MASK 0xF00000u 04460 #define SIM_SDID_SERIESID_SHIFT 20 04461 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK) 04462 #define SIM_SDID_SUBFAMID_MASK 0xF000000u 04463 #define SIM_SDID_SUBFAMID_SHIFT 24 04464 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK) 04465 #define SIM_SDID_FAMID_MASK 0xF0000000u 04466 #define SIM_SDID_FAMID_SHIFT 28 04467 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK) 04468 /* SCGC4 Bit Fields */ 04469 #define SIM_SCGC4_I2C0_MASK 0x40u 04470 #define SIM_SCGC4_I2C0_SHIFT 6 04471 #define SIM_SCGC4_I2C1_MASK 0x80u 04472 #define SIM_SCGC4_I2C1_SHIFT 7 04473 #define SIM_SCGC4_UART0_MASK 0x400u 04474 #define SIM_SCGC4_UART0_SHIFT 10 04475 #define SIM_SCGC4_UART1_MASK 0x800u 04476 #define SIM_SCGC4_UART1_SHIFT 11 04477 #define SIM_SCGC4_UART2_MASK 0x1000u 04478 #define SIM_SCGC4_UART2_SHIFT 12 04479 #define SIM_SCGC4_USBOTG_MASK 0x40000u 04480 #define SIM_SCGC4_USBOTG_SHIFT 18 04481 #define SIM_SCGC4_CMP_MASK 0x80000u 04482 #define SIM_SCGC4_CMP_SHIFT 19 04483 #define SIM_SCGC4_SPI0_MASK 0x400000u 04484 #define SIM_SCGC4_SPI0_SHIFT 22 04485 #define SIM_SCGC4_SPI1_MASK 0x800000u 04486 #define SIM_SCGC4_SPI1_SHIFT 23 04487 /* SCGC5 Bit Fields */ 04488 #define SIM_SCGC5_LPTMR_MASK 0x1u 04489 #define SIM_SCGC5_LPTMR_SHIFT 0 04490 #define SIM_SCGC5_TSI_MASK 0x20u 04491 #define SIM_SCGC5_TSI_SHIFT 5 04492 #define SIM_SCGC5_PORTA_MASK 0x200u 04493 #define SIM_SCGC5_PORTA_SHIFT 9 04494 #define SIM_SCGC5_PORTB_MASK 0x400u 04495 #define SIM_SCGC5_PORTB_SHIFT 10 04496 #define SIM_SCGC5_PORTC_MASK 0x800u 04497 #define SIM_SCGC5_PORTC_SHIFT 11 04498 #define SIM_SCGC5_PORTD_MASK 0x1000u 04499 #define SIM_SCGC5_PORTD_SHIFT 12 04500 #define SIM_SCGC5_PORTE_MASK 0x2000u 04501 #define SIM_SCGC5_PORTE_SHIFT 13 04502 #define SIM_SCGC5_SLCD_MASK 0x80000u 04503 #define SIM_SCGC5_SLCD_SHIFT 19 04504 /* SCGC6 Bit Fields */ 04505 #define SIM_SCGC6_FTF_MASK 0x1u 04506 #define SIM_SCGC6_FTF_SHIFT 0 04507 #define SIM_SCGC6_DMAMUX_MASK 0x2u 04508 #define SIM_SCGC6_DMAMUX_SHIFT 1 04509 #define SIM_SCGC6_I2S_MASK 0x8000u 04510 #define SIM_SCGC6_I2S_SHIFT 15 04511 #define SIM_SCGC6_PIT_MASK 0x800000u 04512 #define SIM_SCGC6_PIT_SHIFT 23 04513 #define SIM_SCGC6_TPM0_MASK 0x1000000u 04514 #define SIM_SCGC6_TPM0_SHIFT 24 04515 #define SIM_SCGC6_TPM1_MASK 0x2000000u 04516 #define SIM_SCGC6_TPM1_SHIFT 25 04517 #define SIM_SCGC6_TPM2_MASK 0x4000000u 04518 #define SIM_SCGC6_TPM2_SHIFT 26 04519 #define SIM_SCGC6_ADC0_MASK 0x8000000u 04520 #define SIM_SCGC6_ADC0_SHIFT 27 04521 #define SIM_SCGC6_RTC_MASK 0x20000000u 04522 #define SIM_SCGC6_RTC_SHIFT 29 04523 #define SIM_SCGC6_DAC0_MASK 0x80000000u 04524 #define SIM_SCGC6_DAC0_SHIFT 31 04525 /* SCGC7 Bit Fields */ 04526 #define SIM_SCGC7_DMA_MASK 0x100u 04527 #define SIM_SCGC7_DMA_SHIFT 8 04528 /* CLKDIV1 Bit Fields */ 04529 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u 04530 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16 04531 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK) 04532 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u 04533 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28 04534 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK) 04535 /* FCFG1 Bit Fields */ 04536 #define SIM_FCFG1_FLASHDIS_MASK 0x1u 04537 #define SIM_FCFG1_FLASHDIS_SHIFT 0 04538 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u 04539 #define SIM_FCFG1_FLASHDOZE_SHIFT 1 04540 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u 04541 #define SIM_FCFG1_PFSIZE_SHIFT 24 04542 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK) 04543 /* FCFG2 Bit Fields */ 04544 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u 04545 #define SIM_FCFG2_MAXADDR1_SHIFT 16 04546 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK) 04547 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u 04548 #define SIM_FCFG2_MAXADDR0_SHIFT 24 04549 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK) 04550 /* UIDMH Bit Fields */ 04551 #define SIM_UIDMH_UID_MASK 0xFFFFu 04552 #define SIM_UIDMH_UID_SHIFT 0 04553 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK) 04554 /* UIDML Bit Fields */ 04555 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu 04556 #define SIM_UIDML_UID_SHIFT 0 04557 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK) 04558 /* UIDL Bit Fields */ 04559 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu 04560 #define SIM_UIDL_UID_SHIFT 0 04561 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK) 04562 /* COPC Bit Fields */ 04563 #define SIM_COPC_COPW_MASK 0x1u 04564 #define SIM_COPC_COPW_SHIFT 0 04565 #define SIM_COPC_COPCLKS_MASK 0x2u 04566 #define SIM_COPC_COPCLKS_SHIFT 1 04567 #define SIM_COPC_COPT_MASK 0xCu 04568 #define SIM_COPC_COPT_SHIFT 2 04569 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK) 04570 /* SRVCOP Bit Fields */ 04571 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu 04572 #define SIM_SRVCOP_SRVCOP_SHIFT 0 04573 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK) 04574 04575 /*! 04576 * @} 04577 */ /* end of group SIM_Register_Masks */ 04578 04579 04580 /* SIM - Peripheral instance base addresses */ 04581 /** Peripheral SIM base address */ 04582 #define SIM_BASE (0x40047000u) 04583 /** Peripheral SIM base pointer */ 04584 #define SIM ((SIM_Type *)SIM_BASE) 04585 /** Array initializer of SIM peripheral base pointers */ 04586 #define SIM_BASES { SIM } 04587 04588 /*! 04589 * @} 04590 */ /* end of group SIM_Peripheral_Access_Layer */ 04591 04592 04593 /* ---------------------------------------------------------------------------- 04594 -- SMC Peripheral Access Layer 04595 ---------------------------------------------------------------------------- */ 04596 04597 /*! 04598 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 04599 * @{ 04600 */ 04601 04602 /** SMC - Register Layout Typedef */ 04603 typedef struct { 04604 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 04605 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 04606 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ 04607 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 04608 } SMC_Type; 04609 04610 /* ---------------------------------------------------------------------------- 04611 -- SMC Register Masks 04612 ---------------------------------------------------------------------------- */ 04613 04614 /*! 04615 * @addtogroup SMC_Register_Masks SMC Register Masks 04616 * @{ 04617 */ 04618 04619 /* PMPROT Bit Fields */ 04620 #define SMC_PMPROT_AVLLS_MASK 0x2u 04621 #define SMC_PMPROT_AVLLS_SHIFT 1 04622 #define SMC_PMPROT_ALLS_MASK 0x8u 04623 #define SMC_PMPROT_ALLS_SHIFT 3 04624 #define SMC_PMPROT_AVLP_MASK 0x20u 04625 #define SMC_PMPROT_AVLP_SHIFT 5 04626 /* PMCTRL Bit Fields */ 04627 #define SMC_PMCTRL_STOPM_MASK 0x7u 04628 #define SMC_PMCTRL_STOPM_SHIFT 0 04629 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK) 04630 #define SMC_PMCTRL_STOPA_MASK 0x8u 04631 #define SMC_PMCTRL_STOPA_SHIFT 3 04632 #define SMC_PMCTRL_RUNM_MASK 0x60u 04633 #define SMC_PMCTRL_RUNM_SHIFT 5 04634 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK) 04635 /* STOPCTRL Bit Fields */ 04636 #define SMC_STOPCTRL_VLLSM_MASK 0x7u 04637 #define SMC_STOPCTRL_VLLSM_SHIFT 0 04638 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK) 04639 #define SMC_STOPCTRL_PORPO_MASK 0x20u 04640 #define SMC_STOPCTRL_PORPO_SHIFT 5 04641 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u 04642 #define SMC_STOPCTRL_PSTOPO_SHIFT 6 04643 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK) 04644 /* PMSTAT Bit Fields */ 04645 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu 04646 #define SMC_PMSTAT_PMSTAT_SHIFT 0 04647 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK) 04648 04649 /*! 04650 * @} 04651 */ /* end of group SMC_Register_Masks */ 04652 04653 04654 /* SMC - Peripheral instance base addresses */ 04655 /** Peripheral SMC base address */ 04656 #define SMC_BASE (0x4007E000u) 04657 /** Peripheral SMC base pointer */ 04658 #define SMC ((SMC_Type *)SMC_BASE) 04659 /** Array initializer of SMC peripheral base pointers */ 04660 #define SMC_BASES { SMC } 04661 04662 /*! 04663 * @} 04664 */ /* end of group SMC_Peripheral_Access_Layer */ 04665 04666 04667 /* ---------------------------------------------------------------------------- 04668 -- SPI Peripheral Access Layer 04669 ---------------------------------------------------------------------------- */ 04670 04671 /*! 04672 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 04673 * @{ 04674 */ 04675 04676 /** SPI - Register Layout Typedef */ 04677 typedef struct { 04678 __I uint8_t S; /**< SPI status register, offset: 0x0 */ 04679 __IO uint8_t BR; /**< SPI baud rate register, offset: 0x1 */ 04680 __IO uint8_t C2; /**< SPI control register 2, offset: 0x2 */ 04681 __IO uint8_t C1; /**< SPI control register 1, offset: 0x3 */ 04682 __IO uint8_t ML; /**< SPI match register low, offset: 0x4 */ 04683 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */ 04684 __IO uint8_t DL; /**< SPI data register low, offset: 0x6 */ 04685 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */ 04686 uint8_t RESERVED_0[2]; 04687 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */ 04688 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */ 04689 } SPI_Type; 04690 04691 /* ---------------------------------------------------------------------------- 04692 -- SPI Register Masks 04693 ---------------------------------------------------------------------------- */ 04694 04695 /*! 04696 * @addtogroup SPI_Register_Masks SPI Register Masks 04697 * @{ 04698 */ 04699 04700 /* S Bit Fields */ 04701 #define SPI_S_RFIFOEF_MASK 0x1u 04702 #define SPI_S_RFIFOEF_SHIFT 0 04703 #define SPI_S_TXFULLF_MASK 0x2u 04704 #define SPI_S_TXFULLF_SHIFT 1 04705 #define SPI_S_TNEAREF_MASK 0x4u 04706 #define SPI_S_TNEAREF_SHIFT 2 04707 #define SPI_S_RNFULLF_MASK 0x8u 04708 #define SPI_S_RNFULLF_SHIFT 3 04709 #define SPI_S_MODF_MASK 0x10u 04710 #define SPI_S_MODF_SHIFT 4 04711 #define SPI_S_SPTEF_MASK 0x20u 04712 #define SPI_S_SPTEF_SHIFT 5 04713 #define SPI_S_SPMF_MASK 0x40u 04714 #define SPI_S_SPMF_SHIFT 6 04715 #define SPI_S_SPRF_MASK 0x80u 04716 #define SPI_S_SPRF_SHIFT 7 04717 /* BR Bit Fields */ 04718 #define SPI_BR_SPR_MASK 0xFu 04719 #define SPI_BR_SPR_SHIFT 0 04720 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK) 04721 #define SPI_BR_SPPR_MASK 0x70u 04722 #define SPI_BR_SPPR_SHIFT 4 04723 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK) 04724 /* C2 Bit Fields */ 04725 #define SPI_C2_SPC0_MASK 0x1u 04726 #define SPI_C2_SPC0_SHIFT 0 04727 #define SPI_C2_SPISWAI_MASK 0x2u 04728 #define SPI_C2_SPISWAI_SHIFT 1 04729 #define SPI_C2_RXDMAE_MASK 0x4u 04730 #define SPI_C2_RXDMAE_SHIFT 2 04731 #define SPI_C2_BIDIROE_MASK 0x8u 04732 #define SPI_C2_BIDIROE_SHIFT 3 04733 #define SPI_C2_MODFEN_MASK 0x10u 04734 #define SPI_C2_MODFEN_SHIFT 4 04735 #define SPI_C2_TXDMAE_MASK 0x20u 04736 #define SPI_C2_TXDMAE_SHIFT 5 04737 #define SPI_C2_SPIMODE_MASK 0x40u 04738 #define SPI_C2_SPIMODE_SHIFT 6 04739 #define SPI_C2_SPMIE_MASK 0x80u 04740 #define SPI_C2_SPMIE_SHIFT 7 04741 /* C1 Bit Fields */ 04742 #define SPI_C1_LSBFE_MASK 0x1u 04743 #define SPI_C1_LSBFE_SHIFT 0 04744 #define SPI_C1_SSOE_MASK 0x2u 04745 #define SPI_C1_SSOE_SHIFT 1 04746 #define SPI_C1_CPHA_MASK 0x4u 04747 #define SPI_C1_CPHA_SHIFT 2 04748 #define SPI_C1_CPOL_MASK 0x8u 04749 #define SPI_C1_CPOL_SHIFT 3 04750 #define SPI_C1_MSTR_MASK 0x10u 04751 #define SPI_C1_MSTR_SHIFT 4 04752 #define SPI_C1_SPTIE_MASK 0x20u 04753 #define SPI_C1_SPTIE_SHIFT 5 04754 #define SPI_C1_SPE_MASK 0x40u 04755 #define SPI_C1_SPE_SHIFT 6 04756 #define SPI_C1_SPIE_MASK 0x80u 04757 #define SPI_C1_SPIE_SHIFT 7 04758 /* ML Bit Fields */ 04759 #define SPI_ML_Bits_MASK 0xFFu 04760 #define SPI_ML_Bits_SHIFT 0 04761 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK) 04762 /* MH Bit Fields */ 04763 #define SPI_MH_Bits_MASK 0xFFu 04764 #define SPI_MH_Bits_SHIFT 0 04765 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK) 04766 /* DL Bit Fields */ 04767 #define SPI_DL_Bits_MASK 0xFFu 04768 #define SPI_DL_Bits_SHIFT 0 04769 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK) 04770 /* DH Bit Fields */ 04771 #define SPI_DH_Bits_MASK 0xFFu 04772 #define SPI_DH_Bits_SHIFT 0 04773 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK) 04774 /* CI Bit Fields */ 04775 #define SPI_CI_SPRFCI_MASK 0x1u 04776 #define SPI_CI_SPRFCI_SHIFT 0 04777 #define SPI_CI_SPTEFCI_MASK 0x2u 04778 #define SPI_CI_SPTEFCI_SHIFT 1 04779 #define SPI_CI_RNFULLFCI_MASK 0x4u 04780 #define SPI_CI_RNFULLFCI_SHIFT 2 04781 #define SPI_CI_TNEAREFCI_MASK 0x8u 04782 #define SPI_CI_TNEAREFCI_SHIFT 3 04783 #define SPI_CI_RXFOF_MASK 0x10u 04784 #define SPI_CI_RXFOF_SHIFT 4 04785 #define SPI_CI_TXFOF_MASK 0x20u 04786 #define SPI_CI_TXFOF_SHIFT 5 04787 #define SPI_CI_RXFERR_MASK 0x40u 04788 #define SPI_CI_RXFERR_SHIFT 6 04789 #define SPI_CI_TXFERR_MASK 0x80u 04790 #define SPI_CI_TXFERR_SHIFT 7 04791 /* C3 Bit Fields */ 04792 #define SPI_C3_FIFOMODE_MASK 0x1u 04793 #define SPI_C3_FIFOMODE_SHIFT 0 04794 #define SPI_C3_RNFULLIEN_MASK 0x2u 04795 #define SPI_C3_RNFULLIEN_SHIFT 1 04796 #define SPI_C3_TNEARIEN_MASK 0x4u 04797 #define SPI_C3_TNEARIEN_SHIFT 2 04798 #define SPI_C3_INTCLR_MASK 0x8u 04799 #define SPI_C3_INTCLR_SHIFT 3 04800 #define SPI_C3_RNFULLF_MARK_MASK 0x10u 04801 #define SPI_C3_RNFULLF_MARK_SHIFT 4 04802 #define SPI_C3_TNEAREF_MARK_MASK 0x20u 04803 #define SPI_C3_TNEAREF_MARK_SHIFT 5 04804 04805 /*! 04806 * @} 04807 */ /* end of group SPI_Register_Masks */ 04808 04809 04810 /* SPI - Peripheral instance base addresses */ 04811 /** Peripheral SPI0 base address */ 04812 #define SPI0_BASE (0x40076000u) 04813 /** Peripheral SPI0 base pointer */ 04814 #define SPI0 ((SPI_Type *)SPI0_BASE) 04815 /** Peripheral SPI1 base address */ 04816 #define SPI1_BASE (0x40077000u) 04817 /** Peripheral SPI1 base pointer */ 04818 #define SPI1 ((SPI_Type *)SPI1_BASE) 04819 /** Array initializer of SPI peripheral base pointers */ 04820 #define SPI_BASES { SPI0, SPI1 } 04821 04822 /*! 04823 * @} 04824 */ /* end of group SPI_Peripheral_Access_Layer */ 04825 04826 04827 /* ---------------------------------------------------------------------------- 04828 -- TPM Peripheral Access Layer 04829 ---------------------------------------------------------------------------- */ 04830 04831 /*! 04832 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer 04833 * @{ 04834 */ 04835 04836 /** TPM - Register Layout Typedef */ 04837 typedef struct { 04838 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ 04839 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 04840 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 04841 struct { /* offset: 0xC, array step: 0x8 */ 04842 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ 04843 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 04844 } CONTROLS[6]; 04845 uint8_t RESERVED_0[20]; 04846 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ 04847 uint8_t RESERVED_1[48]; 04848 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 04849 } TPM_Type; 04850 04851 /* ---------------------------------------------------------------------------- 04852 -- TPM Register Masks 04853 ---------------------------------------------------------------------------- */ 04854 04855 /*! 04856 * @addtogroup TPM_Register_Masks TPM Register Masks 04857 * @{ 04858 */ 04859 04860 /* SC Bit Fields */ 04861 #define TPM_SC_PS_MASK 0x7u 04862 #define TPM_SC_PS_SHIFT 0 04863 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK) 04864 #define TPM_SC_CMOD_MASK 0x18u 04865 #define TPM_SC_CMOD_SHIFT 3 04866 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK) 04867 #define TPM_SC_CPWMS_MASK 0x20u 04868 #define TPM_SC_CPWMS_SHIFT 5 04869 #define TPM_SC_TOIE_MASK 0x40u 04870 #define TPM_SC_TOIE_SHIFT 6 04871 #define TPM_SC_TOF_MASK 0x80u 04872 #define TPM_SC_TOF_SHIFT 7 04873 #define TPM_SC_DMA_MASK 0x100u 04874 #define TPM_SC_DMA_SHIFT 8 04875 /* CNT Bit Fields */ 04876 #define TPM_CNT_COUNT_MASK 0xFFFFu 04877 #define TPM_CNT_COUNT_SHIFT 0 04878 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK) 04879 /* MOD Bit Fields */ 04880 #define TPM_MOD_MOD_MASK 0xFFFFu 04881 #define TPM_MOD_MOD_SHIFT 0 04882 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK) 04883 /* CnSC Bit Fields */ 04884 #define TPM_CnSC_DMA_MASK 0x1u 04885 #define TPM_CnSC_DMA_SHIFT 0 04886 #define TPM_CnSC_ELSA_MASK 0x4u 04887 #define TPM_CnSC_ELSA_SHIFT 2 04888 #define TPM_CnSC_ELSB_MASK 0x8u 04889 #define TPM_CnSC_ELSB_SHIFT 3 04890 #define TPM_CnSC_MSA_MASK 0x10u 04891 #define TPM_CnSC_MSA_SHIFT 4 04892 #define TPM_CnSC_MSB_MASK 0x20u 04893 #define TPM_CnSC_MSB_SHIFT 5 04894 #define TPM_CnSC_CHIE_MASK 0x40u 04895 #define TPM_CnSC_CHIE_SHIFT 6 04896 #define TPM_CnSC_CHF_MASK 0x80u 04897 #define TPM_CnSC_CHF_SHIFT 7 04898 /* CnV Bit Fields */ 04899 #define TPM_CnV_VAL_MASK 0xFFFFu 04900 #define TPM_CnV_VAL_SHIFT 0 04901 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK) 04902 /* STATUS Bit Fields */ 04903 #define TPM_STATUS_CH0F_MASK 0x1u 04904 #define TPM_STATUS_CH0F_SHIFT 0 04905 #define TPM_STATUS_CH1F_MASK 0x2u 04906 #define TPM_STATUS_CH1F_SHIFT 1 04907 #define TPM_STATUS_CH2F_MASK 0x4u 04908 #define TPM_STATUS_CH2F_SHIFT 2 04909 #define TPM_STATUS_CH3F_MASK 0x8u 04910 #define TPM_STATUS_CH3F_SHIFT 3 04911 #define TPM_STATUS_CH4F_MASK 0x10u 04912 #define TPM_STATUS_CH4F_SHIFT 4 04913 #define TPM_STATUS_CH5F_MASK 0x20u 04914 #define TPM_STATUS_CH5F_SHIFT 5 04915 #define TPM_STATUS_TOF_MASK 0x100u 04916 #define TPM_STATUS_TOF_SHIFT 8 04917 /* CONF Bit Fields */ 04918 #define TPM_CONF_DOZEEN_MASK 0x20u 04919 #define TPM_CONF_DOZEEN_SHIFT 5 04920 #define TPM_CONF_DBGMODE_MASK 0xC0u 04921 #define TPM_CONF_DBGMODE_SHIFT 6 04922 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK) 04923 #define TPM_CONF_GTBEEN_MASK 0x200u 04924 #define TPM_CONF_GTBEEN_SHIFT 9 04925 #define TPM_CONF_CSOT_MASK 0x10000u 04926 #define TPM_CONF_CSOT_SHIFT 16 04927 #define TPM_CONF_CSOO_MASK 0x20000u 04928 #define TPM_CONF_CSOO_SHIFT 17 04929 #define TPM_CONF_CROT_MASK 0x40000u 04930 #define TPM_CONF_CROT_SHIFT 18 04931 #define TPM_CONF_TRGSEL_MASK 0xF000000u 04932 #define TPM_CONF_TRGSEL_SHIFT 24 04933 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK) 04934 04935 /*! 04936 * @} 04937 */ /* end of group TPM_Register_Masks */ 04938 04939 04940 /* TPM - Peripheral instance base addresses */ 04941 /** Peripheral TPM0 base address */ 04942 #define TPM0_BASE (0x40038000u) 04943 /** Peripheral TPM0 base pointer */ 04944 #define TPM0 ((TPM_Type *)TPM0_BASE) 04945 /** Peripheral TPM1 base address */ 04946 #define TPM1_BASE (0x40039000u) 04947 /** Peripheral TPM1 base pointer */ 04948 #define TPM1 ((TPM_Type *)TPM1_BASE) 04949 /** Peripheral TPM2 base address */ 04950 #define TPM2_BASE (0x4003A000u) 04951 /** Peripheral TPM2 base pointer */ 04952 #define TPM2 ((TPM_Type *)TPM2_BASE) 04953 /** Array initializer of TPM peripheral base pointers */ 04954 #define TPM_BASES { TPM0, TPM1, TPM2 } 04955 04956 /*! 04957 * @} 04958 */ /* end of group TPM_Peripheral_Access_Layer */ 04959 04960 04961 /* ---------------------------------------------------------------------------- 04962 -- TSI Peripheral Access Layer 04963 ---------------------------------------------------------------------------- */ 04964 04965 /*! 04966 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer 04967 * @{ 04968 */ 04969 04970 /** TSI - Register Layout Typedef */ 04971 typedef struct { 04972 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ 04973 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ 04974 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ 04975 } TSI_Type; 04976 04977 /* ---------------------------------------------------------------------------- 04978 -- TSI Register Masks 04979 ---------------------------------------------------------------------------- */ 04980 04981 /*! 04982 * @addtogroup TSI_Register_Masks TSI Register Masks 04983 * @{ 04984 */ 04985 04986 /* GENCS Bit Fields */ 04987 #define TSI_GENCS_CURSW_MASK 0x2u 04988 #define TSI_GENCS_CURSW_SHIFT 1 04989 #define TSI_GENCS_EOSF_MASK 0x4u 04990 #define TSI_GENCS_EOSF_SHIFT 2 04991 #define TSI_GENCS_SCNIP_MASK 0x8u 04992 #define TSI_GENCS_SCNIP_SHIFT 3 04993 #define TSI_GENCS_STM_MASK 0x10u 04994 #define TSI_GENCS_STM_SHIFT 4 04995 #define TSI_GENCS_STPE_MASK 0x20u 04996 #define TSI_GENCS_STPE_SHIFT 5 04997 #define TSI_GENCS_TSIIEN_MASK 0x40u 04998 #define TSI_GENCS_TSIIEN_SHIFT 6 04999 #define TSI_GENCS_TSIEN_MASK 0x80u 05000 #define TSI_GENCS_TSIEN_SHIFT 7 05001 #define TSI_GENCS_NSCN_MASK 0x1F00u 05002 #define TSI_GENCS_NSCN_SHIFT 8 05003 #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK) 05004 #define TSI_GENCS_PS_MASK 0xE000u 05005 #define TSI_GENCS_PS_SHIFT 13 05006 #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK) 05007 #define TSI_GENCS_EXTCHRG_MASK 0x70000u 05008 #define TSI_GENCS_EXTCHRG_SHIFT 16 05009 #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK) 05010 #define TSI_GENCS_DVOLT_MASK 0x180000u 05011 #define TSI_GENCS_DVOLT_SHIFT 19 05012 #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK) 05013 #define TSI_GENCS_REFCHRG_MASK 0xE00000u 05014 #define TSI_GENCS_REFCHRG_SHIFT 21 05015 #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK) 05016 #define TSI_GENCS_MODE_MASK 0xF000000u 05017 #define TSI_GENCS_MODE_SHIFT 24 05018 #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK) 05019 #define TSI_GENCS_ESOR_MASK 0x10000000u 05020 #define TSI_GENCS_ESOR_SHIFT 28 05021 #define TSI_GENCS_OUTRGF_MASK 0x80000000u 05022 #define TSI_GENCS_OUTRGF_SHIFT 31 05023 /* DATA Bit Fields */ 05024 #define TSI_DATA_TSICNT_MASK 0xFFFFu 05025 #define TSI_DATA_TSICNT_SHIFT 0 05026 #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK) 05027 #define TSI_DATA_SWTS_MASK 0x400000u 05028 #define TSI_DATA_SWTS_SHIFT 22 05029 #define TSI_DATA_DMAEN_MASK 0x800000u 05030 #define TSI_DATA_DMAEN_SHIFT 23 05031 #define TSI_DATA_TSICH_MASK 0xF0000000u 05032 #define TSI_DATA_TSICH_SHIFT 28 05033 #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK) 05034 /* TSHD Bit Fields */ 05035 #define TSI_TSHD_THRESL_MASK 0xFFFFu 05036 #define TSI_TSHD_THRESL_SHIFT 0 05037 #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK) 05038 #define TSI_TSHD_THRESH_MASK 0xFFFF0000u 05039 #define TSI_TSHD_THRESH_SHIFT 16 05040 #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK) 05041 05042 /*! 05043 * @} 05044 */ /* end of group TSI_Register_Masks */ 05045 05046 05047 /* TSI - Peripheral instance base addresses */ 05048 /** Peripheral TSI0 base address */ 05049 #define TSI0_BASE (0x40045000u) 05050 /** Peripheral TSI0 base pointer */ 05051 #define TSI0 ((TSI_Type *)TSI0_BASE) 05052 /** Array initializer of TSI peripheral base pointers */ 05053 #define TSI_BASES { TSI0 } 05054 05055 /*! 05056 * @} 05057 */ /* end of group TSI_Peripheral_Access_Layer */ 05058 05059 05060 /* ---------------------------------------------------------------------------- 05061 -- UART Peripheral Access Layer 05062 ---------------------------------------------------------------------------- */ 05063 05064 /*! 05065 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 05066 * @{ 05067 */ 05068 05069 /** UART - Register Layout Typedef */ 05070 typedef struct { 05071 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */ 05072 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */ 05073 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 05074 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 05075 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 05076 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 05077 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 05078 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 05079 __IO uint8_t C4; /**< UART Control Register 4, offset: 0x8 */ 05080 } UART_Type; 05081 05082 /* ---------------------------------------------------------------------------- 05083 -- UART Register Masks 05084 ---------------------------------------------------------------------------- */ 05085 05086 /*! 05087 * @addtogroup UART_Register_Masks UART Register Masks 05088 * @{ 05089 */ 05090 05091 /* BDH Bit Fields */ 05092 #define UART_BDH_SBR_MASK 0x1Fu 05093 #define UART_BDH_SBR_SHIFT 0 05094 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK) 05095 #define UART_BDH_SBNS_MASK 0x20u 05096 #define UART_BDH_SBNS_SHIFT 5 05097 #define UART_BDH_RXEDGIE_MASK 0x40u 05098 #define UART_BDH_RXEDGIE_SHIFT 6 05099 #define UART_BDH_LBKDIE_MASK 0x80u 05100 #define UART_BDH_LBKDIE_SHIFT 7 05101 /* BDL Bit Fields */ 05102 #define UART_BDL_SBR_MASK 0xFFu 05103 #define UART_BDL_SBR_SHIFT 0 05104 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK) 05105 /* C1 Bit Fields */ 05106 #define UART_C1_PT_MASK 0x1u 05107 #define UART_C1_PT_SHIFT 0 05108 #define UART_C1_PE_MASK 0x2u 05109 #define UART_C1_PE_SHIFT 1 05110 #define UART_C1_ILT_MASK 0x4u 05111 #define UART_C1_ILT_SHIFT 2 05112 #define UART_C1_WAKE_MASK 0x8u 05113 #define UART_C1_WAKE_SHIFT 3 05114 #define UART_C1_M_MASK 0x10u 05115 #define UART_C1_M_SHIFT 4 05116 #define UART_C1_RSRC_MASK 0x20u 05117 #define UART_C1_RSRC_SHIFT 5 05118 #define UART_C1_UARTSWAI_MASK 0x40u 05119 #define UART_C1_UARTSWAI_SHIFT 6 05120 #define UART_C1_LOOPS_MASK 0x80u 05121 #define UART_C1_LOOPS_SHIFT 7 05122 /* C2 Bit Fields */ 05123 #define UART_C2_SBK_MASK 0x1u 05124 #define UART_C2_SBK_SHIFT 0 05125 #define UART_C2_RWU_MASK 0x2u 05126 #define UART_C2_RWU_SHIFT 1 05127 #define UART_C2_RE_MASK 0x4u 05128 #define UART_C2_RE_SHIFT 2 05129 #define UART_C2_TE_MASK 0x8u 05130 #define UART_C2_TE_SHIFT 3 05131 #define UART_C2_ILIE_MASK 0x10u 05132 #define UART_C2_ILIE_SHIFT 4 05133 #define UART_C2_RIE_MASK 0x20u 05134 #define UART_C2_RIE_SHIFT 5 05135 #define UART_C2_TCIE_MASK 0x40u 05136 #define UART_C2_TCIE_SHIFT 6 05137 #define UART_C2_TIE_MASK 0x80u 05138 #define UART_C2_TIE_SHIFT 7 05139 /* S1 Bit Fields */ 05140 #define UART_S1_PF_MASK 0x1u 05141 #define UART_S1_PF_SHIFT 0 05142 #define UART_S1_FE_MASK 0x2u 05143 #define UART_S1_FE_SHIFT 1 05144 #define UART_S1_NF_MASK 0x4u 05145 #define UART_S1_NF_SHIFT 2 05146 #define UART_S1_OR_MASK 0x8u 05147 #define UART_S1_OR_SHIFT 3 05148 #define UART_S1_IDLE_MASK 0x10u 05149 #define UART_S1_IDLE_SHIFT 4 05150 #define UART_S1_RDRF_MASK 0x20u 05151 #define UART_S1_RDRF_SHIFT 5 05152 #define UART_S1_TC_MASK 0x40u 05153 #define UART_S1_TC_SHIFT 6 05154 #define UART_S1_TDRE_MASK 0x80u 05155 #define UART_S1_TDRE_SHIFT 7 05156 /* S2 Bit Fields */ 05157 #define UART_S2_RAF_MASK 0x1u 05158 #define UART_S2_RAF_SHIFT 0 05159 #define UART_S2_LBKDE_MASK 0x2u 05160 #define UART_S2_LBKDE_SHIFT 1 05161 #define UART_S2_BRK13_MASK 0x4u 05162 #define UART_S2_BRK13_SHIFT 2 05163 #define UART_S2_RWUID_MASK 0x8u 05164 #define UART_S2_RWUID_SHIFT 3 05165 #define UART_S2_RXINV_MASK 0x10u 05166 #define UART_S2_RXINV_SHIFT 4 05167 #define UART_S2_RXEDGIF_MASK 0x40u 05168 #define UART_S2_RXEDGIF_SHIFT 6 05169 #define UART_S2_LBKDIF_MASK 0x80u 05170 #define UART_S2_LBKDIF_SHIFT 7 05171 /* C3 Bit Fields */ 05172 #define UART_C3_PEIE_MASK 0x1u 05173 #define UART_C3_PEIE_SHIFT 0 05174 #define UART_C3_FEIE_MASK 0x2u 05175 #define UART_C3_FEIE_SHIFT 1 05176 #define UART_C3_NEIE_MASK 0x4u 05177 #define UART_C3_NEIE_SHIFT 2 05178 #define UART_C3_ORIE_MASK 0x8u 05179 #define UART_C3_ORIE_SHIFT 3 05180 #define UART_C3_TXINV_MASK 0x10u 05181 #define UART_C3_TXINV_SHIFT 4 05182 #define UART_C3_TXDIR_MASK 0x20u 05183 #define UART_C3_TXDIR_SHIFT 5 05184 #define UART_C3_T8_MASK 0x40u 05185 #define UART_C3_T8_SHIFT 6 05186 #define UART_C3_R8_MASK 0x80u 05187 #define UART_C3_R8_SHIFT 7 05188 /* D Bit Fields */ 05189 #define UART_D_R0T0_MASK 0x1u 05190 #define UART_D_R0T0_SHIFT 0 05191 #define UART_D_R1T1_MASK 0x2u 05192 #define UART_D_R1T1_SHIFT 1 05193 #define UART_D_R2T2_MASK 0x4u 05194 #define UART_D_R2T2_SHIFT 2 05195 #define UART_D_R3T3_MASK 0x8u 05196 #define UART_D_R3T3_SHIFT 3 05197 #define UART_D_R4T4_MASK 0x10u 05198 #define UART_D_R4T4_SHIFT 4 05199 #define UART_D_R5T5_MASK 0x20u 05200 #define UART_D_R5T5_SHIFT 5 05201 #define UART_D_R6T6_MASK 0x40u 05202 #define UART_D_R6T6_SHIFT 6 05203 #define UART_D_R7T7_MASK 0x80u 05204 #define UART_D_R7T7_SHIFT 7 05205 /* C4 Bit Fields */ 05206 #define UART_C4_RDMAS_MASK 0x20u 05207 #define UART_C4_RDMAS_SHIFT 5 05208 #define UART_C4_TDMAS_MASK 0x80u 05209 #define UART_C4_TDMAS_SHIFT 7 05210 05211 /*! 05212 * @} 05213 */ /* end of group UART_Register_Masks */ 05214 05215 05216 /* UART - Peripheral instance base addresses */ 05217 /** Peripheral UART1 base address */ 05218 #define UART1_BASE (0x4006B000u) 05219 /** Peripheral UART1 base pointer */ 05220 #define UART1 ((UART_Type *)UART1_BASE) 05221 /** Peripheral UART2 base address */ 05222 #define UART2_BASE (0x4006C000u) 05223 /** Peripheral UART2 base pointer */ 05224 #define UART2 ((UART_Type *)UART2_BASE) 05225 /** Array initializer of UART peripheral base pointers */ 05226 #define UART_BASES { UART1, UART2 } 05227 05228 /*! 05229 * @} 05230 */ /* end of group UART_Peripheral_Access_Layer */ 05231 05232 05233 /* ---------------------------------------------------------------------------- 05234 -- UART0 Peripheral Access Layer 05235 ---------------------------------------------------------------------------- */ 05236 05237 /*! 05238 * @addtogroup UART0_Peripheral_Access_Layer UART0 Peripheral Access Layer 05239 * @{ 05240 */ 05241 05242 /** UART0 - Register Layout Typedef */ 05243 typedef struct { 05244 __IO uint8_t BDH; /**< UART Baud Rate Register High, offset: 0x0 */ 05245 __IO uint8_t BDL; /**< UART Baud Rate Register Low, offset: 0x1 */ 05246 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 05247 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 05248 __IO uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 05249 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 05250 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 05251 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 05252 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 05253 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 05254 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 05255 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 05256 } UART0_Type; 05257 05258 /* ---------------------------------------------------------------------------- 05259 -- UART0 Register Masks 05260 ---------------------------------------------------------------------------- */ 05261 05262 /*! 05263 * @addtogroup UART0_Register_Masks UART0 Register Masks 05264 * @{ 05265 */ 05266 05267 /* BDH Bit Fields */ 05268 #define UART0_BDH_SBR_MASK 0x1Fu 05269 #define UART0_BDH_SBR_SHIFT 0 05270 #define UART0_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDH_SBR_SHIFT))&UART0_BDH_SBR_MASK) 05271 #define UART0_BDH_SBNS_MASK 0x20u 05272 #define UART0_BDH_SBNS_SHIFT 5 05273 #define UART0_BDH_RXEDGIE_MASK 0x40u 05274 #define UART0_BDH_RXEDGIE_SHIFT 6 05275 #define UART0_BDH_LBKDIE_MASK 0x80u 05276 #define UART0_BDH_LBKDIE_SHIFT 7 05277 /* BDL Bit Fields */ 05278 #define UART0_BDL_SBR_MASK 0xFFu 05279 #define UART0_BDL_SBR_SHIFT 0 05280 #define UART0_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART0_BDL_SBR_SHIFT))&UART0_BDL_SBR_MASK) 05281 /* C1 Bit Fields */ 05282 #define UART0_C1_PT_MASK 0x1u 05283 #define UART0_C1_PT_SHIFT 0 05284 #define UART0_C1_PE_MASK 0x2u 05285 #define UART0_C1_PE_SHIFT 1 05286 #define UART0_C1_ILT_MASK 0x4u 05287 #define UART0_C1_ILT_SHIFT 2 05288 #define UART0_C1_WAKE_MASK 0x8u 05289 #define UART0_C1_WAKE_SHIFT 3 05290 #define UART0_C1_M_MASK 0x10u 05291 #define UART0_C1_M_SHIFT 4 05292 #define UART0_C1_RSRC_MASK 0x20u 05293 #define UART0_C1_RSRC_SHIFT 5 05294 #define UART0_C1_DOZEEN_MASK 0x40u 05295 #define UART0_C1_DOZEEN_SHIFT 6 05296 #define UART0_C1_LOOPS_MASK 0x80u 05297 #define UART0_C1_LOOPS_SHIFT 7 05298 /* C2 Bit Fields */ 05299 #define UART0_C2_SBK_MASK 0x1u 05300 #define UART0_C2_SBK_SHIFT 0 05301 #define UART0_C2_RWU_MASK 0x2u 05302 #define UART0_C2_RWU_SHIFT 1 05303 #define UART0_C2_RE_MASK 0x4u 05304 #define UART0_C2_RE_SHIFT 2 05305 #define UART0_C2_TE_MASK 0x8u 05306 #define UART0_C2_TE_SHIFT 3 05307 #define UART0_C2_ILIE_MASK 0x10u 05308 #define UART0_C2_ILIE_SHIFT 4 05309 #define UART0_C2_RIE_MASK 0x20u 05310 #define UART0_C2_RIE_SHIFT 5 05311 #define UART0_C2_TCIE_MASK 0x40u 05312 #define UART0_C2_TCIE_SHIFT 6 05313 #define UART0_C2_TIE_MASK 0x80u 05314 #define UART0_C2_TIE_SHIFT 7 05315 /* S1 Bit Fields */ 05316 #define UART0_S1_PF_MASK 0x1u 05317 #define UART0_S1_PF_SHIFT 0 05318 #define UART0_S1_FE_MASK 0x2u 05319 #define UART0_S1_FE_SHIFT 1 05320 #define UART0_S1_NF_MASK 0x4u 05321 #define UART0_S1_NF_SHIFT 2 05322 #define UART0_S1_OR_MASK 0x8u 05323 #define UART0_S1_OR_SHIFT 3 05324 #define UART0_S1_IDLE_MASK 0x10u 05325 #define UART0_S1_IDLE_SHIFT 4 05326 #define UART0_S1_RDRF_MASK 0x20u 05327 #define UART0_S1_RDRF_SHIFT 5 05328 #define UART0_S1_TC_MASK 0x40u 05329 #define UART0_S1_TC_SHIFT 6 05330 #define UART0_S1_TDRE_MASK 0x80u 05331 #define UART0_S1_TDRE_SHIFT 7 05332 /* S2 Bit Fields */ 05333 #define UART0_S2_RAF_MASK 0x1u 05334 #define UART0_S2_RAF_SHIFT 0 05335 #define UART0_S2_LBKDE_MASK 0x2u 05336 #define UART0_S2_LBKDE_SHIFT 1 05337 #define UART0_S2_BRK13_MASK 0x4u 05338 #define UART0_S2_BRK13_SHIFT 2 05339 #define UART0_S2_RWUID_MASK 0x8u 05340 #define UART0_S2_RWUID_SHIFT 3 05341 #define UART0_S2_RXINV_MASK 0x10u 05342 #define UART0_S2_RXINV_SHIFT 4 05343 #define UART0_S2_MSBF_MASK 0x20u 05344 #define UART0_S2_MSBF_SHIFT 5 05345 #define UART0_S2_RXEDGIF_MASK 0x40u 05346 #define UART0_S2_RXEDGIF_SHIFT 6 05347 #define UART0_S2_LBKDIF_MASK 0x80u 05348 #define UART0_S2_LBKDIF_SHIFT 7 05349 /* C3 Bit Fields */ 05350 #define UART0_C3_PEIE_MASK 0x1u 05351 #define UART0_C3_PEIE_SHIFT 0 05352 #define UART0_C3_FEIE_MASK 0x2u 05353 #define UART0_C3_FEIE_SHIFT 1 05354 #define UART0_C3_NEIE_MASK 0x4u 05355 #define UART0_C3_NEIE_SHIFT 2 05356 #define UART0_C3_ORIE_MASK 0x8u 05357 #define UART0_C3_ORIE_SHIFT 3 05358 #define UART0_C3_TXINV_MASK 0x10u 05359 #define UART0_C3_TXINV_SHIFT 4 05360 #define UART0_C3_TXDIR_MASK 0x20u 05361 #define UART0_C3_TXDIR_SHIFT 5 05362 #define UART0_C3_R9T8_MASK 0x40u 05363 #define UART0_C3_R9T8_SHIFT 6 05364 #define UART0_C3_R8T9_MASK 0x80u 05365 #define UART0_C3_R8T9_SHIFT 7 05366 /* D Bit Fields */ 05367 #define UART0_D_R0T0_MASK 0x1u 05368 #define UART0_D_R0T0_SHIFT 0 05369 #define UART0_D_R1T1_MASK 0x2u 05370 #define UART0_D_R1T1_SHIFT 1 05371 #define UART0_D_R2T2_MASK 0x4u 05372 #define UART0_D_R2T2_SHIFT 2 05373 #define UART0_D_R3T3_MASK 0x8u 05374 #define UART0_D_R3T3_SHIFT 3 05375 #define UART0_D_R4T4_MASK 0x10u 05376 #define UART0_D_R4T4_SHIFT 4 05377 #define UART0_D_R5T5_MASK 0x20u 05378 #define UART0_D_R5T5_SHIFT 5 05379 #define UART0_D_R6T6_MASK 0x40u 05380 #define UART0_D_R6T6_SHIFT 6 05381 #define UART0_D_R7T7_MASK 0x80u 05382 #define UART0_D_R7T7_SHIFT 7 05383 /* MA1 Bit Fields */ 05384 #define UART0_MA1_MA_MASK 0xFFu 05385 #define UART0_MA1_MA_SHIFT 0 05386 #define UART0_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA1_MA_SHIFT))&UART0_MA1_MA_MASK) 05387 /* MA2 Bit Fields */ 05388 #define UART0_MA2_MA_MASK 0xFFu 05389 #define UART0_MA2_MA_SHIFT 0 05390 #define UART0_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART0_MA2_MA_SHIFT))&UART0_MA2_MA_MASK) 05391 /* C4 Bit Fields */ 05392 #define UART0_C4_OSR_MASK 0x1Fu 05393 #define UART0_C4_OSR_SHIFT 0 05394 #define UART0_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UART0_C4_OSR_SHIFT))&UART0_C4_OSR_MASK) 05395 #define UART0_C4_M10_MASK 0x20u 05396 #define UART0_C4_M10_SHIFT 5 05397 #define UART0_C4_MAEN2_MASK 0x40u 05398 #define UART0_C4_MAEN2_SHIFT 6 05399 #define UART0_C4_MAEN1_MASK 0x80u 05400 #define UART0_C4_MAEN1_SHIFT 7 05401 /* C5 Bit Fields */ 05402 #define UART0_C5_RESYNCDIS_MASK 0x1u 05403 #define UART0_C5_RESYNCDIS_SHIFT 0 05404 #define UART0_C5_BOTHEDGE_MASK 0x2u 05405 #define UART0_C5_BOTHEDGE_SHIFT 1 05406 #define UART0_C5_RDMAE_MASK 0x20u 05407 #define UART0_C5_RDMAE_SHIFT 5 05408 #define UART0_C5_TDMAE_MASK 0x80u 05409 #define UART0_C5_TDMAE_SHIFT 7 05410 05411 /*! 05412 * @} 05413 */ /* end of group UART0_Register_Masks */ 05414 05415 05416 /* UART0 - Peripheral instance base addresses */ 05417 /** Peripheral UART0 base address */ 05418 #define UART0_BASE (0x4006A000u) 05419 /** Peripheral UART0 base pointer */ 05420 #define UART0 ((UART0_Type *)UART0_BASE) 05421 /** Array initializer of UART0 peripheral base pointers */ 05422 #define UART0_BASES { UART0 } 05423 05424 /*! 05425 * @} 05426 */ /* end of group UART0_Peripheral_Access_Layer */ 05427 05428 05429 /* ---------------------------------------------------------------------------- 05430 -- USB Peripheral Access Layer 05431 ---------------------------------------------------------------------------- */ 05432 05433 /*! 05434 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer 05435 * @{ 05436 */ 05437 05438 /** USB - Register Layout Typedef */ 05439 typedef struct { 05440 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ 05441 uint8_t RESERVED_0[3]; 05442 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ 05443 uint8_t RESERVED_1[3]; 05444 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ 05445 uint8_t RESERVED_2[3]; 05446 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ 05447 uint8_t RESERVED_3[3]; 05448 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ 05449 uint8_t RESERVED_4[3]; 05450 __IO uint8_t OTGICR; /**< OTG Interrupt Control Register, offset: 0x14 */ 05451 uint8_t RESERVED_5[3]; 05452 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ 05453 uint8_t RESERVED_6[3]; 05454 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ 05455 uint8_t RESERVED_7[99]; 05456 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ 05457 uint8_t RESERVED_8[3]; 05458 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ 05459 uint8_t RESERVED_9[3]; 05460 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ 05461 uint8_t RESERVED_10[3]; 05462 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ 05463 uint8_t RESERVED_11[3]; 05464 __I uint8_t STAT; /**< Status register, offset: 0x90 */ 05465 uint8_t RESERVED_12[3]; 05466 __IO uint8_t CTL; /**< Control register, offset: 0x94 */ 05467 uint8_t RESERVED_13[3]; 05468 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ 05469 uint8_t RESERVED_14[3]; 05470 __IO uint8_t BDTPAGE1; /**< BDT Page Register 1, offset: 0x9C */ 05471 uint8_t RESERVED_15[3]; 05472 __IO uint8_t FRMNUML; /**< Frame Number Register Low, offset: 0xA0 */ 05473 uint8_t RESERVED_16[3]; 05474 __IO uint8_t FRMNUMH; /**< Frame Number Register High, offset: 0xA4 */ 05475 uint8_t RESERVED_17[3]; 05476 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ 05477 uint8_t RESERVED_18[3]; 05478 __IO uint8_t SOFTHLD; /**< SOF Threshold Register, offset: 0xAC */ 05479 uint8_t RESERVED_19[3]; 05480 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ 05481 uint8_t RESERVED_20[3]; 05482 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ 05483 uint8_t RESERVED_21[11]; 05484 struct { /* offset: 0xC0, array step: 0x4 */ 05485 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ 05486 uint8_t RESERVED_0[3]; 05487 } ENDPOINT[16]; 05488 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ 05489 uint8_t RESERVED_22[3]; 05490 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ 05491 uint8_t RESERVED_23[3]; 05492 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ 05493 uint8_t RESERVED_24[3]; 05494 __IO uint8_t USBTRC0; /**< USB Transceiver Control Register 0, offset: 0x10C */ 05495 uint8_t RESERVED_25[7]; 05496 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ 05497 } USB_Type; 05498 05499 /* ---------------------------------------------------------------------------- 05500 -- USB Register Masks 05501 ---------------------------------------------------------------------------- */ 05502 05503 /*! 05504 * @addtogroup USB_Register_Masks USB Register Masks 05505 * @{ 05506 */ 05507 05508 /* PERID Bit Fields */ 05509 #define USB_PERID_ID_MASK 0x3Fu 05510 #define USB_PERID_ID_SHIFT 0 05511 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK) 05512 /* IDCOMP Bit Fields */ 05513 #define USB_IDCOMP_NID_MASK 0x3Fu 05514 #define USB_IDCOMP_NID_SHIFT 0 05515 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK) 05516 /* REV Bit Fields */ 05517 #define USB_REV_REV_MASK 0xFFu 05518 #define USB_REV_REV_SHIFT 0 05519 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK) 05520 /* ADDINFO Bit Fields */ 05521 #define USB_ADDINFO_IEHOST_MASK 0x1u 05522 #define USB_ADDINFO_IEHOST_SHIFT 0 05523 #define USB_ADDINFO_IRQNUM_MASK 0xF8u 05524 #define USB_ADDINFO_IRQNUM_SHIFT 3 05525 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK) 05526 /* OTGISTAT Bit Fields */ 05527 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u 05528 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0 05529 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u 05530 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2 05531 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u 05532 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3 05533 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u 05534 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5 05535 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u 05536 #define USB_OTGISTAT_ONEMSEC_SHIFT 6 05537 #define USB_OTGISTAT_IDCHG_MASK 0x80u 05538 #define USB_OTGISTAT_IDCHG_SHIFT 7 05539 /* OTGICR Bit Fields */ 05540 #define USB_OTGICR_AVBUSEN_MASK 0x1u 05541 #define USB_OTGICR_AVBUSEN_SHIFT 0 05542 #define USB_OTGICR_BSESSEN_MASK 0x4u 05543 #define USB_OTGICR_BSESSEN_SHIFT 2 05544 #define USB_OTGICR_SESSVLDEN_MASK 0x8u 05545 #define USB_OTGICR_SESSVLDEN_SHIFT 3 05546 #define USB_OTGICR_LINESTATEEN_MASK 0x20u 05547 #define USB_OTGICR_LINESTATEEN_SHIFT 5 05548 #define USB_OTGICR_ONEMSECEN_MASK 0x40u 05549 #define USB_OTGICR_ONEMSECEN_SHIFT 6 05550 #define USB_OTGICR_IDEN_MASK 0x80u 05551 #define USB_OTGICR_IDEN_SHIFT 7 05552 /* OTGSTAT Bit Fields */ 05553 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u 05554 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0 05555 #define USB_OTGSTAT_BSESSEND_MASK 0x4u 05556 #define USB_OTGSTAT_BSESSEND_SHIFT 2 05557 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u 05558 #define USB_OTGSTAT_SESS_VLD_SHIFT 3 05559 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u 05560 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5 05561 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u 05562 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6 05563 #define USB_OTGSTAT_ID_MASK 0x80u 05564 #define USB_OTGSTAT_ID_SHIFT 7 05565 /* OTGCTL Bit Fields */ 05566 #define USB_OTGCTL_OTGEN_MASK 0x4u 05567 #define USB_OTGCTL_OTGEN_SHIFT 2 05568 #define USB_OTGCTL_DMLOW_MASK 0x10u 05569 #define USB_OTGCTL_DMLOW_SHIFT 4 05570 #define USB_OTGCTL_DPLOW_MASK 0x20u 05571 #define USB_OTGCTL_DPLOW_SHIFT 5 05572 #define USB_OTGCTL_DPHIGH_MASK 0x80u 05573 #define USB_OTGCTL_DPHIGH_SHIFT 7 05574 /* ISTAT Bit Fields */ 05575 #define USB_ISTAT_USBRST_MASK 0x1u 05576 #define USB_ISTAT_USBRST_SHIFT 0 05577 #define USB_ISTAT_ERROR_MASK 0x2u 05578 #define USB_ISTAT_ERROR_SHIFT 1 05579 #define USB_ISTAT_SOFTOK_MASK 0x4u 05580 #define USB_ISTAT_SOFTOK_SHIFT 2 05581 #define USB_ISTAT_TOKDNE_MASK 0x8u 05582 #define USB_ISTAT_TOKDNE_SHIFT 3 05583 #define USB_ISTAT_SLEEP_MASK 0x10u 05584 #define USB_ISTAT_SLEEP_SHIFT 4 05585 #define USB_ISTAT_RESUME_MASK 0x20u 05586 #define USB_ISTAT_RESUME_SHIFT 5 05587 #define USB_ISTAT_ATTACH_MASK 0x40u 05588 #define USB_ISTAT_ATTACH_SHIFT 6 05589 #define USB_ISTAT_STALL_MASK 0x80u 05590 #define USB_ISTAT_STALL_SHIFT 7 05591 /* INTEN Bit Fields */ 05592 #define USB_INTEN_USBRSTEN_MASK 0x1u 05593 #define USB_INTEN_USBRSTEN_SHIFT 0 05594 #define USB_INTEN_ERROREN_MASK 0x2u 05595 #define USB_INTEN_ERROREN_SHIFT 1 05596 #define USB_INTEN_SOFTOKEN_MASK 0x4u 05597 #define USB_INTEN_SOFTOKEN_SHIFT 2 05598 #define USB_INTEN_TOKDNEEN_MASK 0x8u 05599 #define USB_INTEN_TOKDNEEN_SHIFT 3 05600 #define USB_INTEN_SLEEPEN_MASK 0x10u 05601 #define USB_INTEN_SLEEPEN_SHIFT 4 05602 #define USB_INTEN_RESUMEEN_MASK 0x20u 05603 #define USB_INTEN_RESUMEEN_SHIFT 5 05604 #define USB_INTEN_ATTACHEN_MASK 0x40u 05605 #define USB_INTEN_ATTACHEN_SHIFT 6 05606 #define USB_INTEN_STALLEN_MASK 0x80u 05607 #define USB_INTEN_STALLEN_SHIFT 7 05608 /* ERRSTAT Bit Fields */ 05609 #define USB_ERRSTAT_PIDERR_MASK 0x1u 05610 #define USB_ERRSTAT_PIDERR_SHIFT 0 05611 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u 05612 #define USB_ERRSTAT_CRC5EOF_SHIFT 1 05613 #define USB_ERRSTAT_CRC16_MASK 0x4u 05614 #define USB_ERRSTAT_CRC16_SHIFT 2 05615 #define USB_ERRSTAT_DFN8_MASK 0x8u 05616 #define USB_ERRSTAT_DFN8_SHIFT 3 05617 #define USB_ERRSTAT_BTOERR_MASK 0x10u 05618 #define USB_ERRSTAT_BTOERR_SHIFT 4 05619 #define USB_ERRSTAT_DMAERR_MASK 0x20u 05620 #define USB_ERRSTAT_DMAERR_SHIFT 5 05621 #define USB_ERRSTAT_BTSERR_MASK 0x80u 05622 #define USB_ERRSTAT_BTSERR_SHIFT 7 05623 /* ERREN Bit Fields */ 05624 #define USB_ERREN_PIDERREN_MASK 0x1u 05625 #define USB_ERREN_PIDERREN_SHIFT 0 05626 #define USB_ERREN_CRC5EOFEN_MASK 0x2u 05627 #define USB_ERREN_CRC5EOFEN_SHIFT 1 05628 #define USB_ERREN_CRC16EN_MASK 0x4u 05629 #define USB_ERREN_CRC16EN_SHIFT 2 05630 #define USB_ERREN_DFN8EN_MASK 0x8u 05631 #define USB_ERREN_DFN8EN_SHIFT 3 05632 #define USB_ERREN_BTOERREN_MASK 0x10u 05633 #define USB_ERREN_BTOERREN_SHIFT 4 05634 #define USB_ERREN_DMAERREN_MASK 0x20u 05635 #define USB_ERREN_DMAERREN_SHIFT 5 05636 #define USB_ERREN_BTSERREN_MASK 0x80u 05637 #define USB_ERREN_BTSERREN_SHIFT 7 05638 /* STAT Bit Fields */ 05639 #define USB_STAT_ODD_MASK 0x4u 05640 #define USB_STAT_ODD_SHIFT 2 05641 #define USB_STAT_TX_MASK 0x8u 05642 #define USB_STAT_TX_SHIFT 3 05643 #define USB_STAT_ENDP_MASK 0xF0u 05644 #define USB_STAT_ENDP_SHIFT 4 05645 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK) 05646 /* CTL Bit Fields */ 05647 #define USB_CTL_USBENSOFEN_MASK 0x1u 05648 #define USB_CTL_USBENSOFEN_SHIFT 0 05649 #define USB_CTL_ODDRST_MASK 0x2u 05650 #define USB_CTL_ODDRST_SHIFT 1 05651 #define USB_CTL_RESUME_MASK 0x4u 05652 #define USB_CTL_RESUME_SHIFT 2 05653 #define USB_CTL_HOSTMODEEN_MASK 0x8u 05654 #define USB_CTL_HOSTMODEEN_SHIFT 3 05655 #define USB_CTL_RESET_MASK 0x10u 05656 #define USB_CTL_RESET_SHIFT 4 05657 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u 05658 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5 05659 #define USB_CTL_SE0_MASK 0x40u 05660 #define USB_CTL_SE0_SHIFT 6 05661 #define USB_CTL_JSTATE_MASK 0x80u 05662 #define USB_CTL_JSTATE_SHIFT 7 05663 /* ADDR Bit Fields */ 05664 #define USB_ADDR_ADDR_MASK 0x7Fu 05665 #define USB_ADDR_ADDR_SHIFT 0 05666 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK) 05667 #define USB_ADDR_LSEN_MASK 0x80u 05668 #define USB_ADDR_LSEN_SHIFT 7 05669 /* BDTPAGE1 Bit Fields */ 05670 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu 05671 #define USB_BDTPAGE1_BDTBA_SHIFT 1 05672 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK) 05673 /* FRMNUML Bit Fields */ 05674 #define USB_FRMNUML_FRM_MASK 0xFFu 05675 #define USB_FRMNUML_FRM_SHIFT 0 05676 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK) 05677 /* FRMNUMH Bit Fields */ 05678 #define USB_FRMNUMH_FRM_MASK 0x7u 05679 #define USB_FRMNUMH_FRM_SHIFT 0 05680 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK) 05681 /* TOKEN Bit Fields */ 05682 #define USB_TOKEN_TOKENENDPT_MASK 0xFu 05683 #define USB_TOKEN_TOKENENDPT_SHIFT 0 05684 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK) 05685 #define USB_TOKEN_TOKENPID_MASK 0xF0u 05686 #define USB_TOKEN_TOKENPID_SHIFT 4 05687 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK) 05688 /* SOFTHLD Bit Fields */ 05689 #define USB_SOFTHLD_CNT_MASK 0xFFu 05690 #define USB_SOFTHLD_CNT_SHIFT 0 05691 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK) 05692 /* BDTPAGE2 Bit Fields */ 05693 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu 05694 #define USB_BDTPAGE2_BDTBA_SHIFT 0 05695 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK) 05696 /* BDTPAGE3 Bit Fields */ 05697 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu 05698 #define USB_BDTPAGE3_BDTBA_SHIFT 0 05699 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK) 05700 /* ENDPT Bit Fields */ 05701 #define USB_ENDPT_EPHSHK_MASK 0x1u 05702 #define USB_ENDPT_EPHSHK_SHIFT 0 05703 #define USB_ENDPT_EPSTALL_MASK 0x2u 05704 #define USB_ENDPT_EPSTALL_SHIFT 1 05705 #define USB_ENDPT_EPTXEN_MASK 0x4u 05706 #define USB_ENDPT_EPTXEN_SHIFT 2 05707 #define USB_ENDPT_EPRXEN_MASK 0x8u 05708 #define USB_ENDPT_EPRXEN_SHIFT 3 05709 #define USB_ENDPT_EPCTLDIS_MASK 0x10u 05710 #define USB_ENDPT_EPCTLDIS_SHIFT 4 05711 #define USB_ENDPT_RETRYDIS_MASK 0x40u 05712 #define USB_ENDPT_RETRYDIS_SHIFT 6 05713 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u 05714 #define USB_ENDPT_HOSTWOHUB_SHIFT 7 05715 /* USBCTRL Bit Fields */ 05716 #define USB_USBCTRL_PDE_MASK 0x40u 05717 #define USB_USBCTRL_PDE_SHIFT 6 05718 #define USB_USBCTRL_SUSP_MASK 0x80u 05719 #define USB_USBCTRL_SUSP_SHIFT 7 05720 /* OBSERVE Bit Fields */ 05721 #define USB_OBSERVE_DMPD_MASK 0x10u 05722 #define USB_OBSERVE_DMPD_SHIFT 4 05723 #define USB_OBSERVE_DPPD_MASK 0x40u 05724 #define USB_OBSERVE_DPPD_SHIFT 6 05725 #define USB_OBSERVE_DPPU_MASK 0x80u 05726 #define USB_OBSERVE_DPPU_SHIFT 7 05727 /* CONTROL Bit Fields */ 05728 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u 05729 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4 05730 /* USBTRC0 Bit Fields */ 05731 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u 05732 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0 05733 #define USB_USBTRC0_SYNC_DET_MASK 0x2u 05734 #define USB_USBTRC0_SYNC_DET_SHIFT 1 05735 #define USB_USBTRC0_USBRESMEN_MASK 0x20u 05736 #define USB_USBTRC0_USBRESMEN_SHIFT 5 05737 #define USB_USBTRC0_USBRESET_MASK 0x80u 05738 #define USB_USBTRC0_USBRESET_SHIFT 7 05739 /* USBFRMADJUST Bit Fields */ 05740 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu 05741 #define USB_USBFRMADJUST_ADJ_SHIFT 0 05742 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK) 05743 05744 /*! 05745 * @} 05746 */ /* end of group USB_Register_Masks */ 05747 05748 05749 /* USB - Peripheral instance base addresses */ 05750 /** Peripheral USB0 base address */ 05751 #define USB0_BASE (0x40072000u) 05752 /** Peripheral USB0 base pointer */ 05753 #define USB0 ((USB_Type *)USB0_BASE) 05754 /** Array initializer of USB peripheral base pointers */ 05755 #define USB_BASES { USB0 } 05756 05757 /*! 05758 * @} 05759 */ /* end of group USB_Peripheral_Access_Layer */ 05760 05761 05762 /* 05763 ** End of section using anonymous unions 05764 */ 05765 05766 #if defined(__ARMCC_VERSION) 05767 #pragma pop 05768 #elif defined(__CWCC__) 05769 #pragma pop 05770 #elif defined(__GNUC__) 05771 /* leave anonymous unions enabled */ 05772 #elif defined(__IAR_SYSTEMS_ICC__) 05773 #pragma language=default 05774 #else 05775 #error Not supported compiler type 05776 #endif 05777 05778 /*! 05779 * @} 05780 */ /* end of group Peripheral_access_layer */ 05781 05782 05783 /* ---------------------------------------------------------------------------- 05784 -- Backward Compatibility 05785 ---------------------------------------------------------------------------- */ 05786 05787 /*! 05788 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility 05789 * @{ 05790 */ 05791 05792 /* No backward compatibility issues. */ 05793 05794 /*! 05795 * @} 05796 */ /* end of group Backward_Compatibility_Symbols */ 05797 05798 05799 #endif /* #if !defined(MKL46Z4_H_) */ 05800 05801 /* MKL46Z4.h, eof. */
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