Codebase from CC1101_Transceiver, ported to LPC1114/LPC824/STM32F103 and other micros, will be merged with panStamp project to replace AVR/MSP.
Fork of CC1101_Transceiver_LPC1114 by
CC1101.h
00001 /** 00002 * @author Athanassios Mavrogeorgiadis 00003 * @author TI CC1101 library developed by Athanassios Mavrogeorgiadis (tmav Electronics) as template based on TI C8051 SOURCE CODE swrc021f 00004 * @section LICENSE 00005 * 00006 * Copyright (c) 2010 ARM Limited 00007 * 00008 * Permission is hereby granted, free of charge, to any person obtaining a copy 00009 * of this software and associated documentation files (the "Software"), to deal 00010 * in the Software without restriction, including without limitation the rights 00011 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 00012 * copies of the Software, and to permit persons to whom the Software is 00013 * furnished to do so, subject to the following conditions: 00014 * 00015 * The above copyright notice and this permission notice shall be included in 00016 * all copies or substantial portions of the Software. 00017 * 00018 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 00019 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 00020 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 00021 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 00022 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 00023 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 00024 * THE SOFTWARE. 00025 * 00026 * @section DESCRIPTION 00027 * 00028 * CC1101 Low-Power Sub-1 GHz RF Transceiver CC1101. 00029 * 00030 * Datasheet: 00031 * 00032 * http://focus.ti.com/lit/ds/swrs061f/swrs061f.pdf 00033 */ 00034 00035 #ifndef MBED_CC1101_H 00036 #define MBED_CC1101_H 00037 00038 /** 00039 * Includes 00040 */ 00041 #include "mbed.h" 00042 00043 /** 00044 * Defines 00045 */ 00046 /////////////////////////////////////////////////////////////////////////////////////// 00047 //------------------------------------------------------------------------------------------------------ 00048 // CC2500/CC1100 STROBE, CONTROL AND STATUS REGSITER 00049 #define CCxxx0_IOCFG2 0x00 // GDO2 output pin configuration 00050 #define CCxxx0_IOCFG1 0x01 // GDO1 output pin configuration 00051 #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds 00052 #define CCxxx0_SYNC1 0x04 // Sync word, high byte 00053 #define CCxxx0_SYNC0 0x05 // Sync word, low byte 00054 #define CCxxx0_IOCFG0 0x02 // GDO0 output pin configuration 00055 #define CCxxx0_FIFOTHR 0x03 // RX FIFO and TX FIFO thresholds 00056 #define CCxxx0_SYNC1 0x04 // Sync word, high byte 00057 #define CCxxx0_SYNC0 0x05 // Sync word, low byte 00058 #define CCxxx0_PKTLEN 0x06 // Packet length 00059 #define CCxxx0_PKTCTRL1 0x07 // Packet automation control 00060 #define CCxxx0_PKTCTRL0 0x08 // Packet automation control 00061 #define CCxxx0_ADDR 0x09 // Device address 00062 #define CCxxx0_CHANNR 0x0A // Channel number 00063 #define CCxxx0_FSCTRL1 0x0B // Frequency synthesizer control 00064 #define CCxxx0_FSCTRL0 0x0C // Frequency synthesizer control 00065 #define CCxxx0_FREQ2 0x0D // Frequency control word, high byte 00066 #define CCxxx0_FREQ1 0x0E // Frequency control word, middle byte 00067 #define CCxxx0_FREQ0 0x0F // Frequency control word, low byte 00068 #define CCxxx0_MDMCFG4 0x10 // Modem configuration 00069 #define CCxxx0_MDMCFG3 0x11 // Modem configuration 00070 #define CCxxx0_MDMCFG2 0x12 // Modem configuration 00071 #define CCxxx0_MDMCFG1 0x13 // Modem configuration 00072 #define CCxxx0_MDMCFG0 0x14 // Modem configuration 00073 #define CCxxx0_DEVIATN 0x15 // Modem deviation setting 00074 #define CCxxx0_MCSM2 0x16 // Main Radio Control State Machine configuration 00075 #define CCxxx0_MCSM1 0x17 // Main Radio Control State Machine configuration 00076 #define CCxxx0_MCSM0 0x18 // Main Radio Control State Machine configuration 00077 #define CCxxx0_FOCCFG 0x19 // Frequency Offset Compensation configuration 00078 #define CCxxx0_BSCFG 0x1A // Bit Synchronization configuration 00079 #define CCxxx0_AGCCTRL2 0x1B // AGC control 00080 #define CCxxx0_AGCCTRL1 0x1C // AGC control 00081 #define CCxxx0_AGCCTRL0 0x1D // AGC control 00082 #define CCxxx0_WOREVT1 0x1E // High byte Event 0 timeout 00083 #define CCxxx0_WOREVT0 0x1F // Low byte Event 0 timeout 00084 #define CCxxx0_WORCTRL 0x20 // Wake On Radio control 00085 #define CCxxx0_FREND1 0x21 // Front end RX configuration 00086 #define CCxxx0_FREND0 0x22 // Front end TX configuration 00087 #define CCxxx0_FSCAL3 0x23 // Frequency synthesizer calibration 00088 #define CCxxx0_FSCAL2 0x24 // Frequency synthesizer calibration 00089 #define CCxxx0_FSCAL1 0x25 // Frequency synthesizer calibration 00090 #define CCxxx0_FSCAL0 0x26 // Frequency synthesizer calibration 00091 #define CCxxx0_RCCTRL1 0x27 // RC oscillator configuration 00092 #define CCxxx0_RCCTRL0 0x28 // RC oscillator configuration 00093 #define CCxxx0_FSTEST 0x29 // Frequency synthesizer calibration control 00094 #define CCxxx0_PTEST 0x2A // Production test 00095 #define CCxxx0_AGCTEST 0x2B // AGC test 00096 #define CCxxx0_TEST2 0x2C // Various test settings 00097 #define CCxxx0_TEST1 0x2D // Various test settings 00098 #define CCxxx0_TEST0 0x2E // Various test settings 00099 00100 // Strobe commands 00101 #define CCxxx0_SRES 0x30 // Reset chip. 00102 #define CCxxx0_SFSTXON 0x31 // Enable and calibrate frequency synthesizer (if MCSM0.FS_AUTOCAL=1). 00103 // If in RX/TX: Go to a wait state where only the synthesizer is 00104 // running (for quick RX / TX turnaround). 00105 #define CCxxx0_SXOFF 0x32 // Turn off crystal oscillator. 00106 #define CCxxx0_SCAL 0x33 // Calibrate frequency synthesizer and turn it off 00107 // (enables quick start). 00108 #define CCxxx0_SRX 0x34 // Enable RX. Perform calibration first if coming from IDLE and 00109 // MCSM0.FS_AUTOCAL=1. 00110 #define CCxxx0_STX 0x35 // In IDLE state: Enable TX. Perform calibration first if 00111 // MCSM0.FS_AUTOCAL=1. If in RX state and CCA is enabled: 00112 // Only go to TX if channel is clear. 00113 #define CCxxx0_SIDLE 0x36 // Exit RX / TX, turn off frequency synthesizer and exit 00114 // Wake-On-Radio mode if applicable. 00115 #define CCxxx0_SAFC 0x37 // Perform AFC adjustment of the frequency synthesizer 00116 #define CCxxx0_SWOR 0x38 // Start automatic RX polling sequence (Wake-on-Radio) 00117 #define CCxxx0_SPWD 0x39 // Enter power down mode when CSn goes high. 00118 #define CCxxx0_SFRX 0x3A // Flush the RX FIFO buffer. 00119 #define CCxxx0_SFTX 0x3B // Flush the TX FIFO buffer. 00120 #define CCxxx0_SWORRST 0x3C // Reset real time clock. 00121 #define CCxxx0_SNOP 0x3D // No operation. May be used to pad strobe commands to two 00122 // bytes for simpler software. 00123 00124 #define CCxxx0_PARTNUM 0x30 00125 #define CCxxx0_VERSION 0x31 00126 #define CCxxx0_FREQEST 0x32 00127 #define CCxxx0_LQI 0x33 00128 #define CCxxx0_RSSI 0x34 00129 #define CCxxx0_MARCSTATE 0x35 00130 #define CCxxx0_WORTIME1 0x36 00131 #define CCxxx0_WORTIME0 0x37 00132 #define CCxxx0_PKTSTATUS 0x38 00133 #define CCxxx0_VCO_VC_DAC 0x39 00134 #define CCxxx0_TXBYTES 0x3A 00135 #define CCxxx0_RXBYTES 0x3B 00136 #define CCxxx0_RCCTRL1_STATUS 0x3C 00137 #define CCxxx0_RCCTRL0_STATUS 0x3D 00138 00139 #define CCxxx0_PATABLE 0x3E 00140 #define CCxxx0_TXFIFO 0x3F 00141 #define CCxxx0_RXFIFO 0x3F 00142 /////////////////////////////////////////////////////////////////////////////////////// 00143 // RF_SETTINGS is a data structure which contains all relevant CCxxx0 registers 00144 typedef struct S_RF_SETTINGS 00145 { 00146 unsigned char FSCTRL1; // Frequency synthesizer control. 00147 unsigned char IOCFG0; // GDO0 output pin configuration 00148 unsigned char FSCTRL0; // Frequency synthesizer control. 00149 unsigned char FREQ2; // Frequency control word, high byte. 00150 unsigned char FREQ1; // Frequency control word, middle byte. 00151 unsigned char FREQ0; // Frequency control word, low byte. 00152 unsigned char MDMCFG4; // Modem configuration. 00153 unsigned char MDMCFG3; // Modem configuration. 00154 unsigned char MDMCFG2; // Modem configuration. 00155 unsigned char MDMCFG1; // Modem configuration. 00156 unsigned char MDMCFG0; // Modem configuration. 00157 unsigned char CHANNR; // Channel number. 00158 unsigned char DEVIATN; // Modem deviation setting (when FSK modulation is enabled). 00159 unsigned char FREND1; // Front end RX configuration. 00160 unsigned char FREND0; // Front end RX configuration. 00161 unsigned char MCSM0; // Main Radio Control State Machine configuration. 00162 unsigned char FOCCFG; // Frequency Offset Compensation Configuration. 00163 unsigned char BSCFG; // Bit synchronization Configuration. 00164 unsigned char AGCCTRL2; // AGC control. 00165 unsigned char AGCCTRL1; // AGC control. 00166 unsigned char AGCCTRL0; // AGC control. 00167 unsigned char FSCAL3; // Frequency synthesizer calibration. 00168 unsigned char FSCAL2; // Frequency synthesizer calibration. 00169 unsigned char FSCAL1; // Frequency synthesizer calibration. 00170 unsigned char FSCAL0; // Frequency synthesizer calibration. 00171 unsigned char FSTEST; // Frequency synthesizer calibration control 00172 unsigned char TEST2; // Various test settings. 00173 unsigned char TEST1; // Various test settings. 00174 unsigned char TEST0; // Various test settings. 00175 unsigned char FIFOTHR; // RXFIFO and TXFIFO thresholds. 00176 unsigned char IOCFG2; // GDO2 output pin configuration 00177 unsigned char PKTCTRL1; // Packet automation control. 00178 unsigned char PKTCTRL0; // Packet automation control. 00179 unsigned char ADDR; // Device address. 00180 unsigned char PKTLEN; // Packet length. 00181 unsigned char MCSM1; // Main Radio Control State Machine configuration. 00182 } RF_SETTINGS; 00183 /////////////////////////////////////////////////////////////////////////////////////// 00184 // Definitions to support burst/single access: 00185 #define WRITE_BURST 0x40 00186 #define READ_SINGLE 0x80 00187 #define READ_BURST 0xC0 00188 /////////////////////////////////////////////////////////////////////////////////////// 00189 #define CRC_OK 0x80 00190 #define RSSI 0 00191 #define LQI 1 00192 #define BYTES_IN_RXFIFO 0x7F 00193 /////////////////////////////////////////////////////////////////////////////////////// 00194 // Definitions for chip status 00195 #define CHIP_RDY 0x80 00196 #define CHIP_STATE_MASK 0x70 00197 #define CHIP_STATE_IDLE 0x00 00198 #define CHIP_STATE_RX 0x10 00199 #define CHIP_STATE_TX 0x20 00200 #define CHIP_STATE_FSTON 0x30 00201 #define CHIP_STATE_CALIBRATE 0x40 00202 #define CHIP_STATE_SETTLING 0x50 00203 #define CHIP_STATE_RXFIFO_OVERFLOW 0x60 00204 #define CHIP_STATE_TXFIFO_UNDERFLOW 0x70 00205 #define FIFO_BYTES_MASK 0x0F 00206 /////////////////////////////////////////////////////////////////////////////////////// 00207 /** 00208 * CC1101 Low-Power Sub-1 GHz RF Transceiver . 00209 */ 00210 00211 class CC1101 00212 { 00213 public: 00214 /** 00215 * Constructor. 00216 * 00217 * @param mosi mbed pin to use for MOSI line of SPI interface. 00218 * @param miso mbed pin to use for MISO line of SPI interface. 00219 * @param clk mbed pin to use for SCK line of SPI interface. 00220 * @param csn mbed pin to use for not chip select line of SPI interface. 00221 * @param RDmiso mbed pin connected to SPI MISO pin for CC1101 RDY read. 00222 */ 00223 CC1101(PinName mosi, PinName miso, PinName clk, PinName csn, PinName RDmiso); 00224 00225 /** 00226 * Initialize CC1101 parameters. 00227 */ 00228 void init(void); 00229 00230 /** 00231 * This function gets the value of a single specified CCxxx0 register. 00232 * 00233 * @param addr Value of the accessed CCxxx0 register 00234 * @return Value of the accessed CCxxx0 register 00235 */ 00236 unsigned char ReadReg(unsigned char addr); 00237 00238 /** 00239 * This function reads multiple CCxxx0 register, using SPI burst access. 00240 * 00241 * @param addr Value of the accessed CCxxx0 register 00242 * @param *buffer Pointer to a byte array which stores the values read from a 00243 * corresponding range of CCxxx0 registers. 00244 * @param count Number of bytes to be read from the subsequent CCxxx0 registers. 00245 */ 00246 void ReadBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count); 00247 00248 /** 00249 * Function for writing to a single CCxxx0 register 00250 * 00251 * @param addr Address of the first CCxxx0 register to be accessed. 00252 * @param value Value to be written to the specified CCxxx0 register. 00253 */ 00254 void WriteReg(unsigned char addr, unsigned char value); 00255 00256 /** 00257 * This function writes to multiple CCxxx0 register, using SPI burst access. 00258 * 00259 * @param addr Address of the first CCxxx0 register to be accessed. 00260 * @param *buffer Array of bytes to be written into a corresponding range of 00261 * CCxx00 registers, starting by the address specified in _addr_. 00262 * @param count Number of bytes to be written to the subsequent CCxxx0 registers. 00263 */ 00264 void WriteBurstReg(unsigned char addr, unsigned char *buffer, unsigned char count); 00265 00266 /** 00267 * This function can be used to transmit a packet with packet length up to 63 bytes. 00268 * 00269 * @param *txBuffer Pointer to a buffer containing the data that are going to be transmitted 00270 * @param size The size of the txBuffer 00271 */ 00272 void SendPacket(unsigned char *txBuffer, unsigned char size); 00273 00274 /** 00275 * This function check if the TX FIFO is empty 00276 * 00277 * @return Return value is 1 if the TX FIFO buffer is empty or else 0 00278 */ 00279 unsigned char TxFifoEmpty(void); 00280 00281 /** 00282 * This function can be used to receive a packet of variable packet length (first byte in the packet 00283 * must be the length byte). The packet length should not exceed the RX FIFO size. 00284 * 00285 * @param *rxBuffer Pointer to the buffer where the incoming data should be stored 00286 * @param *length Pointer to a variable containing the size of the buffer where the incoming data should be 00287 * stored. After this function returns, that variable holds the packet length. 00288 * @return Return value is 1 if CRC OK or else 0 if CRC NOT OK (or no packet was put in the RX FIFO due to filtering) 00289 */ 00290 int ReceivePacket(unsigned char *rxBuffer, unsigned char *length); 00291 00292 /** 00293 * This function check if the RX FIFO is empty 00294 * 00295 * @return Return value is 1 if the RX FIFO buffer is empty or else 0 00296 */ 00297 unsigned char RxFifoEmpty(void); 00298 00299 /** 00300 * This function returns the Chip Status RX register 00301 * 00302 * @return Return the Chip Status RX register 00303 */ 00304 unsigned char ReadChipStatusRX(void); 00305 00306 /** 00307 * This function returns the Chip Status TX register 00308 * 00309 * @return Return the Chip Status TX register 00310 */ 00311 unsigned char ReadChipStatusTX(void); 00312 00313 /** 00314 * This function returns the RSSI value based from the last packet received 00315 * 00316 * @return Return the RSSI value. 00317 */ 00318 unsigned char RdRSSI(void); 00319 00320 /** 00321 * This function returns the LQI value based from the last packet received 00322 * 00323 * @return Return the LQI value. 00324 */ 00325 unsigned char RdLQI(void); 00326 00327 /** 00328 * This function flushes the RX FIFO buffer. 00329 */ 00330 void FlushRX(void); 00331 00332 /** 00333 * This function flushes the TX FIFO buffer. 00334 */ 00335 void FlushTX(void); 00336 00337 /** 00338 * This function change the state of CC1101 to RX mode. 00339 */ 00340 void RXMode(void); 00341 00342 protected: 00343 void RESET_CCxxx0(void); 00344 void POWER_UP_RESET_CCxxx0(void); 00345 unsigned char ReadStatus(unsigned char addr); 00346 unsigned char Strobe(unsigned char strobe); 00347 void WriteRfSettings(RF_SETTINGS *pRfSettings); 00348 00349 SPI _spi; 00350 DigitalOut _csn; 00351 DigitalIn _RDmiso; 00352 unsigned char rssi; 00353 unsigned char lqi; 00354 }; 00355 /////////////////////////////////////////////////////////////////////////////////////// 00356 #endif
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