Alexan E
blinky example from NXP code bundle for LPC11Uxx. No mbed library used
KEIL_LPC11U_COMMON_LIB/timer32.c@1:0f1be4e75668, 2012-05-28 (annotated)
- Committer:
- alexan_e
- Date:
- Mon May 28 00:13:23 2012 +0000
- Revision:
- 1:0f1be4e75668
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| alexan_e | 1:0f1be4e75668 | 1 | /**************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 2 | * $Id:: timer32.c 9190 2012-02-16 20:59:45Z nxp41306 $ |
| alexan_e | 1:0f1be4e75668 | 3 | * Project: NXP LPC11Uxx 32-bit timer example |
| alexan_e | 1:0f1be4e75668 | 4 | * |
| alexan_e | 1:0f1be4e75668 | 5 | * Description: |
| alexan_e | 1:0f1be4e75668 | 6 | * This file contains 32-bit timer code example which include timer |
| alexan_e | 1:0f1be4e75668 | 7 | * initialization, timer interrupt handler, and related APIs for |
| alexan_e | 1:0f1be4e75668 | 8 | * timer setup. |
| alexan_e | 1:0f1be4e75668 | 9 | * |
| alexan_e | 1:0f1be4e75668 | 10 | **************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 11 | * Software that is described herein is for illustrative purposes only |
| alexan_e | 1:0f1be4e75668 | 12 | * which provides customers with programming information regarding the |
| alexan_e | 1:0f1be4e75668 | 13 | * products. This software is supplied "AS IS" without any warranties. |
| alexan_e | 1:0f1be4e75668 | 14 | * NXP Semiconductors assumes no responsibility or liability for the |
| alexan_e | 1:0f1be4e75668 | 15 | * use of the software, conveys no license or title under any patent, |
| alexan_e | 1:0f1be4e75668 | 16 | * copyright, or mask work right to the product. NXP Semiconductors |
| alexan_e | 1:0f1be4e75668 | 17 | * reserves the right to make changes in the software without |
| alexan_e | 1:0f1be4e75668 | 18 | * notification. NXP Semiconductors also make no representation or |
| alexan_e | 1:0f1be4e75668 | 19 | * warranty that such application will be suitable for the specified |
| alexan_e | 1:0f1be4e75668 | 20 | * use without further testing or modification. |
| alexan_e | 1:0f1be4e75668 | 21 | |
| alexan_e | 1:0f1be4e75668 | 22 | * Permission to use, copy, modify, and distribute this software and its |
| alexan_e | 1:0f1be4e75668 | 23 | * documentation is hereby granted, under NXP Semiconductors' |
| alexan_e | 1:0f1be4e75668 | 24 | * relevant copyright in the software, without fee, provided that it |
| alexan_e | 1:0f1be4e75668 | 25 | * is used in conjunction with NXP Semiconductors microcontrollers. This |
| alexan_e | 1:0f1be4e75668 | 26 | * copyright, permission, and disclaimer notice must appear in all copies of |
| alexan_e | 1:0f1be4e75668 | 27 | * this code. |
| alexan_e | 1:0f1be4e75668 | 28 | |
| alexan_e | 1:0f1be4e75668 | 29 | ****************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 30 | |
| alexan_e | 1:0f1be4e75668 | 31 | #include "LPC11Uxx.h" |
| alexan_e | 1:0f1be4e75668 | 32 | #include "timer32.h" |
| alexan_e | 1:0f1be4e75668 | 33 | #include "nmi.h" |
| alexan_e | 1:0f1be4e75668 | 34 | |
| alexan_e | 1:0f1be4e75668 | 35 | volatile uint32_t timer32_0_counter[4] = {0,0,0,0}; |
| alexan_e | 1:0f1be4e75668 | 36 | volatile uint32_t timer32_1_counter[4] = {0,0,0,0}; |
| alexan_e | 1:0f1be4e75668 | 37 | volatile uint32_t timer32_0_capture[4] = {0,0,0,0}; |
| alexan_e | 1:0f1be4e75668 | 38 | volatile uint32_t timer32_1_capture[4] = {0,0,0,0}; |
| alexan_e | 1:0f1be4e75668 | 39 | volatile uint32_t timer32_0_period = 0; |
| alexan_e | 1:0f1be4e75668 | 40 | volatile uint32_t timer32_1_period = 0; |
| alexan_e | 1:0f1be4e75668 | 41 | |
| alexan_e | 1:0f1be4e75668 | 42 | /***************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 43 | ** Function name: delay32Ms |
| alexan_e | 1:0f1be4e75668 | 44 | ** |
| alexan_e | 1:0f1be4e75668 | 45 | ** Descriptions: Start the timer delay in milo seconds |
| alexan_e | 1:0f1be4e75668 | 46 | ** until elapsed |
| alexan_e | 1:0f1be4e75668 | 47 | ** |
| alexan_e | 1:0f1be4e75668 | 48 | ** parameters: timer number, Delay value in milo second |
| alexan_e | 1:0f1be4e75668 | 49 | ** |
| alexan_e | 1:0f1be4e75668 | 50 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 51 | ** |
| alexan_e | 1:0f1be4e75668 | 52 | *****************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 53 | void delay32Ms(uint8_t timer_num, uint32_t delayInMs) |
| alexan_e | 1:0f1be4e75668 | 54 | { |
| alexan_e | 1:0f1be4e75668 | 55 | if (timer_num == 0) |
| alexan_e | 1:0f1be4e75668 | 56 | { |
| alexan_e | 1:0f1be4e75668 | 57 | /* setup timer #0 for delay */ |
| alexan_e | 1:0f1be4e75668 | 58 | LPC_CT32B0->TCR = 0x02; /* reset timer */ |
| alexan_e | 1:0f1be4e75668 | 59 | LPC_CT32B0->PR = 0x00; /* set prescaler to zero */ |
| alexan_e | 1:0f1be4e75668 | 60 | LPC_CT32B0->MR0 = delayInMs * (SystemCoreClock / 1000); |
| alexan_e | 1:0f1be4e75668 | 61 | LPC_CT32B0->IR = 0xff; /* reset all interrrupts */ |
| alexan_e | 1:0f1be4e75668 | 62 | LPC_CT32B0->MCR = 0x04; /* stop timer on match */ |
| alexan_e | 1:0f1be4e75668 | 63 | LPC_CT32B0->TCR = 0x01; /* start timer */ |
| alexan_e | 1:0f1be4e75668 | 64 | |
| alexan_e | 1:0f1be4e75668 | 65 | /* wait until delay time has elapsed */ |
| alexan_e | 1:0f1be4e75668 | 66 | while (LPC_CT32B0->TCR & 0x01); |
| alexan_e | 1:0f1be4e75668 | 67 | } |
| alexan_e | 1:0f1be4e75668 | 68 | else if (timer_num == 1) |
| alexan_e | 1:0f1be4e75668 | 69 | { |
| alexan_e | 1:0f1be4e75668 | 70 | /* setup timer #1 for delay */ |
| alexan_e | 1:0f1be4e75668 | 71 | LPC_CT32B1->TCR = 0x02; /* reset timer */ |
| alexan_e | 1:0f1be4e75668 | 72 | LPC_CT32B1->PR = 0x00; /* set prescaler to zero */ |
| alexan_e | 1:0f1be4e75668 | 73 | LPC_CT32B1->MR0 = delayInMs * (SystemCoreClock / 1000); |
| alexan_e | 1:0f1be4e75668 | 74 | LPC_CT32B1->IR = 0xff; /* reset all interrrupts */ |
| alexan_e | 1:0f1be4e75668 | 75 | LPC_CT32B1->MCR = 0x04; /* stop timer on match */ |
| alexan_e | 1:0f1be4e75668 | 76 | LPC_CT32B1->TCR = 0x01; /* start timer */ |
| alexan_e | 1:0f1be4e75668 | 77 | |
| alexan_e | 1:0f1be4e75668 | 78 | /* wait until delay time has elapsed */ |
| alexan_e | 1:0f1be4e75668 | 79 | while (LPC_CT32B1->TCR & 0x01); |
| alexan_e | 1:0f1be4e75668 | 80 | } |
| alexan_e | 1:0f1be4e75668 | 81 | return; |
| alexan_e | 1:0f1be4e75668 | 82 | } |
| alexan_e | 1:0f1be4e75668 | 83 | |
| alexan_e | 1:0f1be4e75668 | 84 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 85 | ** Function name: TIMER32_0_IRQHandler |
| alexan_e | 1:0f1be4e75668 | 86 | ** |
| alexan_e | 1:0f1be4e75668 | 87 | ** Descriptions: Timer/CounterX and captureX interrupt handler |
| alexan_e | 1:0f1be4e75668 | 88 | ** |
| alexan_e | 1:0f1be4e75668 | 89 | ** parameters: None |
| alexan_e | 1:0f1be4e75668 | 90 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 91 | ** |
| alexan_e | 1:0f1be4e75668 | 92 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 93 | void TIMER32_0_IRQHandler(void) |
| alexan_e | 1:0f1be4e75668 | 94 | { |
| alexan_e | 1:0f1be4e75668 | 95 | if ( LPC_CT32B0->IR & (0x01<<0) ) |
| alexan_e | 1:0f1be4e75668 | 96 | { |
| alexan_e | 1:0f1be4e75668 | 97 | LPC_CT32B0->IR = 0x1<<0; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 98 | timer32_0_counter[0]++; |
| alexan_e | 1:0f1be4e75668 | 99 | } |
| alexan_e | 1:0f1be4e75668 | 100 | if ( LPC_CT32B0->IR & (0x01<<1) ) |
| alexan_e | 1:0f1be4e75668 | 101 | { |
| alexan_e | 1:0f1be4e75668 | 102 | LPC_CT32B0->IR = 0x1<<1; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 103 | timer32_0_counter[1]++; |
| alexan_e | 1:0f1be4e75668 | 104 | } |
| alexan_e | 1:0f1be4e75668 | 105 | if ( LPC_CT32B0->IR & (0x01<<2) ) |
| alexan_e | 1:0f1be4e75668 | 106 | { |
| alexan_e | 1:0f1be4e75668 | 107 | LPC_CT32B0->IR = 0x1<<2; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 108 | timer32_0_counter[2]++; |
| alexan_e | 1:0f1be4e75668 | 109 | } |
| alexan_e | 1:0f1be4e75668 | 110 | if ( LPC_CT32B0->IR & (0x01<<3) ) |
| alexan_e | 1:0f1be4e75668 | 111 | { |
| alexan_e | 1:0f1be4e75668 | 112 | LPC_CT32B0->IR = 0x1<<3; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 113 | timer32_0_counter[3]++; |
| alexan_e | 1:0f1be4e75668 | 114 | } |
| alexan_e | 1:0f1be4e75668 | 115 | if ( LPC_CT32B0->IR & (0x1<<4) ) |
| alexan_e | 1:0f1be4e75668 | 116 | { |
| alexan_e | 1:0f1be4e75668 | 117 | LPC_CT32B0->IR = 0x1<<4; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 118 | timer32_0_capture[0]++; |
| alexan_e | 1:0f1be4e75668 | 119 | } |
| alexan_e | 1:0f1be4e75668 | 120 | if ( LPC_CT32B0->IR & (0x1<<5) ) |
| alexan_e | 1:0f1be4e75668 | 121 | { |
| alexan_e | 1:0f1be4e75668 | 122 | LPC_CT32B0->IR = 0x1<<5; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 123 | timer32_0_capture[1]++; |
| alexan_e | 1:0f1be4e75668 | 124 | } |
| alexan_e | 1:0f1be4e75668 | 125 | if ( LPC_CT32B0->IR & (0x1<<6) ) |
| alexan_e | 1:0f1be4e75668 | 126 | { |
| alexan_e | 1:0f1be4e75668 | 127 | LPC_CT32B0->IR = 0x1<<6; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 128 | timer32_0_capture[2]++; |
| alexan_e | 1:0f1be4e75668 | 129 | } |
| alexan_e | 1:0f1be4e75668 | 130 | if ( LPC_CT32B0->IR & (0x1<<7) ) |
| alexan_e | 1:0f1be4e75668 | 131 | { |
| alexan_e | 1:0f1be4e75668 | 132 | LPC_CT32B0->IR = 0x1<<7; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 133 | timer32_0_capture[3]++; |
| alexan_e | 1:0f1be4e75668 | 134 | } |
| alexan_e | 1:0f1be4e75668 | 135 | return; |
| alexan_e | 1:0f1be4e75668 | 136 | } |
| alexan_e | 1:0f1be4e75668 | 137 | |
| alexan_e | 1:0f1be4e75668 | 138 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 139 | ** Function name: TIMER32_1_IRQHandler |
| alexan_e | 1:0f1be4e75668 | 140 | ** |
| alexan_e | 1:0f1be4e75668 | 141 | ** Descriptions: Timer/CounterX and captureX interrupt handler |
| alexan_e | 1:0f1be4e75668 | 142 | ** |
| alexan_e | 1:0f1be4e75668 | 143 | ** parameters: None |
| alexan_e | 1:0f1be4e75668 | 144 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 145 | ** |
| alexan_e | 1:0f1be4e75668 | 146 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 147 | void TIMER32_1_IRQHandler(void) |
| alexan_e | 1:0f1be4e75668 | 148 | { |
| alexan_e | 1:0f1be4e75668 | 149 | if ( LPC_CT32B1->IR & (0x01<<0) ) |
| alexan_e | 1:0f1be4e75668 | 150 | { |
| alexan_e | 1:0f1be4e75668 | 151 | LPC_CT32B1->IR = 0x1<<0; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 152 | timer32_1_counter[0]++; |
| alexan_e | 1:0f1be4e75668 | 153 | } |
| alexan_e | 1:0f1be4e75668 | 154 | if ( LPC_CT32B1->IR & (0x01<<1) ) |
| alexan_e | 1:0f1be4e75668 | 155 | { |
| alexan_e | 1:0f1be4e75668 | 156 | LPC_CT32B1->IR = 0x1<<1; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 157 | timer32_1_counter[1]++; |
| alexan_e | 1:0f1be4e75668 | 158 | } |
| alexan_e | 1:0f1be4e75668 | 159 | if ( LPC_CT32B1->IR & (0x01<<2) ) |
| alexan_e | 1:0f1be4e75668 | 160 | { |
| alexan_e | 1:0f1be4e75668 | 161 | LPC_CT32B1->IR = 0x1<<2; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 162 | timer32_1_counter[2]++; |
| alexan_e | 1:0f1be4e75668 | 163 | } |
| alexan_e | 1:0f1be4e75668 | 164 | if ( LPC_CT32B1->IR & (0x01<<3) ) |
| alexan_e | 1:0f1be4e75668 | 165 | { |
| alexan_e | 1:0f1be4e75668 | 166 | LPC_CT32B1->IR = 0x1<<3; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 167 | timer32_1_counter[3]++; |
| alexan_e | 1:0f1be4e75668 | 168 | } |
| alexan_e | 1:0f1be4e75668 | 169 | if ( LPC_CT32B1->IR & (0x1<<4) ) |
| alexan_e | 1:0f1be4e75668 | 170 | { |
| alexan_e | 1:0f1be4e75668 | 171 | LPC_CT32B1->IR = 0x1<<4; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 172 | timer32_1_capture[0]++; |
| alexan_e | 1:0f1be4e75668 | 173 | } |
| alexan_e | 1:0f1be4e75668 | 174 | if ( LPC_CT32B1->IR & (0x1<<5) ) |
| alexan_e | 1:0f1be4e75668 | 175 | { |
| alexan_e | 1:0f1be4e75668 | 176 | LPC_CT32B1->IR = 0x1<<5; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 177 | timer32_1_capture[1]++; |
| alexan_e | 1:0f1be4e75668 | 178 | } |
| alexan_e | 1:0f1be4e75668 | 179 | if ( LPC_CT32B1->IR & (0x1<<6) ) |
| alexan_e | 1:0f1be4e75668 | 180 | { |
| alexan_e | 1:0f1be4e75668 | 181 | LPC_CT32B1->IR = 0x1<<6; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 182 | timer32_1_capture[2]++; |
| alexan_e | 1:0f1be4e75668 | 183 | } |
| alexan_e | 1:0f1be4e75668 | 184 | if ( LPC_CT32B1->IR & (0x1<<7) ) |
| alexan_e | 1:0f1be4e75668 | 185 | { |
| alexan_e | 1:0f1be4e75668 | 186 | LPC_CT32B1->IR = 0x1<<7; /* clear interrupt flag */ |
| alexan_e | 1:0f1be4e75668 | 187 | timer32_1_capture[3]++; |
| alexan_e | 1:0f1be4e75668 | 188 | } |
| alexan_e | 1:0f1be4e75668 | 189 | return; |
| alexan_e | 1:0f1be4e75668 | 190 | } |
| alexan_e | 1:0f1be4e75668 | 191 | |
| alexan_e | 1:0f1be4e75668 | 192 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 193 | ** Function name: enable_timer |
| alexan_e | 1:0f1be4e75668 | 194 | ** |
| alexan_e | 1:0f1be4e75668 | 195 | ** Descriptions: Enable timer |
| alexan_e | 1:0f1be4e75668 | 196 | ** |
| alexan_e | 1:0f1be4e75668 | 197 | ** parameters: timer number: 0 or 1 |
| alexan_e | 1:0f1be4e75668 | 198 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 199 | ** |
| alexan_e | 1:0f1be4e75668 | 200 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 201 | void enable_timer32(uint8_t timer_num) |
| alexan_e | 1:0f1be4e75668 | 202 | { |
| alexan_e | 1:0f1be4e75668 | 203 | if ( timer_num == 0 ) |
| alexan_e | 1:0f1be4e75668 | 204 | { |
| alexan_e | 1:0f1be4e75668 | 205 | LPC_CT32B0->TCR = 1; |
| alexan_e | 1:0f1be4e75668 | 206 | } |
| alexan_e | 1:0f1be4e75668 | 207 | else |
| alexan_e | 1:0f1be4e75668 | 208 | { |
| alexan_e | 1:0f1be4e75668 | 209 | LPC_CT32B1->TCR = 1; |
| alexan_e | 1:0f1be4e75668 | 210 | } |
| alexan_e | 1:0f1be4e75668 | 211 | return; |
| alexan_e | 1:0f1be4e75668 | 212 | } |
| alexan_e | 1:0f1be4e75668 | 213 | |
| alexan_e | 1:0f1be4e75668 | 214 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 215 | ** Function name: disable_timer |
| alexan_e | 1:0f1be4e75668 | 216 | ** |
| alexan_e | 1:0f1be4e75668 | 217 | ** Descriptions: Disable timer |
| alexan_e | 1:0f1be4e75668 | 218 | ** |
| alexan_e | 1:0f1be4e75668 | 219 | ** parameters: timer number: 0 or 1 |
| alexan_e | 1:0f1be4e75668 | 220 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 221 | ** |
| alexan_e | 1:0f1be4e75668 | 222 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 223 | void disable_timer32(uint8_t timer_num) |
| alexan_e | 1:0f1be4e75668 | 224 | { |
| alexan_e | 1:0f1be4e75668 | 225 | if ( timer_num == 0 ) |
| alexan_e | 1:0f1be4e75668 | 226 | { |
| alexan_e | 1:0f1be4e75668 | 227 | LPC_CT32B0->TCR = 0; |
| alexan_e | 1:0f1be4e75668 | 228 | } |
| alexan_e | 1:0f1be4e75668 | 229 | else |
| alexan_e | 1:0f1be4e75668 | 230 | { |
| alexan_e | 1:0f1be4e75668 | 231 | LPC_CT32B1->TCR = 0; |
| alexan_e | 1:0f1be4e75668 | 232 | } |
| alexan_e | 1:0f1be4e75668 | 233 | return; |
| alexan_e | 1:0f1be4e75668 | 234 | } |
| alexan_e | 1:0f1be4e75668 | 235 | |
| alexan_e | 1:0f1be4e75668 | 236 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 237 | ** Function name: reset_timer |
| alexan_e | 1:0f1be4e75668 | 238 | ** |
| alexan_e | 1:0f1be4e75668 | 239 | ** Descriptions: Reset timer |
| alexan_e | 1:0f1be4e75668 | 240 | ** |
| alexan_e | 1:0f1be4e75668 | 241 | ** parameters: timer number: 0 or 1 |
| alexan_e | 1:0f1be4e75668 | 242 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 243 | ** |
| alexan_e | 1:0f1be4e75668 | 244 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 245 | void reset_timer32(uint8_t timer_num) |
| alexan_e | 1:0f1be4e75668 | 246 | { |
| alexan_e | 1:0f1be4e75668 | 247 | uint32_t regVal; |
| alexan_e | 1:0f1be4e75668 | 248 | |
| alexan_e | 1:0f1be4e75668 | 249 | if ( timer_num == 0 ) |
| alexan_e | 1:0f1be4e75668 | 250 | { |
| alexan_e | 1:0f1be4e75668 | 251 | regVal = LPC_CT32B0->TCR; |
| alexan_e | 1:0f1be4e75668 | 252 | regVal |= 0x02; |
| alexan_e | 1:0f1be4e75668 | 253 | LPC_CT32B0->TCR = regVal; |
| alexan_e | 1:0f1be4e75668 | 254 | } |
| alexan_e | 1:0f1be4e75668 | 255 | else |
| alexan_e | 1:0f1be4e75668 | 256 | { |
| alexan_e | 1:0f1be4e75668 | 257 | regVal = LPC_CT32B1->TCR; |
| alexan_e | 1:0f1be4e75668 | 258 | regVal |= 0x02; |
| alexan_e | 1:0f1be4e75668 | 259 | LPC_CT32B1->TCR = regVal; |
| alexan_e | 1:0f1be4e75668 | 260 | } |
| alexan_e | 1:0f1be4e75668 | 261 | return; |
| alexan_e | 1:0f1be4e75668 | 262 | } |
| alexan_e | 1:0f1be4e75668 | 263 | |
| alexan_e | 1:0f1be4e75668 | 264 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 265 | ** Function name: set_timer_capture |
| alexan_e | 1:0f1be4e75668 | 266 | ** |
| alexan_e | 1:0f1be4e75668 | 267 | ** Descriptions: Set timer capture based on location |
| alexan_e | 1:0f1be4e75668 | 268 | ** |
| alexan_e | 1:0f1be4e75668 | 269 | ** parameters: timer number: 0~1, location 0~2 |
| alexan_e | 1:0f1be4e75668 | 270 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 271 | ** |
| alexan_e | 1:0f1be4e75668 | 272 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 273 | void set_timer32_capture(uint8_t timer_num, uint8_t location ) |
| alexan_e | 1:0f1be4e75668 | 274 | { |
| alexan_e | 1:0f1be4e75668 | 275 | if ( timer_num == 0 ) |
| alexan_e | 1:0f1be4e75668 | 276 | { |
| alexan_e | 1:0f1be4e75668 | 277 | /* Timer0_32 I/O config */ |
| alexan_e | 1:0f1be4e75668 | 278 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 279 | { |
| alexan_e | 1:0f1be4e75668 | 280 | LPC_IOCON->PIO1_28 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 281 | LPC_IOCON->PIO1_28 |= 0x01; /* Timer0_32 CAP0 */ |
| alexan_e | 1:0f1be4e75668 | 282 | LPC_IOCON->PIO1_29 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 283 | LPC_IOCON->PIO1_29 |= 0x02; /* Timer0_32 CAP1 */ |
| alexan_e | 1:0f1be4e75668 | 284 | } |
| alexan_e | 1:0f1be4e75668 | 285 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 286 | { |
| alexan_e | 1:0f1be4e75668 | 287 | LPC_IOCON->PIO0_17 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 288 | LPC_IOCON->PIO0_17 |= 0x02; /* Timer0_32 CAP0 */ |
| alexan_e | 1:0f1be4e75668 | 289 | } |
| alexan_e | 1:0f1be4e75668 | 290 | else |
| alexan_e | 1:0f1be4e75668 | 291 | { |
| alexan_e | 1:0f1be4e75668 | 292 | while ( 1 ); /* Fatal location number error */ |
| alexan_e | 1:0f1be4e75668 | 293 | } |
| alexan_e | 1:0f1be4e75668 | 294 | } |
| alexan_e | 1:0f1be4e75668 | 295 | else |
| alexan_e | 1:0f1be4e75668 | 296 | { |
| alexan_e | 1:0f1be4e75668 | 297 | /* Timer1_32 I/O config */ |
| alexan_e | 1:0f1be4e75668 | 298 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 299 | { |
| alexan_e | 1:0f1be4e75668 | 300 | // LPC_IOCON->PIO1_4 &= ~0x07; /* Timer1_32 I/O config */ |
| alexan_e | 1:0f1be4e75668 | 301 | // LPC_IOCON->PIO1_4 |= 0x01; /* Timer1_32 CAP0 */ |
| alexan_e | 1:0f1be4e75668 | 302 | // LPC_IOCON->PIO1_5 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 303 | // LPC_IOCON->PIO1_5 |= 0x01; /* Timer1_32 CAP1 */ |
| alexan_e | 1:0f1be4e75668 | 304 | } |
| alexan_e | 1:0f1be4e75668 | 305 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 306 | { |
| alexan_e | 1:0f1be4e75668 | 307 | LPC_IOCON->TMS_PIO0_12 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 308 | LPC_IOCON->TMS_PIO0_12 |= 0x03; /* Timer1_32 CAP0 */ |
| alexan_e | 1:0f1be4e75668 | 309 | } |
| alexan_e | 1:0f1be4e75668 | 310 | else |
| alexan_e | 1:0f1be4e75668 | 311 | { |
| alexan_e | 1:0f1be4e75668 | 312 | while ( 1 ); /* Fatal location number error */ |
| alexan_e | 1:0f1be4e75668 | 313 | } |
| alexan_e | 1:0f1be4e75668 | 314 | } |
| alexan_e | 1:0f1be4e75668 | 315 | return; |
| alexan_e | 1:0f1be4e75668 | 316 | } |
| alexan_e | 1:0f1be4e75668 | 317 | |
| alexan_e | 1:0f1be4e75668 | 318 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 319 | ** Function name: set_timer_match |
| alexan_e | 1:0f1be4e75668 | 320 | ** |
| alexan_e | 1:0f1be4e75668 | 321 | ** Descriptions: Set timer match based on location |
| alexan_e | 1:0f1be4e75668 | 322 | ** |
| alexan_e | 1:0f1be4e75668 | 323 | ** parameters: timer number: 0~1, location 0~2 |
| alexan_e | 1:0f1be4e75668 | 324 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 325 | ** |
| alexan_e | 1:0f1be4e75668 | 326 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 327 | void set_timer32_match(uint8_t timer_num, uint8_t match_enable, uint8_t location) |
| alexan_e | 1:0f1be4e75668 | 328 | { |
| alexan_e | 1:0f1be4e75668 | 329 | if ( timer_num == 0 ) |
| alexan_e | 1:0f1be4e75668 | 330 | { |
| alexan_e | 1:0f1be4e75668 | 331 | if ( match_enable & 0x01 ) |
| alexan_e | 1:0f1be4e75668 | 332 | { |
| alexan_e | 1:0f1be4e75668 | 333 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 334 | { |
| alexan_e | 1:0f1be4e75668 | 335 | LPC_IOCON->PIO0_18 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 336 | LPC_IOCON->PIO0_18 |= 0x02; /* Timer0_32 MAT0 */ |
| alexan_e | 1:0f1be4e75668 | 337 | } |
| alexan_e | 1:0f1be4e75668 | 338 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 339 | { |
| alexan_e | 1:0f1be4e75668 | 340 | LPC_IOCON->PIO1_24 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 341 | LPC_IOCON->PIO1_24 |= 0x01; /* Timer0_32 MAT0 */ |
| alexan_e | 1:0f1be4e75668 | 342 | } |
| alexan_e | 1:0f1be4e75668 | 343 | } |
| alexan_e | 1:0f1be4e75668 | 344 | if ( match_enable & 0x02 ) |
| alexan_e | 1:0f1be4e75668 | 345 | { |
| alexan_e | 1:0f1be4e75668 | 346 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 347 | { |
| alexan_e | 1:0f1be4e75668 | 348 | LPC_IOCON->PIO0_19 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 349 | LPC_IOCON->PIO0_19 |= 0x02; /* Timer0_32 MAT1 */ |
| alexan_e | 1:0f1be4e75668 | 350 | } |
| alexan_e | 1:0f1be4e75668 | 351 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 352 | { |
| alexan_e | 1:0f1be4e75668 | 353 | LPC_IOCON->PIO1_25 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 354 | LPC_IOCON->PIO1_25 |= 0x01; /* Timer0_32 MAT1 */ |
| alexan_e | 1:0f1be4e75668 | 355 | } |
| alexan_e | 1:0f1be4e75668 | 356 | } |
| alexan_e | 1:0f1be4e75668 | 357 | if ( match_enable & 0x04 ) |
| alexan_e | 1:0f1be4e75668 | 358 | { |
| alexan_e | 1:0f1be4e75668 | 359 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 360 | { |
| alexan_e | 1:0f1be4e75668 | 361 | LPC_IOCON->PIO0_1 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 362 | LPC_IOCON->PIO0_1 |= 0x02; /* Timer0_32 MAT2 */ |
| alexan_e | 1:0f1be4e75668 | 363 | } |
| alexan_e | 1:0f1be4e75668 | 364 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 365 | { |
| alexan_e | 1:0f1be4e75668 | 366 | LPC_IOCON->PIO1_26 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 367 | LPC_IOCON->PIO1_26 |= 0x01; /* Timer0_32 MAT2 */ |
| alexan_e | 1:0f1be4e75668 | 368 | } |
| alexan_e | 1:0f1be4e75668 | 369 | } |
| alexan_e | 1:0f1be4e75668 | 370 | if ( match_enable & 0x08 ) |
| alexan_e | 1:0f1be4e75668 | 371 | { |
| alexan_e | 1:0f1be4e75668 | 372 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 373 | { |
| alexan_e | 1:0f1be4e75668 | 374 | LPC_IOCON->TDI_PIO0_11 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 375 | LPC_IOCON->TDI_PIO0_11 |= 0x03; /* Timer0_32 MAT3 */ |
| alexan_e | 1:0f1be4e75668 | 376 | } |
| alexan_e | 1:0f1be4e75668 | 377 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 378 | { |
| alexan_e | 1:0f1be4e75668 | 379 | LPC_IOCON->PIO1_27 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 380 | LPC_IOCON->PIO1_27 |= 0x01; /* Timer0_32 MAT3 */ |
| alexan_e | 1:0f1be4e75668 | 381 | } |
| alexan_e | 1:0f1be4e75668 | 382 | } |
| alexan_e | 1:0f1be4e75668 | 383 | } |
| alexan_e | 1:0f1be4e75668 | 384 | else if ( timer_num == 1 ) |
| alexan_e | 1:0f1be4e75668 | 385 | { |
| alexan_e | 1:0f1be4e75668 | 386 | if ( match_enable & 0x01 ) |
| alexan_e | 1:0f1be4e75668 | 387 | { |
| alexan_e | 1:0f1be4e75668 | 388 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 389 | { |
| alexan_e | 1:0f1be4e75668 | 390 | // LPC_IOCON->PIO1_0 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 391 | // LPC_IOCON->PIO1_0 |= 0x01; /* Timer1_32 MAT0 */ |
| alexan_e | 1:0f1be4e75668 | 392 | } |
| alexan_e | 1:0f1be4e75668 | 393 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 394 | { |
| alexan_e | 1:0f1be4e75668 | 395 | LPC_IOCON->TDO_PIO0_13 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 396 | LPC_IOCON->TDO_PIO0_13 |= 0x03; /* Timer1_32 MAT0 */ |
| alexan_e | 1:0f1be4e75668 | 397 | } |
| alexan_e | 1:0f1be4e75668 | 398 | } |
| alexan_e | 1:0f1be4e75668 | 399 | if ( match_enable & 0x02 ) |
| alexan_e | 1:0f1be4e75668 | 400 | { |
| alexan_e | 1:0f1be4e75668 | 401 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 402 | { |
| alexan_e | 1:0f1be4e75668 | 403 | // LPC_IOCON->PIO1_1 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 404 | // LPC_IOCON->PIO1_1 |= 0x01; /* Timer1_32 MAT1 */ |
| alexan_e | 1:0f1be4e75668 | 405 | } |
| alexan_e | 1:0f1be4e75668 | 406 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 407 | { |
| alexan_e | 1:0f1be4e75668 | 408 | LPC_IOCON->TRST_PIO0_14 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 409 | LPC_IOCON->TRST_PIO0_14 |= 0x03; /* Timer1_32 MAT1 */ |
| alexan_e | 1:0f1be4e75668 | 410 | } |
| alexan_e | 1:0f1be4e75668 | 411 | } |
| alexan_e | 1:0f1be4e75668 | 412 | if ( match_enable & 0x04 ) |
| alexan_e | 1:0f1be4e75668 | 413 | { |
| alexan_e | 1:0f1be4e75668 | 414 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 415 | { |
| alexan_e | 1:0f1be4e75668 | 416 | // LPC_IOCON->PIO1_2 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 417 | // LPC_IOCON->PIO1_2 |= 0x01; /* Timer1_32 MAT2 */ |
| alexan_e | 1:0f1be4e75668 | 418 | } |
| alexan_e | 1:0f1be4e75668 | 419 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 420 | { |
| alexan_e | 1:0f1be4e75668 | 421 | #if __SWD_DISABLED |
| alexan_e | 1:0f1be4e75668 | 422 | LPC_IOCON->SWDIO_PIO0_15 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 423 | LPC_IOCON->SWDIO_PIO0_15 |= 0x03; /* Timer1_32 MAT2 */ |
| alexan_e | 1:0f1be4e75668 | 424 | #endif |
| alexan_e | 1:0f1be4e75668 | 425 | } |
| alexan_e | 1:0f1be4e75668 | 426 | } |
| alexan_e | 1:0f1be4e75668 | 427 | if ( match_enable & 0x08 ) |
| alexan_e | 1:0f1be4e75668 | 428 | { |
| alexan_e | 1:0f1be4e75668 | 429 | if ( location == 0 ) |
| alexan_e | 1:0f1be4e75668 | 430 | { |
| alexan_e | 1:0f1be4e75668 | 431 | // LPC_IOCON->PIO1_3 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 432 | // LPC_IOCON->PIO1_3 |= 0x01; /* Timer1_32 MAT3 */ |
| alexan_e | 1:0f1be4e75668 | 433 | } |
| alexan_e | 1:0f1be4e75668 | 434 | else if ( location == 1 ) |
| alexan_e | 1:0f1be4e75668 | 435 | { |
| alexan_e | 1:0f1be4e75668 | 436 | LPC_IOCON->PIO0_16 &= ~0x07; |
| alexan_e | 1:0f1be4e75668 | 437 | LPC_IOCON->PIO0_16 |= 0x02; /* Timer1_32 MAT3 */ |
| alexan_e | 1:0f1be4e75668 | 438 | } |
| alexan_e | 1:0f1be4e75668 | 439 | } |
| alexan_e | 1:0f1be4e75668 | 440 | } |
| alexan_e | 1:0f1be4e75668 | 441 | return; |
| alexan_e | 1:0f1be4e75668 | 442 | } |
| alexan_e | 1:0f1be4e75668 | 443 | |
| alexan_e | 1:0f1be4e75668 | 444 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 445 | ** Function name: init_timer |
| alexan_e | 1:0f1be4e75668 | 446 | ** |
| alexan_e | 1:0f1be4e75668 | 447 | ** Descriptions: Initialize timer, set timer interval, reset timer, |
| alexan_e | 1:0f1be4e75668 | 448 | ** install timer interrupt handler |
| alexan_e | 1:0f1be4e75668 | 449 | ** |
| alexan_e | 1:0f1be4e75668 | 450 | ** parameters: timer number and timer interval |
| alexan_e | 1:0f1be4e75668 | 451 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 452 | ** |
| alexan_e | 1:0f1be4e75668 | 453 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 454 | void init_timer32(uint8_t timer_num, uint32_t TimerInterval) |
| alexan_e | 1:0f1be4e75668 | 455 | { |
| alexan_e | 1:0f1be4e75668 | 456 | uint32_t i; |
| alexan_e | 1:0f1be4e75668 | 457 | |
| alexan_e | 1:0f1be4e75668 | 458 | if ( timer_num == 0 ) |
| alexan_e | 1:0f1be4e75668 | 459 | { |
| alexan_e | 1:0f1be4e75668 | 460 | /* Some of the I/O pins need to be clearfully planned if |
| alexan_e | 1:0f1be4e75668 | 461 | you use below module because JTAG and TIMER CAP/MAT pins are muxed. */ |
| alexan_e | 1:0f1be4e75668 | 462 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9); |
| alexan_e | 1:0f1be4e75668 | 463 | |
| alexan_e | 1:0f1be4e75668 | 464 | LPC_CT32B0->MR0 = TimerInterval; |
| alexan_e | 1:0f1be4e75668 | 465 | #if TIMER_MATCH |
| alexan_e | 1:0f1be4e75668 | 466 | for ( i = 0; i < 4; i++ ) |
| alexan_e | 1:0f1be4e75668 | 467 | { |
| alexan_e | 1:0f1be4e75668 | 468 | timer32_0_counter[i] = 0; |
| alexan_e | 1:0f1be4e75668 | 469 | } |
| alexan_e | 1:0f1be4e75668 | 470 | set_timer32_match(timer_num, 0x0F, 0); |
| alexan_e | 1:0f1be4e75668 | 471 | LPC_CT32B0->EMR &= ~(0xFF<<4); |
| alexan_e | 1:0f1be4e75668 | 472 | LPC_CT32B0->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10)); /* MR0/1/2/3 Toggle */ |
| alexan_e | 1:0f1be4e75668 | 473 | #else |
| alexan_e | 1:0f1be4e75668 | 474 | for ( i = 0; i < 4; i++ ) |
| alexan_e | 1:0f1be4e75668 | 475 | { |
| alexan_e | 1:0f1be4e75668 | 476 | timer32_0_capture[i] = 0; |
| alexan_e | 1:0f1be4e75668 | 477 | } |
| alexan_e | 1:0f1be4e75668 | 478 | set_timer32_capture(timer_num, 0 ); |
| alexan_e | 1:0f1be4e75668 | 479 | /* Capture 0 on rising edge, interrupt enable. */ |
| alexan_e | 1:0f1be4e75668 | 480 | LPC_CT32B0->CCR = (0x5<<0)|(0x5<<3); |
| alexan_e | 1:0f1be4e75668 | 481 | #endif |
| alexan_e | 1:0f1be4e75668 | 482 | LPC_CT32B0->MCR = 3; /* Interrupt and Reset on MR0 */ |
| alexan_e | 1:0f1be4e75668 | 483 | |
| alexan_e | 1:0f1be4e75668 | 484 | /* Enable the TIMER0 Interrupt */ |
| alexan_e | 1:0f1be4e75668 | 485 | #if NMI_ENABLED |
| alexan_e | 1:0f1be4e75668 | 486 | NVIC_DisableIRQ( TIMER_32_0_IRQn ); |
| alexan_e | 1:0f1be4e75668 | 487 | NMI_Init( TIMER_32_0_IRQn ); |
| alexan_e | 1:0f1be4e75668 | 488 | #else |
| alexan_e | 1:0f1be4e75668 | 489 | NVIC_EnableIRQ(TIMER_32_0_IRQn); |
| alexan_e | 1:0f1be4e75668 | 490 | #endif |
| alexan_e | 1:0f1be4e75668 | 491 | } |
| alexan_e | 1:0f1be4e75668 | 492 | else if ( timer_num == 1 ) |
| alexan_e | 1:0f1be4e75668 | 493 | { |
| alexan_e | 1:0f1be4e75668 | 494 | /* Some of the I/O pins need to be clearfully planned if |
| alexan_e | 1:0f1be4e75668 | 495 | you use below module because JTAG and TIMER CAP/MAT pins are muxed. */ |
| alexan_e | 1:0f1be4e75668 | 496 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); |
| alexan_e | 1:0f1be4e75668 | 497 | |
| alexan_e | 1:0f1be4e75668 | 498 | LPC_CT32B1->MR0 = TimerInterval; |
| alexan_e | 1:0f1be4e75668 | 499 | #if TIMER_MATCH |
| alexan_e | 1:0f1be4e75668 | 500 | for ( i = 0; i < 4; i++ ) |
| alexan_e | 1:0f1be4e75668 | 501 | { |
| alexan_e | 1:0f1be4e75668 | 502 | timer32_1_counter[i] = 0; |
| alexan_e | 1:0f1be4e75668 | 503 | } |
| alexan_e | 1:0f1be4e75668 | 504 | set_timer32_match(timer_num, 0x0F, 0); |
| alexan_e | 1:0f1be4e75668 | 505 | LPC_CT32B1->EMR &= ~(0xFF<<4); |
| alexan_e | 1:0f1be4e75668 | 506 | LPC_CT32B1->EMR |= ((0x3<<4)|(0x3<<6)|(0x3<<8)|(0x3<<10)); /* MR0/1/2 Toggle */ |
| alexan_e | 1:0f1be4e75668 | 507 | #else |
| alexan_e | 1:0f1be4e75668 | 508 | for ( i = 0; i < 4; i++ ) |
| alexan_e | 1:0f1be4e75668 | 509 | { |
| alexan_e | 1:0f1be4e75668 | 510 | timer32_1_capture[i] = 0; |
| alexan_e | 1:0f1be4e75668 | 511 | } |
| alexan_e | 1:0f1be4e75668 | 512 | set_timer32_capture(timer_num, 0 ); |
| alexan_e | 1:0f1be4e75668 | 513 | /* Capture 0 on rising edge, interrupt enable. */ |
| alexan_e | 1:0f1be4e75668 | 514 | LPC_CT32B1->CCR = (0x5<<0)|(0x5<<3); |
| alexan_e | 1:0f1be4e75668 | 515 | #endif |
| alexan_e | 1:0f1be4e75668 | 516 | LPC_CT32B1->MCR = 3; /* Interrupt and Reset on MR0 */ |
| alexan_e | 1:0f1be4e75668 | 517 | |
| alexan_e | 1:0f1be4e75668 | 518 | /* Enable the TIMER1 Interrupt */ |
| alexan_e | 1:0f1be4e75668 | 519 | #if NMI_ENABLED |
| alexan_e | 1:0f1be4e75668 | 520 | NVIC_DisableIRQ( TIMER_32_1_IRQn ); |
| alexan_e | 1:0f1be4e75668 | 521 | NMI_Init( TIMER_32_1_IRQn ); |
| alexan_e | 1:0f1be4e75668 | 522 | #else |
| alexan_e | 1:0f1be4e75668 | 523 | NVIC_EnableIRQ(TIMER_32_1_IRQn); |
| alexan_e | 1:0f1be4e75668 | 524 | #endif |
| alexan_e | 1:0f1be4e75668 | 525 | } |
| alexan_e | 1:0f1be4e75668 | 526 | return; |
| alexan_e | 1:0f1be4e75668 | 527 | } |
| alexan_e | 1:0f1be4e75668 | 528 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 529 | ** Function name: init_timer32PWM |
| alexan_e | 1:0f1be4e75668 | 530 | ** |
| alexan_e | 1:0f1be4e75668 | 531 | ** Descriptions: Initialize timer as PWM |
| alexan_e | 1:0f1be4e75668 | 532 | ** |
| alexan_e | 1:0f1be4e75668 | 533 | ** parameters: timer number, period and match enable: |
| alexan_e | 1:0f1be4e75668 | 534 | ** match_enable[0] = PWM for MAT0 |
| alexan_e | 1:0f1be4e75668 | 535 | ** match_enable[1] = PWM for MAT1 |
| alexan_e | 1:0f1be4e75668 | 536 | ** match_enable[2] = PWM for MAT2 |
| alexan_e | 1:0f1be4e75668 | 537 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 538 | ** |
| alexan_e | 1:0f1be4e75668 | 539 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 540 | void init_timer32PWM(uint8_t timer_num, uint32_t period, uint8_t match_enable) |
| alexan_e | 1:0f1be4e75668 | 541 | { |
| alexan_e | 1:0f1be4e75668 | 542 | disable_timer32(timer_num); |
| alexan_e | 1:0f1be4e75668 | 543 | if (timer_num == 1) |
| alexan_e | 1:0f1be4e75668 | 544 | { |
| alexan_e | 1:0f1be4e75668 | 545 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); |
| alexan_e | 1:0f1be4e75668 | 546 | |
| alexan_e | 1:0f1be4e75668 | 547 | /* Setup the external match register */ |
| alexan_e | 1:0f1be4e75668 | 548 | LPC_CT32B1->EMR = (1<<EMC3)|(1<<EMC2)|(2<<EMC1)|(1<<EMC0)|MATCH3|(match_enable); |
| alexan_e | 1:0f1be4e75668 | 549 | |
| alexan_e | 1:0f1be4e75668 | 550 | /* Setup the outputs */ |
| alexan_e | 1:0f1be4e75668 | 551 | /* If match0 is enabled, set the output, use location 0 for test. */ |
| alexan_e | 1:0f1be4e75668 | 552 | set_timer32_match( timer_num, match_enable, 0 ); |
| alexan_e | 1:0f1be4e75668 | 553 | |
| alexan_e | 1:0f1be4e75668 | 554 | /* Enable the selected PWMs and enable Match3 */ |
| alexan_e | 1:0f1be4e75668 | 555 | LPC_CT32B1->PWMC = MATCH3|(match_enable); |
| alexan_e | 1:0f1be4e75668 | 556 | |
| alexan_e | 1:0f1be4e75668 | 557 | /* Setup the match registers */ |
| alexan_e | 1:0f1be4e75668 | 558 | /* set the period value to a global variable */ |
| alexan_e | 1:0f1be4e75668 | 559 | timer32_1_period = period; |
| alexan_e | 1:0f1be4e75668 | 560 | LPC_CT32B1->MR3 = timer32_1_period; |
| alexan_e | 1:0f1be4e75668 | 561 | LPC_CT32B1->MR0 = timer32_1_period/2; |
| alexan_e | 1:0f1be4e75668 | 562 | LPC_CT32B1->MR1 = timer32_1_period/2; |
| alexan_e | 1:0f1be4e75668 | 563 | LPC_CT32B1->MR2 = timer32_1_period/2; |
| alexan_e | 1:0f1be4e75668 | 564 | LPC_CT32B1->MCR = 1<<10; /* Reset on MR3 */ |
| alexan_e | 1:0f1be4e75668 | 565 | } |
| alexan_e | 1:0f1be4e75668 | 566 | else |
| alexan_e | 1:0f1be4e75668 | 567 | { |
| alexan_e | 1:0f1be4e75668 | 568 | /* Some of the I/O pins need to be clearfully planned if |
| alexan_e | 1:0f1be4e75668 | 569 | you use below module because JTAG and TIMER CAP/MAT pins are muxed. */ |
| alexan_e | 1:0f1be4e75668 | 570 | LPC_SYSCON->SYSAHBCLKCTRL |= (1<<9); |
| alexan_e | 1:0f1be4e75668 | 571 | |
| alexan_e | 1:0f1be4e75668 | 572 | /* Setup the external match register */ |
| alexan_e | 1:0f1be4e75668 | 573 | LPC_CT32B0->EMR = (1<<EMC3)|(2<<EMC2)|(1<<EMC1)|(1<<EMC0)|MATCH3|(match_enable); |
| alexan_e | 1:0f1be4e75668 | 574 | |
| alexan_e | 1:0f1be4e75668 | 575 | /* Setup the outputs */ |
| alexan_e | 1:0f1be4e75668 | 576 | /* If match0 is enabled, set the output, use location 0 for test. */ |
| alexan_e | 1:0f1be4e75668 | 577 | set_timer32_match( timer_num, match_enable, 0 ); |
| alexan_e | 1:0f1be4e75668 | 578 | |
| alexan_e | 1:0f1be4e75668 | 579 | /* Enable the selected PWMs and enable Match3 */ |
| alexan_e | 1:0f1be4e75668 | 580 | LPC_CT32B0->PWMC = MATCH3|(match_enable); |
| alexan_e | 1:0f1be4e75668 | 581 | |
| alexan_e | 1:0f1be4e75668 | 582 | /* Setup the match registers */ |
| alexan_e | 1:0f1be4e75668 | 583 | /* set the period value to a global variable */ |
| alexan_e | 1:0f1be4e75668 | 584 | timer32_0_period = period; |
| alexan_e | 1:0f1be4e75668 | 585 | LPC_CT32B0->MR3 = timer32_0_period; |
| alexan_e | 1:0f1be4e75668 | 586 | LPC_CT32B0->MR0 = timer32_0_period/2; |
| alexan_e | 1:0f1be4e75668 | 587 | LPC_CT32B0->MR1 = timer32_0_period/2; |
| alexan_e | 1:0f1be4e75668 | 588 | LPC_CT32B0->MR2 = timer32_0_period/2; |
| alexan_e | 1:0f1be4e75668 | 589 | LPC_CT32B0->MCR = 1<<10; /* Reset on MR3 */ |
| alexan_e | 1:0f1be4e75668 | 590 | } |
| alexan_e | 1:0f1be4e75668 | 591 | } |
| alexan_e | 1:0f1be4e75668 | 592 | |
| alexan_e | 1:0f1be4e75668 | 593 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 594 | ** Function name: pwm32_setMatch |
| alexan_e | 1:0f1be4e75668 | 595 | ** |
| alexan_e | 1:0f1be4e75668 | 596 | ** Descriptions: Set the pwm32 match values |
| alexan_e | 1:0f1be4e75668 | 597 | ** |
| alexan_e | 1:0f1be4e75668 | 598 | ** parameters: timer number, match numner and the value |
| alexan_e | 1:0f1be4e75668 | 599 | ** |
| alexan_e | 1:0f1be4e75668 | 600 | ** Returned value: None |
| alexan_e | 1:0f1be4e75668 | 601 | ** |
| alexan_e | 1:0f1be4e75668 | 602 | ******************************************************************************/ |
| alexan_e | 1:0f1be4e75668 | 603 | void setMatch_timer32PWM (uint8_t timer_num, uint8_t match_nr, uint32_t value) |
| alexan_e | 1:0f1be4e75668 | 604 | { |
| alexan_e | 1:0f1be4e75668 | 605 | if (timer_num) |
| alexan_e | 1:0f1be4e75668 | 606 | { |
| alexan_e | 1:0f1be4e75668 | 607 | switch (match_nr) |
| alexan_e | 1:0f1be4e75668 | 608 | { |
| alexan_e | 1:0f1be4e75668 | 609 | case 0: |
| alexan_e | 1:0f1be4e75668 | 610 | LPC_CT32B1->MR0 = value; |
| alexan_e | 1:0f1be4e75668 | 611 | break; |
| alexan_e | 1:0f1be4e75668 | 612 | case 1: |
| alexan_e | 1:0f1be4e75668 | 613 | LPC_CT32B1->MR1 = value; |
| alexan_e | 1:0f1be4e75668 | 614 | break; |
| alexan_e | 1:0f1be4e75668 | 615 | case 2: |
| alexan_e | 1:0f1be4e75668 | 616 | LPC_CT32B1->MR2 = value; |
| alexan_e | 1:0f1be4e75668 | 617 | break; |
| alexan_e | 1:0f1be4e75668 | 618 | case 3: |
| alexan_e | 1:0f1be4e75668 | 619 | LPC_CT32B1->MR3 = value; |
| alexan_e | 1:0f1be4e75668 | 620 | break; |
| alexan_e | 1:0f1be4e75668 | 621 | default: |
| alexan_e | 1:0f1be4e75668 | 622 | break; |
| alexan_e | 1:0f1be4e75668 | 623 | } |
| alexan_e | 1:0f1be4e75668 | 624 | } |
| alexan_e | 1:0f1be4e75668 | 625 | else |
| alexan_e | 1:0f1be4e75668 | 626 | { |
| alexan_e | 1:0f1be4e75668 | 627 | switch (match_nr) |
| alexan_e | 1:0f1be4e75668 | 628 | { |
| alexan_e | 1:0f1be4e75668 | 629 | case 0: |
| alexan_e | 1:0f1be4e75668 | 630 | LPC_CT32B0->MR0 = value; |
| alexan_e | 1:0f1be4e75668 | 631 | break; |
| alexan_e | 1:0f1be4e75668 | 632 | case 1: |
| alexan_e | 1:0f1be4e75668 | 633 | LPC_CT32B0->MR1 = value; |
| alexan_e | 1:0f1be4e75668 | 634 | break; |
| alexan_e | 1:0f1be4e75668 | 635 | case 2: |
| alexan_e | 1:0f1be4e75668 | 636 | LPC_CT32B0->MR2 = value; |
| alexan_e | 1:0f1be4e75668 | 637 | break; |
| alexan_e | 1:0f1be4e75668 | 638 | case 3: |
| alexan_e | 1:0f1be4e75668 | 639 | LPC_CT32B0->MR3 = value; |
| alexan_e | 1:0f1be4e75668 | 640 | break; |
| alexan_e | 1:0f1be4e75668 | 641 | default: |
| alexan_e | 1:0f1be4e75668 | 642 | break; |
| alexan_e | 1:0f1be4e75668 | 643 | } |
| alexan_e | 1:0f1be4e75668 | 644 | } |
| alexan_e | 1:0f1be4e75668 | 645 | } |
| alexan_e | 1:0f1be4e75668 | 646 | |
| alexan_e | 1:0f1be4e75668 | 647 | /****************************************************************************** |
| alexan_e | 1:0f1be4e75668 | 648 | ** End Of File |
| alexan_e | 1:0f1be4e75668 | 649 | ******************************************************************************/ |