Kevin Abraham / Mbed 2 deprecated EthernetPowerControl

EthernetPowerControl

Dependencies:   mbed

Fork of PowerControl by Michael Wei

PowerControl.h@1:8d381ef0ebcc, 2018-10-09 (annotated)

Committer:
abraha2d
Date:
Tue Oct 09 00:14:42 2018 +0000
Revision:
1:8d381ef0ebcc
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abraha2d 1:8d381ef0ebcc 1 /* mbed PowerControl Library
abraha2d 1:8d381ef0ebcc 2 * Copyright (c) 2010 Michael Wei
abraha2d 1:8d381ef0ebcc 3 */
abraha2d 1:8d381ef0ebcc 4
abraha2d 1:8d381ef0ebcc 5 #ifndef MBED_POWERCONTROL_H
abraha2d 1:8d381ef0ebcc 6 #define MBED_POWERCONTROL_H
abraha2d 1:8d381ef0ebcc 7
abraha2d 1:8d381ef0ebcc 8 //shouldn't have to include, but fixes weird problems with defines
abraha2d 1:8d381ef0ebcc 9 #include "LPC17xx.h"
abraha2d 1:8d381ef0ebcc 10
abraha2d 1:8d381ef0ebcc 11 //System Control Register
abraha2d 1:8d381ef0ebcc 12 // bit 0: Reserved
abraha2d 1:8d381ef0ebcc 13 // bit 1: Sleep on Exit
abraha2d 1:8d381ef0ebcc 14 #define LPC1768_SCR_SLEEPONEXIT 0x2
abraha2d 1:8d381ef0ebcc 15 // bit 2: Deep Sleep
abraha2d 1:8d381ef0ebcc 16 #define LPC1768_SCR_SLEEPDEEP 0x4
abraha2d 1:8d381ef0ebcc 17 // bit 3: Resereved
abraha2d 1:8d381ef0ebcc 18 // bit 4: Send on Pending
abraha2d 1:8d381ef0ebcc 19 #define LPC1768_SCR_SEVONPEND 0x10
abraha2d 1:8d381ef0ebcc 20 // bit 5-31: Reserved
abraha2d 1:8d381ef0ebcc 21
abraha2d 1:8d381ef0ebcc 22 //Power Control Register
abraha2d 1:8d381ef0ebcc 23 // bit 0: Power mode control bit 0 (power-down mode)
abraha2d 1:8d381ef0ebcc 24 #define LPC1768_PCON_PM0 0x1
abraha2d 1:8d381ef0ebcc 25 // bit 1: Power mode control bit 1 (deep power-down mode)
abraha2d 1:8d381ef0ebcc 26 #define LPC1768_PCON_PM1 0x2
abraha2d 1:8d381ef0ebcc 27 // bit 2: Brown-out reduced power mode
abraha2d 1:8d381ef0ebcc 28 #define LPC1768_PCON_BODRPM 0x4
abraha2d 1:8d381ef0ebcc 29 // bit 3: Brown-out global disable
abraha2d 1:8d381ef0ebcc 30 #define LPC1768_PCON_BOGD 0x8
abraha2d 1:8d381ef0ebcc 31 // bit 4: Brown-out reset disable
abraha2d 1:8d381ef0ebcc 32 #define LPC1768_PCON_BORD 0x10
abraha2d 1:8d381ef0ebcc 33 // bit 5-7 : Reserved
abraha2d 1:8d381ef0ebcc 34 // bit 8: Sleep Mode Entry Flag
abraha2d 1:8d381ef0ebcc 35 #define LPC1768_PCON_SMFLAG 0x100
abraha2d 1:8d381ef0ebcc 36 // bit 9: Deep Sleep Entry Flag
abraha2d 1:8d381ef0ebcc 37 #define LPC1768_PCON_DSFLAG 0x200
abraha2d 1:8d381ef0ebcc 38 // bit 10: Power Down Entry Flag
abraha2d 1:8d381ef0ebcc 39 #define LPC1768_PCON_PDFLAG 0x400
abraha2d 1:8d381ef0ebcc 40 // bit 11: Deep Power Down Entry Flag
abraha2d 1:8d381ef0ebcc 41 #define LPC1768_PCON_DPDFLAG 0x800
abraha2d 1:8d381ef0ebcc 42 // bit 12-31: Reserved
abraha2d 1:8d381ef0ebcc 43
abraha2d 1:8d381ef0ebcc 44 //"Sleep Mode" (WFI).
abraha2d 1:8d381ef0ebcc 45 inline void Sleep(void)
abraha2d 1:8d381ef0ebcc 46 {
abraha2d 1:8d381ef0ebcc 47 __WFI();
abraha2d 1:8d381ef0ebcc 48 }
abraha2d 1:8d381ef0ebcc 49
abraha2d 1:8d381ef0ebcc 50 //"Deep Sleep" Mode
abraha2d 1:8d381ef0ebcc 51 inline void DeepSleep(void)
abraha2d 1:8d381ef0ebcc 52 {
abraha2d 1:8d381ef0ebcc 53 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
abraha2d 1:8d381ef0ebcc 54 __WFI();
abraha2d 1:8d381ef0ebcc 55 }
abraha2d 1:8d381ef0ebcc 56
abraha2d 1:8d381ef0ebcc 57 //"Power-Down" Mode
abraha2d 1:8d381ef0ebcc 58 inline void PowerDown(void)
abraha2d 1:8d381ef0ebcc 59 {
abraha2d 1:8d381ef0ebcc 60 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
abraha2d 1:8d381ef0ebcc 61 LPC_SC->PCON &= ~LPC1768_PCON_PM1;
abraha2d 1:8d381ef0ebcc 62 LPC_SC->PCON |= LPC1768_PCON_PM0;
abraha2d 1:8d381ef0ebcc 63 __WFI();
abraha2d 1:8d381ef0ebcc 64 //reset back to normal
abraha2d 1:8d381ef0ebcc 65 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
abraha2d 1:8d381ef0ebcc 66 }
abraha2d 1:8d381ef0ebcc 67
abraha2d 1:8d381ef0ebcc 68 //"Deep Power-Down" Mode
abraha2d 1:8d381ef0ebcc 69 inline void DeepPowerDown(void)
abraha2d 1:8d381ef0ebcc 70 {
abraha2d 1:8d381ef0ebcc 71 SCB->SCR |= LPC1768_SCR_SLEEPDEEP;
abraha2d 1:8d381ef0ebcc 72 LPC_SC->PCON |= LPC1768_PCON_PM1 | LPC1768_PCON_PM0;
abraha2d 1:8d381ef0ebcc 73 __WFI();
abraha2d 1:8d381ef0ebcc 74 //reset back to normal
abraha2d 1:8d381ef0ebcc 75 LPC_SC->PCON &= ~(LPC1768_PCON_PM1 | LPC1768_PCON_PM0);
abraha2d 1:8d381ef0ebcc 76 }
abraha2d 1:8d381ef0ebcc 77
abraha2d 1:8d381ef0ebcc 78 //shut down BOD during power-down/deep sleep
abraha2d 1:8d381ef0ebcc 79 inline void BrownOut_ReducedPowerMode_Enable(void)
abraha2d 1:8d381ef0ebcc 80 {
abraha2d 1:8d381ef0ebcc 81 LPC_SC->PCON |= LPC1768_PCON_BODRPM;
abraha2d 1:8d381ef0ebcc 82 }
abraha2d 1:8d381ef0ebcc 83
abraha2d 1:8d381ef0ebcc 84 //turn on BOD during power-down/deep sleep
abraha2d 1:8d381ef0ebcc 85 inline void BrownOut_ReducedPowerMode_Disable(void)
abraha2d 1:8d381ef0ebcc 86 {
abraha2d 1:8d381ef0ebcc 87 LPC_SC->PCON &= ~LPC1768_PCON_BODRPM;
abraha2d 1:8d381ef0ebcc 88 }
abraha2d 1:8d381ef0ebcc 89
abraha2d 1:8d381ef0ebcc 90 //turn off brown out circutry
abraha2d 1:8d381ef0ebcc 91 inline void BrownOut_Global_Disable(void)
abraha2d 1:8d381ef0ebcc 92 {
abraha2d 1:8d381ef0ebcc 93 LPC_SC->PCON |= LPC1768_PCON_BOGD;
abraha2d 1:8d381ef0ebcc 94 }
abraha2d 1:8d381ef0ebcc 95
abraha2d 1:8d381ef0ebcc 96 //turn on brown out circutry
abraha2d 1:8d381ef0ebcc 97 inline void BrownOut_Global_Enable(void)
abraha2d 1:8d381ef0ebcc 98 {
abraha2d 1:8d381ef0ebcc 99 LPC_SC->PCON &= !LPC1768_PCON_BOGD;
abraha2d 1:8d381ef0ebcc 100 }
abraha2d 1:8d381ef0ebcc 101
abraha2d 1:8d381ef0ebcc 102 //turn off brown out reset circutry
abraha2d 1:8d381ef0ebcc 103 inline void BrownOut_Reset_Disable(void)
abraha2d 1:8d381ef0ebcc 104 {
abraha2d 1:8d381ef0ebcc 105 LPC_SC->PCON |= LPC1768_PCON_BORD;
abraha2d 1:8d381ef0ebcc 106 }
abraha2d 1:8d381ef0ebcc 107
abraha2d 1:8d381ef0ebcc 108 //turn on brown outreset circutry
abraha2d 1:8d381ef0ebcc 109 inline void BrownOut_Reset_Enable(void)
abraha2d 1:8d381ef0ebcc 110 {
abraha2d 1:8d381ef0ebcc 111 LPC_SC->PCON &= ~LPC1768_PCON_BORD;
abraha2d 1:8d381ef0ebcc 112 }
abraha2d 1:8d381ef0ebcc 113 //Peripheral Control Register
abraha2d 1:8d381ef0ebcc 114 // bit 0: Reserved
abraha2d 1:8d381ef0ebcc 115 // bit 1: PCTIM0: Timer/Counter 0 power/clock enable
abraha2d 1:8d381ef0ebcc 116 #define LPC1768_PCONP_PCTIM0 0x2
abraha2d 1:8d381ef0ebcc 117 // bit 2: PCTIM1: Timer/Counter 1 power/clock enable
abraha2d 1:8d381ef0ebcc 118 #define LPC1768_PCONP_PCTIM1 0x4
abraha2d 1:8d381ef0ebcc 119 // bit 3: PCUART0: UART 0 power/clock enable
abraha2d 1:8d381ef0ebcc 120 #define LPC1768_PCONP_PCUART0 0x8
abraha2d 1:8d381ef0ebcc 121 // bit 4: PCUART1: UART 1 power/clock enable
abraha2d 1:8d381ef0ebcc 122 #define LPC1768_PCONP_PCUART1 0x10
abraha2d 1:8d381ef0ebcc 123 // bit 5: Reserved
abraha2d 1:8d381ef0ebcc 124 // bit 6: PCPWM1: PWM 1 power/clock enable
abraha2d 1:8d381ef0ebcc 125 #define LPC1768_PCONP_PCPWM1 0x40
abraha2d 1:8d381ef0ebcc 126 // bit 7: PCI2C0: I2C interface 0 power/clock enable
abraha2d 1:8d381ef0ebcc 127 #define LPC1768_PCONP_PCI2C0 0x80
abraha2d 1:8d381ef0ebcc 128 // bit 8: PCSPI: SPI interface power/clock enable
abraha2d 1:8d381ef0ebcc 129 #define LPC1768_PCONP_PCSPI 0x100
abraha2d 1:8d381ef0ebcc 130 // bit 9: PCRTC: RTC power/clock enable
abraha2d 1:8d381ef0ebcc 131 #define LPC1768_PCONP_PCRTC 0x200
abraha2d 1:8d381ef0ebcc 132 // bit 10: PCSSP1: SSP interface 1 power/clock enable
abraha2d 1:8d381ef0ebcc 133 #define LPC1768_PCONP_PCSSP1 0x400
abraha2d 1:8d381ef0ebcc 134 // bit 11: Reserved
abraha2d 1:8d381ef0ebcc 135 // bit 12: PCADC: A/D converter power/clock enable
abraha2d 1:8d381ef0ebcc 136 #define LPC1768_PCONP_PCADC 0x1000
abraha2d 1:8d381ef0ebcc 137 // bit 13: PCCAN1: CAN controller 1 power/clock enable
abraha2d 1:8d381ef0ebcc 138 #define LPC1768_PCONP_PCCAN1 0x2000
abraha2d 1:8d381ef0ebcc 139 // bit 14: PCCAN2: CAN controller 2 power/clock enable
abraha2d 1:8d381ef0ebcc 140 #define LPC1768_PCONP_PCCAN2 0x4000
abraha2d 1:8d381ef0ebcc 141 // bit 15: PCGPIO: GPIOs power/clock enable
abraha2d 1:8d381ef0ebcc 142 #define LPC1768_PCONP_PCGPIO 0x8000
abraha2d 1:8d381ef0ebcc 143 // bit 16: PCRIT: Repetitive interrupt timer power/clock enable
abraha2d 1:8d381ef0ebcc 144 #define LPC1768_PCONP_PCRIT 0x10000
abraha2d 1:8d381ef0ebcc 145 // bit 17: PCMCPWM: Motor control PWM power/clock enable
abraha2d 1:8d381ef0ebcc 146 #define LPC1768_PCONP_PCMCPWM 0x20000
abraha2d 1:8d381ef0ebcc 147 // bit 18: PCQEI: Quadrature encoder interface power/clock enable
abraha2d 1:8d381ef0ebcc 148 #define LPC1768_PCONP_PCQEI 0x40000
abraha2d 1:8d381ef0ebcc 149 // bit 19: PCI2C1: I2C interface 1 power/clock enable
abraha2d 1:8d381ef0ebcc 150 #define LPC1768_PCONP_PCI2C1 0x80000
abraha2d 1:8d381ef0ebcc 151 // bit 20: Reserved
abraha2d 1:8d381ef0ebcc 152 // bit 21: PCSSP0: SSP interface 0 power/clock enable
abraha2d 1:8d381ef0ebcc 153 #define LPC1768_PCONP_PCSSP0 0x200000
abraha2d 1:8d381ef0ebcc 154 // bit 22: PCTIM2: Timer 2 power/clock enable
abraha2d 1:8d381ef0ebcc 155 #define LPC1768_PCONP_PCTIM2 0x400000
abraha2d 1:8d381ef0ebcc 156 // bit 23: PCTIM3: Timer 3 power/clock enable
abraha2d 1:8d381ef0ebcc 157 #define LPC1768_PCONP_PCQTIM3 0x800000
abraha2d 1:8d381ef0ebcc 158 // bit 24: PCUART2: UART 2 power/clock enable
abraha2d 1:8d381ef0ebcc 159 #define LPC1768_PCONP_PCUART2 0x1000000
abraha2d 1:8d381ef0ebcc 160 // bit 25: PCUART3: UART 3 power/clock enable
abraha2d 1:8d381ef0ebcc 161 #define LPC1768_PCONP_PCUART3 0x2000000
abraha2d 1:8d381ef0ebcc 162 // bit 26: PCI2C2: I2C interface 2 power/clock enable
abraha2d 1:8d381ef0ebcc 163 #define LPC1768_PCONP_PCI2C2 0x4000000
abraha2d 1:8d381ef0ebcc 164 // bit 27: PCI2S: I2S interface power/clock enable
abraha2d 1:8d381ef0ebcc 165 #define LPC1768_PCONP_PCI2S 0x8000000
abraha2d 1:8d381ef0ebcc 166 // bit 28: Reserved
abraha2d 1:8d381ef0ebcc 167 // bit 29: PCGPDMA: GP DMA function power/clock enable
abraha2d 1:8d381ef0ebcc 168 #define LPC1768_PCONP_PCGPDMA 0x20000000
abraha2d 1:8d381ef0ebcc 169 // bit 30: PCENET: Ethernet block power/clock enable
abraha2d 1:8d381ef0ebcc 170 #define LPC1768_PCONP_PCENET 0x40000000
abraha2d 1:8d381ef0ebcc 171 // bit 31: PCUSB: USB interface power/clock enable
abraha2d 1:8d381ef0ebcc 172 #define LPC1768_PCONP_PCUSB 0x80000000
abraha2d 1:8d381ef0ebcc 173
abraha2d 1:8d381ef0ebcc 174 //Powers Up specified Peripheral(s)
abraha2d 1:8d381ef0ebcc 175 inline unsigned int Peripheral_PowerUp(unsigned int bitMask)
abraha2d 1:8d381ef0ebcc 176 {
abraha2d 1:8d381ef0ebcc 177 return LPC_SC->PCONP |= bitMask;
abraha2d 1:8d381ef0ebcc 178 }
abraha2d 1:8d381ef0ebcc 179
abraha2d 1:8d381ef0ebcc 180 //Powers Down specified Peripheral(s)
abraha2d 1:8d381ef0ebcc 181 inline unsigned int Peripheral_PowerDown(unsigned int bitMask)
abraha2d 1:8d381ef0ebcc 182 {
abraha2d 1:8d381ef0ebcc 183 return LPC_SC->PCONP &= ~bitMask;
abraha2d 1:8d381ef0ebcc 184 }
abraha2d 1:8d381ef0ebcc 185
abraha2d 1:8d381ef0ebcc 186 //returns if the peripheral is on or off
abraha2d 1:8d381ef0ebcc 187 inline bool Peripheral_GetStatus(unsigned int peripheral)
abraha2d 1:8d381ef0ebcc 188 {
abraha2d 1:8d381ef0ebcc 189 return (LPC_SC->PCONP & peripheral) ? true : false;
abraha2d 1:8d381ef0ebcc 190 }
abraha2d 1:8d381ef0ebcc 191
abraha2d 1:8d381ef0ebcc 192 #endif