Taouil Yassine
/
nrf52-sdk
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nrf52_bitfields.h
00001 /* Copyright (c) 2015, Nordic Semiconductor ASA 00002 * All rights reserved. 00003 * 00004 * Redistribution and use in source and binary forms, with or without 00005 * modification, are permitted provided that the following conditions are met: 00006 * 00007 * * Redistributions of source code must retain the above copyright notice, this 00008 * list of conditions and the following disclaimer. 00009 * 00010 * * Redistributions in binary form must reproduce the above copyright notice, 00011 * this list of conditions and the following disclaimer in the documentation 00012 * and/or other materials provided with the distribution. 00013 * 00014 * * Neither the name of Nordic Semiconductor ASA nor the names of its 00015 * contributors may be used to endorse or promote products derived from 00016 * this software without specific prior written permission. 00017 * 00018 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00019 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00020 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00021 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00022 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00023 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00024 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00025 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00026 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00027 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00028 * 00029 */ 00030 #ifndef __NRF52_BITS_H 00031 #define __NRF52_BITS_H 00032 00033 /*lint ++flb "Enter library region" */ 00034 00035 /* Peripheral: AAR */ 00036 /* Description: Accelerated Address Resolver */ 00037 00038 /* Register: AAR_INTENSET */ 00039 /* Description: Enable interrupt */ 00040 00041 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */ 00042 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 00043 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 00044 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 00045 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 00046 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */ 00047 00048 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */ 00049 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 00050 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 00051 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 00052 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 00053 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */ 00054 00055 /* Bit 0 : Write '1' to Enable interrupt for END event */ 00056 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 00057 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ 00058 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 00059 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 00060 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */ 00061 00062 /* Register: AAR_INTENCLR */ 00063 /* Description: Disable interrupt */ 00064 00065 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */ 00066 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 00067 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 00068 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */ 00069 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */ 00070 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */ 00071 00072 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */ 00073 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 00074 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 00075 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */ 00076 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */ 00077 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */ 00078 00079 /* Bit 0 : Write '1' to Disable interrupt for END event */ 00080 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 00081 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 00082 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 00083 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 00084 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */ 00085 00086 /* Register: AAR_STATUS */ 00087 /* Description: Resolution status */ 00088 00089 /* Bits 3..0 : The IRK that was used last time an address was resolved */ 00090 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 00091 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 00092 00093 /* Register: AAR_ENABLE */ 00094 /* Description: Enable AAR */ 00095 00096 /* Bits 1..0 : Enable or disable AAR */ 00097 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 00098 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 00099 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 00100 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */ 00101 00102 /* Register: AAR_NIRK */ 00103 /* Description: Number of IRKs */ 00104 00105 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */ 00106 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ 00107 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ 00108 00109 /* Register: AAR_IRKPTR */ 00110 /* Description: Pointer to IRK data structure */ 00111 00112 /* Bits 31..0 : Pointer to the IRK data structure */ 00113 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */ 00114 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */ 00115 00116 /* Register: AAR_ADDRPTR */ 00117 /* Description: Pointer to the resolvable address */ 00118 00119 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */ 00120 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */ 00121 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */ 00122 00123 /* Register: AAR_SCRATCHPTR */ 00124 /* Description: Pointer to data area used for temporary storage */ 00125 00126 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */ 00127 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 00128 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 00129 00130 00131 /* Peripheral: AMLI */ 00132 /* Description: AHB Multi-Layer Interface */ 00133 00134 /* Register: AMLI_RAMPRI_CPU0 */ 00135 /* Description: AHB bus master priority register for CPU0 */ 00136 00137 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 00138 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00139 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00140 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */ 00141 #define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */ 00142 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */ 00143 #define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */ 00144 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */ 00145 #define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */ 00146 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */ 00147 #define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */ 00148 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */ 00149 #define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */ 00150 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */ 00151 #define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */ 00152 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */ 00153 #define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */ 00154 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */ 00155 #define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */ 00156 00157 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 00158 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00159 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00160 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */ 00161 #define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */ 00162 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */ 00163 #define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */ 00164 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */ 00165 #define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */ 00166 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */ 00167 #define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */ 00168 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */ 00169 #define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */ 00170 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */ 00171 #define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */ 00172 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */ 00173 #define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */ 00174 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */ 00175 #define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */ 00176 00177 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 00178 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00179 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00180 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */ 00181 #define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */ 00182 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */ 00183 #define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */ 00184 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */ 00185 #define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */ 00186 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */ 00187 #define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */ 00188 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */ 00189 #define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */ 00190 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */ 00191 #define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */ 00192 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */ 00193 #define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */ 00194 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */ 00195 #define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */ 00196 00197 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 00198 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00199 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00200 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */ 00201 #define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */ 00202 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */ 00203 #define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */ 00204 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */ 00205 #define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */ 00206 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */ 00207 #define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */ 00208 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */ 00209 #define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */ 00210 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */ 00211 #define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */ 00212 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */ 00213 #define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */ 00214 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */ 00215 #define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */ 00216 00217 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 00218 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00219 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00220 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */ 00221 #define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */ 00222 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */ 00223 #define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */ 00224 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */ 00225 #define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */ 00226 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */ 00227 #define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */ 00228 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */ 00229 #define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */ 00230 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */ 00231 #define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */ 00232 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */ 00233 #define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */ 00234 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */ 00235 #define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */ 00236 00237 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 00238 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00239 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00240 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */ 00241 #define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */ 00242 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */ 00243 #define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */ 00244 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */ 00245 #define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */ 00246 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */ 00247 #define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */ 00248 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */ 00249 #define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */ 00250 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */ 00251 #define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */ 00252 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */ 00253 #define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */ 00254 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */ 00255 #define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */ 00256 00257 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 00258 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00259 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00260 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */ 00261 #define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */ 00262 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */ 00263 #define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */ 00264 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */ 00265 #define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */ 00266 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */ 00267 #define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */ 00268 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */ 00269 #define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */ 00270 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */ 00271 #define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */ 00272 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */ 00273 #define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */ 00274 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */ 00275 #define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */ 00276 00277 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 00278 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00279 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00280 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */ 00281 #define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */ 00282 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */ 00283 #define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */ 00284 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */ 00285 #define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */ 00286 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */ 00287 #define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */ 00288 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */ 00289 #define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */ 00290 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */ 00291 #define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */ 00292 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */ 00293 #define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */ 00294 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */ 00295 #define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */ 00296 00297 /* Register: AMLI_RAMPRI_SPIS1 */ 00298 /* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */ 00299 00300 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 00301 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00302 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00303 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */ 00304 #define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */ 00305 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */ 00306 #define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */ 00307 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */ 00308 #define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */ 00309 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */ 00310 #define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */ 00311 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */ 00312 #define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */ 00313 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */ 00314 #define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */ 00315 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */ 00316 #define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */ 00317 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */ 00318 #define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */ 00319 00320 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 00321 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00322 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00323 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */ 00324 #define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */ 00325 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */ 00326 #define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */ 00327 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */ 00328 #define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */ 00329 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */ 00330 #define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */ 00331 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */ 00332 #define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */ 00333 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */ 00334 #define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */ 00335 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */ 00336 #define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */ 00337 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */ 00338 #define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */ 00339 00340 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 00341 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00342 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00343 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */ 00344 #define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */ 00345 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */ 00346 #define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */ 00347 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */ 00348 #define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */ 00349 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */ 00350 #define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */ 00351 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */ 00352 #define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */ 00353 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */ 00354 #define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */ 00355 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */ 00356 #define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */ 00357 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */ 00358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */ 00359 00360 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 00361 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00362 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00363 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */ 00364 #define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */ 00365 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */ 00366 #define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */ 00367 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */ 00368 #define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */ 00369 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */ 00370 #define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */ 00371 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */ 00372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */ 00373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */ 00374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */ 00375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */ 00376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */ 00377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */ 00378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */ 00379 00380 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 00381 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00382 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00383 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */ 00384 #define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */ 00385 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */ 00386 #define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */ 00387 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */ 00388 #define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */ 00389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */ 00390 #define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */ 00391 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */ 00392 #define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */ 00393 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */ 00394 #define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */ 00395 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */ 00396 #define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */ 00397 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */ 00398 #define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */ 00399 00400 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 00401 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00402 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00403 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */ 00404 #define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */ 00405 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */ 00406 #define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */ 00407 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */ 00408 #define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */ 00409 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */ 00410 #define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */ 00411 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */ 00412 #define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */ 00413 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */ 00414 #define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */ 00415 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */ 00416 #define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */ 00417 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */ 00418 #define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */ 00419 00420 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 00421 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00422 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00423 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */ 00424 #define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */ 00425 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */ 00426 #define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */ 00427 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */ 00428 #define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */ 00429 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */ 00430 #define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */ 00431 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */ 00432 #define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */ 00433 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */ 00434 #define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */ 00435 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */ 00436 #define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */ 00437 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */ 00438 #define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */ 00439 00440 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 00441 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00442 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00443 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */ 00444 #define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */ 00445 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */ 00446 #define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */ 00447 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */ 00448 #define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */ 00449 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */ 00450 #define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */ 00451 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */ 00452 #define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */ 00453 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */ 00454 #define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */ 00455 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */ 00456 #define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */ 00457 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */ 00458 #define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */ 00459 00460 /* Register: AMLI_RAMPRI_RADIO */ 00461 /* Description: AHB bus master priority register for RADIO */ 00462 00463 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 00464 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00465 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00466 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */ 00467 #define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */ 00468 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */ 00469 #define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */ 00470 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */ 00471 #define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */ 00472 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */ 00473 #define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */ 00474 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */ 00475 #define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */ 00476 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */ 00477 #define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */ 00478 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */ 00479 #define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */ 00480 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */ 00481 #define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */ 00482 00483 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 00484 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00485 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00486 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */ 00487 #define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */ 00488 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */ 00489 #define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */ 00490 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */ 00491 #define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */ 00492 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */ 00493 #define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */ 00494 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */ 00495 #define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */ 00496 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */ 00497 #define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */ 00498 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */ 00499 #define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */ 00500 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */ 00501 #define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */ 00502 00503 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 00504 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00505 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00506 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */ 00507 #define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */ 00508 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */ 00509 #define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */ 00510 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */ 00511 #define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */ 00512 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */ 00513 #define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */ 00514 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */ 00515 #define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */ 00516 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */ 00517 #define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */ 00518 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */ 00519 #define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */ 00520 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */ 00521 #define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */ 00522 00523 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 00524 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00525 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00526 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */ 00527 #define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */ 00528 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */ 00529 #define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */ 00530 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */ 00531 #define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */ 00532 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */ 00533 #define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */ 00534 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */ 00535 #define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */ 00536 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */ 00537 #define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */ 00538 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */ 00539 #define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */ 00540 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */ 00541 #define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */ 00542 00543 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 00544 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00545 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00546 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */ 00547 #define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */ 00548 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */ 00549 #define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */ 00550 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */ 00551 #define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */ 00552 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */ 00553 #define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */ 00554 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */ 00555 #define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */ 00556 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */ 00557 #define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */ 00558 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */ 00559 #define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */ 00560 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */ 00561 #define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */ 00562 00563 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 00564 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00565 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00566 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */ 00567 #define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */ 00568 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */ 00569 #define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */ 00570 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */ 00571 #define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */ 00572 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */ 00573 #define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */ 00574 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */ 00575 #define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */ 00576 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */ 00577 #define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */ 00578 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */ 00579 #define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */ 00580 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */ 00581 #define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */ 00582 00583 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 00584 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00585 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00586 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */ 00587 #define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */ 00588 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */ 00589 #define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */ 00590 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */ 00591 #define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */ 00592 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */ 00593 #define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */ 00594 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */ 00595 #define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */ 00596 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */ 00597 #define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */ 00598 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */ 00599 #define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */ 00600 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */ 00601 #define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */ 00602 00603 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 00604 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00605 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00606 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */ 00607 #define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */ 00608 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */ 00609 #define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */ 00610 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */ 00611 #define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */ 00612 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */ 00613 #define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */ 00614 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */ 00615 #define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */ 00616 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */ 00617 #define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */ 00618 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */ 00619 #define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */ 00620 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */ 00621 #define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */ 00622 00623 /* Register: AMLI_RAMPRI_ECB */ 00624 /* Description: AHB bus master priority register for ECB */ 00625 00626 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 00627 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00628 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00629 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */ 00630 #define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */ 00631 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */ 00632 #define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */ 00633 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */ 00634 #define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */ 00635 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */ 00636 #define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */ 00637 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */ 00638 #define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */ 00639 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */ 00640 #define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */ 00641 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */ 00642 #define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */ 00643 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */ 00644 #define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */ 00645 00646 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 00647 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00648 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00649 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */ 00650 #define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */ 00651 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */ 00652 #define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */ 00653 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */ 00654 #define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */ 00655 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */ 00656 #define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */ 00657 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */ 00658 #define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */ 00659 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */ 00660 #define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */ 00661 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */ 00662 #define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */ 00663 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */ 00664 #define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */ 00665 00666 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 00667 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00668 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00669 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */ 00670 #define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */ 00671 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */ 00672 #define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */ 00673 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */ 00674 #define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */ 00675 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */ 00676 #define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */ 00677 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */ 00678 #define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */ 00679 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */ 00680 #define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */ 00681 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */ 00682 #define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */ 00683 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */ 00684 #define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */ 00685 00686 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 00687 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00688 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00689 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */ 00690 #define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */ 00691 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */ 00692 #define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */ 00693 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */ 00694 #define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */ 00695 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */ 00696 #define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */ 00697 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */ 00698 #define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */ 00699 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */ 00700 #define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */ 00701 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */ 00702 #define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */ 00703 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */ 00704 #define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */ 00705 00706 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 00707 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00708 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00709 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */ 00710 #define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */ 00711 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */ 00712 #define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */ 00713 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */ 00714 #define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */ 00715 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */ 00716 #define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */ 00717 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */ 00718 #define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */ 00719 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */ 00720 #define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */ 00721 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */ 00722 #define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */ 00723 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */ 00724 #define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */ 00725 00726 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 00727 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00728 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00729 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */ 00730 #define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */ 00731 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */ 00732 #define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */ 00733 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */ 00734 #define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */ 00735 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */ 00736 #define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */ 00737 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */ 00738 #define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */ 00739 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */ 00740 #define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */ 00741 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */ 00742 #define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */ 00743 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */ 00744 #define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */ 00745 00746 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 00747 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00748 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00749 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */ 00750 #define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */ 00751 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */ 00752 #define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */ 00753 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */ 00754 #define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */ 00755 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */ 00756 #define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */ 00757 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */ 00758 #define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */ 00759 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */ 00760 #define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */ 00761 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */ 00762 #define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */ 00763 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */ 00764 #define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */ 00765 00766 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 00767 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00768 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00769 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */ 00770 #define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */ 00771 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */ 00772 #define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */ 00773 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */ 00774 #define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */ 00775 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */ 00776 #define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */ 00777 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */ 00778 #define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */ 00779 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */ 00780 #define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */ 00781 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */ 00782 #define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */ 00783 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */ 00784 #define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */ 00785 00786 /* Register: AMLI_RAMPRI_CCM */ 00787 /* Description: AHB bus master priority register for CCM */ 00788 00789 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 00790 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00791 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00792 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */ 00793 #define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */ 00794 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */ 00795 #define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */ 00796 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */ 00797 #define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */ 00798 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */ 00799 #define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */ 00800 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */ 00801 #define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */ 00802 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */ 00803 #define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */ 00804 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */ 00805 #define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */ 00806 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */ 00807 #define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */ 00808 00809 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 00810 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00811 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00812 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */ 00813 #define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */ 00814 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */ 00815 #define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */ 00816 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */ 00817 #define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */ 00818 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */ 00819 #define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */ 00820 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */ 00821 #define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */ 00822 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */ 00823 #define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */ 00824 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */ 00825 #define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */ 00826 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */ 00827 #define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */ 00828 00829 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 00830 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00831 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00832 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */ 00833 #define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */ 00834 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */ 00835 #define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */ 00836 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */ 00837 #define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */ 00838 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */ 00839 #define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */ 00840 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */ 00841 #define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */ 00842 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */ 00843 #define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */ 00844 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */ 00845 #define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */ 00846 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */ 00847 #define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */ 00848 00849 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 00850 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 00851 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 00852 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */ 00853 #define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */ 00854 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */ 00855 #define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */ 00856 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */ 00857 #define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */ 00858 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */ 00859 #define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */ 00860 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */ 00861 #define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */ 00862 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */ 00863 #define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */ 00864 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */ 00865 #define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */ 00866 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */ 00867 #define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */ 00868 00869 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 00870 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 00871 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 00872 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */ 00873 #define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */ 00874 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */ 00875 #define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */ 00876 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */ 00877 #define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */ 00878 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */ 00879 #define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */ 00880 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */ 00881 #define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */ 00882 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */ 00883 #define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */ 00884 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */ 00885 #define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */ 00886 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */ 00887 #define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */ 00888 00889 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 00890 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 00891 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 00892 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */ 00893 #define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */ 00894 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */ 00895 #define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */ 00896 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */ 00897 #define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */ 00898 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */ 00899 #define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */ 00900 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */ 00901 #define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */ 00902 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */ 00903 #define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */ 00904 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */ 00905 #define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */ 00906 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */ 00907 #define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */ 00908 00909 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 00910 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 00911 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 00912 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */ 00913 #define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */ 00914 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */ 00915 #define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */ 00916 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */ 00917 #define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */ 00918 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */ 00919 #define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */ 00920 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */ 00921 #define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */ 00922 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */ 00923 #define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */ 00924 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */ 00925 #define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */ 00926 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */ 00927 #define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */ 00928 00929 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 00930 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 00931 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 00932 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */ 00933 #define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */ 00934 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */ 00935 #define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */ 00936 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */ 00937 #define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */ 00938 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */ 00939 #define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */ 00940 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */ 00941 #define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */ 00942 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */ 00943 #define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */ 00944 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */ 00945 #define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */ 00946 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */ 00947 #define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */ 00948 00949 /* Register: AMLI_RAMPRI_AAR */ 00950 /* Description: AHB bus master priority register for AAR */ 00951 00952 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 00953 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 00954 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 00955 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */ 00956 #define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */ 00957 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */ 00958 #define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */ 00959 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */ 00960 #define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */ 00961 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */ 00962 #define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */ 00963 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */ 00964 #define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */ 00965 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */ 00966 #define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */ 00967 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */ 00968 #define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */ 00969 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */ 00970 #define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */ 00971 00972 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 00973 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 00974 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 00975 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */ 00976 #define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */ 00977 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */ 00978 #define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */ 00979 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */ 00980 #define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */ 00981 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */ 00982 #define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */ 00983 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */ 00984 #define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */ 00985 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */ 00986 #define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */ 00987 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */ 00988 #define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */ 00989 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */ 00990 #define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */ 00991 00992 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 00993 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 00994 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 00995 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */ 00996 #define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */ 00997 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */ 00998 #define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */ 00999 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */ 01000 #define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */ 01001 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */ 01002 #define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */ 01003 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */ 01004 #define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */ 01005 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */ 01006 #define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */ 01007 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */ 01008 #define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */ 01009 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */ 01010 #define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */ 01011 01012 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 01013 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 01014 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 01015 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */ 01016 #define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */ 01017 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */ 01018 #define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */ 01019 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */ 01020 #define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */ 01021 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */ 01022 #define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */ 01023 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */ 01024 #define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */ 01025 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */ 01026 #define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */ 01027 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */ 01028 #define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */ 01029 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */ 01030 #define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */ 01031 01032 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 01033 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 01034 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 01035 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */ 01036 #define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */ 01037 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */ 01038 #define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */ 01039 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */ 01040 #define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */ 01041 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */ 01042 #define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */ 01043 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */ 01044 #define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */ 01045 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */ 01046 #define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */ 01047 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */ 01048 #define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */ 01049 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */ 01050 #define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */ 01051 01052 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 01053 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 01054 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 01055 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */ 01056 #define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */ 01057 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */ 01058 #define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */ 01059 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */ 01060 #define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */ 01061 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */ 01062 #define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */ 01063 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */ 01064 #define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */ 01065 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */ 01066 #define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */ 01067 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */ 01068 #define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */ 01069 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */ 01070 #define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */ 01071 01072 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 01073 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 01074 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 01075 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */ 01076 #define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */ 01077 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */ 01078 #define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */ 01079 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */ 01080 #define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */ 01081 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */ 01082 #define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */ 01083 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */ 01084 #define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */ 01085 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */ 01086 #define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */ 01087 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */ 01088 #define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */ 01089 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */ 01090 #define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */ 01091 01092 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 01093 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 01094 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 01095 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */ 01096 #define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */ 01097 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */ 01098 #define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */ 01099 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */ 01100 #define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */ 01101 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */ 01102 #define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */ 01103 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */ 01104 #define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */ 01105 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */ 01106 #define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */ 01107 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */ 01108 #define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */ 01109 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */ 01110 #define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */ 01111 01112 /* Register: AMLI_RAMPRI_SAADC */ 01113 /* Description: AHB bus master priority register for SAADC */ 01114 01115 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 01116 #define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 01117 #define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 01118 #define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */ 01119 #define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */ 01120 #define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */ 01121 #define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */ 01122 #define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */ 01123 #define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */ 01124 #define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */ 01125 #define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */ 01126 #define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */ 01127 #define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */ 01128 #define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */ 01129 #define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */ 01130 #define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */ 01131 #define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */ 01132 #define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */ 01133 #define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */ 01134 01135 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 01136 #define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 01137 #define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 01138 #define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */ 01139 #define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */ 01140 #define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */ 01141 #define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */ 01142 #define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */ 01143 #define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */ 01144 #define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */ 01145 #define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */ 01146 #define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */ 01147 #define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */ 01148 #define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */ 01149 #define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */ 01150 #define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */ 01151 #define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */ 01152 #define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */ 01153 #define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */ 01154 01155 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 01156 #define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 01157 #define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 01158 #define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */ 01159 #define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */ 01160 #define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */ 01161 #define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */ 01162 #define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */ 01163 #define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */ 01164 #define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */ 01165 #define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */ 01166 #define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */ 01167 #define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */ 01168 #define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */ 01169 #define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */ 01170 #define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */ 01171 #define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */ 01172 #define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */ 01173 #define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */ 01174 01175 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 01176 #define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 01177 #define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 01178 #define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */ 01179 #define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */ 01180 #define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */ 01181 #define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */ 01182 #define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */ 01183 #define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */ 01184 #define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */ 01185 #define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */ 01186 #define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */ 01187 #define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */ 01188 #define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */ 01189 #define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */ 01190 #define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */ 01191 #define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */ 01192 #define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */ 01193 #define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */ 01194 01195 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 01196 #define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 01197 #define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 01198 #define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */ 01199 #define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */ 01200 #define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */ 01201 #define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */ 01202 #define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */ 01203 #define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */ 01204 #define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */ 01205 #define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */ 01206 #define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */ 01207 #define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */ 01208 #define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */ 01209 #define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */ 01210 #define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */ 01211 #define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */ 01212 #define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */ 01213 #define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */ 01214 01215 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 01216 #define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 01217 #define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 01218 #define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */ 01219 #define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */ 01220 #define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */ 01221 #define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */ 01222 #define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */ 01223 #define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */ 01224 #define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */ 01225 #define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */ 01226 #define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */ 01227 #define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */ 01228 #define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */ 01229 #define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */ 01230 #define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */ 01231 #define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */ 01232 #define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */ 01233 #define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */ 01234 01235 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 01236 #define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 01237 #define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 01238 #define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */ 01239 #define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */ 01240 #define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */ 01241 #define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */ 01242 #define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */ 01243 #define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */ 01244 #define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */ 01245 #define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */ 01246 #define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */ 01247 #define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */ 01248 #define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */ 01249 #define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */ 01250 #define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */ 01251 #define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */ 01252 #define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */ 01253 #define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */ 01254 01255 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 01256 #define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 01257 #define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 01258 #define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */ 01259 #define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */ 01260 #define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */ 01261 #define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */ 01262 #define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */ 01263 #define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */ 01264 #define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */ 01265 #define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */ 01266 #define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */ 01267 #define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */ 01268 #define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */ 01269 #define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */ 01270 #define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */ 01271 #define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */ 01272 #define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */ 01273 #define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */ 01274 01275 /* Register: AMLI_RAMPRI_UARTE */ 01276 /* Description: AHB bus master priority register for UARTE */ 01277 01278 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 01279 #define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 01280 #define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 01281 #define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */ 01282 #define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */ 01283 #define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */ 01284 #define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */ 01285 #define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */ 01286 #define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */ 01287 #define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */ 01288 #define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */ 01289 #define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */ 01290 #define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */ 01291 #define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */ 01292 #define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */ 01293 #define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */ 01294 #define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */ 01295 #define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */ 01296 #define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */ 01297 01298 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 01299 #define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 01300 #define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 01301 #define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */ 01302 #define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */ 01303 #define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */ 01304 #define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */ 01305 #define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */ 01306 #define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */ 01307 #define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */ 01308 #define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */ 01309 #define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */ 01310 #define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */ 01311 #define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */ 01312 #define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */ 01313 #define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */ 01314 #define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */ 01315 #define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */ 01316 #define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */ 01317 01318 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 01319 #define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 01320 #define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 01321 #define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */ 01322 #define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */ 01323 #define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */ 01324 #define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */ 01325 #define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */ 01326 #define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */ 01327 #define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */ 01328 #define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */ 01329 #define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */ 01330 #define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */ 01331 #define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */ 01332 #define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */ 01333 #define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */ 01334 #define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */ 01335 #define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */ 01336 #define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */ 01337 01338 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 01339 #define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 01340 #define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 01341 #define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */ 01342 #define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */ 01343 #define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */ 01344 #define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */ 01345 #define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */ 01346 #define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */ 01347 #define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */ 01348 #define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */ 01349 #define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */ 01350 #define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */ 01351 #define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */ 01352 #define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */ 01353 #define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */ 01354 #define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */ 01355 #define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */ 01356 #define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */ 01357 01358 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 01359 #define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 01360 #define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 01361 #define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */ 01362 #define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */ 01363 #define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */ 01364 #define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */ 01365 #define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */ 01366 #define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */ 01367 #define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */ 01368 #define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */ 01369 #define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */ 01370 #define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */ 01371 #define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */ 01372 #define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */ 01373 #define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */ 01374 #define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */ 01375 #define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */ 01376 #define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */ 01377 01378 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 01379 #define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 01380 #define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 01381 #define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */ 01382 #define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */ 01383 #define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */ 01384 #define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */ 01385 #define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */ 01386 #define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */ 01387 #define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */ 01388 #define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */ 01389 #define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */ 01390 #define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */ 01391 #define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */ 01392 #define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */ 01393 #define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */ 01394 #define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */ 01395 #define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */ 01396 #define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */ 01397 01398 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 01399 #define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 01400 #define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 01401 #define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */ 01402 #define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */ 01403 #define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */ 01404 #define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */ 01405 #define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */ 01406 #define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */ 01407 #define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */ 01408 #define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */ 01409 #define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */ 01410 #define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */ 01411 #define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */ 01412 #define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */ 01413 #define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */ 01414 #define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */ 01415 #define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */ 01416 #define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */ 01417 01418 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 01419 #define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 01420 #define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 01421 #define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */ 01422 #define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */ 01423 #define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */ 01424 #define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */ 01425 #define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */ 01426 #define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */ 01427 #define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */ 01428 #define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */ 01429 #define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */ 01430 #define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */ 01431 #define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */ 01432 #define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */ 01433 #define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */ 01434 #define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */ 01435 #define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */ 01436 #define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */ 01437 01438 /* Register: AMLI_RAMPRI_SERIAL0 */ 01439 /* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */ 01440 01441 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 01442 #define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 01443 #define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 01444 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */ 01445 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */ 01446 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */ 01447 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */ 01448 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */ 01449 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */ 01450 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */ 01451 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */ 01452 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */ 01453 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */ 01454 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */ 01455 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */ 01456 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */ 01457 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */ 01458 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */ 01459 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */ 01460 01461 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 01462 #define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 01463 #define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 01464 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */ 01465 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */ 01466 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */ 01467 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */ 01468 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */ 01469 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */ 01470 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */ 01471 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */ 01472 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */ 01473 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */ 01474 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */ 01475 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */ 01476 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */ 01477 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */ 01478 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */ 01479 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */ 01480 01481 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 01482 #define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 01483 #define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 01484 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */ 01485 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */ 01486 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */ 01487 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */ 01488 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */ 01489 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */ 01490 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */ 01491 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */ 01492 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */ 01493 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */ 01494 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */ 01495 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */ 01496 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */ 01497 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */ 01498 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */ 01499 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */ 01500 01501 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 01502 #define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 01503 #define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 01504 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */ 01505 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */ 01506 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */ 01507 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */ 01508 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */ 01509 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */ 01510 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */ 01511 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */ 01512 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */ 01513 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */ 01514 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */ 01515 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */ 01516 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */ 01517 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */ 01518 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */ 01519 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */ 01520 01521 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 01522 #define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 01523 #define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 01524 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */ 01525 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */ 01526 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */ 01527 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */ 01528 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */ 01529 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */ 01530 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */ 01531 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */ 01532 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */ 01533 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */ 01534 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */ 01535 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */ 01536 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */ 01537 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */ 01538 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */ 01539 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */ 01540 01541 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 01542 #define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 01543 #define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 01544 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */ 01545 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */ 01546 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */ 01547 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */ 01548 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */ 01549 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */ 01550 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */ 01551 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */ 01552 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */ 01553 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */ 01554 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */ 01555 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */ 01556 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */ 01557 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */ 01558 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */ 01559 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */ 01560 01561 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 01562 #define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 01563 #define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 01564 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */ 01565 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */ 01566 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */ 01567 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */ 01568 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */ 01569 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */ 01570 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */ 01571 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */ 01572 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */ 01573 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */ 01574 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */ 01575 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */ 01576 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */ 01577 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */ 01578 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */ 01579 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */ 01580 01581 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 01582 #define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 01583 #define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 01584 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */ 01585 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */ 01586 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */ 01587 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */ 01588 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */ 01589 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */ 01590 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */ 01591 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */ 01592 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */ 01593 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */ 01594 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */ 01595 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */ 01596 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */ 01597 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */ 01598 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */ 01599 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */ 01600 01601 /* Register: AMLI_RAMPRI_SERIAL2 */ 01602 /* Description: AHB bus master priority register for SPIM2 and SPIS2 */ 01603 01604 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 01605 #define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 01606 #define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 01607 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */ 01608 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */ 01609 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */ 01610 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */ 01611 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */ 01612 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */ 01613 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */ 01614 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */ 01615 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */ 01616 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */ 01617 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */ 01618 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */ 01619 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */ 01620 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */ 01621 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */ 01622 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */ 01623 01624 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 01625 #define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 01626 #define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 01627 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */ 01628 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */ 01629 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */ 01630 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */ 01631 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */ 01632 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */ 01633 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */ 01634 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */ 01635 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */ 01636 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */ 01637 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */ 01638 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */ 01639 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */ 01640 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */ 01641 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */ 01642 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */ 01643 01644 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 01645 #define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 01646 #define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 01647 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */ 01648 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */ 01649 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */ 01650 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */ 01651 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */ 01652 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */ 01653 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */ 01654 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */ 01655 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */ 01656 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */ 01657 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */ 01658 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */ 01659 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */ 01660 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */ 01661 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */ 01662 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */ 01663 01664 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 01665 #define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 01666 #define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 01667 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */ 01668 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */ 01669 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */ 01670 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */ 01671 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */ 01672 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */ 01673 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */ 01674 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */ 01675 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */ 01676 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */ 01677 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */ 01678 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */ 01679 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */ 01680 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */ 01681 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */ 01682 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */ 01683 01684 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 01685 #define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 01686 #define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 01687 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */ 01688 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */ 01689 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */ 01690 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */ 01691 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */ 01692 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */ 01693 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */ 01694 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */ 01695 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */ 01696 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */ 01697 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */ 01698 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */ 01699 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */ 01700 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */ 01701 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */ 01702 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */ 01703 01704 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 01705 #define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 01706 #define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 01707 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */ 01708 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */ 01709 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */ 01710 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */ 01711 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */ 01712 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */ 01713 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */ 01714 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */ 01715 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */ 01716 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */ 01717 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */ 01718 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */ 01719 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */ 01720 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */ 01721 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */ 01722 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */ 01723 01724 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 01725 #define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 01726 #define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 01727 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */ 01728 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */ 01729 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */ 01730 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */ 01731 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */ 01732 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */ 01733 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */ 01734 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */ 01735 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */ 01736 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */ 01737 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */ 01738 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */ 01739 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */ 01740 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */ 01741 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */ 01742 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */ 01743 01744 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 01745 #define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 01746 #define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 01747 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */ 01748 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */ 01749 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */ 01750 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */ 01751 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */ 01752 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */ 01753 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */ 01754 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */ 01755 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */ 01756 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */ 01757 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */ 01758 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */ 01759 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */ 01760 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */ 01761 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */ 01762 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */ 01763 01764 /* Register: AMLI_RAMPRI_NFCT */ 01765 /* Description: AHB bus master priority register for NFCT */ 01766 01767 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 01768 #define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 01769 #define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 01770 #define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */ 01771 #define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */ 01772 #define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */ 01773 #define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */ 01774 #define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */ 01775 #define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */ 01776 #define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */ 01777 #define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */ 01778 #define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */ 01779 #define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */ 01780 #define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */ 01781 #define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */ 01782 #define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */ 01783 #define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */ 01784 #define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */ 01785 #define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */ 01786 01787 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 01788 #define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 01789 #define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 01790 #define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */ 01791 #define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */ 01792 #define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */ 01793 #define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */ 01794 #define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */ 01795 #define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */ 01796 #define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */ 01797 #define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */ 01798 #define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */ 01799 #define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */ 01800 #define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */ 01801 #define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */ 01802 #define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */ 01803 #define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */ 01804 #define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */ 01805 #define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */ 01806 01807 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 01808 #define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 01809 #define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 01810 #define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */ 01811 #define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */ 01812 #define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */ 01813 #define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */ 01814 #define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */ 01815 #define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */ 01816 #define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */ 01817 #define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */ 01818 #define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */ 01819 #define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */ 01820 #define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */ 01821 #define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */ 01822 #define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */ 01823 #define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */ 01824 #define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */ 01825 #define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */ 01826 01827 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 01828 #define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 01829 #define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 01830 #define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */ 01831 #define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */ 01832 #define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */ 01833 #define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */ 01834 #define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */ 01835 #define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */ 01836 #define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */ 01837 #define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */ 01838 #define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */ 01839 #define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */ 01840 #define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */ 01841 #define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */ 01842 #define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */ 01843 #define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */ 01844 #define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */ 01845 #define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */ 01846 01847 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 01848 #define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 01849 #define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 01850 #define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */ 01851 #define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */ 01852 #define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */ 01853 #define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */ 01854 #define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */ 01855 #define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */ 01856 #define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */ 01857 #define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */ 01858 #define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */ 01859 #define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */ 01860 #define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */ 01861 #define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */ 01862 #define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */ 01863 #define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */ 01864 #define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */ 01865 #define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */ 01866 01867 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 01868 #define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 01869 #define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 01870 #define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */ 01871 #define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */ 01872 #define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */ 01873 #define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */ 01874 #define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */ 01875 #define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */ 01876 #define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */ 01877 #define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */ 01878 #define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */ 01879 #define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */ 01880 #define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */ 01881 #define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */ 01882 #define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */ 01883 #define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */ 01884 #define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */ 01885 #define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */ 01886 01887 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 01888 #define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 01889 #define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 01890 #define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */ 01891 #define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */ 01892 #define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */ 01893 #define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */ 01894 #define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */ 01895 #define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */ 01896 #define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */ 01897 #define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */ 01898 #define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */ 01899 #define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */ 01900 #define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */ 01901 #define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */ 01902 #define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */ 01903 #define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */ 01904 #define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */ 01905 #define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */ 01906 01907 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 01908 #define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 01909 #define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 01910 #define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */ 01911 #define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */ 01912 #define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */ 01913 #define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */ 01914 #define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */ 01915 #define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */ 01916 #define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */ 01917 #define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */ 01918 #define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */ 01919 #define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */ 01920 #define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */ 01921 #define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */ 01922 #define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */ 01923 #define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */ 01924 #define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */ 01925 #define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */ 01926 01927 /* Register: AMLI_RAMPRI_I2S */ 01928 /* Description: AHB bus master priority register for I2S */ 01929 01930 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 01931 #define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 01932 #define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 01933 #define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */ 01934 #define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */ 01935 #define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */ 01936 #define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */ 01937 #define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */ 01938 #define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */ 01939 #define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */ 01940 #define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */ 01941 #define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */ 01942 #define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */ 01943 #define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */ 01944 #define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */ 01945 #define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */ 01946 #define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */ 01947 #define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */ 01948 #define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */ 01949 01950 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 01951 #define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 01952 #define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 01953 #define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */ 01954 #define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */ 01955 #define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */ 01956 #define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */ 01957 #define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */ 01958 #define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */ 01959 #define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */ 01960 #define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */ 01961 #define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */ 01962 #define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */ 01963 #define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */ 01964 #define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */ 01965 #define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */ 01966 #define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */ 01967 #define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */ 01968 #define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */ 01969 01970 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 01971 #define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 01972 #define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 01973 #define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */ 01974 #define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */ 01975 #define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */ 01976 #define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */ 01977 #define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */ 01978 #define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */ 01979 #define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */ 01980 #define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */ 01981 #define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */ 01982 #define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */ 01983 #define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */ 01984 #define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */ 01985 #define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */ 01986 #define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */ 01987 #define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */ 01988 #define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */ 01989 01990 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 01991 #define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 01992 #define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 01993 #define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */ 01994 #define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */ 01995 #define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */ 01996 #define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */ 01997 #define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */ 01998 #define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */ 01999 #define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */ 02000 #define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */ 02001 #define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */ 02002 #define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */ 02003 #define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */ 02004 #define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */ 02005 #define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */ 02006 #define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */ 02007 #define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */ 02008 #define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */ 02009 02010 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 02011 #define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 02012 #define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 02013 #define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */ 02014 #define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */ 02015 #define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */ 02016 #define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */ 02017 #define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */ 02018 #define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */ 02019 #define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */ 02020 #define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */ 02021 #define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */ 02022 #define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */ 02023 #define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */ 02024 #define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */ 02025 #define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */ 02026 #define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */ 02027 #define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */ 02028 #define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */ 02029 02030 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 02031 #define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 02032 #define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 02033 #define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */ 02034 #define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */ 02035 #define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */ 02036 #define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */ 02037 #define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */ 02038 #define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */ 02039 #define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */ 02040 #define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */ 02041 #define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */ 02042 #define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */ 02043 #define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */ 02044 #define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */ 02045 #define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */ 02046 #define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */ 02047 #define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */ 02048 #define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */ 02049 02050 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 02051 #define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 02052 #define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 02053 #define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */ 02054 #define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */ 02055 #define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */ 02056 #define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */ 02057 #define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */ 02058 #define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */ 02059 #define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */ 02060 #define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */ 02061 #define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */ 02062 #define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */ 02063 #define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */ 02064 #define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */ 02065 #define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */ 02066 #define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */ 02067 #define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */ 02068 #define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */ 02069 02070 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 02071 #define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 02072 #define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 02073 #define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */ 02074 #define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */ 02075 #define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */ 02076 #define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */ 02077 #define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */ 02078 #define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */ 02079 #define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */ 02080 #define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */ 02081 #define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */ 02082 #define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */ 02083 #define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */ 02084 #define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */ 02085 #define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */ 02086 #define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */ 02087 #define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */ 02088 #define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */ 02089 02090 /* Register: AMLI_RAMPRI_PDM */ 02091 /* Description: AHB bus master priority register for PDM */ 02092 02093 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 02094 #define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 02095 #define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 02096 #define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */ 02097 #define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */ 02098 #define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */ 02099 #define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */ 02100 #define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */ 02101 #define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */ 02102 #define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */ 02103 #define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */ 02104 #define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */ 02105 #define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */ 02106 #define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */ 02107 #define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */ 02108 #define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */ 02109 #define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */ 02110 #define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */ 02111 #define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */ 02112 02113 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 02114 #define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 02115 #define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 02116 #define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */ 02117 #define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */ 02118 #define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */ 02119 #define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */ 02120 #define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */ 02121 #define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */ 02122 #define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */ 02123 #define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */ 02124 #define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */ 02125 #define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */ 02126 #define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */ 02127 #define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */ 02128 #define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */ 02129 #define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */ 02130 #define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */ 02131 #define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */ 02132 02133 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 02134 #define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 02135 #define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 02136 #define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */ 02137 #define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */ 02138 #define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */ 02139 #define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */ 02140 #define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */ 02141 #define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */ 02142 #define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */ 02143 #define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */ 02144 #define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */ 02145 #define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */ 02146 #define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */ 02147 #define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */ 02148 #define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */ 02149 #define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */ 02150 #define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */ 02151 #define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */ 02152 02153 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 02154 #define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 02155 #define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 02156 #define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */ 02157 #define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */ 02158 #define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */ 02159 #define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */ 02160 #define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */ 02161 #define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */ 02162 #define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */ 02163 #define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */ 02164 #define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */ 02165 #define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */ 02166 #define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */ 02167 #define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */ 02168 #define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */ 02169 #define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */ 02170 #define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */ 02171 #define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */ 02172 02173 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 02174 #define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 02175 #define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 02176 #define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */ 02177 #define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */ 02178 #define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */ 02179 #define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */ 02180 #define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */ 02181 #define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */ 02182 #define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */ 02183 #define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */ 02184 #define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */ 02185 #define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */ 02186 #define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */ 02187 #define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */ 02188 #define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */ 02189 #define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */ 02190 #define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */ 02191 #define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */ 02192 02193 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 02194 #define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 02195 #define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 02196 #define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */ 02197 #define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */ 02198 #define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */ 02199 #define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */ 02200 #define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */ 02201 #define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */ 02202 #define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */ 02203 #define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */ 02204 #define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */ 02205 #define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */ 02206 #define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */ 02207 #define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */ 02208 #define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */ 02209 #define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */ 02210 #define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */ 02211 #define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */ 02212 02213 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 02214 #define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 02215 #define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 02216 #define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */ 02217 #define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */ 02218 #define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */ 02219 #define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */ 02220 #define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */ 02221 #define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */ 02222 #define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */ 02223 #define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */ 02224 #define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */ 02225 #define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */ 02226 #define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */ 02227 #define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */ 02228 #define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */ 02229 #define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */ 02230 #define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */ 02231 #define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */ 02232 02233 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 02234 #define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 02235 #define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 02236 #define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */ 02237 #define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */ 02238 #define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */ 02239 #define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */ 02240 #define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */ 02241 #define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */ 02242 #define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */ 02243 #define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */ 02244 #define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */ 02245 #define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */ 02246 #define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */ 02247 #define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */ 02248 #define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */ 02249 #define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */ 02250 #define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */ 02251 #define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */ 02252 02253 /* Register: AMLI_RAMPRI_PWM */ 02254 /* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */ 02255 02256 /* Bits 31..28 : Priority register for RAM AHB slave 7 */ 02257 #define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 02258 #define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 02259 #define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */ 02260 #define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */ 02261 #define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */ 02262 #define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */ 02263 #define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */ 02264 #define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */ 02265 #define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */ 02266 #define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */ 02267 #define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */ 02268 #define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */ 02269 #define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */ 02270 #define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */ 02271 #define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */ 02272 #define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */ 02273 #define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */ 02274 #define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */ 02275 02276 /* Bits 27..24 : Priority register for RAM AHB slave 6 */ 02277 #define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 02278 #define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 02279 #define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */ 02280 #define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */ 02281 #define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */ 02282 #define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */ 02283 #define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */ 02284 #define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */ 02285 #define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */ 02286 #define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */ 02287 #define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */ 02288 #define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */ 02289 #define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */ 02290 #define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */ 02291 #define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */ 02292 #define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */ 02293 #define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */ 02294 #define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */ 02295 02296 /* Bits 23..20 : Priority register for RAM AHB slave 5 */ 02297 #define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 02298 #define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 02299 #define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */ 02300 #define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */ 02301 #define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */ 02302 #define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */ 02303 #define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */ 02304 #define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */ 02305 #define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */ 02306 #define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */ 02307 #define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */ 02308 #define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */ 02309 #define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */ 02310 #define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */ 02311 #define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */ 02312 #define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */ 02313 #define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */ 02314 #define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */ 02315 02316 /* Bits 19..16 : Priority register for RAM AHB slave 4 */ 02317 #define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 02318 #define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 02319 #define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */ 02320 #define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */ 02321 #define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */ 02322 #define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */ 02323 #define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */ 02324 #define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */ 02325 #define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */ 02326 #define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */ 02327 #define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */ 02328 #define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */ 02329 #define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */ 02330 #define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */ 02331 #define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */ 02332 #define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */ 02333 #define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */ 02334 #define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */ 02335 02336 /* Bits 15..12 : Priority register for RAM AHB slave 3 */ 02337 #define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 02338 #define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 02339 #define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */ 02340 #define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */ 02341 #define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */ 02342 #define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */ 02343 #define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */ 02344 #define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */ 02345 #define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */ 02346 #define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */ 02347 #define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */ 02348 #define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */ 02349 #define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */ 02350 #define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */ 02351 #define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */ 02352 #define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */ 02353 #define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */ 02354 #define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */ 02355 02356 /* Bits 11..8 : Priority register for RAM AHB slave 2 */ 02357 #define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 02358 #define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 02359 #define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */ 02360 #define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */ 02361 #define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */ 02362 #define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */ 02363 #define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */ 02364 #define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */ 02365 #define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */ 02366 #define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */ 02367 #define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */ 02368 #define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */ 02369 #define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */ 02370 #define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */ 02371 #define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */ 02372 #define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */ 02373 #define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */ 02374 #define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */ 02375 02376 /* Bits 7..4 : Priority register for RAM AHB slave 1 */ 02377 #define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 02378 #define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 02379 #define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */ 02380 #define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */ 02381 #define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */ 02382 #define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */ 02383 #define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */ 02384 #define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */ 02385 #define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */ 02386 #define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */ 02387 #define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */ 02388 #define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */ 02389 #define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */ 02390 #define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */ 02391 #define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */ 02392 #define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */ 02393 #define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */ 02394 #define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */ 02395 02396 /* Bits 3..0 : Priority register for RAM AHB slave 0 */ 02397 #define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 02398 #define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 02399 #define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */ 02400 #define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */ 02401 #define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */ 02402 #define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */ 02403 #define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */ 02404 #define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */ 02405 #define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */ 02406 #define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */ 02407 #define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */ 02408 #define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */ 02409 #define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */ 02410 #define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */ 02411 #define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */ 02412 #define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */ 02413 #define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */ 02414 #define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */ 02415 02416 02417 /* Peripheral: BPROT */ 02418 /* Description: Block Protect */ 02419 02420 /* Register: BPROT_CONFIG0 */ 02421 /* Description: Block protect configuration register 0 */ 02422 02423 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */ 02424 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */ 02425 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */ 02426 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */ 02427 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */ 02428 02429 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */ 02430 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */ 02431 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */ 02432 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */ 02433 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */ 02434 02435 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */ 02436 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */ 02437 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */ 02438 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */ 02439 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */ 02440 02441 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */ 02442 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */ 02443 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */ 02444 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */ 02445 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */ 02446 02447 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */ 02448 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */ 02449 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */ 02450 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */ 02451 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */ 02452 02453 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */ 02454 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */ 02455 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */ 02456 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */ 02457 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */ 02458 02459 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */ 02460 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */ 02461 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */ 02462 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */ 02463 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */ 02464 02465 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */ 02466 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */ 02467 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */ 02468 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */ 02469 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */ 02470 02471 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */ 02472 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */ 02473 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */ 02474 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */ 02475 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */ 02476 02477 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */ 02478 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */ 02479 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */ 02480 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */ 02481 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */ 02482 02483 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */ 02484 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */ 02485 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */ 02486 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */ 02487 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */ 02488 02489 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */ 02490 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */ 02491 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */ 02492 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */ 02493 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */ 02494 02495 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */ 02496 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */ 02497 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */ 02498 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */ 02499 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */ 02500 02501 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */ 02502 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */ 02503 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */ 02504 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */ 02505 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */ 02506 02507 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */ 02508 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */ 02509 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */ 02510 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */ 02511 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */ 02512 02513 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */ 02514 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */ 02515 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */ 02516 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */ 02517 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */ 02518 02519 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */ 02520 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */ 02521 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */ 02522 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */ 02523 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */ 02524 02525 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */ 02526 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */ 02527 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */ 02528 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */ 02529 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */ 02530 02531 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */ 02532 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */ 02533 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */ 02534 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */ 02535 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */ 02536 02537 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */ 02538 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */ 02539 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */ 02540 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */ 02541 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */ 02542 02543 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */ 02544 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */ 02545 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */ 02546 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */ 02547 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */ 02548 02549 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */ 02550 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */ 02551 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */ 02552 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */ 02553 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */ 02554 02555 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */ 02556 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */ 02557 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */ 02558 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */ 02559 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */ 02560 02561 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */ 02562 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */ 02563 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */ 02564 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */ 02565 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */ 02566 02567 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */ 02568 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */ 02569 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */ 02570 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */ 02571 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */ 02572 02573 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */ 02574 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */ 02575 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */ 02576 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */ 02577 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */ 02578 02579 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */ 02580 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */ 02581 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */ 02582 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */ 02583 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */ 02584 02585 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */ 02586 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */ 02587 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */ 02588 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */ 02589 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */ 02590 02591 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */ 02592 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */ 02593 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */ 02594 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */ 02595 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */ 02596 02597 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */ 02598 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */ 02599 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */ 02600 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */ 02601 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */ 02602 02603 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */ 02604 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */ 02605 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */ 02606 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */ 02607 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */ 02608 02609 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */ 02610 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */ 02611 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */ 02612 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */ 02613 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */ 02614 02615 /* Register: BPROT_CONFIG1 */ 02616 /* Description: Block protect configuration register 1 */ 02617 02618 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */ 02619 #define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */ 02620 #define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */ 02621 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */ 02622 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */ 02623 02624 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */ 02625 #define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */ 02626 #define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */ 02627 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */ 02628 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */ 02629 02630 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */ 02631 #define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */ 02632 #define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */ 02633 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */ 02634 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */ 02635 02636 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */ 02637 #define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */ 02638 #define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */ 02639 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */ 02640 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */ 02641 02642 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */ 02643 #define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */ 02644 #define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */ 02645 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */ 02646 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */ 02647 02648 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */ 02649 #define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */ 02650 #define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */ 02651 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */ 02652 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */ 02653 02654 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */ 02655 #define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */ 02656 #define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */ 02657 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */ 02658 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */ 02659 02660 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */ 02661 #define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */ 02662 #define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */ 02663 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */ 02664 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */ 02665 02666 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */ 02667 #define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */ 02668 #define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */ 02669 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */ 02670 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */ 02671 02672 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */ 02673 #define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */ 02674 #define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */ 02675 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */ 02676 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */ 02677 02678 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */ 02679 #define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */ 02680 #define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */ 02681 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */ 02682 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */ 02683 02684 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */ 02685 #define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */ 02686 #define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */ 02687 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */ 02688 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */ 02689 02690 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */ 02691 #define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */ 02692 #define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */ 02693 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */ 02694 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */ 02695 02696 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */ 02697 #define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */ 02698 #define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */ 02699 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */ 02700 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */ 02701 02702 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */ 02703 #define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */ 02704 #define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */ 02705 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */ 02706 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */ 02707 02708 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */ 02709 #define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */ 02710 #define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */ 02711 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */ 02712 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */ 02713 02714 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */ 02715 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */ 02716 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */ 02717 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */ 02718 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */ 02719 02720 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */ 02721 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */ 02722 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */ 02723 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */ 02724 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */ 02725 02726 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */ 02727 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */ 02728 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */ 02729 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */ 02730 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */ 02731 02732 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */ 02733 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */ 02734 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */ 02735 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */ 02736 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */ 02737 02738 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */ 02739 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */ 02740 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */ 02741 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */ 02742 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */ 02743 02744 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */ 02745 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */ 02746 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */ 02747 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */ 02748 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */ 02749 02750 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */ 02751 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */ 02752 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */ 02753 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */ 02754 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */ 02755 02756 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */ 02757 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */ 02758 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */ 02759 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */ 02760 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */ 02761 02762 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */ 02763 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */ 02764 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */ 02765 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */ 02766 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */ 02767 02768 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */ 02769 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */ 02770 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */ 02771 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */ 02772 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */ 02773 02774 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */ 02775 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */ 02776 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */ 02777 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */ 02778 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */ 02779 02780 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */ 02781 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */ 02782 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */ 02783 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */ 02784 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */ 02785 02786 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */ 02787 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */ 02788 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */ 02789 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */ 02790 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */ 02791 02792 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */ 02793 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */ 02794 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */ 02795 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */ 02796 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */ 02797 02798 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */ 02799 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */ 02800 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */ 02801 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */ 02802 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */ 02803 02804 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */ 02805 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */ 02806 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */ 02807 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */ 02808 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */ 02809 02810 /* Register: BPROT_DISABLEINDEBUG */ 02811 /* Description: Disable protection mechanism in debug interface mode */ 02812 02813 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */ 02814 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ 02815 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ 02816 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */ 02817 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */ 02818 02819 /* Register: BPROT_CONFIG2 */ 02820 /* Description: Block protect configuration register 2 */ 02821 02822 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */ 02823 #define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */ 02824 #define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */ 02825 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */ 02826 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */ 02827 02828 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */ 02829 #define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */ 02830 #define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */ 02831 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */ 02832 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */ 02833 02834 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */ 02835 #define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */ 02836 #define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */ 02837 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */ 02838 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */ 02839 02840 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */ 02841 #define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */ 02842 #define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */ 02843 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */ 02844 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */ 02845 02846 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */ 02847 #define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */ 02848 #define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */ 02849 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */ 02850 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */ 02851 02852 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */ 02853 #define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */ 02854 #define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */ 02855 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */ 02856 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */ 02857 02858 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */ 02859 #define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */ 02860 #define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */ 02861 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */ 02862 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */ 02863 02864 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */ 02865 #define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */ 02866 #define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */ 02867 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */ 02868 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */ 02869 02870 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */ 02871 #define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */ 02872 #define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */ 02873 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */ 02874 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */ 02875 02876 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */ 02877 #define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */ 02878 #define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */ 02879 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */ 02880 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */ 02881 02882 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */ 02883 #define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */ 02884 #define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */ 02885 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */ 02886 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */ 02887 02888 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */ 02889 #define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */ 02890 #define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */ 02891 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */ 02892 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */ 02893 02894 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */ 02895 #define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */ 02896 #define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */ 02897 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */ 02898 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */ 02899 02900 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */ 02901 #define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */ 02902 #define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */ 02903 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */ 02904 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */ 02905 02906 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */ 02907 #define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */ 02908 #define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */ 02909 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */ 02910 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */ 02911 02912 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */ 02913 #define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */ 02914 #define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */ 02915 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */ 02916 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */ 02917 02918 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */ 02919 #define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */ 02920 #define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */ 02921 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */ 02922 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */ 02923 02924 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */ 02925 #define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */ 02926 #define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */ 02927 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */ 02928 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */ 02929 02930 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */ 02931 #define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */ 02932 #define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */ 02933 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */ 02934 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */ 02935 02936 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */ 02937 #define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */ 02938 #define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */ 02939 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */ 02940 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */ 02941 02942 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */ 02943 #define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */ 02944 #define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */ 02945 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */ 02946 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */ 02947 02948 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */ 02949 #define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */ 02950 #define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */ 02951 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */ 02952 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */ 02953 02954 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */ 02955 #define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */ 02956 #define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */ 02957 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */ 02958 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */ 02959 02960 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */ 02961 #define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */ 02962 #define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */ 02963 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */ 02964 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */ 02965 02966 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */ 02967 #define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */ 02968 #define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */ 02969 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */ 02970 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */ 02971 02972 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */ 02973 #define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */ 02974 #define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */ 02975 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */ 02976 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */ 02977 02978 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */ 02979 #define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */ 02980 #define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */ 02981 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */ 02982 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */ 02983 02984 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */ 02985 #define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */ 02986 #define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */ 02987 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */ 02988 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */ 02989 02990 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */ 02991 #define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */ 02992 #define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */ 02993 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */ 02994 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */ 02995 02996 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */ 02997 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */ 02998 #define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */ 02999 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */ 03000 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */ 03001 03002 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */ 03003 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */ 03004 #define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */ 03005 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */ 03006 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */ 03007 03008 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */ 03009 #define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */ 03010 #define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */ 03011 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */ 03012 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */ 03013 03014 /* Register: BPROT_CONFIG3 */ 03015 /* Description: Block protect configuration register 3 */ 03016 03017 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */ 03018 #define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */ 03019 #define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */ 03020 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */ 03021 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */ 03022 03023 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */ 03024 #define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */ 03025 #define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */ 03026 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */ 03027 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */ 03028 03029 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */ 03030 #define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */ 03031 #define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */ 03032 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */ 03033 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */ 03034 03035 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */ 03036 #define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */ 03037 #define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */ 03038 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */ 03039 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */ 03040 03041 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */ 03042 #define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */ 03043 #define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */ 03044 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */ 03045 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */ 03046 03047 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */ 03048 #define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */ 03049 #define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */ 03050 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */ 03051 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */ 03052 03053 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */ 03054 #define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */ 03055 #define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */ 03056 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */ 03057 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */ 03058 03059 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */ 03060 #define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */ 03061 #define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */ 03062 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */ 03063 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */ 03064 03065 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */ 03066 #define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */ 03067 #define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */ 03068 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */ 03069 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */ 03070 03071 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */ 03072 #define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */ 03073 #define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */ 03074 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */ 03075 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */ 03076 03077 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */ 03078 #define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */ 03079 #define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */ 03080 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */ 03081 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */ 03082 03083 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */ 03084 #define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */ 03085 #define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */ 03086 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */ 03087 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */ 03088 03089 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */ 03090 #define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */ 03091 #define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */ 03092 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */ 03093 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */ 03094 03095 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */ 03096 #define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */ 03097 #define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */ 03098 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */ 03099 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */ 03100 03101 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */ 03102 #define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */ 03103 #define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */ 03104 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */ 03105 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */ 03106 03107 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */ 03108 #define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */ 03109 #define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */ 03110 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */ 03111 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */ 03112 03113 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */ 03114 #define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */ 03115 #define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */ 03116 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */ 03117 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */ 03118 03119 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */ 03120 #define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */ 03121 #define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */ 03122 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */ 03123 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */ 03124 03125 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */ 03126 #define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */ 03127 #define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */ 03128 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */ 03129 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */ 03130 03131 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */ 03132 #define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */ 03133 #define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */ 03134 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */ 03135 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */ 03136 03137 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */ 03138 #define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */ 03139 #define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */ 03140 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */ 03141 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */ 03142 03143 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */ 03144 #define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */ 03145 #define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */ 03146 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */ 03147 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */ 03148 03149 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */ 03150 #define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */ 03151 #define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */ 03152 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */ 03153 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */ 03154 03155 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */ 03156 #define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */ 03157 #define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */ 03158 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */ 03159 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */ 03160 03161 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */ 03162 #define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */ 03163 #define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */ 03164 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */ 03165 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */ 03166 03167 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */ 03168 #define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */ 03169 #define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */ 03170 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */ 03171 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */ 03172 03173 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */ 03174 #define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */ 03175 #define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */ 03176 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */ 03177 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */ 03178 03179 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */ 03180 #define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */ 03181 #define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */ 03182 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */ 03183 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */ 03184 03185 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */ 03186 #define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */ 03187 #define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */ 03188 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */ 03189 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */ 03190 03191 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */ 03192 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */ 03193 #define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */ 03194 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */ 03195 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */ 03196 03197 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */ 03198 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */ 03199 #define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */ 03200 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */ 03201 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */ 03202 03203 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */ 03204 #define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */ 03205 #define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */ 03206 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */ 03207 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */ 03208 03209 03210 /* Peripheral: CCM */ 03211 /* Description: AES CCM Mode Encryption */ 03212 03213 /* Register: CCM_SHORTS */ 03214 /* Description: Shortcut register */ 03215 03216 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */ 03217 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ 03218 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ 03219 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */ 03220 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */ 03221 03222 /* Register: CCM_INTENSET */ 03223 /* Description: Enable interrupt */ 03224 03225 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */ 03226 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 03227 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 03228 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 03229 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 03230 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 03231 03232 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */ 03233 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 03234 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 03235 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 03236 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 03237 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */ 03238 03239 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */ 03240 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 03241 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 03242 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 03243 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 03244 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */ 03245 03246 /* Register: CCM_INTENCLR */ 03247 /* Description: Disable interrupt */ 03248 03249 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */ 03250 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 03251 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 03252 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 03253 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 03254 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 03255 03256 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */ 03257 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 03258 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 03259 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */ 03260 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */ 03261 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */ 03262 03263 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */ 03264 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 03265 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 03266 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */ 03267 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */ 03268 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */ 03269 03270 /* Register: CCM_MICSTATUS */ 03271 /* Description: MIC check result */ 03272 03273 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */ 03274 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ 03275 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ 03276 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */ 03277 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */ 03278 03279 /* Register: CCM_ENABLE */ 03280 /* Description: Enable */ 03281 03282 /* Bits 1..0 : Enable or disable CCM */ 03283 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 03284 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 03285 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 03286 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ 03287 03288 /* Register: CCM_MODE */ 03289 /* Description: Operation mode */ 03290 03291 /* Bit 24 : Packet length configuration */ 03292 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */ 03293 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */ 03294 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */ 03295 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */ 03296 03297 /* Bit 16 : Data rate that the CCM shall run in synch with */ 03298 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */ 03299 #define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */ 03300 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */ 03301 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */ 03302 03303 /* Bit 0 : The mode of operation to be used */ 03304 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 03305 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 03306 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */ 03307 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */ 03308 03309 /* Register: CCM_CNFPTR */ 03310 /* Description: Pointer to data structure holding AES key and NONCE vector */ 03311 03312 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */ 03313 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */ 03314 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */ 03315 03316 /* Register: CCM_INPTR */ 03317 /* Description: Input pointer */ 03318 03319 /* Bits 31..0 : Input pointer */ 03320 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */ 03321 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */ 03322 03323 /* Register: CCM_OUTPTR */ 03324 /* Description: Output pointer */ 03325 03326 /* Bits 31..0 : Output pointer */ 03327 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */ 03328 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */ 03329 03330 /* Register: CCM_SCRATCHPTR */ 03331 /* Description: Pointer to data area used for temporary storage */ 03332 03333 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */ 03334 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */ 03335 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */ 03336 03337 03338 /* Peripheral: CLOCK */ 03339 /* Description: Clock control */ 03340 03341 /* Register: CLOCK_INTENSET */ 03342 /* Description: Enable interrupt */ 03343 03344 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */ 03345 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 03346 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ 03347 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */ 03348 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */ 03349 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */ 03350 03351 /* Bit 3 : Write '1' to Enable interrupt for DONE event */ 03352 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ 03353 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 03354 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 03355 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 03356 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */ 03357 03358 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */ 03359 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 03360 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 03361 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 03362 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 03363 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */ 03364 03365 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */ 03366 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 03367 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 03368 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 03369 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 03370 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */ 03371 03372 /* Register: CLOCK_INTENCLR */ 03373 /* Description: Disable interrupt */ 03374 03375 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */ 03376 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 03377 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ 03378 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */ 03379 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */ 03380 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */ 03381 03382 /* Bit 3 : Write '1' to Disable interrupt for DONE event */ 03383 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ 03384 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 03385 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 03386 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 03387 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 03388 03389 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */ 03390 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 03391 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 03392 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 03393 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 03394 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */ 03395 03396 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */ 03397 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 03398 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 03399 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */ 03400 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */ 03401 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */ 03402 03403 /* Register: CLOCK_HFCLKRUN */ 03404 /* Description: Status indicating that HFCLKSTART task has been triggered */ 03405 03406 /* Bit 0 : HFCLKSTART task triggered or not */ 03407 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 03408 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 03409 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 03410 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 03411 03412 /* Register: CLOCK_HFCLKSTAT */ 03413 /* Description: HFCLK status */ 03414 03415 /* Bit 16 : HFCLK state */ 03416 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 03417 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 03418 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */ 03419 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */ 03420 03421 /* Bit 0 : Source of HFCLK */ 03422 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 03423 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 03424 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */ 03425 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */ 03426 03427 /* Register: CLOCK_LFCLKRUN */ 03428 /* Description: Status indicating that LFCLKSTART task has been triggered */ 03429 03430 /* Bit 0 : LFCLKSTART task triggered or not */ 03431 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 03432 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 03433 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */ 03434 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */ 03435 03436 /* Register: CLOCK_LFCLKSTAT */ 03437 /* Description: LFCLK status */ 03438 03439 /* Bit 16 : LFCLK state */ 03440 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 03441 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 03442 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */ 03443 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */ 03444 03445 /* Bits 1..0 : Source of LFCLK */ 03446 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 03447 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 03448 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 03449 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 03450 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 03451 03452 /* Register: CLOCK_LFCLKSRCCOPY */ 03453 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */ 03454 03455 /* Bits 1..0 : Clock source */ 03456 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 03457 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 03458 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 03459 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 03460 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 03461 03462 /* Register: CLOCK_LFCLKSRC */ 03463 /* Description: Clock source for the LFCLK */ 03464 03465 /* Bits 1..0 : Clock source */ 03466 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 03467 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 03468 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */ 03469 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */ 03470 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */ 03471 03472 /* Register: CLOCK_CTIV */ 03473 /* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */ 03474 03475 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */ 03476 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ 03477 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ 03478 03479 /* Register: CLOCK_TRACECONFIG */ 03480 /* Description: Clocking options for the Trace Port debug interface */ 03481 03482 /* Bits 17..16 : Pin multiplexing of trace signals. */ 03483 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */ 03484 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */ 03485 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */ 03486 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */ 03487 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */ 03488 03489 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */ 03490 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */ 03491 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */ 03492 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */ 03493 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */ 03494 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */ 03495 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */ 03496 03497 03498 /* Peripheral: COMP */ 03499 /* Description: Comparator */ 03500 03501 /* Register: COMP_SHORTS */ 03502 /* Description: Shortcut register */ 03503 03504 /* Bit 4 : Shortcut between CROSS event and STOP task */ 03505 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ 03506 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ 03507 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ 03508 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ 03509 03510 /* Bit 3 : Shortcut between UP event and STOP task */ 03511 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ 03512 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ 03513 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ 03514 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ 03515 03516 /* Bit 2 : Shortcut between DOWN event and STOP task */ 03517 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ 03518 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ 03519 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ 03520 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ 03521 03522 /* Bit 1 : Shortcut between READY event and STOP task */ 03523 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ 03524 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ 03525 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ 03526 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ 03527 03528 /* Bit 0 : Shortcut between READY event and SAMPLE task */ 03529 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ 03530 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ 03531 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ 03532 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ 03533 03534 /* Register: COMP_INTEN */ 03535 /* Description: Enable or disable interrupt */ 03536 03537 /* Bit 3 : Enable or disable interrupt for CROSS event */ 03538 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 03539 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */ 03540 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */ 03541 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */ 03542 03543 /* Bit 2 : Enable or disable interrupt for UP event */ 03544 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */ 03545 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */ 03546 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */ 03547 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */ 03548 03549 /* Bit 1 : Enable or disable interrupt for DOWN event */ 03550 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 03551 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */ 03552 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */ 03553 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */ 03554 03555 /* Bit 0 : Enable or disable interrupt for READY event */ 03556 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ 03557 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */ 03558 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */ 03559 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */ 03560 03561 /* Register: COMP_INTENSET */ 03562 /* Description: Enable interrupt */ 03563 03564 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */ 03565 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 03566 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ 03567 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ 03568 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ 03569 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ 03570 03571 /* Bit 2 : Write '1' to Enable interrupt for UP event */ 03572 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ 03573 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ 03574 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ 03575 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ 03576 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */ 03577 03578 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */ 03579 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 03580 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ 03581 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ 03582 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ 03583 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ 03584 03585 /* Bit 0 : Write '1' to Enable interrupt for READY event */ 03586 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 03587 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 03588 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 03589 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 03590 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */ 03591 03592 /* Register: COMP_INTENCLR */ 03593 /* Description: Disable interrupt */ 03594 03595 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */ 03596 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 03597 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ 03598 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ 03599 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ 03600 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ 03601 03602 /* Bit 2 : Write '1' to Disable interrupt for UP event */ 03603 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ 03604 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ 03605 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ 03606 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ 03607 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ 03608 03609 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */ 03610 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 03611 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ 03612 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ 03613 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ 03614 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ 03615 03616 /* Bit 0 : Write '1' to Disable interrupt for READY event */ 03617 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 03618 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 03619 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 03620 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 03621 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ 03622 03623 /* Register: COMP_RESULT */ 03624 /* Description: Compare result */ 03625 03626 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ 03627 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 03628 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 03629 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */ 03630 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */ 03631 03632 /* Register: COMP_ENABLE */ 03633 /* Description: COMP enable */ 03634 03635 /* Bits 1..0 : Enable or disable COMP */ 03636 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 03637 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 03638 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 03639 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */ 03640 03641 /* Register: COMP_PSEL */ 03642 /* Description: Pin select */ 03643 03644 /* Bits 2..0 : Analog pin select */ 03645 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ 03646 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ 03647 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ 03648 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ 03649 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ 03650 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ 03651 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ 03652 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ 03653 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ 03654 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ 03655 03656 /* Register: COMP_REFSEL */ 03657 /* Description: Reference source select */ 03658 03659 /* Bits 2..0 : Reference select */ 03660 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ 03661 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 03662 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */ 03663 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */ 03664 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */ 03665 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */ 03666 #define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */ 03667 03668 /* Register: COMP_EXTREFSEL */ 03669 /* Description: External reference select */ 03670 03671 /* Bit 0 : External analog reference select */ 03672 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ 03673 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 03674 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ 03675 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ 03676 03677 /* Register: COMP_TH */ 03678 /* Description: Threshold configuration for hysteresis unit */ 03679 03680 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */ 03681 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */ 03682 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */ 03683 03684 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */ 03685 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */ 03686 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */ 03687 03688 /* Register: COMP_MODE */ 03689 /* Description: Mode configuration */ 03690 03691 /* Bit 8 : Main operation mode */ 03692 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */ 03693 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */ 03694 #define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */ 03695 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */ 03696 03697 /* Bits 1..0 : Speed and power mode */ 03698 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */ 03699 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */ 03700 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode */ 03701 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */ 03702 #define COMP_MODE_SP_High (2UL) /*!< High speed mode */ 03703 03704 /* Register: COMP_HYST */ 03705 /* Description: Comparator hysteresis enable */ 03706 03707 /* Bit 0 : Comparator hysteresis */ 03708 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ 03709 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ 03710 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ 03711 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */ 03712 03713 /* Register: COMP_ISOURCE */ 03714 /* Description: Current source select on analog input */ 03715 03716 /* Bits 1..0 : Comparator hysteresis */ 03717 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */ 03718 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */ 03719 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */ 03720 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */ 03721 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */ 03722 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */ 03723 03724 03725 /* Peripheral: ECB */ 03726 /* Description: AES ECB Mode Encryption */ 03727 03728 /* Register: ECB_INTENSET */ 03729 /* Description: Enable interrupt */ 03730 03731 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */ 03732 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 03733 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 03734 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 03735 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 03736 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */ 03737 03738 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */ 03739 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 03740 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 03741 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 03742 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 03743 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */ 03744 03745 /* Register: ECB_INTENCLR */ 03746 /* Description: Disable interrupt */ 03747 03748 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */ 03749 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 03750 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 03751 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */ 03752 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */ 03753 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */ 03754 03755 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */ 03756 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 03757 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 03758 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */ 03759 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */ 03760 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */ 03761 03762 /* Register: ECB_ECBDATAPTR */ 03763 /* Description: ECB block encrypt memory pointers */ 03764 03765 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */ 03766 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */ 03767 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */ 03768 03769 03770 /* Peripheral: EGU */ 03771 /* Description: Event Generator Unit 0 */ 03772 03773 /* Register: EGU_INTEN */ 03774 /* Description: Enable or disable interrupt */ 03775 03776 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */ 03777 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 03778 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 03779 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */ 03780 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */ 03781 03782 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */ 03783 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 03784 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 03785 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */ 03786 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */ 03787 03788 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */ 03789 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 03790 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 03791 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */ 03792 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */ 03793 03794 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */ 03795 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 03796 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 03797 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */ 03798 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */ 03799 03800 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */ 03801 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 03802 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 03803 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */ 03804 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */ 03805 03806 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */ 03807 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 03808 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 03809 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */ 03810 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */ 03811 03812 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */ 03813 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 03814 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 03815 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */ 03816 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */ 03817 03818 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */ 03819 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 03820 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 03821 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */ 03822 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */ 03823 03824 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */ 03825 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 03826 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 03827 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */ 03828 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */ 03829 03830 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */ 03831 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 03832 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 03833 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */ 03834 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */ 03835 03836 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */ 03837 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 03838 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 03839 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */ 03840 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */ 03841 03842 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */ 03843 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 03844 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 03845 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */ 03846 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */ 03847 03848 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */ 03849 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 03850 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 03851 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */ 03852 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */ 03853 03854 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */ 03855 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 03856 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 03857 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */ 03858 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */ 03859 03860 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */ 03861 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 03862 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 03863 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */ 03864 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */ 03865 03866 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */ 03867 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 03868 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 03869 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */ 03870 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */ 03871 03872 /* Register: EGU_INTENSET */ 03873 /* Description: Enable interrupt */ 03874 03875 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */ 03876 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 03877 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 03878 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 03879 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 03880 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */ 03881 03882 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */ 03883 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 03884 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 03885 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ 03886 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ 03887 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */ 03888 03889 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */ 03890 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 03891 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 03892 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ 03893 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ 03894 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */ 03895 03896 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */ 03897 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 03898 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 03899 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ 03900 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ 03901 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */ 03902 03903 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */ 03904 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 03905 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 03906 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ 03907 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ 03908 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */ 03909 03910 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */ 03911 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 03912 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 03913 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ 03914 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ 03915 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */ 03916 03917 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */ 03918 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 03919 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 03920 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ 03921 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ 03922 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */ 03923 03924 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */ 03925 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 03926 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 03927 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ 03928 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ 03929 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */ 03930 03931 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */ 03932 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 03933 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 03934 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ 03935 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ 03936 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */ 03937 03938 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */ 03939 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 03940 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 03941 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ 03942 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ 03943 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */ 03944 03945 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */ 03946 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 03947 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 03948 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ 03949 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ 03950 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */ 03951 03952 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */ 03953 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 03954 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 03955 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ 03956 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ 03957 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */ 03958 03959 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */ 03960 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 03961 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 03962 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ 03963 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ 03964 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */ 03965 03966 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */ 03967 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 03968 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 03969 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ 03970 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ 03971 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */ 03972 03973 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */ 03974 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 03975 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 03976 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ 03977 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ 03978 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */ 03979 03980 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */ 03981 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 03982 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 03983 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 03984 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 03985 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */ 03986 03987 /* Register: EGU_INTENCLR */ 03988 /* Description: Disable interrupt */ 03989 03990 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */ 03991 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */ 03992 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */ 03993 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */ 03994 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */ 03995 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */ 03996 03997 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */ 03998 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */ 03999 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */ 04000 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */ 04001 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */ 04002 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */ 04003 04004 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */ 04005 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */ 04006 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */ 04007 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */ 04008 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */ 04009 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */ 04010 04011 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */ 04012 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */ 04013 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */ 04014 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */ 04015 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */ 04016 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */ 04017 04018 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */ 04019 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */ 04020 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */ 04021 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */ 04022 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */ 04023 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */ 04024 04025 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */ 04026 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */ 04027 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */ 04028 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */ 04029 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */ 04030 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */ 04031 04032 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */ 04033 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */ 04034 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */ 04035 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */ 04036 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */ 04037 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */ 04038 04039 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */ 04040 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */ 04041 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */ 04042 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */ 04043 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */ 04044 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */ 04045 04046 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */ 04047 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */ 04048 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */ 04049 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */ 04050 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */ 04051 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */ 04052 04053 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */ 04054 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */ 04055 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */ 04056 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */ 04057 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */ 04058 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */ 04059 04060 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */ 04061 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */ 04062 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */ 04063 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */ 04064 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */ 04065 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */ 04066 04067 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */ 04068 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */ 04069 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */ 04070 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */ 04071 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */ 04072 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */ 04073 04074 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */ 04075 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */ 04076 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */ 04077 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */ 04078 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */ 04079 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */ 04080 04081 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */ 04082 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */ 04083 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */ 04084 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */ 04085 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */ 04086 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */ 04087 04088 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */ 04089 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */ 04090 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */ 04091 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */ 04092 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */ 04093 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */ 04094 04095 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */ 04096 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */ 04097 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */ 04098 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */ 04099 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */ 04100 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */ 04101 04102 04103 /* Peripheral: FICR */ 04104 /* Description: Factory Information Configuration Registers */ 04105 04106 /* Register: FICR_CODEPAGESIZE */ 04107 /* Description: Code memory page size */ 04108 04109 /* Bits 31..0 : Code memory page size */ 04110 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */ 04111 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */ 04112 04113 /* Register: FICR_CODESIZE */ 04114 /* Description: Code memory size */ 04115 04116 /* Bits 31..0 : Code memory size in number of pages */ 04117 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */ 04118 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */ 04119 04120 /* Register: FICR_DEVICEID */ 04121 /* Description: Description collection[0]: Device identifier */ 04122 04123 /* Bits 31..0 : 64 bit unique device identifier */ 04124 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */ 04125 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */ 04126 04127 /* Register: FICR_ER */ 04128 /* Description: Description collection[0]: Encryption Root, word 0 */ 04129 04130 /* Bits 31..0 : Encryption Root, word n */ 04131 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */ 04132 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */ 04133 04134 /* Register: FICR_IR */ 04135 /* Description: Description collection[0]: Identity Root, word 0 */ 04136 04137 /* Bits 31..0 : Identity Root, word n */ 04138 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */ 04139 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */ 04140 04141 /* Register: FICR_DEVICEADDRTYPE */ 04142 /* Description: Device address type */ 04143 04144 /* Bit 0 : Device address type */ 04145 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ 04146 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ 04147 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */ 04148 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */ 04149 04150 /* Register: FICR_DEVICEADDR */ 04151 /* Description: Description collection[0]: Device address 0 */ 04152 04153 /* Bits 31..0 : 48 bit device address */ 04154 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */ 04155 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */ 04156 04157 /* Register: FICR_INFO_PART */ 04158 /* Description: Part code */ 04159 04160 /* Bits 31..0 : Part code */ 04161 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ 04162 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ 04163 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */ 04164 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 04165 04166 /* Register: FICR_INFO_VARIANT */ 04167 /* Description: Part Variant, Hardware version and Production configuration */ 04168 04169 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */ 04170 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ 04171 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ 04172 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */ 04173 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */ 04174 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */ 04175 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */ 04176 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 04177 04178 /* Register: FICR_INFO_PACKAGE */ 04179 /* Description: Package option */ 04180 04181 /* Bits 31..0 : Package option */ 04182 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ 04183 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ 04184 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */ 04185 #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */ 04186 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 04187 04188 /* Register: FICR_INFO_RAM */ 04189 /* Description: RAM variant */ 04190 04191 /* Bits 31..0 : RAM variant */ 04192 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ 04193 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ 04194 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */ 04195 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */ 04196 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */ 04197 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 04198 04199 /* Register: FICR_INFO_FLASH */ 04200 /* Description: Flash variant */ 04201 04202 /* Bits 31..0 : Flash variant */ 04203 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ 04204 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ 04205 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */ 04206 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */ 04207 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */ 04208 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 04209 04210 /* Register: FICR_TEMP_A0 */ 04211 /* Description: Slope definition A0. */ 04212 04213 /* Bits 11..0 : A (slope definition) register. */ 04214 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */ 04215 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */ 04216 04217 /* Register: FICR_TEMP_A1 */ 04218 /* Description: Slope definition A1. */ 04219 04220 /* Bits 11..0 : A (slope definition) register. */ 04221 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */ 04222 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */ 04223 04224 /* Register: FICR_TEMP_A2 */ 04225 /* Description: Slope definition A2. */ 04226 04227 /* Bits 11..0 : A (slope definition) register. */ 04228 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */ 04229 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */ 04230 04231 /* Register: FICR_TEMP_A3 */ 04232 /* Description: Slope definition A3. */ 04233 04234 /* Bits 11..0 : A (slope definition) register. */ 04235 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */ 04236 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */ 04237 04238 /* Register: FICR_TEMP_A4 */ 04239 /* Description: Slope definition A4. */ 04240 04241 /* Bits 11..0 : A (slope definition) register. */ 04242 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */ 04243 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */ 04244 04245 /* Register: FICR_TEMP_A5 */ 04246 /* Description: Slope definition A5. */ 04247 04248 /* Bits 11..0 : A (slope definition) register. */ 04249 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */ 04250 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */ 04251 04252 /* Register: FICR_TEMP_B0 */ 04253 /* Description: y-intercept B0. */ 04254 04255 /* Bits 13..0 : B (y-intercept) */ 04256 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */ 04257 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */ 04258 04259 /* Register: FICR_TEMP_B1 */ 04260 /* Description: y-intercept B1. */ 04261 04262 /* Bits 13..0 : B (y-intercept) */ 04263 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */ 04264 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */ 04265 04266 /* Register: FICR_TEMP_B2 */ 04267 /* Description: y-intercept B2. */ 04268 04269 /* Bits 13..0 : B (y-intercept) */ 04270 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */ 04271 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */ 04272 04273 /* Register: FICR_TEMP_B3 */ 04274 /* Description: y-intercept B3. */ 04275 04276 /* Bits 13..0 : B (y-intercept) */ 04277 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */ 04278 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */ 04279 04280 /* Register: FICR_TEMP_B4 */ 04281 /* Description: y-intercept B4. */ 04282 04283 /* Bits 13..0 : B (y-intercept) */ 04284 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */ 04285 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */ 04286 04287 /* Register: FICR_TEMP_B5 */ 04288 /* Description: y-intercept B5. */ 04289 04290 /* Bits 13..0 : B (y-intercept) */ 04291 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */ 04292 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */ 04293 04294 /* Register: FICR_TEMP_T0 */ 04295 /* Description: Segment end T0. */ 04296 04297 /* Bits 7..0 : T (segment end)register. */ 04298 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */ 04299 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */ 04300 04301 /* Register: FICR_TEMP_T1 */ 04302 /* Description: Segment end T1. */ 04303 04304 /* Bits 7..0 : T (segment end)register. */ 04305 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */ 04306 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */ 04307 04308 /* Register: FICR_TEMP_T2 */ 04309 /* Description: Segment end T2. */ 04310 04311 /* Bits 7..0 : T (segment end)register. */ 04312 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */ 04313 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */ 04314 04315 /* Register: FICR_TEMP_T3 */ 04316 /* Description: Segment end T3. */ 04317 04318 /* Bits 7..0 : T (segment end)register. */ 04319 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */ 04320 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */ 04321 04322 /* Register: FICR_TEMP_T4 */ 04323 /* Description: Segment end T4. */ 04324 04325 /* Bits 7..0 : T (segment end)register. */ 04326 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */ 04327 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */ 04328 04329 /* Register: FICR_NFC_TAGHEADER0 */ 04330 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ 04331 04332 /* Bits 31..24 : Unique identifier byte 3 */ 04333 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */ 04334 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */ 04335 04336 /* Bits 23..16 : Unique identifier byte 2 */ 04337 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */ 04338 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */ 04339 04340 /* Bits 15..8 : Unique identifier byte 1 */ 04341 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */ 04342 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */ 04343 04344 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */ 04345 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */ 04346 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */ 04347 04348 /* Register: FICR_NFC_TAGHEADER1 */ 04349 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ 04350 04351 /* Bits 31..24 : Unique identifier byte 7 */ 04352 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */ 04353 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */ 04354 04355 /* Bits 23..16 : Unique identifier byte 6 */ 04356 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */ 04357 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */ 04358 04359 /* Bits 15..8 : Unique identifier byte 5 */ 04360 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */ 04361 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */ 04362 04363 /* Bits 7..0 : Unique identifier byte 4 */ 04364 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */ 04365 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */ 04366 04367 /* Register: FICR_NFC_TAGHEADER2 */ 04368 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ 04369 04370 /* Bits 31..24 : Unique identifier byte 11 */ 04371 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */ 04372 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */ 04373 04374 /* Bits 23..16 : Unique identifier byte 10 */ 04375 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */ 04376 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */ 04377 04378 /* Bits 15..8 : Unique identifier byte 9 */ 04379 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */ 04380 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */ 04381 04382 /* Bits 7..0 : Unique identifier byte 8 */ 04383 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */ 04384 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */ 04385 04386 /* Register: FICR_NFC_TAGHEADER3 */ 04387 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */ 04388 04389 /* Bits 31..24 : Unique identifier byte 15 */ 04390 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */ 04391 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */ 04392 04393 /* Bits 23..16 : Unique identifier byte 14 */ 04394 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */ 04395 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */ 04396 04397 /* Bits 15..8 : Unique identifier byte 13 */ 04398 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */ 04399 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */ 04400 04401 /* Bits 7..0 : Unique identifier byte 12 */ 04402 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */ 04403 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */ 04404 04405 04406 /* Peripheral: GPIOTE */ 04407 /* Description: GPIO Tasks and Events */ 04408 04409 /* Register: GPIOTE_INTENSET */ 04410 /* Description: Enable interrupt */ 04411 04412 /* Bit 31 : Write '1' to Enable interrupt for PORT event */ 04413 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ 04414 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ 04415 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */ 04416 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */ 04417 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */ 04418 04419 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */ 04420 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */ 04421 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */ 04422 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */ 04423 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */ 04424 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */ 04425 04426 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */ 04427 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */ 04428 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */ 04429 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */ 04430 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */ 04431 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */ 04432 04433 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */ 04434 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */ 04435 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */ 04436 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */ 04437 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */ 04438 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */ 04439 04440 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */ 04441 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */ 04442 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */ 04443 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */ 04444 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */ 04445 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */ 04446 04447 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */ 04448 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ 04449 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ 04450 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */ 04451 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */ 04452 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */ 04453 04454 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */ 04455 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ 04456 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ 04457 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */ 04458 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */ 04459 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */ 04460 04461 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */ 04462 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ 04463 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ 04464 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */ 04465 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */ 04466 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */ 04467 04468 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */ 04469 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ 04470 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ 04471 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */ 04472 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */ 04473 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */ 04474 04475 /* Register: GPIOTE_INTENCLR */ 04476 /* Description: Disable interrupt */ 04477 04478 /* Bit 31 : Write '1' to Disable interrupt for PORT event */ 04479 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ 04480 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ 04481 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */ 04482 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */ 04483 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */ 04484 04485 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */ 04486 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */ 04487 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */ 04488 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */ 04489 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */ 04490 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */ 04491 04492 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */ 04493 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */ 04494 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */ 04495 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */ 04496 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */ 04497 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */ 04498 04499 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */ 04500 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */ 04501 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */ 04502 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */ 04503 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */ 04504 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */ 04505 04506 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */ 04507 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */ 04508 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */ 04509 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */ 04510 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */ 04511 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */ 04512 04513 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */ 04514 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ 04515 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ 04516 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */ 04517 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */ 04518 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */ 04519 04520 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */ 04521 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ 04522 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ 04523 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */ 04524 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */ 04525 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */ 04526 04527 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */ 04528 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ 04529 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ 04530 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */ 04531 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */ 04532 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */ 04533 04534 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */ 04535 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ 04536 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ 04537 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */ 04538 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */ 04539 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */ 04540 04541 /* Register: GPIOTE_CONFIG */ 04542 /* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */ 04543 04544 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */ 04545 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ 04546 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ 04547 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */ 04548 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */ 04549 04550 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */ 04551 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ 04552 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ 04553 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */ 04554 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */ 04555 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */ 04556 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */ 04557 04558 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */ 04559 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 04560 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 04561 04562 /* Bits 1..0 : Mode */ 04563 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ 04564 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 04565 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */ 04566 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */ 04567 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */ 04568 04569 04570 /* Peripheral: I2S */ 04571 /* Description: Inter-IC Sound */ 04572 04573 /* Register: I2S_INTEN */ 04574 /* Description: Enable or disable interrupt */ 04575 04576 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */ 04577 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 04578 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 04579 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */ 04580 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */ 04581 04582 /* Bit 2 : Enable or disable interrupt for STOPPED event */ 04583 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 04584 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 04585 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 04586 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 04587 04588 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */ 04589 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 04590 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 04591 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */ 04592 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */ 04593 04594 /* Register: I2S_INTENSET */ 04595 /* Description: Enable interrupt */ 04596 04597 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */ 04598 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 04599 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 04600 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ 04601 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ 04602 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */ 04603 04604 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */ 04605 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 04606 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 04607 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 04608 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 04609 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 04610 04611 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */ 04612 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 04613 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 04614 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ 04615 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ 04616 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */ 04617 04618 /* Register: I2S_INTENCLR */ 04619 /* Description: Disable interrupt */ 04620 04621 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */ 04622 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */ 04623 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */ 04624 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ 04625 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ 04626 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */ 04627 04628 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */ 04629 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */ 04630 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 04631 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 04632 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 04633 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 04634 04635 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */ 04636 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */ 04637 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */ 04638 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */ 04639 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */ 04640 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */ 04641 04642 /* Register: I2S_ENABLE */ 04643 /* Description: Enable I2S module. */ 04644 04645 /* Bit 0 : Enable I2S module. */ 04646 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 04647 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 04648 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 04649 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 04650 04651 /* Register: I2S_CONFIG_MODE */ 04652 /* Description: I2S mode. */ 04653 04654 /* Bit 0 : I2S mode. */ 04655 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 04656 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 04657 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */ 04658 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */ 04659 04660 /* Register: I2S_CONFIG_RXEN */ 04661 /* Description: Reception (RX) enable. */ 04662 04663 /* Bit 0 : Reception (RX) enable. */ 04664 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */ 04665 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */ 04666 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */ 04667 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */ 04668 04669 /* Register: I2S_CONFIG_TXEN */ 04670 /* Description: Transmission (TX) enable. */ 04671 04672 /* Bit 0 : Transmission (TX) enable. */ 04673 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */ 04674 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */ 04675 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */ 04676 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */ 04677 04678 /* Register: I2S_CONFIG_MCKEN */ 04679 /* Description: Master clock generator enable. */ 04680 04681 /* Bit 0 : Master clock generator enable. */ 04682 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */ 04683 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */ 04684 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */ 04685 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */ 04686 04687 /* Register: I2S_CONFIG_MCKFREQ */ 04688 /* Description: Master clock generator frequency. */ 04689 04690 /* Bits 31..0 : Master clock generator frequency. */ 04691 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */ 04692 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */ 04693 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */ 04694 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */ 04695 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */ 04696 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */ 04697 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */ 04698 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */ 04699 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */ 04700 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */ 04701 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */ 04702 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */ 04703 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */ 04704 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */ 04705 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */ 04706 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */ 04707 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */ 04708 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */ 04709 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */ 04710 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */ 04711 04712 /* Register: I2S_CONFIG_RATIO */ 04713 /* Description: MCK / LRCK ratio. */ 04714 04715 /* Bits 3..0 : MCK / LRCK ratio. */ 04716 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */ 04717 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */ 04718 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */ 04719 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */ 04720 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */ 04721 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */ 04722 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */ 04723 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */ 04724 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */ 04725 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */ 04726 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */ 04727 04728 /* Register: I2S_CONFIG_SWIDTH */ 04729 /* Description: Sample width. */ 04730 04731 /* Bits 1..0 : Sample width. */ 04732 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */ 04733 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */ 04734 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */ 04735 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */ 04736 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */ 04737 04738 /* Register: I2S_CONFIG_ALIGN */ 04739 /* Description: Alignment of sample within a frame. */ 04740 04741 /* Bit 0 : Alignment of sample within a frame. */ 04742 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */ 04743 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */ 04744 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */ 04745 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */ 04746 04747 /* Register: I2S_CONFIG_FORMAT */ 04748 /* Description: Frame format. */ 04749 04750 /* Bit 0 : Frame format. */ 04751 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */ 04752 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */ 04753 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */ 04754 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */ 04755 04756 /* Register: I2S_CONFIG_CHANNELS */ 04757 /* Description: Enable channels. */ 04758 04759 /* Bits 1..0 : Enable channels. */ 04760 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */ 04761 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */ 04762 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */ 04763 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */ 04764 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */ 04765 04766 /* Register: I2S_RXD_PTR */ 04767 /* Description: Receive buffer RAM start address. */ 04768 04769 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */ 04770 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 04771 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 04772 04773 /* Register: I2S_TXD_PTR */ 04774 /* Description: Transmit buffer RAM start address. */ 04775 04776 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */ 04777 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 04778 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 04779 04780 /* Register: I2S_RXTXD_MAXCNT */ 04781 /* Description: Size of RXD and TXD buffers. */ 04782 04783 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */ 04784 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 04785 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 04786 04787 /* Register: I2S_PSEL_MCK */ 04788 /* Description: Pin select for MCK signal. */ 04789 04790 /* Bit 31 : Connection */ 04791 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 04792 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 04793 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */ 04794 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 04795 04796 /* Bits 4..0 : Pin number */ 04797 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 04798 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */ 04799 04800 /* Register: I2S_PSEL_SCK */ 04801 /* Description: Pin select for SCK signal. */ 04802 04803 /* Bit 31 : Connection */ 04804 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 04805 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 04806 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 04807 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 04808 04809 /* Bits 4..0 : Pin number */ 04810 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 04811 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 04812 04813 /* Register: I2S_PSEL_LRCK */ 04814 /* Description: Pin select for LRCK signal. */ 04815 04816 /* Bit 31 : Connection */ 04817 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 04818 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 04819 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */ 04820 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 04821 04822 /* Bits 4..0 : Pin number */ 04823 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 04824 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */ 04825 04826 /* Register: I2S_PSEL_SDIN */ 04827 /* Description: Pin select for SDIN signal. */ 04828 04829 /* Bit 31 : Connection */ 04830 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 04831 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 04832 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */ 04833 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 04834 04835 /* Bits 4..0 : Pin number */ 04836 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */ 04837 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */ 04838 04839 /* Register: I2S_PSEL_SDOUT */ 04840 /* Description: Pin select for SDOUT signal. */ 04841 04842 /* Bit 31 : Connection */ 04843 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 04844 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 04845 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */ 04846 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ 04847 04848 /* Bits 4..0 : Pin number */ 04849 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */ 04850 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */ 04851 04852 04853 /* Peripheral: LPCOMP */ 04854 /* Description: Low Power Comparator */ 04855 04856 /* Register: LPCOMP_SHORTS */ 04857 /* Description: Shortcut register */ 04858 04859 /* Bit 4 : Shortcut between CROSS event and STOP task */ 04860 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ 04861 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ 04862 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */ 04863 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */ 04864 04865 /* Bit 3 : Shortcut between UP event and STOP task */ 04866 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ 04867 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ 04868 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */ 04869 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */ 04870 04871 /* Bit 2 : Shortcut between DOWN event and STOP task */ 04872 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ 04873 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ 04874 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */ 04875 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */ 04876 04877 /* Bit 1 : Shortcut between READY event and STOP task */ 04878 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ 04879 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ 04880 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */ 04881 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */ 04882 04883 /* Bit 0 : Shortcut between READY event and SAMPLE task */ 04884 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ 04885 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ 04886 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */ 04887 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */ 04888 04889 /* Register: LPCOMP_INTENSET */ 04890 /* Description: Enable interrupt */ 04891 04892 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */ 04893 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 04894 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ 04895 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */ 04896 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */ 04897 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */ 04898 04899 /* Bit 2 : Write '1' to Enable interrupt for UP event */ 04900 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ 04901 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ 04902 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */ 04903 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */ 04904 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */ 04905 04906 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */ 04907 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 04908 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ 04909 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */ 04910 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */ 04911 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */ 04912 04913 /* Bit 0 : Write '1' to Enable interrupt for READY event */ 04914 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 04915 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 04916 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 04917 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 04918 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */ 04919 04920 /* Register: LPCOMP_INTENCLR */ 04921 /* Description: Disable interrupt */ 04922 04923 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */ 04924 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 04925 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ 04926 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */ 04927 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */ 04928 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */ 04929 04930 /* Bit 2 : Write '1' to Disable interrupt for UP event */ 04931 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ 04932 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ 04933 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */ 04934 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */ 04935 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */ 04936 04937 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */ 04938 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 04939 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ 04940 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */ 04941 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */ 04942 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */ 04943 04944 /* Bit 0 : Write '1' to Disable interrupt for READY event */ 04945 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 04946 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 04947 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 04948 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 04949 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */ 04950 04951 /* Register: LPCOMP_RESULT */ 04952 /* Description: Compare result */ 04953 04954 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ 04955 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 04956 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 04957 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ < VIN-). */ 04958 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ > VIN-). */ 04959 04960 /* Register: LPCOMP_ENABLE */ 04961 /* Description: Enable LPCOMP */ 04962 04963 /* Bits 1..0 : Enable or disable LPCOMP */ 04964 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 04965 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 04966 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 04967 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 04968 04969 /* Register: LPCOMP_PSEL */ 04970 /* Description: Input pin select */ 04971 04972 /* Bits 2..0 : Analog pin select */ 04973 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ 04974 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ 04975 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */ 04976 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */ 04977 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */ 04978 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */ 04979 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */ 04980 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */ 04981 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */ 04982 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */ 04983 04984 /* Register: LPCOMP_REFSEL */ 04985 /* Description: Reference select */ 04986 04987 /* Bits 3..0 : Reference select */ 04988 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ 04989 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 04990 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */ 04991 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */ 04992 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */ 04993 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */ 04994 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */ 04995 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */ 04996 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */ 04997 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */ 04998 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */ 04999 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */ 05000 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */ 05001 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */ 05002 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */ 05003 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */ 05004 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */ 05005 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */ 05006 05007 /* Register: LPCOMP_EXTREFSEL */ 05008 /* Description: External reference select */ 05009 05010 /* Bit 0 : External analog reference select */ 05011 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ 05012 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 05013 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */ 05014 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */ 05015 05016 /* Register: LPCOMP_ANADETECT */ 05017 /* Description: Analog detect configuration */ 05018 05019 /* Bits 1..0 : Analog detect configuration */ 05020 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ 05021 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ 05022 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */ 05023 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */ 05024 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */ 05025 05026 /* Register: LPCOMP_HYST */ 05027 /* Description: Comparator hysteresis enable */ 05028 05029 /* Bit 0 : Comparator hysteresis enable */ 05030 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */ 05031 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */ 05032 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */ 05033 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */ 05034 05035 05036 /* Peripheral: MWU */ 05037 /* Description: Memory Watch Unit */ 05038 05039 /* Register: MWU_INTEN */ 05040 /* Description: Enable or disable interrupt */ 05041 05042 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */ 05043 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ 05044 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ 05045 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */ 05046 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */ 05047 05048 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */ 05049 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ 05050 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ 05051 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */ 05052 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */ 05053 05054 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */ 05055 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ 05056 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ 05057 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */ 05058 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */ 05059 05060 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */ 05061 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ 05062 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ 05063 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */ 05064 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */ 05065 05066 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */ 05067 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ 05068 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ 05069 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */ 05070 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */ 05071 05072 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */ 05073 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ 05074 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ 05075 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */ 05076 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */ 05077 05078 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */ 05079 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ 05080 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ 05081 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */ 05082 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */ 05083 05084 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */ 05085 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ 05086 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ 05087 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */ 05088 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */ 05089 05090 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */ 05091 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ 05092 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ 05093 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */ 05094 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */ 05095 05096 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */ 05097 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ 05098 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ 05099 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */ 05100 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */ 05101 05102 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */ 05103 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ 05104 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ 05105 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */ 05106 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */ 05107 05108 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */ 05109 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ 05110 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ 05111 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */ 05112 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */ 05113 05114 /* Register: MWU_INTENSET */ 05115 /* Description: Enable interrupt */ 05116 05117 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */ 05118 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ 05119 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ 05120 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ 05121 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ 05122 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */ 05123 05124 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */ 05125 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ 05126 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ 05127 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ 05128 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ 05129 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */ 05130 05131 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */ 05132 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ 05133 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ 05134 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ 05135 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ 05136 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */ 05137 05138 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */ 05139 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ 05140 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ 05141 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ 05142 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ 05143 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */ 05144 05145 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */ 05146 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ 05147 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ 05148 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ 05149 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ 05150 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */ 05151 05152 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */ 05153 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ 05154 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ 05155 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ 05156 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ 05157 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */ 05158 05159 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */ 05160 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ 05161 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ 05162 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ 05163 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ 05164 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */ 05165 05166 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */ 05167 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ 05168 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ 05169 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ 05170 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ 05171 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */ 05172 05173 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */ 05174 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ 05175 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ 05176 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ 05177 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ 05178 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */ 05179 05180 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */ 05181 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ 05182 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ 05183 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ 05184 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ 05185 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */ 05186 05187 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */ 05188 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ 05189 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ 05190 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ 05191 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ 05192 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */ 05193 05194 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */ 05195 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ 05196 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ 05197 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ 05198 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ 05199 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */ 05200 05201 /* Register: MWU_INTENCLR */ 05202 /* Description: Disable interrupt */ 05203 05204 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */ 05205 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ 05206 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ 05207 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ 05208 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ 05209 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ 05210 05211 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */ 05212 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ 05213 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ 05214 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ 05215 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ 05216 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ 05217 05218 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */ 05219 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ 05220 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ 05221 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ 05222 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ 05223 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ 05224 05225 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */ 05226 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ 05227 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ 05228 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ 05229 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ 05230 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ 05231 05232 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */ 05233 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ 05234 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ 05235 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ 05236 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ 05237 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */ 05238 05239 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */ 05240 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ 05241 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ 05242 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ 05243 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ 05244 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */ 05245 05246 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */ 05247 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ 05248 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ 05249 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ 05250 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ 05251 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */ 05252 05253 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */ 05254 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ 05255 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ 05256 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ 05257 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ 05258 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */ 05259 05260 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */ 05261 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ 05262 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ 05263 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ 05264 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ 05265 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */ 05266 05267 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */ 05268 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ 05269 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ 05270 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ 05271 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ 05272 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */ 05273 05274 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */ 05275 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ 05276 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ 05277 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ 05278 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ 05279 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */ 05280 05281 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */ 05282 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ 05283 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ 05284 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ 05285 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ 05286 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */ 05287 05288 /* Register: MWU_NMIEN */ 05289 /* Description: Enable or disable non-maskable interrupt */ 05290 05291 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */ 05292 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ 05293 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ 05294 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */ 05295 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */ 05296 05297 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */ 05298 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ 05299 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ 05300 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */ 05301 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */ 05302 05303 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */ 05304 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ 05305 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ 05306 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */ 05307 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */ 05308 05309 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */ 05310 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ 05311 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ 05312 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */ 05313 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */ 05314 05315 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */ 05316 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ 05317 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ 05318 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */ 05319 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */ 05320 05321 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */ 05322 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ 05323 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ 05324 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */ 05325 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */ 05326 05327 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */ 05328 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ 05329 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ 05330 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */ 05331 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */ 05332 05333 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */ 05334 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ 05335 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ 05336 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */ 05337 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */ 05338 05339 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */ 05340 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ 05341 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ 05342 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */ 05343 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */ 05344 05345 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */ 05346 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ 05347 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ 05348 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */ 05349 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */ 05350 05351 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */ 05352 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ 05353 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ 05354 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */ 05355 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */ 05356 05357 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */ 05358 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ 05359 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ 05360 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */ 05361 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */ 05362 05363 /* Register: MWU_NMIENSET */ 05364 /* Description: Enable non-maskable interrupt */ 05365 05366 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */ 05367 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ 05368 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ 05369 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ 05370 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ 05371 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */ 05372 05373 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */ 05374 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ 05375 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ 05376 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ 05377 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ 05378 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */ 05379 05380 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */ 05381 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ 05382 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ 05383 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ 05384 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ 05385 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */ 05386 05387 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */ 05388 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ 05389 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ 05390 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ 05391 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ 05392 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */ 05393 05394 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */ 05395 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ 05396 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ 05397 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ 05398 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ 05399 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */ 05400 05401 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */ 05402 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ 05403 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ 05404 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ 05405 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ 05406 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */ 05407 05408 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */ 05409 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ 05410 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ 05411 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ 05412 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ 05413 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */ 05414 05415 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */ 05416 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ 05417 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ 05418 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ 05419 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ 05420 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */ 05421 05422 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */ 05423 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ 05424 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ 05425 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ 05426 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ 05427 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */ 05428 05429 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */ 05430 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ 05431 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ 05432 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ 05433 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ 05434 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */ 05435 05436 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */ 05437 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ 05438 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ 05439 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ 05440 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ 05441 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */ 05442 05443 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */ 05444 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ 05445 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ 05446 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ 05447 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ 05448 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */ 05449 05450 /* Register: MWU_NMIENCLR */ 05451 /* Description: Disable non-maskable interrupt */ 05452 05453 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */ 05454 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */ 05455 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */ 05456 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */ 05457 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */ 05458 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */ 05459 05460 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */ 05461 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */ 05462 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */ 05463 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */ 05464 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */ 05465 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */ 05466 05467 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */ 05468 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */ 05469 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */ 05470 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */ 05471 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */ 05472 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */ 05473 05474 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */ 05475 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */ 05476 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */ 05477 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */ 05478 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */ 05479 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */ 05480 05481 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */ 05482 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */ 05483 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */ 05484 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */ 05485 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */ 05486 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */ 05487 05488 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */ 05489 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */ 05490 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */ 05491 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */ 05492 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */ 05493 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */ 05494 05495 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */ 05496 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */ 05497 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */ 05498 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */ 05499 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */ 05500 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */ 05501 05502 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */ 05503 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */ 05504 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */ 05505 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */ 05506 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */ 05507 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */ 05508 05509 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */ 05510 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */ 05511 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */ 05512 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */ 05513 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */ 05514 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */ 05515 05516 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */ 05517 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */ 05518 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */ 05519 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */ 05520 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */ 05521 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */ 05522 05523 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */ 05524 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */ 05525 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */ 05526 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */ 05527 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */ 05528 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */ 05529 05530 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */ 05531 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */ 05532 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */ 05533 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */ 05534 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */ 05535 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */ 05536 05537 /* Register: MWU_PERREGION_SUBSTATWA */ 05538 /* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */ 05539 05540 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ 05541 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */ 05542 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */ 05543 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05544 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05545 05546 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ 05547 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */ 05548 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */ 05549 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05550 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05551 05552 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ 05553 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */ 05554 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */ 05555 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05556 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05557 05558 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ 05559 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */ 05560 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */ 05561 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05562 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05563 05564 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ 05565 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */ 05566 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */ 05567 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05568 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05569 05570 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ 05571 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */ 05572 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */ 05573 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05574 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05575 05576 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ 05577 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */ 05578 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */ 05579 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05580 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05581 05582 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ 05583 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */ 05584 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */ 05585 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05586 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05587 05588 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ 05589 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */ 05590 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */ 05591 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05592 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05593 05594 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ 05595 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */ 05596 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */ 05597 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05598 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05599 05600 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ 05601 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */ 05602 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */ 05603 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05604 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05605 05606 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ 05607 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */ 05608 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */ 05609 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05610 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05611 05612 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ 05613 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */ 05614 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */ 05615 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05616 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05617 05618 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ 05619 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */ 05620 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */ 05621 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05622 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05623 05624 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ 05625 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */ 05626 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */ 05627 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05628 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05629 05630 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ 05631 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */ 05632 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */ 05633 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05634 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05635 05636 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ 05637 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */ 05638 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */ 05639 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05640 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05641 05642 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ 05643 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */ 05644 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */ 05645 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05646 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05647 05648 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ 05649 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */ 05650 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */ 05651 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05652 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05653 05654 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ 05655 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */ 05656 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */ 05657 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05658 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05659 05660 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ 05661 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */ 05662 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */ 05663 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05664 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05665 05666 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ 05667 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */ 05668 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */ 05669 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05670 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05671 05672 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ 05673 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */ 05674 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */ 05675 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05676 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05677 05678 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ 05679 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */ 05680 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */ 05681 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05682 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05683 05684 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ 05685 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */ 05686 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */ 05687 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05688 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05689 05690 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ 05691 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */ 05692 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */ 05693 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05694 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05695 05696 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ 05697 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */ 05698 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */ 05699 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05700 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05701 05702 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ 05703 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */ 05704 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */ 05705 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05706 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05707 05708 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ 05709 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */ 05710 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */ 05711 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05712 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05713 05714 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ 05715 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */ 05716 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */ 05717 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05718 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05719 05720 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ 05721 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */ 05722 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */ 05723 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05724 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05725 05726 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ 05727 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */ 05728 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */ 05729 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */ 05730 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */ 05731 05732 /* Register: MWU_PERREGION_SUBSTATRA */ 05733 /* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */ 05734 05735 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */ 05736 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */ 05737 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */ 05738 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05739 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05740 05741 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */ 05742 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */ 05743 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */ 05744 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05745 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05746 05747 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */ 05748 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */ 05749 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */ 05750 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05751 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05752 05753 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */ 05754 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */ 05755 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */ 05756 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05757 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05758 05759 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */ 05760 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */ 05761 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */ 05762 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05763 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05764 05765 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */ 05766 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */ 05767 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */ 05768 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05769 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05770 05771 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */ 05772 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */ 05773 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */ 05774 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05775 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05776 05777 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */ 05778 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */ 05779 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */ 05780 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05781 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05782 05783 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */ 05784 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */ 05785 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */ 05786 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05787 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05788 05789 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */ 05790 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */ 05791 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */ 05792 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05793 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05794 05795 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */ 05796 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */ 05797 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */ 05798 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05799 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05800 05801 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */ 05802 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */ 05803 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */ 05804 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05805 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05806 05807 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */ 05808 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */ 05809 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */ 05810 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05811 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05812 05813 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */ 05814 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */ 05815 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */ 05816 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05817 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05818 05819 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */ 05820 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */ 05821 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */ 05822 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05823 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05824 05825 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */ 05826 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */ 05827 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */ 05828 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05829 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05830 05831 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */ 05832 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */ 05833 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */ 05834 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05835 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05836 05837 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */ 05838 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */ 05839 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */ 05840 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05841 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05842 05843 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */ 05844 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */ 05845 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */ 05846 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05847 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05848 05849 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */ 05850 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */ 05851 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */ 05852 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05853 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05854 05855 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */ 05856 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */ 05857 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */ 05858 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05859 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05860 05861 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */ 05862 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */ 05863 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */ 05864 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05865 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05866 05867 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */ 05868 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */ 05869 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */ 05870 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05871 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05872 05873 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */ 05874 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */ 05875 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */ 05876 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05877 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05878 05879 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */ 05880 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */ 05881 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */ 05882 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05883 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05884 05885 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */ 05886 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */ 05887 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */ 05888 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05889 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05890 05891 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */ 05892 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */ 05893 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */ 05894 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05895 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05896 05897 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */ 05898 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */ 05899 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */ 05900 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05901 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05902 05903 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */ 05904 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */ 05905 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */ 05906 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05907 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05908 05909 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */ 05910 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */ 05911 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */ 05912 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05913 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05914 05915 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */ 05916 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */ 05917 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */ 05918 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05919 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05920 05921 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */ 05922 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */ 05923 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */ 05924 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */ 05925 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */ 05926 05927 /* Register: MWU_REGIONEN */ 05928 /* Description: Enable/disable regions watch */ 05929 05930 /* Bit 27 : Enable/disable read access watch in PREGION[1] */ 05931 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ 05932 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ 05933 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ 05934 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ 05935 05936 /* Bit 26 : Enable/disable write access watch in PREGION[1] */ 05937 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ 05938 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ 05939 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ 05940 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ 05941 05942 /* Bit 25 : Enable/disable read access watch in PREGION[0] */ 05943 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ 05944 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ 05945 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */ 05946 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */ 05947 05948 /* Bit 24 : Enable/disable write access watch in PREGION[0] */ 05949 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ 05950 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ 05951 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */ 05952 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */ 05953 05954 /* Bit 7 : Enable/disable read access watch in region[3] */ 05955 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ 05956 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ 05957 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */ 05958 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */ 05959 05960 /* Bit 6 : Enable/disable write access watch in region[3] */ 05961 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ 05962 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ 05963 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */ 05964 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */ 05965 05966 /* Bit 5 : Enable/disable read access watch in region[2] */ 05967 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ 05968 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ 05969 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */ 05970 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */ 05971 05972 /* Bit 4 : Enable/disable write access watch in region[2] */ 05973 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ 05974 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ 05975 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */ 05976 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */ 05977 05978 /* Bit 3 : Enable/disable read access watch in region[1] */ 05979 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ 05980 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ 05981 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */ 05982 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */ 05983 05984 /* Bit 2 : Enable/disable write access watch in region[1] */ 05985 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ 05986 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ 05987 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */ 05988 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */ 05989 05990 /* Bit 1 : Enable/disable read access watch in region[0] */ 05991 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ 05992 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ 05993 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */ 05994 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */ 05995 05996 /* Bit 0 : Enable/disable write access watch in region[0] */ 05997 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ 05998 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ 05999 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */ 06000 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */ 06001 06002 /* Register: MWU_REGIONENSET */ 06003 /* Description: Enable regions watch */ 06004 06005 /* Bit 27 : Enable read access watch in PREGION[1] */ 06006 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ 06007 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ 06008 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ 06009 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ 06010 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */ 06011 06012 /* Bit 26 : Enable write access watch in PREGION[1] */ 06013 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ 06014 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ 06015 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ 06016 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ 06017 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */ 06018 06019 /* Bit 25 : Enable read access watch in PREGION[0] */ 06020 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ 06021 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ 06022 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ 06023 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ 06024 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */ 06025 06026 /* Bit 24 : Enable write access watch in PREGION[0] */ 06027 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ 06028 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ 06029 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ 06030 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ 06031 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */ 06032 06033 /* Bit 7 : Enable read access watch in region[3] */ 06034 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ 06035 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ 06036 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ 06037 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ 06038 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */ 06039 06040 /* Bit 6 : Enable write access watch in region[3] */ 06041 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ 06042 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ 06043 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ 06044 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ 06045 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */ 06046 06047 /* Bit 5 : Enable read access watch in region[2] */ 06048 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ 06049 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ 06050 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ 06051 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ 06052 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */ 06053 06054 /* Bit 4 : Enable write access watch in region[2] */ 06055 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ 06056 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ 06057 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ 06058 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ 06059 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */ 06060 06061 /* Bit 3 : Enable read access watch in region[1] */ 06062 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ 06063 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ 06064 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ 06065 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ 06066 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */ 06067 06068 /* Bit 2 : Enable write access watch in region[1] */ 06069 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ 06070 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ 06071 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ 06072 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ 06073 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */ 06074 06075 /* Bit 1 : Enable read access watch in region[0] */ 06076 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ 06077 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ 06078 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ 06079 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ 06080 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */ 06081 06082 /* Bit 0 : Enable write access watch in region[0] */ 06083 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ 06084 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ 06085 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ 06086 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ 06087 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */ 06088 06089 /* Register: MWU_REGIONENCLR */ 06090 /* Description: Disable regions watch */ 06091 06092 /* Bit 27 : Disable read access watch in PREGION[1] */ 06093 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */ 06094 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */ 06095 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ 06096 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ 06097 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ 06098 06099 /* Bit 26 : Disable write access watch in PREGION[1] */ 06100 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */ 06101 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */ 06102 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ 06103 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ 06104 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ 06105 06106 /* Bit 25 : Disable read access watch in PREGION[0] */ 06107 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */ 06108 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */ 06109 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */ 06110 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */ 06111 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */ 06112 06113 /* Bit 24 : Disable write access watch in PREGION[0] */ 06114 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */ 06115 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */ 06116 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */ 06117 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */ 06118 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */ 06119 06120 /* Bit 7 : Disable read access watch in region[3] */ 06121 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */ 06122 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */ 06123 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ 06124 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ 06125 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */ 06126 06127 /* Bit 6 : Disable write access watch in region[3] */ 06128 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */ 06129 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */ 06130 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ 06131 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ 06132 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */ 06133 06134 /* Bit 5 : Disable read access watch in region[2] */ 06135 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */ 06136 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */ 06137 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ 06138 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ 06139 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */ 06140 06141 /* Bit 4 : Disable write access watch in region[2] */ 06142 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */ 06143 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */ 06144 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ 06145 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ 06146 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */ 06147 06148 /* Bit 3 : Disable read access watch in region[1] */ 06149 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */ 06150 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */ 06151 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ 06152 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ 06153 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */ 06154 06155 /* Bit 2 : Disable write access watch in region[1] */ 06156 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */ 06157 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */ 06158 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ 06159 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ 06160 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */ 06161 06162 /* Bit 1 : Disable read access watch in region[0] */ 06163 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */ 06164 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */ 06165 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */ 06166 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */ 06167 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */ 06168 06169 /* Bit 0 : Disable write access watch in region[0] */ 06170 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */ 06171 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */ 06172 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */ 06173 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */ 06174 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */ 06175 06176 /* Register: MWU_REGION_START */ 06177 /* Description: Description cluster[0]: Start address for region 0 */ 06178 06179 /* Bits 31..0 : Start address for region */ 06180 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */ 06181 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */ 06182 06183 /* Register: MWU_REGION_END */ 06184 /* Description: Description cluster[0]: End address of region 0 */ 06185 06186 /* Bits 31..0 : End address of region. */ 06187 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */ 06188 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */ 06189 06190 /* Register: MWU_PREGION_START */ 06191 /* Description: Description cluster[0]: Reserved for future use */ 06192 06193 /* Bits 31..0 : Reserved for future use */ 06194 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */ 06195 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */ 06196 06197 /* Register: MWU_PREGION_END */ 06198 /* Description: Description cluster[0]: Reserved for future use */ 06199 06200 /* Bits 31..0 : Reserved for future use */ 06201 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */ 06202 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */ 06203 06204 /* Register: MWU_PREGION_SUBS */ 06205 /* Description: Description cluster[0]: Subregions of region 0 */ 06206 06207 /* Bit 31 : Include or exclude subregion 31 in region */ 06208 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */ 06209 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */ 06210 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */ 06211 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */ 06212 06213 /* Bit 30 : Include or exclude subregion 30 in region */ 06214 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */ 06215 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */ 06216 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */ 06217 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */ 06218 06219 /* Bit 29 : Include or exclude subregion 29 in region */ 06220 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */ 06221 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */ 06222 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */ 06223 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */ 06224 06225 /* Bit 28 : Include or exclude subregion 28 in region */ 06226 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */ 06227 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */ 06228 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */ 06229 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */ 06230 06231 /* Bit 27 : Include or exclude subregion 27 in region */ 06232 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */ 06233 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */ 06234 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */ 06235 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */ 06236 06237 /* Bit 26 : Include or exclude subregion 26 in region */ 06238 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */ 06239 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */ 06240 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */ 06241 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */ 06242 06243 /* Bit 25 : Include or exclude subregion 25 in region */ 06244 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */ 06245 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */ 06246 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */ 06247 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */ 06248 06249 /* Bit 24 : Include or exclude subregion 24 in region */ 06250 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */ 06251 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */ 06252 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */ 06253 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */ 06254 06255 /* Bit 23 : Include or exclude subregion 23 in region */ 06256 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */ 06257 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */ 06258 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */ 06259 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */ 06260 06261 /* Bit 22 : Include or exclude subregion 22 in region */ 06262 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */ 06263 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */ 06264 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */ 06265 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */ 06266 06267 /* Bit 21 : Include or exclude subregion 21 in region */ 06268 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */ 06269 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */ 06270 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */ 06271 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */ 06272 06273 /* Bit 20 : Include or exclude subregion 20 in region */ 06274 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */ 06275 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */ 06276 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */ 06277 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */ 06278 06279 /* Bit 19 : Include or exclude subregion 19 in region */ 06280 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */ 06281 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */ 06282 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */ 06283 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */ 06284 06285 /* Bit 18 : Include or exclude subregion 18 in region */ 06286 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */ 06287 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */ 06288 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */ 06289 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */ 06290 06291 /* Bit 17 : Include or exclude subregion 17 in region */ 06292 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */ 06293 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */ 06294 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */ 06295 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */ 06296 06297 /* Bit 16 : Include or exclude subregion 16 in region */ 06298 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */ 06299 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */ 06300 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */ 06301 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */ 06302 06303 /* Bit 15 : Include or exclude subregion 15 in region */ 06304 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */ 06305 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */ 06306 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */ 06307 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */ 06308 06309 /* Bit 14 : Include or exclude subregion 14 in region */ 06310 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */ 06311 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */ 06312 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */ 06313 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */ 06314 06315 /* Bit 13 : Include or exclude subregion 13 in region */ 06316 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */ 06317 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */ 06318 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */ 06319 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */ 06320 06321 /* Bit 12 : Include or exclude subregion 12 in region */ 06322 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */ 06323 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */ 06324 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */ 06325 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */ 06326 06327 /* Bit 11 : Include or exclude subregion 11 in region */ 06328 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */ 06329 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */ 06330 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */ 06331 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */ 06332 06333 /* Bit 10 : Include or exclude subregion 10 in region */ 06334 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */ 06335 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */ 06336 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */ 06337 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */ 06338 06339 /* Bit 9 : Include or exclude subregion 9 in region */ 06340 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */ 06341 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */ 06342 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */ 06343 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */ 06344 06345 /* Bit 8 : Include or exclude subregion 8 in region */ 06346 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */ 06347 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */ 06348 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */ 06349 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */ 06350 06351 /* Bit 7 : Include or exclude subregion 7 in region */ 06352 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */ 06353 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */ 06354 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */ 06355 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */ 06356 06357 /* Bit 6 : Include or exclude subregion 6 in region */ 06358 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */ 06359 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */ 06360 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */ 06361 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */ 06362 06363 /* Bit 5 : Include or exclude subregion 5 in region */ 06364 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */ 06365 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */ 06366 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */ 06367 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */ 06368 06369 /* Bit 4 : Include or exclude subregion 4 in region */ 06370 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */ 06371 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */ 06372 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */ 06373 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */ 06374 06375 /* Bit 3 : Include or exclude subregion 3 in region */ 06376 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */ 06377 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */ 06378 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */ 06379 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */ 06380 06381 /* Bit 2 : Include or exclude subregion 2 in region */ 06382 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */ 06383 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */ 06384 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */ 06385 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */ 06386 06387 /* Bit 1 : Include or exclude subregion 1 in region */ 06388 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */ 06389 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */ 06390 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */ 06391 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */ 06392 06393 /* Bit 0 : Include or exclude subregion 0 in region */ 06394 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */ 06395 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */ 06396 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */ 06397 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */ 06398 06399 06400 /* Peripheral: NFCT */ 06401 /* Description: NFC-A compatible radio */ 06402 06403 /* Register: NFCT_SHORTS */ 06404 /* Description: Shortcut register */ 06405 06406 /* Bit 1 : Shortcut between FIELDLOST event and SENSE task */ 06407 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */ 06408 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */ 06409 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */ 06410 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */ 06411 06412 /* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */ 06413 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */ 06414 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */ 06415 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */ 06416 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */ 06417 06418 /* Register: NFCT_INTEN */ 06419 /* Description: Enable or disable interrupt */ 06420 06421 /* Bit 20 : Enable or disable interrupt for STARTED event */ 06422 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */ 06423 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 06424 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */ 06425 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */ 06426 06427 /* Bit 19 : Enable or disable interrupt for SELECTED event */ 06428 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ 06429 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ 06430 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */ 06431 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */ 06432 06433 /* Bit 18 : Enable or disable interrupt for COLLISION event */ 06434 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ 06435 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ 06436 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */ 06437 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */ 06438 06439 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */ 06440 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ 06441 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ 06442 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */ 06443 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */ 06444 06445 /* Bit 12 : Enable or disable interrupt for ENDTX event */ 06446 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ 06447 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 06448 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ 06449 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ 06450 06451 /* Bit 11 : Enable or disable interrupt for ENDRX event */ 06452 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ 06453 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 06454 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ 06455 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ 06456 06457 /* Bit 10 : Enable or disable interrupt for RXERROR event */ 06458 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ 06459 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ 06460 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */ 06461 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */ 06462 06463 /* Bit 7 : Enable or disable interrupt for ERROR event */ 06464 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */ 06465 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 06466 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 06467 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 06468 06469 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */ 06470 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ 06471 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ 06472 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */ 06473 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */ 06474 06475 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */ 06476 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ 06477 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ 06478 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */ 06479 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */ 06480 06481 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */ 06482 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ 06483 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ 06484 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */ 06485 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */ 06486 06487 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */ 06488 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ 06489 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ 06490 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */ 06491 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */ 06492 06493 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */ 06494 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ 06495 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ 06496 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */ 06497 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */ 06498 06499 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */ 06500 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ 06501 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ 06502 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */ 06503 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */ 06504 06505 /* Bit 0 : Enable or disable interrupt for READY event */ 06506 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */ 06507 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */ 06508 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */ 06509 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */ 06510 06511 /* Register: NFCT_INTENSET */ 06512 /* Description: Enable interrupt */ 06513 06514 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */ 06515 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */ 06516 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 06517 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 06518 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 06519 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */ 06520 06521 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */ 06522 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ 06523 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ 06524 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */ 06525 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */ 06526 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */ 06527 06528 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */ 06529 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ 06530 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ 06531 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */ 06532 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */ 06533 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */ 06534 06535 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */ 06536 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ 06537 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ 06538 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ 06539 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ 06540 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */ 06541 06542 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */ 06543 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ 06544 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 06545 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 06546 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 06547 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 06548 06549 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */ 06550 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ 06551 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 06552 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 06553 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 06554 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 06555 06556 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */ 06557 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ 06558 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ 06559 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */ 06560 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */ 06561 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */ 06562 06563 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */ 06564 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */ 06565 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 06566 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 06567 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 06568 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */ 06569 06570 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */ 06571 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ 06572 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ 06573 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ 06574 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ 06575 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */ 06576 06577 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */ 06578 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ 06579 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ 06580 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ 06581 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ 06582 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */ 06583 06584 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */ 06585 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ 06586 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ 06587 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ 06588 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ 06589 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */ 06590 06591 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */ 06592 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ 06593 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ 06594 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ 06595 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ 06596 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */ 06597 06598 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */ 06599 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ 06600 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ 06601 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ 06602 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ 06603 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */ 06604 06605 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */ 06606 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ 06607 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ 06608 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ 06609 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ 06610 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */ 06611 06612 /* Bit 0 : Write '1' to Enable interrupt for READY event */ 06613 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 06614 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 06615 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 06616 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 06617 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */ 06618 06619 /* Register: NFCT_INTENCLR */ 06620 /* Description: Disable interrupt */ 06621 06622 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */ 06623 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */ 06624 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 06625 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 06626 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 06627 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 06628 06629 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */ 06630 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */ 06631 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */ 06632 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */ 06633 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */ 06634 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */ 06635 06636 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */ 06637 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */ 06638 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */ 06639 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */ 06640 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */ 06641 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */ 06642 06643 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */ 06644 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */ 06645 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */ 06646 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */ 06647 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */ 06648 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */ 06649 06650 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */ 06651 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */ 06652 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 06653 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 06654 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 06655 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 06656 06657 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */ 06658 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */ 06659 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 06660 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 06661 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 06662 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 06663 06664 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */ 06665 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */ 06666 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */ 06667 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */ 06668 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */ 06669 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */ 06670 06671 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */ 06672 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */ 06673 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 06674 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 06675 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 06676 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 06677 06678 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */ 06679 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */ 06680 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */ 06681 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ 06682 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ 06683 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */ 06684 06685 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */ 06686 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */ 06687 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */ 06688 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ 06689 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ 06690 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */ 06691 06692 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */ 06693 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */ 06694 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */ 06695 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */ 06696 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */ 06697 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */ 06698 06699 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */ 06700 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */ 06701 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */ 06702 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */ 06703 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */ 06704 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */ 06705 06706 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */ 06707 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */ 06708 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */ 06709 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */ 06710 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */ 06711 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */ 06712 06713 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */ 06714 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */ 06715 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */ 06716 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */ 06717 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */ 06718 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */ 06719 06720 /* Bit 0 : Write '1' to Disable interrupt for READY event */ 06721 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 06722 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 06723 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 06724 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 06725 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */ 06726 06727 /* Register: NFCT_ERRORSTATUS */ 06728 /* Description: NFC Error Status register */ 06729 06730 /* Bit 3 : Field level is too low at min load resistance */ 06731 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */ 06732 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */ 06733 06734 /* Bit 2 : Field level is too high at max load resistance */ 06735 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */ 06736 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */ 06737 06738 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */ 06739 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */ 06740 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */ 06741 06742 /* Register: NFCT_FRAMESTATUS_RX */ 06743 /* Description: Result of last incoming frames */ 06744 06745 /* Bit 3 : Overrun detected */ 06746 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */ 06747 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 06748 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */ 06749 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */ 06750 06751 /* Bit 2 : Parity status of received frame */ 06752 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */ 06753 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */ 06754 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */ 06755 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */ 06756 06757 /* Bit 0 : No valid End of Frame detected */ 06758 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */ 06759 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 06760 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */ 06761 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */ 06762 06763 /* Register: NFCT_CURRENTLOADCTRL */ 06764 /* Description: Current value driven to the NFC Load Control */ 06765 06766 /* Bits 5..0 : Current value driven to the NFC Load Control */ 06767 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */ 06768 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */ 06769 06770 /* Register: NFCT_FIELDPRESENT */ 06771 /* Description: Indicates the presence or not of a valid field */ 06772 06773 /* Bit 1 : Indicates if the low level has locked to the field */ 06774 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */ 06775 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */ 06776 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */ 06777 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */ 06778 06779 /* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */ 06780 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */ 06781 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */ 06782 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */ 06783 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */ 06784 06785 /* Register: NFCT_FRAMEDELAYMIN */ 06786 /* Description: Minimum frame delay */ 06787 06788 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */ 06789 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */ 06790 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */ 06791 06792 /* Register: NFCT_FRAMEDELAYMAX */ 06793 /* Description: Maximum frame delay */ 06794 06795 /* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */ 06796 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */ 06797 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */ 06798 06799 /* Register: NFCT_FRAMEDELAYMODE */ 06800 /* Description: Configuration register for the Frame Delay Timer */ 06801 06802 /* Bits 1..0 : Configuration register for the Frame Delay Timer */ 06803 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */ 06804 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */ 06805 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */ 06806 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */ 06807 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */ 06808 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */ 06809 06810 /* Register: NFCT_PACKETPTR */ 06811 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */ 06812 06813 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */ 06814 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 06815 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */ 06816 06817 /* Register: NFCT_MAXLEN */ 06818 /* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */ 06819 06820 /* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */ 06821 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 06822 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 06823 06824 /* Register: NFCT_TXD_FRAMECONFIG */ 06825 /* Description: Configuration of outgoing frames */ 06826 06827 /* Bit 4 : CRC mode for outgoing frames */ 06828 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */ 06829 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */ 06830 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */ 06831 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */ 06832 06833 /* Bit 2 : Adding SoF or not in TX frames */ 06834 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ 06835 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ 06836 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */ 06837 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */ 06838 06839 /* Bit 1 : Discarding unused bits in start or at end of a Frame */ 06840 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */ 06841 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */ 06842 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */ 06843 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */ 06844 06845 /* Bit 0 : Adding parity or not in the frame */ 06846 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ 06847 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 06848 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */ 06849 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */ 06850 06851 /* Register: NFCT_TXD_AMOUNT */ 06852 /* Description: Size of outgoing frame */ 06853 06854 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */ 06855 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */ 06856 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */ 06857 06858 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */ 06859 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */ 06860 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */ 06861 06862 /* Register: NFCT_RXD_FRAMECONFIG */ 06863 /* Description: Configuration of incoming frames */ 06864 06865 /* Bit 4 : CRC mode for incoming frames */ 06866 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */ 06867 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */ 06868 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */ 06869 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */ 06870 06871 /* Bit 2 : SoF expected or not in RX frames */ 06872 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */ 06873 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */ 06874 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */ 06875 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */ 06876 06877 /* Bit 0 : Parity expected or not in RX frame */ 06878 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */ 06879 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 06880 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */ 06881 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */ 06882 06883 /* Register: NFCT_RXD_AMOUNT */ 06884 /* Description: Size of last incoming frame */ 06885 06886 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */ 06887 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */ 06888 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */ 06889 06890 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */ 06891 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */ 06892 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */ 06893 06894 /* Register: NFCT_NFCID1_LAST */ 06895 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */ 06896 06897 /* Bits 31..24 : NFCID1 byte W */ 06898 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */ 06899 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */ 06900 06901 /* Bits 23..16 : NFCID1 byte X */ 06902 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */ 06903 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */ 06904 06905 /* Bits 15..8 : NFCID1 byte Y */ 06906 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */ 06907 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */ 06908 06909 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */ 06910 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */ 06911 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */ 06912 06913 /* Register: NFCT_NFCID1_2ND_LAST */ 06914 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */ 06915 06916 /* Bits 23..16 : NFCID1 byte T */ 06917 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */ 06918 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */ 06919 06920 /* Bits 15..8 : NFCID1 byte U */ 06921 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */ 06922 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */ 06923 06924 /* Bits 7..0 : NFCID1 byte V */ 06925 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */ 06926 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */ 06927 06928 /* Register: NFCT_NFCID1_3RD_LAST */ 06929 /* Description: Third last NFCID1 part (10 bytes ID) */ 06930 06931 /* Bits 23..16 : NFCID1 byte Q */ 06932 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */ 06933 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */ 06934 06935 /* Bits 15..8 : NFCID1 byte R */ 06936 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */ 06937 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */ 06938 06939 /* Bits 7..0 : NFCID1 byte S */ 06940 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */ 06941 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */ 06942 06943 /* Register: NFCT_SENSRES */ 06944 /* Description: NFC-A SENS_RES auto-response settings */ 06945 06946 /* Bits 15..12 : Reserved for future use. Shall be 0. */ 06947 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */ 06948 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */ 06949 06950 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ 06951 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */ 06952 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */ 06953 06954 /* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */ 06955 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */ 06956 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */ 06957 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */ 06958 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */ 06959 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */ 06960 06961 /* Bit 5 : Reserved for future use. Shall be 0. */ 06962 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */ 06963 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */ 06964 06965 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ 06966 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */ 06967 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */ 06968 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */ 06969 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */ 06970 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */ 06971 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */ 06972 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */ 06973 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */ 06974 06975 /* Register: NFCT_SELRES */ 06976 /* Description: NFC-A SEL_RES auto-response settings */ 06977 06978 /* Bit 7 : Reserved for future use. Shall be 0. */ 06979 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */ 06980 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */ 06981 06982 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */ 06983 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */ 06984 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */ 06985 06986 /* Bits 4..3 : Reserved for future use. Shall be 0. */ 06987 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */ 06988 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */ 06989 06990 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */ 06991 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */ 06992 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */ 06993 #define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */ 06994 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */ 06995 06996 /* Bits 1..0 : Reserved for future use. Shall be 0. */ 06997 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */ 06998 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */ 06999 07000 07001 /* Peripheral: NVMC */ 07002 /* Description: Non Volatile Memory Controller */ 07003 07004 /* Register: NVMC_READY */ 07005 /* Description: Ready flag */ 07006 07007 /* Bit 0 : NVMC is ready or busy */ 07008 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 07009 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 07010 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */ 07011 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */ 07012 07013 /* Register: NVMC_CONFIG */ 07014 /* Description: Configuration register */ 07015 07016 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */ 07017 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 07018 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 07019 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */ 07020 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */ 07021 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */ 07022 07023 /* Register: NVMC_ERASEPAGE */ 07024 /* Description: Register for erasing a page in Code area */ 07025 07026 /* Bits 31..0 : Register for starting erase of a page in Code area */ 07027 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */ 07028 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */ 07029 07030 /* Register: NVMC_ERASEPCR1 */ 07031 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ 07032 07033 /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ 07034 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */ 07035 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */ 07036 07037 /* Register: NVMC_ERASEALL */ 07038 /* Description: Register for erasing all non-volatile user memory */ 07039 07040 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ 07041 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 07042 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 07043 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */ 07044 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */ 07045 07046 /* Register: NVMC_ERASEPCR0 */ 07047 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */ 07048 07049 /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */ 07050 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */ 07051 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */ 07052 07053 /* Register: NVMC_ERASEUICR */ 07054 /* Description: Register for erasing User Information Configuration Registers */ 07055 07056 /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */ 07057 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ 07058 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ 07059 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */ 07060 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */ 07061 07062 /* Register: NVMC_ICACHECNF */ 07063 /* Description: I-Code cache configuration register. */ 07064 07065 /* Bit 8 : Cache profiling enable */ 07066 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */ 07067 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */ 07068 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */ 07069 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */ 07070 07071 /* Bit 0 : Cache enable */ 07072 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */ 07073 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */ 07074 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */ 07075 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */ 07076 07077 /* Register: NVMC_IHIT */ 07078 /* Description: I-Code cache hit counter. */ 07079 07080 /* Bits 31..0 : Number of cache hits */ 07081 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */ 07082 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */ 07083 07084 /* Register: NVMC_IMISS */ 07085 /* Description: I-Code cache miss counter. */ 07086 07087 /* Bits 31..0 : Number of cache misses */ 07088 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */ 07089 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */ 07090 07091 07092 /* Peripheral: GPIO */ 07093 /* Description: GPIO Port 1 */ 07094 07095 /* Register: GPIO_OUT */ 07096 /* Description: Write GPIO port */ 07097 07098 /* Bit 31 : P0.31 pin */ 07099 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 07100 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 07101 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */ 07102 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */ 07103 07104 /* Bit 30 : P0.30 pin */ 07105 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 07106 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 07107 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */ 07108 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */ 07109 07110 /* Bit 29 : P0.29 pin */ 07111 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 07112 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 07113 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */ 07114 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */ 07115 07116 /* Bit 28 : P0.28 pin */ 07117 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 07118 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 07119 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */ 07120 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */ 07121 07122 /* Bit 27 : P0.27 pin */ 07123 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 07124 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 07125 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */ 07126 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */ 07127 07128 /* Bit 26 : P0.26 pin */ 07129 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 07130 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 07131 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */ 07132 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */ 07133 07134 /* Bit 25 : P0.25 pin */ 07135 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 07136 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 07137 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */ 07138 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */ 07139 07140 /* Bit 24 : P0.24 pin */ 07141 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 07142 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 07143 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */ 07144 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */ 07145 07146 /* Bit 23 : P0.23 pin */ 07147 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 07148 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 07149 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */ 07150 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */ 07151 07152 /* Bit 22 : P0.22 pin */ 07153 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 07154 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 07155 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */ 07156 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */ 07157 07158 /* Bit 21 : P0.21 pin */ 07159 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 07160 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 07161 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */ 07162 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */ 07163 07164 /* Bit 20 : P0.20 pin */ 07165 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 07166 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 07167 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */ 07168 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */ 07169 07170 /* Bit 19 : P0.19 pin */ 07171 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 07172 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 07173 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */ 07174 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */ 07175 07176 /* Bit 18 : P0.18 pin */ 07177 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 07178 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 07179 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */ 07180 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */ 07181 07182 /* Bit 17 : P0.17 pin */ 07183 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 07184 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 07185 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */ 07186 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */ 07187 07188 /* Bit 16 : P0.16 pin */ 07189 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 07190 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 07191 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */ 07192 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */ 07193 07194 /* Bit 15 : P0.15 pin */ 07195 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 07196 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 07197 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */ 07198 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */ 07199 07200 /* Bit 14 : P0.14 pin */ 07201 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 07202 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 07203 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */ 07204 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */ 07205 07206 /* Bit 13 : P0.13 pin */ 07207 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 07208 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 07209 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */ 07210 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */ 07211 07212 /* Bit 12 : P0.12 pin */ 07213 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 07214 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 07215 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */ 07216 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */ 07217 07218 /* Bit 11 : P0.11 pin */ 07219 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 07220 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 07221 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */ 07222 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */ 07223 07224 /* Bit 10 : P0.10 pin */ 07225 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 07226 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 07227 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */ 07228 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */ 07229 07230 /* Bit 9 : P0.9 pin */ 07231 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 07232 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 07233 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */ 07234 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */ 07235 07236 /* Bit 8 : P0.8 pin */ 07237 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 07238 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 07239 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */ 07240 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */ 07241 07242 /* Bit 7 : P0.7 pin */ 07243 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 07244 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 07245 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */ 07246 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */ 07247 07248 /* Bit 6 : P0.6 pin */ 07249 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 07250 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 07251 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */ 07252 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */ 07253 07254 /* Bit 5 : P0.5 pin */ 07255 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 07256 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 07257 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */ 07258 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */ 07259 07260 /* Bit 4 : P0.4 pin */ 07261 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 07262 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 07263 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */ 07264 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */ 07265 07266 /* Bit 3 : P0.3 pin */ 07267 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 07268 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 07269 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */ 07270 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */ 07271 07272 /* Bit 2 : P0.2 pin */ 07273 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 07274 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 07275 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */ 07276 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */ 07277 07278 /* Bit 1 : P0.1 pin */ 07279 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 07280 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 07281 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */ 07282 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */ 07283 07284 /* Bit 0 : P0.0 pin */ 07285 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 07286 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 07287 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */ 07288 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */ 07289 07290 /* Register: GPIO_OUTSET */ 07291 /* Description: Set individual bits in GPIO port */ 07292 07293 /* Bit 31 : P0.31 pin */ 07294 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 07295 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 07296 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */ 07297 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */ 07298 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07299 07300 /* Bit 30 : P0.30 pin */ 07301 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 07302 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 07303 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */ 07304 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */ 07305 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07306 07307 /* Bit 29 : P0.29 pin */ 07308 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 07309 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 07310 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */ 07311 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */ 07312 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07313 07314 /* Bit 28 : P0.28 pin */ 07315 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 07316 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 07317 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */ 07318 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */ 07319 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07320 07321 /* Bit 27 : P0.27 pin */ 07322 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 07323 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 07324 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */ 07325 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */ 07326 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07327 07328 /* Bit 26 : P0.26 pin */ 07329 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 07330 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 07331 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */ 07332 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */ 07333 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07334 07335 /* Bit 25 : P0.25 pin */ 07336 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 07337 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 07338 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */ 07339 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */ 07340 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07341 07342 /* Bit 24 : P0.24 pin */ 07343 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 07344 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 07345 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */ 07346 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */ 07347 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07348 07349 /* Bit 23 : P0.23 pin */ 07350 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 07351 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 07352 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */ 07353 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */ 07354 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07355 07356 /* Bit 22 : P0.22 pin */ 07357 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 07358 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 07359 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */ 07360 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */ 07361 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07362 07363 /* Bit 21 : P0.21 pin */ 07364 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 07365 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 07366 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */ 07367 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */ 07368 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07369 07370 /* Bit 20 : P0.20 pin */ 07371 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 07372 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 07373 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */ 07374 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */ 07375 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07376 07377 /* Bit 19 : P0.19 pin */ 07378 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 07379 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 07380 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */ 07381 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */ 07382 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07383 07384 /* Bit 18 : P0.18 pin */ 07385 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 07386 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 07387 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */ 07388 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */ 07389 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07390 07391 /* Bit 17 : P0.17 pin */ 07392 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 07393 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 07394 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */ 07395 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */ 07396 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07397 07398 /* Bit 16 : P0.16 pin */ 07399 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 07400 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 07401 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */ 07402 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */ 07403 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07404 07405 /* Bit 15 : P0.15 pin */ 07406 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 07407 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 07408 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */ 07409 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */ 07410 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07411 07412 /* Bit 14 : P0.14 pin */ 07413 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 07414 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 07415 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */ 07416 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */ 07417 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07418 07419 /* Bit 13 : P0.13 pin */ 07420 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 07421 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 07422 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */ 07423 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */ 07424 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07425 07426 /* Bit 12 : P0.12 pin */ 07427 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 07428 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 07429 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */ 07430 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */ 07431 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07432 07433 /* Bit 11 : P0.11 pin */ 07434 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 07435 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 07436 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */ 07437 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */ 07438 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07439 07440 /* Bit 10 : P0.10 pin */ 07441 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 07442 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 07443 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */ 07444 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */ 07445 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07446 07447 /* Bit 9 : P0.9 pin */ 07448 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 07449 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 07450 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */ 07451 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */ 07452 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07453 07454 /* Bit 8 : P0.8 pin */ 07455 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 07456 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 07457 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */ 07458 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */ 07459 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07460 07461 /* Bit 7 : P0.7 pin */ 07462 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 07463 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 07464 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */ 07465 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */ 07466 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07467 07468 /* Bit 6 : P0.6 pin */ 07469 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 07470 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 07471 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */ 07472 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */ 07473 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07474 07475 /* Bit 5 : P0.5 pin */ 07476 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 07477 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 07478 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */ 07479 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */ 07480 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07481 07482 /* Bit 4 : P0.4 pin */ 07483 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 07484 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 07485 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */ 07486 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */ 07487 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07488 07489 /* Bit 3 : P0.3 pin */ 07490 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 07491 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 07492 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */ 07493 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */ 07494 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07495 07496 /* Bit 2 : P0.2 pin */ 07497 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 07498 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 07499 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */ 07500 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */ 07501 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07502 07503 /* Bit 1 : P0.1 pin */ 07504 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 07505 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 07506 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */ 07507 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */ 07508 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07509 07510 /* Bit 0 : P0.0 pin */ 07511 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 07512 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 07513 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */ 07514 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */ 07515 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */ 07516 07517 /* Register: GPIO_OUTCLR */ 07518 /* Description: Clear individual bits in GPIO port */ 07519 07520 /* Bit 31 : P0.31 pin */ 07521 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 07522 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 07523 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */ 07524 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */ 07525 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07526 07527 /* Bit 30 : P0.30 pin */ 07528 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 07529 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 07530 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */ 07531 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */ 07532 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07533 07534 /* Bit 29 : P0.29 pin */ 07535 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 07536 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 07537 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */ 07538 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */ 07539 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07540 07541 /* Bit 28 : P0.28 pin */ 07542 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 07543 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 07544 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */ 07545 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */ 07546 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07547 07548 /* Bit 27 : P0.27 pin */ 07549 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 07550 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 07551 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */ 07552 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */ 07553 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07554 07555 /* Bit 26 : P0.26 pin */ 07556 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 07557 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 07558 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */ 07559 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */ 07560 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07561 07562 /* Bit 25 : P0.25 pin */ 07563 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 07564 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 07565 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */ 07566 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */ 07567 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07568 07569 /* Bit 24 : P0.24 pin */ 07570 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 07571 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 07572 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */ 07573 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */ 07574 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07575 07576 /* Bit 23 : P0.23 pin */ 07577 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 07578 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 07579 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */ 07580 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */ 07581 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07582 07583 /* Bit 22 : P0.22 pin */ 07584 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 07585 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 07586 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */ 07587 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */ 07588 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07589 07590 /* Bit 21 : P0.21 pin */ 07591 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 07592 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 07593 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */ 07594 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */ 07595 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07596 07597 /* Bit 20 : P0.20 pin */ 07598 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 07599 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 07600 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */ 07601 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */ 07602 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07603 07604 /* Bit 19 : P0.19 pin */ 07605 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 07606 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 07607 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */ 07608 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */ 07609 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07610 07611 /* Bit 18 : P0.18 pin */ 07612 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 07613 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 07614 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */ 07615 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */ 07616 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07617 07618 /* Bit 17 : P0.17 pin */ 07619 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 07620 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 07621 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */ 07622 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */ 07623 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07624 07625 /* Bit 16 : P0.16 pin */ 07626 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 07627 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 07628 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */ 07629 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */ 07630 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07631 07632 /* Bit 15 : P0.15 pin */ 07633 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 07634 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 07635 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */ 07636 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */ 07637 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07638 07639 /* Bit 14 : P0.14 pin */ 07640 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 07641 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 07642 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */ 07643 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */ 07644 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07645 07646 /* Bit 13 : P0.13 pin */ 07647 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 07648 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 07649 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */ 07650 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */ 07651 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07652 07653 /* Bit 12 : P0.12 pin */ 07654 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 07655 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 07656 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */ 07657 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */ 07658 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07659 07660 /* Bit 11 : P0.11 pin */ 07661 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 07662 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 07663 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */ 07664 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */ 07665 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07666 07667 /* Bit 10 : P0.10 pin */ 07668 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 07669 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 07670 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */ 07671 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */ 07672 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07673 07674 /* Bit 9 : P0.9 pin */ 07675 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 07676 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 07677 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */ 07678 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */ 07679 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07680 07681 /* Bit 8 : P0.8 pin */ 07682 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 07683 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 07684 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */ 07685 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */ 07686 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07687 07688 /* Bit 7 : P0.7 pin */ 07689 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 07690 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 07691 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */ 07692 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */ 07693 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07694 07695 /* Bit 6 : P0.6 pin */ 07696 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 07697 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 07698 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */ 07699 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */ 07700 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07701 07702 /* Bit 5 : P0.5 pin */ 07703 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 07704 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 07705 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */ 07706 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */ 07707 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07708 07709 /* Bit 4 : P0.4 pin */ 07710 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 07711 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 07712 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */ 07713 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */ 07714 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07715 07716 /* Bit 3 : P0.3 pin */ 07717 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 07718 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 07719 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */ 07720 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */ 07721 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07722 07723 /* Bit 2 : P0.2 pin */ 07724 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 07725 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 07726 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */ 07727 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */ 07728 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07729 07730 /* Bit 1 : P0.1 pin */ 07731 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 07732 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 07733 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */ 07734 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */ 07735 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07736 07737 /* Bit 0 : P0.0 pin */ 07738 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 07739 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 07740 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */ 07741 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */ 07742 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */ 07743 07744 /* Register: GPIO_IN */ 07745 /* Description: Read GPIO port */ 07746 07747 /* Bit 31 : P0.31 pin */ 07748 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 07749 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 07750 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */ 07751 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */ 07752 07753 /* Bit 30 : P0.30 pin */ 07754 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 07755 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 07756 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */ 07757 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */ 07758 07759 /* Bit 29 : P0.29 pin */ 07760 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 07761 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 07762 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */ 07763 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */ 07764 07765 /* Bit 28 : P0.28 pin */ 07766 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 07767 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 07768 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */ 07769 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */ 07770 07771 /* Bit 27 : P0.27 pin */ 07772 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 07773 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 07774 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */ 07775 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */ 07776 07777 /* Bit 26 : P0.26 pin */ 07778 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 07779 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 07780 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */ 07781 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */ 07782 07783 /* Bit 25 : P0.25 pin */ 07784 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 07785 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 07786 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */ 07787 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */ 07788 07789 /* Bit 24 : P0.24 pin */ 07790 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 07791 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 07792 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */ 07793 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */ 07794 07795 /* Bit 23 : P0.23 pin */ 07796 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 07797 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 07798 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */ 07799 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */ 07800 07801 /* Bit 22 : P0.22 pin */ 07802 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 07803 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 07804 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */ 07805 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */ 07806 07807 /* Bit 21 : P0.21 pin */ 07808 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 07809 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 07810 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */ 07811 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */ 07812 07813 /* Bit 20 : P0.20 pin */ 07814 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 07815 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 07816 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */ 07817 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */ 07818 07819 /* Bit 19 : P0.19 pin */ 07820 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 07821 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 07822 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */ 07823 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */ 07824 07825 /* Bit 18 : P0.18 pin */ 07826 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 07827 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 07828 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */ 07829 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */ 07830 07831 /* Bit 17 : P0.17 pin */ 07832 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 07833 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 07834 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */ 07835 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */ 07836 07837 /* Bit 16 : P0.16 pin */ 07838 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 07839 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 07840 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */ 07841 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */ 07842 07843 /* Bit 15 : P0.15 pin */ 07844 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 07845 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 07846 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */ 07847 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */ 07848 07849 /* Bit 14 : P0.14 pin */ 07850 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 07851 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 07852 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */ 07853 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */ 07854 07855 /* Bit 13 : P0.13 pin */ 07856 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 07857 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 07858 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */ 07859 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */ 07860 07861 /* Bit 12 : P0.12 pin */ 07862 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 07863 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 07864 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */ 07865 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */ 07866 07867 /* Bit 11 : P0.11 pin */ 07868 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 07869 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 07870 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */ 07871 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */ 07872 07873 /* Bit 10 : P0.10 pin */ 07874 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 07875 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 07876 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */ 07877 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */ 07878 07879 /* Bit 9 : P0.9 pin */ 07880 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 07881 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 07882 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */ 07883 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */ 07884 07885 /* Bit 8 : P0.8 pin */ 07886 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 07887 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 07888 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */ 07889 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */ 07890 07891 /* Bit 7 : P0.7 pin */ 07892 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 07893 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 07894 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */ 07895 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */ 07896 07897 /* Bit 6 : P0.6 pin */ 07898 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 07899 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 07900 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */ 07901 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */ 07902 07903 /* Bit 5 : P0.5 pin */ 07904 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 07905 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 07906 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */ 07907 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */ 07908 07909 /* Bit 4 : P0.4 pin */ 07910 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 07911 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 07912 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */ 07913 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */ 07914 07915 /* Bit 3 : P0.3 pin */ 07916 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 07917 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 07918 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */ 07919 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */ 07920 07921 /* Bit 2 : P0.2 pin */ 07922 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 07923 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 07924 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */ 07925 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */ 07926 07927 /* Bit 1 : P0.1 pin */ 07928 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 07929 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 07930 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */ 07931 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */ 07932 07933 /* Bit 0 : P0.0 pin */ 07934 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 07935 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 07936 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */ 07937 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */ 07938 07939 /* Register: GPIO_DIR */ 07940 /* Description: Direction of GPIO pins */ 07941 07942 /* Bit 31 : P0.31 pin */ 07943 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 07944 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 07945 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */ 07946 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */ 07947 07948 /* Bit 30 : P0.30 pin */ 07949 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 07950 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 07951 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */ 07952 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */ 07953 07954 /* Bit 29 : P0.29 pin */ 07955 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 07956 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 07957 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */ 07958 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */ 07959 07960 /* Bit 28 : P0.28 pin */ 07961 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 07962 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 07963 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */ 07964 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */ 07965 07966 /* Bit 27 : P0.27 pin */ 07967 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 07968 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 07969 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */ 07970 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */ 07971 07972 /* Bit 26 : P0.26 pin */ 07973 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 07974 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 07975 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */ 07976 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */ 07977 07978 /* Bit 25 : P0.25 pin */ 07979 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 07980 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 07981 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */ 07982 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */ 07983 07984 /* Bit 24 : P0.24 pin */ 07985 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 07986 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 07987 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */ 07988 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */ 07989 07990 /* Bit 23 : P0.23 pin */ 07991 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 07992 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 07993 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */ 07994 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */ 07995 07996 /* Bit 22 : P0.22 pin */ 07997 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 07998 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 07999 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */ 08000 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */ 08001 08002 /* Bit 21 : P0.21 pin */ 08003 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 08004 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 08005 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */ 08006 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */ 08007 08008 /* Bit 20 : P0.20 pin */ 08009 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 08010 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 08011 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */ 08012 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */ 08013 08014 /* Bit 19 : P0.19 pin */ 08015 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 08016 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 08017 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */ 08018 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */ 08019 08020 /* Bit 18 : P0.18 pin */ 08021 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 08022 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 08023 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */ 08024 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */ 08025 08026 /* Bit 17 : P0.17 pin */ 08027 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 08028 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 08029 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */ 08030 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */ 08031 08032 /* Bit 16 : P0.16 pin */ 08033 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 08034 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 08035 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */ 08036 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */ 08037 08038 /* Bit 15 : P0.15 pin */ 08039 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 08040 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 08041 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */ 08042 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */ 08043 08044 /* Bit 14 : P0.14 pin */ 08045 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 08046 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 08047 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */ 08048 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */ 08049 08050 /* Bit 13 : P0.13 pin */ 08051 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 08052 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 08053 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */ 08054 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */ 08055 08056 /* Bit 12 : P0.12 pin */ 08057 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 08058 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 08059 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */ 08060 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */ 08061 08062 /* Bit 11 : P0.11 pin */ 08063 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 08064 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 08065 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */ 08066 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */ 08067 08068 /* Bit 10 : P0.10 pin */ 08069 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 08070 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 08071 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */ 08072 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */ 08073 08074 /* Bit 9 : P0.9 pin */ 08075 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 08076 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 08077 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */ 08078 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */ 08079 08080 /* Bit 8 : P0.8 pin */ 08081 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 08082 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 08083 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */ 08084 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */ 08085 08086 /* Bit 7 : P0.7 pin */ 08087 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 08088 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 08089 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */ 08090 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */ 08091 08092 /* Bit 6 : P0.6 pin */ 08093 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 08094 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 08095 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */ 08096 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */ 08097 08098 /* Bit 5 : P0.5 pin */ 08099 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 08100 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 08101 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */ 08102 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */ 08103 08104 /* Bit 4 : P0.4 pin */ 08105 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 08106 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 08107 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */ 08108 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */ 08109 08110 /* Bit 3 : P0.3 pin */ 08111 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 08112 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 08113 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */ 08114 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */ 08115 08116 /* Bit 2 : P0.2 pin */ 08117 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 08118 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 08119 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */ 08120 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */ 08121 08122 /* Bit 1 : P0.1 pin */ 08123 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 08124 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 08125 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */ 08126 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */ 08127 08128 /* Bit 0 : P0.0 pin */ 08129 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 08130 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 08131 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */ 08132 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */ 08133 08134 /* Register: GPIO_DIRSET */ 08135 /* Description: DIR set register */ 08136 08137 /* Bit 31 : Set as output pin 31 */ 08138 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 08139 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 08140 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */ 08141 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */ 08142 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08143 08144 /* Bit 30 : Set as output pin 30 */ 08145 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 08146 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 08147 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */ 08148 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */ 08149 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08150 08151 /* Bit 29 : Set as output pin 29 */ 08152 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 08153 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 08154 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */ 08155 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */ 08156 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08157 08158 /* Bit 28 : Set as output pin 28 */ 08159 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 08160 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 08161 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */ 08162 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */ 08163 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08164 08165 /* Bit 27 : Set as output pin 27 */ 08166 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 08167 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 08168 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */ 08169 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */ 08170 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08171 08172 /* Bit 26 : Set as output pin 26 */ 08173 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 08174 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 08175 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */ 08176 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */ 08177 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08178 08179 /* Bit 25 : Set as output pin 25 */ 08180 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 08181 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 08182 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */ 08183 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */ 08184 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08185 08186 /* Bit 24 : Set as output pin 24 */ 08187 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 08188 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 08189 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */ 08190 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */ 08191 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08192 08193 /* Bit 23 : Set as output pin 23 */ 08194 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 08195 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 08196 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */ 08197 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */ 08198 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08199 08200 /* Bit 22 : Set as output pin 22 */ 08201 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 08202 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 08203 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */ 08204 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */ 08205 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08206 08207 /* Bit 21 : Set as output pin 21 */ 08208 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 08209 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 08210 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */ 08211 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */ 08212 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08213 08214 /* Bit 20 : Set as output pin 20 */ 08215 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 08216 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 08217 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */ 08218 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */ 08219 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08220 08221 /* Bit 19 : Set as output pin 19 */ 08222 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 08223 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 08224 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */ 08225 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */ 08226 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08227 08228 /* Bit 18 : Set as output pin 18 */ 08229 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 08230 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 08231 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */ 08232 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */ 08233 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08234 08235 /* Bit 17 : Set as output pin 17 */ 08236 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 08237 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 08238 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */ 08239 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */ 08240 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08241 08242 /* Bit 16 : Set as output pin 16 */ 08243 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 08244 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 08245 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */ 08246 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */ 08247 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08248 08249 /* Bit 15 : Set as output pin 15 */ 08250 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 08251 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 08252 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */ 08253 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */ 08254 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08255 08256 /* Bit 14 : Set as output pin 14 */ 08257 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 08258 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 08259 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */ 08260 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */ 08261 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08262 08263 /* Bit 13 : Set as output pin 13 */ 08264 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 08265 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 08266 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */ 08267 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */ 08268 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08269 08270 /* Bit 12 : Set as output pin 12 */ 08271 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 08272 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 08273 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */ 08274 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */ 08275 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08276 08277 /* Bit 11 : Set as output pin 11 */ 08278 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 08279 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 08280 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */ 08281 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */ 08282 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08283 08284 /* Bit 10 : Set as output pin 10 */ 08285 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 08286 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 08287 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */ 08288 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */ 08289 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08290 08291 /* Bit 9 : Set as output pin 9 */ 08292 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 08293 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 08294 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */ 08295 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */ 08296 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08297 08298 /* Bit 8 : Set as output pin 8 */ 08299 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 08300 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 08301 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */ 08302 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */ 08303 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08304 08305 /* Bit 7 : Set as output pin 7 */ 08306 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 08307 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 08308 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */ 08309 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */ 08310 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08311 08312 /* Bit 6 : Set as output pin 6 */ 08313 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 08314 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 08315 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */ 08316 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */ 08317 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08318 08319 /* Bit 5 : Set as output pin 5 */ 08320 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 08321 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 08322 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */ 08323 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */ 08324 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08325 08326 /* Bit 4 : Set as output pin 4 */ 08327 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 08328 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 08329 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */ 08330 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */ 08331 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08332 08333 /* Bit 3 : Set as output pin 3 */ 08334 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 08335 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 08336 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */ 08337 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */ 08338 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08339 08340 /* Bit 2 : Set as output pin 2 */ 08341 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 08342 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 08343 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */ 08344 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */ 08345 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08346 08347 /* Bit 1 : Set as output pin 1 */ 08348 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 08349 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 08350 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */ 08351 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */ 08352 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08353 08354 /* Bit 0 : Set as output pin 0 */ 08355 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 08356 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 08357 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */ 08358 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */ 08359 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */ 08360 08361 /* Register: GPIO_DIRCLR */ 08362 /* Description: DIR clear register */ 08363 08364 /* Bit 31 : Set as input pin 31 */ 08365 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 08366 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 08367 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */ 08368 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */ 08369 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08370 08371 /* Bit 30 : Set as input pin 30 */ 08372 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 08373 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 08374 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */ 08375 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */ 08376 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08377 08378 /* Bit 29 : Set as input pin 29 */ 08379 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 08380 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 08381 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */ 08382 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */ 08383 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08384 08385 /* Bit 28 : Set as input pin 28 */ 08386 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 08387 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 08388 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */ 08389 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */ 08390 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08391 08392 /* Bit 27 : Set as input pin 27 */ 08393 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 08394 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 08395 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */ 08396 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */ 08397 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08398 08399 /* Bit 26 : Set as input pin 26 */ 08400 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 08401 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 08402 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */ 08403 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */ 08404 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08405 08406 /* Bit 25 : Set as input pin 25 */ 08407 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 08408 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 08409 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */ 08410 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */ 08411 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08412 08413 /* Bit 24 : Set as input pin 24 */ 08414 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 08415 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 08416 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */ 08417 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */ 08418 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08419 08420 /* Bit 23 : Set as input pin 23 */ 08421 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 08422 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 08423 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */ 08424 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */ 08425 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08426 08427 /* Bit 22 : Set as input pin 22 */ 08428 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 08429 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 08430 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */ 08431 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */ 08432 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08433 08434 /* Bit 21 : Set as input pin 21 */ 08435 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 08436 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 08437 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */ 08438 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */ 08439 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08440 08441 /* Bit 20 : Set as input pin 20 */ 08442 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 08443 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 08444 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */ 08445 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */ 08446 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08447 08448 /* Bit 19 : Set as input pin 19 */ 08449 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 08450 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 08451 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */ 08452 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */ 08453 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08454 08455 /* Bit 18 : Set as input pin 18 */ 08456 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 08457 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 08458 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */ 08459 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */ 08460 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08461 08462 /* Bit 17 : Set as input pin 17 */ 08463 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 08464 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 08465 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */ 08466 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */ 08467 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08468 08469 /* Bit 16 : Set as input pin 16 */ 08470 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 08471 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 08472 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */ 08473 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */ 08474 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08475 08476 /* Bit 15 : Set as input pin 15 */ 08477 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 08478 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 08479 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */ 08480 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */ 08481 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08482 08483 /* Bit 14 : Set as input pin 14 */ 08484 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 08485 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 08486 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */ 08487 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */ 08488 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08489 08490 /* Bit 13 : Set as input pin 13 */ 08491 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 08492 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 08493 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */ 08494 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */ 08495 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08496 08497 /* Bit 12 : Set as input pin 12 */ 08498 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 08499 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 08500 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */ 08501 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */ 08502 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08503 08504 /* Bit 11 : Set as input pin 11 */ 08505 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 08506 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 08507 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */ 08508 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */ 08509 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08510 08511 /* Bit 10 : Set as input pin 10 */ 08512 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 08513 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 08514 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */ 08515 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */ 08516 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08517 08518 /* Bit 9 : Set as input pin 9 */ 08519 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 08520 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 08521 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */ 08522 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */ 08523 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08524 08525 /* Bit 8 : Set as input pin 8 */ 08526 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 08527 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 08528 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */ 08529 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */ 08530 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08531 08532 /* Bit 7 : Set as input pin 7 */ 08533 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 08534 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 08535 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */ 08536 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */ 08537 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08538 08539 /* Bit 6 : Set as input pin 6 */ 08540 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 08541 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 08542 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */ 08543 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */ 08544 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08545 08546 /* Bit 5 : Set as input pin 5 */ 08547 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 08548 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 08549 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */ 08550 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */ 08551 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08552 08553 /* Bit 4 : Set as input pin 4 */ 08554 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 08555 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 08556 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */ 08557 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */ 08558 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08559 08560 /* Bit 3 : Set as input pin 3 */ 08561 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 08562 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 08563 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */ 08564 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */ 08565 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08566 08567 /* Bit 2 : Set as input pin 2 */ 08568 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 08569 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 08570 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */ 08571 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */ 08572 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08573 08574 /* Bit 1 : Set as input pin 1 */ 08575 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 08576 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 08577 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */ 08578 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */ 08579 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08580 08581 /* Bit 0 : Set as input pin 0 */ 08582 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 08583 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 08584 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */ 08585 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */ 08586 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */ 08587 08588 /* Register: GPIO_LATCH */ 08589 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */ 08590 08591 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */ 08592 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 08593 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 08594 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */ 08595 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */ 08596 08597 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */ 08598 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 08599 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 08600 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */ 08601 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */ 08602 08603 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */ 08604 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 08605 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 08606 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */ 08607 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */ 08608 08609 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */ 08610 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 08611 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 08612 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */ 08613 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */ 08614 08615 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */ 08616 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 08617 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 08618 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */ 08619 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */ 08620 08621 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */ 08622 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 08623 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 08624 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */ 08625 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */ 08626 08627 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */ 08628 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 08629 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 08630 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */ 08631 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */ 08632 08633 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */ 08634 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 08635 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 08636 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */ 08637 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */ 08638 08639 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */ 08640 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 08641 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 08642 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */ 08643 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */ 08644 08645 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */ 08646 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 08647 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 08648 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */ 08649 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */ 08650 08651 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */ 08652 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 08653 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 08654 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */ 08655 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */ 08656 08657 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */ 08658 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 08659 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 08660 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */ 08661 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */ 08662 08663 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */ 08664 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 08665 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 08666 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */ 08667 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */ 08668 08669 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */ 08670 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 08671 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 08672 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */ 08673 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */ 08674 08675 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */ 08676 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 08677 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 08678 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */ 08679 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */ 08680 08681 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */ 08682 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 08683 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 08684 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */ 08685 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */ 08686 08687 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */ 08688 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 08689 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 08690 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */ 08691 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */ 08692 08693 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */ 08694 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 08695 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 08696 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */ 08697 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */ 08698 08699 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */ 08700 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 08701 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 08702 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */ 08703 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */ 08704 08705 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */ 08706 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 08707 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 08708 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */ 08709 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */ 08710 08711 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */ 08712 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 08713 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 08714 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */ 08715 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */ 08716 08717 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */ 08718 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 08719 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 08720 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */ 08721 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */ 08722 08723 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */ 08724 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 08725 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 08726 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */ 08727 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */ 08728 08729 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */ 08730 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 08731 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 08732 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */ 08733 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */ 08734 08735 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */ 08736 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 08737 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 08738 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */ 08739 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */ 08740 08741 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */ 08742 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 08743 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 08744 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */ 08745 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */ 08746 08747 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */ 08748 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 08749 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 08750 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */ 08751 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */ 08752 08753 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */ 08754 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 08755 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 08756 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */ 08757 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */ 08758 08759 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */ 08760 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 08761 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 08762 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */ 08763 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */ 08764 08765 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */ 08766 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 08767 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 08768 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */ 08769 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */ 08770 08771 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */ 08772 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 08773 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 08774 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */ 08775 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */ 08776 08777 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */ 08778 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 08779 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 08780 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */ 08781 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */ 08782 08783 /* Register: GPIO_DETECTMODE */ 08784 /* Description: Select between default DETECT signal behaviour and LDETECT mode */ 08785 08786 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */ 08787 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */ 08788 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */ 08789 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */ 08790 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */ 08791 08792 /* Register: GPIO_PIN_CNF */ 08793 /* Description: Description collection[0]: Configuration of GPIO pins */ 08794 08795 /* Bits 17..16 : Pin sensing mechanism */ 08796 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ 08797 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ 08798 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */ 08799 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */ 08800 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */ 08801 08802 /* Bits 10..8 : Drive configuration */ 08803 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ 08804 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ 08805 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */ 08806 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */ 08807 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */ 08808 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */ 08809 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */ 08810 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */ 08811 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */ 08812 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */ 08813 08814 /* Bits 3..2 : Pull configuration */ 08815 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ 08816 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ 08817 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */ 08818 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */ 08819 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */ 08820 08821 /* Bit 1 : Connect or disconnect input buffer */ 08822 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ 08823 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ 08824 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */ 08825 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */ 08826 08827 /* Bit 0 : Pin direction. Same physical register as DIR register */ 08828 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ 08829 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ 08830 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */ 08831 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */ 08832 08833 08834 /* Peripheral: PDM */ 08835 /* Description: Pulse Density Modulation (Digital Microphone) Interface */ 08836 08837 /* Register: PDM_INTEN */ 08838 /* Description: Enable or disable interrupt */ 08839 08840 /* Bit 2 : Enable or disable interrupt for END event */ 08841 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */ 08842 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */ 08843 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */ 08844 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */ 08845 08846 /* Bit 1 : Enable or disable interrupt for STOPPED event */ 08847 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 08848 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 08849 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 08850 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 08851 08852 /* Bit 0 : Enable or disable interrupt for STARTED event */ 08853 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 08854 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 08855 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */ 08856 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */ 08857 08858 /* Register: PDM_INTENSET */ 08859 /* Description: Enable interrupt */ 08860 08861 /* Bit 2 : Write '1' to Enable interrupt for END event */ 08862 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */ 08863 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 08864 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 08865 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 08866 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */ 08867 08868 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ 08869 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 08870 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 08871 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 08872 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 08873 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 08874 08875 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */ 08876 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 08877 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 08878 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 08879 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 08880 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */ 08881 08882 /* Register: PDM_INTENCLR */ 08883 /* Description: Disable interrupt */ 08884 08885 /* Bit 2 : Write '1' to Disable interrupt for END event */ 08886 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */ 08887 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 08888 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 08889 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 08890 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */ 08891 08892 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ 08893 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 08894 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 08895 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 08896 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 08897 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 08898 08899 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */ 08900 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 08901 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 08902 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 08903 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 08904 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 08905 08906 /* Register: PDM_ENABLE */ 08907 /* Description: PDM module enable register */ 08908 08909 /* Bit 0 : Enable or disable PDM module */ 08910 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 08911 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 08912 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 08913 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 08914 08915 /* Register: PDM_PDMCLKCTRL */ 08916 /* Description: PDM clock generator control */ 08917 08918 /* Bits 31..0 : PDM_CLK frequency */ 08919 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */ 08920 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */ 08921 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */ 08922 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */ 08923 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */ 08924 08925 /* Register: PDM_MODE */ 08926 /* Description: Defines the routing of the connected PDM microphones' signals */ 08927 08928 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */ 08929 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */ 08930 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */ 08931 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */ 08932 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */ 08933 08934 /* Bit 0 : Mono or stereo operation */ 08935 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */ 08936 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */ 08937 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */ 08938 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */ 08939 08940 /* Register: PDM_GAINL */ 08941 /* Description: Left output gain adjustment */ 08942 08943 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */ 08944 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */ 08945 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */ 08946 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ 08947 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ 08948 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ 08949 08950 /* Register: PDM_GAINR */ 08951 /* Description: Right output gain adjustment */ 08952 08953 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */ 08954 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */ 08955 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */ 08956 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */ 08957 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */ 08958 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */ 08959 08960 /* Register: PDM_PSEL_CLK */ 08961 /* Description: Pin number configuration for PDM CLK signal */ 08962 08963 /* Bit 31 : Connection */ 08964 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 08965 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 08966 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */ 08967 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 08968 08969 /* Bits 4..0 : Pin number */ 08970 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */ 08971 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */ 08972 08973 /* Register: PDM_PSEL_DIN */ 08974 /* Description: Pin number configuration for PDM DIN signal */ 08975 08976 /* Bit 31 : Connection */ 08977 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 08978 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 08979 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */ 08980 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 08981 08982 /* Bits 4..0 : Pin number */ 08983 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */ 08984 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */ 08985 08986 /* Register: PDM_SAMPLE_PTR */ 08987 /* Description: RAM address pointer to write samples to with EasyDMA */ 08988 08989 /* Bits 31..0 : Address to write PDM samples to over DMA */ 08990 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */ 08991 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */ 08992 08993 /* Register: PDM_SAMPLE_MAXCNT */ 08994 /* Description: Number of samples to allocate memory for in EasyDMA mode */ 08995 08996 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */ 08997 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */ 08998 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */ 08999 09000 09001 /* Peripheral: POWER */ 09002 /* Description: Power control */ 09003 09004 /* Register: POWER_INTENSET */ 09005 /* Description: Enable interrupt */ 09006 09007 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */ 09008 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 09009 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 09010 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ 09011 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ 09012 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */ 09013 09014 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */ 09015 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 09016 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 09017 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ 09018 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ 09019 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */ 09020 09021 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */ 09022 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 09023 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 09024 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */ 09025 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */ 09026 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */ 09027 09028 /* Register: POWER_INTENCLR */ 09029 /* Description: Disable interrupt */ 09030 09031 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */ 09032 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */ 09033 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */ 09034 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */ 09035 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */ 09036 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */ 09037 09038 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */ 09039 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */ 09040 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */ 09041 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */ 09042 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */ 09043 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */ 09044 09045 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */ 09046 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 09047 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 09048 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */ 09049 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */ 09050 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */ 09051 09052 /* Register: POWER_RESETREAS */ 09053 /* Description: Reset reason */ 09054 09055 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */ 09056 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */ 09057 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */ 09058 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */ 09059 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */ 09060 09061 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */ 09062 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ 09063 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ 09064 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */ 09065 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */ 09066 09067 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */ 09068 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ 09069 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ 09070 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */ 09071 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */ 09072 09073 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */ 09074 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ 09075 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ 09076 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */ 09077 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */ 09078 09079 /* Bit 3 : Reset from CPU lock-up detected */ 09080 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ 09081 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ 09082 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */ 09083 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */ 09084 09085 /* Bit 2 : Reset from soft reset detected */ 09086 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ 09087 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ 09088 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */ 09089 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */ 09090 09091 /* Bit 1 : Reset from watchdog detected */ 09092 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ 09093 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ 09094 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */ 09095 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */ 09096 09097 /* Bit 0 : Reset from pin-reset detected */ 09098 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ 09099 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ 09100 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */ 09101 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */ 09102 09103 /* Register: POWER_RAMSTATUS */ 09104 /* Description: Deprecated register - RAM status register */ 09105 09106 /* Bit 3 : RAM block 3 is on or off/powering up */ 09107 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ 09108 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ 09109 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */ 09110 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */ 09111 09112 /* Bit 2 : RAM block 2 is on or off/powering up */ 09113 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ 09114 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ 09115 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */ 09116 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */ 09117 09118 /* Bit 1 : RAM block 1 is on or off/powering up */ 09119 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ 09120 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ 09121 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */ 09122 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */ 09123 09124 /* Bit 0 : RAM block 0 is on or off/powering up */ 09125 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ 09126 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ 09127 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */ 09128 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */ 09129 09130 /* Register: POWER_SYSTEMOFF */ 09131 /* Description: System OFF register */ 09132 09133 /* Bit 0 : Enable System OFF mode */ 09134 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ 09135 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ 09136 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */ 09137 09138 /* Register: POWER_POFCON */ 09139 /* Description: Power failure comparator configuration */ 09140 09141 /* Bits 4..1 : Power failure comparator threshold setting */ 09142 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ 09143 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ 09144 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */ 09145 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */ 09146 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */ 09147 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */ 09148 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */ 09149 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */ 09150 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */ 09151 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */ 09152 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */ 09153 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */ 09154 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */ 09155 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */ 09156 09157 /* Bit 0 : Enable or disable power failure comparator */ 09158 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ 09159 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ 09160 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */ 09161 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */ 09162 09163 /* Register: POWER_GPREGRET */ 09164 /* Description: General purpose retention register */ 09165 09166 /* Bits 7..0 : General purpose retention register */ 09167 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 09168 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 09169 09170 /* Register: POWER_GPREGRET2 */ 09171 /* Description: General purpose retention register */ 09172 09173 /* Bits 7..0 : General purpose retention register */ 09174 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 09175 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 09176 09177 /* Register: POWER_RAMON */ 09178 /* Description: Deprecated register - RAM on/off register (this register is retained) */ 09179 09180 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */ 09181 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ 09182 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ 09183 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */ 09184 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */ 09185 09186 /* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */ 09187 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ 09188 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ 09189 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */ 09190 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */ 09191 09192 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */ 09193 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ 09194 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ 09195 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */ 09196 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */ 09197 09198 /* Bit 0 : Keep RAM block 0 on or off in system ON Mode */ 09199 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ 09200 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ 09201 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */ 09202 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */ 09203 09204 /* Register: POWER_RAMONB */ 09205 /* Description: Deprecated register - RAM on/off register (this register is retained) */ 09206 09207 /* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */ 09208 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ 09209 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ 09210 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */ 09211 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */ 09212 09213 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */ 09214 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ 09215 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ 09216 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */ 09217 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */ 09218 09219 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */ 09220 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ 09221 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ 09222 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */ 09223 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */ 09224 09225 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */ 09226 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ 09227 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ 09228 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */ 09229 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */ 09230 09231 /* Register: POWER_DCDCEN */ 09232 /* Description: DC/DC enable register */ 09233 09234 /* Bit 0 : Enable or disable DC/DC converter */ 09235 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ 09236 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ 09237 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */ 09238 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */ 09239 09240 /* Register: POWER_RAM_POWER */ 09241 /* Description: Description cluster[0]: RAM0 power control register */ 09242 09243 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */ 09244 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 09245 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 09246 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */ 09247 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */ 09248 09249 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */ 09250 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 09251 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 09252 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */ 09253 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */ 09254 09255 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */ 09256 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 09257 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 09258 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */ 09259 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */ 09260 09261 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */ 09262 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 09263 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 09264 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */ 09265 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */ 09266 09267 /* Register: POWER_RAM_POWERSET */ 09268 /* Description: Description cluster[0]: RAM0 power control set register */ 09269 09270 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ 09271 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 09272 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 09273 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */ 09274 09275 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ 09276 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 09277 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 09278 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */ 09279 09280 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ 09281 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 09282 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 09283 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */ 09284 09285 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ 09286 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 09287 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 09288 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */ 09289 09290 /* Register: POWER_RAM_POWERCLR */ 09291 /* Description: Description cluster[0]: RAM0 power control clear register */ 09292 09293 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */ 09294 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */ 09295 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */ 09296 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */ 09297 09298 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */ 09299 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */ 09300 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */ 09301 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */ 09302 09303 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */ 09304 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */ 09305 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */ 09306 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */ 09307 09308 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */ 09309 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */ 09310 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */ 09311 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */ 09312 09313 09314 /* Peripheral: PPI */ 09315 /* Description: Programmable Peripheral Interconnect */ 09316 09317 /* Register: PPI_CHEN */ 09318 /* Description: Channel enable register */ 09319 09320 /* Bit 31 : Enable or disable channel 31 */ 09321 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ 09322 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ 09323 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */ 09324 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */ 09325 09326 /* Bit 30 : Enable or disable channel 30 */ 09327 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ 09328 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ 09329 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */ 09330 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */ 09331 09332 /* Bit 29 : Enable or disable channel 29 */ 09333 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ 09334 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ 09335 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */ 09336 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */ 09337 09338 /* Bit 28 : Enable or disable channel 28 */ 09339 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ 09340 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ 09341 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */ 09342 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */ 09343 09344 /* Bit 27 : Enable or disable channel 27 */ 09345 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ 09346 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ 09347 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */ 09348 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */ 09349 09350 /* Bit 26 : Enable or disable channel 26 */ 09351 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ 09352 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ 09353 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */ 09354 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */ 09355 09356 /* Bit 25 : Enable or disable channel 25 */ 09357 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ 09358 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ 09359 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */ 09360 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */ 09361 09362 /* Bit 24 : Enable or disable channel 24 */ 09363 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ 09364 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ 09365 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */ 09366 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */ 09367 09368 /* Bit 23 : Enable or disable channel 23 */ 09369 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ 09370 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ 09371 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */ 09372 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */ 09373 09374 /* Bit 22 : Enable or disable channel 22 */ 09375 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ 09376 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ 09377 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */ 09378 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */ 09379 09380 /* Bit 21 : Enable or disable channel 21 */ 09381 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ 09382 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ 09383 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */ 09384 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */ 09385 09386 /* Bit 20 : Enable or disable channel 20 */ 09387 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ 09388 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ 09389 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */ 09390 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */ 09391 09392 /* Bit 19 : Enable or disable channel 19 */ 09393 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */ 09394 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */ 09395 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */ 09396 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */ 09397 09398 /* Bit 18 : Enable or disable channel 18 */ 09399 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */ 09400 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */ 09401 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */ 09402 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */ 09403 09404 /* Bit 17 : Enable or disable channel 17 */ 09405 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */ 09406 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */ 09407 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */ 09408 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */ 09409 09410 /* Bit 16 : Enable or disable channel 16 */ 09411 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */ 09412 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */ 09413 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */ 09414 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */ 09415 09416 /* Bit 15 : Enable or disable channel 15 */ 09417 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ 09418 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ 09419 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */ 09420 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */ 09421 09422 /* Bit 14 : Enable or disable channel 14 */ 09423 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ 09424 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ 09425 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */ 09426 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */ 09427 09428 /* Bit 13 : Enable or disable channel 13 */ 09429 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ 09430 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ 09431 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */ 09432 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */ 09433 09434 /* Bit 12 : Enable or disable channel 12 */ 09435 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ 09436 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ 09437 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */ 09438 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */ 09439 09440 /* Bit 11 : Enable or disable channel 11 */ 09441 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ 09442 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ 09443 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */ 09444 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */ 09445 09446 /* Bit 10 : Enable or disable channel 10 */ 09447 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ 09448 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ 09449 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */ 09450 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */ 09451 09452 /* Bit 9 : Enable or disable channel 9 */ 09453 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ 09454 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ 09455 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */ 09456 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */ 09457 09458 /* Bit 8 : Enable or disable channel 8 */ 09459 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ 09460 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ 09461 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */ 09462 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */ 09463 09464 /* Bit 7 : Enable or disable channel 7 */ 09465 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ 09466 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ 09467 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */ 09468 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */ 09469 09470 /* Bit 6 : Enable or disable channel 6 */ 09471 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ 09472 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ 09473 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */ 09474 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */ 09475 09476 /* Bit 5 : Enable or disable channel 5 */ 09477 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ 09478 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ 09479 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */ 09480 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */ 09481 09482 /* Bit 4 : Enable or disable channel 4 */ 09483 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ 09484 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ 09485 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */ 09486 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */ 09487 09488 /* Bit 3 : Enable or disable channel 3 */ 09489 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ 09490 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ 09491 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */ 09492 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */ 09493 09494 /* Bit 2 : Enable or disable channel 2 */ 09495 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ 09496 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ 09497 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */ 09498 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */ 09499 09500 /* Bit 1 : Enable or disable channel 1 */ 09501 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ 09502 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ 09503 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */ 09504 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */ 09505 09506 /* Bit 0 : Enable or disable channel 0 */ 09507 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 09508 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 09509 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */ 09510 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */ 09511 09512 /* Register: PPI_CHENSET */ 09513 /* Description: Channel enable set register */ 09514 09515 /* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */ 09516 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ 09517 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ 09518 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */ 09519 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */ 09520 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */ 09521 09522 /* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */ 09523 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ 09524 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ 09525 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */ 09526 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */ 09527 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */ 09528 09529 /* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */ 09530 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ 09531 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ 09532 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */ 09533 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */ 09534 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */ 09535 09536 /* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */ 09537 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ 09538 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ 09539 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */ 09540 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */ 09541 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */ 09542 09543 /* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */ 09544 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ 09545 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ 09546 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */ 09547 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */ 09548 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */ 09549 09550 /* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */ 09551 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ 09552 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ 09553 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */ 09554 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */ 09555 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */ 09556 09557 /* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */ 09558 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ 09559 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ 09560 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */ 09561 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */ 09562 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */ 09563 09564 /* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */ 09565 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ 09566 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ 09567 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */ 09568 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */ 09569 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */ 09570 09571 /* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */ 09572 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ 09573 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ 09574 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */ 09575 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */ 09576 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */ 09577 09578 /* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */ 09579 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ 09580 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ 09581 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */ 09582 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */ 09583 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */ 09584 09585 /* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */ 09586 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ 09587 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ 09588 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */ 09589 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */ 09590 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */ 09591 09592 /* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */ 09593 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ 09594 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ 09595 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */ 09596 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */ 09597 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */ 09598 09599 /* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */ 09600 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */ 09601 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */ 09602 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */ 09603 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */ 09604 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */ 09605 09606 /* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */ 09607 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */ 09608 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */ 09609 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */ 09610 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */ 09611 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */ 09612 09613 /* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */ 09614 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */ 09615 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */ 09616 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */ 09617 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */ 09618 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */ 09619 09620 /* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */ 09621 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */ 09622 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */ 09623 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */ 09624 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */ 09625 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */ 09626 09627 /* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */ 09628 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ 09629 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ 09630 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */ 09631 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */ 09632 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */ 09633 09634 /* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */ 09635 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ 09636 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ 09637 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */ 09638 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */ 09639 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */ 09640 09641 /* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */ 09642 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ 09643 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ 09644 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */ 09645 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */ 09646 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */ 09647 09648 /* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */ 09649 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ 09650 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ 09651 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */ 09652 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */ 09653 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */ 09654 09655 /* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */ 09656 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ 09657 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ 09658 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */ 09659 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */ 09660 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */ 09661 09662 /* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */ 09663 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ 09664 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ 09665 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */ 09666 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */ 09667 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */ 09668 09669 /* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */ 09670 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ 09671 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ 09672 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */ 09673 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */ 09674 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */ 09675 09676 /* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */ 09677 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ 09678 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ 09679 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */ 09680 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */ 09681 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */ 09682 09683 /* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */ 09684 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ 09685 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ 09686 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */ 09687 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */ 09688 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */ 09689 09690 /* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */ 09691 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ 09692 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ 09693 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */ 09694 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */ 09695 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */ 09696 09697 /* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */ 09698 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ 09699 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ 09700 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */ 09701 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */ 09702 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */ 09703 09704 /* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */ 09705 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ 09706 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ 09707 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */ 09708 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */ 09709 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */ 09710 09711 /* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */ 09712 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ 09713 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ 09714 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */ 09715 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */ 09716 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */ 09717 09718 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */ 09719 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ 09720 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ 09721 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */ 09722 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */ 09723 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */ 09724 09725 /* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */ 09726 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ 09727 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ 09728 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */ 09729 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */ 09730 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */ 09731 09732 /* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */ 09733 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 09734 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 09735 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */ 09736 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */ 09737 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */ 09738 09739 /* Register: PPI_CHENCLR */ 09740 /* Description: Channel enable clear register */ 09741 09742 /* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */ 09743 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ 09744 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ 09745 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */ 09746 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */ 09747 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */ 09748 09749 /* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */ 09750 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ 09751 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ 09752 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */ 09753 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */ 09754 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */ 09755 09756 /* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */ 09757 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ 09758 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ 09759 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */ 09760 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */ 09761 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */ 09762 09763 /* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */ 09764 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ 09765 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ 09766 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */ 09767 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */ 09768 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */ 09769 09770 /* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */ 09771 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ 09772 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ 09773 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */ 09774 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */ 09775 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */ 09776 09777 /* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */ 09778 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ 09779 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ 09780 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */ 09781 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */ 09782 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */ 09783 09784 /* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */ 09785 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ 09786 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ 09787 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */ 09788 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */ 09789 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */ 09790 09791 /* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */ 09792 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ 09793 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ 09794 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */ 09795 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */ 09796 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */ 09797 09798 /* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */ 09799 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ 09800 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ 09801 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */ 09802 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */ 09803 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */ 09804 09805 /* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */ 09806 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ 09807 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ 09808 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */ 09809 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */ 09810 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */ 09811 09812 /* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */ 09813 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ 09814 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ 09815 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */ 09816 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */ 09817 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */ 09818 09819 /* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */ 09820 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ 09821 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ 09822 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */ 09823 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */ 09824 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */ 09825 09826 /* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */ 09827 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */ 09828 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */ 09829 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */ 09830 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */ 09831 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */ 09832 09833 /* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */ 09834 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */ 09835 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */ 09836 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */ 09837 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */ 09838 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */ 09839 09840 /* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */ 09841 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */ 09842 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */ 09843 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */ 09844 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */ 09845 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */ 09846 09847 /* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */ 09848 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */ 09849 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */ 09850 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */ 09851 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */ 09852 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */ 09853 09854 /* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */ 09855 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ 09856 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ 09857 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */ 09858 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */ 09859 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */ 09860 09861 /* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */ 09862 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ 09863 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ 09864 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */ 09865 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */ 09866 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */ 09867 09868 /* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */ 09869 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ 09870 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ 09871 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */ 09872 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */ 09873 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */ 09874 09875 /* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */ 09876 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ 09877 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ 09878 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */ 09879 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */ 09880 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */ 09881 09882 /* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */ 09883 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ 09884 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ 09885 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */ 09886 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */ 09887 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */ 09888 09889 /* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */ 09890 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ 09891 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ 09892 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */ 09893 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */ 09894 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */ 09895 09896 /* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */ 09897 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ 09898 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ 09899 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */ 09900 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */ 09901 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */ 09902 09903 /* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */ 09904 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ 09905 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ 09906 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */ 09907 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */ 09908 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */ 09909 09910 /* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */ 09911 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ 09912 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ 09913 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */ 09914 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */ 09915 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */ 09916 09917 /* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */ 09918 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ 09919 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ 09920 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */ 09921 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */ 09922 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */ 09923 09924 /* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */ 09925 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ 09926 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ 09927 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */ 09928 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */ 09929 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */ 09930 09931 /* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */ 09932 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ 09933 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ 09934 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */ 09935 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */ 09936 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */ 09937 09938 /* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */ 09939 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ 09940 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ 09941 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */ 09942 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */ 09943 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */ 09944 09945 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */ 09946 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ 09947 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ 09948 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */ 09949 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */ 09950 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */ 09951 09952 /* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */ 09953 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ 09954 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ 09955 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */ 09956 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */ 09957 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */ 09958 09959 /* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */ 09960 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 09961 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 09962 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */ 09963 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */ 09964 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */ 09965 09966 /* Register: PPI_CH_EEP */ 09967 /* Description: Description cluster[0]: Channel 0 event end-point */ 09968 09969 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */ 09970 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */ 09971 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */ 09972 09973 /* Register: PPI_CH_TEP */ 09974 /* Description: Description cluster[0]: Channel 0 task end-point */ 09975 09976 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */ 09977 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ 09978 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ 09979 09980 /* Register: PPI_CHG */ 09981 /* Description: Description collection[0]: Channel group 0 */ 09982 09983 /* Bit 31 : Include or exclude channel 31 */ 09984 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ 09985 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ 09986 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */ 09987 #define PPI_CHG_CH31_Included (1UL) /*!< Include */ 09988 09989 /* Bit 30 : Include or exclude channel 30 */ 09990 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ 09991 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ 09992 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */ 09993 #define PPI_CHG_CH30_Included (1UL) /*!< Include */ 09994 09995 /* Bit 29 : Include or exclude channel 29 */ 09996 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ 09997 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ 09998 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */ 09999 #define PPI_CHG_CH29_Included (1UL) /*!< Include */ 10000 10001 /* Bit 28 : Include or exclude channel 28 */ 10002 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ 10003 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ 10004 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */ 10005 #define PPI_CHG_CH28_Included (1UL) /*!< Include */ 10006 10007 /* Bit 27 : Include or exclude channel 27 */ 10008 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ 10009 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ 10010 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */ 10011 #define PPI_CHG_CH27_Included (1UL) /*!< Include */ 10012 10013 /* Bit 26 : Include or exclude channel 26 */ 10014 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ 10015 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ 10016 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */ 10017 #define PPI_CHG_CH26_Included (1UL) /*!< Include */ 10018 10019 /* Bit 25 : Include or exclude channel 25 */ 10020 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ 10021 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ 10022 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */ 10023 #define PPI_CHG_CH25_Included (1UL) /*!< Include */ 10024 10025 /* Bit 24 : Include or exclude channel 24 */ 10026 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ 10027 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ 10028 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */ 10029 #define PPI_CHG_CH24_Included (1UL) /*!< Include */ 10030 10031 /* Bit 23 : Include or exclude channel 23 */ 10032 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ 10033 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ 10034 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */ 10035 #define PPI_CHG_CH23_Included (1UL) /*!< Include */ 10036 10037 /* Bit 22 : Include or exclude channel 22 */ 10038 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ 10039 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ 10040 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */ 10041 #define PPI_CHG_CH22_Included (1UL) /*!< Include */ 10042 10043 /* Bit 21 : Include or exclude channel 21 */ 10044 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ 10045 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ 10046 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */ 10047 #define PPI_CHG_CH21_Included (1UL) /*!< Include */ 10048 10049 /* Bit 20 : Include or exclude channel 20 */ 10050 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ 10051 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ 10052 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */ 10053 #define PPI_CHG_CH20_Included (1UL) /*!< Include */ 10054 10055 /* Bit 19 : Include or exclude channel 19 */ 10056 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */ 10057 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */ 10058 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */ 10059 #define PPI_CHG_CH19_Included (1UL) /*!< Include */ 10060 10061 /* Bit 18 : Include or exclude channel 18 */ 10062 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */ 10063 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */ 10064 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */ 10065 #define PPI_CHG_CH18_Included (1UL) /*!< Include */ 10066 10067 /* Bit 17 : Include or exclude channel 17 */ 10068 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */ 10069 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */ 10070 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */ 10071 #define PPI_CHG_CH17_Included (1UL) /*!< Include */ 10072 10073 /* Bit 16 : Include or exclude channel 16 */ 10074 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */ 10075 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */ 10076 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */ 10077 #define PPI_CHG_CH16_Included (1UL) /*!< Include */ 10078 10079 /* Bit 15 : Include or exclude channel 15 */ 10080 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ 10081 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ 10082 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */ 10083 #define PPI_CHG_CH15_Included (1UL) /*!< Include */ 10084 10085 /* Bit 14 : Include or exclude channel 14 */ 10086 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ 10087 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ 10088 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */ 10089 #define PPI_CHG_CH14_Included (1UL) /*!< Include */ 10090 10091 /* Bit 13 : Include or exclude channel 13 */ 10092 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ 10093 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ 10094 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */ 10095 #define PPI_CHG_CH13_Included (1UL) /*!< Include */ 10096 10097 /* Bit 12 : Include or exclude channel 12 */ 10098 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ 10099 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ 10100 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */ 10101 #define PPI_CHG_CH12_Included (1UL) /*!< Include */ 10102 10103 /* Bit 11 : Include or exclude channel 11 */ 10104 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ 10105 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ 10106 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */ 10107 #define PPI_CHG_CH11_Included (1UL) /*!< Include */ 10108 10109 /* Bit 10 : Include or exclude channel 10 */ 10110 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ 10111 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ 10112 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */ 10113 #define PPI_CHG_CH10_Included (1UL) /*!< Include */ 10114 10115 /* Bit 9 : Include or exclude channel 9 */ 10116 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ 10117 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ 10118 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */ 10119 #define PPI_CHG_CH9_Included (1UL) /*!< Include */ 10120 10121 /* Bit 8 : Include or exclude channel 8 */ 10122 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ 10123 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ 10124 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */ 10125 #define PPI_CHG_CH8_Included (1UL) /*!< Include */ 10126 10127 /* Bit 7 : Include or exclude channel 7 */ 10128 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ 10129 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ 10130 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */ 10131 #define PPI_CHG_CH7_Included (1UL) /*!< Include */ 10132 10133 /* Bit 6 : Include or exclude channel 6 */ 10134 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ 10135 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ 10136 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */ 10137 #define PPI_CHG_CH6_Included (1UL) /*!< Include */ 10138 10139 /* Bit 5 : Include or exclude channel 5 */ 10140 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ 10141 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ 10142 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */ 10143 #define PPI_CHG_CH5_Included (1UL) /*!< Include */ 10144 10145 /* Bit 4 : Include or exclude channel 4 */ 10146 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ 10147 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ 10148 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */ 10149 #define PPI_CHG_CH4_Included (1UL) /*!< Include */ 10150 10151 /* Bit 3 : Include or exclude channel 3 */ 10152 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ 10153 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ 10154 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */ 10155 #define PPI_CHG_CH3_Included (1UL) /*!< Include */ 10156 10157 /* Bit 2 : Include or exclude channel 2 */ 10158 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ 10159 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ 10160 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */ 10161 #define PPI_CHG_CH2_Included (1UL) /*!< Include */ 10162 10163 /* Bit 1 : Include or exclude channel 1 */ 10164 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ 10165 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ 10166 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */ 10167 #define PPI_CHG_CH1_Included (1UL) /*!< Include */ 10168 10169 /* Bit 0 : Include or exclude channel 0 */ 10170 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 10171 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 10172 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */ 10173 #define PPI_CHG_CH0_Included (1UL) /*!< Include */ 10174 10175 /* Register: PPI_FORK_TEP */ 10176 /* Description: Description cluster[0]: Channel 0 task end-point */ 10177 10178 /* Bits 31..0 : Pointer to task register */ 10179 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */ 10180 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */ 10181 10182 10183 /* Peripheral: PWM */ 10184 /* Description: Pulse Width Modulation Unit 0 */ 10185 10186 /* Register: PWM_SHORTS */ 10187 /* Description: Shortcut register */ 10188 10189 /* Bit 4 : Shortcut between LOOPSDONE event and STOP task */ 10190 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */ 10191 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */ 10192 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */ 10193 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */ 10194 10195 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */ 10196 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */ 10197 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */ 10198 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */ 10199 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */ 10200 10201 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */ 10202 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */ 10203 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */ 10204 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */ 10205 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */ 10206 10207 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */ 10208 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */ 10209 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */ 10210 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */ 10211 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */ 10212 10213 /* Bit 0 : Shortcut between SEQEND[0] event and STOP task */ 10214 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */ 10215 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */ 10216 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */ 10217 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */ 10218 10219 /* Register: PWM_INTEN */ 10220 /* Description: Enable or disable interrupt */ 10221 10222 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */ 10223 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 10224 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 10225 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */ 10226 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */ 10227 10228 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */ 10229 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 10230 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 10231 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */ 10232 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */ 10233 10234 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */ 10235 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 10236 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 10237 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */ 10238 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */ 10239 10240 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */ 10241 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 10242 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 10243 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */ 10244 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */ 10245 10246 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */ 10247 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 10248 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 10249 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */ 10250 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */ 10251 10252 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */ 10253 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 10254 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 10255 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */ 10256 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */ 10257 10258 /* Bit 1 : Enable or disable interrupt for STOPPED event */ 10259 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 10260 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 10261 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 10262 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 10263 10264 /* Register: PWM_INTENSET */ 10265 /* Description: Enable interrupt */ 10266 10267 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */ 10268 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 10269 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 10270 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ 10271 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ 10272 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */ 10273 10274 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */ 10275 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 10276 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 10277 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ 10278 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ 10279 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */ 10280 10281 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */ 10282 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 10283 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 10284 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ 10285 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ 10286 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */ 10287 10288 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */ 10289 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 10290 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 10291 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ 10292 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ 10293 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */ 10294 10295 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */ 10296 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 10297 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 10298 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ 10299 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ 10300 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */ 10301 10302 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */ 10303 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 10304 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 10305 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ 10306 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ 10307 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */ 10308 10309 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ 10310 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 10311 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 10312 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 10313 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 10314 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 10315 10316 /* Register: PWM_INTENCLR */ 10317 /* Description: Disable interrupt */ 10318 10319 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */ 10320 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */ 10321 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */ 10322 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */ 10323 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */ 10324 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */ 10325 10326 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */ 10327 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */ 10328 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */ 10329 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */ 10330 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */ 10331 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */ 10332 10333 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */ 10334 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */ 10335 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */ 10336 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */ 10337 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */ 10338 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */ 10339 10340 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */ 10341 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */ 10342 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */ 10343 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */ 10344 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */ 10345 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */ 10346 10347 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */ 10348 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */ 10349 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */ 10350 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */ 10351 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */ 10352 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */ 10353 10354 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */ 10355 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */ 10356 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */ 10357 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */ 10358 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */ 10359 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */ 10360 10361 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ 10362 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 10363 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 10364 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 10365 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 10366 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 10367 10368 /* Register: PWM_ENABLE */ 10369 /* Description: PWM module enable register */ 10370 10371 /* Bit 0 : Enable or disable PWM module */ 10372 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 10373 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 10374 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */ 10375 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 10376 10377 /* Register: PWM_MODE */ 10378 /* Description: Selects operating mode of the wave counter */ 10379 10380 /* Bit 0 : Selects up or up and down as wave counter mode */ 10381 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */ 10382 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */ 10383 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */ 10384 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */ 10385 10386 /* Register: PWM_COUNTERTOP */ 10387 /* Description: Value up to which the pulse generator counter counts */ 10388 10389 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */ 10390 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */ 10391 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */ 10392 10393 /* Register: PWM_PRESCALER */ 10394 /* Description: Configuration for PWM_CLK */ 10395 10396 /* Bits 2..0 : Pre-scaler of PWM_CLK */ 10397 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 10398 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 10399 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */ 10400 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */ 10401 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */ 10402 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */ 10403 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */ 10404 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */ 10405 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */ 10406 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */ 10407 10408 /* Register: PWM_DECODER */ 10409 /* Description: Configuration of the decoder */ 10410 10411 /* Bit 8 : Selects source for advancing the active sequence */ 10412 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */ 10413 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */ 10414 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */ 10415 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */ 10416 10417 /* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */ 10418 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */ 10419 #define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */ 10420 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */ 10421 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */ 10422 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */ 10423 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */ 10424 10425 /* Register: PWM_LOOP */ 10426 /* Description: Amount of playback of a loop */ 10427 10428 /* Bits 15..0 : Amount of playback of pattern cycles */ 10429 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */ 10430 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */ 10431 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */ 10432 10433 /* Register: PWM_SEQ_PTR */ 10434 /* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */ 10435 10436 /* Bits 31..0 : Beginning address in Data RAM of sequence A */ 10437 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 10438 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 10439 10440 /* Register: PWM_SEQ_CNT */ 10441 /* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */ 10442 10443 /* Bits 14..0 : Amount of values (duty cycles) in sequence A */ 10444 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */ 10445 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */ 10446 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */ 10447 10448 /* Register: PWM_SEQ_REFRESH */ 10449 /* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ 10450 10451 /* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */ 10452 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */ 10453 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */ 10454 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */ 10455 10456 /* Register: PWM_SEQ_ENDDELAY */ 10457 /* Description: Description cluster[0]: Time added after the sequence */ 10458 10459 /* Bits 23..0 : Time added after the sequence in PWM periods */ 10460 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */ 10461 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */ 10462 10463 /* Register: PWM_PSEL_OUT */ 10464 /* Description: Description collection[0]: Output pin select for PWM channel 0 */ 10465 10466 /* Bit 31 : Connection */ 10467 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10468 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10469 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */ 10470 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10471 10472 /* Bits 4..0 : Pin number */ 10473 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */ 10474 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */ 10475 10476 10477 /* Peripheral: QDEC */ 10478 /* Description: Quadrature Decoder */ 10479 10480 /* Register: QDEC_SHORTS */ 10481 /* Description: Shortcut register */ 10482 10483 /* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */ 10484 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */ 10485 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */ 10486 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ 10487 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ 10488 10489 /* Bit 5 : Shortcut between DBLRDY event and STOP task */ 10490 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */ 10491 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */ 10492 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 10493 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 10494 10495 /* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */ 10496 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */ 10497 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */ 10498 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */ 10499 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */ 10500 10501 /* Bit 3 : Shortcut between REPORTRDY event and STOP task */ 10502 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */ 10503 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */ 10504 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 10505 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 10506 10507 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */ 10508 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */ 10509 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */ 10510 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */ 10511 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */ 10512 10513 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */ 10514 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ 10515 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ 10516 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 10517 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 10518 10519 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */ 10520 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ 10521 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ 10522 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */ 10523 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */ 10524 10525 /* Register: QDEC_INTENSET */ 10526 /* Description: Enable interrupt */ 10527 10528 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */ 10529 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ 10530 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 10531 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 10532 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 10533 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 10534 10535 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */ 10536 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ 10537 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ 10538 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ 10539 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ 10540 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */ 10541 10542 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */ 10543 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 10544 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 10545 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */ 10546 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */ 10547 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */ 10548 10549 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */ 10550 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 10551 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 10552 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ 10553 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ 10554 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */ 10555 10556 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */ 10557 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 10558 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 10559 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ 10560 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ 10561 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */ 10562 10563 /* Register: QDEC_INTENCLR */ 10564 /* Description: Disable interrupt */ 10565 10566 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */ 10567 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */ 10568 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 10569 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 10570 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 10571 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 10572 10573 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */ 10574 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */ 10575 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */ 10576 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */ 10577 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */ 10578 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */ 10579 10580 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */ 10581 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 10582 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 10583 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */ 10584 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */ 10585 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */ 10586 10587 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */ 10588 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 10589 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 10590 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */ 10591 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */ 10592 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */ 10593 10594 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */ 10595 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 10596 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 10597 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */ 10598 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */ 10599 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */ 10600 10601 /* Register: QDEC_ENABLE */ 10602 /* Description: Enable the quadrature decoder */ 10603 10604 /* Bit 0 : Enable or disable the quadrature decoder */ 10605 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 10606 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 10607 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */ 10608 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */ 10609 10610 /* Register: QDEC_LEDPOL */ 10611 /* Description: LED output pin polarity */ 10612 10613 /* Bit 0 : LED output pin polarity */ 10614 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ 10615 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ 10616 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */ 10617 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */ 10618 10619 /* Register: QDEC_SAMPLEPER */ 10620 /* Description: Sample period */ 10621 10622 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */ 10623 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ 10624 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ 10625 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */ 10626 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */ 10627 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */ 10628 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */ 10629 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */ 10630 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */ 10631 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */ 10632 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */ 10633 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */ 10634 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */ 10635 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */ 10636 10637 /* Register: QDEC_SAMPLE */ 10638 /* Description: Motion sample value */ 10639 10640 /* Bits 31..0 : Last motion sample */ 10641 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ 10642 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ 10643 10644 /* Register: QDEC_REPORTPER */ 10645 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */ 10646 10647 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */ 10648 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ 10649 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ 10650 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */ 10651 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */ 10652 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */ 10653 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */ 10654 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */ 10655 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */ 10656 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */ 10657 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */ 10658 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */ 10659 10660 /* Register: QDEC_ACC */ 10661 /* Description: Register accumulating the valid transitions */ 10662 10663 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */ 10664 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */ 10665 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */ 10666 10667 /* Register: QDEC_ACCREAD */ 10668 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */ 10669 10670 /* Bits 31..0 : Snapshot of the ACC register. */ 10671 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */ 10672 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */ 10673 10674 /* Register: QDEC_PSEL_LED */ 10675 /* Description: Pin select for LED signal */ 10676 10677 /* Bit 31 : Connection */ 10678 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10679 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10680 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */ 10681 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10682 10683 /* Bits 4..0 : Pin number */ 10684 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */ 10685 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */ 10686 10687 /* Register: QDEC_PSEL_A */ 10688 /* Description: Pin select for A signal */ 10689 10690 /* Bit 31 : Connection */ 10691 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10692 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10693 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */ 10694 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10695 10696 /* Bits 4..0 : Pin number */ 10697 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */ 10698 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */ 10699 10700 /* Register: QDEC_PSEL_B */ 10701 /* Description: Pin select for B signal */ 10702 10703 /* Bit 31 : Connection */ 10704 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 10705 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 10706 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */ 10707 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */ 10708 10709 /* Bits 4..0 : Pin number */ 10710 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */ 10711 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */ 10712 10713 /* Register: QDEC_DBFEN */ 10714 /* Description: Enable input debounce filters */ 10715 10716 /* Bit 0 : Enable input debounce filters */ 10717 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ 10718 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ 10719 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */ 10720 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */ 10721 10722 /* Register: QDEC_LEDPRE */ 10723 /* Description: Time period the LED is switched ON prior to sampling */ 10724 10725 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */ 10726 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ 10727 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ 10728 10729 /* Register: QDEC_ACCDBL */ 10730 /* Description: Register accumulating the number of detected double transitions */ 10731 10732 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */ 10733 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ 10734 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ 10735 10736 /* Register: QDEC_ACCDBLREAD */ 10737 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */ 10738 10739 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */ 10740 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ 10741 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ 10742 10743 10744 /* Peripheral: RADIO */ 10745 /* Description: 2.4 GHz Radio */ 10746 10747 /* Register: RADIO_SHORTS */ 10748 /* Description: Shortcut register */ 10749 10750 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */ 10751 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ 10752 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ 10753 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */ 10754 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */ 10755 10756 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task */ 10757 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ 10758 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ 10759 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */ 10760 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */ 10761 10762 /* Bit 5 : Shortcut between END event and START task */ 10763 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ 10764 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 10765 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 10766 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 10767 10768 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */ 10769 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ 10770 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ 10771 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */ 10772 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */ 10773 10774 /* Bit 3 : Shortcut between DISABLED event and RXEN task */ 10775 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ 10776 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ 10777 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */ 10778 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */ 10779 10780 /* Bit 2 : Shortcut between DISABLED event and TXEN task */ 10781 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ 10782 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ 10783 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */ 10784 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */ 10785 10786 /* Bit 1 : Shortcut between END event and DISABLE task */ 10787 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ 10788 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ 10789 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */ 10790 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */ 10791 10792 /* Bit 0 : Shortcut between READY event and START task */ 10793 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ 10794 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ 10795 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */ 10796 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */ 10797 10798 /* Register: RADIO_INTENSET */ 10799 /* Description: Enable interrupt */ 10800 10801 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */ 10802 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 10803 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 10804 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 10805 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 10806 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */ 10807 10808 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */ 10809 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 10810 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 10811 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 10812 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 10813 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */ 10814 10815 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */ 10816 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 10817 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 10818 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 10819 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 10820 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */ 10821 10822 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */ 10823 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 10824 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 10825 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 10826 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 10827 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */ 10828 10829 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */ 10830 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 10831 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 10832 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 10833 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 10834 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */ 10835 10836 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */ 10837 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 10838 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 10839 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 10840 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 10841 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */ 10842 10843 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */ 10844 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 10845 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 10846 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 10847 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 10848 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */ 10849 10850 /* Bit 3 : Write '1' to Enable interrupt for END event */ 10851 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ 10852 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ 10853 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 10854 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 10855 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */ 10856 10857 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */ 10858 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 10859 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 10860 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 10861 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 10862 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */ 10863 10864 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */ 10865 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 10866 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 10867 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 10868 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 10869 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */ 10870 10871 /* Bit 0 : Write '1' to Enable interrupt for READY event */ 10872 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 10873 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 10874 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 10875 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 10876 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */ 10877 10878 /* Register: RADIO_INTENCLR */ 10879 /* Description: Disable interrupt */ 10880 10881 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */ 10882 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */ 10883 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */ 10884 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */ 10885 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */ 10886 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */ 10887 10888 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */ 10889 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */ 10890 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */ 10891 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */ 10892 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */ 10893 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */ 10894 10895 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */ 10896 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 10897 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 10898 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */ 10899 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */ 10900 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */ 10901 10902 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */ 10903 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 10904 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 10905 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */ 10906 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */ 10907 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */ 10908 10909 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */ 10910 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 10911 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 10912 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */ 10913 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */ 10914 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */ 10915 10916 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */ 10917 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 10918 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 10919 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */ 10920 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */ 10921 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */ 10922 10923 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */ 10924 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 10925 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 10926 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */ 10927 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */ 10928 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */ 10929 10930 /* Bit 3 : Write '1' to Disable interrupt for END event */ 10931 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ 10932 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 10933 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 10934 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 10935 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */ 10936 10937 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */ 10938 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 10939 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 10940 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */ 10941 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */ 10942 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */ 10943 10944 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */ 10945 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 10946 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 10947 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */ 10948 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */ 10949 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */ 10950 10951 /* Bit 0 : Write '1' to Disable interrupt for READY event */ 10952 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 10953 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 10954 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 10955 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 10956 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */ 10957 10958 /* Register: RADIO_CRCSTATUS */ 10959 /* Description: CRC status */ 10960 10961 /* Bit 0 : CRC status of packet received */ 10962 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ 10963 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ 10964 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */ 10965 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */ 10966 10967 /* Register: RADIO_RXMATCH */ 10968 /* Description: Received address */ 10969 10970 /* Bits 2..0 : Received address */ 10971 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ 10972 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ 10973 10974 /* Register: RADIO_RXCRC */ 10975 /* Description: CRC field of previously received packet */ 10976 10977 /* Bits 23..0 : CRC field of previously received packet */ 10978 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ 10979 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ 10980 10981 /* Register: RADIO_DAI */ 10982 /* Description: Device address match index */ 10983 10984 /* Bits 2..0 : Device address match index */ 10985 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ 10986 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ 10987 10988 /* Register: RADIO_PACKETPTR */ 10989 /* Description: Packet pointer */ 10990 10991 /* Bits 31..0 : Packet pointer */ 10992 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */ 10993 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */ 10994 10995 /* Register: RADIO_FREQUENCY */ 10996 /* Description: Frequency */ 10997 10998 /* Bit 8 : Channel map selection. */ 10999 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */ 11000 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */ 11001 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */ 11002 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */ 11003 11004 /* Bits 6..0 : Radio channel frequency */ 11005 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 11006 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 11007 11008 /* Register: RADIO_TXPOWER */ 11009 /* Description: Output power */ 11010 11011 /* Bits 7..0 : RADIO output power. */ 11012 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ 11013 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ 11014 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */ 11015 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */ 11016 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */ 11017 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */ 11018 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */ 11019 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */ 11020 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */ 11021 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */ 11022 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */ 11023 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */ 11024 11025 /* Register: RADIO_MODE */ 11026 /* Description: Data rate and modulation */ 11027 11028 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */ 11029 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 11030 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 11031 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */ 11032 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */ 11033 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */ 11034 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */ 11035 11036 /* Register: RADIO_PCNF0 */ 11037 /* Description: Packet configuration register 0 */ 11038 11039 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */ 11040 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */ 11041 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */ 11042 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */ 11043 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */ 11044 11045 /* Bit 20 : Include or exclude S1 field in RAM */ 11046 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */ 11047 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */ 11048 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN > 0 */ 11049 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */ 11050 11051 /* Bits 19..16 : Length on air of S1 field in number of bits. */ 11052 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ 11053 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ 11054 11055 /* Bit 8 : Length on air of S0 field in number of bytes. */ 11056 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ 11057 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ 11058 11059 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */ 11060 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ 11061 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ 11062 11063 /* Register: RADIO_PCNF1 */ 11064 /* Description: Packet configuration register 1 */ 11065 11066 /* Bit 25 : Enable or disable packet whitening */ 11067 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ 11068 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ 11069 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */ 11070 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */ 11071 11072 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */ 11073 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ 11074 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 11075 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */ 11076 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ 11077 11078 /* Bits 18..16 : Base address length in number of bytes */ 11079 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ 11080 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ 11081 11082 /* Bits 15..8 : Static length in number of bytes */ 11083 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ 11084 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ 11085 11086 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */ 11087 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 11088 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 11089 11090 /* Register: RADIO_BASE0 */ 11091 /* Description: Base address 0 */ 11092 11093 /* Bits 31..0 : Base address 0 */ 11094 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */ 11095 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */ 11096 11097 /* Register: RADIO_BASE1 */ 11098 /* Description: Base address 1 */ 11099 11100 /* Bits 31..0 : Base address 1 */ 11101 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */ 11102 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */ 11103 11104 /* Register: RADIO_PREFIX0 */ 11105 /* Description: Prefixes bytes for logical addresses 0-3 */ 11106 11107 /* Bits 31..24 : Address prefix 3. */ 11108 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ 11109 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ 11110 11111 /* Bits 23..16 : Address prefix 2. */ 11112 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ 11113 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ 11114 11115 /* Bits 15..8 : Address prefix 1. */ 11116 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ 11117 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ 11118 11119 /* Bits 7..0 : Address prefix 0. */ 11120 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ 11121 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ 11122 11123 /* Register: RADIO_PREFIX1 */ 11124 /* Description: Prefixes bytes for logical addresses 4-7 */ 11125 11126 /* Bits 31..24 : Address prefix 7. */ 11127 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ 11128 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ 11129 11130 /* Bits 23..16 : Address prefix 6. */ 11131 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ 11132 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ 11133 11134 /* Bits 15..8 : Address prefix 5. */ 11135 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ 11136 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ 11137 11138 /* Bits 7..0 : Address prefix 4. */ 11139 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ 11140 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ 11141 11142 /* Register: RADIO_TXADDRESS */ 11143 /* Description: Transmit address select */ 11144 11145 /* Bits 2..0 : Transmit address select */ 11146 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ 11147 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ 11148 11149 /* Register: RADIO_RXADDRESSES */ 11150 /* Description: Receive address select */ 11151 11152 /* Bit 7 : Enable or disable reception on logical address 7. */ 11153 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ 11154 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ 11155 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */ 11156 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */ 11157 11158 /* Bit 6 : Enable or disable reception on logical address 6. */ 11159 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ 11160 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ 11161 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */ 11162 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */ 11163 11164 /* Bit 5 : Enable or disable reception on logical address 5. */ 11165 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ 11166 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ 11167 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */ 11168 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */ 11169 11170 /* Bit 4 : Enable or disable reception on logical address 4. */ 11171 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ 11172 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ 11173 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */ 11174 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */ 11175 11176 /* Bit 3 : Enable or disable reception on logical address 3. */ 11177 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ 11178 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ 11179 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */ 11180 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */ 11181 11182 /* Bit 2 : Enable or disable reception on logical address 2. */ 11183 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ 11184 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ 11185 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */ 11186 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */ 11187 11188 /* Bit 1 : Enable or disable reception on logical address 1. */ 11189 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ 11190 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ 11191 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */ 11192 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */ 11193 11194 /* Bit 0 : Enable or disable reception on logical address 0. */ 11195 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ 11196 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ 11197 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */ 11198 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */ 11199 11200 /* Register: RADIO_CRCCNF */ 11201 /* Description: CRC configuration */ 11202 11203 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */ 11204 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ 11205 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ 11206 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */ 11207 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */ 11208 11209 /* Bits 1..0 : CRC length in number of bytes. */ 11210 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ 11211 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ 11212 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */ 11213 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */ 11214 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */ 11215 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */ 11216 11217 /* Register: RADIO_CRCPOLY */ 11218 /* Description: CRC polynomial */ 11219 11220 /* Bits 23..0 : CRC polynomial */ 11221 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ 11222 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ 11223 11224 /* Register: RADIO_CRCINIT */ 11225 /* Description: CRC initial value */ 11226 11227 /* Bits 23..0 : CRC initial value */ 11228 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ 11229 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ 11230 11231 /* Register: RADIO_TIFS */ 11232 /* Description: Inter Frame Spacing in us */ 11233 11234 /* Bits 7..0 : Inter Frame Spacing in us */ 11235 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ 11236 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ 11237 11238 /* Register: RADIO_RSSISAMPLE */ 11239 /* Description: RSSI sample */ 11240 11241 /* Bits 6..0 : RSSI sample */ 11242 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ 11243 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ 11244 11245 /* Register: RADIO_STATE */ 11246 /* Description: Current radio state */ 11247 11248 /* Bits 3..0 : Current radio state */ 11249 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ 11250 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ 11251 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */ 11252 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */ 11253 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */ 11254 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */ 11255 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */ 11256 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */ 11257 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */ 11258 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */ 11259 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */ 11260 11261 /* Register: RADIO_DATAWHITEIV */ 11262 /* Description: Data whitening initial value */ 11263 11264 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */ 11265 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ 11266 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ 11267 11268 /* Register: RADIO_BCC */ 11269 /* Description: Bit counter compare */ 11270 11271 /* Bits 31..0 : Bit counter compare */ 11272 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */ 11273 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */ 11274 11275 /* Register: RADIO_DAB */ 11276 /* Description: Description collection[0]: Device address base segment 0 */ 11277 11278 /* Bits 31..0 : Device address base segment 0 */ 11279 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */ 11280 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */ 11281 11282 /* Register: RADIO_DAP */ 11283 /* Description: Description collection[0]: Device address prefix 0 */ 11284 11285 /* Bits 15..0 : Device address prefix 0 */ 11286 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ 11287 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ 11288 11289 /* Register: RADIO_DACNF */ 11290 /* Description: Device address match configuration */ 11291 11292 /* Bit 15 : TxAdd for device address 7 */ 11293 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ 11294 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ 11295 11296 /* Bit 14 : TxAdd for device address 6 */ 11297 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ 11298 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ 11299 11300 /* Bit 13 : TxAdd for device address 5 */ 11301 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ 11302 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ 11303 11304 /* Bit 12 : TxAdd for device address 4 */ 11305 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ 11306 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ 11307 11308 /* Bit 11 : TxAdd for device address 3 */ 11309 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ 11310 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ 11311 11312 /* Bit 10 : TxAdd for device address 2 */ 11313 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ 11314 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ 11315 11316 /* Bit 9 : TxAdd for device address 1 */ 11317 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ 11318 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ 11319 11320 /* Bit 8 : TxAdd for device address 0 */ 11321 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ 11322 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ 11323 11324 /* Bit 7 : Enable or disable device address matching using device address 7 */ 11325 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ 11326 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ 11327 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */ 11328 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */ 11329 11330 /* Bit 6 : Enable or disable device address matching using device address 6 */ 11331 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ 11332 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ 11333 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */ 11334 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */ 11335 11336 /* Bit 5 : Enable or disable device address matching using device address 5 */ 11337 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ 11338 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ 11339 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */ 11340 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */ 11341 11342 /* Bit 4 : Enable or disable device address matching using device address 4 */ 11343 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ 11344 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ 11345 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */ 11346 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */ 11347 11348 /* Bit 3 : Enable or disable device address matching using device address 3 */ 11349 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ 11350 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ 11351 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */ 11352 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */ 11353 11354 /* Bit 2 : Enable or disable device address matching using device address 2 */ 11355 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ 11356 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ 11357 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */ 11358 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */ 11359 11360 /* Bit 1 : Enable or disable device address matching using device address 1 */ 11361 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ 11362 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ 11363 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */ 11364 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */ 11365 11366 /* Bit 0 : Enable or disable device address matching using device address 0 */ 11367 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ 11368 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ 11369 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */ 11370 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */ 11371 11372 /* Register: RADIO_MODECNF0 */ 11373 /* Description: Radio mode configuration register 0 */ 11374 11375 /* Bits 9..8 : Default TX value */ 11376 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */ 11377 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */ 11378 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */ 11379 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */ 11380 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */ 11381 11382 /* Bit 0 : Radio ramp-up time */ 11383 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */ 11384 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */ 11385 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */ 11386 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */ 11387 11388 /* Register: RADIO_POWER */ 11389 /* Description: Peripheral power control */ 11390 11391 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */ 11392 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 11393 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 11394 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */ 11395 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */ 11396 11397 11398 /* Peripheral: RNG */ 11399 /* Description: Random Number Generator */ 11400 11401 /* Register: RNG_SHORTS */ 11402 /* Description: Shortcut register */ 11403 11404 /* Bit 0 : Shortcut between VALRDY event and STOP task */ 11405 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ 11406 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ 11407 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */ 11408 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */ 11409 11410 /* Register: RNG_INTENSET */ 11411 /* Description: Enable interrupt */ 11412 11413 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */ 11414 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 11415 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 11416 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 11417 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 11418 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */ 11419 11420 /* Register: RNG_INTENCLR */ 11421 /* Description: Disable interrupt */ 11422 11423 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */ 11424 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 11425 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 11426 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */ 11427 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */ 11428 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */ 11429 11430 /* Register: RNG_CONFIG */ 11431 /* Description: Configuration register */ 11432 11433 /* Bit 0 : Bias correction */ 11434 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ 11435 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ 11436 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */ 11437 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */ 11438 11439 /* Register: RNG_VALUE */ 11440 /* Description: Output random number */ 11441 11442 /* Bits 7..0 : Generated random number */ 11443 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 11444 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 11445 11446 11447 /* Peripheral: RTC */ 11448 /* Description: Real time counter 0 */ 11449 11450 /* Register: RTC_INTENSET */ 11451 /* Description: Enable interrupt */ 11452 11453 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ 11454 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 11455 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 11456 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 11457 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 11458 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 11459 11460 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ 11461 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 11462 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 11463 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 11464 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 11465 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ 11466 11467 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ 11468 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 11469 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 11470 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 11471 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 11472 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ 11473 11474 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ 11475 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 11476 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 11477 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 11478 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 11479 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 11480 11481 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */ 11482 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 11483 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 11484 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 11485 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 11486 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */ 11487 11488 /* Bit 0 : Write '1' to Enable interrupt for TICK event */ 11489 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 11490 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 11491 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 11492 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 11493 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */ 11494 11495 /* Register: RTC_INTENCLR */ 11496 /* Description: Disable interrupt */ 11497 11498 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ 11499 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 11500 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 11501 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 11502 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 11503 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 11504 11505 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ 11506 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 11507 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 11508 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 11509 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 11510 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 11511 11512 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ 11513 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 11514 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 11515 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 11516 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 11517 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 11518 11519 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ 11520 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 11521 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 11522 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 11523 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 11524 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 11525 11526 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */ 11527 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 11528 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 11529 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 11530 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 11531 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 11532 11533 /* Bit 0 : Write '1' to Disable interrupt for TICK event */ 11534 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 11535 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 11536 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 11537 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 11538 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */ 11539 11540 /* Register: RTC_EVTEN */ 11541 /* Description: Enable or disable event routing */ 11542 11543 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */ 11544 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 11545 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 11546 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */ 11547 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */ 11548 11549 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */ 11550 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 11551 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 11552 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */ 11553 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */ 11554 11555 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */ 11556 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 11557 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 11558 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */ 11559 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */ 11560 11561 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */ 11562 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 11563 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 11564 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */ 11565 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */ 11566 11567 /* Bit 1 : Enable or disable event routing for OVRFLW event */ 11568 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 11569 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 11570 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */ 11571 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */ 11572 11573 /* Bit 0 : Enable or disable event routing for TICK event */ 11574 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 11575 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 11576 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */ 11577 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */ 11578 11579 /* Register: RTC_EVTENSET */ 11580 /* Description: Enable event routing */ 11581 11582 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */ 11583 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 11584 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 11585 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 11586 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 11587 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */ 11588 11589 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */ 11590 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 11591 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 11592 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 11593 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 11594 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */ 11595 11596 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */ 11597 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 11598 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 11599 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 11600 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 11601 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */ 11602 11603 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */ 11604 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 11605 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 11606 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 11607 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 11608 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */ 11609 11610 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */ 11611 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 11612 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 11613 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 11614 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 11615 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */ 11616 11617 /* Bit 0 : Write '1' to Enable event routing for TICK event */ 11618 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 11619 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 11620 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */ 11621 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */ 11622 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */ 11623 11624 /* Register: RTC_EVTENCLR */ 11625 /* Description: Disable event routing */ 11626 11627 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */ 11628 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 11629 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 11630 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 11631 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 11632 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 11633 11634 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */ 11635 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 11636 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 11637 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 11638 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 11639 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 11640 11641 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */ 11642 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 11643 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 11644 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 11645 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 11646 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 11647 11648 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */ 11649 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 11650 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 11651 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 11652 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 11653 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 11654 11655 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */ 11656 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 11657 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 11658 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */ 11659 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */ 11660 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */ 11661 11662 /* Bit 0 : Write '1' to Disable event routing for TICK event */ 11663 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 11664 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 11665 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */ 11666 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */ 11667 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */ 11668 11669 /* Register: RTC_COUNTER */ 11670 /* Description: Current COUNTER value */ 11671 11672 /* Bits 23..0 : Counter value */ 11673 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 11674 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 11675 11676 /* Register: RTC_PRESCALER */ 11677 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */ 11678 11679 /* Bits 11..0 : Prescaler value */ 11680 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 11681 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 11682 11683 /* Register: RTC_CC */ 11684 /* Description: Description collection[0]: Compare register 0 */ 11685 11686 /* Bits 23..0 : Compare value */ 11687 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 11688 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 11689 11690 11691 /* Peripheral: SAADC */ 11692 /* Description: Analog to Digital Converter */ 11693 11694 /* Register: SAADC_INTEN */ 11695 /* Description: Enable or disable interrupt */ 11696 11697 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */ 11698 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 11699 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 11700 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */ 11701 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */ 11702 11703 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */ 11704 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 11705 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 11706 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */ 11707 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */ 11708 11709 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */ 11710 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 11711 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 11712 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */ 11713 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */ 11714 11715 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */ 11716 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 11717 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 11718 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */ 11719 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */ 11720 11721 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */ 11722 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 11723 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 11724 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */ 11725 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */ 11726 11727 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */ 11728 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 11729 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 11730 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */ 11731 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */ 11732 11733 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */ 11734 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 11735 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 11736 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */ 11737 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */ 11738 11739 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */ 11740 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 11741 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 11742 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */ 11743 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */ 11744 11745 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */ 11746 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 11747 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 11748 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */ 11749 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */ 11750 11751 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */ 11752 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 11753 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 11754 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */ 11755 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */ 11756 11757 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */ 11758 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 11759 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 11760 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */ 11761 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */ 11762 11763 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */ 11764 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 11765 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 11766 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */ 11767 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */ 11768 11769 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */ 11770 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 11771 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 11772 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */ 11773 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */ 11774 11775 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */ 11776 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 11777 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 11778 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */ 11779 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */ 11780 11781 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */ 11782 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 11783 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 11784 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */ 11785 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */ 11786 11787 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */ 11788 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 11789 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 11790 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */ 11791 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */ 11792 11793 /* Bit 5 : Enable or disable interrupt for STOPPED event */ 11794 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 11795 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 11796 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 11797 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 11798 11799 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */ 11800 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 11801 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 11802 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */ 11803 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */ 11804 11805 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */ 11806 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 11807 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 11808 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */ 11809 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */ 11810 11811 /* Bit 2 : Enable or disable interrupt for DONE event */ 11812 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */ 11813 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */ 11814 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */ 11815 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */ 11816 11817 /* Bit 1 : Enable or disable interrupt for END event */ 11818 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */ 11819 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */ 11820 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */ 11821 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */ 11822 11823 /* Bit 0 : Enable or disable interrupt for STARTED event */ 11824 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 11825 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */ 11826 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */ 11827 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */ 11828 11829 /* Register: SAADC_INTENSET */ 11830 /* Description: Enable interrupt */ 11831 11832 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */ 11833 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 11834 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 11835 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11836 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11837 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */ 11838 11839 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */ 11840 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 11841 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 11842 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ 11843 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ 11844 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */ 11845 11846 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */ 11847 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 11848 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 11849 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11850 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11851 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */ 11852 11853 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */ 11854 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 11855 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 11856 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ 11857 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ 11858 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */ 11859 11860 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */ 11861 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 11862 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 11863 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11864 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11865 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */ 11866 11867 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */ 11868 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 11869 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 11870 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ 11871 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ 11872 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */ 11873 11874 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */ 11875 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 11876 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 11877 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11878 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11879 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */ 11880 11881 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */ 11882 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 11883 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 11884 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ 11885 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ 11886 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */ 11887 11888 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */ 11889 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 11890 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 11891 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11892 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11893 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */ 11894 11895 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */ 11896 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 11897 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 11898 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ 11899 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ 11900 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */ 11901 11902 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */ 11903 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 11904 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 11905 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11906 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11907 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */ 11908 11909 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */ 11910 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 11911 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 11912 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ 11913 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ 11914 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */ 11915 11916 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */ 11917 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 11918 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 11919 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11920 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11921 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */ 11922 11923 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */ 11924 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 11925 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 11926 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ 11927 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ 11928 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */ 11929 11930 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */ 11931 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 11932 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 11933 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11934 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11935 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */ 11936 11937 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */ 11938 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 11939 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 11940 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ 11941 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ 11942 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */ 11943 11944 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */ 11945 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 11946 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 11947 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 11948 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 11949 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 11950 11951 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */ 11952 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 11953 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 11954 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ 11955 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ 11956 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */ 11957 11958 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */ 11959 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 11960 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 11961 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ 11962 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ 11963 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */ 11964 11965 /* Bit 2 : Write '1' to Enable interrupt for DONE event */ 11966 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */ 11967 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 11968 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */ 11969 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */ 11970 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */ 11971 11972 /* Bit 1 : Write '1' to Enable interrupt for END event */ 11973 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 11974 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ 11975 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 11976 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 11977 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */ 11978 11979 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */ 11980 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 11981 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 11982 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 11983 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 11984 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */ 11985 11986 /* Register: SAADC_INTENCLR */ 11987 /* Description: Disable interrupt */ 11988 11989 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */ 11990 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */ 11991 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */ 11992 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */ 11993 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */ 11994 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */ 11995 11996 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */ 11997 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */ 11998 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */ 11999 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */ 12000 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */ 12001 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */ 12002 12003 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */ 12004 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */ 12005 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */ 12006 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */ 12007 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */ 12008 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */ 12009 12010 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */ 12011 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */ 12012 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */ 12013 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */ 12014 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */ 12015 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */ 12016 12017 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */ 12018 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */ 12019 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */ 12020 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */ 12021 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */ 12022 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */ 12023 12024 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */ 12025 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */ 12026 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */ 12027 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */ 12028 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */ 12029 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */ 12030 12031 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */ 12032 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */ 12033 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */ 12034 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */ 12035 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */ 12036 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */ 12037 12038 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */ 12039 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */ 12040 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */ 12041 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */ 12042 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */ 12043 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */ 12044 12045 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */ 12046 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */ 12047 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */ 12048 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */ 12049 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */ 12050 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */ 12051 12052 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */ 12053 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */ 12054 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */ 12055 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */ 12056 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */ 12057 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */ 12058 12059 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */ 12060 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */ 12061 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */ 12062 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */ 12063 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */ 12064 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */ 12065 12066 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */ 12067 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */ 12068 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */ 12069 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */ 12070 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */ 12071 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */ 12072 12073 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */ 12074 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */ 12075 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */ 12076 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */ 12077 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */ 12078 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */ 12079 12080 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */ 12081 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */ 12082 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */ 12083 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */ 12084 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */ 12085 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */ 12086 12087 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */ 12088 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */ 12089 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */ 12090 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */ 12091 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */ 12092 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */ 12093 12094 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */ 12095 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */ 12096 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */ 12097 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */ 12098 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */ 12099 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */ 12100 12101 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */ 12102 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */ 12103 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 12104 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 12105 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 12106 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 12107 12108 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */ 12109 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */ 12110 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */ 12111 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */ 12112 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */ 12113 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */ 12114 12115 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */ 12116 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */ 12117 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */ 12118 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */ 12119 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */ 12120 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */ 12121 12122 /* Bit 2 : Write '1' to Disable interrupt for DONE event */ 12123 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */ 12124 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 12125 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */ 12126 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */ 12127 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */ 12128 12129 /* Bit 1 : Write '1' to Disable interrupt for END event */ 12130 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 12131 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 12132 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 12133 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 12134 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */ 12135 12136 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */ 12137 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */ 12138 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 12139 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 12140 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 12141 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 12142 12143 /* Register: SAADC_STATUS */ 12144 /* Description: Status */ 12145 12146 /* Bit 0 : Status */ 12147 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 12148 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 12149 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */ 12150 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */ 12151 12152 /* Register: SAADC_ENABLE */ 12153 /* Description: Enable or disable ADC */ 12154 12155 /* Bit 0 : Enable or disable ADC */ 12156 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 12157 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 12158 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */ 12159 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */ 12160 12161 /* Register: SAADC_CH_PSELP */ 12162 /* Description: Description cluster[0]: Input positive pin selection for CH[0] */ 12163 12164 /* Bits 4..0 : Analog positive input channel */ 12165 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */ 12166 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */ 12167 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */ 12168 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */ 12169 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */ 12170 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */ 12171 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */ 12172 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */ 12173 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */ 12174 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */ 12175 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */ 12176 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */ 12177 12178 /* Register: SAADC_CH_PSELN */ 12179 /* Description: Description cluster[0]: Input negative pin selection for CH[0] */ 12180 12181 /* Bits 4..0 : Analog negative input, enables differential channel */ 12182 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */ 12183 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */ 12184 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */ 12185 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */ 12186 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */ 12187 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */ 12188 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */ 12189 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */ 12190 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */ 12191 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */ 12192 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */ 12193 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */ 12194 12195 /* Register: SAADC_CH_CONFIG */ 12196 /* Description: Description cluster[0]: Input configuration for CH[0] */ 12197 12198 /* Bit 24 : Enable burst mode */ 12199 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */ 12200 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */ 12201 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */ 12202 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */ 12203 12204 /* Bit 20 : Enable differential mode */ 12205 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */ 12206 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 12207 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */ 12208 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */ 12209 12210 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */ 12211 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */ 12212 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */ 12213 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */ 12214 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */ 12215 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */ 12216 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */ 12217 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */ 12218 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */ 12219 12220 /* Bit 12 : Reference control */ 12221 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */ 12222 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 12223 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */ 12224 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */ 12225 12226 /* Bits 10..8 : Gain control */ 12227 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */ 12228 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */ 12229 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */ 12230 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */ 12231 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */ 12232 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */ 12233 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */ 12234 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */ 12235 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */ 12236 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */ 12237 12238 /* Bits 5..4 : Negative channel resistor control */ 12239 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */ 12240 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */ 12241 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */ 12242 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */ 12243 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */ 12244 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */ 12245 12246 /* Bits 1..0 : Positive channel resistor control */ 12247 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */ 12248 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */ 12249 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */ 12250 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */ 12251 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */ 12252 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */ 12253 12254 /* Register: SAADC_CH_LIMIT */ 12255 /* Description: Description cluster[0]: High/low limits for event monitoring a channel */ 12256 12257 /* Bits 31..16 : High level limit */ 12258 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */ 12259 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */ 12260 12261 /* Bits 15..0 : Low level limit */ 12262 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */ 12263 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */ 12264 12265 /* Register: SAADC_RESOLUTION */ 12266 /* Description: Resolution configuration */ 12267 12268 /* Bits 2..0 : Set the resolution */ 12269 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */ 12270 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */ 12271 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */ 12272 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */ 12273 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */ 12274 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */ 12275 12276 /* Register: SAADC_OVERSAMPLE */ 12277 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */ 12278 12279 /* Bits 3..0 : Oversample control */ 12280 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */ 12281 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */ 12282 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */ 12283 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */ 12284 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */ 12285 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */ 12286 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */ 12287 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */ 12288 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */ 12289 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */ 12290 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */ 12291 12292 /* Register: SAADC_SAMPLERATE */ 12293 /* Description: Controls normal or continuous sample rate */ 12294 12295 /* Bit 12 : Select mode for sample rate control */ 12296 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */ 12297 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */ 12298 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */ 12299 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */ 12300 12301 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */ 12302 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */ 12303 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */ 12304 12305 /* Register: SAADC_RESULT_PTR */ 12306 /* Description: Data pointer */ 12307 12308 /* Bits 31..0 : Data pointer */ 12309 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 12310 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 12311 12312 /* Register: SAADC_RESULT_MAXCNT */ 12313 /* Description: Maximum number of buffer words to transfer */ 12314 12315 /* Bits 14..0 : Maximum number of buffer words to transfer */ 12316 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 12317 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 12318 12319 /* Register: SAADC_RESULT_AMOUNT */ 12320 /* Description: Number of buffer words transferred since last START */ 12321 12322 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */ 12323 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 12324 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 12325 12326 12327 /* Peripheral: SPI */ 12328 /* Description: Serial Peripheral Interface 0 */ 12329 12330 /* Register: SPI_INTENSET */ 12331 /* Description: Enable interrupt */ 12332 12333 /* Bit 2 : Write '1' to Enable interrupt for READY event */ 12334 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ 12335 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 12336 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */ 12337 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */ 12338 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */ 12339 12340 /* Register: SPI_INTENCLR */ 12341 /* Description: Disable interrupt */ 12342 12343 /* Bit 2 : Write '1' to Disable interrupt for READY event */ 12344 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ 12345 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 12346 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */ 12347 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */ 12348 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */ 12349 12350 /* Register: SPI_ENABLE */ 12351 /* Description: Enable SPI */ 12352 12353 /* Bits 3..0 : Enable or disable SPI */ 12354 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 12355 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 12356 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */ 12357 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */ 12358 12359 /* Register: SPI_PSEL_SCK */ 12360 /* Description: Pin select for SCK */ 12361 12362 /* Bits 31..0 : Pin number configuration for SPI SCK signal */ 12363 #define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */ 12364 #define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */ 12365 #define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 12366 12367 /* Register: SPI_PSEL_MOSI */ 12368 /* Description: Pin select for MOSI */ 12369 12370 /* Bits 31..0 : Pin number configuration for SPI MOSI signal */ 12371 #define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */ 12372 #define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */ 12373 #define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 12374 12375 /* Register: SPI_PSEL_MISO */ 12376 /* Description: Pin select for MISO */ 12377 12378 /* Bits 31..0 : Pin number configuration for SPI MISO signal */ 12379 #define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */ 12380 #define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */ 12381 #define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 12382 12383 /* Register: SPI_RXD */ 12384 /* Description: RXD register */ 12385 12386 /* Bits 7..0 : RX data received. Double buffered */ 12387 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 12388 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 12389 12390 /* Register: SPI_TXD */ 12391 /* Description: TXD register */ 12392 12393 /* Bits 7..0 : TX data to send. Double buffered */ 12394 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 12395 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 12396 12397 /* Register: SPI_FREQUENCY */ 12398 /* Description: SPI frequency */ 12399 12400 /* Bits 31..0 : SPI master data rate */ 12401 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 12402 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 12403 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ 12404 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 12405 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ 12406 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ 12407 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ 12408 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ 12409 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ 12410 12411 /* Register: SPI_CONFIG */ 12412 /* Description: Configuration register */ 12413 12414 /* Bit 2 : Serial clock (SCK) polarity */ 12415 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 12416 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 12417 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 12418 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 12419 12420 /* Bit 1 : Serial clock (SCK) phase */ 12421 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 12422 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 12423 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 12424 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 12425 12426 /* Bit 0 : Bit order */ 12427 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 12428 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 12429 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 12430 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 12431 12432 12433 /* Peripheral: SPIM */ 12434 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */ 12435 12436 /* Register: SPIM_SHORTS */ 12437 /* Description: Shortcut register */ 12438 12439 /* Bit 17 : Shortcut between END event and START task */ 12440 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ 12441 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 12442 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */ 12443 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */ 12444 12445 /* Register: SPIM_INTENSET */ 12446 /* Description: Enable interrupt */ 12447 12448 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */ 12449 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 12450 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 12451 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */ 12452 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */ 12453 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */ 12454 12455 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ 12456 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 12457 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 12458 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 12459 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 12460 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 12461 12462 /* Bit 6 : Write '1' to Enable interrupt for END event */ 12463 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ 12464 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 12465 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 12466 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 12467 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */ 12468 12469 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ 12470 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 12471 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 12472 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 12473 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 12474 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 12475 12476 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ 12477 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 12478 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 12479 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 12480 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 12481 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 12482 12483 /* Register: SPIM_INTENCLR */ 12484 /* Description: Disable interrupt */ 12485 12486 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */ 12487 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 12488 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 12489 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */ 12490 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */ 12491 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */ 12492 12493 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ 12494 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 12495 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 12496 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 12497 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 12498 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 12499 12500 /* Bit 6 : Write '1' to Disable interrupt for END event */ 12501 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ 12502 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 12503 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 12504 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 12505 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */ 12506 12507 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ 12508 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 12509 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 12510 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 12511 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 12512 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 12513 12514 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ 12515 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 12516 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 12517 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 12518 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 12519 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 12520 12521 /* Register: SPIM_ENABLE */ 12522 /* Description: Enable SPIM */ 12523 12524 /* Bits 3..0 : Enable or disable SPIM */ 12525 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 12526 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 12527 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */ 12528 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */ 12529 12530 /* Register: SPIM_PSEL_SCK */ 12531 /* Description: Pin select for SCK */ 12532 12533 /* Bit 31 : Connection */ 12534 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12535 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12536 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 12537 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 12538 12539 /* Bits 4..0 : Pin number */ 12540 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 12541 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 12542 12543 /* Register: SPIM_PSEL_MOSI */ 12544 /* Description: Pin select for MOSI signal */ 12545 12546 /* Bit 31 : Connection */ 12547 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12548 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12549 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 12550 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 12551 12552 /* Bits 4..0 : Pin number */ 12553 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 12554 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 12555 12556 /* Register: SPIM_PSEL_MISO */ 12557 /* Description: Pin select for MISO signal */ 12558 12559 /* Bit 31 : Connection */ 12560 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12561 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12562 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 12563 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 12564 12565 /* Bits 4..0 : Pin number */ 12566 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 12567 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 12568 12569 /* Register: SPIM_FREQUENCY */ 12570 /* Description: SPI frequency */ 12571 12572 /* Bits 31..0 : SPI master data rate */ 12573 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 12574 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 12575 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */ 12576 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 12577 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */ 12578 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */ 12579 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */ 12580 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */ 12581 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */ 12582 12583 /* Register: SPIM_RXD_PTR */ 12584 /* Description: Data pointer */ 12585 12586 /* Bits 31..0 : Data pointer */ 12587 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 12588 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 12589 12590 /* Register: SPIM_RXD_MAXCNT */ 12591 /* Description: Maximum number of bytes in receive buffer */ 12592 12593 /* Bits 7..0 : Maximum number of bytes in receive buffer */ 12594 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 12595 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 12596 12597 /* Register: SPIM_RXD_AMOUNT */ 12598 /* Description: Number of bytes transferred in the last transaction */ 12599 12600 /* Bits 7..0 : Number of bytes transferred in the last transaction */ 12601 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 12602 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 12603 12604 /* Register: SPIM_RXD_LIST */ 12605 /* Description: EasyDMA list type */ 12606 12607 /* Bits 2..0 : List type */ 12608 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 12609 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 12610 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 12611 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 12612 12613 /* Register: SPIM_TXD_PTR */ 12614 /* Description: Data pointer */ 12615 12616 /* Bits 31..0 : Data pointer */ 12617 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 12618 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 12619 12620 /* Register: SPIM_TXD_MAXCNT */ 12621 /* Description: Maximum number of bytes in transmit buffer */ 12622 12623 /* Bits 7..0 : Maximum number of bytes in transmit buffer */ 12624 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 12625 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 12626 12627 /* Register: SPIM_TXD_AMOUNT */ 12628 /* Description: Number of bytes transferred in the last transaction */ 12629 12630 /* Bits 7..0 : Number of bytes transferred in the last transaction */ 12631 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 12632 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 12633 12634 /* Register: SPIM_TXD_LIST */ 12635 /* Description: EasyDMA list type */ 12636 12637 /* Bits 2..0 : List type */ 12638 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 12639 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 12640 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 12641 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 12642 12643 /* Register: SPIM_CONFIG */ 12644 /* Description: Configuration register */ 12645 12646 /* Bit 2 : Serial clock (SCK) polarity */ 12647 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 12648 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 12649 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 12650 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 12651 12652 /* Bit 1 : Serial clock (SCK) phase */ 12653 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 12654 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 12655 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 12656 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 12657 12658 /* Bit 0 : Bit order */ 12659 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 12660 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 12661 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 12662 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 12663 12664 /* Register: SPIM_ORC */ 12665 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */ 12666 12667 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */ 12668 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 12669 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 12670 12671 12672 /* Peripheral: SPIS */ 12673 /* Description: SPI Slave 0 */ 12674 12675 /* Register: SPIS_SHORTS */ 12676 /* Description: Shortcut register */ 12677 12678 /* Bit 2 : Shortcut between END event and ACQUIRE task */ 12679 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ 12680 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ 12681 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */ 12682 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */ 12683 12684 /* Register: SPIS_INTENSET */ 12685 /* Description: Enable interrupt */ 12686 12687 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */ 12688 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 12689 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 12690 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ 12691 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ 12692 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */ 12693 12694 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ 12695 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 12696 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 12697 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 12698 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 12699 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 12700 12701 /* Bit 1 : Write '1' to Enable interrupt for END event */ 12702 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 12703 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ 12704 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */ 12705 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */ 12706 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */ 12707 12708 /* Register: SPIS_INTENCLR */ 12709 /* Description: Disable interrupt */ 12710 12711 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */ 12712 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 12713 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 12714 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */ 12715 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */ 12716 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */ 12717 12718 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ 12719 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 12720 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 12721 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 12722 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 12723 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 12724 12725 /* Bit 1 : Write '1' to Disable interrupt for END event */ 12726 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 12727 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 12728 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */ 12729 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */ 12730 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */ 12731 12732 /* Register: SPIS_SEMSTAT */ 12733 /* Description: Semaphore status register */ 12734 12735 /* Bits 1..0 : Semaphore status */ 12736 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ 12737 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ 12738 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */ 12739 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */ 12740 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */ 12741 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */ 12742 12743 /* Register: SPIS_STATUS */ 12744 /* Description: Status from last transaction */ 12745 12746 /* Bit 1 : RX buffer overflow detected, and prevented */ 12747 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ 12748 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 12749 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */ 12750 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */ 12751 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */ 12752 12753 /* Bit 0 : TX buffer over-read detected, and prevented */ 12754 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ 12755 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 12756 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */ 12757 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */ 12758 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */ 12759 12760 /* Register: SPIS_ENABLE */ 12761 /* Description: Enable SPI slave */ 12762 12763 /* Bits 3..0 : Enable or disable SPI slave */ 12764 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 12765 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 12766 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */ 12767 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */ 12768 12769 /* Register: SPIS_PSEL_SCK */ 12770 /* Description: Pin select for SCK */ 12771 12772 /* Bit 31 : Connection */ 12773 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12774 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12775 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */ 12776 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */ 12777 12778 /* Bits 4..0 : Pin number */ 12779 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */ 12780 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */ 12781 12782 /* Register: SPIS_PSEL_MISO */ 12783 /* Description: Pin select for MISO signal */ 12784 12785 /* Bit 31 : Connection */ 12786 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12787 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12788 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */ 12789 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */ 12790 12791 /* Bits 4..0 : Pin number */ 12792 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */ 12793 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */ 12794 12795 /* Register: SPIS_PSEL_MOSI */ 12796 /* Description: Pin select for MOSI signal */ 12797 12798 /* Bit 31 : Connection */ 12799 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12800 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12801 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */ 12802 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */ 12803 12804 /* Bits 4..0 : Pin number */ 12805 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */ 12806 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */ 12807 12808 /* Register: SPIS_PSEL_CSN */ 12809 /* Description: Pin select for CSN signal */ 12810 12811 /* Bit 31 : Connection */ 12812 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 12813 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 12814 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */ 12815 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */ 12816 12817 /* Bits 4..0 : Pin number */ 12818 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */ 12819 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */ 12820 12821 /* Register: SPIS_RXD_PTR */ 12822 /* Description: RXD data pointer */ 12823 12824 /* Bits 31..0 : RXD data pointer */ 12825 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 12826 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 12827 12828 /* Register: SPIS_RXD_MAXCNT */ 12829 /* Description: Maximum number of bytes in receive buffer */ 12830 12831 /* Bits 7..0 : Maximum number of bytes in receive buffer */ 12832 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 12833 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 12834 12835 /* Register: SPIS_RXD_AMOUNT */ 12836 /* Description: Number of bytes received in last granted transaction */ 12837 12838 /* Bits 7..0 : Number of bytes received in the last granted transaction */ 12839 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 12840 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 12841 12842 /* Register: SPIS_TXD_PTR */ 12843 /* Description: TXD data pointer */ 12844 12845 /* Bits 31..0 : TXD data pointer */ 12846 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 12847 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 12848 12849 /* Register: SPIS_TXD_MAXCNT */ 12850 /* Description: Maximum number of bytes in transmit buffer */ 12851 12852 /* Bits 7..0 : Maximum number of bytes in transmit buffer */ 12853 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 12854 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 12855 12856 /* Register: SPIS_TXD_AMOUNT */ 12857 /* Description: Number of bytes transmitted in last granted transaction */ 12858 12859 /* Bits 7..0 : Number of bytes transmitted in last granted transaction */ 12860 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 12861 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 12862 12863 /* Register: SPIS_CONFIG */ 12864 /* Description: Configuration register */ 12865 12866 /* Bit 2 : Serial clock (SCK) polarity */ 12867 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 12868 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 12869 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */ 12870 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */ 12871 12872 /* Bit 1 : Serial clock (SCK) phase */ 12873 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 12874 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 12875 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */ 12876 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */ 12877 12878 /* Bit 0 : Bit order */ 12879 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 12880 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 12881 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */ 12882 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */ 12883 12884 /* Register: SPIS_DEF */ 12885 /* Description: Default character. Character clocked out in case of an ignored transaction. */ 12886 12887 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */ 12888 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ 12889 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ 12890 12891 /* Register: SPIS_ORC */ 12892 /* Description: Over-read character */ 12893 12894 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */ 12895 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 12896 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 12897 12898 12899 /* Peripheral: TEMP */ 12900 /* Description: Temperature Sensor */ 12901 12902 /* Register: TEMP_INTENSET */ 12903 /* Description: Enable interrupt */ 12904 12905 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */ 12906 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 12907 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 12908 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 12909 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 12910 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */ 12911 12912 /* Register: TEMP_INTENCLR */ 12913 /* Description: Disable interrupt */ 12914 12915 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */ 12916 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 12917 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 12918 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */ 12919 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */ 12920 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */ 12921 12922 /* Register: TEMP_TEMP */ 12923 /* Description: Temperature in degC (0.25deg steps) */ 12924 12925 /* Bits 31..0 : Temperature in degC (0.25deg steps) */ 12926 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */ 12927 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */ 12928 12929 /* Register: TEMP_A0 */ 12930 /* Description: Slope of 1st piece wise linear function */ 12931 12932 /* Bits 11..0 : Slope of 1st piece wise linear function */ 12933 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */ 12934 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */ 12935 12936 /* Register: TEMP_A1 */ 12937 /* Description: Slope of 2nd piece wise linear function */ 12938 12939 /* Bits 11..0 : Slope of 2nd piece wise linear function */ 12940 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */ 12941 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */ 12942 12943 /* Register: TEMP_A2 */ 12944 /* Description: Slope of 3rd piece wise linear function */ 12945 12946 /* Bits 11..0 : Slope of 3rd piece wise linear function */ 12947 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */ 12948 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */ 12949 12950 /* Register: TEMP_A3 */ 12951 /* Description: Slope of 4th piece wise linear function */ 12952 12953 /* Bits 11..0 : Slope of 4th piece wise linear function */ 12954 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */ 12955 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */ 12956 12957 /* Register: TEMP_A4 */ 12958 /* Description: Slope of 5th piece wise linear function */ 12959 12960 /* Bits 11..0 : Slope of 5th piece wise linear function */ 12961 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */ 12962 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */ 12963 12964 /* Register: TEMP_A5 */ 12965 /* Description: Slope of 6th piece wise linear function */ 12966 12967 /* Bits 11..0 : Slope of 6th piece wise linear function */ 12968 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */ 12969 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */ 12970 12971 /* Register: TEMP_B0 */ 12972 /* Description: y-intercept of 1st piece wise linear function */ 12973 12974 /* Bits 13..0 : y-intercept of 1st piece wise linear function */ 12975 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */ 12976 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */ 12977 12978 /* Register: TEMP_B1 */ 12979 /* Description: y-intercept of 2nd piece wise linear function */ 12980 12981 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */ 12982 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */ 12983 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */ 12984 12985 /* Register: TEMP_B2 */ 12986 /* Description: y-intercept of 3rd piece wise linear function */ 12987 12988 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */ 12989 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */ 12990 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */ 12991 12992 /* Register: TEMP_B3 */ 12993 /* Description: y-intercept of 4th piece wise linear function */ 12994 12995 /* Bits 13..0 : y-intercept of 4th piece wise linear function */ 12996 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */ 12997 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */ 12998 12999 /* Register: TEMP_B4 */ 13000 /* Description: y-intercept of 5th piece wise linear function */ 13001 13002 /* Bits 13..0 : y-intercept of 5th piece wise linear function */ 13003 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */ 13004 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */ 13005 13006 /* Register: TEMP_B5 */ 13007 /* Description: y-intercept of 6th piece wise linear function */ 13008 13009 /* Bits 13..0 : y-intercept of 6th piece wise linear function */ 13010 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */ 13011 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */ 13012 13013 /* Register: TEMP_T0 */ 13014 /* Description: End point of 1st piece wise linear function */ 13015 13016 /* Bits 7..0 : End point of 1st piece wise linear function */ 13017 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */ 13018 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */ 13019 13020 /* Register: TEMP_T1 */ 13021 /* Description: End point of 2nd piece wise linear function */ 13022 13023 /* Bits 7..0 : End point of 2nd piece wise linear function */ 13024 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */ 13025 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */ 13026 13027 /* Register: TEMP_T2 */ 13028 /* Description: End point of 3rd piece wise linear function */ 13029 13030 /* Bits 7..0 : End point of 3rd piece wise linear function */ 13031 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */ 13032 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */ 13033 13034 /* Register: TEMP_T3 */ 13035 /* Description: End point of 4th piece wise linear function */ 13036 13037 /* Bits 7..0 : End point of 4th piece wise linear function */ 13038 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */ 13039 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */ 13040 13041 /* Register: TEMP_T4 */ 13042 /* Description: End point of 5th piece wise linear function */ 13043 13044 /* Bits 7..0 : End point of 5th piece wise linear function */ 13045 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */ 13046 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */ 13047 13048 13049 /* Peripheral: TIMER */ 13050 /* Description: Timer/Counter 0 */ 13051 13052 /* Register: TIMER_SHORTS */ 13053 /* Description: Shortcut register */ 13054 13055 /* Bit 13 : Shortcut between COMPARE[5] event and STOP task */ 13056 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */ 13057 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */ 13058 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */ 13059 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */ 13060 13061 /* Bit 12 : Shortcut between COMPARE[4] event and STOP task */ 13062 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */ 13063 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */ 13064 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */ 13065 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */ 13066 13067 /* Bit 11 : Shortcut between COMPARE[3] event and STOP task */ 13068 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ 13069 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ 13070 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */ 13071 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */ 13072 13073 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */ 13074 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ 13075 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ 13076 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */ 13077 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */ 13078 13079 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */ 13080 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ 13081 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ 13082 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */ 13083 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */ 13084 13085 /* Bit 8 : Shortcut between COMPARE[0] event and STOP task */ 13086 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ 13087 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 13088 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */ 13089 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */ 13090 13091 /* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */ 13092 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */ 13093 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */ 13094 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 13095 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 13096 13097 /* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */ 13098 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */ 13099 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */ 13100 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 13101 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 13102 13103 /* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */ 13104 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 13105 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 13106 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 13107 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 13108 13109 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */ 13110 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ 13111 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ 13112 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 13113 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 13114 13115 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */ 13116 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ 13117 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ 13118 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 13119 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 13120 13121 /* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */ 13122 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 13123 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 13124 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */ 13125 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */ 13126 13127 /* Register: TIMER_INTENSET */ 13128 /* Description: Enable interrupt */ 13129 13130 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */ 13131 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 13132 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 13133 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ 13134 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ 13135 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */ 13136 13137 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */ 13138 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 13139 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 13140 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ 13141 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ 13142 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */ 13143 13144 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */ 13145 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 13146 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 13147 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 13148 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 13149 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */ 13150 13151 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */ 13152 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 13153 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 13154 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 13155 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 13156 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */ 13157 13158 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */ 13159 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 13160 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 13161 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 13162 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 13163 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */ 13164 13165 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */ 13166 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 13167 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 13168 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 13169 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 13170 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */ 13171 13172 /* Register: TIMER_INTENCLR */ 13173 /* Description: Disable interrupt */ 13174 13175 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */ 13176 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */ 13177 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */ 13178 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */ 13179 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */ 13180 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */ 13181 13182 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */ 13183 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */ 13184 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */ 13185 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */ 13186 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */ 13187 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */ 13188 13189 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */ 13190 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 13191 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 13192 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */ 13193 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */ 13194 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */ 13195 13196 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */ 13197 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 13198 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 13199 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */ 13200 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */ 13201 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */ 13202 13203 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */ 13204 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 13205 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 13206 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */ 13207 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */ 13208 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */ 13209 13210 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */ 13211 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 13212 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 13213 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */ 13214 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */ 13215 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */ 13216 13217 /* Register: TIMER_MODE */ 13218 /* Description: Timer mode selection */ 13219 13220 /* Bits 1..0 : Timer mode */ 13221 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 13222 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 13223 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */ 13224 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */ 13225 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */ 13226 13227 /* Register: TIMER_BITMODE */ 13228 /* Description: Configure the number of bits used by the TIMER */ 13229 13230 /* Bits 1..0 : Timer bit width */ 13231 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 13232 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 13233 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */ 13234 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */ 13235 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */ 13236 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */ 13237 13238 /* Register: TIMER_PRESCALER */ 13239 /* Description: Timer prescaler register */ 13240 13241 /* Bits 3..0 : Prescaler value */ 13242 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 13243 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 13244 13245 /* Register: TIMER_CC */ 13246 /* Description: Description collection[0]: Capture/Compare register 0 */ 13247 13248 /* Bits 31..0 : Capture/Compare value */ 13249 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */ 13250 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */ 13251 13252 13253 /* Peripheral: TWI */ 13254 /* Description: I2C compatible Two-Wire Interface 0 */ 13255 13256 /* Register: TWI_SHORTS */ 13257 /* Description: Shortcut register */ 13258 13259 /* Bit 1 : Shortcut between BB event and STOP task */ 13260 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ 13261 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ 13262 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */ 13263 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */ 13264 13265 /* Bit 0 : Shortcut between BB event and SUSPEND task */ 13266 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ 13267 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ 13268 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 13269 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 13270 13271 /* Register: TWI_INTENSET */ 13272 /* Description: Enable interrupt */ 13273 13274 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ 13275 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 13276 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 13277 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 13278 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 13279 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ 13280 13281 /* Bit 14 : Write '1' to Enable interrupt for BB event */ 13282 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ 13283 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ 13284 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */ 13285 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */ 13286 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */ 13287 13288 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */ 13289 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 13290 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 13291 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 13292 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 13293 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */ 13294 13295 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */ 13296 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 13297 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 13298 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ 13299 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ 13300 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */ 13301 13302 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */ 13303 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 13304 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 13305 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ 13306 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ 13307 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */ 13308 13309 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ 13310 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 13311 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 13312 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 13313 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 13314 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 13315 13316 /* Register: TWI_INTENCLR */ 13317 /* Description: Disable interrupt */ 13318 13319 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ 13320 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 13321 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 13322 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 13323 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 13324 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ 13325 13326 /* Bit 14 : Write '1' to Disable interrupt for BB event */ 13327 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ 13328 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ 13329 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */ 13330 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */ 13331 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */ 13332 13333 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */ 13334 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 13335 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 13336 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 13337 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 13338 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 13339 13340 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */ 13341 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 13342 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 13343 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */ 13344 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */ 13345 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */ 13346 13347 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */ 13348 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 13349 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 13350 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */ 13351 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */ 13352 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */ 13353 13354 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ 13355 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 13356 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 13357 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 13358 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 13359 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 13360 13361 /* Register: TWI_ERRORSRC */ 13362 /* Description: Error source */ 13363 13364 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ 13365 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 13366 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 13367 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */ 13368 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */ 13369 13370 /* Bit 1 : NACK received after sending the address (write '1' to clear) */ 13371 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 13372 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 13373 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */ 13374 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */ 13375 13376 /* Bit 0 : Overrun error */ 13377 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 13378 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 13379 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */ 13380 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */ 13381 13382 /* Register: TWI_ENABLE */ 13383 /* Description: Enable TWI */ 13384 13385 /* Bits 3..0 : Enable or disable TWI */ 13386 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 13387 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 13388 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */ 13389 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */ 13390 13391 /* Register: TWI_PSELSCL */ 13392 /* Description: Pin select for SCL */ 13393 13394 /* Bits 31..0 : Pin number configuration for TWI SCL signal */ 13395 #define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */ 13396 #define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */ 13397 #define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 13398 13399 /* Register: TWI_PSELSDA */ 13400 /* Description: Pin select for SDA */ 13401 13402 /* Bits 31..0 : Pin number configuration for TWI SDA signal */ 13403 #define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */ 13404 #define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */ 13405 #define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 13406 13407 /* Register: TWI_RXD */ 13408 /* Description: RXD register */ 13409 13410 /* Bits 7..0 : RXD register */ 13411 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 13412 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 13413 13414 /* Register: TWI_TXD */ 13415 /* Description: TXD register */ 13416 13417 /* Bits 7..0 : TXD register */ 13418 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 13419 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 13420 13421 /* Register: TWI_FREQUENCY */ 13422 /* Description: TWI frequency */ 13423 13424 /* Bits 31..0 : TWI master clock frequency */ 13425 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 13426 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 13427 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ 13428 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 13429 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */ 13430 13431 /* Register: TWI_ADDRESS */ 13432 /* Description: Address used in the TWI transfer */ 13433 13434 /* Bits 6..0 : Address used in the TWI transfer */ 13435 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 13436 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 13437 13438 13439 /* Peripheral: TWIM */ 13440 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */ 13441 13442 /* Register: TWIM_SHORTS */ 13443 /* Description: Shortcut register */ 13444 13445 /* Bit 12 : Shortcut between LASTRX event and STOP task */ 13446 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */ 13447 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */ 13448 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */ 13449 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */ 13450 13451 /* Bit 10 : Shortcut between LASTRX event and STARTTX task */ 13452 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */ 13453 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */ 13454 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */ 13455 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */ 13456 13457 /* Bit 9 : Shortcut between LASTTX event and STOP task */ 13458 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */ 13459 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */ 13460 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */ 13461 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */ 13462 13463 /* Bit 8 : Shortcut between LASTTX event and SUSPEND task */ 13464 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */ 13465 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */ 13466 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 13467 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 13468 13469 /* Bit 7 : Shortcut between LASTTX event and STARTRX task */ 13470 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */ 13471 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */ 13472 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 13473 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 13474 13475 /* Register: TWIM_INTEN */ 13476 /* Description: Enable or disable interrupt */ 13477 13478 /* Bit 24 : Enable or disable interrupt for LASTTX event */ 13479 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 13480 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 13481 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */ 13482 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */ 13483 13484 /* Bit 23 : Enable or disable interrupt for LASTRX event */ 13485 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 13486 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 13487 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */ 13488 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */ 13489 13490 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */ 13491 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 13492 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 13493 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 13494 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 13495 13496 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */ 13497 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 13498 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 13499 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 13500 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 13501 13502 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */ 13503 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 13504 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 13505 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */ 13506 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */ 13507 13508 /* Bit 9 : Enable or disable interrupt for ERROR event */ 13509 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 13510 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 13511 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 13512 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 13513 13514 /* Bit 1 : Enable or disable interrupt for STOPPED event */ 13515 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 13516 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 13517 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 13518 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 13519 13520 /* Register: TWIM_INTENSET */ 13521 /* Description: Enable interrupt */ 13522 13523 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */ 13524 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 13525 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 13526 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */ 13527 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */ 13528 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */ 13529 13530 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */ 13531 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 13532 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 13533 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */ 13534 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */ 13535 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */ 13536 13537 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ 13538 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 13539 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 13540 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 13541 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 13542 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 13543 13544 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ 13545 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 13546 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 13547 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 13548 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 13549 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 13550 13551 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */ 13552 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 13553 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 13554 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 13555 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 13556 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */ 13557 13558 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */ 13559 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 13560 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 13561 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 13562 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 13563 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */ 13564 13565 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ 13566 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 13567 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 13568 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 13569 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 13570 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 13571 13572 /* Register: TWIM_INTENCLR */ 13573 /* Description: Disable interrupt */ 13574 13575 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */ 13576 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */ 13577 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */ 13578 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */ 13579 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */ 13580 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */ 13581 13582 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */ 13583 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */ 13584 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */ 13585 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */ 13586 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */ 13587 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */ 13588 13589 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ 13590 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 13591 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 13592 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 13593 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 13594 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 13595 13596 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ 13597 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 13598 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 13599 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 13600 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 13601 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 13602 13603 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */ 13604 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 13605 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 13606 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */ 13607 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */ 13608 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */ 13609 13610 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */ 13611 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 13612 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 13613 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 13614 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 13615 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 13616 13617 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ 13618 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 13619 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 13620 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 13621 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 13622 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 13623 13624 /* Register: TWIM_ERRORSRC */ 13625 /* Description: Error source */ 13626 13627 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */ 13628 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 13629 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 13630 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ 13631 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ 13632 13633 /* Bit 1 : NACK received after sending the address (write '1' to clear) */ 13634 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 13635 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 13636 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */ 13637 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */ 13638 13639 /* Register: TWIM_ENABLE */ 13640 /* Description: Enable TWIM */ 13641 13642 /* Bits 3..0 : Enable or disable TWIM */ 13643 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 13644 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 13645 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */ 13646 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */ 13647 13648 /* Register: TWIM_PSEL_SCL */ 13649 /* Description: Pin select for SCL signal */ 13650 13651 /* Bit 31 : Connection */ 13652 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 13653 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 13654 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 13655 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 13656 13657 /* Bits 4..0 : Pin number */ 13658 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 13659 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 13660 13661 /* Register: TWIM_PSEL_SDA */ 13662 /* Description: Pin select for SDA signal */ 13663 13664 /* Bit 31 : Connection */ 13665 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 13666 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 13667 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 13668 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 13669 13670 /* Bits 4..0 : Pin number */ 13671 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 13672 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 13673 13674 /* Register: TWIM_FREQUENCY */ 13675 /* Description: TWI frequency */ 13676 13677 /* Bits 31..0 : TWI master clock frequency */ 13678 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 13679 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 13680 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */ 13681 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */ 13682 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */ 13683 13684 /* Register: TWIM_RXD_PTR */ 13685 /* Description: Data pointer */ 13686 13687 /* Bits 31..0 : Data pointer */ 13688 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 13689 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 13690 13691 /* Register: TWIM_RXD_MAXCNT */ 13692 /* Description: Maximum number of bytes in receive buffer */ 13693 13694 /* Bits 7..0 : Maximum number of bytes in receive buffer */ 13695 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 13696 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 13697 13698 /* Register: TWIM_RXD_AMOUNT */ 13699 /* Description: Number of bytes transferred in the last transaction */ 13700 13701 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 13702 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 13703 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 13704 13705 /* Register: TWIM_RXD_LIST */ 13706 /* Description: EasyDMA list type */ 13707 13708 /* Bits 2..0 : List type */ 13709 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 13710 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 13711 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 13712 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 13713 13714 /* Register: TWIM_TXD_PTR */ 13715 /* Description: Data pointer */ 13716 13717 /* Bits 31..0 : Data pointer */ 13718 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 13719 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 13720 13721 /* Register: TWIM_TXD_MAXCNT */ 13722 /* Description: Maximum number of bytes in transmit buffer */ 13723 13724 /* Bits 7..0 : Maximum number of bytes in transmit buffer */ 13725 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 13726 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 13727 13728 /* Register: TWIM_TXD_AMOUNT */ 13729 /* Description: Number of bytes transferred in the last transaction */ 13730 13731 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */ 13732 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 13733 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 13734 13735 /* Register: TWIM_TXD_LIST */ 13736 /* Description: EasyDMA list type */ 13737 13738 /* Bits 2..0 : List type */ 13739 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */ 13740 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */ 13741 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */ 13742 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */ 13743 13744 /* Register: TWIM_ADDRESS */ 13745 /* Description: Address used in the TWI transfer */ 13746 13747 /* Bits 6..0 : Address used in the TWI transfer */ 13748 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 13749 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 13750 13751 13752 /* Peripheral: TWIS */ 13753 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */ 13754 13755 /* Register: TWIS_SHORTS */ 13756 /* Description: Shortcut register */ 13757 13758 /* Bit 14 : Shortcut between READ event and SUSPEND task */ 13759 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */ 13760 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */ 13761 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 13762 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 13763 13764 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */ 13765 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */ 13766 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */ 13767 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */ 13768 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */ 13769 13770 /* Register: TWIS_INTEN */ 13771 /* Description: Enable or disable interrupt */ 13772 13773 /* Bit 26 : Enable or disable interrupt for READ event */ 13774 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */ 13775 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */ 13776 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */ 13777 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */ 13778 13779 /* Bit 25 : Enable or disable interrupt for WRITE event */ 13780 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 13781 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */ 13782 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */ 13783 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */ 13784 13785 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */ 13786 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 13787 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 13788 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 13789 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 13790 13791 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */ 13792 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 13793 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 13794 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 13795 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 13796 13797 /* Bit 9 : Enable or disable interrupt for ERROR event */ 13798 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 13799 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 13800 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 13801 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 13802 13803 /* Bit 1 : Enable or disable interrupt for STOPPED event */ 13804 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 13805 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 13806 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */ 13807 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */ 13808 13809 /* Register: TWIS_INTENSET */ 13810 /* Description: Enable interrupt */ 13811 13812 /* Bit 26 : Write '1' to Enable interrupt for READ event */ 13813 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */ 13814 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */ 13815 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */ 13816 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */ 13817 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */ 13818 13819 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */ 13820 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 13821 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */ 13822 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */ 13823 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */ 13824 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */ 13825 13826 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ 13827 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 13828 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 13829 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 13830 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 13831 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 13832 13833 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ 13834 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 13835 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 13836 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 13837 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 13838 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 13839 13840 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */ 13841 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 13842 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 13843 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 13844 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 13845 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */ 13846 13847 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */ 13848 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 13849 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 13850 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 13851 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 13852 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */ 13853 13854 /* Register: TWIS_INTENCLR */ 13855 /* Description: Disable interrupt */ 13856 13857 /* Bit 26 : Write '1' to Disable interrupt for READ event */ 13858 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */ 13859 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */ 13860 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */ 13861 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */ 13862 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */ 13863 13864 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */ 13865 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */ 13866 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */ 13867 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */ 13868 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */ 13869 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */ 13870 13871 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ 13872 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 13873 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 13874 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 13875 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 13876 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 13877 13878 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ 13879 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 13880 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 13881 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 13882 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 13883 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 13884 13885 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */ 13886 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 13887 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 13888 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 13889 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 13890 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 13891 13892 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */ 13893 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 13894 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 13895 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */ 13896 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */ 13897 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */ 13898 13899 /* Register: TWIS_ERRORSRC */ 13900 /* Description: Error source */ 13901 13902 /* Bit 3 : TX buffer over-read detected, and prevented */ 13903 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */ 13904 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 13905 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */ 13906 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */ 13907 13908 /* Bit 2 : NACK sent after receiving a data byte */ 13909 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 13910 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 13911 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */ 13912 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */ 13913 13914 /* Bit 0 : RX buffer overflow detected, and prevented */ 13915 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */ 13916 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 13917 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */ 13918 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */ 13919 13920 /* Register: TWIS_MATCH */ 13921 /* Description: Status register indicating which address had a match */ 13922 13923 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */ 13924 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */ 13925 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */ 13926 13927 /* Register: TWIS_ENABLE */ 13928 /* Description: Enable TWIS */ 13929 13930 /* Bits 3..0 : Enable or disable TWIS */ 13931 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 13932 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 13933 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */ 13934 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */ 13935 13936 /* Register: TWIS_PSEL_SCL */ 13937 /* Description: Pin select for SCL signal */ 13938 13939 /* Bit 31 : Connection */ 13940 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 13941 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 13942 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */ 13943 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */ 13944 13945 /* Bits 4..0 : Pin number */ 13946 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */ 13947 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */ 13948 13949 /* Register: TWIS_PSEL_SDA */ 13950 /* Description: Pin select for SDA signal */ 13951 13952 /* Bit 31 : Connection */ 13953 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 13954 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 13955 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */ 13956 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */ 13957 13958 /* Bits 4..0 : Pin number */ 13959 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */ 13960 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */ 13961 13962 /* Register: TWIS_RXD_PTR */ 13963 /* Description: RXD Data pointer */ 13964 13965 /* Bits 31..0 : RXD Data pointer */ 13966 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 13967 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 13968 13969 /* Register: TWIS_RXD_MAXCNT */ 13970 /* Description: Maximum number of bytes in RXD buffer */ 13971 13972 /* Bits 7..0 : Maximum number of bytes in RXD buffer */ 13973 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 13974 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 13975 13976 /* Register: TWIS_RXD_AMOUNT */ 13977 /* Description: Number of bytes transferred in the last RXD transaction */ 13978 13979 /* Bits 7..0 : Number of bytes transferred in the last RXD transaction */ 13980 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 13981 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 13982 13983 /* Register: TWIS_TXD_PTR */ 13984 /* Description: TXD Data pointer */ 13985 13986 /* Bits 31..0 : TXD Data pointer */ 13987 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 13988 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 13989 13990 /* Register: TWIS_TXD_MAXCNT */ 13991 /* Description: Maximum number of bytes in TXD buffer */ 13992 13993 /* Bits 7..0 : Maximum number of bytes in TXD buffer */ 13994 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 13995 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 13996 13997 /* Register: TWIS_TXD_AMOUNT */ 13998 /* Description: Number of bytes transferred in the last TXD transaction */ 13999 14000 /* Bits 7..0 : Number of bytes transferred in the last TXD transaction */ 14001 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 14002 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 14003 14004 /* Register: TWIS_ADDRESS */ 14005 /* Description: Description collection[0]: TWI slave address 0 */ 14006 14007 /* Bits 6..0 : TWI slave address */ 14008 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 14009 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 14010 14011 /* Register: TWIS_CONFIG */ 14012 /* Description: Configuration register for the address match mechanism */ 14013 14014 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */ 14015 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */ 14016 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */ 14017 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */ 14018 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */ 14019 14020 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */ 14021 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */ 14022 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */ 14023 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */ 14024 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */ 14025 14026 /* Register: TWIS_ORC */ 14027 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 14028 14029 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */ 14030 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 14031 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 14032 14033 14034 /* Peripheral: UART */ 14035 /* Description: Universal Asynchronous Receiver/Transmitter */ 14036 14037 /* Register: UART_SHORTS */ 14038 /* Description: Shortcut register */ 14039 14040 /* Bit 4 : Shortcut between NCTS event and STOPRX task */ 14041 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ 14042 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ 14043 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */ 14044 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */ 14045 14046 /* Bit 3 : Shortcut between CTS event and STARTRX task */ 14047 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ 14048 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ 14049 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 14050 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 14051 14052 /* Register: UART_INTENSET */ 14053 /* Description: Enable interrupt */ 14054 14055 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */ 14056 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 14057 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 14058 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ 14059 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ 14060 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */ 14061 14062 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */ 14063 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14064 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14065 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 14066 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 14067 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */ 14068 14069 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */ 14070 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 14071 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 14072 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 14073 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 14074 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */ 14075 14076 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */ 14077 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 14078 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 14079 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 14080 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 14081 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */ 14082 14083 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */ 14084 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 14085 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 14086 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ 14087 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ 14088 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */ 14089 14090 /* Bit 0 : Write '1' to Enable interrupt for CTS event */ 14091 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 14092 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 14093 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ 14094 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ 14095 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */ 14096 14097 /* Register: UART_INTENCLR */ 14098 /* Description: Disable interrupt */ 14099 14100 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */ 14101 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 14102 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 14103 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ 14104 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ 14105 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ 14106 14107 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */ 14108 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14109 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14110 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 14111 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 14112 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 14113 14114 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */ 14115 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 14116 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 14117 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */ 14118 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */ 14119 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */ 14120 14121 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */ 14122 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 14123 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 14124 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */ 14125 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */ 14126 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */ 14127 14128 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */ 14129 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 14130 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 14131 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ 14132 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ 14133 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ 14134 14135 /* Bit 0 : Write '1' to Disable interrupt for CTS event */ 14136 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 14137 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 14138 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ 14139 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ 14140 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */ 14141 14142 /* Register: UART_ERRORSRC */ 14143 /* Description: Error source */ 14144 14145 /* Bit 3 : Break condition */ 14146 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 14147 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 14148 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ 14149 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ 14150 14151 /* Bit 2 : Framing error occurred */ 14152 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 14153 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 14154 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ 14155 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ 14156 14157 /* Bit 1 : Parity error */ 14158 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 14159 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 14160 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ 14161 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ 14162 14163 /* Bit 0 : Overrun error */ 14164 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 14165 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 14166 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ 14167 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ 14168 14169 /* Register: UART_ENABLE */ 14170 /* Description: Enable UART */ 14171 14172 /* Bits 3..0 : Enable or disable UART */ 14173 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 14174 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 14175 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */ 14176 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */ 14177 14178 /* Register: UART_PSELRTS */ 14179 /* Description: Pin select for RTS */ 14180 14181 /* Bits 31..0 : Pin number configuration for UART RTS signal */ 14182 #define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */ 14183 #define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */ 14184 #define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 14185 14186 /* Register: UART_PSELTXD */ 14187 /* Description: Pin select for TXD */ 14188 14189 /* Bits 31..0 : Pin number configuration for UART TXD signal */ 14190 #define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */ 14191 #define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */ 14192 #define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 14193 14194 /* Register: UART_PSELCTS */ 14195 /* Description: Pin select for CTS */ 14196 14197 /* Bits 31..0 : Pin number configuration for UART CTS signal */ 14198 #define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */ 14199 #define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */ 14200 #define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 14201 14202 /* Register: UART_PSELRXD */ 14203 /* Description: Pin select for RXD */ 14204 14205 /* Bits 31..0 : Pin number configuration for UART RXD signal */ 14206 #define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */ 14207 #define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */ 14208 #define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */ 14209 14210 /* Register: UART_RXD */ 14211 /* Description: RXD register */ 14212 14213 /* Bits 7..0 : RX data received in previous transfers, double buffered */ 14214 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 14215 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 14216 14217 /* Register: UART_TXD */ 14218 /* Description: TXD register */ 14219 14220 /* Bits 7..0 : TX data to be transferred */ 14221 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 14222 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 14223 14224 /* Register: UART_BAUDRATE */ 14225 /* Description: Baud rate */ 14226 14227 /* Bits 31..0 : Baud-rate */ 14228 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 14229 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 14230 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 14231 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 14232 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 14233 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 14234 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */ 14235 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 14236 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */ 14237 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */ 14238 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */ 14239 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 14240 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */ 14241 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */ 14242 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 14243 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */ 14244 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */ 14245 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ 14246 14247 /* Register: UART_CONFIG */ 14248 /* Description: Configuration of parity and hardware flow control */ 14249 14250 /* Bits 3..1 : Parity */ 14251 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 14252 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 14253 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 14254 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ 14255 14256 /* Bit 0 : Hardware flow control */ 14257 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 14258 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 14259 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ 14260 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ 14261 14262 14263 /* Peripheral: UARTE */ 14264 /* Description: UART with EasyDMA */ 14265 14266 /* Register: UARTE_SHORTS */ 14267 /* Description: Shortcut register */ 14268 14269 /* Bit 6 : Shortcut between ENDRX event and STOPRX task */ 14270 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */ 14271 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */ 14272 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */ 14273 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */ 14274 14275 /* Bit 5 : Shortcut between ENDRX event and STARTRX task */ 14276 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */ 14277 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */ 14278 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */ 14279 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */ 14280 14281 /* Register: UARTE_INTEN */ 14282 /* Description: Enable or disable interrupt */ 14283 14284 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */ 14285 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 14286 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 14287 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */ 14288 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */ 14289 14290 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */ 14291 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 14292 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 14293 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */ 14294 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */ 14295 14296 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */ 14297 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 14298 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 14299 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */ 14300 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */ 14301 14302 /* Bit 17 : Enable or disable interrupt for RXTO event */ 14303 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 14304 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */ 14305 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */ 14306 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */ 14307 14308 /* Bit 9 : Enable or disable interrupt for ERROR event */ 14309 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14310 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14311 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */ 14312 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */ 14313 14314 /* Bit 8 : Enable or disable interrupt for ENDTX event */ 14315 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 14316 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 14317 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */ 14318 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */ 14319 14320 /* Bit 4 : Enable or disable interrupt for ENDRX event */ 14321 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 14322 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 14323 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */ 14324 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */ 14325 14326 /* Bit 1 : Enable or disable interrupt for NCTS event */ 14327 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 14328 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */ 14329 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */ 14330 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */ 14331 14332 /* Bit 0 : Enable or disable interrupt for CTS event */ 14333 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */ 14334 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */ 14335 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */ 14336 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */ 14337 14338 /* Register: UARTE_INTENSET */ 14339 /* Description: Enable interrupt */ 14340 14341 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */ 14342 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 14343 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 14344 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 14345 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 14346 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */ 14347 14348 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */ 14349 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 14350 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 14351 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 14352 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 14353 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */ 14354 14355 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */ 14356 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 14357 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 14358 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 14359 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 14360 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */ 14361 14362 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */ 14363 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 14364 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 14365 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */ 14366 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */ 14367 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */ 14368 14369 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */ 14370 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14371 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14372 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */ 14373 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */ 14374 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */ 14375 14376 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */ 14377 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 14378 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 14379 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 14380 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 14381 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */ 14382 14383 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */ 14384 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 14385 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 14386 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 14387 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 14388 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */ 14389 14390 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */ 14391 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 14392 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 14393 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */ 14394 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */ 14395 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */ 14396 14397 /* Bit 0 : Write '1' to Enable interrupt for CTS event */ 14398 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 14399 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 14400 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */ 14401 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */ 14402 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */ 14403 14404 /* Register: UARTE_INTENCLR */ 14405 /* Description: Disable interrupt */ 14406 14407 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */ 14408 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */ 14409 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */ 14410 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */ 14411 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */ 14412 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */ 14413 14414 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */ 14415 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */ 14416 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */ 14417 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 14418 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 14419 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */ 14420 14421 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */ 14422 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */ 14423 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */ 14424 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */ 14425 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */ 14426 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */ 14427 14428 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */ 14429 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 14430 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 14431 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */ 14432 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */ 14433 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */ 14434 14435 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */ 14436 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 14437 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 14438 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */ 14439 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */ 14440 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */ 14441 14442 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */ 14443 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 14444 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 14445 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */ 14446 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */ 14447 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */ 14448 14449 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */ 14450 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 14451 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 14452 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */ 14453 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */ 14454 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */ 14455 14456 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */ 14457 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 14458 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 14459 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */ 14460 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */ 14461 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */ 14462 14463 /* Bit 0 : Write '1' to Disable interrupt for CTS event */ 14464 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 14465 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 14466 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */ 14467 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */ 14468 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */ 14469 14470 /* Register: UARTE_ERRORSRC */ 14471 /* Description: Error source */ 14472 14473 /* Bit 3 : Break condition */ 14474 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 14475 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 14476 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */ 14477 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */ 14478 14479 /* Bit 2 : Framing error occurred */ 14480 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 14481 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 14482 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */ 14483 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */ 14484 14485 /* Bit 1 : Parity error */ 14486 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 14487 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 14488 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */ 14489 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */ 14490 14491 /* Bit 0 : Overrun error */ 14492 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 14493 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 14494 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */ 14495 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */ 14496 14497 /* Register: UARTE_ENABLE */ 14498 /* Description: Enable UART */ 14499 14500 /* Bits 3..0 : Enable or disable UARTE */ 14501 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 14502 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 14503 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */ 14504 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */ 14505 14506 /* Register: UARTE_PSEL_RTS */ 14507 /* Description: Pin select for RTS signal */ 14508 14509 /* Bit 31 : Connection */ 14510 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 14511 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 14512 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */ 14513 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 14514 14515 /* Bits 4..0 : Pin number */ 14516 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 14517 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */ 14518 14519 /* Register: UARTE_PSEL_TXD */ 14520 /* Description: Pin select for TXD signal */ 14521 14522 /* Bit 31 : Connection */ 14523 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 14524 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 14525 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */ 14526 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 14527 14528 /* Bits 4..0 : Pin number */ 14529 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 14530 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */ 14531 14532 /* Register: UARTE_PSEL_CTS */ 14533 /* Description: Pin select for CTS signal */ 14534 14535 /* Bit 31 : Connection */ 14536 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 14537 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 14538 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */ 14539 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */ 14540 14541 /* Bits 4..0 : Pin number */ 14542 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */ 14543 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */ 14544 14545 /* Register: UARTE_PSEL_RXD */ 14546 /* Description: Pin select for RXD signal */ 14547 14548 /* Bit 31 : Connection */ 14549 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 14550 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 14551 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */ 14552 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */ 14553 14554 /* Bits 4..0 : Pin number */ 14555 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */ 14556 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */ 14557 14558 /* Register: UARTE_BAUDRATE */ 14559 /* Description: Baud rate */ 14560 14561 /* Bits 31..0 : Baud-rate */ 14562 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 14563 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 14564 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */ 14565 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */ 14566 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */ 14567 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */ 14568 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */ 14569 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */ 14570 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */ 14571 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */ 14572 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */ 14573 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */ 14574 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */ 14575 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */ 14576 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */ 14577 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */ 14578 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */ 14579 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */ 14580 14581 /* Register: UARTE_RXD_PTR */ 14582 /* Description: Data pointer */ 14583 14584 /* Bits 31..0 : Data pointer */ 14585 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 14586 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 14587 14588 /* Register: UARTE_RXD_MAXCNT */ 14589 /* Description: Maximum number of bytes in receive buffer */ 14590 14591 /* Bits 7..0 : Maximum number of bytes in receive buffer */ 14592 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 14593 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 14594 14595 /* Register: UARTE_RXD_AMOUNT */ 14596 /* Description: Number of bytes transferred in the last transaction */ 14597 14598 /* Bits 7..0 : Number of bytes transferred in the last transaction */ 14599 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 14600 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 14601 14602 /* Register: UARTE_TXD_PTR */ 14603 /* Description: Data pointer */ 14604 14605 /* Bits 31..0 : Data pointer */ 14606 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 14607 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 14608 14609 /* Register: UARTE_TXD_MAXCNT */ 14610 /* Description: Maximum number of bytes in transmit buffer */ 14611 14612 /* Bits 7..0 : Maximum number of bytes in transmit buffer */ 14613 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 14614 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 14615 14616 /* Register: UARTE_TXD_AMOUNT */ 14617 /* Description: Number of bytes transferred in the last transaction */ 14618 14619 /* Bits 7..0 : Number of bytes transferred in the last transaction */ 14620 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 14621 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 14622 14623 /* Register: UARTE_CONFIG */ 14624 /* Description: Configuration of parity and hardware flow control */ 14625 14626 /* Bits 3..1 : Parity */ 14627 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 14628 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 14629 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */ 14630 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */ 14631 14632 /* Bit 0 : Hardware flow control */ 14633 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 14634 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 14635 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */ 14636 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */ 14637 14638 14639 /* Peripheral: UICR */ 14640 /* Description: User Information Configuration Registers */ 14641 14642 /* Register: UICR_NRFFW */ 14643 /* Description: Description collection[0]: Reserved for Nordic firmware design */ 14644 14645 /* Bits 31..0 : Reserved for Nordic firmware design */ 14646 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */ 14647 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */ 14648 14649 /* Register: UICR_NRFHW */ 14650 /* Description: Description collection[0]: Reserved for Nordic hardware design */ 14651 14652 /* Bits 31..0 : Reserved for Nordic hardware design */ 14653 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */ 14654 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */ 14655 14656 /* Register: UICR_CUSTOMER */ 14657 /* Description: Description collection[0]: Reserved for customer */ 14658 14659 /* Bits 31..0 : Reserved for customer */ 14660 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */ 14661 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */ 14662 14663 /* Register: UICR_PSELRESET */ 14664 /* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */ 14665 14666 /* Bit 31 : Connection */ 14667 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */ 14668 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */ 14669 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */ 14670 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */ 14671 14672 /* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */ 14673 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */ 14674 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */ 14675 14676 /* Register: UICR_APPROTECT */ 14677 /* Description: Access Port protection */ 14678 14679 /* Bits 7..0 : Enable or disable Access Port protection. */ 14680 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */ 14681 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */ 14682 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */ 14683 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */ 14684 14685 /* Register: UICR_NFCPINS */ 14686 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */ 14687 14688 /* Bit 0 : Setting of pins dedicated to NFC functionality */ 14689 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */ 14690 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */ 14691 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */ 14692 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */ 14693 14694 14695 /* Peripheral: WDT */ 14696 /* Description: Watchdog Timer */ 14697 14698 /* Register: WDT_INTENSET */ 14699 /* Description: Enable interrupt */ 14700 14701 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */ 14702 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 14703 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 14704 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ 14705 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ 14706 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */ 14707 14708 /* Register: WDT_INTENCLR */ 14709 /* Description: Disable interrupt */ 14710 14711 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */ 14712 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 14713 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 14714 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */ 14715 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */ 14716 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */ 14717 14718 /* Register: WDT_RUNSTATUS */ 14719 /* Description: Run status */ 14720 14721 /* Bit 0 : Indicates whether or not the watchdog is running */ 14722 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ 14723 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ 14724 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */ 14725 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */ 14726 14727 /* Register: WDT_REQSTATUS */ 14728 /* Description: Request status */ 14729 14730 /* Bit 7 : Request status for RR[7] register */ 14731 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ 14732 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ 14733 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */ 14734 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */ 14735 14736 /* Bit 6 : Request status for RR[6] register */ 14737 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ 14738 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ 14739 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */ 14740 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */ 14741 14742 /* Bit 5 : Request status for RR[5] register */ 14743 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ 14744 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ 14745 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */ 14746 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */ 14747 14748 /* Bit 4 : Request status for RR[4] register */ 14749 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ 14750 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ 14751 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */ 14752 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */ 14753 14754 /* Bit 3 : Request status for RR[3] register */ 14755 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ 14756 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ 14757 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */ 14758 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */ 14759 14760 /* Bit 2 : Request status for RR[2] register */ 14761 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ 14762 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ 14763 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */ 14764 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */ 14765 14766 /* Bit 1 : Request status for RR[1] register */ 14767 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ 14768 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ 14769 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */ 14770 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */ 14771 14772 /* Bit 0 : Request status for RR[0] register */ 14773 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ 14774 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ 14775 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */ 14776 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */ 14777 14778 /* Register: WDT_CRV */ 14779 /* Description: Counter reload value */ 14780 14781 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */ 14782 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */ 14783 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */ 14784 14785 /* Register: WDT_RREN */ 14786 /* Description: Enable register for reload request registers */ 14787 14788 /* Bit 7 : Enable or disable RR[7] register */ 14789 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ 14790 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ 14791 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */ 14792 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */ 14793 14794 /* Bit 6 : Enable or disable RR[6] register */ 14795 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ 14796 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ 14797 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */ 14798 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */ 14799 14800 /* Bit 5 : Enable or disable RR[5] register */ 14801 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ 14802 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ 14803 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */ 14804 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */ 14805 14806 /* Bit 4 : Enable or disable RR[4] register */ 14807 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ 14808 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ 14809 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */ 14810 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */ 14811 14812 /* Bit 3 : Enable or disable RR[3] register */ 14813 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ 14814 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ 14815 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */ 14816 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */ 14817 14818 /* Bit 2 : Enable or disable RR[2] register */ 14819 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ 14820 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ 14821 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */ 14822 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */ 14823 14824 /* Bit 1 : Enable or disable RR[1] register */ 14825 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ 14826 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ 14827 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */ 14828 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */ 14829 14830 /* Bit 0 : Enable or disable RR[0] register */ 14831 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ 14832 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ 14833 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */ 14834 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */ 14835 14836 /* Register: WDT_CONFIG */ 14837 /* Description: Configuration register */ 14838 14839 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */ 14840 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ 14841 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ 14842 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */ 14843 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */ 14844 14845 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */ 14846 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ 14847 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ 14848 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */ 14849 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */ 14850 14851 /* Register: WDT_RR */ 14852 /* Description: Description collection[0]: Reload request 0 */ 14853 14854 /* Bits 31..0 : Reload request register */ 14855 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ 14856 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ 14857 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */ 14858 14859 14860 /*lint --flb "Leave library region" */ 14861 #endif 14862
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