Taouil Yassine
/
nrf52-sdk
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nrf51-sdk
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nrf51_to_nrf52.h
00001 /* Copyright (c) 2015, Nordic Semiconductor ASA 00002 * All rights reserved. 00003 * 00004 * Redistribution and use in source and binary forms, with or without 00005 * modification, are permitted provided that the following conditions are met: 00006 * 00007 * * Redistributions of source code must retain the above copyright notice, this 00008 * list of conditions and the following disclaimer. 00009 * 00010 * * Redistributions in binary form must reproduce the above copyright notice, 00011 * this list of conditions and the following disclaimer in the documentation 00012 * and/or other materials provided with the distribution. 00013 * 00014 * * Neither the name of Nordic Semiconductor ASA nor the names of its 00015 * contributors may be used to endorse or promote products derived from 00016 * this software without specific prior written permission. 00017 * 00018 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00019 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00020 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00021 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00022 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00023 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00024 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00025 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00026 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00027 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00028 * 00029 */ 00030 00031 #ifndef NRF51_TO_NRF52_H 00032 #define NRF51_TO_NRF52_H 00033 00034 /*lint ++flb "Enter library region */ 00035 00036 /* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices. 00037 * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the 00038 * functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros 00039 * from the nrf51_deprecated.h file. */ 00040 00041 00042 /* IRQ */ 00043 /* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */ 00044 #define UART0_IRQHandler UARTE0_UART0_IRQHandler 00045 #define SPI0_TWI0_IRQHandler SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler 00046 #define SPI1_TWI1_IRQHandler SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler 00047 #define ADC_IRQHandler SAADC_IRQHandler 00048 #define LPCOMP_IRQHandler COMP_LPCOMP_IRQHandler 00049 #define SWI0_IRQHandler SWI0_EGU0_IRQHandler 00050 #define SWI1_IRQHandler SWI1_EGU1_IRQHandler 00051 #define SWI2_IRQHandler SWI2_EGU2_IRQHandler 00052 #define SWI3_IRQHandler SWI3_EGU3_IRQHandler 00053 #define SWI4_IRQHandler SWI4_EGU4_IRQHandler 00054 #define SWI5_IRQHandler SWI5_EGU5_IRQHandler 00055 00056 #define UART0_IRQn UARTE0_UART0_IRQn 00057 #define SPI0_TWI0_IRQn SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn 00058 #define SPI1_TWI1_IRQn SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn 00059 #define ADC_IRQn SAADC_IRQn 00060 #define LPCOMP_IRQn COMP_LPCOMP_IRQn 00061 #define SWI0_IRQn SWI0_EGU0_IRQn 00062 #define SWI1_IRQn SWI1_EGU1_IRQn 00063 #define SWI2_IRQn SWI2_EGU2_IRQn 00064 #define SWI3_IRQn SWI3_EGU3_IRQn 00065 #define SWI4_IRQn SWI4_EGU4_IRQn 00066 #define SWI5_IRQn SWI5_EGU5_IRQn 00067 00068 00069 /* UICR */ 00070 /* Register RBPCONF was renamed to APPROTECT. */ 00071 #define RBPCONF APPROTECT 00072 00073 #define UICR_RBPCONF_PALL_Pos UICR_APPROTECT_PALL_Pos 00074 #define UICR_RBPCONF_PALL_Msk UICR_APPROTECT_PALL_Msk 00075 #define UICR_RBPCONF_PALL_Enabled UICR_APPROTECT_PALL_Enabled 00076 #define UICR_RBPCONF_PALL_Disabled UICR_APPROTECT_PALL_Disabled 00077 00078 00079 /* GPIO */ 00080 /* GPIO port was renamed to P0. */ 00081 #define NRF_GPIO NRF_P0 00082 #define NRF_GPIO_BASE NRF_P0_BASE 00083 00084 00085 /* SPIS */ 00086 /* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */ 00087 #define PSELSCK PSEL.SCK 00088 #define PSELMISO PSEL.MISO 00089 #define PSELMOSI PSEL.MOSI 00090 #define PSELCSN PSEL.CSN 00091 00092 /* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */ 00093 #define RXDPTR RXD.PTR 00094 #define MAXRX RXD.MAXCNT 00095 #define AMOUNTRX RXD.AMOUNT 00096 00097 #define SPIS_MAXRX_MAXRX_Pos SPIS_RXD_MAXCNT_MAXCNT_Pos 00098 #define SPIS_MAXRX_MAXRX_Msk SPIS_RXD_MAXCNT_MAXCNT_Msk 00099 00100 #define SPIS_AMOUNTRX_AMOUNTRX_Pos SPIS_RXD_AMOUNT_AMOUNT_Pos 00101 #define SPIS_AMOUNTRX_AMOUNTRX_Msk SPIS_RXD_AMOUNT_AMOUNT_Msk 00102 00103 /* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */ 00104 #define TXDPTR TXD.PTR 00105 #define MAXTX TXD.MAXCNT 00106 #define AMOUNTTX TXD.AMOUNT 00107 00108 #define SPIS_MAXTX_MAXTX_Pos SPIS_TXD_MAXCNT_MAXCNT_Pos 00109 #define SPIS_MAXTX_MAXTX_Msk SPIS_TXD_MAXCNT_MAXCNT_Msk 00110 00111 #define SPIS_AMOUNTTX_AMOUNTTX_Pos SPIS_TXD_AMOUNT_AMOUNT_Pos 00112 #define SPIS_AMOUNTTX_AMOUNTTX_Msk SPIS_TXD_AMOUNT_AMOUNT_Msk 00113 00114 00115 /* MPU */ 00116 /* Part of MPU module was renamed BPROT, while the rest was eliminated. */ 00117 #define NRF_MPU NRF_BPROT 00118 00119 /* Register DISABLEINDEBUG macros were affected. */ 00120 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos 00121 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk 00122 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled 00123 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled 00124 00125 /* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */ 00126 #define PROTENSET0 CONFIG0 00127 #define PROTENSET1 CONFIG1 00128 00129 #define MPU_PROTENSET1_PROTREG63_Pos BPROT_CONFIG1_REGION63_Pos 00130 #define MPU_PROTENSET1_PROTREG63_Msk BPROT_CONFIG1_REGION63_Msk 00131 #define MPU_PROTENSET1_PROTREG63_Disabled BPROT_CONFIG1_REGION63_Disabled 00132 #define MPU_PROTENSET1_PROTREG63_Enabled BPROT_CONFIG1_REGION63_Enabled 00133 #define MPU_PROTENSET1_PROTREG63_Set BPROT_CONFIG1_REGION63_Enabled 00134 00135 #define MPU_PROTENSET1_PROTREG62_Pos BPROT_CONFIG1_REGION62_Pos 00136 #define MPU_PROTENSET1_PROTREG62_Msk BPROT_CONFIG1_REGION62_Msk 00137 #define MPU_PROTENSET1_PROTREG62_Disabled BPROT_CONFIG1_REGION62_Disabled 00138 #define MPU_PROTENSET1_PROTREG62_Enabled BPROT_CONFIG1_REGION62_Enabled 00139 #define MPU_PROTENSET1_PROTREG62_Set BPROT_CONFIG1_REGION62_Enabled 00140 00141 #define MPU_PROTENSET1_PROTREG61_Pos BPROT_CONFIG1_REGION61_Pos 00142 #define MPU_PROTENSET1_PROTREG61_Msk BPROT_CONFIG1_REGION61_Msk 00143 #define MPU_PROTENSET1_PROTREG61_Disabled BPROT_CONFIG1_REGION61_Disabled 00144 #define MPU_PROTENSET1_PROTREG61_Enabled BPROT_CONFIG1_REGION61_Enabled 00145 #define MPU_PROTENSET1_PROTREG61_Set BPROT_CONFIG1_REGION61_Enabled 00146 00147 #define MPU_PROTENSET1_PROTREG60_Pos BPROT_CONFIG1_REGION60_Pos 00148 #define MPU_PROTENSET1_PROTREG60_Msk BPROT_CONFIG1_REGION60_Msk 00149 #define MPU_PROTENSET1_PROTREG60_Disabled BPROT_CONFIG1_REGION60_Disabled 00150 #define MPU_PROTENSET1_PROTREG60_Enabled BPROT_CONFIG1_REGION60_Enabled 00151 #define MPU_PROTENSET1_PROTREG60_Set BPROT_CONFIG1_REGION60_Enabled 00152 00153 #define MPU_PROTENSET1_PROTREG59_Pos BPROT_CONFIG1_REGION59_Pos 00154 #define MPU_PROTENSET1_PROTREG59_Msk BPROT_CONFIG1_REGION59_Msk 00155 #define MPU_PROTENSET1_PROTREG59_Disabled BPROT_CONFIG1_REGION59_Disabled 00156 #define MPU_PROTENSET1_PROTREG59_Enabled BPROT_CONFIG1_REGION59_Enabled 00157 #define MPU_PROTENSET1_PROTREG59_Set BPROT_CONFIG1_REGION59_Enabled 00158 00159 #define MPU_PROTENSET1_PROTREG58_Pos BPROT_CONFIG1_REGION58_Pos 00160 #define MPU_PROTENSET1_PROTREG58_Msk BPROT_CONFIG1_REGION58_Msk 00161 #define MPU_PROTENSET1_PROTREG58_Disabled BPROT_CONFIG1_REGION58_Disabled 00162 #define MPU_PROTENSET1_PROTREG58_Enabled BPROT_CONFIG1_REGION58_Enabled 00163 #define MPU_PROTENSET1_PROTREG58_Set BPROT_CONFIG1_REGION58_Enabled 00164 00165 #define MPU_PROTENSET1_PROTREG57_Pos BPROT_CONFIG1_REGION57_Pos 00166 #define MPU_PROTENSET1_PROTREG57_Msk BPROT_CONFIG1_REGION57_Msk 00167 #define MPU_PROTENSET1_PROTREG57_Disabled BPROT_CONFIG1_REGION57_Disabled 00168 #define MPU_PROTENSET1_PROTREG57_Enabled BPROT_CONFIG1_REGION57_Enabled 00169 #define MPU_PROTENSET1_PROTREG57_Set BPROT_CONFIG1_REGION57_Enabled 00170 00171 #define MPU_PROTENSET1_PROTREG56_Pos BPROT_CONFIG1_REGION56_Pos 00172 #define MPU_PROTENSET1_PROTREG56_Msk BPROT_CONFIG1_REGION56_Msk 00173 #define MPU_PROTENSET1_PROTREG56_Disabled BPROT_CONFIG1_REGION56_Disabled 00174 #define MPU_PROTENSET1_PROTREG56_Enabled BPROT_CONFIG1_REGION56_Enabled 00175 #define MPU_PROTENSET1_PROTREG56_Set BPROT_CONFIG1_REGION56_Enabled 00176 00177 #define MPU_PROTENSET1_PROTREG55_Pos BPROT_CONFIG1_REGION55_Pos 00178 #define MPU_PROTENSET1_PROTREG55_Msk BPROT_CONFIG1_REGION55_Msk 00179 #define MPU_PROTENSET1_PROTREG55_Disabled BPROT_CONFIG1_REGION55_Disabled 00180 #define MPU_PROTENSET1_PROTREG55_Enabled BPROT_CONFIG1_REGION55_Enabled 00181 #define MPU_PROTENSET1_PROTREG55_Set BPROT_CONFIG1_REGION55_Enabled 00182 00183 #define MPU_PROTENSET1_PROTREG54_Pos BPROT_CONFIG1_REGION54_Pos 00184 #define MPU_PROTENSET1_PROTREG54_Msk BPROT_CONFIG1_REGION54_Msk 00185 #define MPU_PROTENSET1_PROTREG54_Disabled BPROT_CONFIG1_REGION54_Disabled 00186 #define MPU_PROTENSET1_PROTREG54_Enabled BPROT_CONFIG1_REGION54_Enabled 00187 #define MPU_PROTENSET1_PROTREG54_Set BPROT_CONFIG1_REGION54_Enabled 00188 00189 #define MPU_PROTENSET1_PROTREG53_Pos BPROT_CONFIG1_REGION53_Pos 00190 #define MPU_PROTENSET1_PROTREG53_Msk BPROT_CONFIG1_REGION53_Msk 00191 #define MPU_PROTENSET1_PROTREG53_Disabled BPROT_CONFIG1_REGION53_Disabled 00192 #define MPU_PROTENSET1_PROTREG53_Enabled BPROT_CONFIG1_REGION53_Enabled 00193 #define MPU_PROTENSET1_PROTREG53_Set BPROT_CONFIG1_REGION53_Enabled 00194 00195 #define MPU_PROTENSET1_PROTREG52_Pos BPROT_CONFIG1_REGION52_Pos 00196 #define MPU_PROTENSET1_PROTREG52_Msk BPROT_CONFIG1_REGION52_Msk 00197 #define MPU_PROTENSET1_PROTREG52_Disabled BPROT_CONFIG1_REGION52_Disabled 00198 #define MPU_PROTENSET1_PROTREG52_Enabled BPROT_CONFIG1_REGION52_Enabled 00199 #define MPU_PROTENSET1_PROTREG52_Set BPROT_CONFIG1_REGION52_Enabled 00200 00201 #define MPU_PROTENSET1_PROTREG51_Pos BPROT_CONFIG1_REGION51_Pos 00202 #define MPU_PROTENSET1_PROTREG51_Msk BPROT_CONFIG1_REGION51_Msk 00203 #define MPU_PROTENSET1_PROTREG51_Disabled BPROT_CONFIG1_REGION51_Disabled 00204 #define MPU_PROTENSET1_PROTREG51_Enabled BPROT_CONFIG1_REGION51_Enabled 00205 #define MPU_PROTENSET1_PROTREG51_Set BPROT_CONFIG1_REGION51_Enabled 00206 00207 #define MPU_PROTENSET1_PROTREG50_Pos BPROT_CONFIG1_REGION50_Pos 00208 #define MPU_PROTENSET1_PROTREG50_Msk BPROT_CONFIG1_REGION50_Msk 00209 #define MPU_PROTENSET1_PROTREG50_Disabled BPROT_CONFIG1_REGION50_Disabled 00210 #define MPU_PROTENSET1_PROTREG50_Enabled BPROT_CONFIG1_REGION50_Enabled 00211 #define MPU_PROTENSET1_PROTREG50_Set BPROT_CONFIG1_REGION50_Enabled 00212 00213 #define MPU_PROTENSET1_PROTREG49_Pos BPROT_CONFIG1_REGION49_Pos 00214 #define MPU_PROTENSET1_PROTREG49_Msk BPROT_CONFIG1_REGION49_Msk 00215 #define MPU_PROTENSET1_PROTREG49_Disabled BPROT_CONFIG1_REGION49_Disabled 00216 #define MPU_PROTENSET1_PROTREG49_Enabled BPROT_CONFIG1_REGION49_Enabled 00217 #define MPU_PROTENSET1_PROTREG49_Set BPROT_CONFIG1_REGION49_Enabled 00218 00219 #define MPU_PROTENSET1_PROTREG48_Pos BPROT_CONFIG1_REGION48_Pos 00220 #define MPU_PROTENSET1_PROTREG48_Msk BPROT_CONFIG1_REGION48_Msk 00221 #define MPU_PROTENSET1_PROTREG48_Disabled BPROT_CONFIG1_REGION48_Disabled 00222 #define MPU_PROTENSET1_PROTREG48_Enabled BPROT_CONFIG1_REGION48_Enabled 00223 #define MPU_PROTENSET1_PROTREG48_Set BPROT_CONFIG1_REGION48_Enabled 00224 00225 #define MPU_PROTENSET1_PROTREG47_Pos BPROT_CONFIG1_REGION47_Pos 00226 #define MPU_PROTENSET1_PROTREG47_Msk BPROT_CONFIG1_REGION47_Msk 00227 #define MPU_PROTENSET1_PROTREG47_Disabled BPROT_CONFIG1_REGION47_Disabled 00228 #define MPU_PROTENSET1_PROTREG47_Enabled BPROT_CONFIG1_REGION47_Enabled 00229 #define MPU_PROTENSET1_PROTREG47_Set BPROT_CONFIG1_REGION47_Enabled 00230 00231 #define MPU_PROTENSET1_PROTREG46_Pos BPROT_CONFIG1_REGION46_Pos 00232 #define MPU_PROTENSET1_PROTREG46_Msk BPROT_CONFIG1_REGION46_Msk 00233 #define MPU_PROTENSET1_PROTREG46_Disabled BPROT_CONFIG1_REGION46_Disabled 00234 #define MPU_PROTENSET1_PROTREG46_Enabled BPROT_CONFIG1_REGION46_Enabled 00235 #define MPU_PROTENSET1_PROTREG46_Set BPROT_CONFIG1_REGION46_Enabled 00236 00237 #define MPU_PROTENSET1_PROTREG45_Pos BPROT_CONFIG1_REGION45_Pos 00238 #define MPU_PROTENSET1_PROTREG45_Msk BPROT_CONFIG1_REGION45_Msk 00239 #define MPU_PROTENSET1_PROTREG45_Disabled BPROT_CONFIG1_REGION45_Disabled 00240 #define MPU_PROTENSET1_PROTREG45_Enabled BPROT_CONFIG1_REGION45_Enabled 00241 #define MPU_PROTENSET1_PROTREG45_Set BPROT_CONFIG1_REGION45_Enabled 00242 00243 #define MPU_PROTENSET1_PROTREG44_Pos BPROT_CONFIG1_REGION44_Pos 00244 #define MPU_PROTENSET1_PROTREG44_Msk BPROT_CONFIG1_REGION44_Msk 00245 #define MPU_PROTENSET1_PROTREG44_Disabled BPROT_CONFIG1_REGION44_Disabled 00246 #define MPU_PROTENSET1_PROTREG44_Enabled BPROT_CONFIG1_REGION44_Enabled 00247 #define MPU_PROTENSET1_PROTREG44_Set BPROT_CONFIG1_REGION44_Enabled 00248 00249 #define MPU_PROTENSET1_PROTREG43_Pos BPROT_CONFIG1_REGION43_Pos 00250 #define MPU_PROTENSET1_PROTREG43_Msk BPROT_CONFIG1_REGION43_Msk 00251 #define MPU_PROTENSET1_PROTREG43_Disabled BPROT_CONFIG1_REGION43_Disabled 00252 #define MPU_PROTENSET1_PROTREG43_Enabled BPROT_CONFIG1_REGION43_Enabled 00253 #define MPU_PROTENSET1_PROTREG43_Set BPROT_CONFIG1_REGION43_Enabled 00254 00255 #define MPU_PROTENSET1_PROTREG42_Pos BPROT_CONFIG1_REGION42_Pos 00256 #define MPU_PROTENSET1_PROTREG42_Msk BPROT_CONFIG1_REGION42_Msk 00257 #define MPU_PROTENSET1_PROTREG42_Disabled BPROT_CONFIG1_REGION42_Disabled 00258 #define MPU_PROTENSET1_PROTREG42_Enabled BPROT_CONFIG1_REGION42_Enabled 00259 #define MPU_PROTENSET1_PROTREG42_Set BPROT_CONFIG1_REGION42_Enabled 00260 00261 #define MPU_PROTENSET1_PROTREG41_Pos BPROT_CONFIG1_REGION41_Pos 00262 #define MPU_PROTENSET1_PROTREG41_Msk BPROT_CONFIG1_REGION41_Msk 00263 #define MPU_PROTENSET1_PROTREG41_Disabled BPROT_CONFIG1_REGION41_Disabled 00264 #define MPU_PROTENSET1_PROTREG41_Enabled BPROT_CONFIG1_REGION41_Enabled 00265 #define MPU_PROTENSET1_PROTREG41_Set BPROT_CONFIG1_REGION41_Enabled 00266 00267 #define MPU_PROTENSET1_PROTREG40_Pos BPROT_CONFIG1_REGION40_Pos 00268 #define MPU_PROTENSET1_PROTREG40_Msk BPROT_CONFIG1_REGION40_Msk 00269 #define MPU_PROTENSET1_PROTREG40_Disabled BPROT_CONFIG1_REGION40_Disabled 00270 #define MPU_PROTENSET1_PROTREG40_Enabled BPROT_CONFIG1_REGION40_Enabled 00271 #define MPU_PROTENSET1_PROTREG40_Set BPROT_CONFIG1_REGION40_Enabled 00272 00273 #define MPU_PROTENSET1_PROTREG39_Pos BPROT_CONFIG1_REGION39_Pos 00274 #define MPU_PROTENSET1_PROTREG39_Msk BPROT_CONFIG1_REGION39_Msk 00275 #define MPU_PROTENSET1_PROTREG39_Disabled BPROT_CONFIG1_REGION39_Disabled 00276 #define MPU_PROTENSET1_PROTREG39_Enabled BPROT_CONFIG1_REGION39_Enabled 00277 #define MPU_PROTENSET1_PROTREG39_Set BPROT_CONFIG1_REGION39_Enabled 00278 00279 #define MPU_PROTENSET1_PROTREG38_Pos BPROT_CONFIG1_REGION38_Pos 00280 #define MPU_PROTENSET1_PROTREG38_Msk BPROT_CONFIG1_REGION38_Msk 00281 #define MPU_PROTENSET1_PROTREG38_Disabled BPROT_CONFIG1_REGION38_Disabled 00282 #define MPU_PROTENSET1_PROTREG38_Enabled BPROT_CONFIG1_REGION38_Enabled 00283 #define MPU_PROTENSET1_PROTREG38_Set BPROT_CONFIG1_REGION38_Enabled 00284 00285 #define MPU_PROTENSET1_PROTREG37_Pos BPROT_CONFIG1_REGION37_Pos 00286 #define MPU_PROTENSET1_PROTREG37_Msk BPROT_CONFIG1_REGION37_Msk 00287 #define MPU_PROTENSET1_PROTREG37_Disabled BPROT_CONFIG1_REGION37_Disabled 00288 #define MPU_PROTENSET1_PROTREG37_Enabled BPROT_CONFIG1_REGION37_Enabled 00289 #define MPU_PROTENSET1_PROTREG37_Set BPROT_CONFIG1_REGION37_Enabled 00290 00291 #define MPU_PROTENSET1_PROTREG36_Pos BPROT_CONFIG1_REGION36_Pos 00292 #define MPU_PROTENSET1_PROTREG36_Msk BPROT_CONFIG1_REGION36_Msk 00293 #define MPU_PROTENSET1_PROTREG36_Disabled BPROT_CONFIG1_REGION36_Disabled 00294 #define MPU_PROTENSET1_PROTREG36_Enabled BPROT_CONFIG1_REGION36_Enabled 00295 #define MPU_PROTENSET1_PROTREG36_Set BPROT_CONFIG1_REGION36_Enabled 00296 00297 #define MPU_PROTENSET1_PROTREG35_Pos BPROT_CONFIG1_REGION35_Pos 00298 #define MPU_PROTENSET1_PROTREG35_Msk BPROT_CONFIG1_REGION35_Msk 00299 #define MPU_PROTENSET1_PROTREG35_Disabled BPROT_CONFIG1_REGION35_Disabled 00300 #define MPU_PROTENSET1_PROTREG35_Enabled BPROT_CONFIG1_REGION35_Enabled 00301 #define MPU_PROTENSET1_PROTREG35_Set BPROT_CONFIG1_REGION35_Enabled 00302 00303 #define MPU_PROTENSET1_PROTREG34_Pos BPROT_CONFIG1_REGION34_Pos 00304 #define MPU_PROTENSET1_PROTREG34_Msk BPROT_CONFIG1_REGION34_Msk 00305 #define MPU_PROTENSET1_PROTREG34_Disabled BPROT_CONFIG1_REGION34_Disabled 00306 #define MPU_PROTENSET1_PROTREG34_Enabled BPROT_CONFIG1_REGION34_Enabled 00307 #define MPU_PROTENSET1_PROTREG34_Set BPROT_CONFIG1_REGION34_Enabled 00308 00309 #define MPU_PROTENSET1_PROTREG33_Pos BPROT_CONFIG1_REGION33_Pos 00310 #define MPU_PROTENSET1_PROTREG33_Msk BPROT_CONFIG1_REGION33_Msk 00311 #define MPU_PROTENSET1_PROTREG33_Disabled BPROT_CONFIG1_REGION33_Disabled 00312 #define MPU_PROTENSET1_PROTREG33_Enabled BPROT_CONFIG1_REGION33_Enabled 00313 #define MPU_PROTENSET1_PROTREG33_Set BPROT_CONFIG1_REGION33_Enabled 00314 00315 #define MPU_PROTENSET1_PROTREG32_Pos BPROT_CONFIG1_REGION32_Pos 00316 #define MPU_PROTENSET1_PROTREG32_Msk BPROT_CONFIG1_REGION32_Msk 00317 #define MPU_PROTENSET1_PROTREG32_Disabled BPROT_CONFIG1_REGION32_Disabled 00318 #define MPU_PROTENSET1_PROTREG32_Enabled BPROT_CONFIG1_REGION32_Enabled 00319 #define MPU_PROTENSET1_PROTREG32_Set BPROT_CONFIG1_REGION32_Enabled 00320 00321 #define MPU_PROTENSET0_PROTREG31_Pos BPROT_CONFIG0_REGION31_Pos 00322 #define MPU_PROTENSET0_PROTREG31_Msk BPROT_CONFIG0_REGION31_Msk 00323 #define MPU_PROTENSET0_PROTREG31_Disabled BPROT_CONFIG0_REGION31_Disabled 00324 #define MPU_PROTENSET0_PROTREG31_Enabled BPROT_CONFIG0_REGION31_Enabled 00325 #define MPU_PROTENSET0_PROTREG31_Set BPROT_CONFIG0_REGION31_Enabled 00326 00327 #define MPU_PROTENSET0_PROTREG30_Pos BPROT_CONFIG0_REGION30_Pos 00328 #define MPU_PROTENSET0_PROTREG30_Msk BPROT_CONFIG0_REGION30_Msk 00329 #define MPU_PROTENSET0_PROTREG30_Disabled BPROT_CONFIG0_REGION30_Disabled 00330 #define MPU_PROTENSET0_PROTREG30_Enabled BPROT_CONFIG0_REGION30_Enabled 00331 #define MPU_PROTENSET0_PROTREG30_Set BPROT_CONFIG0_REGION30_Enabled 00332 00333 #define MPU_PROTENSET0_PROTREG29_Pos BPROT_CONFIG0_REGION29_Pos 00334 #define MPU_PROTENSET0_PROTREG29_Msk BPROT_CONFIG0_REGION29_Msk 00335 #define MPU_PROTENSET0_PROTREG29_Disabled BPROT_CONFIG0_REGION29_Disabled 00336 #define MPU_PROTENSET0_PROTREG29_Enabled BPROT_CONFIG0_REGION29_Enabled 00337 #define MPU_PROTENSET0_PROTREG29_Set BPROT_CONFIG0_REGION29_Enabled 00338 00339 #define MPU_PROTENSET0_PROTREG28_Pos BPROT_CONFIG0_REGION28_Pos 00340 #define MPU_PROTENSET0_PROTREG28_Msk BPROT_CONFIG0_REGION28_Msk 00341 #define MPU_PROTENSET0_PROTREG28_Disabled BPROT_CONFIG0_REGION28_Disabled 00342 #define MPU_PROTENSET0_PROTREG28_Enabled BPROT_CONFIG0_REGION28_Enabled 00343 #define MPU_PROTENSET0_PROTREG28_Set BPROT_CONFIG0_REGION28_Enabled 00344 00345 #define MPU_PROTENSET0_PROTREG27_Pos BPROT_CONFIG0_REGION27_Pos 00346 #define MPU_PROTENSET0_PROTREG27_Msk BPROT_CONFIG0_REGION27_Msk 00347 #define MPU_PROTENSET0_PROTREG27_Disabled BPROT_CONFIG0_REGION27_Disabled 00348 #define MPU_PROTENSET0_PROTREG27_Enabled BPROT_CONFIG0_REGION27_Enabled 00349 #define MPU_PROTENSET0_PROTREG27_Set BPROT_CONFIG0_REGION27_Enabled 00350 00351 #define MPU_PROTENSET0_PROTREG26_Pos BPROT_CONFIG0_REGION26_Pos 00352 #define MPU_PROTENSET0_PROTREG26_Msk BPROT_CONFIG0_REGION26_Msk 00353 #define MPU_PROTENSET0_PROTREG26_Disabled BPROT_CONFIG0_REGION26_Disabled 00354 #define MPU_PROTENSET0_PROTREG26_Enabled BPROT_CONFIG0_REGION26_Enabled 00355 #define MPU_PROTENSET0_PROTREG26_Set BPROT_CONFIG0_REGION26_Enabled 00356 00357 #define MPU_PROTENSET0_PROTREG25_Pos BPROT_CONFIG0_REGION25_Pos 00358 #define MPU_PROTENSET0_PROTREG25_Msk BPROT_CONFIG0_REGION25_Msk 00359 #define MPU_PROTENSET0_PROTREG25_Disabled BPROT_CONFIG0_REGION25_Disabled 00360 #define MPU_PROTENSET0_PROTREG25_Enabled BPROT_CONFIG0_REGION25_Enabled 00361 #define MPU_PROTENSET0_PROTREG25_Set BPROT_CONFIG0_REGION25_Enabled 00362 00363 #define MPU_PROTENSET0_PROTREG24_Pos BPROT_CONFIG0_REGION24_Pos 00364 #define MPU_PROTENSET0_PROTREG24_Msk BPROT_CONFIG0_REGION24_Msk 00365 #define MPU_PROTENSET0_PROTREG24_Disabled BPROT_CONFIG0_REGION24_Disabled 00366 #define MPU_PROTENSET0_PROTREG24_Enabled BPROT_CONFIG0_REGION24_Enabled 00367 #define MPU_PROTENSET0_PROTREG24_Set BPROT_CONFIG0_REGION24_Enabled 00368 00369 #define MPU_PROTENSET0_PROTREG23_Pos BPROT_CONFIG0_REGION23_Pos 00370 #define MPU_PROTENSET0_PROTREG23_Msk BPROT_CONFIG0_REGION23_Msk 00371 #define MPU_PROTENSET0_PROTREG23_Disabled BPROT_CONFIG0_REGION23_Disabled 00372 #define MPU_PROTENSET0_PROTREG23_Enabled BPROT_CONFIG0_REGION23_Enabled 00373 #define MPU_PROTENSET0_PROTREG23_Set BPROT_CONFIG0_REGION23_Enabled 00374 00375 #define MPU_PROTENSET0_PROTREG22_Pos BPROT_CONFIG0_REGION22_Pos 00376 #define MPU_PROTENSET0_PROTREG22_Msk BPROT_CONFIG0_REGION22_Msk 00377 #define MPU_PROTENSET0_PROTREG22_Disabled BPROT_CONFIG0_REGION22_Disabled 00378 #define MPU_PROTENSET0_PROTREG22_Enabled BPROT_CONFIG0_REGION22_Enabled 00379 #define MPU_PROTENSET0_PROTREG22_Set BPROT_CONFIG0_REGION22_Enabled 00380 00381 #define MPU_PROTENSET0_PROTREG21_Pos BPROT_CONFIG0_REGION21_Pos 00382 #define MPU_PROTENSET0_PROTREG21_Msk BPROT_CONFIG0_REGION21_Msk 00383 #define MPU_PROTENSET0_PROTREG21_Disabled BPROT_CONFIG0_REGION21_Disabled 00384 #define MPU_PROTENSET0_PROTREG21_Enabled BPROT_CONFIG0_REGION21_Enabled 00385 #define MPU_PROTENSET0_PROTREG21_Set BPROT_CONFIG0_REGION21_Enabled 00386 00387 #define MPU_PROTENSET0_PROTREG20_Pos BPROT_CONFIG0_REGION20_Pos 00388 #define MPU_PROTENSET0_PROTREG20_Msk BPROT_CONFIG0_REGION20_Msk 00389 #define MPU_PROTENSET0_PROTREG20_Disabled BPROT_CONFIG0_REGION20_Disabled 00390 #define MPU_PROTENSET0_PROTREG20_Enabled BPROT_CONFIG0_REGION20_Enabled 00391 #define MPU_PROTENSET0_PROTREG20_Set BPROT_CONFIG0_REGION20_Enabled 00392 00393 #define MPU_PROTENSET0_PROTREG19_Pos BPROT_CONFIG0_REGION19_Pos 00394 #define MPU_PROTENSET0_PROTREG19_Msk BPROT_CONFIG0_REGION19_Msk 00395 #define MPU_PROTENSET0_PROTREG19_Disabled BPROT_CONFIG0_REGION19_Disabled 00396 #define MPU_PROTENSET0_PROTREG19_Enabled BPROT_CONFIG0_REGION19_Enabled 00397 #define MPU_PROTENSET0_PROTREG19_Set BPROT_CONFIG0_REGION19_Enabled 00398 00399 #define MPU_PROTENSET0_PROTREG18_Pos BPROT_CONFIG0_REGION18_Pos 00400 #define MPU_PROTENSET0_PROTREG18_Msk BPROT_CONFIG0_REGION18_Msk 00401 #define MPU_PROTENSET0_PROTREG18_Disabled BPROT_CONFIG0_REGION18_Disabled 00402 #define MPU_PROTENSET0_PROTREG18_Enabled BPROT_CONFIG0_REGION18_Enabled 00403 #define MPU_PROTENSET0_PROTREG18_Set BPROT_CONFIG0_REGION18_Enabled 00404 00405 #define MPU_PROTENSET0_PROTREG17_Pos BPROT_CONFIG0_REGION17_Pos 00406 #define MPU_PROTENSET0_PROTREG17_Msk BPROT_CONFIG0_REGION17_Msk 00407 #define MPU_PROTENSET0_PROTREG17_Disabled BPROT_CONFIG0_REGION17_Disabled 00408 #define MPU_PROTENSET0_PROTREG17_Enabled BPROT_CONFIG0_REGION17_Enabled 00409 #define MPU_PROTENSET0_PROTREG17_Set BPROT_CONFIG0_REGION17_Enabled 00410 00411 #define MPU_PROTENSET0_PROTREG16_Pos BPROT_CONFIG0_REGION16_Pos 00412 #define MPU_PROTENSET0_PROTREG16_Msk BPROT_CONFIG0_REGION16_Msk 00413 #define MPU_PROTENSET0_PROTREG16_Disabled BPROT_CONFIG0_REGION16_Disabled 00414 #define MPU_PROTENSET0_PROTREG16_Enabled BPROT_CONFIG0_REGION16_Enabled 00415 #define MPU_PROTENSET0_PROTREG16_Set BPROT_CONFIG0_REGION16_Enabled 00416 00417 #define MPU_PROTENSET0_PROTREG15_Pos BPROT_CONFIG0_REGION15_Pos 00418 #define MPU_PROTENSET0_PROTREG15_Msk BPROT_CONFIG0_REGION15_Msk 00419 #define MPU_PROTENSET0_PROTREG15_Disabled BPROT_CONFIG0_REGION15_Disabled 00420 #define MPU_PROTENSET0_PROTREG15_Enabled BPROT_CONFIG0_REGION15_Enabled 00421 #define MPU_PROTENSET0_PROTREG15_Set BPROT_CONFIG0_REGION15_Enabled 00422 00423 #define MPU_PROTENSET0_PROTREG14_Pos BPROT_CONFIG0_REGION14_Pos 00424 #define MPU_PROTENSET0_PROTREG14_Msk BPROT_CONFIG0_REGION14_Msk 00425 #define MPU_PROTENSET0_PROTREG14_Disabled BPROT_CONFIG0_REGION14_Disabled 00426 #define MPU_PROTENSET0_PROTREG14_Enabled BPROT_CONFIG0_REGION14_Enabled 00427 #define MPU_PROTENSET0_PROTREG14_Set BPROT_CONFIG0_REGION14_Enabled 00428 00429 #define MPU_PROTENSET0_PROTREG13_Pos BPROT_CONFIG0_REGION13_Pos 00430 #define MPU_PROTENSET0_PROTREG13_Msk BPROT_CONFIG0_REGION13_Msk 00431 #define MPU_PROTENSET0_PROTREG13_Disabled BPROT_CONFIG0_REGION13_Disabled 00432 #define MPU_PROTENSET0_PROTREG13_Enabled BPROT_CONFIG0_REGION13_Enabled 00433 #define MPU_PROTENSET0_PROTREG13_Set BPROT_CONFIG0_REGION13_Enabled 00434 00435 #define MPU_PROTENSET0_PROTREG12_Pos BPROT_CONFIG0_REGION12_Pos 00436 #define MPU_PROTENSET0_PROTREG12_Msk BPROT_CONFIG0_REGION12_Msk 00437 #define MPU_PROTENSET0_PROTREG12_Disabled BPROT_CONFIG0_REGION12_Disabled 00438 #define MPU_PROTENSET0_PROTREG12_Enabled BPROT_CONFIG0_REGION12_Enabled 00439 #define MPU_PROTENSET0_PROTREG12_Set BPROT_CONFIG0_REGION12_Enabled 00440 00441 #define MPU_PROTENSET0_PROTREG11_Pos BPROT_CONFIG0_REGION11_Pos 00442 #define MPU_PROTENSET0_PROTREG11_Msk BPROT_CONFIG0_REGION11_Msk 00443 #define MPU_PROTENSET0_PROTREG11_Disabled BPROT_CONFIG0_REGION11_Disabled 00444 #define MPU_PROTENSET0_PROTREG11_Enabled BPROT_CONFIG0_REGION11_Enabled 00445 #define MPU_PROTENSET0_PROTREG11_Set BPROT_CONFIG0_REGION11_Enabled 00446 00447 #define MPU_PROTENSET0_PROTREG10_Pos BPROT_CONFIG0_REGION10_Pos 00448 #define MPU_PROTENSET0_PROTREG10_Msk BPROT_CONFIG0_REGION10_Msk 00449 #define MPU_PROTENSET0_PROTREG10_Disabled BPROT_CONFIG0_REGION10_Disabled 00450 #define MPU_PROTENSET0_PROTREG10_Enabled BPROT_CONFIG0_REGION10_Enabled 00451 #define MPU_PROTENSET0_PROTREG10_Set BPROT_CONFIG0_REGION10_Enabled 00452 00453 #define MPU_PROTENSET0_PROTREG9_Pos BPROT_CONFIG0_REGION9_Pos 00454 #define MPU_PROTENSET0_PROTREG9_Msk BPROT_CONFIG0_REGION9_Msk 00455 #define MPU_PROTENSET0_PROTREG9_Disabled BPROT_CONFIG0_REGION9_Disabled 00456 #define MPU_PROTENSET0_PROTREG9_Enabled BPROT_CONFIG0_REGION9_Enabled 00457 #define MPU_PROTENSET0_PROTREG9_Set BPROT_CONFIG0_REGION9_Enabled 00458 00459 #define MPU_PROTENSET0_PROTREG8_Pos BPROT_CONFIG0_REGION8_Pos 00460 #define MPU_PROTENSET0_PROTREG8_Msk BPROT_CONFIG0_REGION8_Msk 00461 #define MPU_PROTENSET0_PROTREG8_Disabled BPROT_CONFIG0_REGION8_Disabled 00462 #define MPU_PROTENSET0_PROTREG8_Enabled BPROT_CONFIG0_REGION8_Enabled 00463 #define MPU_PROTENSET0_PROTREG8_Set BPROT_CONFIG0_REGION8_Enabled 00464 00465 #define MPU_PROTENSET0_PROTREG7_Pos BPROT_CONFIG0_REGION7_Pos 00466 #define MPU_PROTENSET0_PROTREG7_Msk BPROT_CONFIG0_REGION7_Msk 00467 #define MPU_PROTENSET0_PROTREG7_Disabled BPROT_CONFIG0_REGION7_Disabled 00468 #define MPU_PROTENSET0_PROTREG7_Enabled BPROT_CONFIG0_REGION7_Enabled 00469 #define MPU_PROTENSET0_PROTREG7_Set BPROT_CONFIG0_REGION7_Enabled 00470 00471 #define MPU_PROTENSET0_PROTREG6_Pos BPROT_CONFIG0_REGION6_Pos 00472 #define MPU_PROTENSET0_PROTREG6_Msk BPROT_CONFIG0_REGION6_Msk 00473 #define MPU_PROTENSET0_PROTREG6_Disabled BPROT_CONFIG0_REGION6_Disabled 00474 #define MPU_PROTENSET0_PROTREG6_Enabled BPROT_CONFIG0_REGION6_Enabled 00475 #define MPU_PROTENSET0_PROTREG6_Set BPROT_CONFIG0_REGION6_Enabled 00476 00477 #define MPU_PROTENSET0_PROTREG5_Pos BPROT_CONFIG0_REGION5_Pos 00478 #define MPU_PROTENSET0_PROTREG5_Msk BPROT_CONFIG0_REGION5_Msk 00479 #define MPU_PROTENSET0_PROTREG5_Disabled BPROT_CONFIG0_REGION5_Disabled 00480 #define MPU_PROTENSET0_PROTREG5_Enabled BPROT_CONFIG0_REGION5_Enabled 00481 #define MPU_PROTENSET0_PROTREG5_Set BPROT_CONFIG0_REGION5_Enabled 00482 00483 #define MPU_PROTENSET0_PROTREG4_Pos BPROT_CONFIG0_REGION4_Pos 00484 #define MPU_PROTENSET0_PROTREG4_Msk BPROT_CONFIG0_REGION4_Msk 00485 #define MPU_PROTENSET0_PROTREG4_Disabled BPROT_CONFIG0_REGION4_Disabled 00486 #define MPU_PROTENSET0_PROTREG4_Enabled BPROT_CONFIG0_REGION4_Enabled 00487 #define MPU_PROTENSET0_PROTREG4_Set BPROT_CONFIG0_REGION4_Enabled 00488 00489 #define MPU_PROTENSET0_PROTREG3_Pos BPROT_CONFIG0_REGION3_Pos 00490 #define MPU_PROTENSET0_PROTREG3_Msk BPROT_CONFIG0_REGION3_Msk 00491 #define MPU_PROTENSET0_PROTREG3_Disabled BPROT_CONFIG0_REGION3_Disabled 00492 #define MPU_PROTENSET0_PROTREG3_Enabled BPROT_CONFIG0_REGION3_Enabled 00493 #define MPU_PROTENSET0_PROTREG3_Set BPROT_CONFIG0_REGION3_Enabled 00494 00495 #define MPU_PROTENSET0_PROTREG2_Pos BPROT_CONFIG0_REGION2_Pos 00496 #define MPU_PROTENSET0_PROTREG2_Msk BPROT_CONFIG0_REGION2_Msk 00497 #define MPU_PROTENSET0_PROTREG2_Disabled BPROT_CONFIG0_REGION2_Disabled 00498 #define MPU_PROTENSET0_PROTREG2_Enabled BPROT_CONFIG0_REGION2_Enabled 00499 #define MPU_PROTENSET0_PROTREG2_Set BPROT_CONFIG0_REGION2_Enabled 00500 00501 #define MPU_PROTENSET0_PROTREG1_Pos BPROT_CONFIG0_REGION1_Pos 00502 #define MPU_PROTENSET0_PROTREG1_Msk BPROT_CONFIG0_REGION1_Msk 00503 #define MPU_PROTENSET0_PROTREG1_Disabled BPROT_CONFIG0_REGION1_Disabled 00504 #define MPU_PROTENSET0_PROTREG1_Enabled BPROT_CONFIG0_REGION1_Enabled 00505 #define MPU_PROTENSET0_PROTREG1_Set BPROT_CONFIG0_REGION1_Enabled 00506 00507 #define MPU_PROTENSET0_PROTREG0_Pos BPROT_CONFIG0_REGION0_Pos 00508 #define MPU_PROTENSET0_PROTREG0_Msk BPROT_CONFIG0_REGION0_Msk 00509 #define MPU_PROTENSET0_PROTREG0_Disabled BPROT_CONFIG0_REGION0_Disabled 00510 #define MPU_PROTENSET0_PROTREG0_Enabled BPROT_CONFIG0_REGION0_Enabled 00511 #define MPU_PROTENSET0_PROTREG0_Set BPROT_CONFIG0_REGION0_Enabled 00512 00513 00514 /* From nrf51_deprecated.h */ 00515 00516 /* NVMC */ 00517 /* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */ 00518 #define ERASEPROTECTEDPAGE ERASEPCR0 00519 00520 00521 /* IRQ */ 00522 /* COMP module was eliminated. Adapted to nrf52 headers. */ 00523 #define LPCOMP_COMP_IRQHandler COMP_LPCOMP_IRQHandler 00524 #define LPCOMP_COMP_IRQn COMP_LPCOMP_IRQn 00525 00526 00527 /* RADIO */ 00528 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 00529 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 00530 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 00531 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 00532 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 00533 00534 00535 /* FICR */ 00536 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 00537 #define DEVICEID0 DEVICEID[0] 00538 #define DEVICEID1 DEVICEID[1] 00539 00540 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 00541 #define ER0 ER[0] 00542 #define ER1 ER[1] 00543 #define ER2 ER[2] 00544 #define ER3 ER[3] 00545 00546 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 00547 #define IR0 IR[0] 00548 #define IR1 IR[1] 00549 #define IR2 IR[2] 00550 #define IR3 IR[3] 00551 00552 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 00553 #define DEVICEADDR0 DEVICEADDR[0] 00554 #define DEVICEADDR1 DEVICEADDR[1] 00555 00556 00557 /* PPI */ 00558 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 00559 #define TASKS_CHG0EN TASKS_CHG[0].EN 00560 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 00561 #define TASKS_CHG1EN TASKS_CHG[1].EN 00562 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 00563 #define TASKS_CHG2EN TASKS_CHG[2].EN 00564 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 00565 #define TASKS_CHG3EN TASKS_CHG[3].EN 00566 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 00567 00568 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 00569 #define CH0_EEP CH[0].EEP 00570 #define CH0_TEP CH[0].TEP 00571 #define CH1_EEP CH[1].EEP 00572 #define CH1_TEP CH[1].TEP 00573 #define CH2_EEP CH[2].EEP 00574 #define CH2_TEP CH[2].TEP 00575 #define CH3_EEP CH[3].EEP 00576 #define CH3_TEP CH[3].TEP 00577 #define CH4_EEP CH[4].EEP 00578 #define CH4_TEP CH[4].TEP 00579 #define CH5_EEP CH[5].EEP 00580 #define CH5_TEP CH[5].TEP 00581 #define CH6_EEP CH[6].EEP 00582 #define CH6_TEP CH[6].TEP 00583 #define CH7_EEP CH[7].EEP 00584 #define CH7_TEP CH[7].TEP 00585 #define CH8_EEP CH[8].EEP 00586 #define CH8_TEP CH[8].TEP 00587 #define CH9_EEP CH[9].EEP 00588 #define CH9_TEP CH[9].TEP 00589 #define CH10_EEP CH[10].EEP 00590 #define CH10_TEP CH[10].TEP 00591 #define CH11_EEP CH[11].EEP 00592 #define CH11_TEP CH[11].TEP 00593 #define CH12_EEP CH[12].EEP 00594 #define CH12_TEP CH[12].TEP 00595 #define CH13_EEP CH[13].EEP 00596 #define CH13_TEP CH[13].TEP 00597 #define CH14_EEP CH[14].EEP 00598 #define CH14_TEP CH[14].TEP 00599 #define CH15_EEP CH[15].EEP 00600 #define CH15_TEP CH[15].TEP 00601 00602 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 00603 #define CHG0 CHG[0] 00604 #define CHG1 CHG[1] 00605 #define CHG2 CHG[2] 00606 #define CHG3 CHG[3] 00607 00608 /* All bitfield macros for the CHGx registers therefore changed name. */ 00609 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 00610 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 00611 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 00612 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 00613 00614 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 00615 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 00616 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 00617 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 00618 00619 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 00620 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 00621 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 00622 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 00623 00624 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 00625 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 00626 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 00627 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 00628 00629 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 00630 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 00631 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 00632 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 00633 00634 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 00635 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 00636 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 00637 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 00638 00639 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 00640 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 00641 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 00642 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 00643 00644 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 00645 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 00646 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 00647 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 00648 00649 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 00650 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 00651 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 00652 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 00653 00654 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 00655 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 00656 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 00657 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 00658 00659 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 00660 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 00661 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 00662 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 00663 00664 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 00665 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 00666 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 00667 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 00668 00669 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 00670 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 00671 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 00672 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 00673 00674 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 00675 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 00676 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 00677 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 00678 00679 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 00680 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 00681 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 00682 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 00683 00684 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 00685 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 00686 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 00687 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 00688 00689 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 00690 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 00691 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 00692 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 00693 00694 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 00695 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 00696 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 00697 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 00698 00699 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 00700 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 00701 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 00702 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 00703 00704 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 00705 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 00706 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 00707 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 00708 00709 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 00710 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 00711 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 00712 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 00713 00714 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 00715 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 00716 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 00717 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 00718 00719 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 00720 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 00721 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 00722 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 00723 00724 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 00725 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 00726 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 00727 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 00728 00729 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 00730 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 00731 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 00732 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 00733 00734 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 00735 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 00736 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 00737 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 00738 00739 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 00740 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 00741 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 00742 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 00743 00744 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 00745 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 00746 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 00747 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 00748 00749 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 00750 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 00751 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 00752 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 00753 00754 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 00755 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 00756 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 00757 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 00758 00759 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 00760 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 00761 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 00762 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 00763 00764 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 00765 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 00766 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 00767 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 00768 00769 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 00770 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 00771 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 00772 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 00773 00774 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 00775 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 00776 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 00777 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 00778 00779 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 00780 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 00781 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 00782 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 00783 00784 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 00785 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 00786 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 00787 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 00788 00789 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 00790 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 00791 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 00792 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 00793 00794 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 00795 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 00796 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 00797 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 00798 00799 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 00800 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 00801 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 00802 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 00803 00804 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 00805 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 00806 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 00807 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 00808 00809 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 00810 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 00811 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 00812 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 00813 00814 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 00815 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 00816 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 00817 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 00818 00819 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 00820 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 00821 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 00822 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 00823 00824 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 00825 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 00826 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 00827 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 00828 00829 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 00830 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 00831 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 00832 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 00833 00834 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 00835 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 00836 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 00837 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 00838 00839 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 00840 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 00841 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 00842 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 00843 00844 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 00845 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 00846 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 00847 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 00848 00849 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 00850 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 00851 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 00852 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 00853 00854 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 00855 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 00856 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 00857 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 00858 00859 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 00860 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 00861 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 00862 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 00863 00864 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 00865 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 00866 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 00867 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 00868 00869 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 00870 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 00871 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 00872 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 00873 00874 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 00875 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 00876 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 00877 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 00878 00879 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 00880 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 00881 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 00882 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 00883 00884 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 00885 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 00886 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 00887 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 00888 00889 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 00890 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 00891 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 00892 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 00893 00894 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 00895 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 00896 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 00897 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 00898 00899 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 00900 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 00901 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 00902 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 00903 00904 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 00905 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 00906 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 00907 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 00908 00909 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 00910 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 00911 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 00912 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 00913 00914 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 00915 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 00916 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 00917 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 00918 00919 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 00920 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 00921 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 00922 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 00923 00924 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 00925 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 00926 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 00927 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 00928 00929 00930 00931 00932 /*lint --flb "Leave library region" */ 00933 00934 #endif /* NRF51_TO_NRF52_H */ 00935 00936
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