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nrf51_deprecated.h
00001 /* 00002 * Copyright (c) Nordic Semiconductor ASA 00003 * All rights reserved. 00004 * 00005 * Redistribution and use in source and binary forms, with or without modification, 00006 * are permitted provided that the following conditions are met: 00007 * 00008 * 1. Redistributions of source code must retain the above copyright notice, this 00009 * list of conditions and the following disclaimer. 00010 * 00011 * 2. Redistributions in binary form must reproduce the above copyright notice, this 00012 * list of conditions and the following disclaimer in the documentation and/or 00013 * other materials provided with the distribution. 00014 * 00015 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other 00016 * contributors to this software may be used to endorse or promote products 00017 * derived from this software without specific prior written permission. 00018 * 00019 * 00020 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 00021 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 00022 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00023 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 00024 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 00025 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 00026 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 00027 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 00028 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 00029 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00030 * 00031 */ 00032 00033 #ifndef NRF51_DEPRECATED_H 00034 #define NRF51_DEPRECATED_H 00035 00036 /*lint ++flb "Enter library region */ 00037 00038 /* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 00039 * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these 00040 * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. 00041 */ 00042 00043 /* NVMC */ 00044 /* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ 00045 #define ERASEPROTECTEDPAGE ERASEPCR0 00046 00047 00048 /* LPCOMP */ 00049 /* The interrupt ISR was renamed. Adding old name to the macros. */ 00050 #define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler 00051 #define LPCOMP_COMP_IRQn LPCOMP_IRQn 00052 00053 00054 /* MPU */ 00055 /* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ 00056 #define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos 00057 #define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk 00058 #define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 00059 #define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 00060 00061 00062 /* POWER */ 00063 /* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 00064 #define POWER_RAMON_OFFRAM3_Pos (19UL) 00065 #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) 00066 #define POWER_RAMON_OFFRAM3_RAM3Off (0UL) 00067 #define POWER_RAMON_OFFRAM3_RAM3On (1UL) 00068 /* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 00069 #define POWER_RAMON_OFFRAM2_Pos (18UL) 00070 #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) 00071 #define POWER_RAMON_OFFRAM2_RAM2Off (0UL) 00072 #define POWER_RAMON_OFFRAM2_RAM2On (1UL) 00073 /* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 00074 #define POWER_RAMON_ONRAM3_Pos (3UL) 00075 #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) 00076 #define POWER_RAMON_ONRAM3_RAM3Off (0UL) 00077 #define POWER_RAMON_ONRAM3_RAM3On (1UL) 00078 /* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ 00079 #define POWER_RAMON_ONRAM2_Pos (2UL) 00080 #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) 00081 #define POWER_RAMON_ONRAM2_RAM2Off (0UL) 00082 #define POWER_RAMON_ONRAM2_RAM2On (1UL) 00083 00084 00085 /* RADIO */ 00086 /* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ 00087 #define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm 00088 /* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ 00089 #define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos 00090 #define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk 00091 #define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include 00092 #define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip 00093 /* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ 00094 #define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos 00095 #define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk 00096 #define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled 00097 #define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled 00098 /* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ 00099 #define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos 00100 #define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk 00101 #define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled 00102 #define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled 00103 00104 00105 /* FICR */ 00106 /* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ 00107 #define SIZERAMBLOCK0 SIZERAMBLOCKS 00108 #define SIZERAMBLOCK1 SIZERAMBLOCKS 00109 #define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ 00110 #define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ 00111 /* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ 00112 #define DEVICEID0 DEVICEID[0] 00113 #define DEVICEID1 DEVICEID[1] 00114 /* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ 00115 #define ER0 ER[0] 00116 #define ER1 ER[1] 00117 #define ER2 ER[2] 00118 #define ER3 ER[3] 00119 /* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ 00120 #define IR0 IR[0] 00121 #define IR1 IR[1] 00122 #define IR2 IR[2] 00123 #define IR3 IR[3] 00124 /* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ 00125 #define DEVICEADDR0 DEVICEADDR[0] 00126 #define DEVICEADDR1 DEVICEADDR[1] 00127 00128 00129 /* PPI */ 00130 /* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ 00131 #define TASKS_CHG0EN TASKS_CHG[0].EN 00132 #define TASKS_CHG0DIS TASKS_CHG[0].DIS 00133 #define TASKS_CHG1EN TASKS_CHG[1].EN 00134 #define TASKS_CHG1DIS TASKS_CHG[1].DIS 00135 #define TASKS_CHG2EN TASKS_CHG[2].EN 00136 #define TASKS_CHG2DIS TASKS_CHG[2].DIS 00137 #define TASKS_CHG3EN TASKS_CHG[3].EN 00138 #define TASKS_CHG3DIS TASKS_CHG[3].DIS 00139 /* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ 00140 #define CH0_EEP CH[0].EEP 00141 #define CH0_TEP CH[0].TEP 00142 #define CH1_EEP CH[1].EEP 00143 #define CH1_TEP CH[1].TEP 00144 #define CH2_EEP CH[2].EEP 00145 #define CH2_TEP CH[2].TEP 00146 #define CH3_EEP CH[3].EEP 00147 #define CH3_TEP CH[3].TEP 00148 #define CH4_EEP CH[4].EEP 00149 #define CH4_TEP CH[4].TEP 00150 #define CH5_EEP CH[5].EEP 00151 #define CH5_TEP CH[5].TEP 00152 #define CH6_EEP CH[6].EEP 00153 #define CH6_TEP CH[6].TEP 00154 #define CH7_EEP CH[7].EEP 00155 #define CH7_TEP CH[7].TEP 00156 #define CH8_EEP CH[8].EEP 00157 #define CH8_TEP CH[8].TEP 00158 #define CH9_EEP CH[9].EEP 00159 #define CH9_TEP CH[9].TEP 00160 #define CH10_EEP CH[10].EEP 00161 #define CH10_TEP CH[10].TEP 00162 #define CH11_EEP CH[11].EEP 00163 #define CH11_TEP CH[11].TEP 00164 #define CH12_EEP CH[12].EEP 00165 #define CH12_TEP CH[12].TEP 00166 #define CH13_EEP CH[13].EEP 00167 #define CH13_TEP CH[13].TEP 00168 #define CH14_EEP CH[14].EEP 00169 #define CH14_TEP CH[14].TEP 00170 #define CH15_EEP CH[15].EEP 00171 #define CH15_TEP CH[15].TEP 00172 /* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ 00173 #define CHG0 CHG[0] 00174 #define CHG1 CHG[1] 00175 #define CHG2 CHG[2] 00176 #define CHG3 CHG[3] 00177 /* All bitfield macros for the CHGx registers therefore changed name. */ 00178 #define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos 00179 #define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk 00180 #define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded 00181 #define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included 00182 #define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos 00183 #define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk 00184 #define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded 00185 #define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included 00186 #define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos 00187 #define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk 00188 #define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded 00189 #define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included 00190 #define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos 00191 #define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk 00192 #define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded 00193 #define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included 00194 #define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos 00195 #define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk 00196 #define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded 00197 #define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included 00198 #define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos 00199 #define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk 00200 #define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded 00201 #define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included 00202 #define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos 00203 #define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk 00204 #define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded 00205 #define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included 00206 #define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos 00207 #define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk 00208 #define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded 00209 #define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included 00210 #define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos 00211 #define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk 00212 #define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded 00213 #define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included 00214 #define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos 00215 #define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk 00216 #define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded 00217 #define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included 00218 #define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos 00219 #define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk 00220 #define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded 00221 #define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included 00222 #define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos 00223 #define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk 00224 #define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded 00225 #define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included 00226 #define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos 00227 #define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk 00228 #define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded 00229 #define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included 00230 #define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos 00231 #define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk 00232 #define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded 00233 #define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included 00234 #define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos 00235 #define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk 00236 #define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded 00237 #define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included 00238 #define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos 00239 #define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk 00240 #define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded 00241 #define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included 00242 #define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos 00243 #define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk 00244 #define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded 00245 #define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included 00246 #define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos 00247 #define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk 00248 #define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded 00249 #define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included 00250 #define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos 00251 #define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk 00252 #define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded 00253 #define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included 00254 #define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos 00255 #define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk 00256 #define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded 00257 #define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included 00258 #define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos 00259 #define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk 00260 #define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded 00261 #define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included 00262 #define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos 00263 #define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk 00264 #define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded 00265 #define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included 00266 #define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos 00267 #define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk 00268 #define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded 00269 #define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included 00270 #define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos 00271 #define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk 00272 #define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded 00273 #define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included 00274 #define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos 00275 #define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk 00276 #define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded 00277 #define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included 00278 #define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos 00279 #define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk 00280 #define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded 00281 #define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included 00282 #define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos 00283 #define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk 00284 #define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded 00285 #define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included 00286 #define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos 00287 #define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk 00288 #define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded 00289 #define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included 00290 #define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos 00291 #define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk 00292 #define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded 00293 #define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included 00294 #define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos 00295 #define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk 00296 #define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded 00297 #define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included 00298 #define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos 00299 #define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk 00300 #define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded 00301 #define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included 00302 #define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos 00303 #define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk 00304 #define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded 00305 #define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included 00306 #define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos 00307 #define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk 00308 #define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded 00309 #define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included 00310 #define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos 00311 #define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk 00312 #define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded 00313 #define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included 00314 #define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos 00315 #define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk 00316 #define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded 00317 #define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included 00318 #define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos 00319 #define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk 00320 #define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded 00321 #define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included 00322 #define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos 00323 #define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk 00324 #define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded 00325 #define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included 00326 #define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos 00327 #define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk 00328 #define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded 00329 #define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included 00330 #define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos 00331 #define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk 00332 #define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded 00333 #define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included 00334 #define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos 00335 #define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk 00336 #define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded 00337 #define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included 00338 #define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos 00339 #define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk 00340 #define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded 00341 #define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included 00342 #define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos 00343 #define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk 00344 #define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded 00345 #define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included 00346 #define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos 00347 #define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk 00348 #define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded 00349 #define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included 00350 #define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos 00351 #define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk 00352 #define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded 00353 #define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included 00354 #define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos 00355 #define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk 00356 #define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded 00357 #define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included 00358 #define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos 00359 #define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk 00360 #define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded 00361 #define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included 00362 #define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos 00363 #define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk 00364 #define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded 00365 #define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included 00366 #define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos 00367 #define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk 00368 #define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded 00369 #define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included 00370 #define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos 00371 #define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk 00372 #define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded 00373 #define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included 00374 #define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos 00375 #define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk 00376 #define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded 00377 #define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included 00378 #define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos 00379 #define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk 00380 #define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded 00381 #define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included 00382 #define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos 00383 #define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk 00384 #define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded 00385 #define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included 00386 #define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos 00387 #define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk 00388 #define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded 00389 #define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included 00390 #define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos 00391 #define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk 00392 #define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded 00393 #define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included 00394 #define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos 00395 #define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk 00396 #define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded 00397 #define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included 00398 #define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos 00399 #define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk 00400 #define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded 00401 #define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included 00402 #define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos 00403 #define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk 00404 #define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded 00405 #define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included 00406 #define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos 00407 #define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk 00408 #define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded 00409 #define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included 00410 #define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos 00411 #define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk 00412 #define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded 00413 #define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included 00414 #define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos 00415 #define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk 00416 #define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded 00417 #define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included 00418 #define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos 00419 #define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk 00420 #define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded 00421 #define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included 00422 #define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos 00423 #define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk 00424 #define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded 00425 #define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included 00426 #define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos 00427 #define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk 00428 #define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded 00429 #define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included 00430 #define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos 00431 #define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk 00432 #define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded 00433 #define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included 00434 00435 00436 00437 /*lint --flb "Leave library region" */ 00438 00439 #endif /* NRF51_DEPRECATED_H */ 00440
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