Taouil Yassine / nrf52-sdk

Nordic nrf51 sdk sources. Mirrored from https://github.com/ARMmbed/nrf51-sdk.

Fork of nrf51-sdk by Nordic Semiconductor

source/nordic_sdk/components/device/nrf52_bitfields.h@46:b1a9de66ecab, 2016-11-02 (annotated)

Committer:
Yassinetaouil
Date:
Wed Nov 02 15:29:13 2016 +0000
Revision:
46:b1a9de66ecab
f1;

Who changed what in which revision?

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Yassinetaouil 46:b1a9de66ecab 1 /* Copyright (c) 2015, Nordic Semiconductor ASA
Yassinetaouil 46:b1a9de66ecab 2 * All rights reserved.
Yassinetaouil 46:b1a9de66ecab 3 *
Yassinetaouil 46:b1a9de66ecab 4 * Redistribution and use in source and binary forms, with or without
Yassinetaouil 46:b1a9de66ecab 5 * modification, are permitted provided that the following conditions are met:
Yassinetaouil 46:b1a9de66ecab 6 *
Yassinetaouil 46:b1a9de66ecab 7 * * Redistributions of source code must retain the above copyright notice, this
Yassinetaouil 46:b1a9de66ecab 8 * list of conditions and the following disclaimer.
Yassinetaouil 46:b1a9de66ecab 9 *
Yassinetaouil 46:b1a9de66ecab 10 * * Redistributions in binary form must reproduce the above copyright notice,
Yassinetaouil 46:b1a9de66ecab 11 * this list of conditions and the following disclaimer in the documentation
Yassinetaouil 46:b1a9de66ecab 12 * and/or other materials provided with the distribution.
Yassinetaouil 46:b1a9de66ecab 13 *
Yassinetaouil 46:b1a9de66ecab 14 * * Neither the name of Nordic Semiconductor ASA nor the names of its
Yassinetaouil 46:b1a9de66ecab 15 * contributors may be used to endorse or promote products derived from
Yassinetaouil 46:b1a9de66ecab 16 * this software without specific prior written permission.
Yassinetaouil 46:b1a9de66ecab 17 *
Yassinetaouil 46:b1a9de66ecab 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Yassinetaouil 46:b1a9de66ecab 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Yassinetaouil 46:b1a9de66ecab 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Yassinetaouil 46:b1a9de66ecab 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Yassinetaouil 46:b1a9de66ecab 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Yassinetaouil 46:b1a9de66ecab 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Yassinetaouil 46:b1a9de66ecab 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Yassinetaouil 46:b1a9de66ecab 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Yassinetaouil 46:b1a9de66ecab 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Yassinetaouil 46:b1a9de66ecab 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Yassinetaouil 46:b1a9de66ecab 28 *
Yassinetaouil 46:b1a9de66ecab 29 */
Yassinetaouil 46:b1a9de66ecab 30 #ifndef __NRF52_BITS_H
Yassinetaouil 46:b1a9de66ecab 31 #define __NRF52_BITS_H
Yassinetaouil 46:b1a9de66ecab 32
Yassinetaouil 46:b1a9de66ecab 33 /*lint ++flb "Enter library region" */
Yassinetaouil 46:b1a9de66ecab 34
Yassinetaouil 46:b1a9de66ecab 35 /* Peripheral: AAR */
Yassinetaouil 46:b1a9de66ecab 36 /* Description: Accelerated Address Resolver */
Yassinetaouil 46:b1a9de66ecab 37
Yassinetaouil 46:b1a9de66ecab 38 /* Register: AAR_INTENSET */
Yassinetaouil 46:b1a9de66ecab 39 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 40
Yassinetaouil 46:b1a9de66ecab 41 /* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
Yassinetaouil 46:b1a9de66ecab 42 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
Yassinetaouil 46:b1a9de66ecab 43 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
Yassinetaouil 46:b1a9de66ecab 44 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 45 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 46 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 47
Yassinetaouil 46:b1a9de66ecab 48 /* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
Yassinetaouil 46:b1a9de66ecab 49 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
Yassinetaouil 46:b1a9de66ecab 50 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
Yassinetaouil 46:b1a9de66ecab 51 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 52 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 53 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 54
Yassinetaouil 46:b1a9de66ecab 55 /* Bit 0 : Write '1' to Enable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 56 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 57 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 58 #define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 59 #define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 60 #define AAR_INTENSET_END_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 61
Yassinetaouil 46:b1a9de66ecab 62 /* Register: AAR_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 63 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 64
Yassinetaouil 46:b1a9de66ecab 65 /* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
Yassinetaouil 46:b1a9de66ecab 66 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
Yassinetaouil 46:b1a9de66ecab 67 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
Yassinetaouil 46:b1a9de66ecab 68 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 69 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 70 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 71
Yassinetaouil 46:b1a9de66ecab 72 /* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
Yassinetaouil 46:b1a9de66ecab 73 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
Yassinetaouil 46:b1a9de66ecab 74 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
Yassinetaouil 46:b1a9de66ecab 75 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 76 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 77 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 78
Yassinetaouil 46:b1a9de66ecab 79 /* Bit 0 : Write '1' to Disable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 80 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 81 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 82 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 83 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 84 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 85
Yassinetaouil 46:b1a9de66ecab 86 /* Register: AAR_STATUS */
Yassinetaouil 46:b1a9de66ecab 87 /* Description: Resolution status */
Yassinetaouil 46:b1a9de66ecab 88
Yassinetaouil 46:b1a9de66ecab 89 /* Bits 3..0 : The IRK that was used last time an address was resolved */
Yassinetaouil 46:b1a9de66ecab 90 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
Yassinetaouil 46:b1a9de66ecab 91 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
Yassinetaouil 46:b1a9de66ecab 92
Yassinetaouil 46:b1a9de66ecab 93 /* Register: AAR_ENABLE */
Yassinetaouil 46:b1a9de66ecab 94 /* Description: Enable AAR */
Yassinetaouil 46:b1a9de66ecab 95
Yassinetaouil 46:b1a9de66ecab 96 /* Bits 1..0 : Enable or disable AAR */
Yassinetaouil 46:b1a9de66ecab 97 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 98 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 99 #define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 100 #define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 101
Yassinetaouil 46:b1a9de66ecab 102 /* Register: AAR_NIRK */
Yassinetaouil 46:b1a9de66ecab 103 /* Description: Number of IRKs */
Yassinetaouil 46:b1a9de66ecab 104
Yassinetaouil 46:b1a9de66ecab 105 /* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
Yassinetaouil 46:b1a9de66ecab 106 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
Yassinetaouil 46:b1a9de66ecab 107 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
Yassinetaouil 46:b1a9de66ecab 108
Yassinetaouil 46:b1a9de66ecab 109 /* Register: AAR_IRKPTR */
Yassinetaouil 46:b1a9de66ecab 110 /* Description: Pointer to IRK data structure */
Yassinetaouil 46:b1a9de66ecab 111
Yassinetaouil 46:b1a9de66ecab 112 /* Bits 31..0 : Pointer to the IRK data structure */
Yassinetaouil 46:b1a9de66ecab 113 #define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
Yassinetaouil 46:b1a9de66ecab 114 #define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
Yassinetaouil 46:b1a9de66ecab 115
Yassinetaouil 46:b1a9de66ecab 116 /* Register: AAR_ADDRPTR */
Yassinetaouil 46:b1a9de66ecab 117 /* Description: Pointer to the resolvable address */
Yassinetaouil 46:b1a9de66ecab 118
Yassinetaouil 46:b1a9de66ecab 119 /* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
Yassinetaouil 46:b1a9de66ecab 120 #define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
Yassinetaouil 46:b1a9de66ecab 121 #define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
Yassinetaouil 46:b1a9de66ecab 122
Yassinetaouil 46:b1a9de66ecab 123 /* Register: AAR_SCRATCHPTR */
Yassinetaouil 46:b1a9de66ecab 124 /* Description: Pointer to data area used for temporary storage */
Yassinetaouil 46:b1a9de66ecab 125
Yassinetaouil 46:b1a9de66ecab 126 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
Yassinetaouil 46:b1a9de66ecab 127 #define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
Yassinetaouil 46:b1a9de66ecab 128 #define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
Yassinetaouil 46:b1a9de66ecab 129
Yassinetaouil 46:b1a9de66ecab 130
Yassinetaouil 46:b1a9de66ecab 131 /* Peripheral: AMLI */
Yassinetaouil 46:b1a9de66ecab 132 /* Description: AHB Multi-Layer Interface */
Yassinetaouil 46:b1a9de66ecab 133
Yassinetaouil 46:b1a9de66ecab 134 /* Register: AMLI_RAMPRI_CPU0 */
Yassinetaouil 46:b1a9de66ecab 135 /* Description: AHB bus master priority register for CPU0 */
Yassinetaouil 46:b1a9de66ecab 136
Yassinetaouil 46:b1a9de66ecab 137 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 138 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 139 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 140 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 141 #define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 142 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 143 #define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 144 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 145 #define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 146 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 147 #define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 148 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 149 #define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 150 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 151 #define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 152 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 153 #define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 154 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 155 #define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 156
Yassinetaouil 46:b1a9de66ecab 157 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 158 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 159 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 160 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 161 #define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 162 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 163 #define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 164 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 165 #define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 166 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 167 #define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 168 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 169 #define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 170 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 171 #define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 172 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 173 #define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 174 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 175 #define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 176
Yassinetaouil 46:b1a9de66ecab 177 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 178 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 179 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 180 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 181 #define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 182 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 183 #define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 184 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 185 #define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 186 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 187 #define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 188 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 189 #define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 190 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 191 #define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 192 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 193 #define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 194 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 195 #define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 196
Yassinetaouil 46:b1a9de66ecab 197 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 198 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 199 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 200 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 201 #define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 202 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 203 #define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 204 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 205 #define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 206 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 207 #define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 208 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 209 #define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 210 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 211 #define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 212 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 213 #define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 214 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 215 #define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 216
Yassinetaouil 46:b1a9de66ecab 217 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 218 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 219 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 220 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 221 #define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 222 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 223 #define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 224 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 225 #define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 226 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 227 #define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 228 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 229 #define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 230 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 231 #define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 232 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 233 #define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 234 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 235 #define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 236
Yassinetaouil 46:b1a9de66ecab 237 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 238 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 239 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 240 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 241 #define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 242 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 243 #define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 244 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 245 #define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 246 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 247 #define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 248 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 249 #define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 250 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 251 #define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 252 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 253 #define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 254 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 255 #define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 256
Yassinetaouil 46:b1a9de66ecab 257 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 258 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 259 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 260 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 261 #define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 262 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 263 #define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 264 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 265 #define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 266 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 267 #define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 268 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 269 #define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 270 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 271 #define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 272 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 273 #define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 274 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 275 #define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 276
Yassinetaouil 46:b1a9de66ecab 277 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 278 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 279 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 280 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 281 #define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 282 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 283 #define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 284 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 285 #define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 286 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 287 #define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 288 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 289 #define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 290 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 291 #define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 292 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 293 #define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 294 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 295 #define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 296
Yassinetaouil 46:b1a9de66ecab 297 /* Register: AMLI_RAMPRI_SPIS1 */
Yassinetaouil 46:b1a9de66ecab 298 /* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */
Yassinetaouil 46:b1a9de66ecab 299
Yassinetaouil 46:b1a9de66ecab 300 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 301 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 302 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 303 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 304 #define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 305 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 306 #define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 307 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 308 #define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 309 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 310 #define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 311 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 312 #define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 313 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 314 #define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 315 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 316 #define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 317 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 318 #define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 319
Yassinetaouil 46:b1a9de66ecab 320 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 321 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 322 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 323 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 324 #define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 325 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 326 #define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 327 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 328 #define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 329 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 330 #define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 331 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 332 #define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 333 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 334 #define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 335 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 336 #define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 337 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 338 #define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 339
Yassinetaouil 46:b1a9de66ecab 340 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 341 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 342 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 343 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 344 #define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 345 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 346 #define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 347 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 348 #define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 349 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 350 #define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 351 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 352 #define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 353 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 354 #define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 355 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 356 #define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 357 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 359
Yassinetaouil 46:b1a9de66ecab 360 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 361 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 362 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 363 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 364 #define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 365 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 366 #define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 367 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 368 #define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 369 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 370 #define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 371 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 379
Yassinetaouil 46:b1a9de66ecab 380 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 381 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 382 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 383 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 384 #define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 385 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 386 #define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 387 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 388 #define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 390 #define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 391 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 392 #define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 393 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 394 #define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 395 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 396 #define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 397 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 398 #define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 399
Yassinetaouil 46:b1a9de66ecab 400 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 401 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 402 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 403 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 404 #define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 405 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 406 #define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 407 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 408 #define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 409 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 410 #define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 411 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 412 #define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 413 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 414 #define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 415 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 416 #define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 417 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 418 #define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 419
Yassinetaouil 46:b1a9de66ecab 420 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 421 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 422 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 423 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 424 #define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 425 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 426 #define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 427 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 428 #define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 429 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 430 #define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 431 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 432 #define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 433 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 434 #define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 435 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 436 #define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 437 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 438 #define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 439
Yassinetaouil 46:b1a9de66ecab 440 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 441 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 442 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 443 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 444 #define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 445 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 446 #define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 447 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 448 #define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 449 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 450 #define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 451 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 452 #define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 453 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 454 #define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 455 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 456 #define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 457 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 458 #define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 459
Yassinetaouil 46:b1a9de66ecab 460 /* Register: AMLI_RAMPRI_RADIO */
Yassinetaouil 46:b1a9de66ecab 461 /* Description: AHB bus master priority register for RADIO */
Yassinetaouil 46:b1a9de66ecab 462
Yassinetaouil 46:b1a9de66ecab 463 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 464 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 465 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 466 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 467 #define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 468 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 469 #define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 470 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 471 #define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 472 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 473 #define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 474 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 475 #define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 476 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 477 #define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 478 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 479 #define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 480 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 481 #define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 482
Yassinetaouil 46:b1a9de66ecab 483 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 484 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 485 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 486 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 487 #define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 488 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 489 #define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 490 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 491 #define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 492 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 493 #define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 494 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 495 #define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 496 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 497 #define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 498 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 499 #define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 500 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 501 #define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 502
Yassinetaouil 46:b1a9de66ecab 503 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 504 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 505 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 506 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 507 #define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 508 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 509 #define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 510 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 511 #define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 512 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 513 #define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 514 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 515 #define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 516 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 517 #define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 518 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 519 #define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 520 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 521 #define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 522
Yassinetaouil 46:b1a9de66ecab 523 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 524 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 525 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 526 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 527 #define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 528 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 529 #define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 530 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 531 #define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 532 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 533 #define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 534 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 535 #define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 536 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 537 #define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 538 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 539 #define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 540 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 541 #define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 542
Yassinetaouil 46:b1a9de66ecab 543 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 544 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 545 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 546 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 547 #define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 548 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 549 #define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 550 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 551 #define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 552 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 553 #define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 554 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 555 #define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 556 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 557 #define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 558 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 559 #define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 560 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 561 #define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 562
Yassinetaouil 46:b1a9de66ecab 563 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 564 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 565 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 566 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 567 #define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 568 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 569 #define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 570 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 571 #define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 572 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 573 #define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 574 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 575 #define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 576 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 577 #define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 578 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 579 #define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 580 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 581 #define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 582
Yassinetaouil 46:b1a9de66ecab 583 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 584 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 585 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 586 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 587 #define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 588 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 589 #define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 590 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 591 #define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 592 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 593 #define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 594 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 595 #define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 596 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 597 #define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 598 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 599 #define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 600 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 601 #define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 602
Yassinetaouil 46:b1a9de66ecab 603 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 604 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 605 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 606 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 607 #define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 608 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 609 #define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 610 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 611 #define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 612 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 613 #define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 614 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 615 #define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 616 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 617 #define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 618 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 619 #define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 620 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 621 #define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 622
Yassinetaouil 46:b1a9de66ecab 623 /* Register: AMLI_RAMPRI_ECB */
Yassinetaouil 46:b1a9de66ecab 624 /* Description: AHB bus master priority register for ECB */
Yassinetaouil 46:b1a9de66ecab 625
Yassinetaouil 46:b1a9de66ecab 626 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 627 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 628 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 629 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 630 #define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 631 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 632 #define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 633 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 634 #define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 635 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 636 #define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 637 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 638 #define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 639 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 640 #define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 641 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 642 #define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 643 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 644 #define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 645
Yassinetaouil 46:b1a9de66ecab 646 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 647 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 648 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 649 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 650 #define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 651 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 652 #define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 653 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 654 #define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 655 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 656 #define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 657 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 658 #define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 659 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 660 #define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 661 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 662 #define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 663 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 664 #define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 665
Yassinetaouil 46:b1a9de66ecab 666 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 667 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 668 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 669 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 670 #define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 671 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 672 #define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 673 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 674 #define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 675 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 676 #define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 677 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 678 #define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 679 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 680 #define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 681 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 682 #define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 683 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 684 #define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 685
Yassinetaouil 46:b1a9de66ecab 686 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 687 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 688 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 689 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 690 #define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 691 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 692 #define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 693 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 694 #define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 695 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 696 #define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 697 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 698 #define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 699 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 700 #define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 701 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 702 #define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 703 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 704 #define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 705
Yassinetaouil 46:b1a9de66ecab 706 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 707 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 708 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 709 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 710 #define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 711 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 712 #define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 713 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 714 #define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 715 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 716 #define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 717 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 718 #define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 719 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 720 #define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 721 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 722 #define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 723 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 724 #define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 725
Yassinetaouil 46:b1a9de66ecab 726 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 727 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 728 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 729 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 730 #define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 731 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 732 #define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 733 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 734 #define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 735 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 736 #define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 737 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 738 #define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 739 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 740 #define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 741 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 742 #define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 743 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 744 #define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 745
Yassinetaouil 46:b1a9de66ecab 746 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 747 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 748 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 749 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 750 #define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 751 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 752 #define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 753 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 754 #define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 755 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 756 #define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 757 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 758 #define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 759 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 760 #define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 761 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 762 #define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 763 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 764 #define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 765
Yassinetaouil 46:b1a9de66ecab 766 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 767 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 768 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 769 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 770 #define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 771 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 772 #define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 773 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 774 #define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 775 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 776 #define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 777 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 778 #define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 779 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 780 #define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 781 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 782 #define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 783 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 784 #define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 785
Yassinetaouil 46:b1a9de66ecab 786 /* Register: AMLI_RAMPRI_CCM */
Yassinetaouil 46:b1a9de66ecab 787 /* Description: AHB bus master priority register for CCM */
Yassinetaouil 46:b1a9de66ecab 788
Yassinetaouil 46:b1a9de66ecab 789 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 790 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 791 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 792 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 793 #define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 794 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 795 #define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 796 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 797 #define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 798 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 799 #define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 800 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 801 #define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 802 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 803 #define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 804 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 805 #define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 806 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 807 #define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 808
Yassinetaouil 46:b1a9de66ecab 809 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 810 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 811 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 812 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 813 #define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 814 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 815 #define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 816 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 817 #define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 818 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 819 #define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 820 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 821 #define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 822 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 823 #define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 824 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 825 #define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 826 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 827 #define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 828
Yassinetaouil 46:b1a9de66ecab 829 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 830 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 831 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 832 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 833 #define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 834 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 835 #define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 836 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 837 #define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 838 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 839 #define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 840 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 841 #define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 842 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 843 #define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 844 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 845 #define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 846 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 847 #define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 848
Yassinetaouil 46:b1a9de66ecab 849 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 850 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 851 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 852 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 853 #define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 854 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 855 #define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 856 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 857 #define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 858 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 859 #define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 860 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 861 #define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 862 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 863 #define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 864 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 865 #define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 866 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 867 #define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 868
Yassinetaouil 46:b1a9de66ecab 869 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 870 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 871 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 872 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 873 #define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 874 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 875 #define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 876 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 877 #define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 878 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 879 #define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 880 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 881 #define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 882 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 883 #define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 884 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 885 #define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 886 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 887 #define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 888
Yassinetaouil 46:b1a9de66ecab 889 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 890 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 891 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 892 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 893 #define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 894 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 895 #define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 896 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 897 #define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 898 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 899 #define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 900 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 901 #define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 902 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 903 #define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 904 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 905 #define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 906 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 907 #define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 908
Yassinetaouil 46:b1a9de66ecab 909 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 910 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 911 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 912 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 913 #define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 914 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 915 #define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 916 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 917 #define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 918 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 919 #define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 920 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 921 #define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 922 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 923 #define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 924 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 925 #define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 926 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 927 #define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 928
Yassinetaouil 46:b1a9de66ecab 929 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 930 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 931 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 932 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 933 #define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 934 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 935 #define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 936 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 937 #define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 938 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 939 #define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 940 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 941 #define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 942 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 943 #define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 944 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 945 #define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 946 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 947 #define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 948
Yassinetaouil 46:b1a9de66ecab 949 /* Register: AMLI_RAMPRI_AAR */
Yassinetaouil 46:b1a9de66ecab 950 /* Description: AHB bus master priority register for AAR */
Yassinetaouil 46:b1a9de66ecab 951
Yassinetaouil 46:b1a9de66ecab 952 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 953 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 954 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 955 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 956 #define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 957 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 958 #define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 959 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 960 #define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 961 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 962 #define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 963 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 964 #define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 965 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 966 #define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 967 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 968 #define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 969 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 970 #define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 971
Yassinetaouil 46:b1a9de66ecab 972 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 973 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 974 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 975 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 976 #define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 977 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 978 #define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 979 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 980 #define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 981 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 982 #define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 983 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 984 #define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 985 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 986 #define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 987 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 988 #define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 989 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 990 #define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 991
Yassinetaouil 46:b1a9de66ecab 992 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 993 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 994 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 995 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 996 #define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 997 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 998 #define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 999 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1000 #define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1001 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1002 #define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1003 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1004 #define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1005 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1006 #define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1007 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1008 #define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1009 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1010 #define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1011
Yassinetaouil 46:b1a9de66ecab 1012 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 1013 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1014 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1015 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1016 #define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1017 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1018 #define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1019 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1020 #define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1021 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1022 #define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1023 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1024 #define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1025 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1026 #define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1027 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1028 #define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1029 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1030 #define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1031
Yassinetaouil 46:b1a9de66ecab 1032 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 1033 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1034 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1035 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1036 #define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1037 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1038 #define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1039 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1040 #define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1041 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1042 #define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1043 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1044 #define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1045 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1046 #define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1047 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1048 #define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1049 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1050 #define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1051
Yassinetaouil 46:b1a9de66ecab 1052 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 1053 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1054 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1055 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1056 #define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1057 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1058 #define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1059 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1060 #define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1061 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1062 #define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1063 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1064 #define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1065 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1066 #define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1067 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1068 #define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1069 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1070 #define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1071
Yassinetaouil 46:b1a9de66ecab 1072 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 1073 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1074 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1075 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1076 #define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1077 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1078 #define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1079 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1080 #define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1081 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1082 #define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1083 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1084 #define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1085 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1086 #define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1087 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1088 #define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1089 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1090 #define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1091
Yassinetaouil 46:b1a9de66ecab 1092 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 1093 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1094 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1095 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1096 #define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1097 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1098 #define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1099 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1100 #define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1101 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1102 #define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1103 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1104 #define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1105 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1106 #define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1107 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1108 #define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1109 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1110 #define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1111
Yassinetaouil 46:b1a9de66ecab 1112 /* Register: AMLI_RAMPRI_SAADC */
Yassinetaouil 46:b1a9de66ecab 1113 /* Description: AHB bus master priority register for SAADC */
Yassinetaouil 46:b1a9de66ecab 1114
Yassinetaouil 46:b1a9de66ecab 1115 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 1116 #define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1117 #define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1118 #define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1119 #define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1120 #define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1121 #define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1122 #define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1123 #define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1124 #define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1125 #define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1126 #define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1127 #define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1128 #define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1129 #define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1130 #define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1131 #define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1132 #define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1133 #define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1134
Yassinetaouil 46:b1a9de66ecab 1135 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 1136 #define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1137 #define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1138 #define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1139 #define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1140 #define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1141 #define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1142 #define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1143 #define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1144 #define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1145 #define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1146 #define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1147 #define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1148 #define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1149 #define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1150 #define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1151 #define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1152 #define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1153 #define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1154
Yassinetaouil 46:b1a9de66ecab 1155 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 1156 #define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1157 #define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1158 #define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1159 #define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1160 #define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1161 #define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1162 #define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1163 #define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1164 #define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1165 #define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1166 #define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1167 #define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1168 #define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1169 #define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1170 #define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1171 #define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1172 #define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1173 #define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1174
Yassinetaouil 46:b1a9de66ecab 1175 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 1176 #define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1177 #define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1178 #define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1179 #define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1180 #define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1181 #define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1182 #define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1183 #define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1184 #define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1185 #define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1186 #define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1187 #define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1188 #define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1189 #define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1190 #define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1191 #define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1192 #define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1193 #define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1194
Yassinetaouil 46:b1a9de66ecab 1195 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 1196 #define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1197 #define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1198 #define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1199 #define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1200 #define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1201 #define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1202 #define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1203 #define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1204 #define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1205 #define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1206 #define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1207 #define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1208 #define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1209 #define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1210 #define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1211 #define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1212 #define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1213 #define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1214
Yassinetaouil 46:b1a9de66ecab 1215 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 1216 #define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1217 #define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1218 #define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1219 #define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1220 #define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1221 #define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1222 #define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1223 #define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1224 #define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1225 #define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1226 #define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1227 #define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1228 #define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1229 #define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1230 #define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1231 #define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1232 #define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1233 #define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1234
Yassinetaouil 46:b1a9de66ecab 1235 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 1236 #define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1237 #define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1238 #define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1239 #define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1240 #define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1241 #define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1242 #define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1243 #define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1244 #define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1245 #define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1246 #define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1247 #define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1248 #define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1249 #define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1250 #define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1251 #define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1252 #define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1253 #define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1254
Yassinetaouil 46:b1a9de66ecab 1255 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 1256 #define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1257 #define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1258 #define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1259 #define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1260 #define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1261 #define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1262 #define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1263 #define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1264 #define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1265 #define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1266 #define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1267 #define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1268 #define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1269 #define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1270 #define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1271 #define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1272 #define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1273 #define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1274
Yassinetaouil 46:b1a9de66ecab 1275 /* Register: AMLI_RAMPRI_UARTE */
Yassinetaouil 46:b1a9de66ecab 1276 /* Description: AHB bus master priority register for UARTE */
Yassinetaouil 46:b1a9de66ecab 1277
Yassinetaouil 46:b1a9de66ecab 1278 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 1279 #define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1280 #define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1281 #define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1282 #define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1283 #define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1284 #define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1285 #define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1286 #define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1287 #define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1288 #define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1289 #define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1290 #define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1291 #define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1292 #define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1293 #define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1294 #define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1295 #define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1296 #define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1297
Yassinetaouil 46:b1a9de66ecab 1298 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 1299 #define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1300 #define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1301 #define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1302 #define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1303 #define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1304 #define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1305 #define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1306 #define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1307 #define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1308 #define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1309 #define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1310 #define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1311 #define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1312 #define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1313 #define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1314 #define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1315 #define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1316 #define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1317
Yassinetaouil 46:b1a9de66ecab 1318 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 1319 #define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1320 #define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1321 #define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1322 #define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1323 #define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1324 #define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1325 #define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1326 #define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1327 #define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1328 #define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1329 #define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1330 #define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1331 #define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1332 #define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1333 #define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1334 #define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1335 #define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1336 #define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1337
Yassinetaouil 46:b1a9de66ecab 1338 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 1339 #define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1340 #define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1341 #define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1342 #define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1343 #define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1344 #define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1345 #define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1346 #define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1347 #define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1348 #define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1349 #define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1350 #define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1351 #define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1352 #define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1353 #define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1354 #define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1355 #define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1356 #define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1357
Yassinetaouil 46:b1a9de66ecab 1358 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 1359 #define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1360 #define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1361 #define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1362 #define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1363 #define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1364 #define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1365 #define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1366 #define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1367 #define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1368 #define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1369 #define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1370 #define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1371 #define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1372 #define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1373 #define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1374 #define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1375 #define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1376 #define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1377
Yassinetaouil 46:b1a9de66ecab 1378 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 1379 #define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1380 #define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1381 #define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1382 #define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1383 #define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1384 #define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1385 #define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1386 #define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1387 #define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1388 #define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1389 #define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1390 #define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1391 #define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1392 #define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1393 #define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1394 #define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1395 #define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1396 #define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1397
Yassinetaouil 46:b1a9de66ecab 1398 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 1399 #define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1400 #define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1401 #define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1402 #define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1403 #define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1404 #define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1405 #define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1406 #define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1407 #define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1408 #define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1409 #define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1410 #define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1411 #define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1412 #define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1413 #define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1414 #define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1415 #define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1416 #define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1417
Yassinetaouil 46:b1a9de66ecab 1418 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 1419 #define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1420 #define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1421 #define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1422 #define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1423 #define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1424 #define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1425 #define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1426 #define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1427 #define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1428 #define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1429 #define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1430 #define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1431 #define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1432 #define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1433 #define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1434 #define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1435 #define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1436 #define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1437
Yassinetaouil 46:b1a9de66ecab 1438 /* Register: AMLI_RAMPRI_SERIAL0 */
Yassinetaouil 46:b1a9de66ecab 1439 /* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */
Yassinetaouil 46:b1a9de66ecab 1440
Yassinetaouil 46:b1a9de66ecab 1441 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 1442 #define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1443 #define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1444 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1445 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1446 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1447 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1448 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1449 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1450 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1451 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1452 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1453 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1454 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1455 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1456 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1457 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1458 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1459 #define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1460
Yassinetaouil 46:b1a9de66ecab 1461 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 1462 #define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1463 #define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1464 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1465 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1466 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1467 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1468 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1469 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1470 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1471 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1472 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1473 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1474 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1475 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1476 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1477 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1478 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1479 #define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1480
Yassinetaouil 46:b1a9de66ecab 1481 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 1482 #define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1483 #define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1484 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1485 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1486 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1487 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1488 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1489 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1490 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1491 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1492 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1493 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1494 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1495 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1496 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1497 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1498 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1499 #define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1500
Yassinetaouil 46:b1a9de66ecab 1501 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 1502 #define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1503 #define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1504 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1505 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1506 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1507 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1508 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1509 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1510 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1511 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1512 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1513 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1514 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1515 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1516 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1517 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1518 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1519 #define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1520
Yassinetaouil 46:b1a9de66ecab 1521 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 1522 #define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1523 #define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1524 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1525 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1526 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1527 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1528 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1529 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1530 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1531 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1532 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1533 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1534 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1535 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1536 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1537 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1538 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1539 #define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1540
Yassinetaouil 46:b1a9de66ecab 1541 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 1542 #define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1543 #define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1544 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1545 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1546 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1547 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1548 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1549 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1550 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1551 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1552 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1553 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1554 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1555 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1556 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1557 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1558 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1559 #define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1560
Yassinetaouil 46:b1a9de66ecab 1561 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 1562 #define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1563 #define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1564 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1565 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1566 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1567 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1568 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1569 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1570 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1571 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1572 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1573 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1574 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1575 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1576 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1577 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1578 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1579 #define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1580
Yassinetaouil 46:b1a9de66ecab 1581 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 1582 #define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1583 #define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1584 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1585 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1586 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1587 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1588 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1589 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1590 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1591 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1592 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1593 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1594 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1595 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1596 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1597 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1598 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1599 #define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1600
Yassinetaouil 46:b1a9de66ecab 1601 /* Register: AMLI_RAMPRI_SERIAL2 */
Yassinetaouil 46:b1a9de66ecab 1602 /* Description: AHB bus master priority register for SPIM2 and SPIS2 */
Yassinetaouil 46:b1a9de66ecab 1603
Yassinetaouil 46:b1a9de66ecab 1604 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 1605 #define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1606 #define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1607 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1608 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1609 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1610 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1611 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1612 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1613 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1614 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1615 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1616 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1617 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1618 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1619 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1620 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1621 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1622 #define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1623
Yassinetaouil 46:b1a9de66ecab 1624 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 1625 #define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1626 #define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1627 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1628 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1629 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1630 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1631 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1632 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1633 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1634 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1635 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1636 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1637 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1638 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1639 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1640 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1641 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1642 #define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1643
Yassinetaouil 46:b1a9de66ecab 1644 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 1645 #define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1646 #define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1647 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1648 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1649 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1650 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1651 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1652 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1653 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1654 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1655 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1656 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1657 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1658 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1659 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1660 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1661 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1662 #define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1663
Yassinetaouil 46:b1a9de66ecab 1664 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 1665 #define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1666 #define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1667 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1668 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1669 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1670 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1671 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1672 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1673 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1674 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1675 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1676 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1677 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1678 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1679 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1680 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1681 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1682 #define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1683
Yassinetaouil 46:b1a9de66ecab 1684 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 1685 #define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1686 #define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1687 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1688 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1689 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1690 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1691 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1692 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1693 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1694 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1695 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1696 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1697 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1698 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1699 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1700 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1701 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1702 #define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1703
Yassinetaouil 46:b1a9de66ecab 1704 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 1705 #define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1706 #define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1707 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1708 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1709 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1710 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1711 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1712 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1713 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1714 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1715 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1716 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1717 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1718 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1719 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1720 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1721 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1722 #define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1723
Yassinetaouil 46:b1a9de66ecab 1724 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 1725 #define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1726 #define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1727 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1728 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1729 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1730 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1731 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1732 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1733 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1734 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1735 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1736 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1737 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1738 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1739 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1740 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1741 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1742 #define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1743
Yassinetaouil 46:b1a9de66ecab 1744 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 1745 #define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1746 #define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1747 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1748 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1749 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1750 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1751 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1752 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1753 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1754 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1755 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1756 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1757 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1758 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1759 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1760 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1761 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1762 #define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1763
Yassinetaouil 46:b1a9de66ecab 1764 /* Register: AMLI_RAMPRI_NFCT */
Yassinetaouil 46:b1a9de66ecab 1765 /* Description: AHB bus master priority register for NFCT */
Yassinetaouil 46:b1a9de66ecab 1766
Yassinetaouil 46:b1a9de66ecab 1767 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 1768 #define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1769 #define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1770 #define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1771 #define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1772 #define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1773 #define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1774 #define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1775 #define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1776 #define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1777 #define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1778 #define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1779 #define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1780 #define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1781 #define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1782 #define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1783 #define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1784 #define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1785 #define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1786
Yassinetaouil 46:b1a9de66ecab 1787 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 1788 #define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1789 #define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1790 #define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1791 #define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1792 #define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1793 #define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1794 #define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1795 #define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1796 #define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1797 #define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1798 #define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1799 #define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1800 #define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1801 #define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1802 #define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1803 #define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1804 #define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1805 #define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1806
Yassinetaouil 46:b1a9de66ecab 1807 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 1808 #define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1809 #define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1810 #define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1811 #define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1812 #define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1813 #define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1814 #define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1815 #define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1816 #define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1817 #define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1818 #define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1819 #define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1820 #define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1821 #define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1822 #define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1823 #define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1824 #define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1825 #define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1826
Yassinetaouil 46:b1a9de66ecab 1827 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 1828 #define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1829 #define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1830 #define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1831 #define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1832 #define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1833 #define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1834 #define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1835 #define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1836 #define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1837 #define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1838 #define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1839 #define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1840 #define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1841 #define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1842 #define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1843 #define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1844 #define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1845 #define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1846
Yassinetaouil 46:b1a9de66ecab 1847 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 1848 #define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1849 #define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 1850 #define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1851 #define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1852 #define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1853 #define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1854 #define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1855 #define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1856 #define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1857 #define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1858 #define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1859 #define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1860 #define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1861 #define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1862 #define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1863 #define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1864 #define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1865 #define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1866
Yassinetaouil 46:b1a9de66ecab 1867 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 1868 #define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1869 #define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 1870 #define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1871 #define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1872 #define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1873 #define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1874 #define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1875 #define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1876 #define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1877 #define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1878 #define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1879 #define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1880 #define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1881 #define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1882 #define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1883 #define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1884 #define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1885 #define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1886
Yassinetaouil 46:b1a9de66ecab 1887 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 1888 #define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1889 #define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 1890 #define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1891 #define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1892 #define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1893 #define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1894 #define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1895 #define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1896 #define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1897 #define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1898 #define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1899 #define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1900 #define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1901 #define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1902 #define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1903 #define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1904 #define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1905 #define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1906
Yassinetaouil 46:b1a9de66ecab 1907 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 1908 #define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1909 #define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 1910 #define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1911 #define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1912 #define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1913 #define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1914 #define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1915 #define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1916 #define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1917 #define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1918 #define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1919 #define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1920 #define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1921 #define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1922 #define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1923 #define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1924 #define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1925 #define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1926
Yassinetaouil 46:b1a9de66ecab 1927 /* Register: AMLI_RAMPRI_I2S */
Yassinetaouil 46:b1a9de66ecab 1928 /* Description: AHB bus master priority register for I2S */
Yassinetaouil 46:b1a9de66ecab 1929
Yassinetaouil 46:b1a9de66ecab 1930 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 1931 #define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1932 #define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 1933 #define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1934 #define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1935 #define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1936 #define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1937 #define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1938 #define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1939 #define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1940 #define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1941 #define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1942 #define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1943 #define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1944 #define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1945 #define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1946 #define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1947 #define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1948 #define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1949
Yassinetaouil 46:b1a9de66ecab 1950 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 1951 #define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1952 #define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 1953 #define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1954 #define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1955 #define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1956 #define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1957 #define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1958 #define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1959 #define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1960 #define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1961 #define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1962 #define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1963 #define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1964 #define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1965 #define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1966 #define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1967 #define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1968 #define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1969
Yassinetaouil 46:b1a9de66ecab 1970 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 1971 #define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1972 #define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 1973 #define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1974 #define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1975 #define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1976 #define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1977 #define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1978 #define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1979 #define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 1980 #define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 1981 #define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 1982 #define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 1983 #define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 1984 #define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 1985 #define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 1986 #define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 1987 #define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 1988 #define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 1989
Yassinetaouil 46:b1a9de66ecab 1990 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 1991 #define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1992 #define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 1993 #define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 1994 #define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 1995 #define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 1996 #define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 1997 #define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 1998 #define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 1999 #define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2000 #define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2001 #define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2002 #define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2003 #define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2004 #define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2005 #define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2006 #define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2007 #define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2008 #define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2009
Yassinetaouil 46:b1a9de66ecab 2010 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 2011 #define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 2012 #define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 2013 #define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2014 #define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2015 #define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2016 #define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2017 #define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2018 #define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2019 #define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2020 #define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2021 #define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2022 #define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2023 #define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2024 #define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2025 #define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2026 #define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2027 #define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2028 #define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2029
Yassinetaouil 46:b1a9de66ecab 2030 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 2031 #define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 2032 #define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 2033 #define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2034 #define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2035 #define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2036 #define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2037 #define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2038 #define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2039 #define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2040 #define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2041 #define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2042 #define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2043 #define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2044 #define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2045 #define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2046 #define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2047 #define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2048 #define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2049
Yassinetaouil 46:b1a9de66ecab 2050 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 2051 #define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 2052 #define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 2053 #define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2054 #define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2055 #define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2056 #define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2057 #define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2058 #define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2059 #define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2060 #define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2061 #define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2062 #define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2063 #define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2064 #define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2065 #define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2066 #define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2067 #define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2068 #define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2069
Yassinetaouil 46:b1a9de66ecab 2070 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 2071 #define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 2072 #define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 2073 #define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2074 #define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2075 #define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2076 #define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2077 #define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2078 #define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2079 #define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2080 #define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2081 #define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2082 #define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2083 #define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2084 #define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2085 #define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2086 #define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2087 #define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2088 #define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2089
Yassinetaouil 46:b1a9de66ecab 2090 /* Register: AMLI_RAMPRI_PDM */
Yassinetaouil 46:b1a9de66ecab 2091 /* Description: AHB bus master priority register for PDM */
Yassinetaouil 46:b1a9de66ecab 2092
Yassinetaouil 46:b1a9de66ecab 2093 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 2094 #define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 2095 #define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 2096 #define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2097 #define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2098 #define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2099 #define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2100 #define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2101 #define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2102 #define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2103 #define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2104 #define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2105 #define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2106 #define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2107 #define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2108 #define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2109 #define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2110 #define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2111 #define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2112
Yassinetaouil 46:b1a9de66ecab 2113 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 2114 #define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 2115 #define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 2116 #define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2117 #define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2118 #define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2119 #define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2120 #define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2121 #define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2122 #define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2123 #define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2124 #define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2125 #define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2126 #define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2127 #define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2128 #define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2129 #define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2130 #define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2131 #define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2132
Yassinetaouil 46:b1a9de66ecab 2133 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 2134 #define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 2135 #define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 2136 #define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2137 #define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2138 #define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2139 #define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2140 #define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2141 #define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2142 #define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2143 #define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2144 #define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2145 #define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2146 #define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2147 #define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2148 #define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2149 #define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2150 #define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2151 #define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2152
Yassinetaouil 46:b1a9de66ecab 2153 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 2154 #define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 2155 #define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 2156 #define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2157 #define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2158 #define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2159 #define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2160 #define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2161 #define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2162 #define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2163 #define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2164 #define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2165 #define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2166 #define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2167 #define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2168 #define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2169 #define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2170 #define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2171 #define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2172
Yassinetaouil 46:b1a9de66ecab 2173 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 2174 #define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 2175 #define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 2176 #define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2177 #define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2178 #define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2179 #define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2180 #define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2181 #define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2182 #define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2183 #define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2184 #define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2185 #define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2186 #define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2187 #define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2188 #define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2189 #define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2190 #define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2191 #define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2192
Yassinetaouil 46:b1a9de66ecab 2193 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 2194 #define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 2195 #define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 2196 #define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2197 #define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2198 #define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2199 #define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2200 #define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2201 #define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2202 #define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2203 #define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2204 #define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2205 #define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2206 #define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2207 #define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2208 #define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2209 #define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2210 #define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2211 #define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2212
Yassinetaouil 46:b1a9de66ecab 2213 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 2214 #define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 2215 #define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 2216 #define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2217 #define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2218 #define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2219 #define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2220 #define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2221 #define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2222 #define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2223 #define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2224 #define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2225 #define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2226 #define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2227 #define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2228 #define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2229 #define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2230 #define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2231 #define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2232
Yassinetaouil 46:b1a9de66ecab 2233 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 2234 #define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 2235 #define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 2236 #define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2237 #define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2238 #define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2239 #define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2240 #define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2241 #define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2242 #define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2243 #define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2244 #define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2245 #define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2246 #define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2247 #define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2248 #define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2249 #define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2250 #define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2251 #define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2252
Yassinetaouil 46:b1a9de66ecab 2253 /* Register: AMLI_RAMPRI_PWM */
Yassinetaouil 46:b1a9de66ecab 2254 /* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */
Yassinetaouil 46:b1a9de66ecab 2255
Yassinetaouil 46:b1a9de66ecab 2256 /* Bits 31..28 : Priority register for RAM AHB slave 7 */
Yassinetaouil 46:b1a9de66ecab 2257 #define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 2258 #define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
Yassinetaouil 46:b1a9de66ecab 2259 #define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2260 #define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2261 #define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2262 #define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2263 #define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2264 #define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2265 #define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2266 #define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2267 #define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2268 #define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2269 #define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2270 #define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2271 #define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2272 #define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2273 #define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2274 #define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2275
Yassinetaouil 46:b1a9de66ecab 2276 /* Bits 27..24 : Priority register for RAM AHB slave 6 */
Yassinetaouil 46:b1a9de66ecab 2277 #define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 2278 #define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
Yassinetaouil 46:b1a9de66ecab 2279 #define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2280 #define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2281 #define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2282 #define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2283 #define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2284 #define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2285 #define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2286 #define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2287 #define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2288 #define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2289 #define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2290 #define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2291 #define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2292 #define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2293 #define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2294 #define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2295
Yassinetaouil 46:b1a9de66ecab 2296 /* Bits 23..20 : Priority register for RAM AHB slave 5 */
Yassinetaouil 46:b1a9de66ecab 2297 #define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 2298 #define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
Yassinetaouil 46:b1a9de66ecab 2299 #define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2300 #define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2301 #define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2302 #define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2303 #define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2304 #define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2305 #define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2306 #define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2307 #define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2308 #define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2309 #define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2310 #define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2311 #define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2312 #define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2313 #define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2314 #define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2315
Yassinetaouil 46:b1a9de66ecab 2316 /* Bits 19..16 : Priority register for RAM AHB slave 4 */
Yassinetaouil 46:b1a9de66ecab 2317 #define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 2318 #define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
Yassinetaouil 46:b1a9de66ecab 2319 #define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2320 #define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2321 #define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2322 #define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2323 #define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2324 #define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2325 #define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2326 #define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2327 #define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2328 #define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2329 #define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2330 #define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2331 #define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2332 #define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2333 #define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2334 #define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2335
Yassinetaouil 46:b1a9de66ecab 2336 /* Bits 15..12 : Priority register for RAM AHB slave 3 */
Yassinetaouil 46:b1a9de66ecab 2337 #define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 2338 #define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Yassinetaouil 46:b1a9de66ecab 2339 #define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2340 #define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2341 #define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2342 #define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2343 #define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2344 #define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2345 #define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2346 #define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2347 #define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2348 #define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2349 #define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2350 #define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2351 #define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2352 #define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2353 #define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2354 #define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2355
Yassinetaouil 46:b1a9de66ecab 2356 /* Bits 11..8 : Priority register for RAM AHB slave 2 */
Yassinetaouil 46:b1a9de66ecab 2357 #define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 2358 #define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Yassinetaouil 46:b1a9de66ecab 2359 #define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2360 #define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2361 #define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2362 #define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2363 #define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2364 #define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2365 #define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2366 #define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2367 #define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2368 #define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2369 #define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2370 #define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2371 #define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2372 #define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2373 #define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2374 #define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2375
Yassinetaouil 46:b1a9de66ecab 2376 /* Bits 7..4 : Priority register for RAM AHB slave 1 */
Yassinetaouil 46:b1a9de66ecab 2377 #define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 2378 #define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Yassinetaouil 46:b1a9de66ecab 2379 #define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2380 #define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2381 #define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2382 #define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2383 #define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2384 #define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2385 #define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2386 #define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2387 #define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2388 #define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2389 #define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2390 #define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2391 #define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2392 #define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2393 #define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2394 #define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2395
Yassinetaouil 46:b1a9de66ecab 2396 /* Bits 3..0 : Priority register for RAM AHB slave 0 */
Yassinetaouil 46:b1a9de66ecab 2397 #define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 2398 #define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Yassinetaouil 46:b1a9de66ecab 2399 #define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */
Yassinetaouil 46:b1a9de66ecab 2400 #define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */
Yassinetaouil 46:b1a9de66ecab 2401 #define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */
Yassinetaouil 46:b1a9de66ecab 2402 #define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */
Yassinetaouil 46:b1a9de66ecab 2403 #define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */
Yassinetaouil 46:b1a9de66ecab 2404 #define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */
Yassinetaouil 46:b1a9de66ecab 2405 #define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */
Yassinetaouil 46:b1a9de66ecab 2406 #define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */
Yassinetaouil 46:b1a9de66ecab 2407 #define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */
Yassinetaouil 46:b1a9de66ecab 2408 #define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */
Yassinetaouil 46:b1a9de66ecab 2409 #define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */
Yassinetaouil 46:b1a9de66ecab 2410 #define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */
Yassinetaouil 46:b1a9de66ecab 2411 #define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */
Yassinetaouil 46:b1a9de66ecab 2412 #define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */
Yassinetaouil 46:b1a9de66ecab 2413 #define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */
Yassinetaouil 46:b1a9de66ecab 2414 #define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */
Yassinetaouil 46:b1a9de66ecab 2415
Yassinetaouil 46:b1a9de66ecab 2416
Yassinetaouil 46:b1a9de66ecab 2417 /* Peripheral: BPROT */
Yassinetaouil 46:b1a9de66ecab 2418 /* Description: Block Protect */
Yassinetaouil 46:b1a9de66ecab 2419
Yassinetaouil 46:b1a9de66ecab 2420 /* Register: BPROT_CONFIG0 */
Yassinetaouil 46:b1a9de66ecab 2421 /* Description: Block protect configuration register 0 */
Yassinetaouil 46:b1a9de66ecab 2422
Yassinetaouil 46:b1a9de66ecab 2423 /* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2424 #define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
Yassinetaouil 46:b1a9de66ecab 2425 #define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
Yassinetaouil 46:b1a9de66ecab 2426 #define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2427 #define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2428
Yassinetaouil 46:b1a9de66ecab 2429 /* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2430 #define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
Yassinetaouil 46:b1a9de66ecab 2431 #define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
Yassinetaouil 46:b1a9de66ecab 2432 #define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2433 #define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2434
Yassinetaouil 46:b1a9de66ecab 2435 /* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2436 #define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
Yassinetaouil 46:b1a9de66ecab 2437 #define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
Yassinetaouil 46:b1a9de66ecab 2438 #define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2439 #define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2440
Yassinetaouil 46:b1a9de66ecab 2441 /* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2442 #define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
Yassinetaouil 46:b1a9de66ecab 2443 #define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
Yassinetaouil 46:b1a9de66ecab 2444 #define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2445 #define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2446
Yassinetaouil 46:b1a9de66ecab 2447 /* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2448 #define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
Yassinetaouil 46:b1a9de66ecab 2449 #define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
Yassinetaouil 46:b1a9de66ecab 2450 #define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2451 #define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2452
Yassinetaouil 46:b1a9de66ecab 2453 /* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2454 #define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
Yassinetaouil 46:b1a9de66ecab 2455 #define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
Yassinetaouil 46:b1a9de66ecab 2456 #define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2457 #define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2458
Yassinetaouil 46:b1a9de66ecab 2459 /* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2460 #define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
Yassinetaouil 46:b1a9de66ecab 2461 #define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
Yassinetaouil 46:b1a9de66ecab 2462 #define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2463 #define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2464
Yassinetaouil 46:b1a9de66ecab 2465 /* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2466 #define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
Yassinetaouil 46:b1a9de66ecab 2467 #define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
Yassinetaouil 46:b1a9de66ecab 2468 #define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2469 #define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2470
Yassinetaouil 46:b1a9de66ecab 2471 /* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2472 #define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
Yassinetaouil 46:b1a9de66ecab 2473 #define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
Yassinetaouil 46:b1a9de66ecab 2474 #define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2475 #define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2476
Yassinetaouil 46:b1a9de66ecab 2477 /* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2478 #define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
Yassinetaouil 46:b1a9de66ecab 2479 #define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
Yassinetaouil 46:b1a9de66ecab 2480 #define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2481 #define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2482
Yassinetaouil 46:b1a9de66ecab 2483 /* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2484 #define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
Yassinetaouil 46:b1a9de66ecab 2485 #define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
Yassinetaouil 46:b1a9de66ecab 2486 #define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2487 #define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2488
Yassinetaouil 46:b1a9de66ecab 2489 /* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2490 #define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
Yassinetaouil 46:b1a9de66ecab 2491 #define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
Yassinetaouil 46:b1a9de66ecab 2492 #define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2493 #define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2494
Yassinetaouil 46:b1a9de66ecab 2495 /* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2496 #define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
Yassinetaouil 46:b1a9de66ecab 2497 #define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
Yassinetaouil 46:b1a9de66ecab 2498 #define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2499 #define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2500
Yassinetaouil 46:b1a9de66ecab 2501 /* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2502 #define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
Yassinetaouil 46:b1a9de66ecab 2503 #define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
Yassinetaouil 46:b1a9de66ecab 2504 #define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2505 #define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2506
Yassinetaouil 46:b1a9de66ecab 2507 /* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2508 #define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
Yassinetaouil 46:b1a9de66ecab 2509 #define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
Yassinetaouil 46:b1a9de66ecab 2510 #define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2511 #define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2512
Yassinetaouil 46:b1a9de66ecab 2513 /* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2514 #define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
Yassinetaouil 46:b1a9de66ecab 2515 #define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
Yassinetaouil 46:b1a9de66ecab 2516 #define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2517 #define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2518
Yassinetaouil 46:b1a9de66ecab 2519 /* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2520 #define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
Yassinetaouil 46:b1a9de66ecab 2521 #define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
Yassinetaouil 46:b1a9de66ecab 2522 #define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2523 #define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2524
Yassinetaouil 46:b1a9de66ecab 2525 /* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2526 #define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
Yassinetaouil 46:b1a9de66ecab 2527 #define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
Yassinetaouil 46:b1a9de66ecab 2528 #define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2529 #define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2530
Yassinetaouil 46:b1a9de66ecab 2531 /* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2532 #define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
Yassinetaouil 46:b1a9de66ecab 2533 #define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
Yassinetaouil 46:b1a9de66ecab 2534 #define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2535 #define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2536
Yassinetaouil 46:b1a9de66ecab 2537 /* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2538 #define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
Yassinetaouil 46:b1a9de66ecab 2539 #define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
Yassinetaouil 46:b1a9de66ecab 2540 #define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2541 #define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2542
Yassinetaouil 46:b1a9de66ecab 2543 /* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2544 #define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
Yassinetaouil 46:b1a9de66ecab 2545 #define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
Yassinetaouil 46:b1a9de66ecab 2546 #define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2547 #define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2548
Yassinetaouil 46:b1a9de66ecab 2549 /* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2550 #define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
Yassinetaouil 46:b1a9de66ecab 2551 #define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
Yassinetaouil 46:b1a9de66ecab 2552 #define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2553 #define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2554
Yassinetaouil 46:b1a9de66ecab 2555 /* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2556 #define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
Yassinetaouil 46:b1a9de66ecab 2557 #define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
Yassinetaouil 46:b1a9de66ecab 2558 #define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2559 #define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2560
Yassinetaouil 46:b1a9de66ecab 2561 /* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2562 #define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
Yassinetaouil 46:b1a9de66ecab 2563 #define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
Yassinetaouil 46:b1a9de66ecab 2564 #define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2565 #define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2566
Yassinetaouil 46:b1a9de66ecab 2567 /* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2568 #define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
Yassinetaouil 46:b1a9de66ecab 2569 #define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
Yassinetaouil 46:b1a9de66ecab 2570 #define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2571 #define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2572
Yassinetaouil 46:b1a9de66ecab 2573 /* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2574 #define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
Yassinetaouil 46:b1a9de66ecab 2575 #define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
Yassinetaouil 46:b1a9de66ecab 2576 #define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2577 #define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2578
Yassinetaouil 46:b1a9de66ecab 2579 /* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2580 #define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
Yassinetaouil 46:b1a9de66ecab 2581 #define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
Yassinetaouil 46:b1a9de66ecab 2582 #define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2583 #define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2584
Yassinetaouil 46:b1a9de66ecab 2585 /* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2586 #define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
Yassinetaouil 46:b1a9de66ecab 2587 #define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
Yassinetaouil 46:b1a9de66ecab 2588 #define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2589 #define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2590
Yassinetaouil 46:b1a9de66ecab 2591 /* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2592 #define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
Yassinetaouil 46:b1a9de66ecab 2593 #define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
Yassinetaouil 46:b1a9de66ecab 2594 #define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2595 #define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2596
Yassinetaouil 46:b1a9de66ecab 2597 /* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2598 #define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
Yassinetaouil 46:b1a9de66ecab 2599 #define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
Yassinetaouil 46:b1a9de66ecab 2600 #define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2601 #define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2602
Yassinetaouil 46:b1a9de66ecab 2603 /* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2604 #define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
Yassinetaouil 46:b1a9de66ecab 2605 #define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
Yassinetaouil 46:b1a9de66ecab 2606 #define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2607 #define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2608
Yassinetaouil 46:b1a9de66ecab 2609 /* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2610 #define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
Yassinetaouil 46:b1a9de66ecab 2611 #define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
Yassinetaouil 46:b1a9de66ecab 2612 #define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2613 #define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
Yassinetaouil 46:b1a9de66ecab 2614
Yassinetaouil 46:b1a9de66ecab 2615 /* Register: BPROT_CONFIG1 */
Yassinetaouil 46:b1a9de66ecab 2616 /* Description: Block protect configuration register 1 */
Yassinetaouil 46:b1a9de66ecab 2617
Yassinetaouil 46:b1a9de66ecab 2618 /* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2619 #define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
Yassinetaouil 46:b1a9de66ecab 2620 #define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
Yassinetaouil 46:b1a9de66ecab 2621 #define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2622 #define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2623
Yassinetaouil 46:b1a9de66ecab 2624 /* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2625 #define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
Yassinetaouil 46:b1a9de66ecab 2626 #define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
Yassinetaouil 46:b1a9de66ecab 2627 #define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2628 #define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2629
Yassinetaouil 46:b1a9de66ecab 2630 /* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2631 #define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
Yassinetaouil 46:b1a9de66ecab 2632 #define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
Yassinetaouil 46:b1a9de66ecab 2633 #define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2634 #define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2635
Yassinetaouil 46:b1a9de66ecab 2636 /* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2637 #define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
Yassinetaouil 46:b1a9de66ecab 2638 #define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
Yassinetaouil 46:b1a9de66ecab 2639 #define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2640 #define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2641
Yassinetaouil 46:b1a9de66ecab 2642 /* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2643 #define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
Yassinetaouil 46:b1a9de66ecab 2644 #define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
Yassinetaouil 46:b1a9de66ecab 2645 #define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2646 #define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2647
Yassinetaouil 46:b1a9de66ecab 2648 /* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2649 #define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
Yassinetaouil 46:b1a9de66ecab 2650 #define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
Yassinetaouil 46:b1a9de66ecab 2651 #define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2652 #define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2653
Yassinetaouil 46:b1a9de66ecab 2654 /* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2655 #define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
Yassinetaouil 46:b1a9de66ecab 2656 #define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
Yassinetaouil 46:b1a9de66ecab 2657 #define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2658 #define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2659
Yassinetaouil 46:b1a9de66ecab 2660 /* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2661 #define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
Yassinetaouil 46:b1a9de66ecab 2662 #define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
Yassinetaouil 46:b1a9de66ecab 2663 #define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2664 #define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2665
Yassinetaouil 46:b1a9de66ecab 2666 /* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2667 #define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
Yassinetaouil 46:b1a9de66ecab 2668 #define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
Yassinetaouil 46:b1a9de66ecab 2669 #define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2670 #define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2671
Yassinetaouil 46:b1a9de66ecab 2672 /* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2673 #define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
Yassinetaouil 46:b1a9de66ecab 2674 #define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
Yassinetaouil 46:b1a9de66ecab 2675 #define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2676 #define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2677
Yassinetaouil 46:b1a9de66ecab 2678 /* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2679 #define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
Yassinetaouil 46:b1a9de66ecab 2680 #define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
Yassinetaouil 46:b1a9de66ecab 2681 #define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2682 #define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2683
Yassinetaouil 46:b1a9de66ecab 2684 /* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2685 #define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
Yassinetaouil 46:b1a9de66ecab 2686 #define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
Yassinetaouil 46:b1a9de66ecab 2687 #define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2688 #define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2689
Yassinetaouil 46:b1a9de66ecab 2690 /* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2691 #define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
Yassinetaouil 46:b1a9de66ecab 2692 #define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
Yassinetaouil 46:b1a9de66ecab 2693 #define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2694 #define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2695
Yassinetaouil 46:b1a9de66ecab 2696 /* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2697 #define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
Yassinetaouil 46:b1a9de66ecab 2698 #define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
Yassinetaouil 46:b1a9de66ecab 2699 #define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2700 #define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2701
Yassinetaouil 46:b1a9de66ecab 2702 /* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2703 #define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
Yassinetaouil 46:b1a9de66ecab 2704 #define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
Yassinetaouil 46:b1a9de66ecab 2705 #define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2706 #define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2707
Yassinetaouil 46:b1a9de66ecab 2708 /* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2709 #define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
Yassinetaouil 46:b1a9de66ecab 2710 #define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
Yassinetaouil 46:b1a9de66ecab 2711 #define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2712 #define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2713
Yassinetaouil 46:b1a9de66ecab 2714 /* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2715 #define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
Yassinetaouil 46:b1a9de66ecab 2716 #define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
Yassinetaouil 46:b1a9de66ecab 2717 #define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2718 #define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2719
Yassinetaouil 46:b1a9de66ecab 2720 /* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2721 #define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
Yassinetaouil 46:b1a9de66ecab 2722 #define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
Yassinetaouil 46:b1a9de66ecab 2723 #define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2724 #define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2725
Yassinetaouil 46:b1a9de66ecab 2726 /* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2727 #define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
Yassinetaouil 46:b1a9de66ecab 2728 #define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
Yassinetaouil 46:b1a9de66ecab 2729 #define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2730 #define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2731
Yassinetaouil 46:b1a9de66ecab 2732 /* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2733 #define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
Yassinetaouil 46:b1a9de66ecab 2734 #define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
Yassinetaouil 46:b1a9de66ecab 2735 #define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2736 #define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2737
Yassinetaouil 46:b1a9de66ecab 2738 /* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2739 #define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
Yassinetaouil 46:b1a9de66ecab 2740 #define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
Yassinetaouil 46:b1a9de66ecab 2741 #define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2742 #define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2743
Yassinetaouil 46:b1a9de66ecab 2744 /* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2745 #define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
Yassinetaouil 46:b1a9de66ecab 2746 #define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
Yassinetaouil 46:b1a9de66ecab 2747 #define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2748 #define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2749
Yassinetaouil 46:b1a9de66ecab 2750 /* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2751 #define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
Yassinetaouil 46:b1a9de66ecab 2752 #define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
Yassinetaouil 46:b1a9de66ecab 2753 #define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2754 #define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2755
Yassinetaouil 46:b1a9de66ecab 2756 /* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2757 #define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
Yassinetaouil 46:b1a9de66ecab 2758 #define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
Yassinetaouil 46:b1a9de66ecab 2759 #define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2760 #define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2761
Yassinetaouil 46:b1a9de66ecab 2762 /* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2763 #define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
Yassinetaouil 46:b1a9de66ecab 2764 #define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
Yassinetaouil 46:b1a9de66ecab 2765 #define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2766 #define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2767
Yassinetaouil 46:b1a9de66ecab 2768 /* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2769 #define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
Yassinetaouil 46:b1a9de66ecab 2770 #define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
Yassinetaouil 46:b1a9de66ecab 2771 #define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2772 #define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2773
Yassinetaouil 46:b1a9de66ecab 2774 /* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2775 #define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
Yassinetaouil 46:b1a9de66ecab 2776 #define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
Yassinetaouil 46:b1a9de66ecab 2777 #define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2778 #define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2779
Yassinetaouil 46:b1a9de66ecab 2780 /* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2781 #define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
Yassinetaouil 46:b1a9de66ecab 2782 #define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
Yassinetaouil 46:b1a9de66ecab 2783 #define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2784 #define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2785
Yassinetaouil 46:b1a9de66ecab 2786 /* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2787 #define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
Yassinetaouil 46:b1a9de66ecab 2788 #define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
Yassinetaouil 46:b1a9de66ecab 2789 #define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2790 #define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2791
Yassinetaouil 46:b1a9de66ecab 2792 /* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2793 #define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
Yassinetaouil 46:b1a9de66ecab 2794 #define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
Yassinetaouil 46:b1a9de66ecab 2795 #define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2796 #define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2797
Yassinetaouil 46:b1a9de66ecab 2798 /* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2799 #define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
Yassinetaouil 46:b1a9de66ecab 2800 #define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
Yassinetaouil 46:b1a9de66ecab 2801 #define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2802 #define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2803
Yassinetaouil 46:b1a9de66ecab 2804 /* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2805 #define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
Yassinetaouil 46:b1a9de66ecab 2806 #define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
Yassinetaouil 46:b1a9de66ecab 2807 #define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2808 #define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2809
Yassinetaouil 46:b1a9de66ecab 2810 /* Register: BPROT_DISABLEINDEBUG */
Yassinetaouil 46:b1a9de66ecab 2811 /* Description: Disable protection mechanism in debug interface mode */
Yassinetaouil 46:b1a9de66ecab 2812
Yassinetaouil 46:b1a9de66ecab 2813 /* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
Yassinetaouil 46:b1a9de66ecab 2814 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
Yassinetaouil 46:b1a9de66ecab 2815 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
Yassinetaouil 46:b1a9de66ecab 2816 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
Yassinetaouil 46:b1a9de66ecab 2817 #define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
Yassinetaouil 46:b1a9de66ecab 2818
Yassinetaouil 46:b1a9de66ecab 2819 /* Register: BPROT_CONFIG2 */
Yassinetaouil 46:b1a9de66ecab 2820 /* Description: Block protect configuration register 2 */
Yassinetaouil 46:b1a9de66ecab 2821
Yassinetaouil 46:b1a9de66ecab 2822 /* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2823 #define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
Yassinetaouil 46:b1a9de66ecab 2824 #define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
Yassinetaouil 46:b1a9de66ecab 2825 #define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2826 #define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2827
Yassinetaouil 46:b1a9de66ecab 2828 /* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2829 #define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
Yassinetaouil 46:b1a9de66ecab 2830 #define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
Yassinetaouil 46:b1a9de66ecab 2831 #define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2832 #define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2833
Yassinetaouil 46:b1a9de66ecab 2834 /* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2835 #define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
Yassinetaouil 46:b1a9de66ecab 2836 #define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
Yassinetaouil 46:b1a9de66ecab 2837 #define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2838 #define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2839
Yassinetaouil 46:b1a9de66ecab 2840 /* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2841 #define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
Yassinetaouil 46:b1a9de66ecab 2842 #define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
Yassinetaouil 46:b1a9de66ecab 2843 #define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2844 #define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2845
Yassinetaouil 46:b1a9de66ecab 2846 /* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2847 #define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
Yassinetaouil 46:b1a9de66ecab 2848 #define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
Yassinetaouil 46:b1a9de66ecab 2849 #define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2850 #define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2851
Yassinetaouil 46:b1a9de66ecab 2852 /* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2853 #define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
Yassinetaouil 46:b1a9de66ecab 2854 #define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
Yassinetaouil 46:b1a9de66ecab 2855 #define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2856 #define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2857
Yassinetaouil 46:b1a9de66ecab 2858 /* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2859 #define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
Yassinetaouil 46:b1a9de66ecab 2860 #define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
Yassinetaouil 46:b1a9de66ecab 2861 #define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2862 #define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2863
Yassinetaouil 46:b1a9de66ecab 2864 /* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2865 #define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
Yassinetaouil 46:b1a9de66ecab 2866 #define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
Yassinetaouil 46:b1a9de66ecab 2867 #define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2868 #define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2869
Yassinetaouil 46:b1a9de66ecab 2870 /* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2871 #define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
Yassinetaouil 46:b1a9de66ecab 2872 #define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
Yassinetaouil 46:b1a9de66ecab 2873 #define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2874 #define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2875
Yassinetaouil 46:b1a9de66ecab 2876 /* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2877 #define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
Yassinetaouil 46:b1a9de66ecab 2878 #define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
Yassinetaouil 46:b1a9de66ecab 2879 #define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2880 #define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2881
Yassinetaouil 46:b1a9de66ecab 2882 /* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2883 #define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
Yassinetaouil 46:b1a9de66ecab 2884 #define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
Yassinetaouil 46:b1a9de66ecab 2885 #define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2886 #define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2887
Yassinetaouil 46:b1a9de66ecab 2888 /* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2889 #define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
Yassinetaouil 46:b1a9de66ecab 2890 #define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
Yassinetaouil 46:b1a9de66ecab 2891 #define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2892 #define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2893
Yassinetaouil 46:b1a9de66ecab 2894 /* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2895 #define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
Yassinetaouil 46:b1a9de66ecab 2896 #define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
Yassinetaouil 46:b1a9de66ecab 2897 #define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2898 #define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2899
Yassinetaouil 46:b1a9de66ecab 2900 /* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2901 #define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
Yassinetaouil 46:b1a9de66ecab 2902 #define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
Yassinetaouil 46:b1a9de66ecab 2903 #define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2904 #define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2905
Yassinetaouil 46:b1a9de66ecab 2906 /* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2907 #define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
Yassinetaouil 46:b1a9de66ecab 2908 #define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
Yassinetaouil 46:b1a9de66ecab 2909 #define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2910 #define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2911
Yassinetaouil 46:b1a9de66ecab 2912 /* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2913 #define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
Yassinetaouil 46:b1a9de66ecab 2914 #define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
Yassinetaouil 46:b1a9de66ecab 2915 #define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2916 #define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2917
Yassinetaouil 46:b1a9de66ecab 2918 /* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2919 #define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
Yassinetaouil 46:b1a9de66ecab 2920 #define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
Yassinetaouil 46:b1a9de66ecab 2921 #define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2922 #define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2923
Yassinetaouil 46:b1a9de66ecab 2924 /* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2925 #define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
Yassinetaouil 46:b1a9de66ecab 2926 #define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
Yassinetaouil 46:b1a9de66ecab 2927 #define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2928 #define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2929
Yassinetaouil 46:b1a9de66ecab 2930 /* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2931 #define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
Yassinetaouil 46:b1a9de66ecab 2932 #define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
Yassinetaouil 46:b1a9de66ecab 2933 #define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2934 #define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2935
Yassinetaouil 46:b1a9de66ecab 2936 /* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2937 #define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
Yassinetaouil 46:b1a9de66ecab 2938 #define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
Yassinetaouil 46:b1a9de66ecab 2939 #define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2940 #define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2941
Yassinetaouil 46:b1a9de66ecab 2942 /* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2943 #define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
Yassinetaouil 46:b1a9de66ecab 2944 #define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
Yassinetaouil 46:b1a9de66ecab 2945 #define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2946 #define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2947
Yassinetaouil 46:b1a9de66ecab 2948 /* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2949 #define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
Yassinetaouil 46:b1a9de66ecab 2950 #define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
Yassinetaouil 46:b1a9de66ecab 2951 #define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2952 #define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2953
Yassinetaouil 46:b1a9de66ecab 2954 /* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2955 #define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
Yassinetaouil 46:b1a9de66ecab 2956 #define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
Yassinetaouil 46:b1a9de66ecab 2957 #define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2958 #define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2959
Yassinetaouil 46:b1a9de66ecab 2960 /* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2961 #define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
Yassinetaouil 46:b1a9de66ecab 2962 #define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
Yassinetaouil 46:b1a9de66ecab 2963 #define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2964 #define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2965
Yassinetaouil 46:b1a9de66ecab 2966 /* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2967 #define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
Yassinetaouil 46:b1a9de66ecab 2968 #define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
Yassinetaouil 46:b1a9de66ecab 2969 #define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2970 #define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2971
Yassinetaouil 46:b1a9de66ecab 2972 /* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2973 #define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
Yassinetaouil 46:b1a9de66ecab 2974 #define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
Yassinetaouil 46:b1a9de66ecab 2975 #define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2976 #define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2977
Yassinetaouil 46:b1a9de66ecab 2978 /* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2979 #define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
Yassinetaouil 46:b1a9de66ecab 2980 #define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
Yassinetaouil 46:b1a9de66ecab 2981 #define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2982 #define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2983
Yassinetaouil 46:b1a9de66ecab 2984 /* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2985 #define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
Yassinetaouil 46:b1a9de66ecab 2986 #define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
Yassinetaouil 46:b1a9de66ecab 2987 #define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2988 #define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2989
Yassinetaouil 46:b1a9de66ecab 2990 /* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2991 #define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
Yassinetaouil 46:b1a9de66ecab 2992 #define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
Yassinetaouil 46:b1a9de66ecab 2993 #define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 2994 #define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 2995
Yassinetaouil 46:b1a9de66ecab 2996 /* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 2997 #define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
Yassinetaouil 46:b1a9de66ecab 2998 #define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
Yassinetaouil 46:b1a9de66ecab 2999 #define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3000 #define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3001
Yassinetaouil 46:b1a9de66ecab 3002 /* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3003 #define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
Yassinetaouil 46:b1a9de66ecab 3004 #define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
Yassinetaouil 46:b1a9de66ecab 3005 #define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3006 #define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3007
Yassinetaouil 46:b1a9de66ecab 3008 /* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3009 #define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
Yassinetaouil 46:b1a9de66ecab 3010 #define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
Yassinetaouil 46:b1a9de66ecab 3011 #define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3012 #define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3013
Yassinetaouil 46:b1a9de66ecab 3014 /* Register: BPROT_CONFIG3 */
Yassinetaouil 46:b1a9de66ecab 3015 /* Description: Block protect configuration register 3 */
Yassinetaouil 46:b1a9de66ecab 3016
Yassinetaouil 46:b1a9de66ecab 3017 /* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3018 #define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
Yassinetaouil 46:b1a9de66ecab 3019 #define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
Yassinetaouil 46:b1a9de66ecab 3020 #define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3021 #define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3022
Yassinetaouil 46:b1a9de66ecab 3023 /* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3024 #define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
Yassinetaouil 46:b1a9de66ecab 3025 #define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
Yassinetaouil 46:b1a9de66ecab 3026 #define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3027 #define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3028
Yassinetaouil 46:b1a9de66ecab 3029 /* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3030 #define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
Yassinetaouil 46:b1a9de66ecab 3031 #define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
Yassinetaouil 46:b1a9de66ecab 3032 #define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3033 #define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3034
Yassinetaouil 46:b1a9de66ecab 3035 /* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3036 #define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
Yassinetaouil 46:b1a9de66ecab 3037 #define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
Yassinetaouil 46:b1a9de66ecab 3038 #define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3039 #define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3040
Yassinetaouil 46:b1a9de66ecab 3041 /* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3042 #define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
Yassinetaouil 46:b1a9de66ecab 3043 #define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
Yassinetaouil 46:b1a9de66ecab 3044 #define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3045 #define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3046
Yassinetaouil 46:b1a9de66ecab 3047 /* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3048 #define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
Yassinetaouil 46:b1a9de66ecab 3049 #define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
Yassinetaouil 46:b1a9de66ecab 3050 #define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3051 #define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3052
Yassinetaouil 46:b1a9de66ecab 3053 /* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3054 #define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
Yassinetaouil 46:b1a9de66ecab 3055 #define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
Yassinetaouil 46:b1a9de66ecab 3056 #define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3057 #define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3058
Yassinetaouil 46:b1a9de66ecab 3059 /* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3060 #define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
Yassinetaouil 46:b1a9de66ecab 3061 #define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
Yassinetaouil 46:b1a9de66ecab 3062 #define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3063 #define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3064
Yassinetaouil 46:b1a9de66ecab 3065 /* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3066 #define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
Yassinetaouil 46:b1a9de66ecab 3067 #define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
Yassinetaouil 46:b1a9de66ecab 3068 #define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3069 #define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3070
Yassinetaouil 46:b1a9de66ecab 3071 /* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3072 #define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
Yassinetaouil 46:b1a9de66ecab 3073 #define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
Yassinetaouil 46:b1a9de66ecab 3074 #define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3075 #define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3076
Yassinetaouil 46:b1a9de66ecab 3077 /* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3078 #define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
Yassinetaouil 46:b1a9de66ecab 3079 #define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
Yassinetaouil 46:b1a9de66ecab 3080 #define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3081 #define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3082
Yassinetaouil 46:b1a9de66ecab 3083 /* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3084 #define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
Yassinetaouil 46:b1a9de66ecab 3085 #define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
Yassinetaouil 46:b1a9de66ecab 3086 #define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3087 #define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3088
Yassinetaouil 46:b1a9de66ecab 3089 /* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3090 #define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
Yassinetaouil 46:b1a9de66ecab 3091 #define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
Yassinetaouil 46:b1a9de66ecab 3092 #define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3093 #define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3094
Yassinetaouil 46:b1a9de66ecab 3095 /* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3096 #define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
Yassinetaouil 46:b1a9de66ecab 3097 #define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
Yassinetaouil 46:b1a9de66ecab 3098 #define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3099 #define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3100
Yassinetaouil 46:b1a9de66ecab 3101 /* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3102 #define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
Yassinetaouil 46:b1a9de66ecab 3103 #define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
Yassinetaouil 46:b1a9de66ecab 3104 #define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3105 #define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3106
Yassinetaouil 46:b1a9de66ecab 3107 /* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3108 #define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
Yassinetaouil 46:b1a9de66ecab 3109 #define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
Yassinetaouil 46:b1a9de66ecab 3110 #define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3111 #define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3112
Yassinetaouil 46:b1a9de66ecab 3113 /* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3114 #define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
Yassinetaouil 46:b1a9de66ecab 3115 #define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
Yassinetaouil 46:b1a9de66ecab 3116 #define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3117 #define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3118
Yassinetaouil 46:b1a9de66ecab 3119 /* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3120 #define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
Yassinetaouil 46:b1a9de66ecab 3121 #define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
Yassinetaouil 46:b1a9de66ecab 3122 #define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3123 #define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3124
Yassinetaouil 46:b1a9de66ecab 3125 /* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3126 #define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
Yassinetaouil 46:b1a9de66ecab 3127 #define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
Yassinetaouil 46:b1a9de66ecab 3128 #define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3129 #define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3130
Yassinetaouil 46:b1a9de66ecab 3131 /* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3132 #define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
Yassinetaouil 46:b1a9de66ecab 3133 #define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
Yassinetaouil 46:b1a9de66ecab 3134 #define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3135 #define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3136
Yassinetaouil 46:b1a9de66ecab 3137 /* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3138 #define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
Yassinetaouil 46:b1a9de66ecab 3139 #define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
Yassinetaouil 46:b1a9de66ecab 3140 #define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3141 #define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3142
Yassinetaouil 46:b1a9de66ecab 3143 /* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3144 #define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
Yassinetaouil 46:b1a9de66ecab 3145 #define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
Yassinetaouil 46:b1a9de66ecab 3146 #define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3147 #define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3148
Yassinetaouil 46:b1a9de66ecab 3149 /* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3150 #define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
Yassinetaouil 46:b1a9de66ecab 3151 #define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
Yassinetaouil 46:b1a9de66ecab 3152 #define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3153 #define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3154
Yassinetaouil 46:b1a9de66ecab 3155 /* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3156 #define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
Yassinetaouil 46:b1a9de66ecab 3157 #define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
Yassinetaouil 46:b1a9de66ecab 3158 #define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3159 #define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3160
Yassinetaouil 46:b1a9de66ecab 3161 /* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3162 #define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
Yassinetaouil 46:b1a9de66ecab 3163 #define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
Yassinetaouil 46:b1a9de66ecab 3164 #define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3165 #define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3166
Yassinetaouil 46:b1a9de66ecab 3167 /* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3168 #define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
Yassinetaouil 46:b1a9de66ecab 3169 #define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
Yassinetaouil 46:b1a9de66ecab 3170 #define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3171 #define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3172
Yassinetaouil 46:b1a9de66ecab 3173 /* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3174 #define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
Yassinetaouil 46:b1a9de66ecab 3175 #define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
Yassinetaouil 46:b1a9de66ecab 3176 #define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3177 #define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3178
Yassinetaouil 46:b1a9de66ecab 3179 /* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3180 #define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
Yassinetaouil 46:b1a9de66ecab 3181 #define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
Yassinetaouil 46:b1a9de66ecab 3182 #define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3183 #define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3184
Yassinetaouil 46:b1a9de66ecab 3185 /* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3186 #define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
Yassinetaouil 46:b1a9de66ecab 3187 #define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
Yassinetaouil 46:b1a9de66ecab 3188 #define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3189 #define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3190
Yassinetaouil 46:b1a9de66ecab 3191 /* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3192 #define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
Yassinetaouil 46:b1a9de66ecab 3193 #define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
Yassinetaouil 46:b1a9de66ecab 3194 #define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3195 #define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3196
Yassinetaouil 46:b1a9de66ecab 3197 /* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3198 #define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
Yassinetaouil 46:b1a9de66ecab 3199 #define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
Yassinetaouil 46:b1a9de66ecab 3200 #define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3201 #define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3202
Yassinetaouil 46:b1a9de66ecab 3203 /* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
Yassinetaouil 46:b1a9de66ecab 3204 #define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
Yassinetaouil 46:b1a9de66ecab 3205 #define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
Yassinetaouil 46:b1a9de66ecab 3206 #define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
Yassinetaouil 46:b1a9de66ecab 3207 #define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
Yassinetaouil 46:b1a9de66ecab 3208
Yassinetaouil 46:b1a9de66ecab 3209
Yassinetaouil 46:b1a9de66ecab 3210 /* Peripheral: CCM */
Yassinetaouil 46:b1a9de66ecab 3211 /* Description: AES CCM Mode Encryption */
Yassinetaouil 46:b1a9de66ecab 3212
Yassinetaouil 46:b1a9de66ecab 3213 /* Register: CCM_SHORTS */
Yassinetaouil 46:b1a9de66ecab 3214 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 3215
Yassinetaouil 46:b1a9de66ecab 3216 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
Yassinetaouil 46:b1a9de66ecab 3217 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
Yassinetaouil 46:b1a9de66ecab 3218 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
Yassinetaouil 46:b1a9de66ecab 3219 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 3220 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 3221
Yassinetaouil 46:b1a9de66ecab 3222 /* Register: CCM_INTENSET */
Yassinetaouil 46:b1a9de66ecab 3223 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 3224
Yassinetaouil 46:b1a9de66ecab 3225 /* Bit 2 : Write '1' to Enable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 3226 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 3227 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 3228 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3229 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3230 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3231
Yassinetaouil 46:b1a9de66ecab 3232 /* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
Yassinetaouil 46:b1a9de66ecab 3233 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
Yassinetaouil 46:b1a9de66ecab 3234 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
Yassinetaouil 46:b1a9de66ecab 3235 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3236 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3237 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3238
Yassinetaouil 46:b1a9de66ecab 3239 /* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
Yassinetaouil 46:b1a9de66ecab 3240 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
Yassinetaouil 46:b1a9de66ecab 3241 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
Yassinetaouil 46:b1a9de66ecab 3242 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3243 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3244 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3245
Yassinetaouil 46:b1a9de66ecab 3246 /* Register: CCM_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 3247 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 3248
Yassinetaouil 46:b1a9de66ecab 3249 /* Bit 2 : Write '1' to Disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 3250 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 3251 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 3252 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3253 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3254 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3255
Yassinetaouil 46:b1a9de66ecab 3256 /* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
Yassinetaouil 46:b1a9de66ecab 3257 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
Yassinetaouil 46:b1a9de66ecab 3258 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
Yassinetaouil 46:b1a9de66ecab 3259 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3260 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3261 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3262
Yassinetaouil 46:b1a9de66ecab 3263 /* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
Yassinetaouil 46:b1a9de66ecab 3264 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
Yassinetaouil 46:b1a9de66ecab 3265 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
Yassinetaouil 46:b1a9de66ecab 3266 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3267 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3268 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3269
Yassinetaouil 46:b1a9de66ecab 3270 /* Register: CCM_MICSTATUS */
Yassinetaouil 46:b1a9de66ecab 3271 /* Description: MIC check result */
Yassinetaouil 46:b1a9de66ecab 3272
Yassinetaouil 46:b1a9de66ecab 3273 /* Bit 0 : The result of the MIC check performed during the previous decryption operation */
Yassinetaouil 46:b1a9de66ecab 3274 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
Yassinetaouil 46:b1a9de66ecab 3275 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
Yassinetaouil 46:b1a9de66ecab 3276 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
Yassinetaouil 46:b1a9de66ecab 3277 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
Yassinetaouil 46:b1a9de66ecab 3278
Yassinetaouil 46:b1a9de66ecab 3279 /* Register: CCM_ENABLE */
Yassinetaouil 46:b1a9de66ecab 3280 /* Description: Enable */
Yassinetaouil 46:b1a9de66ecab 3281
Yassinetaouil 46:b1a9de66ecab 3282 /* Bits 1..0 : Enable or disable CCM */
Yassinetaouil 46:b1a9de66ecab 3283 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 3284 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 3285 #define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3286 #define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3287
Yassinetaouil 46:b1a9de66ecab 3288 /* Register: CCM_MODE */
Yassinetaouil 46:b1a9de66ecab 3289 /* Description: Operation mode */
Yassinetaouil 46:b1a9de66ecab 3290
Yassinetaouil 46:b1a9de66ecab 3291 /* Bit 24 : Packet length configuration */
Yassinetaouil 46:b1a9de66ecab 3292 #define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
Yassinetaouil 46:b1a9de66ecab 3293 #define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
Yassinetaouil 46:b1a9de66ecab 3294 #define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
Yassinetaouil 46:b1a9de66ecab 3295 #define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
Yassinetaouil 46:b1a9de66ecab 3296
Yassinetaouil 46:b1a9de66ecab 3297 /* Bit 16 : Data rate that the CCM shall run in synch with */
Yassinetaouil 46:b1a9de66ecab 3298 #define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
Yassinetaouil 46:b1a9de66ecab 3299 #define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
Yassinetaouil 46:b1a9de66ecab 3300 #define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
Yassinetaouil 46:b1a9de66ecab 3301 #define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
Yassinetaouil 46:b1a9de66ecab 3302
Yassinetaouil 46:b1a9de66ecab 3303 /* Bit 0 : The mode of operation to be used */
Yassinetaouil 46:b1a9de66ecab 3304 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Yassinetaouil 46:b1a9de66ecab 3305 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Yassinetaouil 46:b1a9de66ecab 3306 #define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
Yassinetaouil 46:b1a9de66ecab 3307 #define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
Yassinetaouil 46:b1a9de66ecab 3308
Yassinetaouil 46:b1a9de66ecab 3309 /* Register: CCM_CNFPTR */
Yassinetaouil 46:b1a9de66ecab 3310 /* Description: Pointer to data structure holding AES key and NONCE vector */
Yassinetaouil 46:b1a9de66ecab 3311
Yassinetaouil 46:b1a9de66ecab 3312 /* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
Yassinetaouil 46:b1a9de66ecab 3313 #define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
Yassinetaouil 46:b1a9de66ecab 3314 #define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
Yassinetaouil 46:b1a9de66ecab 3315
Yassinetaouil 46:b1a9de66ecab 3316 /* Register: CCM_INPTR */
Yassinetaouil 46:b1a9de66ecab 3317 /* Description: Input pointer */
Yassinetaouil 46:b1a9de66ecab 3318
Yassinetaouil 46:b1a9de66ecab 3319 /* Bits 31..0 : Input pointer */
Yassinetaouil 46:b1a9de66ecab 3320 #define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
Yassinetaouil 46:b1a9de66ecab 3321 #define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
Yassinetaouil 46:b1a9de66ecab 3322
Yassinetaouil 46:b1a9de66ecab 3323 /* Register: CCM_OUTPTR */
Yassinetaouil 46:b1a9de66ecab 3324 /* Description: Output pointer */
Yassinetaouil 46:b1a9de66ecab 3325
Yassinetaouil 46:b1a9de66ecab 3326 /* Bits 31..0 : Output pointer */
Yassinetaouil 46:b1a9de66ecab 3327 #define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
Yassinetaouil 46:b1a9de66ecab 3328 #define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
Yassinetaouil 46:b1a9de66ecab 3329
Yassinetaouil 46:b1a9de66ecab 3330 /* Register: CCM_SCRATCHPTR */
Yassinetaouil 46:b1a9de66ecab 3331 /* Description: Pointer to data area used for temporary storage */
Yassinetaouil 46:b1a9de66ecab 3332
Yassinetaouil 46:b1a9de66ecab 3333 /* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
Yassinetaouil 46:b1a9de66ecab 3334 #define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
Yassinetaouil 46:b1a9de66ecab 3335 #define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
Yassinetaouil 46:b1a9de66ecab 3336
Yassinetaouil 46:b1a9de66ecab 3337
Yassinetaouil 46:b1a9de66ecab 3338 /* Peripheral: CLOCK */
Yassinetaouil 46:b1a9de66ecab 3339 /* Description: Clock control */
Yassinetaouil 46:b1a9de66ecab 3340
Yassinetaouil 46:b1a9de66ecab 3341 /* Register: CLOCK_INTENSET */
Yassinetaouil 46:b1a9de66ecab 3342 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 3343
Yassinetaouil 46:b1a9de66ecab 3344 /* Bit 4 : Write '1' to Enable interrupt for CTTO event */
Yassinetaouil 46:b1a9de66ecab 3345 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
Yassinetaouil 46:b1a9de66ecab 3346 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
Yassinetaouil 46:b1a9de66ecab 3347 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3348 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3349 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3350
Yassinetaouil 46:b1a9de66ecab 3351 /* Bit 3 : Write '1' to Enable interrupt for DONE event */
Yassinetaouil 46:b1a9de66ecab 3352 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
Yassinetaouil 46:b1a9de66ecab 3353 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
Yassinetaouil 46:b1a9de66ecab 3354 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3355 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3356 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3357
Yassinetaouil 46:b1a9de66ecab 3358 /* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
Yassinetaouil 46:b1a9de66ecab 3359 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 3360 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 3361 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3362 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3363 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3364
Yassinetaouil 46:b1a9de66ecab 3365 /* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
Yassinetaouil 46:b1a9de66ecab 3366 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 3367 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 3368 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3369 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3370 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3371
Yassinetaouil 46:b1a9de66ecab 3372 /* Register: CLOCK_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 3373 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 3374
Yassinetaouil 46:b1a9de66ecab 3375 /* Bit 4 : Write '1' to Disable interrupt for CTTO event */
Yassinetaouil 46:b1a9de66ecab 3376 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
Yassinetaouil 46:b1a9de66ecab 3377 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
Yassinetaouil 46:b1a9de66ecab 3378 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3379 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3380 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3381
Yassinetaouil 46:b1a9de66ecab 3382 /* Bit 3 : Write '1' to Disable interrupt for DONE event */
Yassinetaouil 46:b1a9de66ecab 3383 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
Yassinetaouil 46:b1a9de66ecab 3384 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
Yassinetaouil 46:b1a9de66ecab 3385 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3386 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3387 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3388
Yassinetaouil 46:b1a9de66ecab 3389 /* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
Yassinetaouil 46:b1a9de66ecab 3390 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 3391 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 3392 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3393 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3394 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3395
Yassinetaouil 46:b1a9de66ecab 3396 /* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
Yassinetaouil 46:b1a9de66ecab 3397 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 3398 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 3399 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3400 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3401 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3402
Yassinetaouil 46:b1a9de66ecab 3403 /* Register: CLOCK_HFCLKRUN */
Yassinetaouil 46:b1a9de66ecab 3404 /* Description: Status indicating that HFCLKSTART task has been triggered */
Yassinetaouil 46:b1a9de66ecab 3405
Yassinetaouil 46:b1a9de66ecab 3406 /* Bit 0 : HFCLKSTART task triggered or not */
Yassinetaouil 46:b1a9de66ecab 3407 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
Yassinetaouil 46:b1a9de66ecab 3408 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
Yassinetaouil 46:b1a9de66ecab 3409 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
Yassinetaouil 46:b1a9de66ecab 3410 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
Yassinetaouil 46:b1a9de66ecab 3411
Yassinetaouil 46:b1a9de66ecab 3412 /* Register: CLOCK_HFCLKSTAT */
Yassinetaouil 46:b1a9de66ecab 3413 /* Description: HFCLK status */
Yassinetaouil 46:b1a9de66ecab 3414
Yassinetaouil 46:b1a9de66ecab 3415 /* Bit 16 : HFCLK state */
Yassinetaouil 46:b1a9de66ecab 3416 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
Yassinetaouil 46:b1a9de66ecab 3417 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
Yassinetaouil 46:b1a9de66ecab 3418 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
Yassinetaouil 46:b1a9de66ecab 3419 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
Yassinetaouil 46:b1a9de66ecab 3420
Yassinetaouil 46:b1a9de66ecab 3421 /* Bit 0 : Source of HFCLK */
Yassinetaouil 46:b1a9de66ecab 3422 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
Yassinetaouil 46:b1a9de66ecab 3423 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
Yassinetaouil 46:b1a9de66ecab 3424 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
Yassinetaouil 46:b1a9de66ecab 3425 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
Yassinetaouil 46:b1a9de66ecab 3426
Yassinetaouil 46:b1a9de66ecab 3427 /* Register: CLOCK_LFCLKRUN */
Yassinetaouil 46:b1a9de66ecab 3428 /* Description: Status indicating that LFCLKSTART task has been triggered */
Yassinetaouil 46:b1a9de66ecab 3429
Yassinetaouil 46:b1a9de66ecab 3430 /* Bit 0 : LFCLKSTART task triggered or not */
Yassinetaouil 46:b1a9de66ecab 3431 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
Yassinetaouil 46:b1a9de66ecab 3432 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
Yassinetaouil 46:b1a9de66ecab 3433 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
Yassinetaouil 46:b1a9de66ecab 3434 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
Yassinetaouil 46:b1a9de66ecab 3435
Yassinetaouil 46:b1a9de66ecab 3436 /* Register: CLOCK_LFCLKSTAT */
Yassinetaouil 46:b1a9de66ecab 3437 /* Description: LFCLK status */
Yassinetaouil 46:b1a9de66ecab 3438
Yassinetaouil 46:b1a9de66ecab 3439 /* Bit 16 : LFCLK state */
Yassinetaouil 46:b1a9de66ecab 3440 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
Yassinetaouil 46:b1a9de66ecab 3441 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
Yassinetaouil 46:b1a9de66ecab 3442 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
Yassinetaouil 46:b1a9de66ecab 3443 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
Yassinetaouil 46:b1a9de66ecab 3444
Yassinetaouil 46:b1a9de66ecab 3445 /* Bits 1..0 : Source of LFCLK */
Yassinetaouil 46:b1a9de66ecab 3446 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
Yassinetaouil 46:b1a9de66ecab 3447 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
Yassinetaouil 46:b1a9de66ecab 3448 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
Yassinetaouil 46:b1a9de66ecab 3449 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
Yassinetaouil 46:b1a9de66ecab 3450 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
Yassinetaouil 46:b1a9de66ecab 3451
Yassinetaouil 46:b1a9de66ecab 3452 /* Register: CLOCK_LFCLKSRCCOPY */
Yassinetaouil 46:b1a9de66ecab 3453 /* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
Yassinetaouil 46:b1a9de66ecab 3454
Yassinetaouil 46:b1a9de66ecab 3455 /* Bits 1..0 : Clock source */
Yassinetaouil 46:b1a9de66ecab 3456 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
Yassinetaouil 46:b1a9de66ecab 3457 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
Yassinetaouil 46:b1a9de66ecab 3458 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
Yassinetaouil 46:b1a9de66ecab 3459 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
Yassinetaouil 46:b1a9de66ecab 3460 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
Yassinetaouil 46:b1a9de66ecab 3461
Yassinetaouil 46:b1a9de66ecab 3462 /* Register: CLOCK_LFCLKSRC */
Yassinetaouil 46:b1a9de66ecab 3463 /* Description: Clock source for the LFCLK */
Yassinetaouil 46:b1a9de66ecab 3464
Yassinetaouil 46:b1a9de66ecab 3465 /* Bits 1..0 : Clock source */
Yassinetaouil 46:b1a9de66ecab 3466 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
Yassinetaouil 46:b1a9de66ecab 3467 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
Yassinetaouil 46:b1a9de66ecab 3468 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
Yassinetaouil 46:b1a9de66ecab 3469 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
Yassinetaouil 46:b1a9de66ecab 3470 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
Yassinetaouil 46:b1a9de66ecab 3471
Yassinetaouil 46:b1a9de66ecab 3472 /* Register: CLOCK_CTIV */
Yassinetaouil 46:b1a9de66ecab 3473 /* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */
Yassinetaouil 46:b1a9de66ecab 3474
Yassinetaouil 46:b1a9de66ecab 3475 /* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
Yassinetaouil 46:b1a9de66ecab 3476 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
Yassinetaouil 46:b1a9de66ecab 3477 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
Yassinetaouil 46:b1a9de66ecab 3478
Yassinetaouil 46:b1a9de66ecab 3479 /* Register: CLOCK_TRACECONFIG */
Yassinetaouil 46:b1a9de66ecab 3480 /* Description: Clocking options for the Trace Port debug interface */
Yassinetaouil 46:b1a9de66ecab 3481
Yassinetaouil 46:b1a9de66ecab 3482 /* Bits 17..16 : Pin multiplexing of trace signals. */
Yassinetaouil 46:b1a9de66ecab 3483 #define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
Yassinetaouil 46:b1a9de66ecab 3484 #define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
Yassinetaouil 46:b1a9de66ecab 3485 #define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
Yassinetaouil 46:b1a9de66ecab 3486 #define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
Yassinetaouil 46:b1a9de66ecab 3487 #define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
Yassinetaouil 46:b1a9de66ecab 3488
Yassinetaouil 46:b1a9de66ecab 3489 /* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
Yassinetaouil 46:b1a9de66ecab 3490 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
Yassinetaouil 46:b1a9de66ecab 3491 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
Yassinetaouil 46:b1a9de66ecab 3492 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
Yassinetaouil 46:b1a9de66ecab 3493 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
Yassinetaouil 46:b1a9de66ecab 3494 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
Yassinetaouil 46:b1a9de66ecab 3495 #define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
Yassinetaouil 46:b1a9de66ecab 3496
Yassinetaouil 46:b1a9de66ecab 3497
Yassinetaouil 46:b1a9de66ecab 3498 /* Peripheral: COMP */
Yassinetaouil 46:b1a9de66ecab 3499 /* Description: Comparator */
Yassinetaouil 46:b1a9de66ecab 3500
Yassinetaouil 46:b1a9de66ecab 3501 /* Register: COMP_SHORTS */
Yassinetaouil 46:b1a9de66ecab 3502 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 3503
Yassinetaouil 46:b1a9de66ecab 3504 /* Bit 4 : Shortcut between CROSS event and STOP task */
Yassinetaouil 46:b1a9de66ecab 3505 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
Yassinetaouil 46:b1a9de66ecab 3506 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
Yassinetaouil 46:b1a9de66ecab 3507 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 3508 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 3509
Yassinetaouil 46:b1a9de66ecab 3510 /* Bit 3 : Shortcut between UP event and STOP task */
Yassinetaouil 46:b1a9de66ecab 3511 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
Yassinetaouil 46:b1a9de66ecab 3512 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
Yassinetaouil 46:b1a9de66ecab 3513 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 3514 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 3515
Yassinetaouil 46:b1a9de66ecab 3516 /* Bit 2 : Shortcut between DOWN event and STOP task */
Yassinetaouil 46:b1a9de66ecab 3517 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
Yassinetaouil 46:b1a9de66ecab 3518 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
Yassinetaouil 46:b1a9de66ecab 3519 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 3520 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 3521
Yassinetaouil 46:b1a9de66ecab 3522 /* Bit 1 : Shortcut between READY event and STOP task */
Yassinetaouil 46:b1a9de66ecab 3523 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 3524 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 3525 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 3526 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 3527
Yassinetaouil 46:b1a9de66ecab 3528 /* Bit 0 : Shortcut between READY event and SAMPLE task */
Yassinetaouil 46:b1a9de66ecab 3529 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 3530 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 3531 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 3532 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 3533
Yassinetaouil 46:b1a9de66ecab 3534 /* Register: COMP_INTEN */
Yassinetaouil 46:b1a9de66ecab 3535 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 3536
Yassinetaouil 46:b1a9de66ecab 3537 /* Bit 3 : Enable or disable interrupt for CROSS event */
Yassinetaouil 46:b1a9de66ecab 3538 #define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 3539 #define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 3540 #define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3541 #define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3542
Yassinetaouil 46:b1a9de66ecab 3543 /* Bit 2 : Enable or disable interrupt for UP event */
Yassinetaouil 46:b1a9de66ecab 3544 #define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
Yassinetaouil 46:b1a9de66ecab 3545 #define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
Yassinetaouil 46:b1a9de66ecab 3546 #define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3547 #define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3548
Yassinetaouil 46:b1a9de66ecab 3549 /* Bit 1 : Enable or disable interrupt for DOWN event */
Yassinetaouil 46:b1a9de66ecab 3550 #define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 3551 #define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 3552 #define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3553 #define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3554
Yassinetaouil 46:b1a9de66ecab 3555 /* Bit 0 : Enable or disable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 3556 #define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 3557 #define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 3558 #define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3559 #define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3560
Yassinetaouil 46:b1a9de66ecab 3561 /* Register: COMP_INTENSET */
Yassinetaouil 46:b1a9de66ecab 3562 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 3563
Yassinetaouil 46:b1a9de66ecab 3564 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
Yassinetaouil 46:b1a9de66ecab 3565 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 3566 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 3567 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3568 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3569 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3570
Yassinetaouil 46:b1a9de66ecab 3571 /* Bit 2 : Write '1' to Enable interrupt for UP event */
Yassinetaouil 46:b1a9de66ecab 3572 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
Yassinetaouil 46:b1a9de66ecab 3573 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
Yassinetaouil 46:b1a9de66ecab 3574 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3575 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3576 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3577
Yassinetaouil 46:b1a9de66ecab 3578 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
Yassinetaouil 46:b1a9de66ecab 3579 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 3580 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 3581 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3582 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3583 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3584
Yassinetaouil 46:b1a9de66ecab 3585 /* Bit 0 : Write '1' to Enable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 3586 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 3587 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 3588 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3589 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3590 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3591
Yassinetaouil 46:b1a9de66ecab 3592 /* Register: COMP_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 3593 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 3594
Yassinetaouil 46:b1a9de66ecab 3595 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
Yassinetaouil 46:b1a9de66ecab 3596 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 3597 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 3598 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3599 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3600 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3601
Yassinetaouil 46:b1a9de66ecab 3602 /* Bit 2 : Write '1' to Disable interrupt for UP event */
Yassinetaouil 46:b1a9de66ecab 3603 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
Yassinetaouil 46:b1a9de66ecab 3604 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
Yassinetaouil 46:b1a9de66ecab 3605 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3606 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3607 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3608
Yassinetaouil 46:b1a9de66ecab 3609 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
Yassinetaouil 46:b1a9de66ecab 3610 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 3611 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 3612 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3613 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3614 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3615
Yassinetaouil 46:b1a9de66ecab 3616 /* Bit 0 : Write '1' to Disable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 3617 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 3618 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 3619 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3620 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3621 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3622
Yassinetaouil 46:b1a9de66ecab 3623 /* Register: COMP_RESULT */
Yassinetaouil 46:b1a9de66ecab 3624 /* Description: Compare result */
Yassinetaouil 46:b1a9de66ecab 3625
Yassinetaouil 46:b1a9de66ecab 3626 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
Yassinetaouil 46:b1a9de66ecab 3627 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
Yassinetaouil 46:b1a9de66ecab 3628 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
Yassinetaouil 46:b1a9de66ecab 3629 #define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
Yassinetaouil 46:b1a9de66ecab 3630 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
Yassinetaouil 46:b1a9de66ecab 3631
Yassinetaouil 46:b1a9de66ecab 3632 /* Register: COMP_ENABLE */
Yassinetaouil 46:b1a9de66ecab 3633 /* Description: COMP enable */
Yassinetaouil 46:b1a9de66ecab 3634
Yassinetaouil 46:b1a9de66ecab 3635 /* Bits 1..0 : Enable or disable COMP */
Yassinetaouil 46:b1a9de66ecab 3636 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 3637 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 3638 #define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3639 #define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3640
Yassinetaouil 46:b1a9de66ecab 3641 /* Register: COMP_PSEL */
Yassinetaouil 46:b1a9de66ecab 3642 /* Description: Pin select */
Yassinetaouil 46:b1a9de66ecab 3643
Yassinetaouil 46:b1a9de66ecab 3644 /* Bits 2..0 : Analog pin select */
Yassinetaouil 46:b1a9de66ecab 3645 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
Yassinetaouil 46:b1a9de66ecab 3646 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
Yassinetaouil 46:b1a9de66ecab 3647 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 3648 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 3649 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 3650 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 3651 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 3652 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 3653 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 3654 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 3655
Yassinetaouil 46:b1a9de66ecab 3656 /* Register: COMP_REFSEL */
Yassinetaouil 46:b1a9de66ecab 3657 /* Description: Reference source select */
Yassinetaouil 46:b1a9de66ecab 3658
Yassinetaouil 46:b1a9de66ecab 3659 /* Bits 2..0 : Reference select */
Yassinetaouil 46:b1a9de66ecab 3660 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
Yassinetaouil 46:b1a9de66ecab 3661 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
Yassinetaouil 46:b1a9de66ecab 3662 #define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
Yassinetaouil 46:b1a9de66ecab 3663 #define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
Yassinetaouil 46:b1a9de66ecab 3664 #define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
Yassinetaouil 46:b1a9de66ecab 3665 #define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
Yassinetaouil 46:b1a9de66ecab 3666 #define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
Yassinetaouil 46:b1a9de66ecab 3667
Yassinetaouil 46:b1a9de66ecab 3668 /* Register: COMP_EXTREFSEL */
Yassinetaouil 46:b1a9de66ecab 3669 /* Description: External reference select */
Yassinetaouil 46:b1a9de66ecab 3670
Yassinetaouil 46:b1a9de66ecab 3671 /* Bit 0 : External analog reference select */
Yassinetaouil 46:b1a9de66ecab 3672 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
Yassinetaouil 46:b1a9de66ecab 3673 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
Yassinetaouil 46:b1a9de66ecab 3674 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
Yassinetaouil 46:b1a9de66ecab 3675 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
Yassinetaouil 46:b1a9de66ecab 3676
Yassinetaouil 46:b1a9de66ecab 3677 /* Register: COMP_TH */
Yassinetaouil 46:b1a9de66ecab 3678 /* Description: Threshold configuration for hysteresis unit */
Yassinetaouil 46:b1a9de66ecab 3679
Yassinetaouil 46:b1a9de66ecab 3680 /* Bits 13..8 : VUP = (THUP+1)/64*VREF */
Yassinetaouil 46:b1a9de66ecab 3681 #define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
Yassinetaouil 46:b1a9de66ecab 3682 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
Yassinetaouil 46:b1a9de66ecab 3683
Yassinetaouil 46:b1a9de66ecab 3684 /* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
Yassinetaouil 46:b1a9de66ecab 3685 #define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
Yassinetaouil 46:b1a9de66ecab 3686 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
Yassinetaouil 46:b1a9de66ecab 3687
Yassinetaouil 46:b1a9de66ecab 3688 /* Register: COMP_MODE */
Yassinetaouil 46:b1a9de66ecab 3689 /* Description: Mode configuration */
Yassinetaouil 46:b1a9de66ecab 3690
Yassinetaouil 46:b1a9de66ecab 3691 /* Bit 8 : Main operation mode */
Yassinetaouil 46:b1a9de66ecab 3692 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
Yassinetaouil 46:b1a9de66ecab 3693 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
Yassinetaouil 46:b1a9de66ecab 3694 #define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
Yassinetaouil 46:b1a9de66ecab 3695 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
Yassinetaouil 46:b1a9de66ecab 3696
Yassinetaouil 46:b1a9de66ecab 3697 /* Bits 1..0 : Speed and power mode */
Yassinetaouil 46:b1a9de66ecab 3698 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
Yassinetaouil 46:b1a9de66ecab 3699 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
Yassinetaouil 46:b1a9de66ecab 3700 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
Yassinetaouil 46:b1a9de66ecab 3701 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
Yassinetaouil 46:b1a9de66ecab 3702 #define COMP_MODE_SP_High (2UL) /*!< High speed mode */
Yassinetaouil 46:b1a9de66ecab 3703
Yassinetaouil 46:b1a9de66ecab 3704 /* Register: COMP_HYST */
Yassinetaouil 46:b1a9de66ecab 3705 /* Description: Comparator hysteresis enable */
Yassinetaouil 46:b1a9de66ecab 3706
Yassinetaouil 46:b1a9de66ecab 3707 /* Bit 0 : Comparator hysteresis */
Yassinetaouil 46:b1a9de66ecab 3708 #define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
Yassinetaouil 46:b1a9de66ecab 3709 #define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
Yassinetaouil 46:b1a9de66ecab 3710 #define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
Yassinetaouil 46:b1a9de66ecab 3711 #define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
Yassinetaouil 46:b1a9de66ecab 3712
Yassinetaouil 46:b1a9de66ecab 3713 /* Register: COMP_ISOURCE */
Yassinetaouil 46:b1a9de66ecab 3714 /* Description: Current source select on analog input */
Yassinetaouil 46:b1a9de66ecab 3715
Yassinetaouil 46:b1a9de66ecab 3716 /* Bits 1..0 : Comparator hysteresis */
Yassinetaouil 46:b1a9de66ecab 3717 #define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
Yassinetaouil 46:b1a9de66ecab 3718 #define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
Yassinetaouil 46:b1a9de66ecab 3719 #define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
Yassinetaouil 46:b1a9de66ecab 3720 #define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
Yassinetaouil 46:b1a9de66ecab 3721 #define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
Yassinetaouil 46:b1a9de66ecab 3722 #define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
Yassinetaouil 46:b1a9de66ecab 3723
Yassinetaouil 46:b1a9de66ecab 3724
Yassinetaouil 46:b1a9de66ecab 3725 /* Peripheral: ECB */
Yassinetaouil 46:b1a9de66ecab 3726 /* Description: AES ECB Mode Encryption */
Yassinetaouil 46:b1a9de66ecab 3727
Yassinetaouil 46:b1a9de66ecab 3728 /* Register: ECB_INTENSET */
Yassinetaouil 46:b1a9de66ecab 3729 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 3730
Yassinetaouil 46:b1a9de66ecab 3731 /* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
Yassinetaouil 46:b1a9de66ecab 3732 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
Yassinetaouil 46:b1a9de66ecab 3733 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
Yassinetaouil 46:b1a9de66ecab 3734 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3735 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3736 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3737
Yassinetaouil 46:b1a9de66ecab 3738 /* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
Yassinetaouil 46:b1a9de66ecab 3739 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
Yassinetaouil 46:b1a9de66ecab 3740 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
Yassinetaouil 46:b1a9de66ecab 3741 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3742 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3743 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3744
Yassinetaouil 46:b1a9de66ecab 3745 /* Register: ECB_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 3746 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 3747
Yassinetaouil 46:b1a9de66ecab 3748 /* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
Yassinetaouil 46:b1a9de66ecab 3749 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
Yassinetaouil 46:b1a9de66ecab 3750 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
Yassinetaouil 46:b1a9de66ecab 3751 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3752 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3753 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3754
Yassinetaouil 46:b1a9de66ecab 3755 /* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
Yassinetaouil 46:b1a9de66ecab 3756 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
Yassinetaouil 46:b1a9de66ecab 3757 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
Yassinetaouil 46:b1a9de66ecab 3758 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3759 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3760 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3761
Yassinetaouil 46:b1a9de66ecab 3762 /* Register: ECB_ECBDATAPTR */
Yassinetaouil 46:b1a9de66ecab 3763 /* Description: ECB block encrypt memory pointers */
Yassinetaouil 46:b1a9de66ecab 3764
Yassinetaouil 46:b1a9de66ecab 3765 /* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
Yassinetaouil 46:b1a9de66ecab 3766 #define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
Yassinetaouil 46:b1a9de66ecab 3767 #define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
Yassinetaouil 46:b1a9de66ecab 3768
Yassinetaouil 46:b1a9de66ecab 3769
Yassinetaouil 46:b1a9de66ecab 3770 /* Peripheral: EGU */
Yassinetaouil 46:b1a9de66ecab 3771 /* Description: Event Generator Unit 0 */
Yassinetaouil 46:b1a9de66ecab 3772
Yassinetaouil 46:b1a9de66ecab 3773 /* Register: EGU_INTEN */
Yassinetaouil 46:b1a9de66ecab 3774 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 3775
Yassinetaouil 46:b1a9de66ecab 3776 /* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
Yassinetaouil 46:b1a9de66ecab 3777 #define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
Yassinetaouil 46:b1a9de66ecab 3778 #define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
Yassinetaouil 46:b1a9de66ecab 3779 #define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3780 #define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3781
Yassinetaouil 46:b1a9de66ecab 3782 /* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
Yassinetaouil 46:b1a9de66ecab 3783 #define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
Yassinetaouil 46:b1a9de66ecab 3784 #define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
Yassinetaouil 46:b1a9de66ecab 3785 #define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3786 #define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3787
Yassinetaouil 46:b1a9de66ecab 3788 /* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
Yassinetaouil 46:b1a9de66ecab 3789 #define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
Yassinetaouil 46:b1a9de66ecab 3790 #define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
Yassinetaouil 46:b1a9de66ecab 3791 #define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3792 #define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3793
Yassinetaouil 46:b1a9de66ecab 3794 /* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
Yassinetaouil 46:b1a9de66ecab 3795 #define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
Yassinetaouil 46:b1a9de66ecab 3796 #define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
Yassinetaouil 46:b1a9de66ecab 3797 #define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3798 #define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3799
Yassinetaouil 46:b1a9de66ecab 3800 /* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
Yassinetaouil 46:b1a9de66ecab 3801 #define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
Yassinetaouil 46:b1a9de66ecab 3802 #define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
Yassinetaouil 46:b1a9de66ecab 3803 #define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3804 #define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3805
Yassinetaouil 46:b1a9de66ecab 3806 /* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
Yassinetaouil 46:b1a9de66ecab 3807 #define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
Yassinetaouil 46:b1a9de66ecab 3808 #define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
Yassinetaouil 46:b1a9de66ecab 3809 #define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3810 #define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3811
Yassinetaouil 46:b1a9de66ecab 3812 /* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
Yassinetaouil 46:b1a9de66ecab 3813 #define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
Yassinetaouil 46:b1a9de66ecab 3814 #define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
Yassinetaouil 46:b1a9de66ecab 3815 #define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3816 #define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3817
Yassinetaouil 46:b1a9de66ecab 3818 /* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
Yassinetaouil 46:b1a9de66ecab 3819 #define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
Yassinetaouil 46:b1a9de66ecab 3820 #define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
Yassinetaouil 46:b1a9de66ecab 3821 #define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3822 #define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3823
Yassinetaouil 46:b1a9de66ecab 3824 /* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
Yassinetaouil 46:b1a9de66ecab 3825 #define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
Yassinetaouil 46:b1a9de66ecab 3826 #define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
Yassinetaouil 46:b1a9de66ecab 3827 #define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3828 #define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3829
Yassinetaouil 46:b1a9de66ecab 3830 /* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
Yassinetaouil 46:b1a9de66ecab 3831 #define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
Yassinetaouil 46:b1a9de66ecab 3832 #define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
Yassinetaouil 46:b1a9de66ecab 3833 #define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3834 #define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3835
Yassinetaouil 46:b1a9de66ecab 3836 /* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
Yassinetaouil 46:b1a9de66ecab 3837 #define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
Yassinetaouil 46:b1a9de66ecab 3838 #define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
Yassinetaouil 46:b1a9de66ecab 3839 #define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3840 #define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3841
Yassinetaouil 46:b1a9de66ecab 3842 /* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
Yassinetaouil 46:b1a9de66ecab 3843 #define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
Yassinetaouil 46:b1a9de66ecab 3844 #define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
Yassinetaouil 46:b1a9de66ecab 3845 #define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3846 #define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3847
Yassinetaouil 46:b1a9de66ecab 3848 /* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
Yassinetaouil 46:b1a9de66ecab 3849 #define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
Yassinetaouil 46:b1a9de66ecab 3850 #define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
Yassinetaouil 46:b1a9de66ecab 3851 #define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3852 #define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3853
Yassinetaouil 46:b1a9de66ecab 3854 /* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
Yassinetaouil 46:b1a9de66ecab 3855 #define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
Yassinetaouil 46:b1a9de66ecab 3856 #define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
Yassinetaouil 46:b1a9de66ecab 3857 #define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3858 #define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3859
Yassinetaouil 46:b1a9de66ecab 3860 /* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
Yassinetaouil 46:b1a9de66ecab 3861 #define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
Yassinetaouil 46:b1a9de66ecab 3862 #define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
Yassinetaouil 46:b1a9de66ecab 3863 #define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3864 #define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3865
Yassinetaouil 46:b1a9de66ecab 3866 /* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
Yassinetaouil 46:b1a9de66ecab 3867 #define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
Yassinetaouil 46:b1a9de66ecab 3868 #define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
Yassinetaouil 46:b1a9de66ecab 3869 #define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3870 #define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3871
Yassinetaouil 46:b1a9de66ecab 3872 /* Register: EGU_INTENSET */
Yassinetaouil 46:b1a9de66ecab 3873 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 3874
Yassinetaouil 46:b1a9de66ecab 3875 /* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
Yassinetaouil 46:b1a9de66ecab 3876 #define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
Yassinetaouil 46:b1a9de66ecab 3877 #define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
Yassinetaouil 46:b1a9de66ecab 3878 #define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3879 #define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3880 #define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3881
Yassinetaouil 46:b1a9de66ecab 3882 /* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
Yassinetaouil 46:b1a9de66ecab 3883 #define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
Yassinetaouil 46:b1a9de66ecab 3884 #define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
Yassinetaouil 46:b1a9de66ecab 3885 #define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3886 #define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3887 #define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3888
Yassinetaouil 46:b1a9de66ecab 3889 /* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
Yassinetaouil 46:b1a9de66ecab 3890 #define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
Yassinetaouil 46:b1a9de66ecab 3891 #define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
Yassinetaouil 46:b1a9de66ecab 3892 #define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3893 #define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3894 #define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3895
Yassinetaouil 46:b1a9de66ecab 3896 /* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
Yassinetaouil 46:b1a9de66ecab 3897 #define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
Yassinetaouil 46:b1a9de66ecab 3898 #define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
Yassinetaouil 46:b1a9de66ecab 3899 #define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3900 #define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3901 #define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3902
Yassinetaouil 46:b1a9de66ecab 3903 /* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
Yassinetaouil 46:b1a9de66ecab 3904 #define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
Yassinetaouil 46:b1a9de66ecab 3905 #define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
Yassinetaouil 46:b1a9de66ecab 3906 #define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3907 #define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3908 #define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3909
Yassinetaouil 46:b1a9de66ecab 3910 /* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
Yassinetaouil 46:b1a9de66ecab 3911 #define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
Yassinetaouil 46:b1a9de66ecab 3912 #define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
Yassinetaouil 46:b1a9de66ecab 3913 #define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3914 #define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3915 #define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3916
Yassinetaouil 46:b1a9de66ecab 3917 /* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
Yassinetaouil 46:b1a9de66ecab 3918 #define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
Yassinetaouil 46:b1a9de66ecab 3919 #define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
Yassinetaouil 46:b1a9de66ecab 3920 #define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3921 #define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3922 #define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3923
Yassinetaouil 46:b1a9de66ecab 3924 /* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
Yassinetaouil 46:b1a9de66ecab 3925 #define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
Yassinetaouil 46:b1a9de66ecab 3926 #define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
Yassinetaouil 46:b1a9de66ecab 3927 #define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3928 #define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3929 #define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3930
Yassinetaouil 46:b1a9de66ecab 3931 /* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
Yassinetaouil 46:b1a9de66ecab 3932 #define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
Yassinetaouil 46:b1a9de66ecab 3933 #define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
Yassinetaouil 46:b1a9de66ecab 3934 #define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3935 #define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3936 #define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3937
Yassinetaouil 46:b1a9de66ecab 3938 /* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
Yassinetaouil 46:b1a9de66ecab 3939 #define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
Yassinetaouil 46:b1a9de66ecab 3940 #define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
Yassinetaouil 46:b1a9de66ecab 3941 #define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3942 #define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3943 #define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3944
Yassinetaouil 46:b1a9de66ecab 3945 /* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
Yassinetaouil 46:b1a9de66ecab 3946 #define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
Yassinetaouil 46:b1a9de66ecab 3947 #define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
Yassinetaouil 46:b1a9de66ecab 3948 #define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3949 #define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3950 #define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3951
Yassinetaouil 46:b1a9de66ecab 3952 /* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
Yassinetaouil 46:b1a9de66ecab 3953 #define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
Yassinetaouil 46:b1a9de66ecab 3954 #define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
Yassinetaouil 46:b1a9de66ecab 3955 #define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3956 #define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3957 #define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3958
Yassinetaouil 46:b1a9de66ecab 3959 /* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
Yassinetaouil 46:b1a9de66ecab 3960 #define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
Yassinetaouil 46:b1a9de66ecab 3961 #define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
Yassinetaouil 46:b1a9de66ecab 3962 #define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3963 #define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3964 #define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3965
Yassinetaouil 46:b1a9de66ecab 3966 /* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
Yassinetaouil 46:b1a9de66ecab 3967 #define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
Yassinetaouil 46:b1a9de66ecab 3968 #define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
Yassinetaouil 46:b1a9de66ecab 3969 #define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3970 #define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3971 #define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3972
Yassinetaouil 46:b1a9de66ecab 3973 /* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
Yassinetaouil 46:b1a9de66ecab 3974 #define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
Yassinetaouil 46:b1a9de66ecab 3975 #define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
Yassinetaouil 46:b1a9de66ecab 3976 #define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3977 #define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3978 #define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3979
Yassinetaouil 46:b1a9de66ecab 3980 /* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
Yassinetaouil 46:b1a9de66ecab 3981 #define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
Yassinetaouil 46:b1a9de66ecab 3982 #define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
Yassinetaouil 46:b1a9de66ecab 3983 #define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3984 #define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3985 #define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 3986
Yassinetaouil 46:b1a9de66ecab 3987 /* Register: EGU_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 3988 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 3989
Yassinetaouil 46:b1a9de66ecab 3990 /* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
Yassinetaouil 46:b1a9de66ecab 3991 #define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
Yassinetaouil 46:b1a9de66ecab 3992 #define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
Yassinetaouil 46:b1a9de66ecab 3993 #define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 3994 #define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 3995 #define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 3996
Yassinetaouil 46:b1a9de66ecab 3997 /* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
Yassinetaouil 46:b1a9de66ecab 3998 #define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
Yassinetaouil 46:b1a9de66ecab 3999 #define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
Yassinetaouil 46:b1a9de66ecab 4000 #define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4001 #define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4002 #define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4003
Yassinetaouil 46:b1a9de66ecab 4004 /* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
Yassinetaouil 46:b1a9de66ecab 4005 #define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
Yassinetaouil 46:b1a9de66ecab 4006 #define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
Yassinetaouil 46:b1a9de66ecab 4007 #define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4008 #define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4009 #define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4010
Yassinetaouil 46:b1a9de66ecab 4011 /* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
Yassinetaouil 46:b1a9de66ecab 4012 #define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
Yassinetaouil 46:b1a9de66ecab 4013 #define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
Yassinetaouil 46:b1a9de66ecab 4014 #define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4015 #define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4016 #define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4017
Yassinetaouil 46:b1a9de66ecab 4018 /* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
Yassinetaouil 46:b1a9de66ecab 4019 #define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
Yassinetaouil 46:b1a9de66ecab 4020 #define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
Yassinetaouil 46:b1a9de66ecab 4021 #define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4022 #define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4023 #define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4024
Yassinetaouil 46:b1a9de66ecab 4025 /* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
Yassinetaouil 46:b1a9de66ecab 4026 #define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
Yassinetaouil 46:b1a9de66ecab 4027 #define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
Yassinetaouil 46:b1a9de66ecab 4028 #define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4029 #define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4030 #define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4031
Yassinetaouil 46:b1a9de66ecab 4032 /* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
Yassinetaouil 46:b1a9de66ecab 4033 #define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
Yassinetaouil 46:b1a9de66ecab 4034 #define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
Yassinetaouil 46:b1a9de66ecab 4035 #define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4036 #define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4037 #define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4038
Yassinetaouil 46:b1a9de66ecab 4039 /* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
Yassinetaouil 46:b1a9de66ecab 4040 #define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
Yassinetaouil 46:b1a9de66ecab 4041 #define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
Yassinetaouil 46:b1a9de66ecab 4042 #define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4043 #define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4044 #define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4045
Yassinetaouil 46:b1a9de66ecab 4046 /* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
Yassinetaouil 46:b1a9de66ecab 4047 #define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
Yassinetaouil 46:b1a9de66ecab 4048 #define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
Yassinetaouil 46:b1a9de66ecab 4049 #define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4050 #define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4051 #define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4052
Yassinetaouil 46:b1a9de66ecab 4053 /* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
Yassinetaouil 46:b1a9de66ecab 4054 #define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
Yassinetaouil 46:b1a9de66ecab 4055 #define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
Yassinetaouil 46:b1a9de66ecab 4056 #define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4057 #define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4058 #define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4059
Yassinetaouil 46:b1a9de66ecab 4060 /* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
Yassinetaouil 46:b1a9de66ecab 4061 #define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
Yassinetaouil 46:b1a9de66ecab 4062 #define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
Yassinetaouil 46:b1a9de66ecab 4063 #define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4064 #define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4065 #define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4066
Yassinetaouil 46:b1a9de66ecab 4067 /* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
Yassinetaouil 46:b1a9de66ecab 4068 #define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
Yassinetaouil 46:b1a9de66ecab 4069 #define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
Yassinetaouil 46:b1a9de66ecab 4070 #define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4071 #define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4072 #define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4073
Yassinetaouil 46:b1a9de66ecab 4074 /* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
Yassinetaouil 46:b1a9de66ecab 4075 #define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
Yassinetaouil 46:b1a9de66ecab 4076 #define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
Yassinetaouil 46:b1a9de66ecab 4077 #define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4078 #define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4079 #define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4080
Yassinetaouil 46:b1a9de66ecab 4081 /* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
Yassinetaouil 46:b1a9de66ecab 4082 #define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
Yassinetaouil 46:b1a9de66ecab 4083 #define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
Yassinetaouil 46:b1a9de66ecab 4084 #define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4085 #define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4086 #define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4087
Yassinetaouil 46:b1a9de66ecab 4088 /* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
Yassinetaouil 46:b1a9de66ecab 4089 #define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
Yassinetaouil 46:b1a9de66ecab 4090 #define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
Yassinetaouil 46:b1a9de66ecab 4091 #define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4092 #define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4093 #define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4094
Yassinetaouil 46:b1a9de66ecab 4095 /* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
Yassinetaouil 46:b1a9de66ecab 4096 #define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
Yassinetaouil 46:b1a9de66ecab 4097 #define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
Yassinetaouil 46:b1a9de66ecab 4098 #define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4099 #define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4100 #define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4101
Yassinetaouil 46:b1a9de66ecab 4102
Yassinetaouil 46:b1a9de66ecab 4103 /* Peripheral: FICR */
Yassinetaouil 46:b1a9de66ecab 4104 /* Description: Factory Information Configuration Registers */
Yassinetaouil 46:b1a9de66ecab 4105
Yassinetaouil 46:b1a9de66ecab 4106 /* Register: FICR_CODEPAGESIZE */
Yassinetaouil 46:b1a9de66ecab 4107 /* Description: Code memory page size */
Yassinetaouil 46:b1a9de66ecab 4108
Yassinetaouil 46:b1a9de66ecab 4109 /* Bits 31..0 : Code memory page size */
Yassinetaouil 46:b1a9de66ecab 4110 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
Yassinetaouil 46:b1a9de66ecab 4111 #define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
Yassinetaouil 46:b1a9de66ecab 4112
Yassinetaouil 46:b1a9de66ecab 4113 /* Register: FICR_CODESIZE */
Yassinetaouil 46:b1a9de66ecab 4114 /* Description: Code memory size */
Yassinetaouil 46:b1a9de66ecab 4115
Yassinetaouil 46:b1a9de66ecab 4116 /* Bits 31..0 : Code memory size in number of pages */
Yassinetaouil 46:b1a9de66ecab 4117 #define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
Yassinetaouil 46:b1a9de66ecab 4118 #define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
Yassinetaouil 46:b1a9de66ecab 4119
Yassinetaouil 46:b1a9de66ecab 4120 /* Register: FICR_DEVICEID */
Yassinetaouil 46:b1a9de66ecab 4121 /* Description: Description collection[0]: Device identifier */
Yassinetaouil 46:b1a9de66ecab 4122
Yassinetaouil 46:b1a9de66ecab 4123 /* Bits 31..0 : 64 bit unique device identifier */
Yassinetaouil 46:b1a9de66ecab 4124 #define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
Yassinetaouil 46:b1a9de66ecab 4125 #define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
Yassinetaouil 46:b1a9de66ecab 4126
Yassinetaouil 46:b1a9de66ecab 4127 /* Register: FICR_ER */
Yassinetaouil 46:b1a9de66ecab 4128 /* Description: Description collection[0]: Encryption Root, word 0 */
Yassinetaouil 46:b1a9de66ecab 4129
Yassinetaouil 46:b1a9de66ecab 4130 /* Bits 31..0 : Encryption Root, word n */
Yassinetaouil 46:b1a9de66ecab 4131 #define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
Yassinetaouil 46:b1a9de66ecab 4132 #define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
Yassinetaouil 46:b1a9de66ecab 4133
Yassinetaouil 46:b1a9de66ecab 4134 /* Register: FICR_IR */
Yassinetaouil 46:b1a9de66ecab 4135 /* Description: Description collection[0]: Identity Root, word 0 */
Yassinetaouil 46:b1a9de66ecab 4136
Yassinetaouil 46:b1a9de66ecab 4137 /* Bits 31..0 : Identity Root, word n */
Yassinetaouil 46:b1a9de66ecab 4138 #define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
Yassinetaouil 46:b1a9de66ecab 4139 #define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
Yassinetaouil 46:b1a9de66ecab 4140
Yassinetaouil 46:b1a9de66ecab 4141 /* Register: FICR_DEVICEADDRTYPE */
Yassinetaouil 46:b1a9de66ecab 4142 /* Description: Device address type */
Yassinetaouil 46:b1a9de66ecab 4143
Yassinetaouil 46:b1a9de66ecab 4144 /* Bit 0 : Device address type */
Yassinetaouil 46:b1a9de66ecab 4145 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
Yassinetaouil 46:b1a9de66ecab 4146 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
Yassinetaouil 46:b1a9de66ecab 4147 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
Yassinetaouil 46:b1a9de66ecab 4148 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
Yassinetaouil 46:b1a9de66ecab 4149
Yassinetaouil 46:b1a9de66ecab 4150 /* Register: FICR_DEVICEADDR */
Yassinetaouil 46:b1a9de66ecab 4151 /* Description: Description collection[0]: Device address 0 */
Yassinetaouil 46:b1a9de66ecab 4152
Yassinetaouil 46:b1a9de66ecab 4153 /* Bits 31..0 : 48 bit device address */
Yassinetaouil 46:b1a9de66ecab 4154 #define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
Yassinetaouil 46:b1a9de66ecab 4155 #define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
Yassinetaouil 46:b1a9de66ecab 4156
Yassinetaouil 46:b1a9de66ecab 4157 /* Register: FICR_INFO_PART */
Yassinetaouil 46:b1a9de66ecab 4158 /* Description: Part code */
Yassinetaouil 46:b1a9de66ecab 4159
Yassinetaouil 46:b1a9de66ecab 4160 /* Bits 31..0 : Part code */
Yassinetaouil 46:b1a9de66ecab 4161 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
Yassinetaouil 46:b1a9de66ecab 4162 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
Yassinetaouil 46:b1a9de66ecab 4163 #define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
Yassinetaouil 46:b1a9de66ecab 4164 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Yassinetaouil 46:b1a9de66ecab 4165
Yassinetaouil 46:b1a9de66ecab 4166 /* Register: FICR_INFO_VARIANT */
Yassinetaouil 46:b1a9de66ecab 4167 /* Description: Part Variant, Hardware version and Production configuration */
Yassinetaouil 46:b1a9de66ecab 4168
Yassinetaouil 46:b1a9de66ecab 4169 /* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
Yassinetaouil 46:b1a9de66ecab 4170 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
Yassinetaouil 46:b1a9de66ecab 4171 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
Yassinetaouil 46:b1a9de66ecab 4172 #define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
Yassinetaouil 46:b1a9de66ecab 4173 #define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
Yassinetaouil 46:b1a9de66ecab 4174 #define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
Yassinetaouil 46:b1a9de66ecab 4175 #define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
Yassinetaouil 46:b1a9de66ecab 4176 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Yassinetaouil 46:b1a9de66ecab 4177
Yassinetaouil 46:b1a9de66ecab 4178 /* Register: FICR_INFO_PACKAGE */
Yassinetaouil 46:b1a9de66ecab 4179 /* Description: Package option */
Yassinetaouil 46:b1a9de66ecab 4180
Yassinetaouil 46:b1a9de66ecab 4181 /* Bits 31..0 : Package option */
Yassinetaouil 46:b1a9de66ecab 4182 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
Yassinetaouil 46:b1a9de66ecab 4183 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
Yassinetaouil 46:b1a9de66ecab 4184 #define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
Yassinetaouil 46:b1a9de66ecab 4185 #define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
Yassinetaouil 46:b1a9de66ecab 4186 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Yassinetaouil 46:b1a9de66ecab 4187
Yassinetaouil 46:b1a9de66ecab 4188 /* Register: FICR_INFO_RAM */
Yassinetaouil 46:b1a9de66ecab 4189 /* Description: RAM variant */
Yassinetaouil 46:b1a9de66ecab 4190
Yassinetaouil 46:b1a9de66ecab 4191 /* Bits 31..0 : RAM variant */
Yassinetaouil 46:b1a9de66ecab 4192 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
Yassinetaouil 46:b1a9de66ecab 4193 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
Yassinetaouil 46:b1a9de66ecab 4194 #define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
Yassinetaouil 46:b1a9de66ecab 4195 #define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
Yassinetaouil 46:b1a9de66ecab 4196 #define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
Yassinetaouil 46:b1a9de66ecab 4197 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Yassinetaouil 46:b1a9de66ecab 4198
Yassinetaouil 46:b1a9de66ecab 4199 /* Register: FICR_INFO_FLASH */
Yassinetaouil 46:b1a9de66ecab 4200 /* Description: Flash variant */
Yassinetaouil 46:b1a9de66ecab 4201
Yassinetaouil 46:b1a9de66ecab 4202 /* Bits 31..0 : Flash variant */
Yassinetaouil 46:b1a9de66ecab 4203 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
Yassinetaouil 46:b1a9de66ecab 4204 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
Yassinetaouil 46:b1a9de66ecab 4205 #define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
Yassinetaouil 46:b1a9de66ecab 4206 #define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
Yassinetaouil 46:b1a9de66ecab 4207 #define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
Yassinetaouil 46:b1a9de66ecab 4208 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
Yassinetaouil 46:b1a9de66ecab 4209
Yassinetaouil 46:b1a9de66ecab 4210 /* Register: FICR_TEMP_A0 */
Yassinetaouil 46:b1a9de66ecab 4211 /* Description: Slope definition A0. */
Yassinetaouil 46:b1a9de66ecab 4212
Yassinetaouil 46:b1a9de66ecab 4213 /* Bits 11..0 : A (slope definition) register. */
Yassinetaouil 46:b1a9de66ecab 4214 #define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
Yassinetaouil 46:b1a9de66ecab 4215 #define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
Yassinetaouil 46:b1a9de66ecab 4216
Yassinetaouil 46:b1a9de66ecab 4217 /* Register: FICR_TEMP_A1 */
Yassinetaouil 46:b1a9de66ecab 4218 /* Description: Slope definition A1. */
Yassinetaouil 46:b1a9de66ecab 4219
Yassinetaouil 46:b1a9de66ecab 4220 /* Bits 11..0 : A (slope definition) register. */
Yassinetaouil 46:b1a9de66ecab 4221 #define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
Yassinetaouil 46:b1a9de66ecab 4222 #define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
Yassinetaouil 46:b1a9de66ecab 4223
Yassinetaouil 46:b1a9de66ecab 4224 /* Register: FICR_TEMP_A2 */
Yassinetaouil 46:b1a9de66ecab 4225 /* Description: Slope definition A2. */
Yassinetaouil 46:b1a9de66ecab 4226
Yassinetaouil 46:b1a9de66ecab 4227 /* Bits 11..0 : A (slope definition) register. */
Yassinetaouil 46:b1a9de66ecab 4228 #define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
Yassinetaouil 46:b1a9de66ecab 4229 #define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
Yassinetaouil 46:b1a9de66ecab 4230
Yassinetaouil 46:b1a9de66ecab 4231 /* Register: FICR_TEMP_A3 */
Yassinetaouil 46:b1a9de66ecab 4232 /* Description: Slope definition A3. */
Yassinetaouil 46:b1a9de66ecab 4233
Yassinetaouil 46:b1a9de66ecab 4234 /* Bits 11..0 : A (slope definition) register. */
Yassinetaouil 46:b1a9de66ecab 4235 #define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
Yassinetaouil 46:b1a9de66ecab 4236 #define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
Yassinetaouil 46:b1a9de66ecab 4237
Yassinetaouil 46:b1a9de66ecab 4238 /* Register: FICR_TEMP_A4 */
Yassinetaouil 46:b1a9de66ecab 4239 /* Description: Slope definition A4. */
Yassinetaouil 46:b1a9de66ecab 4240
Yassinetaouil 46:b1a9de66ecab 4241 /* Bits 11..0 : A (slope definition) register. */
Yassinetaouil 46:b1a9de66ecab 4242 #define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
Yassinetaouil 46:b1a9de66ecab 4243 #define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
Yassinetaouil 46:b1a9de66ecab 4244
Yassinetaouil 46:b1a9de66ecab 4245 /* Register: FICR_TEMP_A5 */
Yassinetaouil 46:b1a9de66ecab 4246 /* Description: Slope definition A5. */
Yassinetaouil 46:b1a9de66ecab 4247
Yassinetaouil 46:b1a9de66ecab 4248 /* Bits 11..0 : A (slope definition) register. */
Yassinetaouil 46:b1a9de66ecab 4249 #define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
Yassinetaouil 46:b1a9de66ecab 4250 #define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
Yassinetaouil 46:b1a9de66ecab 4251
Yassinetaouil 46:b1a9de66ecab 4252 /* Register: FICR_TEMP_B0 */
Yassinetaouil 46:b1a9de66ecab 4253 /* Description: y-intercept B0. */
Yassinetaouil 46:b1a9de66ecab 4254
Yassinetaouil 46:b1a9de66ecab 4255 /* Bits 13..0 : B (y-intercept) */
Yassinetaouil 46:b1a9de66ecab 4256 #define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
Yassinetaouil 46:b1a9de66ecab 4257 #define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
Yassinetaouil 46:b1a9de66ecab 4258
Yassinetaouil 46:b1a9de66ecab 4259 /* Register: FICR_TEMP_B1 */
Yassinetaouil 46:b1a9de66ecab 4260 /* Description: y-intercept B1. */
Yassinetaouil 46:b1a9de66ecab 4261
Yassinetaouil 46:b1a9de66ecab 4262 /* Bits 13..0 : B (y-intercept) */
Yassinetaouil 46:b1a9de66ecab 4263 #define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
Yassinetaouil 46:b1a9de66ecab 4264 #define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
Yassinetaouil 46:b1a9de66ecab 4265
Yassinetaouil 46:b1a9de66ecab 4266 /* Register: FICR_TEMP_B2 */
Yassinetaouil 46:b1a9de66ecab 4267 /* Description: y-intercept B2. */
Yassinetaouil 46:b1a9de66ecab 4268
Yassinetaouil 46:b1a9de66ecab 4269 /* Bits 13..0 : B (y-intercept) */
Yassinetaouil 46:b1a9de66ecab 4270 #define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
Yassinetaouil 46:b1a9de66ecab 4271 #define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
Yassinetaouil 46:b1a9de66ecab 4272
Yassinetaouil 46:b1a9de66ecab 4273 /* Register: FICR_TEMP_B3 */
Yassinetaouil 46:b1a9de66ecab 4274 /* Description: y-intercept B3. */
Yassinetaouil 46:b1a9de66ecab 4275
Yassinetaouil 46:b1a9de66ecab 4276 /* Bits 13..0 : B (y-intercept) */
Yassinetaouil 46:b1a9de66ecab 4277 #define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
Yassinetaouil 46:b1a9de66ecab 4278 #define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
Yassinetaouil 46:b1a9de66ecab 4279
Yassinetaouil 46:b1a9de66ecab 4280 /* Register: FICR_TEMP_B4 */
Yassinetaouil 46:b1a9de66ecab 4281 /* Description: y-intercept B4. */
Yassinetaouil 46:b1a9de66ecab 4282
Yassinetaouil 46:b1a9de66ecab 4283 /* Bits 13..0 : B (y-intercept) */
Yassinetaouil 46:b1a9de66ecab 4284 #define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
Yassinetaouil 46:b1a9de66ecab 4285 #define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
Yassinetaouil 46:b1a9de66ecab 4286
Yassinetaouil 46:b1a9de66ecab 4287 /* Register: FICR_TEMP_B5 */
Yassinetaouil 46:b1a9de66ecab 4288 /* Description: y-intercept B5. */
Yassinetaouil 46:b1a9de66ecab 4289
Yassinetaouil 46:b1a9de66ecab 4290 /* Bits 13..0 : B (y-intercept) */
Yassinetaouil 46:b1a9de66ecab 4291 #define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
Yassinetaouil 46:b1a9de66ecab 4292 #define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
Yassinetaouil 46:b1a9de66ecab 4293
Yassinetaouil 46:b1a9de66ecab 4294 /* Register: FICR_TEMP_T0 */
Yassinetaouil 46:b1a9de66ecab 4295 /* Description: Segment end T0. */
Yassinetaouil 46:b1a9de66ecab 4296
Yassinetaouil 46:b1a9de66ecab 4297 /* Bits 7..0 : T (segment end)register. */
Yassinetaouil 46:b1a9de66ecab 4298 #define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
Yassinetaouil 46:b1a9de66ecab 4299 #define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
Yassinetaouil 46:b1a9de66ecab 4300
Yassinetaouil 46:b1a9de66ecab 4301 /* Register: FICR_TEMP_T1 */
Yassinetaouil 46:b1a9de66ecab 4302 /* Description: Segment end T1. */
Yassinetaouil 46:b1a9de66ecab 4303
Yassinetaouil 46:b1a9de66ecab 4304 /* Bits 7..0 : T (segment end)register. */
Yassinetaouil 46:b1a9de66ecab 4305 #define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
Yassinetaouil 46:b1a9de66ecab 4306 #define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
Yassinetaouil 46:b1a9de66ecab 4307
Yassinetaouil 46:b1a9de66ecab 4308 /* Register: FICR_TEMP_T2 */
Yassinetaouil 46:b1a9de66ecab 4309 /* Description: Segment end T2. */
Yassinetaouil 46:b1a9de66ecab 4310
Yassinetaouil 46:b1a9de66ecab 4311 /* Bits 7..0 : T (segment end)register. */
Yassinetaouil 46:b1a9de66ecab 4312 #define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
Yassinetaouil 46:b1a9de66ecab 4313 #define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
Yassinetaouil 46:b1a9de66ecab 4314
Yassinetaouil 46:b1a9de66ecab 4315 /* Register: FICR_TEMP_T3 */
Yassinetaouil 46:b1a9de66ecab 4316 /* Description: Segment end T3. */
Yassinetaouil 46:b1a9de66ecab 4317
Yassinetaouil 46:b1a9de66ecab 4318 /* Bits 7..0 : T (segment end)register. */
Yassinetaouil 46:b1a9de66ecab 4319 #define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
Yassinetaouil 46:b1a9de66ecab 4320 #define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
Yassinetaouil 46:b1a9de66ecab 4321
Yassinetaouil 46:b1a9de66ecab 4322 /* Register: FICR_TEMP_T4 */
Yassinetaouil 46:b1a9de66ecab 4323 /* Description: Segment end T4. */
Yassinetaouil 46:b1a9de66ecab 4324
Yassinetaouil 46:b1a9de66ecab 4325 /* Bits 7..0 : T (segment end)register. */
Yassinetaouil 46:b1a9de66ecab 4326 #define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
Yassinetaouil 46:b1a9de66ecab 4327 #define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
Yassinetaouil 46:b1a9de66ecab 4328
Yassinetaouil 46:b1a9de66ecab 4329 /* Register: FICR_NFC_TAGHEADER0 */
Yassinetaouil 46:b1a9de66ecab 4330 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Yassinetaouil 46:b1a9de66ecab 4331
Yassinetaouil 46:b1a9de66ecab 4332 /* Bits 31..24 : Unique identifier byte 3 */
Yassinetaouil 46:b1a9de66ecab 4333 #define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
Yassinetaouil 46:b1a9de66ecab 4334 #define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
Yassinetaouil 46:b1a9de66ecab 4335
Yassinetaouil 46:b1a9de66ecab 4336 /* Bits 23..16 : Unique identifier byte 2 */
Yassinetaouil 46:b1a9de66ecab 4337 #define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
Yassinetaouil 46:b1a9de66ecab 4338 #define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
Yassinetaouil 46:b1a9de66ecab 4339
Yassinetaouil 46:b1a9de66ecab 4340 /* Bits 15..8 : Unique identifier byte 1 */
Yassinetaouil 46:b1a9de66ecab 4341 #define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
Yassinetaouil 46:b1a9de66ecab 4342 #define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
Yassinetaouil 46:b1a9de66ecab 4343
Yassinetaouil 46:b1a9de66ecab 4344 /* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
Yassinetaouil 46:b1a9de66ecab 4345 #define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
Yassinetaouil 46:b1a9de66ecab 4346 #define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
Yassinetaouil 46:b1a9de66ecab 4347
Yassinetaouil 46:b1a9de66ecab 4348 /* Register: FICR_NFC_TAGHEADER1 */
Yassinetaouil 46:b1a9de66ecab 4349 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Yassinetaouil 46:b1a9de66ecab 4350
Yassinetaouil 46:b1a9de66ecab 4351 /* Bits 31..24 : Unique identifier byte 7 */
Yassinetaouil 46:b1a9de66ecab 4352 #define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
Yassinetaouil 46:b1a9de66ecab 4353 #define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
Yassinetaouil 46:b1a9de66ecab 4354
Yassinetaouil 46:b1a9de66ecab 4355 /* Bits 23..16 : Unique identifier byte 6 */
Yassinetaouil 46:b1a9de66ecab 4356 #define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
Yassinetaouil 46:b1a9de66ecab 4357 #define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
Yassinetaouil 46:b1a9de66ecab 4358
Yassinetaouil 46:b1a9de66ecab 4359 /* Bits 15..8 : Unique identifier byte 5 */
Yassinetaouil 46:b1a9de66ecab 4360 #define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
Yassinetaouil 46:b1a9de66ecab 4361 #define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
Yassinetaouil 46:b1a9de66ecab 4362
Yassinetaouil 46:b1a9de66ecab 4363 /* Bits 7..0 : Unique identifier byte 4 */
Yassinetaouil 46:b1a9de66ecab 4364 #define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
Yassinetaouil 46:b1a9de66ecab 4365 #define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
Yassinetaouil 46:b1a9de66ecab 4366
Yassinetaouil 46:b1a9de66ecab 4367 /* Register: FICR_NFC_TAGHEADER2 */
Yassinetaouil 46:b1a9de66ecab 4368 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Yassinetaouil 46:b1a9de66ecab 4369
Yassinetaouil 46:b1a9de66ecab 4370 /* Bits 31..24 : Unique identifier byte 11 */
Yassinetaouil 46:b1a9de66ecab 4371 #define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
Yassinetaouil 46:b1a9de66ecab 4372 #define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
Yassinetaouil 46:b1a9de66ecab 4373
Yassinetaouil 46:b1a9de66ecab 4374 /* Bits 23..16 : Unique identifier byte 10 */
Yassinetaouil 46:b1a9de66ecab 4375 #define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
Yassinetaouil 46:b1a9de66ecab 4376 #define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
Yassinetaouil 46:b1a9de66ecab 4377
Yassinetaouil 46:b1a9de66ecab 4378 /* Bits 15..8 : Unique identifier byte 9 */
Yassinetaouil 46:b1a9de66ecab 4379 #define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
Yassinetaouil 46:b1a9de66ecab 4380 #define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
Yassinetaouil 46:b1a9de66ecab 4381
Yassinetaouil 46:b1a9de66ecab 4382 /* Bits 7..0 : Unique identifier byte 8 */
Yassinetaouil 46:b1a9de66ecab 4383 #define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
Yassinetaouil 46:b1a9de66ecab 4384 #define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
Yassinetaouil 46:b1a9de66ecab 4385
Yassinetaouil 46:b1a9de66ecab 4386 /* Register: FICR_NFC_TAGHEADER3 */
Yassinetaouil 46:b1a9de66ecab 4387 /* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Yassinetaouil 46:b1a9de66ecab 4388
Yassinetaouil 46:b1a9de66ecab 4389 /* Bits 31..24 : Unique identifier byte 15 */
Yassinetaouil 46:b1a9de66ecab 4390 #define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
Yassinetaouil 46:b1a9de66ecab 4391 #define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
Yassinetaouil 46:b1a9de66ecab 4392
Yassinetaouil 46:b1a9de66ecab 4393 /* Bits 23..16 : Unique identifier byte 14 */
Yassinetaouil 46:b1a9de66ecab 4394 #define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
Yassinetaouil 46:b1a9de66ecab 4395 #define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
Yassinetaouil 46:b1a9de66ecab 4396
Yassinetaouil 46:b1a9de66ecab 4397 /* Bits 15..8 : Unique identifier byte 13 */
Yassinetaouil 46:b1a9de66ecab 4398 #define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
Yassinetaouil 46:b1a9de66ecab 4399 #define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
Yassinetaouil 46:b1a9de66ecab 4400
Yassinetaouil 46:b1a9de66ecab 4401 /* Bits 7..0 : Unique identifier byte 12 */
Yassinetaouil 46:b1a9de66ecab 4402 #define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
Yassinetaouil 46:b1a9de66ecab 4403 #define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
Yassinetaouil 46:b1a9de66ecab 4404
Yassinetaouil 46:b1a9de66ecab 4405
Yassinetaouil 46:b1a9de66ecab 4406 /* Peripheral: GPIOTE */
Yassinetaouil 46:b1a9de66ecab 4407 /* Description: GPIO Tasks and Events */
Yassinetaouil 46:b1a9de66ecab 4408
Yassinetaouil 46:b1a9de66ecab 4409 /* Register: GPIOTE_INTENSET */
Yassinetaouil 46:b1a9de66ecab 4410 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 4411
Yassinetaouil 46:b1a9de66ecab 4412 /* Bit 31 : Write '1' to Enable interrupt for PORT event */
Yassinetaouil 46:b1a9de66ecab 4413 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
Yassinetaouil 46:b1a9de66ecab 4414 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
Yassinetaouil 46:b1a9de66ecab 4415 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4416 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4417 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4418
Yassinetaouil 46:b1a9de66ecab 4419 /* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
Yassinetaouil 46:b1a9de66ecab 4420 #define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
Yassinetaouil 46:b1a9de66ecab 4421 #define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
Yassinetaouil 46:b1a9de66ecab 4422 #define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4423 #define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4424 #define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4425
Yassinetaouil 46:b1a9de66ecab 4426 /* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
Yassinetaouil 46:b1a9de66ecab 4427 #define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
Yassinetaouil 46:b1a9de66ecab 4428 #define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
Yassinetaouil 46:b1a9de66ecab 4429 #define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4430 #define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4431 #define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4432
Yassinetaouil 46:b1a9de66ecab 4433 /* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
Yassinetaouil 46:b1a9de66ecab 4434 #define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
Yassinetaouil 46:b1a9de66ecab 4435 #define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
Yassinetaouil 46:b1a9de66ecab 4436 #define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4437 #define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4438 #define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4439
Yassinetaouil 46:b1a9de66ecab 4440 /* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
Yassinetaouil 46:b1a9de66ecab 4441 #define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
Yassinetaouil 46:b1a9de66ecab 4442 #define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
Yassinetaouil 46:b1a9de66ecab 4443 #define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4444 #define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4445 #define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4446
Yassinetaouil 46:b1a9de66ecab 4447 /* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
Yassinetaouil 46:b1a9de66ecab 4448 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
Yassinetaouil 46:b1a9de66ecab 4449 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
Yassinetaouil 46:b1a9de66ecab 4450 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4451 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4452 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4453
Yassinetaouil 46:b1a9de66ecab 4454 /* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
Yassinetaouil 46:b1a9de66ecab 4455 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
Yassinetaouil 46:b1a9de66ecab 4456 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
Yassinetaouil 46:b1a9de66ecab 4457 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4458 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4459 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4460
Yassinetaouil 46:b1a9de66ecab 4461 /* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
Yassinetaouil 46:b1a9de66ecab 4462 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
Yassinetaouil 46:b1a9de66ecab 4463 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
Yassinetaouil 46:b1a9de66ecab 4464 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4465 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4466 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4467
Yassinetaouil 46:b1a9de66ecab 4468 /* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
Yassinetaouil 46:b1a9de66ecab 4469 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
Yassinetaouil 46:b1a9de66ecab 4470 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
Yassinetaouil 46:b1a9de66ecab 4471 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4472 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4473 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4474
Yassinetaouil 46:b1a9de66ecab 4475 /* Register: GPIOTE_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 4476 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 4477
Yassinetaouil 46:b1a9de66ecab 4478 /* Bit 31 : Write '1' to Disable interrupt for PORT event */
Yassinetaouil 46:b1a9de66ecab 4479 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
Yassinetaouil 46:b1a9de66ecab 4480 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
Yassinetaouil 46:b1a9de66ecab 4481 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4482 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4483 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4484
Yassinetaouil 46:b1a9de66ecab 4485 /* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
Yassinetaouil 46:b1a9de66ecab 4486 #define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
Yassinetaouil 46:b1a9de66ecab 4487 #define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
Yassinetaouil 46:b1a9de66ecab 4488 #define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4489 #define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4490 #define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4491
Yassinetaouil 46:b1a9de66ecab 4492 /* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
Yassinetaouil 46:b1a9de66ecab 4493 #define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
Yassinetaouil 46:b1a9de66ecab 4494 #define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
Yassinetaouil 46:b1a9de66ecab 4495 #define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4496 #define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4497 #define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4498
Yassinetaouil 46:b1a9de66ecab 4499 /* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
Yassinetaouil 46:b1a9de66ecab 4500 #define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
Yassinetaouil 46:b1a9de66ecab 4501 #define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
Yassinetaouil 46:b1a9de66ecab 4502 #define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4503 #define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4504 #define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4505
Yassinetaouil 46:b1a9de66ecab 4506 /* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
Yassinetaouil 46:b1a9de66ecab 4507 #define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
Yassinetaouil 46:b1a9de66ecab 4508 #define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
Yassinetaouil 46:b1a9de66ecab 4509 #define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4510 #define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4511 #define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4512
Yassinetaouil 46:b1a9de66ecab 4513 /* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
Yassinetaouil 46:b1a9de66ecab 4514 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
Yassinetaouil 46:b1a9de66ecab 4515 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
Yassinetaouil 46:b1a9de66ecab 4516 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4517 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4518 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4519
Yassinetaouil 46:b1a9de66ecab 4520 /* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
Yassinetaouil 46:b1a9de66ecab 4521 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
Yassinetaouil 46:b1a9de66ecab 4522 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
Yassinetaouil 46:b1a9de66ecab 4523 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4524 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4525 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4526
Yassinetaouil 46:b1a9de66ecab 4527 /* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
Yassinetaouil 46:b1a9de66ecab 4528 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
Yassinetaouil 46:b1a9de66ecab 4529 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
Yassinetaouil 46:b1a9de66ecab 4530 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4531 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4532 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4533
Yassinetaouil 46:b1a9de66ecab 4534 /* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
Yassinetaouil 46:b1a9de66ecab 4535 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
Yassinetaouil 46:b1a9de66ecab 4536 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
Yassinetaouil 46:b1a9de66ecab 4537 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4538 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4539 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4540
Yassinetaouil 46:b1a9de66ecab 4541 /* Register: GPIOTE_CONFIG */
Yassinetaouil 46:b1a9de66ecab 4542 /* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
Yassinetaouil 46:b1a9de66ecab 4543
Yassinetaouil 46:b1a9de66ecab 4544 /* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
Yassinetaouil 46:b1a9de66ecab 4545 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
Yassinetaouil 46:b1a9de66ecab 4546 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
Yassinetaouil 46:b1a9de66ecab 4547 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
Yassinetaouil 46:b1a9de66ecab 4548 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
Yassinetaouil 46:b1a9de66ecab 4549
Yassinetaouil 46:b1a9de66ecab 4550 /* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
Yassinetaouil 46:b1a9de66ecab 4551 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
Yassinetaouil 46:b1a9de66ecab 4552 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
Yassinetaouil 46:b1a9de66ecab 4553 #define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
Yassinetaouil 46:b1a9de66ecab 4554 #define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
Yassinetaouil 46:b1a9de66ecab 4555 #define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
Yassinetaouil 46:b1a9de66ecab 4556 #define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
Yassinetaouil 46:b1a9de66ecab 4557
Yassinetaouil 46:b1a9de66ecab 4558 /* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
Yassinetaouil 46:b1a9de66ecab 4559 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
Yassinetaouil 46:b1a9de66ecab 4560 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
Yassinetaouil 46:b1a9de66ecab 4561
Yassinetaouil 46:b1a9de66ecab 4562 /* Bits 1..0 : Mode */
Yassinetaouil 46:b1a9de66ecab 4563 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
Yassinetaouil 46:b1a9de66ecab 4564 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
Yassinetaouil 46:b1a9de66ecab 4565 #define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
Yassinetaouil 46:b1a9de66ecab 4566 #define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
Yassinetaouil 46:b1a9de66ecab 4567 #define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
Yassinetaouil 46:b1a9de66ecab 4568
Yassinetaouil 46:b1a9de66ecab 4569
Yassinetaouil 46:b1a9de66ecab 4570 /* Peripheral: I2S */
Yassinetaouil 46:b1a9de66ecab 4571 /* Description: Inter-IC Sound */
Yassinetaouil 46:b1a9de66ecab 4572
Yassinetaouil 46:b1a9de66ecab 4573 /* Register: I2S_INTEN */
Yassinetaouil 46:b1a9de66ecab 4574 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 4575
Yassinetaouil 46:b1a9de66ecab 4576 /* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
Yassinetaouil 46:b1a9de66ecab 4577 #define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4578 #define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4579 #define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4580 #define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4581
Yassinetaouil 46:b1a9de66ecab 4582 /* Bit 2 : Enable or disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 4583 #define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 4584 #define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 4585 #define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4586 #define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4587
Yassinetaouil 46:b1a9de66ecab 4588 /* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
Yassinetaouil 46:b1a9de66ecab 4589 #define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4590 #define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4591 #define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4592 #define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4593
Yassinetaouil 46:b1a9de66ecab 4594 /* Register: I2S_INTENSET */
Yassinetaouil 46:b1a9de66ecab 4595 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 4596
Yassinetaouil 46:b1a9de66ecab 4597 /* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
Yassinetaouil 46:b1a9de66ecab 4598 #define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4599 #define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4600 #define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4601 #define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4602 #define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4603
Yassinetaouil 46:b1a9de66ecab 4604 /* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 4605 #define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 4606 #define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 4607 #define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4608 #define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4609 #define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4610
Yassinetaouil 46:b1a9de66ecab 4611 /* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
Yassinetaouil 46:b1a9de66ecab 4612 #define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4613 #define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4614 #define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4615 #define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4616 #define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4617
Yassinetaouil 46:b1a9de66ecab 4618 /* Register: I2S_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 4619 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 4620
Yassinetaouil 46:b1a9de66ecab 4621 /* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
Yassinetaouil 46:b1a9de66ecab 4622 #define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4623 #define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4624 #define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4625 #define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4626 #define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4627
Yassinetaouil 46:b1a9de66ecab 4628 /* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 4629 #define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 4630 #define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 4631 #define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4632 #define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4633 #define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4634
Yassinetaouil 46:b1a9de66ecab 4635 /* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
Yassinetaouil 46:b1a9de66ecab 4636 #define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4637 #define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
Yassinetaouil 46:b1a9de66ecab 4638 #define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4639 #define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4640 #define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4641
Yassinetaouil 46:b1a9de66ecab 4642 /* Register: I2S_ENABLE */
Yassinetaouil 46:b1a9de66ecab 4643 /* Description: Enable I2S module. */
Yassinetaouil 46:b1a9de66ecab 4644
Yassinetaouil 46:b1a9de66ecab 4645 /* Bit 0 : Enable I2S module. */
Yassinetaouil 46:b1a9de66ecab 4646 #define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 4647 #define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 4648 #define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4649 #define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4650
Yassinetaouil 46:b1a9de66ecab 4651 /* Register: I2S_CONFIG_MODE */
Yassinetaouil 46:b1a9de66ecab 4652 /* Description: I2S mode. */
Yassinetaouil 46:b1a9de66ecab 4653
Yassinetaouil 46:b1a9de66ecab 4654 /* Bit 0 : I2S mode. */
Yassinetaouil 46:b1a9de66ecab 4655 #define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Yassinetaouil 46:b1a9de66ecab 4656 #define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Yassinetaouil 46:b1a9de66ecab 4657 #define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
Yassinetaouil 46:b1a9de66ecab 4658 #define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
Yassinetaouil 46:b1a9de66ecab 4659
Yassinetaouil 46:b1a9de66ecab 4660 /* Register: I2S_CONFIG_RXEN */
Yassinetaouil 46:b1a9de66ecab 4661 /* Description: Reception (RX) enable. */
Yassinetaouil 46:b1a9de66ecab 4662
Yassinetaouil 46:b1a9de66ecab 4663 /* Bit 0 : Reception (RX) enable. */
Yassinetaouil 46:b1a9de66ecab 4664 #define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
Yassinetaouil 46:b1a9de66ecab 4665 #define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
Yassinetaouil 46:b1a9de66ecab 4666 #define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
Yassinetaouil 46:b1a9de66ecab 4667 #define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
Yassinetaouil 46:b1a9de66ecab 4668
Yassinetaouil 46:b1a9de66ecab 4669 /* Register: I2S_CONFIG_TXEN */
Yassinetaouil 46:b1a9de66ecab 4670 /* Description: Transmission (TX) enable. */
Yassinetaouil 46:b1a9de66ecab 4671
Yassinetaouil 46:b1a9de66ecab 4672 /* Bit 0 : Transmission (TX) enable. */
Yassinetaouil 46:b1a9de66ecab 4673 #define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
Yassinetaouil 46:b1a9de66ecab 4674 #define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
Yassinetaouil 46:b1a9de66ecab 4675 #define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
Yassinetaouil 46:b1a9de66ecab 4676 #define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
Yassinetaouil 46:b1a9de66ecab 4677
Yassinetaouil 46:b1a9de66ecab 4678 /* Register: I2S_CONFIG_MCKEN */
Yassinetaouil 46:b1a9de66ecab 4679 /* Description: Master clock generator enable. */
Yassinetaouil 46:b1a9de66ecab 4680
Yassinetaouil 46:b1a9de66ecab 4681 /* Bit 0 : Master clock generator enable. */
Yassinetaouil 46:b1a9de66ecab 4682 #define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
Yassinetaouil 46:b1a9de66ecab 4683 #define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
Yassinetaouil 46:b1a9de66ecab 4684 #define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
Yassinetaouil 46:b1a9de66ecab 4685 #define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
Yassinetaouil 46:b1a9de66ecab 4686
Yassinetaouil 46:b1a9de66ecab 4687 /* Register: I2S_CONFIG_MCKFREQ */
Yassinetaouil 46:b1a9de66ecab 4688 /* Description: Master clock generator frequency. */
Yassinetaouil 46:b1a9de66ecab 4689
Yassinetaouil 46:b1a9de66ecab 4690 /* Bits 31..0 : Master clock generator frequency. */
Yassinetaouil 46:b1a9de66ecab 4691 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
Yassinetaouil 46:b1a9de66ecab 4692 #define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
Yassinetaouil 46:b1a9de66ecab 4693 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
Yassinetaouil 46:b1a9de66ecab 4694 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
Yassinetaouil 46:b1a9de66ecab 4695 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
Yassinetaouil 46:b1a9de66ecab 4696 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
Yassinetaouil 46:b1a9de66ecab 4697 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
Yassinetaouil 46:b1a9de66ecab 4698 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
Yassinetaouil 46:b1a9de66ecab 4699 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
Yassinetaouil 46:b1a9de66ecab 4700 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
Yassinetaouil 46:b1a9de66ecab 4701 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
Yassinetaouil 46:b1a9de66ecab 4702 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
Yassinetaouil 46:b1a9de66ecab 4703 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
Yassinetaouil 46:b1a9de66ecab 4704 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
Yassinetaouil 46:b1a9de66ecab 4705 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
Yassinetaouil 46:b1a9de66ecab 4706 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
Yassinetaouil 46:b1a9de66ecab 4707 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
Yassinetaouil 46:b1a9de66ecab 4708 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
Yassinetaouil 46:b1a9de66ecab 4709 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
Yassinetaouil 46:b1a9de66ecab 4710 #define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
Yassinetaouil 46:b1a9de66ecab 4711
Yassinetaouil 46:b1a9de66ecab 4712 /* Register: I2S_CONFIG_RATIO */
Yassinetaouil 46:b1a9de66ecab 4713 /* Description: MCK / LRCK ratio. */
Yassinetaouil 46:b1a9de66ecab 4714
Yassinetaouil 46:b1a9de66ecab 4715 /* Bits 3..0 : MCK / LRCK ratio. */
Yassinetaouil 46:b1a9de66ecab 4716 #define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
Yassinetaouil 46:b1a9de66ecab 4717 #define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
Yassinetaouil 46:b1a9de66ecab 4718 #define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
Yassinetaouil 46:b1a9de66ecab 4719 #define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
Yassinetaouil 46:b1a9de66ecab 4720 #define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
Yassinetaouil 46:b1a9de66ecab 4721 #define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
Yassinetaouil 46:b1a9de66ecab 4722 #define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
Yassinetaouil 46:b1a9de66ecab 4723 #define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
Yassinetaouil 46:b1a9de66ecab 4724 #define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
Yassinetaouil 46:b1a9de66ecab 4725 #define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
Yassinetaouil 46:b1a9de66ecab 4726 #define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
Yassinetaouil 46:b1a9de66ecab 4727
Yassinetaouil 46:b1a9de66ecab 4728 /* Register: I2S_CONFIG_SWIDTH */
Yassinetaouil 46:b1a9de66ecab 4729 /* Description: Sample width. */
Yassinetaouil 46:b1a9de66ecab 4730
Yassinetaouil 46:b1a9de66ecab 4731 /* Bits 1..0 : Sample width. */
Yassinetaouil 46:b1a9de66ecab 4732 #define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
Yassinetaouil 46:b1a9de66ecab 4733 #define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
Yassinetaouil 46:b1a9de66ecab 4734 #define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
Yassinetaouil 46:b1a9de66ecab 4735 #define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
Yassinetaouil 46:b1a9de66ecab 4736 #define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
Yassinetaouil 46:b1a9de66ecab 4737
Yassinetaouil 46:b1a9de66ecab 4738 /* Register: I2S_CONFIG_ALIGN */
Yassinetaouil 46:b1a9de66ecab 4739 /* Description: Alignment of sample within a frame. */
Yassinetaouil 46:b1a9de66ecab 4740
Yassinetaouil 46:b1a9de66ecab 4741 /* Bit 0 : Alignment of sample within a frame. */
Yassinetaouil 46:b1a9de66ecab 4742 #define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
Yassinetaouil 46:b1a9de66ecab 4743 #define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
Yassinetaouil 46:b1a9de66ecab 4744 #define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
Yassinetaouil 46:b1a9de66ecab 4745 #define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
Yassinetaouil 46:b1a9de66ecab 4746
Yassinetaouil 46:b1a9de66ecab 4747 /* Register: I2S_CONFIG_FORMAT */
Yassinetaouil 46:b1a9de66ecab 4748 /* Description: Frame format. */
Yassinetaouil 46:b1a9de66ecab 4749
Yassinetaouil 46:b1a9de66ecab 4750 /* Bit 0 : Frame format. */
Yassinetaouil 46:b1a9de66ecab 4751 #define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
Yassinetaouil 46:b1a9de66ecab 4752 #define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
Yassinetaouil 46:b1a9de66ecab 4753 #define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
Yassinetaouil 46:b1a9de66ecab 4754 #define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
Yassinetaouil 46:b1a9de66ecab 4755
Yassinetaouil 46:b1a9de66ecab 4756 /* Register: I2S_CONFIG_CHANNELS */
Yassinetaouil 46:b1a9de66ecab 4757 /* Description: Enable channels. */
Yassinetaouil 46:b1a9de66ecab 4758
Yassinetaouil 46:b1a9de66ecab 4759 /* Bits 1..0 : Enable channels. */
Yassinetaouil 46:b1a9de66ecab 4760 #define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
Yassinetaouil 46:b1a9de66ecab 4761 #define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
Yassinetaouil 46:b1a9de66ecab 4762 #define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
Yassinetaouil 46:b1a9de66ecab 4763 #define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
Yassinetaouil 46:b1a9de66ecab 4764 #define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
Yassinetaouil 46:b1a9de66ecab 4765
Yassinetaouil 46:b1a9de66ecab 4766 /* Register: I2S_RXD_PTR */
Yassinetaouil 46:b1a9de66ecab 4767 /* Description: Receive buffer RAM start address. */
Yassinetaouil 46:b1a9de66ecab 4768
Yassinetaouil 46:b1a9de66ecab 4769 /* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
Yassinetaouil 46:b1a9de66ecab 4770 #define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 4771 #define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 4772
Yassinetaouil 46:b1a9de66ecab 4773 /* Register: I2S_TXD_PTR */
Yassinetaouil 46:b1a9de66ecab 4774 /* Description: Transmit buffer RAM start address. */
Yassinetaouil 46:b1a9de66ecab 4775
Yassinetaouil 46:b1a9de66ecab 4776 /* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
Yassinetaouil 46:b1a9de66ecab 4777 #define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 4778 #define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 4779
Yassinetaouil 46:b1a9de66ecab 4780 /* Register: I2S_RXTXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 4781 /* Description: Size of RXD and TXD buffers. */
Yassinetaouil 46:b1a9de66ecab 4782
Yassinetaouil 46:b1a9de66ecab 4783 /* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
Yassinetaouil 46:b1a9de66ecab 4784 #define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 4785 #define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 4786
Yassinetaouil 46:b1a9de66ecab 4787 /* Register: I2S_PSEL_MCK */
Yassinetaouil 46:b1a9de66ecab 4788 /* Description: Pin select for MCK signal. */
Yassinetaouil 46:b1a9de66ecab 4789
Yassinetaouil 46:b1a9de66ecab 4790 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 4791 #define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4792 #define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4793 #define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 4794 #define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 4795
Yassinetaouil 46:b1a9de66ecab 4796 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 4797 #define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4798 #define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4799
Yassinetaouil 46:b1a9de66ecab 4800 /* Register: I2S_PSEL_SCK */
Yassinetaouil 46:b1a9de66ecab 4801 /* Description: Pin select for SCK signal. */
Yassinetaouil 46:b1a9de66ecab 4802
Yassinetaouil 46:b1a9de66ecab 4803 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 4804 #define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4805 #define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4806 #define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 4807 #define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 4808
Yassinetaouil 46:b1a9de66ecab 4809 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 4810 #define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4811 #define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4812
Yassinetaouil 46:b1a9de66ecab 4813 /* Register: I2S_PSEL_LRCK */
Yassinetaouil 46:b1a9de66ecab 4814 /* Description: Pin select for LRCK signal. */
Yassinetaouil 46:b1a9de66ecab 4815
Yassinetaouil 46:b1a9de66ecab 4816 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 4817 #define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4818 #define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4819 #define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 4820 #define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 4821
Yassinetaouil 46:b1a9de66ecab 4822 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 4823 #define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4824 #define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4825
Yassinetaouil 46:b1a9de66ecab 4826 /* Register: I2S_PSEL_SDIN */
Yassinetaouil 46:b1a9de66ecab 4827 /* Description: Pin select for SDIN signal. */
Yassinetaouil 46:b1a9de66ecab 4828
Yassinetaouil 46:b1a9de66ecab 4829 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 4830 #define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4831 #define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4832 #define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 4833 #define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 4834
Yassinetaouil 46:b1a9de66ecab 4835 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 4836 #define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4837 #define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4838
Yassinetaouil 46:b1a9de66ecab 4839 /* Register: I2S_PSEL_SDOUT */
Yassinetaouil 46:b1a9de66ecab 4840 /* Description: Pin select for SDOUT signal. */
Yassinetaouil 46:b1a9de66ecab 4841
Yassinetaouil 46:b1a9de66ecab 4842 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 4843 #define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4844 #define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 4845 #define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 4846 #define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 4847
Yassinetaouil 46:b1a9de66ecab 4848 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 4849 #define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4850 #define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 4851
Yassinetaouil 46:b1a9de66ecab 4852
Yassinetaouil 46:b1a9de66ecab 4853 /* Peripheral: LPCOMP */
Yassinetaouil 46:b1a9de66ecab 4854 /* Description: Low Power Comparator */
Yassinetaouil 46:b1a9de66ecab 4855
Yassinetaouil 46:b1a9de66ecab 4856 /* Register: LPCOMP_SHORTS */
Yassinetaouil 46:b1a9de66ecab 4857 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 4858
Yassinetaouil 46:b1a9de66ecab 4859 /* Bit 4 : Shortcut between CROSS event and STOP task */
Yassinetaouil 46:b1a9de66ecab 4860 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
Yassinetaouil 46:b1a9de66ecab 4861 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
Yassinetaouil 46:b1a9de66ecab 4862 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 4863 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 4864
Yassinetaouil 46:b1a9de66ecab 4865 /* Bit 3 : Shortcut between UP event and STOP task */
Yassinetaouil 46:b1a9de66ecab 4866 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
Yassinetaouil 46:b1a9de66ecab 4867 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
Yassinetaouil 46:b1a9de66ecab 4868 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 4869 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 4870
Yassinetaouil 46:b1a9de66ecab 4871 /* Bit 2 : Shortcut between DOWN event and STOP task */
Yassinetaouil 46:b1a9de66ecab 4872 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
Yassinetaouil 46:b1a9de66ecab 4873 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
Yassinetaouil 46:b1a9de66ecab 4874 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 4875 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 4876
Yassinetaouil 46:b1a9de66ecab 4877 /* Bit 1 : Shortcut between READY event and STOP task */
Yassinetaouil 46:b1a9de66ecab 4878 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 4879 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 4880 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 4881 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 4882
Yassinetaouil 46:b1a9de66ecab 4883 /* Bit 0 : Shortcut between READY event and SAMPLE task */
Yassinetaouil 46:b1a9de66ecab 4884 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 4885 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 4886 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 4887 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 4888
Yassinetaouil 46:b1a9de66ecab 4889 /* Register: LPCOMP_INTENSET */
Yassinetaouil 46:b1a9de66ecab 4890 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 4891
Yassinetaouil 46:b1a9de66ecab 4892 /* Bit 3 : Write '1' to Enable interrupt for CROSS event */
Yassinetaouil 46:b1a9de66ecab 4893 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 4894 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 4895 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4896 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4897 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4898
Yassinetaouil 46:b1a9de66ecab 4899 /* Bit 2 : Write '1' to Enable interrupt for UP event */
Yassinetaouil 46:b1a9de66ecab 4900 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
Yassinetaouil 46:b1a9de66ecab 4901 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
Yassinetaouil 46:b1a9de66ecab 4902 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4903 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4904 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4905
Yassinetaouil 46:b1a9de66ecab 4906 /* Bit 1 : Write '1' to Enable interrupt for DOWN event */
Yassinetaouil 46:b1a9de66ecab 4907 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 4908 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 4909 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4910 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4911 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4912
Yassinetaouil 46:b1a9de66ecab 4913 /* Bit 0 : Write '1' to Enable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 4914 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 4915 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 4916 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4917 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4918 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4919
Yassinetaouil 46:b1a9de66ecab 4920 /* Register: LPCOMP_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 4921 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 4922
Yassinetaouil 46:b1a9de66ecab 4923 /* Bit 3 : Write '1' to Disable interrupt for CROSS event */
Yassinetaouil 46:b1a9de66ecab 4924 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 4925 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
Yassinetaouil 46:b1a9de66ecab 4926 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4927 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4928 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4929
Yassinetaouil 46:b1a9de66ecab 4930 /* Bit 2 : Write '1' to Disable interrupt for UP event */
Yassinetaouil 46:b1a9de66ecab 4931 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
Yassinetaouil 46:b1a9de66ecab 4932 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
Yassinetaouil 46:b1a9de66ecab 4933 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4934 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4935 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4936
Yassinetaouil 46:b1a9de66ecab 4937 /* Bit 1 : Write '1' to Disable interrupt for DOWN event */
Yassinetaouil 46:b1a9de66ecab 4938 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 4939 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
Yassinetaouil 46:b1a9de66ecab 4940 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4941 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4942 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4943
Yassinetaouil 46:b1a9de66ecab 4944 /* Bit 0 : Write '1' to Disable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 4945 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 4946 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 4947 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 4948 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 4949 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4950
Yassinetaouil 46:b1a9de66ecab 4951 /* Register: LPCOMP_RESULT */
Yassinetaouil 46:b1a9de66ecab 4952 /* Description: Compare result */
Yassinetaouil 46:b1a9de66ecab 4953
Yassinetaouil 46:b1a9de66ecab 4954 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
Yassinetaouil 46:b1a9de66ecab 4955 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
Yassinetaouil 46:b1a9de66ecab 4956 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
Yassinetaouil 46:b1a9de66ecab 4957 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
Yassinetaouil 46:b1a9de66ecab 4958 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
Yassinetaouil 46:b1a9de66ecab 4959
Yassinetaouil 46:b1a9de66ecab 4960 /* Register: LPCOMP_ENABLE */
Yassinetaouil 46:b1a9de66ecab 4961 /* Description: Enable LPCOMP */
Yassinetaouil 46:b1a9de66ecab 4962
Yassinetaouil 46:b1a9de66ecab 4963 /* Bits 1..0 : Enable or disable LPCOMP */
Yassinetaouil 46:b1a9de66ecab 4964 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 4965 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 4966 #define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 4967 #define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 4968
Yassinetaouil 46:b1a9de66ecab 4969 /* Register: LPCOMP_PSEL */
Yassinetaouil 46:b1a9de66ecab 4970 /* Description: Input pin select */
Yassinetaouil 46:b1a9de66ecab 4971
Yassinetaouil 46:b1a9de66ecab 4972 /* Bits 2..0 : Analog pin select */
Yassinetaouil 46:b1a9de66ecab 4973 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
Yassinetaouil 46:b1a9de66ecab 4974 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
Yassinetaouil 46:b1a9de66ecab 4975 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 4976 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 4977 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 4978 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 4979 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 4980 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 4981 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 4982 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
Yassinetaouil 46:b1a9de66ecab 4983
Yassinetaouil 46:b1a9de66ecab 4984 /* Register: LPCOMP_REFSEL */
Yassinetaouil 46:b1a9de66ecab 4985 /* Description: Reference select */
Yassinetaouil 46:b1a9de66ecab 4986
Yassinetaouil 46:b1a9de66ecab 4987 /* Bits 3..0 : Reference select */
Yassinetaouil 46:b1a9de66ecab 4988 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
Yassinetaouil 46:b1a9de66ecab 4989 #define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
Yassinetaouil 46:b1a9de66ecab 4990 #define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
Yassinetaouil 46:b1a9de66ecab 4991 #define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
Yassinetaouil 46:b1a9de66ecab 4992 #define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
Yassinetaouil 46:b1a9de66ecab 4993 #define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
Yassinetaouil 46:b1a9de66ecab 4994 #define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
Yassinetaouil 46:b1a9de66ecab 4995 #define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
Yassinetaouil 46:b1a9de66ecab 4996 #define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
Yassinetaouil 46:b1a9de66ecab 4997 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
Yassinetaouil 46:b1a9de66ecab 4998 #define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
Yassinetaouil 46:b1a9de66ecab 4999 #define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
Yassinetaouil 46:b1a9de66ecab 5000 #define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
Yassinetaouil 46:b1a9de66ecab 5001 #define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
Yassinetaouil 46:b1a9de66ecab 5002 #define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
Yassinetaouil 46:b1a9de66ecab 5003 #define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
Yassinetaouil 46:b1a9de66ecab 5004 #define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
Yassinetaouil 46:b1a9de66ecab 5005 #define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
Yassinetaouil 46:b1a9de66ecab 5006
Yassinetaouil 46:b1a9de66ecab 5007 /* Register: LPCOMP_EXTREFSEL */
Yassinetaouil 46:b1a9de66ecab 5008 /* Description: External reference select */
Yassinetaouil 46:b1a9de66ecab 5009
Yassinetaouil 46:b1a9de66ecab 5010 /* Bit 0 : External analog reference select */
Yassinetaouil 46:b1a9de66ecab 5011 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
Yassinetaouil 46:b1a9de66ecab 5012 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
Yassinetaouil 46:b1a9de66ecab 5013 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
Yassinetaouil 46:b1a9de66ecab 5014 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
Yassinetaouil 46:b1a9de66ecab 5015
Yassinetaouil 46:b1a9de66ecab 5016 /* Register: LPCOMP_ANADETECT */
Yassinetaouil 46:b1a9de66ecab 5017 /* Description: Analog detect configuration */
Yassinetaouil 46:b1a9de66ecab 5018
Yassinetaouil 46:b1a9de66ecab 5019 /* Bits 1..0 : Analog detect configuration */
Yassinetaouil 46:b1a9de66ecab 5020 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
Yassinetaouil 46:b1a9de66ecab 5021 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
Yassinetaouil 46:b1a9de66ecab 5022 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
Yassinetaouil 46:b1a9de66ecab 5023 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
Yassinetaouil 46:b1a9de66ecab 5024 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
Yassinetaouil 46:b1a9de66ecab 5025
Yassinetaouil 46:b1a9de66ecab 5026 /* Register: LPCOMP_HYST */
Yassinetaouil 46:b1a9de66ecab 5027 /* Description: Comparator hysteresis enable */
Yassinetaouil 46:b1a9de66ecab 5028
Yassinetaouil 46:b1a9de66ecab 5029 /* Bit 0 : Comparator hysteresis enable */
Yassinetaouil 46:b1a9de66ecab 5030 #define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
Yassinetaouil 46:b1a9de66ecab 5031 #define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
Yassinetaouil 46:b1a9de66ecab 5032 #define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
Yassinetaouil 46:b1a9de66ecab 5033 #define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
Yassinetaouil 46:b1a9de66ecab 5034
Yassinetaouil 46:b1a9de66ecab 5035
Yassinetaouil 46:b1a9de66ecab 5036 /* Peripheral: MWU */
Yassinetaouil 46:b1a9de66ecab 5037 /* Description: Memory Watch Unit */
Yassinetaouil 46:b1a9de66ecab 5038
Yassinetaouil 46:b1a9de66ecab 5039 /* Register: MWU_INTEN */
Yassinetaouil 46:b1a9de66ecab 5040 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 5041
Yassinetaouil 46:b1a9de66ecab 5042 /* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5043 #define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5044 #define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5045 #define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5046 #define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5047
Yassinetaouil 46:b1a9de66ecab 5048 /* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5049 #define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5050 #define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5051 #define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5052 #define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5053
Yassinetaouil 46:b1a9de66ecab 5054 /* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5055 #define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5056 #define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5057 #define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5058 #define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5059
Yassinetaouil 46:b1a9de66ecab 5060 /* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5061 #define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5062 #define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5063 #define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5064 #define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5065
Yassinetaouil 46:b1a9de66ecab 5066 /* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
Yassinetaouil 46:b1a9de66ecab 5067 #define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5068 #define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5069 #define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5070 #define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5071
Yassinetaouil 46:b1a9de66ecab 5072 /* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
Yassinetaouil 46:b1a9de66ecab 5073 #define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5074 #define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5075 #define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5076 #define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5077
Yassinetaouil 46:b1a9de66ecab 5078 /* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
Yassinetaouil 46:b1a9de66ecab 5079 #define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5080 #define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5081 #define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5082 #define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5083
Yassinetaouil 46:b1a9de66ecab 5084 /* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
Yassinetaouil 46:b1a9de66ecab 5085 #define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5086 #define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5087 #define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5088 #define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5089
Yassinetaouil 46:b1a9de66ecab 5090 /* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5091 #define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5092 #define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5093 #define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5094 #define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5095
Yassinetaouil 46:b1a9de66ecab 5096 /* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5097 #define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5098 #define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5099 #define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5100 #define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5101
Yassinetaouil 46:b1a9de66ecab 5102 /* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5103 #define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5104 #define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5105 #define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5106 #define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5107
Yassinetaouil 46:b1a9de66ecab 5108 /* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5109 #define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5110 #define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5111 #define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5112 #define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5113
Yassinetaouil 46:b1a9de66ecab 5114 /* Register: MWU_INTENSET */
Yassinetaouil 46:b1a9de66ecab 5115 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 5116
Yassinetaouil 46:b1a9de66ecab 5117 /* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5118 #define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5119 #define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5120 #define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5121 #define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5122 #define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5123
Yassinetaouil 46:b1a9de66ecab 5124 /* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5125 #define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5126 #define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5127 #define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5128 #define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5129 #define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5130
Yassinetaouil 46:b1a9de66ecab 5131 /* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5132 #define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5133 #define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5134 #define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5135 #define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5136 #define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5137
Yassinetaouil 46:b1a9de66ecab 5138 /* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5139 #define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5140 #define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5141 #define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5142 #define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5143 #define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5144
Yassinetaouil 46:b1a9de66ecab 5145 /* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
Yassinetaouil 46:b1a9de66ecab 5146 #define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5147 #define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5148 #define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5149 #define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5150 #define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5151
Yassinetaouil 46:b1a9de66ecab 5152 /* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
Yassinetaouil 46:b1a9de66ecab 5153 #define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5154 #define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5155 #define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5156 #define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5157 #define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5158
Yassinetaouil 46:b1a9de66ecab 5159 /* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
Yassinetaouil 46:b1a9de66ecab 5160 #define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5161 #define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5162 #define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5163 #define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5164 #define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5165
Yassinetaouil 46:b1a9de66ecab 5166 /* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
Yassinetaouil 46:b1a9de66ecab 5167 #define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5168 #define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5169 #define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5170 #define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5171 #define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5172
Yassinetaouil 46:b1a9de66ecab 5173 /* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5174 #define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5175 #define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5176 #define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5177 #define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5178 #define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5179
Yassinetaouil 46:b1a9de66ecab 5180 /* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5181 #define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5182 #define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5183 #define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5184 #define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5185 #define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5186
Yassinetaouil 46:b1a9de66ecab 5187 /* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5188 #define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5189 #define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5190 #define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5191 #define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5192 #define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5193
Yassinetaouil 46:b1a9de66ecab 5194 /* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5195 #define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5196 #define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5197 #define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5198 #define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5199 #define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5200
Yassinetaouil 46:b1a9de66ecab 5201 /* Register: MWU_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 5202 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 5203
Yassinetaouil 46:b1a9de66ecab 5204 /* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5205 #define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5206 #define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5207 #define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5208 #define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5209 #define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5210
Yassinetaouil 46:b1a9de66ecab 5211 /* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5212 #define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5213 #define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5214 #define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5215 #define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5216 #define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5217
Yassinetaouil 46:b1a9de66ecab 5218 /* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5219 #define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5220 #define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5221 #define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5222 #define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5223 #define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5224
Yassinetaouil 46:b1a9de66ecab 5225 /* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5226 #define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5227 #define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5228 #define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5229 #define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5230 #define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5231
Yassinetaouil 46:b1a9de66ecab 5232 /* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
Yassinetaouil 46:b1a9de66ecab 5233 #define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5234 #define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5235 #define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5236 #define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5237 #define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5238
Yassinetaouil 46:b1a9de66ecab 5239 /* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
Yassinetaouil 46:b1a9de66ecab 5240 #define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5241 #define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5242 #define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5243 #define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5244 #define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5245
Yassinetaouil 46:b1a9de66ecab 5246 /* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
Yassinetaouil 46:b1a9de66ecab 5247 #define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5248 #define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5249 #define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5250 #define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5251 #define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5252
Yassinetaouil 46:b1a9de66ecab 5253 /* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
Yassinetaouil 46:b1a9de66ecab 5254 #define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5255 #define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5256 #define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5257 #define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5258 #define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5259
Yassinetaouil 46:b1a9de66ecab 5260 /* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5261 #define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5262 #define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5263 #define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5264 #define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5265 #define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5266
Yassinetaouil 46:b1a9de66ecab 5267 /* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5268 #define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5269 #define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5270 #define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5271 #define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5272 #define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5273
Yassinetaouil 46:b1a9de66ecab 5274 /* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5275 #define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5276 #define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5277 #define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5278 #define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5279 #define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5280
Yassinetaouil 46:b1a9de66ecab 5281 /* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5282 #define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5283 #define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5284 #define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5285 #define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5286 #define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5287
Yassinetaouil 46:b1a9de66ecab 5288 /* Register: MWU_NMIEN */
Yassinetaouil 46:b1a9de66ecab 5289 /* Description: Enable or disable non-maskable interrupt */
Yassinetaouil 46:b1a9de66ecab 5290
Yassinetaouil 46:b1a9de66ecab 5291 /* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5292 #define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5293 #define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5294 #define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5295 #define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5296
Yassinetaouil 46:b1a9de66ecab 5297 /* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5298 #define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5299 #define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5300 #define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5301 #define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5302
Yassinetaouil 46:b1a9de66ecab 5303 /* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5304 #define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5305 #define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5306 #define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5307 #define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5308
Yassinetaouil 46:b1a9de66ecab 5309 /* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5310 #define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5311 #define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5312 #define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5313 #define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5314
Yassinetaouil 46:b1a9de66ecab 5315 /* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
Yassinetaouil 46:b1a9de66ecab 5316 #define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5317 #define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5318 #define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5319 #define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5320
Yassinetaouil 46:b1a9de66ecab 5321 /* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
Yassinetaouil 46:b1a9de66ecab 5322 #define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5323 #define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5324 #define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5325 #define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5326
Yassinetaouil 46:b1a9de66ecab 5327 /* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
Yassinetaouil 46:b1a9de66ecab 5328 #define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5329 #define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5330 #define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5331 #define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5332
Yassinetaouil 46:b1a9de66ecab 5333 /* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
Yassinetaouil 46:b1a9de66ecab 5334 #define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5335 #define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5336 #define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5337 #define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5338
Yassinetaouil 46:b1a9de66ecab 5339 /* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5340 #define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5341 #define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5342 #define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5343 #define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5344
Yassinetaouil 46:b1a9de66ecab 5345 /* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5346 #define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5347 #define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5348 #define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5349 #define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5350
Yassinetaouil 46:b1a9de66ecab 5351 /* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5352 #define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5353 #define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5354 #define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5355 #define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5356
Yassinetaouil 46:b1a9de66ecab 5357 /* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5358 #define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5359 #define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5360 #define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5361 #define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5362
Yassinetaouil 46:b1a9de66ecab 5363 /* Register: MWU_NMIENSET */
Yassinetaouil 46:b1a9de66ecab 5364 /* Description: Enable non-maskable interrupt */
Yassinetaouil 46:b1a9de66ecab 5365
Yassinetaouil 46:b1a9de66ecab 5366 /* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5367 #define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5368 #define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5369 #define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5370 #define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5371 #define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5372
Yassinetaouil 46:b1a9de66ecab 5373 /* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5374 #define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5375 #define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5376 #define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5377 #define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5378 #define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5379
Yassinetaouil 46:b1a9de66ecab 5380 /* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5381 #define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5382 #define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5383 #define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5384 #define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5385 #define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5386
Yassinetaouil 46:b1a9de66ecab 5387 /* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5388 #define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5389 #define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5390 #define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5391 #define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5392 #define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5393
Yassinetaouil 46:b1a9de66ecab 5394 /* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
Yassinetaouil 46:b1a9de66ecab 5395 #define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5396 #define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5397 #define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5398 #define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5399 #define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5400
Yassinetaouil 46:b1a9de66ecab 5401 /* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
Yassinetaouil 46:b1a9de66ecab 5402 #define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5403 #define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5404 #define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5405 #define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5406 #define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5407
Yassinetaouil 46:b1a9de66ecab 5408 /* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
Yassinetaouil 46:b1a9de66ecab 5409 #define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5410 #define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5411 #define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5412 #define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5413 #define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5414
Yassinetaouil 46:b1a9de66ecab 5415 /* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
Yassinetaouil 46:b1a9de66ecab 5416 #define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5417 #define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5418 #define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5419 #define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5420 #define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5421
Yassinetaouil 46:b1a9de66ecab 5422 /* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5423 #define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5424 #define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5425 #define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5426 #define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5427 #define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5428
Yassinetaouil 46:b1a9de66ecab 5429 /* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5430 #define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5431 #define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5432 #define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5433 #define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5434 #define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5435
Yassinetaouil 46:b1a9de66ecab 5436 /* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5437 #define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5438 #define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5439 #define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5440 #define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5441 #define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5442
Yassinetaouil 46:b1a9de66ecab 5443 /* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5444 #define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5445 #define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5446 #define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5447 #define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5448 #define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 5449
Yassinetaouil 46:b1a9de66ecab 5450 /* Register: MWU_NMIENCLR */
Yassinetaouil 46:b1a9de66ecab 5451 /* Description: Disable non-maskable interrupt */
Yassinetaouil 46:b1a9de66ecab 5452
Yassinetaouil 46:b1a9de66ecab 5453 /* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5454 #define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5455 #define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5456 #define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5457 #define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5458 #define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5459
Yassinetaouil 46:b1a9de66ecab 5460 /* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5461 #define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5462 #define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5463 #define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5464 #define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5465 #define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5466
Yassinetaouil 46:b1a9de66ecab 5467 /* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5468 #define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5469 #define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5470 #define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5471 #define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5472 #define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5473
Yassinetaouil 46:b1a9de66ecab 5474 /* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5475 #define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5476 #define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5477 #define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5478 #define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5479 #define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5480
Yassinetaouil 46:b1a9de66ecab 5481 /* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
Yassinetaouil 46:b1a9de66ecab 5482 #define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5483 #define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
Yassinetaouil 46:b1a9de66ecab 5484 #define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5485 #define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5486 #define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5487
Yassinetaouil 46:b1a9de66ecab 5488 /* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
Yassinetaouil 46:b1a9de66ecab 5489 #define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5490 #define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
Yassinetaouil 46:b1a9de66ecab 5491 #define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5492 #define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5493 #define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5494
Yassinetaouil 46:b1a9de66ecab 5495 /* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
Yassinetaouil 46:b1a9de66ecab 5496 #define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5497 #define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
Yassinetaouil 46:b1a9de66ecab 5498 #define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5499 #define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5500 #define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5501
Yassinetaouil 46:b1a9de66ecab 5502 /* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
Yassinetaouil 46:b1a9de66ecab 5503 #define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5504 #define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
Yassinetaouil 46:b1a9de66ecab 5505 #define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5506 #define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5507 #define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5508
Yassinetaouil 46:b1a9de66ecab 5509 /* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
Yassinetaouil 46:b1a9de66ecab 5510 #define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5511 #define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
Yassinetaouil 46:b1a9de66ecab 5512 #define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5513 #define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5514 #define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5515
Yassinetaouil 46:b1a9de66ecab 5516 /* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
Yassinetaouil 46:b1a9de66ecab 5517 #define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5518 #define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
Yassinetaouil 46:b1a9de66ecab 5519 #define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5520 #define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5521 #define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5522
Yassinetaouil 46:b1a9de66ecab 5523 /* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
Yassinetaouil 46:b1a9de66ecab 5524 #define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5525 #define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
Yassinetaouil 46:b1a9de66ecab 5526 #define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5527 #define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5528 #define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5529
Yassinetaouil 46:b1a9de66ecab 5530 /* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
Yassinetaouil 46:b1a9de66ecab 5531 #define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5532 #define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
Yassinetaouil 46:b1a9de66ecab 5533 #define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 5534 #define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 5535 #define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 5536
Yassinetaouil 46:b1a9de66ecab 5537 /* Register: MWU_PERREGION_SUBSTATWA */
Yassinetaouil 46:b1a9de66ecab 5538 /* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
Yassinetaouil 46:b1a9de66ecab 5539
Yassinetaouil 46:b1a9de66ecab 5540 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5541 #define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
Yassinetaouil 46:b1a9de66ecab 5542 #define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
Yassinetaouil 46:b1a9de66ecab 5543 #define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5544 #define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5545
Yassinetaouil 46:b1a9de66ecab 5546 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5547 #define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
Yassinetaouil 46:b1a9de66ecab 5548 #define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
Yassinetaouil 46:b1a9de66ecab 5549 #define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5550 #define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5551
Yassinetaouil 46:b1a9de66ecab 5552 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5553 #define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
Yassinetaouil 46:b1a9de66ecab 5554 #define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
Yassinetaouil 46:b1a9de66ecab 5555 #define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5556 #define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5557
Yassinetaouil 46:b1a9de66ecab 5558 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5559 #define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
Yassinetaouil 46:b1a9de66ecab 5560 #define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
Yassinetaouil 46:b1a9de66ecab 5561 #define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5562 #define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5563
Yassinetaouil 46:b1a9de66ecab 5564 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5565 #define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
Yassinetaouil 46:b1a9de66ecab 5566 #define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
Yassinetaouil 46:b1a9de66ecab 5567 #define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5568 #define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5569
Yassinetaouil 46:b1a9de66ecab 5570 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5571 #define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
Yassinetaouil 46:b1a9de66ecab 5572 #define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
Yassinetaouil 46:b1a9de66ecab 5573 #define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5574 #define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5575
Yassinetaouil 46:b1a9de66ecab 5576 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5577 #define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
Yassinetaouil 46:b1a9de66ecab 5578 #define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
Yassinetaouil 46:b1a9de66ecab 5579 #define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5580 #define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5581
Yassinetaouil 46:b1a9de66ecab 5582 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5583 #define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
Yassinetaouil 46:b1a9de66ecab 5584 #define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
Yassinetaouil 46:b1a9de66ecab 5585 #define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5586 #define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5587
Yassinetaouil 46:b1a9de66ecab 5588 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5589 #define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
Yassinetaouil 46:b1a9de66ecab 5590 #define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
Yassinetaouil 46:b1a9de66ecab 5591 #define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5592 #define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5593
Yassinetaouil 46:b1a9de66ecab 5594 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5595 #define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
Yassinetaouil 46:b1a9de66ecab 5596 #define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
Yassinetaouil 46:b1a9de66ecab 5597 #define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5598 #define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5599
Yassinetaouil 46:b1a9de66ecab 5600 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5601 #define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
Yassinetaouil 46:b1a9de66ecab 5602 #define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
Yassinetaouil 46:b1a9de66ecab 5603 #define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5604 #define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5605
Yassinetaouil 46:b1a9de66ecab 5606 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5607 #define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
Yassinetaouil 46:b1a9de66ecab 5608 #define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
Yassinetaouil 46:b1a9de66ecab 5609 #define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5610 #define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5611
Yassinetaouil 46:b1a9de66ecab 5612 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5613 #define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
Yassinetaouil 46:b1a9de66ecab 5614 #define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
Yassinetaouil 46:b1a9de66ecab 5615 #define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5616 #define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5617
Yassinetaouil 46:b1a9de66ecab 5618 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5619 #define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
Yassinetaouil 46:b1a9de66ecab 5620 #define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
Yassinetaouil 46:b1a9de66ecab 5621 #define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5622 #define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5623
Yassinetaouil 46:b1a9de66ecab 5624 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5625 #define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
Yassinetaouil 46:b1a9de66ecab 5626 #define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
Yassinetaouil 46:b1a9de66ecab 5627 #define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5628 #define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5629
Yassinetaouil 46:b1a9de66ecab 5630 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5631 #define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
Yassinetaouil 46:b1a9de66ecab 5632 #define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
Yassinetaouil 46:b1a9de66ecab 5633 #define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5634 #define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5635
Yassinetaouil 46:b1a9de66ecab 5636 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5637 #define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
Yassinetaouil 46:b1a9de66ecab 5638 #define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
Yassinetaouil 46:b1a9de66ecab 5639 #define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5640 #define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5641
Yassinetaouil 46:b1a9de66ecab 5642 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5643 #define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
Yassinetaouil 46:b1a9de66ecab 5644 #define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
Yassinetaouil 46:b1a9de66ecab 5645 #define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5646 #define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5647
Yassinetaouil 46:b1a9de66ecab 5648 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5649 #define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
Yassinetaouil 46:b1a9de66ecab 5650 #define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
Yassinetaouil 46:b1a9de66ecab 5651 #define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5652 #define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5653
Yassinetaouil 46:b1a9de66ecab 5654 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5655 #define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
Yassinetaouil 46:b1a9de66ecab 5656 #define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
Yassinetaouil 46:b1a9de66ecab 5657 #define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5658 #define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5659
Yassinetaouil 46:b1a9de66ecab 5660 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5661 #define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
Yassinetaouil 46:b1a9de66ecab 5662 #define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
Yassinetaouil 46:b1a9de66ecab 5663 #define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5664 #define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5665
Yassinetaouil 46:b1a9de66ecab 5666 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5667 #define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
Yassinetaouil 46:b1a9de66ecab 5668 #define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
Yassinetaouil 46:b1a9de66ecab 5669 #define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5670 #define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5671
Yassinetaouil 46:b1a9de66ecab 5672 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5673 #define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
Yassinetaouil 46:b1a9de66ecab 5674 #define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
Yassinetaouil 46:b1a9de66ecab 5675 #define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5676 #define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5677
Yassinetaouil 46:b1a9de66ecab 5678 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5679 #define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
Yassinetaouil 46:b1a9de66ecab 5680 #define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
Yassinetaouil 46:b1a9de66ecab 5681 #define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5682 #define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5683
Yassinetaouil 46:b1a9de66ecab 5684 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5685 #define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
Yassinetaouil 46:b1a9de66ecab 5686 #define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
Yassinetaouil 46:b1a9de66ecab 5687 #define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5688 #define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5689
Yassinetaouil 46:b1a9de66ecab 5690 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5691 #define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
Yassinetaouil 46:b1a9de66ecab 5692 #define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
Yassinetaouil 46:b1a9de66ecab 5693 #define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5694 #define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5695
Yassinetaouil 46:b1a9de66ecab 5696 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5697 #define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
Yassinetaouil 46:b1a9de66ecab 5698 #define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
Yassinetaouil 46:b1a9de66ecab 5699 #define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5700 #define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5701
Yassinetaouil 46:b1a9de66ecab 5702 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5703 #define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
Yassinetaouil 46:b1a9de66ecab 5704 #define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
Yassinetaouil 46:b1a9de66ecab 5705 #define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5706 #define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5707
Yassinetaouil 46:b1a9de66ecab 5708 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5709 #define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
Yassinetaouil 46:b1a9de66ecab 5710 #define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
Yassinetaouil 46:b1a9de66ecab 5711 #define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5712 #define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5713
Yassinetaouil 46:b1a9de66ecab 5714 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5715 #define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
Yassinetaouil 46:b1a9de66ecab 5716 #define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
Yassinetaouil 46:b1a9de66ecab 5717 #define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5718 #define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5719
Yassinetaouil 46:b1a9de66ecab 5720 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5721 #define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
Yassinetaouil 46:b1a9de66ecab 5722 #define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
Yassinetaouil 46:b1a9de66ecab 5723 #define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5724 #define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5725
Yassinetaouil 46:b1a9de66ecab 5726 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5727 #define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
Yassinetaouil 46:b1a9de66ecab 5728 #define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
Yassinetaouil 46:b1a9de66ecab 5729 #define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5730 #define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5731
Yassinetaouil 46:b1a9de66ecab 5732 /* Register: MWU_PERREGION_SUBSTATRA */
Yassinetaouil 46:b1a9de66ecab 5733 /* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
Yassinetaouil 46:b1a9de66ecab 5734
Yassinetaouil 46:b1a9de66ecab 5735 /* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5736 #define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
Yassinetaouil 46:b1a9de66ecab 5737 #define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
Yassinetaouil 46:b1a9de66ecab 5738 #define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5739 #define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5740
Yassinetaouil 46:b1a9de66ecab 5741 /* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5742 #define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
Yassinetaouil 46:b1a9de66ecab 5743 #define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
Yassinetaouil 46:b1a9de66ecab 5744 #define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5745 #define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5746
Yassinetaouil 46:b1a9de66ecab 5747 /* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5748 #define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
Yassinetaouil 46:b1a9de66ecab 5749 #define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
Yassinetaouil 46:b1a9de66ecab 5750 #define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5751 #define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5752
Yassinetaouil 46:b1a9de66ecab 5753 /* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5754 #define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
Yassinetaouil 46:b1a9de66ecab 5755 #define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
Yassinetaouil 46:b1a9de66ecab 5756 #define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5757 #define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5758
Yassinetaouil 46:b1a9de66ecab 5759 /* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5760 #define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
Yassinetaouil 46:b1a9de66ecab 5761 #define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
Yassinetaouil 46:b1a9de66ecab 5762 #define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5763 #define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5764
Yassinetaouil 46:b1a9de66ecab 5765 /* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5766 #define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
Yassinetaouil 46:b1a9de66ecab 5767 #define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
Yassinetaouil 46:b1a9de66ecab 5768 #define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5769 #define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5770
Yassinetaouil 46:b1a9de66ecab 5771 /* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5772 #define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
Yassinetaouil 46:b1a9de66ecab 5773 #define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
Yassinetaouil 46:b1a9de66ecab 5774 #define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5775 #define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5776
Yassinetaouil 46:b1a9de66ecab 5777 /* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5778 #define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
Yassinetaouil 46:b1a9de66ecab 5779 #define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
Yassinetaouil 46:b1a9de66ecab 5780 #define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5781 #define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5782
Yassinetaouil 46:b1a9de66ecab 5783 /* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5784 #define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
Yassinetaouil 46:b1a9de66ecab 5785 #define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
Yassinetaouil 46:b1a9de66ecab 5786 #define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5787 #define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5788
Yassinetaouil 46:b1a9de66ecab 5789 /* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5790 #define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
Yassinetaouil 46:b1a9de66ecab 5791 #define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
Yassinetaouil 46:b1a9de66ecab 5792 #define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5793 #define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5794
Yassinetaouil 46:b1a9de66ecab 5795 /* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5796 #define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
Yassinetaouil 46:b1a9de66ecab 5797 #define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
Yassinetaouil 46:b1a9de66ecab 5798 #define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5799 #define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5800
Yassinetaouil 46:b1a9de66ecab 5801 /* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5802 #define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
Yassinetaouil 46:b1a9de66ecab 5803 #define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
Yassinetaouil 46:b1a9de66ecab 5804 #define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5805 #define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5806
Yassinetaouil 46:b1a9de66ecab 5807 /* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5808 #define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
Yassinetaouil 46:b1a9de66ecab 5809 #define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
Yassinetaouil 46:b1a9de66ecab 5810 #define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5811 #define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5812
Yassinetaouil 46:b1a9de66ecab 5813 /* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5814 #define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
Yassinetaouil 46:b1a9de66ecab 5815 #define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
Yassinetaouil 46:b1a9de66ecab 5816 #define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5817 #define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5818
Yassinetaouil 46:b1a9de66ecab 5819 /* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5820 #define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
Yassinetaouil 46:b1a9de66ecab 5821 #define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
Yassinetaouil 46:b1a9de66ecab 5822 #define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5823 #define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5824
Yassinetaouil 46:b1a9de66ecab 5825 /* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5826 #define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
Yassinetaouil 46:b1a9de66ecab 5827 #define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
Yassinetaouil 46:b1a9de66ecab 5828 #define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5829 #define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5830
Yassinetaouil 46:b1a9de66ecab 5831 /* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5832 #define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
Yassinetaouil 46:b1a9de66ecab 5833 #define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
Yassinetaouil 46:b1a9de66ecab 5834 #define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5835 #define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5836
Yassinetaouil 46:b1a9de66ecab 5837 /* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5838 #define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
Yassinetaouil 46:b1a9de66ecab 5839 #define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
Yassinetaouil 46:b1a9de66ecab 5840 #define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5841 #define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5842
Yassinetaouil 46:b1a9de66ecab 5843 /* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5844 #define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
Yassinetaouil 46:b1a9de66ecab 5845 #define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
Yassinetaouil 46:b1a9de66ecab 5846 #define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5847 #define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5848
Yassinetaouil 46:b1a9de66ecab 5849 /* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5850 #define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
Yassinetaouil 46:b1a9de66ecab 5851 #define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
Yassinetaouil 46:b1a9de66ecab 5852 #define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5853 #define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5854
Yassinetaouil 46:b1a9de66ecab 5855 /* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5856 #define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
Yassinetaouil 46:b1a9de66ecab 5857 #define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
Yassinetaouil 46:b1a9de66ecab 5858 #define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5859 #define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5860
Yassinetaouil 46:b1a9de66ecab 5861 /* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5862 #define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
Yassinetaouil 46:b1a9de66ecab 5863 #define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
Yassinetaouil 46:b1a9de66ecab 5864 #define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5865 #define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5866
Yassinetaouil 46:b1a9de66ecab 5867 /* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5868 #define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
Yassinetaouil 46:b1a9de66ecab 5869 #define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
Yassinetaouil 46:b1a9de66ecab 5870 #define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5871 #define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5872
Yassinetaouil 46:b1a9de66ecab 5873 /* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5874 #define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
Yassinetaouil 46:b1a9de66ecab 5875 #define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
Yassinetaouil 46:b1a9de66ecab 5876 #define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5877 #define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5878
Yassinetaouil 46:b1a9de66ecab 5879 /* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5880 #define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
Yassinetaouil 46:b1a9de66ecab 5881 #define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
Yassinetaouil 46:b1a9de66ecab 5882 #define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5883 #define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5884
Yassinetaouil 46:b1a9de66ecab 5885 /* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5886 #define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
Yassinetaouil 46:b1a9de66ecab 5887 #define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
Yassinetaouil 46:b1a9de66ecab 5888 #define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5889 #define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5890
Yassinetaouil 46:b1a9de66ecab 5891 /* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5892 #define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
Yassinetaouil 46:b1a9de66ecab 5893 #define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
Yassinetaouil 46:b1a9de66ecab 5894 #define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5895 #define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5896
Yassinetaouil 46:b1a9de66ecab 5897 /* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5898 #define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
Yassinetaouil 46:b1a9de66ecab 5899 #define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
Yassinetaouil 46:b1a9de66ecab 5900 #define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5901 #define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5902
Yassinetaouil 46:b1a9de66ecab 5903 /* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5904 #define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
Yassinetaouil 46:b1a9de66ecab 5905 #define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
Yassinetaouil 46:b1a9de66ecab 5906 #define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5907 #define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5908
Yassinetaouil 46:b1a9de66ecab 5909 /* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5910 #define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
Yassinetaouil 46:b1a9de66ecab 5911 #define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
Yassinetaouil 46:b1a9de66ecab 5912 #define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5913 #define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5914
Yassinetaouil 46:b1a9de66ecab 5915 /* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5916 #define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
Yassinetaouil 46:b1a9de66ecab 5917 #define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
Yassinetaouil 46:b1a9de66ecab 5918 #define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5919 #define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5920
Yassinetaouil 46:b1a9de66ecab 5921 /* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 5922 #define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
Yassinetaouil 46:b1a9de66ecab 5923 #define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
Yassinetaouil 46:b1a9de66ecab 5924 #define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5925 #define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
Yassinetaouil 46:b1a9de66ecab 5926
Yassinetaouil 46:b1a9de66ecab 5927 /* Register: MWU_REGIONEN */
Yassinetaouil 46:b1a9de66ecab 5928 /* Description: Enable/disable regions watch */
Yassinetaouil 46:b1a9de66ecab 5929
Yassinetaouil 46:b1a9de66ecab 5930 /* Bit 27 : Enable/disable read access watch in PREGION[1] */
Yassinetaouil 46:b1a9de66ecab 5931 #define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 5932 #define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 5933 #define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 5934 #define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 5935
Yassinetaouil 46:b1a9de66ecab 5936 /* Bit 26 : Enable/disable write access watch in PREGION[1] */
Yassinetaouil 46:b1a9de66ecab 5937 #define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 5938 #define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 5939 #define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 5940 #define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 5941
Yassinetaouil 46:b1a9de66ecab 5942 /* Bit 25 : Enable/disable read access watch in PREGION[0] */
Yassinetaouil 46:b1a9de66ecab 5943 #define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 5944 #define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 5945 #define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 5946 #define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 5947
Yassinetaouil 46:b1a9de66ecab 5948 /* Bit 24 : Enable/disable write access watch in PREGION[0] */
Yassinetaouil 46:b1a9de66ecab 5949 #define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 5950 #define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 5951 #define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 5952 #define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 5953
Yassinetaouil 46:b1a9de66ecab 5954 /* Bit 7 : Enable/disable read access watch in region[3] */
Yassinetaouil 46:b1a9de66ecab 5955 #define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
Yassinetaouil 46:b1a9de66ecab 5956 #define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
Yassinetaouil 46:b1a9de66ecab 5957 #define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5958 #define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5959
Yassinetaouil 46:b1a9de66ecab 5960 /* Bit 6 : Enable/disable write access watch in region[3] */
Yassinetaouil 46:b1a9de66ecab 5961 #define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
Yassinetaouil 46:b1a9de66ecab 5962 #define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
Yassinetaouil 46:b1a9de66ecab 5963 #define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5964 #define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5965
Yassinetaouil 46:b1a9de66ecab 5966 /* Bit 5 : Enable/disable read access watch in region[2] */
Yassinetaouil 46:b1a9de66ecab 5967 #define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
Yassinetaouil 46:b1a9de66ecab 5968 #define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
Yassinetaouil 46:b1a9de66ecab 5969 #define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5970 #define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5971
Yassinetaouil 46:b1a9de66ecab 5972 /* Bit 4 : Enable/disable write access watch in region[2] */
Yassinetaouil 46:b1a9de66ecab 5973 #define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
Yassinetaouil 46:b1a9de66ecab 5974 #define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
Yassinetaouil 46:b1a9de66ecab 5975 #define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5976 #define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5977
Yassinetaouil 46:b1a9de66ecab 5978 /* Bit 3 : Enable/disable read access watch in region[1] */
Yassinetaouil 46:b1a9de66ecab 5979 #define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 5980 #define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 5981 #define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5982 #define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5983
Yassinetaouil 46:b1a9de66ecab 5984 /* Bit 2 : Enable/disable write access watch in region[1] */
Yassinetaouil 46:b1a9de66ecab 5985 #define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 5986 #define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 5987 #define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5988 #define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5989
Yassinetaouil 46:b1a9de66ecab 5990 /* Bit 1 : Enable/disable read access watch in region[0] */
Yassinetaouil 46:b1a9de66ecab 5991 #define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 5992 #define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 5993 #define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5994 #define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 5995
Yassinetaouil 46:b1a9de66ecab 5996 /* Bit 0 : Enable/disable write access watch in region[0] */
Yassinetaouil 46:b1a9de66ecab 5997 #define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 5998 #define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 5999 #define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6000 #define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6001
Yassinetaouil 46:b1a9de66ecab 6002 /* Register: MWU_REGIONENSET */
Yassinetaouil 46:b1a9de66ecab 6003 /* Description: Enable regions watch */
Yassinetaouil 46:b1a9de66ecab 6004
Yassinetaouil 46:b1a9de66ecab 6005 /* Bit 27 : Enable read access watch in PREGION[1] */
Yassinetaouil 46:b1a9de66ecab 6006 #define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 6007 #define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 6008 #define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
Yassinetaouil 46:b1a9de66ecab 6009 #define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
Yassinetaouil 46:b1a9de66ecab 6010 #define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 6011
Yassinetaouil 46:b1a9de66ecab 6012 /* Bit 26 : Enable write access watch in PREGION[1] */
Yassinetaouil 46:b1a9de66ecab 6013 #define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 6014 #define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 6015 #define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
Yassinetaouil 46:b1a9de66ecab 6016 #define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
Yassinetaouil 46:b1a9de66ecab 6017 #define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 6018
Yassinetaouil 46:b1a9de66ecab 6019 /* Bit 25 : Enable read access watch in PREGION[0] */
Yassinetaouil 46:b1a9de66ecab 6020 #define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 6021 #define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 6022 #define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
Yassinetaouil 46:b1a9de66ecab 6023 #define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
Yassinetaouil 46:b1a9de66ecab 6024 #define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 6025
Yassinetaouil 46:b1a9de66ecab 6026 /* Bit 24 : Enable write access watch in PREGION[0] */
Yassinetaouil 46:b1a9de66ecab 6027 #define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 6028 #define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 6029 #define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
Yassinetaouil 46:b1a9de66ecab 6030 #define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
Yassinetaouil 46:b1a9de66ecab 6031 #define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 6032
Yassinetaouil 46:b1a9de66ecab 6033 /* Bit 7 : Enable read access watch in region[3] */
Yassinetaouil 46:b1a9de66ecab 6034 #define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
Yassinetaouil 46:b1a9de66ecab 6035 #define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
Yassinetaouil 46:b1a9de66ecab 6036 #define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6037 #define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6038 #define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6039
Yassinetaouil 46:b1a9de66ecab 6040 /* Bit 6 : Enable write access watch in region[3] */
Yassinetaouil 46:b1a9de66ecab 6041 #define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
Yassinetaouil 46:b1a9de66ecab 6042 #define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
Yassinetaouil 46:b1a9de66ecab 6043 #define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6044 #define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6045 #define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6046
Yassinetaouil 46:b1a9de66ecab 6047 /* Bit 5 : Enable read access watch in region[2] */
Yassinetaouil 46:b1a9de66ecab 6048 #define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
Yassinetaouil 46:b1a9de66ecab 6049 #define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
Yassinetaouil 46:b1a9de66ecab 6050 #define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6051 #define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6052 #define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6053
Yassinetaouil 46:b1a9de66ecab 6054 /* Bit 4 : Enable write access watch in region[2] */
Yassinetaouil 46:b1a9de66ecab 6055 #define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
Yassinetaouil 46:b1a9de66ecab 6056 #define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
Yassinetaouil 46:b1a9de66ecab 6057 #define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6058 #define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6059 #define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6060
Yassinetaouil 46:b1a9de66ecab 6061 /* Bit 3 : Enable read access watch in region[1] */
Yassinetaouil 46:b1a9de66ecab 6062 #define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 6063 #define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 6064 #define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6065 #define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6066 #define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6067
Yassinetaouil 46:b1a9de66ecab 6068 /* Bit 2 : Enable write access watch in region[1] */
Yassinetaouil 46:b1a9de66ecab 6069 #define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 6070 #define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 6071 #define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6072 #define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6073 #define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6074
Yassinetaouil 46:b1a9de66ecab 6075 /* Bit 1 : Enable read access watch in region[0] */
Yassinetaouil 46:b1a9de66ecab 6076 #define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 6077 #define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 6078 #define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6079 #define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6080 #define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6081
Yassinetaouil 46:b1a9de66ecab 6082 /* Bit 0 : Enable write access watch in region[0] */
Yassinetaouil 46:b1a9de66ecab 6083 #define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 6084 #define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 6085 #define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6086 #define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6087 #define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6088
Yassinetaouil 46:b1a9de66ecab 6089 /* Register: MWU_REGIONENCLR */
Yassinetaouil 46:b1a9de66ecab 6090 /* Description: Disable regions watch */
Yassinetaouil 46:b1a9de66ecab 6091
Yassinetaouil 46:b1a9de66ecab 6092 /* Bit 27 : Disable read access watch in PREGION[1] */
Yassinetaouil 46:b1a9de66ecab 6093 #define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 6094 #define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 6095 #define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
Yassinetaouil 46:b1a9de66ecab 6096 #define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
Yassinetaouil 46:b1a9de66ecab 6097 #define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 6098
Yassinetaouil 46:b1a9de66ecab 6099 /* Bit 26 : Disable write access watch in PREGION[1] */
Yassinetaouil 46:b1a9de66ecab 6100 #define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 6101 #define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 6102 #define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
Yassinetaouil 46:b1a9de66ecab 6103 #define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
Yassinetaouil 46:b1a9de66ecab 6104 #define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 6105
Yassinetaouil 46:b1a9de66ecab 6106 /* Bit 25 : Disable read access watch in PREGION[0] */
Yassinetaouil 46:b1a9de66ecab 6107 #define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 6108 #define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 6109 #define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
Yassinetaouil 46:b1a9de66ecab 6110 #define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
Yassinetaouil 46:b1a9de66ecab 6111 #define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 6112
Yassinetaouil 46:b1a9de66ecab 6113 /* Bit 24 : Disable write access watch in PREGION[0] */
Yassinetaouil 46:b1a9de66ecab 6114 #define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 6115 #define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 6116 #define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
Yassinetaouil 46:b1a9de66ecab 6117 #define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
Yassinetaouil 46:b1a9de66ecab 6118 #define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
Yassinetaouil 46:b1a9de66ecab 6119
Yassinetaouil 46:b1a9de66ecab 6120 /* Bit 7 : Disable read access watch in region[3] */
Yassinetaouil 46:b1a9de66ecab 6121 #define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
Yassinetaouil 46:b1a9de66ecab 6122 #define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
Yassinetaouil 46:b1a9de66ecab 6123 #define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6124 #define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6125 #define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6126
Yassinetaouil 46:b1a9de66ecab 6127 /* Bit 6 : Disable write access watch in region[3] */
Yassinetaouil 46:b1a9de66ecab 6128 #define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
Yassinetaouil 46:b1a9de66ecab 6129 #define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
Yassinetaouil 46:b1a9de66ecab 6130 #define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6131 #define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6132 #define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6133
Yassinetaouil 46:b1a9de66ecab 6134 /* Bit 5 : Disable read access watch in region[2] */
Yassinetaouil 46:b1a9de66ecab 6135 #define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
Yassinetaouil 46:b1a9de66ecab 6136 #define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
Yassinetaouil 46:b1a9de66ecab 6137 #define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6138 #define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6139 #define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6140
Yassinetaouil 46:b1a9de66ecab 6141 /* Bit 4 : Disable write access watch in region[2] */
Yassinetaouil 46:b1a9de66ecab 6142 #define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
Yassinetaouil 46:b1a9de66ecab 6143 #define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
Yassinetaouil 46:b1a9de66ecab 6144 #define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6145 #define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6146 #define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6147
Yassinetaouil 46:b1a9de66ecab 6148 /* Bit 3 : Disable read access watch in region[1] */
Yassinetaouil 46:b1a9de66ecab 6149 #define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 6150 #define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
Yassinetaouil 46:b1a9de66ecab 6151 #define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6152 #define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6153 #define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6154
Yassinetaouil 46:b1a9de66ecab 6155 /* Bit 2 : Disable write access watch in region[1] */
Yassinetaouil 46:b1a9de66ecab 6156 #define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 6157 #define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
Yassinetaouil 46:b1a9de66ecab 6158 #define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6159 #define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6160 #define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6161
Yassinetaouil 46:b1a9de66ecab 6162 /* Bit 1 : Disable read access watch in region[0] */
Yassinetaouil 46:b1a9de66ecab 6163 #define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 6164 #define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
Yassinetaouil 46:b1a9de66ecab 6165 #define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6166 #define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6167 #define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6168
Yassinetaouil 46:b1a9de66ecab 6169 /* Bit 0 : Disable write access watch in region[0] */
Yassinetaouil 46:b1a9de66ecab 6170 #define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 6171 #define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
Yassinetaouil 46:b1a9de66ecab 6172 #define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
Yassinetaouil 46:b1a9de66ecab 6173 #define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
Yassinetaouil 46:b1a9de66ecab 6174 #define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
Yassinetaouil 46:b1a9de66ecab 6175
Yassinetaouil 46:b1a9de66ecab 6176 /* Register: MWU_REGION_START */
Yassinetaouil 46:b1a9de66ecab 6177 /* Description: Description cluster[0]: Start address for region 0 */
Yassinetaouil 46:b1a9de66ecab 6178
Yassinetaouil 46:b1a9de66ecab 6179 /* Bits 31..0 : Start address for region */
Yassinetaouil 46:b1a9de66ecab 6180 #define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
Yassinetaouil 46:b1a9de66ecab 6181 #define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
Yassinetaouil 46:b1a9de66ecab 6182
Yassinetaouil 46:b1a9de66ecab 6183 /* Register: MWU_REGION_END */
Yassinetaouil 46:b1a9de66ecab 6184 /* Description: Description cluster[0]: End address of region 0 */
Yassinetaouil 46:b1a9de66ecab 6185
Yassinetaouil 46:b1a9de66ecab 6186 /* Bits 31..0 : End address of region. */
Yassinetaouil 46:b1a9de66ecab 6187 #define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 6188 #define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 6189
Yassinetaouil 46:b1a9de66ecab 6190 /* Register: MWU_PREGION_START */
Yassinetaouil 46:b1a9de66ecab 6191 /* Description: Description cluster[0]: Reserved for future use */
Yassinetaouil 46:b1a9de66ecab 6192
Yassinetaouil 46:b1a9de66ecab 6193 /* Bits 31..0 : Reserved for future use */
Yassinetaouil 46:b1a9de66ecab 6194 #define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
Yassinetaouil 46:b1a9de66ecab 6195 #define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
Yassinetaouil 46:b1a9de66ecab 6196
Yassinetaouil 46:b1a9de66ecab 6197 /* Register: MWU_PREGION_END */
Yassinetaouil 46:b1a9de66ecab 6198 /* Description: Description cluster[0]: Reserved for future use */
Yassinetaouil 46:b1a9de66ecab 6199
Yassinetaouil 46:b1a9de66ecab 6200 /* Bits 31..0 : Reserved for future use */
Yassinetaouil 46:b1a9de66ecab 6201 #define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 6202 #define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 6203
Yassinetaouil 46:b1a9de66ecab 6204 /* Register: MWU_PREGION_SUBS */
Yassinetaouil 46:b1a9de66ecab 6205 /* Description: Description cluster[0]: Subregions of region 0 */
Yassinetaouil 46:b1a9de66ecab 6206
Yassinetaouil 46:b1a9de66ecab 6207 /* Bit 31 : Include or exclude subregion 31 in region */
Yassinetaouil 46:b1a9de66ecab 6208 #define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
Yassinetaouil 46:b1a9de66ecab 6209 #define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
Yassinetaouil 46:b1a9de66ecab 6210 #define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6211 #define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6212
Yassinetaouil 46:b1a9de66ecab 6213 /* Bit 30 : Include or exclude subregion 30 in region */
Yassinetaouil 46:b1a9de66ecab 6214 #define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
Yassinetaouil 46:b1a9de66ecab 6215 #define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
Yassinetaouil 46:b1a9de66ecab 6216 #define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6217 #define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6218
Yassinetaouil 46:b1a9de66ecab 6219 /* Bit 29 : Include or exclude subregion 29 in region */
Yassinetaouil 46:b1a9de66ecab 6220 #define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
Yassinetaouil 46:b1a9de66ecab 6221 #define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
Yassinetaouil 46:b1a9de66ecab 6222 #define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6223 #define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6224
Yassinetaouil 46:b1a9de66ecab 6225 /* Bit 28 : Include or exclude subregion 28 in region */
Yassinetaouil 46:b1a9de66ecab 6226 #define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
Yassinetaouil 46:b1a9de66ecab 6227 #define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
Yassinetaouil 46:b1a9de66ecab 6228 #define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6229 #define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6230
Yassinetaouil 46:b1a9de66ecab 6231 /* Bit 27 : Include or exclude subregion 27 in region */
Yassinetaouil 46:b1a9de66ecab 6232 #define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
Yassinetaouil 46:b1a9de66ecab 6233 #define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
Yassinetaouil 46:b1a9de66ecab 6234 #define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6235 #define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6236
Yassinetaouil 46:b1a9de66ecab 6237 /* Bit 26 : Include or exclude subregion 26 in region */
Yassinetaouil 46:b1a9de66ecab 6238 #define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
Yassinetaouil 46:b1a9de66ecab 6239 #define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
Yassinetaouil 46:b1a9de66ecab 6240 #define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6241 #define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6242
Yassinetaouil 46:b1a9de66ecab 6243 /* Bit 25 : Include or exclude subregion 25 in region */
Yassinetaouil 46:b1a9de66ecab 6244 #define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
Yassinetaouil 46:b1a9de66ecab 6245 #define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
Yassinetaouil 46:b1a9de66ecab 6246 #define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6247 #define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6248
Yassinetaouil 46:b1a9de66ecab 6249 /* Bit 24 : Include or exclude subregion 24 in region */
Yassinetaouil 46:b1a9de66ecab 6250 #define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
Yassinetaouil 46:b1a9de66ecab 6251 #define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
Yassinetaouil 46:b1a9de66ecab 6252 #define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6253 #define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6254
Yassinetaouil 46:b1a9de66ecab 6255 /* Bit 23 : Include or exclude subregion 23 in region */
Yassinetaouil 46:b1a9de66ecab 6256 #define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
Yassinetaouil 46:b1a9de66ecab 6257 #define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
Yassinetaouil 46:b1a9de66ecab 6258 #define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6259 #define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6260
Yassinetaouil 46:b1a9de66ecab 6261 /* Bit 22 : Include or exclude subregion 22 in region */
Yassinetaouil 46:b1a9de66ecab 6262 #define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
Yassinetaouil 46:b1a9de66ecab 6263 #define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
Yassinetaouil 46:b1a9de66ecab 6264 #define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6265 #define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6266
Yassinetaouil 46:b1a9de66ecab 6267 /* Bit 21 : Include or exclude subregion 21 in region */
Yassinetaouil 46:b1a9de66ecab 6268 #define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
Yassinetaouil 46:b1a9de66ecab 6269 #define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
Yassinetaouil 46:b1a9de66ecab 6270 #define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6271 #define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6272
Yassinetaouil 46:b1a9de66ecab 6273 /* Bit 20 : Include or exclude subregion 20 in region */
Yassinetaouil 46:b1a9de66ecab 6274 #define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
Yassinetaouil 46:b1a9de66ecab 6275 #define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
Yassinetaouil 46:b1a9de66ecab 6276 #define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6277 #define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6278
Yassinetaouil 46:b1a9de66ecab 6279 /* Bit 19 : Include or exclude subregion 19 in region */
Yassinetaouil 46:b1a9de66ecab 6280 #define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
Yassinetaouil 46:b1a9de66ecab 6281 #define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
Yassinetaouil 46:b1a9de66ecab 6282 #define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6283 #define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6284
Yassinetaouil 46:b1a9de66ecab 6285 /* Bit 18 : Include or exclude subregion 18 in region */
Yassinetaouil 46:b1a9de66ecab 6286 #define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
Yassinetaouil 46:b1a9de66ecab 6287 #define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
Yassinetaouil 46:b1a9de66ecab 6288 #define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6289 #define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6290
Yassinetaouil 46:b1a9de66ecab 6291 /* Bit 17 : Include or exclude subregion 17 in region */
Yassinetaouil 46:b1a9de66ecab 6292 #define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
Yassinetaouil 46:b1a9de66ecab 6293 #define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
Yassinetaouil 46:b1a9de66ecab 6294 #define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6295 #define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6296
Yassinetaouil 46:b1a9de66ecab 6297 /* Bit 16 : Include or exclude subregion 16 in region */
Yassinetaouil 46:b1a9de66ecab 6298 #define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
Yassinetaouil 46:b1a9de66ecab 6299 #define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
Yassinetaouil 46:b1a9de66ecab 6300 #define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6301 #define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6302
Yassinetaouil 46:b1a9de66ecab 6303 /* Bit 15 : Include or exclude subregion 15 in region */
Yassinetaouil 46:b1a9de66ecab 6304 #define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
Yassinetaouil 46:b1a9de66ecab 6305 #define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
Yassinetaouil 46:b1a9de66ecab 6306 #define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6307 #define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6308
Yassinetaouil 46:b1a9de66ecab 6309 /* Bit 14 : Include or exclude subregion 14 in region */
Yassinetaouil 46:b1a9de66ecab 6310 #define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
Yassinetaouil 46:b1a9de66ecab 6311 #define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
Yassinetaouil 46:b1a9de66ecab 6312 #define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6313 #define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6314
Yassinetaouil 46:b1a9de66ecab 6315 /* Bit 13 : Include or exclude subregion 13 in region */
Yassinetaouil 46:b1a9de66ecab 6316 #define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
Yassinetaouil 46:b1a9de66ecab 6317 #define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
Yassinetaouil 46:b1a9de66ecab 6318 #define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6319 #define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6320
Yassinetaouil 46:b1a9de66ecab 6321 /* Bit 12 : Include or exclude subregion 12 in region */
Yassinetaouil 46:b1a9de66ecab 6322 #define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
Yassinetaouil 46:b1a9de66ecab 6323 #define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
Yassinetaouil 46:b1a9de66ecab 6324 #define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6325 #define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6326
Yassinetaouil 46:b1a9de66ecab 6327 /* Bit 11 : Include or exclude subregion 11 in region */
Yassinetaouil 46:b1a9de66ecab 6328 #define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
Yassinetaouil 46:b1a9de66ecab 6329 #define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
Yassinetaouil 46:b1a9de66ecab 6330 #define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6331 #define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6332
Yassinetaouil 46:b1a9de66ecab 6333 /* Bit 10 : Include or exclude subregion 10 in region */
Yassinetaouil 46:b1a9de66ecab 6334 #define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
Yassinetaouil 46:b1a9de66ecab 6335 #define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
Yassinetaouil 46:b1a9de66ecab 6336 #define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6337 #define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6338
Yassinetaouil 46:b1a9de66ecab 6339 /* Bit 9 : Include or exclude subregion 9 in region */
Yassinetaouil 46:b1a9de66ecab 6340 #define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
Yassinetaouil 46:b1a9de66ecab 6341 #define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
Yassinetaouil 46:b1a9de66ecab 6342 #define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6343 #define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6344
Yassinetaouil 46:b1a9de66ecab 6345 /* Bit 8 : Include or exclude subregion 8 in region */
Yassinetaouil 46:b1a9de66ecab 6346 #define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
Yassinetaouil 46:b1a9de66ecab 6347 #define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
Yassinetaouil 46:b1a9de66ecab 6348 #define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6349 #define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6350
Yassinetaouil 46:b1a9de66ecab 6351 /* Bit 7 : Include or exclude subregion 7 in region */
Yassinetaouil 46:b1a9de66ecab 6352 #define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
Yassinetaouil 46:b1a9de66ecab 6353 #define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
Yassinetaouil 46:b1a9de66ecab 6354 #define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6355 #define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6356
Yassinetaouil 46:b1a9de66ecab 6357 /* Bit 6 : Include or exclude subregion 6 in region */
Yassinetaouil 46:b1a9de66ecab 6358 #define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
Yassinetaouil 46:b1a9de66ecab 6359 #define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
Yassinetaouil 46:b1a9de66ecab 6360 #define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6361 #define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6362
Yassinetaouil 46:b1a9de66ecab 6363 /* Bit 5 : Include or exclude subregion 5 in region */
Yassinetaouil 46:b1a9de66ecab 6364 #define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
Yassinetaouil 46:b1a9de66ecab 6365 #define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
Yassinetaouil 46:b1a9de66ecab 6366 #define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6367 #define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6368
Yassinetaouil 46:b1a9de66ecab 6369 /* Bit 4 : Include or exclude subregion 4 in region */
Yassinetaouil 46:b1a9de66ecab 6370 #define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
Yassinetaouil 46:b1a9de66ecab 6371 #define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
Yassinetaouil 46:b1a9de66ecab 6372 #define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6373 #define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6374
Yassinetaouil 46:b1a9de66ecab 6375 /* Bit 3 : Include or exclude subregion 3 in region */
Yassinetaouil 46:b1a9de66ecab 6376 #define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
Yassinetaouil 46:b1a9de66ecab 6377 #define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
Yassinetaouil 46:b1a9de66ecab 6378 #define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6379 #define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6380
Yassinetaouil 46:b1a9de66ecab 6381 /* Bit 2 : Include or exclude subregion 2 in region */
Yassinetaouil 46:b1a9de66ecab 6382 #define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
Yassinetaouil 46:b1a9de66ecab 6383 #define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
Yassinetaouil 46:b1a9de66ecab 6384 #define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6385 #define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6386
Yassinetaouil 46:b1a9de66ecab 6387 /* Bit 1 : Include or exclude subregion 1 in region */
Yassinetaouil 46:b1a9de66ecab 6388 #define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
Yassinetaouil 46:b1a9de66ecab 6389 #define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
Yassinetaouil 46:b1a9de66ecab 6390 #define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6391 #define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6392
Yassinetaouil 46:b1a9de66ecab 6393 /* Bit 0 : Include or exclude subregion 0 in region */
Yassinetaouil 46:b1a9de66ecab 6394 #define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
Yassinetaouil 46:b1a9de66ecab 6395 #define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
Yassinetaouil 46:b1a9de66ecab 6396 #define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 6397 #define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 6398
Yassinetaouil 46:b1a9de66ecab 6399
Yassinetaouil 46:b1a9de66ecab 6400 /* Peripheral: NFCT */
Yassinetaouil 46:b1a9de66ecab 6401 /* Description: NFC-A compatible radio */
Yassinetaouil 46:b1a9de66ecab 6402
Yassinetaouil 46:b1a9de66ecab 6403 /* Register: NFCT_SHORTS */
Yassinetaouil 46:b1a9de66ecab 6404 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 6405
Yassinetaouil 46:b1a9de66ecab 6406 /* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
Yassinetaouil 46:b1a9de66ecab 6407 #define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
Yassinetaouil 46:b1a9de66ecab 6408 #define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
Yassinetaouil 46:b1a9de66ecab 6409 #define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 6410 #define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 6411
Yassinetaouil 46:b1a9de66ecab 6412 /* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
Yassinetaouil 46:b1a9de66ecab 6413 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
Yassinetaouil 46:b1a9de66ecab 6414 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
Yassinetaouil 46:b1a9de66ecab 6415 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 6416 #define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 6417
Yassinetaouil 46:b1a9de66ecab 6418 /* Register: NFCT_INTEN */
Yassinetaouil 46:b1a9de66ecab 6419 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 6420
Yassinetaouil 46:b1a9de66ecab 6421 /* Bit 20 : Enable or disable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 6422 #define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 6423 #define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 6424 #define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6425 #define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6426
Yassinetaouil 46:b1a9de66ecab 6427 /* Bit 19 : Enable or disable interrupt for SELECTED event */
Yassinetaouil 46:b1a9de66ecab 6428 #define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
Yassinetaouil 46:b1a9de66ecab 6429 #define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
Yassinetaouil 46:b1a9de66ecab 6430 #define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6431 #define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6432
Yassinetaouil 46:b1a9de66ecab 6433 /* Bit 18 : Enable or disable interrupt for COLLISION event */
Yassinetaouil 46:b1a9de66ecab 6434 #define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
Yassinetaouil 46:b1a9de66ecab 6435 #define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
Yassinetaouil 46:b1a9de66ecab 6436 #define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6437 #define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6438
Yassinetaouil 46:b1a9de66ecab 6439 /* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
Yassinetaouil 46:b1a9de66ecab 6440 #define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 6441 #define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 6442 #define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6443 #define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6444
Yassinetaouil 46:b1a9de66ecab 6445 /* Bit 12 : Enable or disable interrupt for ENDTX event */
Yassinetaouil 46:b1a9de66ecab 6446 #define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 6447 #define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 6448 #define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6449 #define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6450
Yassinetaouil 46:b1a9de66ecab 6451 /* Bit 11 : Enable or disable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 6452 #define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 6453 #define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 6454 #define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6455 #define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6456
Yassinetaouil 46:b1a9de66ecab 6457 /* Bit 10 : Enable or disable interrupt for RXERROR event */
Yassinetaouil 46:b1a9de66ecab 6458 #define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
Yassinetaouil 46:b1a9de66ecab 6459 #define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
Yassinetaouil 46:b1a9de66ecab 6460 #define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6461 #define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6462
Yassinetaouil 46:b1a9de66ecab 6463 /* Bit 7 : Enable or disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 6464 #define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 6465 #define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 6466 #define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6467 #define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6468
Yassinetaouil 46:b1a9de66ecab 6469 /* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
Yassinetaouil 46:b1a9de66ecab 6470 #define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6471 #define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6472 #define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6473 #define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6474
Yassinetaouil 46:b1a9de66ecab 6475 /* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
Yassinetaouil 46:b1a9de66ecab 6476 #define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6477 #define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6478 #define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6479 #define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6480
Yassinetaouil 46:b1a9de66ecab 6481 /* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
Yassinetaouil 46:b1a9de66ecab 6482 #define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6483 #define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6484 #define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6485 #define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6486
Yassinetaouil 46:b1a9de66ecab 6487 /* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
Yassinetaouil 46:b1a9de66ecab 6488 #define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6489 #define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6490 #define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6491 #define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6492
Yassinetaouil 46:b1a9de66ecab 6493 /* Bit 2 : Enable or disable interrupt for FIELDLOST event */
Yassinetaouil 46:b1a9de66ecab 6494 #define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
Yassinetaouil 46:b1a9de66ecab 6495 #define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
Yassinetaouil 46:b1a9de66ecab 6496 #define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6497 #define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6498
Yassinetaouil 46:b1a9de66ecab 6499 /* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
Yassinetaouil 46:b1a9de66ecab 6500 #define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
Yassinetaouil 46:b1a9de66ecab 6501 #define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
Yassinetaouil 46:b1a9de66ecab 6502 #define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6503 #define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6504
Yassinetaouil 46:b1a9de66ecab 6505 /* Bit 0 : Enable or disable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 6506 #define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 6507 #define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 6508 #define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6509 #define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6510
Yassinetaouil 46:b1a9de66ecab 6511 /* Register: NFCT_INTENSET */
Yassinetaouil 46:b1a9de66ecab 6512 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 6513
Yassinetaouil 46:b1a9de66ecab 6514 /* Bit 20 : Write '1' to Enable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 6515 #define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 6516 #define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 6517 #define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6518 #define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6519 #define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6520
Yassinetaouil 46:b1a9de66ecab 6521 /* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
Yassinetaouil 46:b1a9de66ecab 6522 #define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
Yassinetaouil 46:b1a9de66ecab 6523 #define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
Yassinetaouil 46:b1a9de66ecab 6524 #define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6525 #define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6526 #define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6527
Yassinetaouil 46:b1a9de66ecab 6528 /* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
Yassinetaouil 46:b1a9de66ecab 6529 #define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
Yassinetaouil 46:b1a9de66ecab 6530 #define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
Yassinetaouil 46:b1a9de66ecab 6531 #define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6532 #define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6533 #define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6534
Yassinetaouil 46:b1a9de66ecab 6535 /* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
Yassinetaouil 46:b1a9de66ecab 6536 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 6537 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 6538 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6539 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6540 #define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6541
Yassinetaouil 46:b1a9de66ecab 6542 /* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
Yassinetaouil 46:b1a9de66ecab 6543 #define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 6544 #define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 6545 #define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6546 #define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6547 #define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6548
Yassinetaouil 46:b1a9de66ecab 6549 /* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 6550 #define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 6551 #define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 6552 #define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6553 #define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6554 #define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6555
Yassinetaouil 46:b1a9de66ecab 6556 /* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
Yassinetaouil 46:b1a9de66ecab 6557 #define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
Yassinetaouil 46:b1a9de66ecab 6558 #define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
Yassinetaouil 46:b1a9de66ecab 6559 #define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6560 #define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6561 #define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6562
Yassinetaouil 46:b1a9de66ecab 6563 /* Bit 7 : Write '1' to Enable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 6564 #define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 6565 #define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 6566 #define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6567 #define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6568 #define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6569
Yassinetaouil 46:b1a9de66ecab 6570 /* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
Yassinetaouil 46:b1a9de66ecab 6571 #define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6572 #define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6573 #define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6574 #define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6575 #define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6576
Yassinetaouil 46:b1a9de66ecab 6577 /* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
Yassinetaouil 46:b1a9de66ecab 6578 #define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6579 #define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6580 #define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6581 #define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6582 #define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6583
Yassinetaouil 46:b1a9de66ecab 6584 /* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
Yassinetaouil 46:b1a9de66ecab 6585 #define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6586 #define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6587 #define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6588 #define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6589 #define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6590
Yassinetaouil 46:b1a9de66ecab 6591 /* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
Yassinetaouil 46:b1a9de66ecab 6592 #define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6593 #define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6594 #define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6595 #define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6596 #define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6597
Yassinetaouil 46:b1a9de66ecab 6598 /* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
Yassinetaouil 46:b1a9de66ecab 6599 #define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
Yassinetaouil 46:b1a9de66ecab 6600 #define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
Yassinetaouil 46:b1a9de66ecab 6601 #define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6602 #define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6603 #define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6604
Yassinetaouil 46:b1a9de66ecab 6605 /* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
Yassinetaouil 46:b1a9de66ecab 6606 #define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
Yassinetaouil 46:b1a9de66ecab 6607 #define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
Yassinetaouil 46:b1a9de66ecab 6608 #define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6609 #define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6610 #define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6611
Yassinetaouil 46:b1a9de66ecab 6612 /* Bit 0 : Write '1' to Enable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 6613 #define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 6614 #define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 6615 #define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6616 #define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6617 #define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 6618
Yassinetaouil 46:b1a9de66ecab 6619 /* Register: NFCT_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 6620 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 6621
Yassinetaouil 46:b1a9de66ecab 6622 /* Bit 20 : Write '1' to Disable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 6623 #define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 6624 #define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 6625 #define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6626 #define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6627 #define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6628
Yassinetaouil 46:b1a9de66ecab 6629 /* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
Yassinetaouil 46:b1a9de66ecab 6630 #define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
Yassinetaouil 46:b1a9de66ecab 6631 #define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
Yassinetaouil 46:b1a9de66ecab 6632 #define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6633 #define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6634 #define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6635
Yassinetaouil 46:b1a9de66ecab 6636 /* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
Yassinetaouil 46:b1a9de66ecab 6637 #define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
Yassinetaouil 46:b1a9de66ecab 6638 #define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
Yassinetaouil 46:b1a9de66ecab 6639 #define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6640 #define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6641 #define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6642
Yassinetaouil 46:b1a9de66ecab 6643 /* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
Yassinetaouil 46:b1a9de66ecab 6644 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 6645 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 6646 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6647 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6648 #define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6649
Yassinetaouil 46:b1a9de66ecab 6650 /* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
Yassinetaouil 46:b1a9de66ecab 6651 #define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 6652 #define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 6653 #define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6654 #define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6655 #define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6656
Yassinetaouil 46:b1a9de66ecab 6657 /* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 6658 #define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 6659 #define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 6660 #define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6661 #define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6662 #define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6663
Yassinetaouil 46:b1a9de66ecab 6664 /* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
Yassinetaouil 46:b1a9de66ecab 6665 #define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
Yassinetaouil 46:b1a9de66ecab 6666 #define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
Yassinetaouil 46:b1a9de66ecab 6667 #define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6668 #define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6669 #define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6670
Yassinetaouil 46:b1a9de66ecab 6671 /* Bit 7 : Write '1' to Disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 6672 #define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 6673 #define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 6674 #define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6675 #define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6676 #define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6677
Yassinetaouil 46:b1a9de66ecab 6678 /* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
Yassinetaouil 46:b1a9de66ecab 6679 #define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6680 #define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6681 #define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6682 #define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6683 #define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6684
Yassinetaouil 46:b1a9de66ecab 6685 /* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
Yassinetaouil 46:b1a9de66ecab 6686 #define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6687 #define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6688 #define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6689 #define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6690 #define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6691
Yassinetaouil 46:b1a9de66ecab 6692 /* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
Yassinetaouil 46:b1a9de66ecab 6693 #define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6694 #define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
Yassinetaouil 46:b1a9de66ecab 6695 #define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6696 #define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6697 #define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6698
Yassinetaouil 46:b1a9de66ecab 6699 /* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
Yassinetaouil 46:b1a9de66ecab 6700 #define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6701 #define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
Yassinetaouil 46:b1a9de66ecab 6702 #define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6703 #define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6704 #define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6705
Yassinetaouil 46:b1a9de66ecab 6706 /* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
Yassinetaouil 46:b1a9de66ecab 6707 #define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
Yassinetaouil 46:b1a9de66ecab 6708 #define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
Yassinetaouil 46:b1a9de66ecab 6709 #define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6710 #define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6711 #define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6712
Yassinetaouil 46:b1a9de66ecab 6713 /* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
Yassinetaouil 46:b1a9de66ecab 6714 #define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
Yassinetaouil 46:b1a9de66ecab 6715 #define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
Yassinetaouil 46:b1a9de66ecab 6716 #define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6717 #define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6718 #define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6719
Yassinetaouil 46:b1a9de66ecab 6720 /* Bit 0 : Write '1' to Disable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 6721 #define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 6722 #define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 6723 #define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 6724 #define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 6725 #define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 6726
Yassinetaouil 46:b1a9de66ecab 6727 /* Register: NFCT_ERRORSTATUS */
Yassinetaouil 46:b1a9de66ecab 6728 /* Description: NFC Error Status register */
Yassinetaouil 46:b1a9de66ecab 6729
Yassinetaouil 46:b1a9de66ecab 6730 /* Bit 3 : Field level is too low at min load resistance */
Yassinetaouil 46:b1a9de66ecab 6731 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
Yassinetaouil 46:b1a9de66ecab 6732 #define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
Yassinetaouil 46:b1a9de66ecab 6733
Yassinetaouil 46:b1a9de66ecab 6734 /* Bit 2 : Field level is too high at max load resistance */
Yassinetaouil 46:b1a9de66ecab 6735 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
Yassinetaouil 46:b1a9de66ecab 6736 #define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
Yassinetaouil 46:b1a9de66ecab 6737
Yassinetaouil 46:b1a9de66ecab 6738 /* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
Yassinetaouil 46:b1a9de66ecab 6739 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
Yassinetaouil 46:b1a9de66ecab 6740 #define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
Yassinetaouil 46:b1a9de66ecab 6741
Yassinetaouil 46:b1a9de66ecab 6742 /* Register: NFCT_FRAMESTATUS_RX */
Yassinetaouil 46:b1a9de66ecab 6743 /* Description: Result of last incoming frames */
Yassinetaouil 46:b1a9de66ecab 6744
Yassinetaouil 46:b1a9de66ecab 6745 /* Bit 3 : Overrun detected */
Yassinetaouil 46:b1a9de66ecab 6746 #define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
Yassinetaouil 46:b1a9de66ecab 6747 #define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
Yassinetaouil 46:b1a9de66ecab 6748 #define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
Yassinetaouil 46:b1a9de66ecab 6749 #define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
Yassinetaouil 46:b1a9de66ecab 6750
Yassinetaouil 46:b1a9de66ecab 6751 /* Bit 2 : Parity status of received frame */
Yassinetaouil 46:b1a9de66ecab 6752 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
Yassinetaouil 46:b1a9de66ecab 6753 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
Yassinetaouil 46:b1a9de66ecab 6754 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
Yassinetaouil 46:b1a9de66ecab 6755 #define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
Yassinetaouil 46:b1a9de66ecab 6756
Yassinetaouil 46:b1a9de66ecab 6757 /* Bit 0 : No valid End of Frame detected */
Yassinetaouil 46:b1a9de66ecab 6758 #define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
Yassinetaouil 46:b1a9de66ecab 6759 #define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
Yassinetaouil 46:b1a9de66ecab 6760 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
Yassinetaouil 46:b1a9de66ecab 6761 #define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
Yassinetaouil 46:b1a9de66ecab 6762
Yassinetaouil 46:b1a9de66ecab 6763 /* Register: NFCT_CURRENTLOADCTRL */
Yassinetaouil 46:b1a9de66ecab 6764 /* Description: Current value driven to the NFC Load Control */
Yassinetaouil 46:b1a9de66ecab 6765
Yassinetaouil 46:b1a9de66ecab 6766 /* Bits 5..0 : Current value driven to the NFC Load Control */
Yassinetaouil 46:b1a9de66ecab 6767 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
Yassinetaouil 46:b1a9de66ecab 6768 #define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
Yassinetaouil 46:b1a9de66ecab 6769
Yassinetaouil 46:b1a9de66ecab 6770 /* Register: NFCT_FIELDPRESENT */
Yassinetaouil 46:b1a9de66ecab 6771 /* Description: Indicates the presence or not of a valid field */
Yassinetaouil 46:b1a9de66ecab 6772
Yassinetaouil 46:b1a9de66ecab 6773 /* Bit 1 : Indicates if the low level has locked to the field */
Yassinetaouil 46:b1a9de66ecab 6774 #define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
Yassinetaouil 46:b1a9de66ecab 6775 #define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
Yassinetaouil 46:b1a9de66ecab 6776 #define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
Yassinetaouil 46:b1a9de66ecab 6777 #define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
Yassinetaouil 46:b1a9de66ecab 6778
Yassinetaouil 46:b1a9de66ecab 6779 /* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
Yassinetaouil 46:b1a9de66ecab 6780 #define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
Yassinetaouil 46:b1a9de66ecab 6781 #define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
Yassinetaouil 46:b1a9de66ecab 6782 #define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
Yassinetaouil 46:b1a9de66ecab 6783 #define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
Yassinetaouil 46:b1a9de66ecab 6784
Yassinetaouil 46:b1a9de66ecab 6785 /* Register: NFCT_FRAMEDELAYMIN */
Yassinetaouil 46:b1a9de66ecab 6786 /* Description: Minimum frame delay */
Yassinetaouil 46:b1a9de66ecab 6787
Yassinetaouil 46:b1a9de66ecab 6788 /* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
Yassinetaouil 46:b1a9de66ecab 6789 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
Yassinetaouil 46:b1a9de66ecab 6790 #define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
Yassinetaouil 46:b1a9de66ecab 6791
Yassinetaouil 46:b1a9de66ecab 6792 /* Register: NFCT_FRAMEDELAYMAX */
Yassinetaouil 46:b1a9de66ecab 6793 /* Description: Maximum frame delay */
Yassinetaouil 46:b1a9de66ecab 6794
Yassinetaouil 46:b1a9de66ecab 6795 /* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
Yassinetaouil 46:b1a9de66ecab 6796 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
Yassinetaouil 46:b1a9de66ecab 6797 #define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
Yassinetaouil 46:b1a9de66ecab 6798
Yassinetaouil 46:b1a9de66ecab 6799 /* Register: NFCT_FRAMEDELAYMODE */
Yassinetaouil 46:b1a9de66ecab 6800 /* Description: Configuration register for the Frame Delay Timer */
Yassinetaouil 46:b1a9de66ecab 6801
Yassinetaouil 46:b1a9de66ecab 6802 /* Bits 1..0 : Configuration register for the Frame Delay Timer */
Yassinetaouil 46:b1a9de66ecab 6803 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
Yassinetaouil 46:b1a9de66ecab 6804 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
Yassinetaouil 46:b1a9de66ecab 6805 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
Yassinetaouil 46:b1a9de66ecab 6806 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
Yassinetaouil 46:b1a9de66ecab 6807 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
Yassinetaouil 46:b1a9de66ecab 6808 #define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
Yassinetaouil 46:b1a9de66ecab 6809
Yassinetaouil 46:b1a9de66ecab 6810 /* Register: NFCT_PACKETPTR */
Yassinetaouil 46:b1a9de66ecab 6811 /* Description: Packet pointer for TXD and RXD data storage in Data RAM */
Yassinetaouil 46:b1a9de66ecab 6812
Yassinetaouil 46:b1a9de66ecab 6813 /* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
Yassinetaouil 46:b1a9de66ecab 6814 #define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 6815 #define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 6816
Yassinetaouil 46:b1a9de66ecab 6817 /* Register: NFCT_MAXLEN */
Yassinetaouil 46:b1a9de66ecab 6818 /* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
Yassinetaouil 46:b1a9de66ecab 6819
Yassinetaouil 46:b1a9de66ecab 6820 /* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
Yassinetaouil 46:b1a9de66ecab 6821 #define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
Yassinetaouil 46:b1a9de66ecab 6822 #define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
Yassinetaouil 46:b1a9de66ecab 6823
Yassinetaouil 46:b1a9de66ecab 6824 /* Register: NFCT_TXD_FRAMECONFIG */
Yassinetaouil 46:b1a9de66ecab 6825 /* Description: Configuration of outgoing frames */
Yassinetaouil 46:b1a9de66ecab 6826
Yassinetaouil 46:b1a9de66ecab 6827 /* Bit 4 : CRC mode for outgoing frames */
Yassinetaouil 46:b1a9de66ecab 6828 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
Yassinetaouil 46:b1a9de66ecab 6829 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
Yassinetaouil 46:b1a9de66ecab 6830 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
Yassinetaouil 46:b1a9de66ecab 6831 #define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
Yassinetaouil 46:b1a9de66ecab 6832
Yassinetaouil 46:b1a9de66ecab 6833 /* Bit 2 : Adding SoF or not in TX frames */
Yassinetaouil 46:b1a9de66ecab 6834 #define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
Yassinetaouil 46:b1a9de66ecab 6835 #define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
Yassinetaouil 46:b1a9de66ecab 6836 #define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
Yassinetaouil 46:b1a9de66ecab 6837 #define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
Yassinetaouil 46:b1a9de66ecab 6838
Yassinetaouil 46:b1a9de66ecab 6839 /* Bit 1 : Discarding unused bits in start or at end of a Frame */
Yassinetaouil 46:b1a9de66ecab 6840 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
Yassinetaouil 46:b1a9de66ecab 6841 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
Yassinetaouil 46:b1a9de66ecab 6842 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
Yassinetaouil 46:b1a9de66ecab 6843 #define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
Yassinetaouil 46:b1a9de66ecab 6844
Yassinetaouil 46:b1a9de66ecab 6845 /* Bit 0 : Adding parity or not in the frame */
Yassinetaouil 46:b1a9de66ecab 6846 #define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 6847 #define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 6848 #define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
Yassinetaouil 46:b1a9de66ecab 6849 #define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
Yassinetaouil 46:b1a9de66ecab 6850
Yassinetaouil 46:b1a9de66ecab 6851 /* Register: NFCT_TXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 6852 /* Description: Size of outgoing frame */
Yassinetaouil 46:b1a9de66ecab 6853
Yassinetaouil 46:b1a9de66ecab 6854 /* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
Yassinetaouil 46:b1a9de66ecab 6855 #define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
Yassinetaouil 46:b1a9de66ecab 6856 #define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
Yassinetaouil 46:b1a9de66ecab 6857
Yassinetaouil 46:b1a9de66ecab 6858 /* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
Yassinetaouil 46:b1a9de66ecab 6859 #define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
Yassinetaouil 46:b1a9de66ecab 6860 #define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
Yassinetaouil 46:b1a9de66ecab 6861
Yassinetaouil 46:b1a9de66ecab 6862 /* Register: NFCT_RXD_FRAMECONFIG */
Yassinetaouil 46:b1a9de66ecab 6863 /* Description: Configuration of incoming frames */
Yassinetaouil 46:b1a9de66ecab 6864
Yassinetaouil 46:b1a9de66ecab 6865 /* Bit 4 : CRC mode for incoming frames */
Yassinetaouil 46:b1a9de66ecab 6866 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
Yassinetaouil 46:b1a9de66ecab 6867 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
Yassinetaouil 46:b1a9de66ecab 6868 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
Yassinetaouil 46:b1a9de66ecab 6869 #define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
Yassinetaouil 46:b1a9de66ecab 6870
Yassinetaouil 46:b1a9de66ecab 6871 /* Bit 2 : SoF expected or not in RX frames */
Yassinetaouil 46:b1a9de66ecab 6872 #define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
Yassinetaouil 46:b1a9de66ecab 6873 #define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
Yassinetaouil 46:b1a9de66ecab 6874 #define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
Yassinetaouil 46:b1a9de66ecab 6875 #define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
Yassinetaouil 46:b1a9de66ecab 6876
Yassinetaouil 46:b1a9de66ecab 6877 /* Bit 0 : Parity expected or not in RX frame */
Yassinetaouil 46:b1a9de66ecab 6878 #define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 6879 #define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 6880 #define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
Yassinetaouil 46:b1a9de66ecab 6881 #define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
Yassinetaouil 46:b1a9de66ecab 6882
Yassinetaouil 46:b1a9de66ecab 6883 /* Register: NFCT_RXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 6884 /* Description: Size of last incoming frame */
Yassinetaouil 46:b1a9de66ecab 6885
Yassinetaouil 46:b1a9de66ecab 6886 /* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
Yassinetaouil 46:b1a9de66ecab 6887 #define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
Yassinetaouil 46:b1a9de66ecab 6888 #define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
Yassinetaouil 46:b1a9de66ecab 6889
Yassinetaouil 46:b1a9de66ecab 6890 /* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
Yassinetaouil 46:b1a9de66ecab 6891 #define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
Yassinetaouil 46:b1a9de66ecab 6892 #define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
Yassinetaouil 46:b1a9de66ecab 6893
Yassinetaouil 46:b1a9de66ecab 6894 /* Register: NFCT_NFCID1_LAST */
Yassinetaouil 46:b1a9de66ecab 6895 /* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
Yassinetaouil 46:b1a9de66ecab 6896
Yassinetaouil 46:b1a9de66ecab 6897 /* Bits 31..24 : NFCID1 byte W */
Yassinetaouil 46:b1a9de66ecab 6898 #define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
Yassinetaouil 46:b1a9de66ecab 6899 #define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
Yassinetaouil 46:b1a9de66ecab 6900
Yassinetaouil 46:b1a9de66ecab 6901 /* Bits 23..16 : NFCID1 byte X */
Yassinetaouil 46:b1a9de66ecab 6902 #define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
Yassinetaouil 46:b1a9de66ecab 6903 #define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
Yassinetaouil 46:b1a9de66ecab 6904
Yassinetaouil 46:b1a9de66ecab 6905 /* Bits 15..8 : NFCID1 byte Y */
Yassinetaouil 46:b1a9de66ecab 6906 #define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
Yassinetaouil 46:b1a9de66ecab 6907 #define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
Yassinetaouil 46:b1a9de66ecab 6908
Yassinetaouil 46:b1a9de66ecab 6909 /* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
Yassinetaouil 46:b1a9de66ecab 6910 #define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
Yassinetaouil 46:b1a9de66ecab 6911 #define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
Yassinetaouil 46:b1a9de66ecab 6912
Yassinetaouil 46:b1a9de66ecab 6913 /* Register: NFCT_NFCID1_2ND_LAST */
Yassinetaouil 46:b1a9de66ecab 6914 /* Description: Second last NFCID1 part (7 or 10 bytes ID) */
Yassinetaouil 46:b1a9de66ecab 6915
Yassinetaouil 46:b1a9de66ecab 6916 /* Bits 23..16 : NFCID1 byte T */
Yassinetaouil 46:b1a9de66ecab 6917 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
Yassinetaouil 46:b1a9de66ecab 6918 #define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
Yassinetaouil 46:b1a9de66ecab 6919
Yassinetaouil 46:b1a9de66ecab 6920 /* Bits 15..8 : NFCID1 byte U */
Yassinetaouil 46:b1a9de66ecab 6921 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
Yassinetaouil 46:b1a9de66ecab 6922 #define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
Yassinetaouil 46:b1a9de66ecab 6923
Yassinetaouil 46:b1a9de66ecab 6924 /* Bits 7..0 : NFCID1 byte V */
Yassinetaouil 46:b1a9de66ecab 6925 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
Yassinetaouil 46:b1a9de66ecab 6926 #define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
Yassinetaouil 46:b1a9de66ecab 6927
Yassinetaouil 46:b1a9de66ecab 6928 /* Register: NFCT_NFCID1_3RD_LAST */
Yassinetaouil 46:b1a9de66ecab 6929 /* Description: Third last NFCID1 part (10 bytes ID) */
Yassinetaouil 46:b1a9de66ecab 6930
Yassinetaouil 46:b1a9de66ecab 6931 /* Bits 23..16 : NFCID1 byte Q */
Yassinetaouil 46:b1a9de66ecab 6932 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
Yassinetaouil 46:b1a9de66ecab 6933 #define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
Yassinetaouil 46:b1a9de66ecab 6934
Yassinetaouil 46:b1a9de66ecab 6935 /* Bits 15..8 : NFCID1 byte R */
Yassinetaouil 46:b1a9de66ecab 6936 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
Yassinetaouil 46:b1a9de66ecab 6937 #define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
Yassinetaouil 46:b1a9de66ecab 6938
Yassinetaouil 46:b1a9de66ecab 6939 /* Bits 7..0 : NFCID1 byte S */
Yassinetaouil 46:b1a9de66ecab 6940 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
Yassinetaouil 46:b1a9de66ecab 6941 #define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
Yassinetaouil 46:b1a9de66ecab 6942
Yassinetaouil 46:b1a9de66ecab 6943 /* Register: NFCT_SENSRES */
Yassinetaouil 46:b1a9de66ecab 6944 /* Description: NFC-A SENS_RES auto-response settings */
Yassinetaouil 46:b1a9de66ecab 6945
Yassinetaouil 46:b1a9de66ecab 6946 /* Bits 15..12 : Reserved for future use. Shall be 0. */
Yassinetaouil 46:b1a9de66ecab 6947 #define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
Yassinetaouil 46:b1a9de66ecab 6948 #define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
Yassinetaouil 46:b1a9de66ecab 6949
Yassinetaouil 46:b1a9de66ecab 6950 /* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
Yassinetaouil 46:b1a9de66ecab 6951 #define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
Yassinetaouil 46:b1a9de66ecab 6952 #define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
Yassinetaouil 46:b1a9de66ecab 6953
Yassinetaouil 46:b1a9de66ecab 6954 /* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
Yassinetaouil 46:b1a9de66ecab 6955 #define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
Yassinetaouil 46:b1a9de66ecab 6956 #define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
Yassinetaouil 46:b1a9de66ecab 6957 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
Yassinetaouil 46:b1a9de66ecab 6958 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
Yassinetaouil 46:b1a9de66ecab 6959 #define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
Yassinetaouil 46:b1a9de66ecab 6960
Yassinetaouil 46:b1a9de66ecab 6961 /* Bit 5 : Reserved for future use. Shall be 0. */
Yassinetaouil 46:b1a9de66ecab 6962 #define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
Yassinetaouil 46:b1a9de66ecab 6963 #define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
Yassinetaouil 46:b1a9de66ecab 6964
Yassinetaouil 46:b1a9de66ecab 6965 /* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
Yassinetaouil 46:b1a9de66ecab 6966 #define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
Yassinetaouil 46:b1a9de66ecab 6967 #define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
Yassinetaouil 46:b1a9de66ecab 6968 #define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
Yassinetaouil 46:b1a9de66ecab 6969 #define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
Yassinetaouil 46:b1a9de66ecab 6970 #define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
Yassinetaouil 46:b1a9de66ecab 6971 #define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
Yassinetaouil 46:b1a9de66ecab 6972 #define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
Yassinetaouil 46:b1a9de66ecab 6973 #define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
Yassinetaouil 46:b1a9de66ecab 6974
Yassinetaouil 46:b1a9de66ecab 6975 /* Register: NFCT_SELRES */
Yassinetaouil 46:b1a9de66ecab 6976 /* Description: NFC-A SEL_RES auto-response settings */
Yassinetaouil 46:b1a9de66ecab 6977
Yassinetaouil 46:b1a9de66ecab 6978 /* Bit 7 : Reserved for future use. Shall be 0. */
Yassinetaouil 46:b1a9de66ecab 6979 #define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
Yassinetaouil 46:b1a9de66ecab 6980 #define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
Yassinetaouil 46:b1a9de66ecab 6981
Yassinetaouil 46:b1a9de66ecab 6982 /* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
Yassinetaouil 46:b1a9de66ecab 6983 #define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
Yassinetaouil 46:b1a9de66ecab 6984 #define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
Yassinetaouil 46:b1a9de66ecab 6985
Yassinetaouil 46:b1a9de66ecab 6986 /* Bits 4..3 : Reserved for future use. Shall be 0. */
Yassinetaouil 46:b1a9de66ecab 6987 #define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
Yassinetaouil 46:b1a9de66ecab 6988 #define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
Yassinetaouil 46:b1a9de66ecab 6989
Yassinetaouil 46:b1a9de66ecab 6990 /* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
Yassinetaouil 46:b1a9de66ecab 6991 #define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
Yassinetaouil 46:b1a9de66ecab 6992 #define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
Yassinetaouil 46:b1a9de66ecab 6993 #define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
Yassinetaouil 46:b1a9de66ecab 6994 #define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
Yassinetaouil 46:b1a9de66ecab 6995
Yassinetaouil 46:b1a9de66ecab 6996 /* Bits 1..0 : Reserved for future use. Shall be 0. */
Yassinetaouil 46:b1a9de66ecab 6997 #define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
Yassinetaouil 46:b1a9de66ecab 6998 #define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
Yassinetaouil 46:b1a9de66ecab 6999
Yassinetaouil 46:b1a9de66ecab 7000
Yassinetaouil 46:b1a9de66ecab 7001 /* Peripheral: NVMC */
Yassinetaouil 46:b1a9de66ecab 7002 /* Description: Non Volatile Memory Controller */
Yassinetaouil 46:b1a9de66ecab 7003
Yassinetaouil 46:b1a9de66ecab 7004 /* Register: NVMC_READY */
Yassinetaouil 46:b1a9de66ecab 7005 /* Description: Ready flag */
Yassinetaouil 46:b1a9de66ecab 7006
Yassinetaouil 46:b1a9de66ecab 7007 /* Bit 0 : NVMC is ready or busy */
Yassinetaouil 46:b1a9de66ecab 7008 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 7009 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 7010 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
Yassinetaouil 46:b1a9de66ecab 7011 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
Yassinetaouil 46:b1a9de66ecab 7012
Yassinetaouil 46:b1a9de66ecab 7013 /* Register: NVMC_CONFIG */
Yassinetaouil 46:b1a9de66ecab 7014 /* Description: Configuration register */
Yassinetaouil 46:b1a9de66ecab 7015
Yassinetaouil 46:b1a9de66ecab 7016 /* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
Yassinetaouil 46:b1a9de66ecab 7017 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
Yassinetaouil 46:b1a9de66ecab 7018 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
Yassinetaouil 46:b1a9de66ecab 7019 #define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
Yassinetaouil 46:b1a9de66ecab 7020 #define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
Yassinetaouil 46:b1a9de66ecab 7021 #define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
Yassinetaouil 46:b1a9de66ecab 7022
Yassinetaouil 46:b1a9de66ecab 7023 /* Register: NVMC_ERASEPAGE */
Yassinetaouil 46:b1a9de66ecab 7024 /* Description: Register for erasing a page in Code area */
Yassinetaouil 46:b1a9de66ecab 7025
Yassinetaouil 46:b1a9de66ecab 7026 /* Bits 31..0 : Register for starting erase of a page in Code area */
Yassinetaouil 46:b1a9de66ecab 7027 #define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
Yassinetaouil 46:b1a9de66ecab 7028 #define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
Yassinetaouil 46:b1a9de66ecab 7029
Yassinetaouil 46:b1a9de66ecab 7030 /* Register: NVMC_ERASEPCR1 */
Yassinetaouil 46:b1a9de66ecab 7031 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
Yassinetaouil 46:b1a9de66ecab 7032
Yassinetaouil 46:b1a9de66ecab 7033 /* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
Yassinetaouil 46:b1a9de66ecab 7034 #define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
Yassinetaouil 46:b1a9de66ecab 7035 #define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
Yassinetaouil 46:b1a9de66ecab 7036
Yassinetaouil 46:b1a9de66ecab 7037 /* Register: NVMC_ERASEALL */
Yassinetaouil 46:b1a9de66ecab 7038 /* Description: Register for erasing all non-volatile user memory */
Yassinetaouil 46:b1a9de66ecab 7039
Yassinetaouil 46:b1a9de66ecab 7040 /* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
Yassinetaouil 46:b1a9de66ecab 7041 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
Yassinetaouil 46:b1a9de66ecab 7042 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
Yassinetaouil 46:b1a9de66ecab 7043 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
Yassinetaouil 46:b1a9de66ecab 7044 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
Yassinetaouil 46:b1a9de66ecab 7045
Yassinetaouil 46:b1a9de66ecab 7046 /* Register: NVMC_ERASEPCR0 */
Yassinetaouil 46:b1a9de66ecab 7047 /* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
Yassinetaouil 46:b1a9de66ecab 7048
Yassinetaouil 46:b1a9de66ecab 7049 /* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
Yassinetaouil 46:b1a9de66ecab 7050 #define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
Yassinetaouil 46:b1a9de66ecab 7051 #define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
Yassinetaouil 46:b1a9de66ecab 7052
Yassinetaouil 46:b1a9de66ecab 7053 /* Register: NVMC_ERASEUICR */
Yassinetaouil 46:b1a9de66ecab 7054 /* Description: Register for erasing User Information Configuration Registers */
Yassinetaouil 46:b1a9de66ecab 7055
Yassinetaouil 46:b1a9de66ecab 7056 /* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
Yassinetaouil 46:b1a9de66ecab 7057 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
Yassinetaouil 46:b1a9de66ecab 7058 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
Yassinetaouil 46:b1a9de66ecab 7059 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
Yassinetaouil 46:b1a9de66ecab 7060 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
Yassinetaouil 46:b1a9de66ecab 7061
Yassinetaouil 46:b1a9de66ecab 7062 /* Register: NVMC_ICACHECNF */
Yassinetaouil 46:b1a9de66ecab 7063 /* Description: I-Code cache configuration register. */
Yassinetaouil 46:b1a9de66ecab 7064
Yassinetaouil 46:b1a9de66ecab 7065 /* Bit 8 : Cache profiling enable */
Yassinetaouil 46:b1a9de66ecab 7066 #define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
Yassinetaouil 46:b1a9de66ecab 7067 #define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
Yassinetaouil 46:b1a9de66ecab 7068 #define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
Yassinetaouil 46:b1a9de66ecab 7069 #define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
Yassinetaouil 46:b1a9de66ecab 7070
Yassinetaouil 46:b1a9de66ecab 7071 /* Bit 0 : Cache enable */
Yassinetaouil 46:b1a9de66ecab 7072 #define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
Yassinetaouil 46:b1a9de66ecab 7073 #define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
Yassinetaouil 46:b1a9de66ecab 7074 #define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
Yassinetaouil 46:b1a9de66ecab 7075 #define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
Yassinetaouil 46:b1a9de66ecab 7076
Yassinetaouil 46:b1a9de66ecab 7077 /* Register: NVMC_IHIT */
Yassinetaouil 46:b1a9de66ecab 7078 /* Description: I-Code cache hit counter. */
Yassinetaouil 46:b1a9de66ecab 7079
Yassinetaouil 46:b1a9de66ecab 7080 /* Bits 31..0 : Number of cache hits */
Yassinetaouil 46:b1a9de66ecab 7081 #define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
Yassinetaouil 46:b1a9de66ecab 7082 #define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
Yassinetaouil 46:b1a9de66ecab 7083
Yassinetaouil 46:b1a9de66ecab 7084 /* Register: NVMC_IMISS */
Yassinetaouil 46:b1a9de66ecab 7085 /* Description: I-Code cache miss counter. */
Yassinetaouil 46:b1a9de66ecab 7086
Yassinetaouil 46:b1a9de66ecab 7087 /* Bits 31..0 : Number of cache misses */
Yassinetaouil 46:b1a9de66ecab 7088 #define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
Yassinetaouil 46:b1a9de66ecab 7089 #define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
Yassinetaouil 46:b1a9de66ecab 7090
Yassinetaouil 46:b1a9de66ecab 7091
Yassinetaouil 46:b1a9de66ecab 7092 /* Peripheral: GPIO */
Yassinetaouil 46:b1a9de66ecab 7093 /* Description: GPIO Port 1 */
Yassinetaouil 46:b1a9de66ecab 7094
Yassinetaouil 46:b1a9de66ecab 7095 /* Register: GPIO_OUT */
Yassinetaouil 46:b1a9de66ecab 7096 /* Description: Write GPIO port */
Yassinetaouil 46:b1a9de66ecab 7097
Yassinetaouil 46:b1a9de66ecab 7098 /* Bit 31 : P0.31 pin */
Yassinetaouil 46:b1a9de66ecab 7099 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7100 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7101 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7102 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7103
Yassinetaouil 46:b1a9de66ecab 7104 /* Bit 30 : P0.30 pin */
Yassinetaouil 46:b1a9de66ecab 7105 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7106 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7107 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7108 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7109
Yassinetaouil 46:b1a9de66ecab 7110 /* Bit 29 : P0.29 pin */
Yassinetaouil 46:b1a9de66ecab 7111 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7112 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7113 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7114 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7115
Yassinetaouil 46:b1a9de66ecab 7116 /* Bit 28 : P0.28 pin */
Yassinetaouil 46:b1a9de66ecab 7117 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7118 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7119 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7120 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7121
Yassinetaouil 46:b1a9de66ecab 7122 /* Bit 27 : P0.27 pin */
Yassinetaouil 46:b1a9de66ecab 7123 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7124 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7125 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7126 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7127
Yassinetaouil 46:b1a9de66ecab 7128 /* Bit 26 : P0.26 pin */
Yassinetaouil 46:b1a9de66ecab 7129 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7130 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7131 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7132 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7133
Yassinetaouil 46:b1a9de66ecab 7134 /* Bit 25 : P0.25 pin */
Yassinetaouil 46:b1a9de66ecab 7135 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7136 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7137 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7138 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7139
Yassinetaouil 46:b1a9de66ecab 7140 /* Bit 24 : P0.24 pin */
Yassinetaouil 46:b1a9de66ecab 7141 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7142 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7143 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7144 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7145
Yassinetaouil 46:b1a9de66ecab 7146 /* Bit 23 : P0.23 pin */
Yassinetaouil 46:b1a9de66ecab 7147 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7148 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7149 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7150 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7151
Yassinetaouil 46:b1a9de66ecab 7152 /* Bit 22 : P0.22 pin */
Yassinetaouil 46:b1a9de66ecab 7153 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7154 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7155 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7156 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7157
Yassinetaouil 46:b1a9de66ecab 7158 /* Bit 21 : P0.21 pin */
Yassinetaouil 46:b1a9de66ecab 7159 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 7160 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 7161 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7162 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7163
Yassinetaouil 46:b1a9de66ecab 7164 /* Bit 20 : P0.20 pin */
Yassinetaouil 46:b1a9de66ecab 7165 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 7166 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 7167 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7168 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7169
Yassinetaouil 46:b1a9de66ecab 7170 /* Bit 19 : P0.19 pin */
Yassinetaouil 46:b1a9de66ecab 7171 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 7172 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 7173 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7174 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7175
Yassinetaouil 46:b1a9de66ecab 7176 /* Bit 18 : P0.18 pin */
Yassinetaouil 46:b1a9de66ecab 7177 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 7178 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 7179 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7180 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7181
Yassinetaouil 46:b1a9de66ecab 7182 /* Bit 17 : P0.17 pin */
Yassinetaouil 46:b1a9de66ecab 7183 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 7184 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 7185 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7186 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7187
Yassinetaouil 46:b1a9de66ecab 7188 /* Bit 16 : P0.16 pin */
Yassinetaouil 46:b1a9de66ecab 7189 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 7190 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 7191 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7192 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7193
Yassinetaouil 46:b1a9de66ecab 7194 /* Bit 15 : P0.15 pin */
Yassinetaouil 46:b1a9de66ecab 7195 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 7196 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 7197 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7198 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7199
Yassinetaouil 46:b1a9de66ecab 7200 /* Bit 14 : P0.14 pin */
Yassinetaouil 46:b1a9de66ecab 7201 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 7202 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 7203 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7204 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7205
Yassinetaouil 46:b1a9de66ecab 7206 /* Bit 13 : P0.13 pin */
Yassinetaouil 46:b1a9de66ecab 7207 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 7208 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 7209 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7210 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7211
Yassinetaouil 46:b1a9de66ecab 7212 /* Bit 12 : P0.12 pin */
Yassinetaouil 46:b1a9de66ecab 7213 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 7214 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 7215 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7216 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7217
Yassinetaouil 46:b1a9de66ecab 7218 /* Bit 11 : P0.11 pin */
Yassinetaouil 46:b1a9de66ecab 7219 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 7220 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 7221 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7222 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7223
Yassinetaouil 46:b1a9de66ecab 7224 /* Bit 10 : P0.10 pin */
Yassinetaouil 46:b1a9de66ecab 7225 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 7226 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 7227 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7228 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7229
Yassinetaouil 46:b1a9de66ecab 7230 /* Bit 9 : P0.9 pin */
Yassinetaouil 46:b1a9de66ecab 7231 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 7232 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 7233 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7234 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7235
Yassinetaouil 46:b1a9de66ecab 7236 /* Bit 8 : P0.8 pin */
Yassinetaouil 46:b1a9de66ecab 7237 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 7238 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 7239 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7240 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7241
Yassinetaouil 46:b1a9de66ecab 7242 /* Bit 7 : P0.7 pin */
Yassinetaouil 46:b1a9de66ecab 7243 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 7244 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 7245 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7246 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7247
Yassinetaouil 46:b1a9de66ecab 7248 /* Bit 6 : P0.6 pin */
Yassinetaouil 46:b1a9de66ecab 7249 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 7250 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 7251 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7252 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7253
Yassinetaouil 46:b1a9de66ecab 7254 /* Bit 5 : P0.5 pin */
Yassinetaouil 46:b1a9de66ecab 7255 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 7256 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 7257 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7258 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7259
Yassinetaouil 46:b1a9de66ecab 7260 /* Bit 4 : P0.4 pin */
Yassinetaouil 46:b1a9de66ecab 7261 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 7262 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 7263 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7264 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7265
Yassinetaouil 46:b1a9de66ecab 7266 /* Bit 3 : P0.3 pin */
Yassinetaouil 46:b1a9de66ecab 7267 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 7268 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 7269 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7270 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7271
Yassinetaouil 46:b1a9de66ecab 7272 /* Bit 2 : P0.2 pin */
Yassinetaouil 46:b1a9de66ecab 7273 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 7274 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 7275 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7276 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7277
Yassinetaouil 46:b1a9de66ecab 7278 /* Bit 1 : P0.1 pin */
Yassinetaouil 46:b1a9de66ecab 7279 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 7280 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 7281 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7282 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7283
Yassinetaouil 46:b1a9de66ecab 7284 /* Bit 0 : P0.0 pin */
Yassinetaouil 46:b1a9de66ecab 7285 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 7286 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 7287 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7288 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7289
Yassinetaouil 46:b1a9de66ecab 7290 /* Register: GPIO_OUTSET */
Yassinetaouil 46:b1a9de66ecab 7291 /* Description: Set individual bits in GPIO port */
Yassinetaouil 46:b1a9de66ecab 7292
Yassinetaouil 46:b1a9de66ecab 7293 /* Bit 31 : P0.31 pin */
Yassinetaouil 46:b1a9de66ecab 7294 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7295 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7296 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7297 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7298 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7299
Yassinetaouil 46:b1a9de66ecab 7300 /* Bit 30 : P0.30 pin */
Yassinetaouil 46:b1a9de66ecab 7301 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7302 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7303 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7304 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7305 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7306
Yassinetaouil 46:b1a9de66ecab 7307 /* Bit 29 : P0.29 pin */
Yassinetaouil 46:b1a9de66ecab 7308 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7309 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7310 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7311 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7312 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7313
Yassinetaouil 46:b1a9de66ecab 7314 /* Bit 28 : P0.28 pin */
Yassinetaouil 46:b1a9de66ecab 7315 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7316 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7317 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7318 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7319 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7320
Yassinetaouil 46:b1a9de66ecab 7321 /* Bit 27 : P0.27 pin */
Yassinetaouil 46:b1a9de66ecab 7322 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7323 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7324 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7325 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7326 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7327
Yassinetaouil 46:b1a9de66ecab 7328 /* Bit 26 : P0.26 pin */
Yassinetaouil 46:b1a9de66ecab 7329 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7330 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7331 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7332 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7333 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7334
Yassinetaouil 46:b1a9de66ecab 7335 /* Bit 25 : P0.25 pin */
Yassinetaouil 46:b1a9de66ecab 7336 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7337 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7338 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7339 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7340 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7341
Yassinetaouil 46:b1a9de66ecab 7342 /* Bit 24 : P0.24 pin */
Yassinetaouil 46:b1a9de66ecab 7343 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7344 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7345 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7346 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7347 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7348
Yassinetaouil 46:b1a9de66ecab 7349 /* Bit 23 : P0.23 pin */
Yassinetaouil 46:b1a9de66ecab 7350 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7351 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7352 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7353 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7354 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7355
Yassinetaouil 46:b1a9de66ecab 7356 /* Bit 22 : P0.22 pin */
Yassinetaouil 46:b1a9de66ecab 7357 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7358 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7359 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7360 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7361 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7362
Yassinetaouil 46:b1a9de66ecab 7363 /* Bit 21 : P0.21 pin */
Yassinetaouil 46:b1a9de66ecab 7364 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 7365 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 7366 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7367 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7368 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7369
Yassinetaouil 46:b1a9de66ecab 7370 /* Bit 20 : P0.20 pin */
Yassinetaouil 46:b1a9de66ecab 7371 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 7372 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 7373 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7374 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7375 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7376
Yassinetaouil 46:b1a9de66ecab 7377 /* Bit 19 : P0.19 pin */
Yassinetaouil 46:b1a9de66ecab 7378 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 7379 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 7380 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7381 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7382 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7383
Yassinetaouil 46:b1a9de66ecab 7384 /* Bit 18 : P0.18 pin */
Yassinetaouil 46:b1a9de66ecab 7385 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 7386 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 7387 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7388 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7389 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7390
Yassinetaouil 46:b1a9de66ecab 7391 /* Bit 17 : P0.17 pin */
Yassinetaouil 46:b1a9de66ecab 7392 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 7393 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 7394 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7395 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7396 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7397
Yassinetaouil 46:b1a9de66ecab 7398 /* Bit 16 : P0.16 pin */
Yassinetaouil 46:b1a9de66ecab 7399 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 7400 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 7401 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7402 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7403 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7404
Yassinetaouil 46:b1a9de66ecab 7405 /* Bit 15 : P0.15 pin */
Yassinetaouil 46:b1a9de66ecab 7406 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 7407 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 7408 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7409 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7410 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7411
Yassinetaouil 46:b1a9de66ecab 7412 /* Bit 14 : P0.14 pin */
Yassinetaouil 46:b1a9de66ecab 7413 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 7414 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 7415 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7416 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7417 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7418
Yassinetaouil 46:b1a9de66ecab 7419 /* Bit 13 : P0.13 pin */
Yassinetaouil 46:b1a9de66ecab 7420 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 7421 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 7422 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7423 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7424 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7425
Yassinetaouil 46:b1a9de66ecab 7426 /* Bit 12 : P0.12 pin */
Yassinetaouil 46:b1a9de66ecab 7427 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 7428 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 7429 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7430 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7431 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7432
Yassinetaouil 46:b1a9de66ecab 7433 /* Bit 11 : P0.11 pin */
Yassinetaouil 46:b1a9de66ecab 7434 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 7435 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 7436 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7437 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7438 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7439
Yassinetaouil 46:b1a9de66ecab 7440 /* Bit 10 : P0.10 pin */
Yassinetaouil 46:b1a9de66ecab 7441 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 7442 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 7443 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7444 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7445 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7446
Yassinetaouil 46:b1a9de66ecab 7447 /* Bit 9 : P0.9 pin */
Yassinetaouil 46:b1a9de66ecab 7448 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 7449 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 7450 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7451 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7452 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7453
Yassinetaouil 46:b1a9de66ecab 7454 /* Bit 8 : P0.8 pin */
Yassinetaouil 46:b1a9de66ecab 7455 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 7456 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 7457 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7458 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7459 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7460
Yassinetaouil 46:b1a9de66ecab 7461 /* Bit 7 : P0.7 pin */
Yassinetaouil 46:b1a9de66ecab 7462 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 7463 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 7464 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7465 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7466 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7467
Yassinetaouil 46:b1a9de66ecab 7468 /* Bit 6 : P0.6 pin */
Yassinetaouil 46:b1a9de66ecab 7469 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 7470 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 7471 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7472 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7473 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7474
Yassinetaouil 46:b1a9de66ecab 7475 /* Bit 5 : P0.5 pin */
Yassinetaouil 46:b1a9de66ecab 7476 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 7477 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 7478 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7479 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7480 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7481
Yassinetaouil 46:b1a9de66ecab 7482 /* Bit 4 : P0.4 pin */
Yassinetaouil 46:b1a9de66ecab 7483 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 7484 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 7485 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7486 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7487 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7488
Yassinetaouil 46:b1a9de66ecab 7489 /* Bit 3 : P0.3 pin */
Yassinetaouil 46:b1a9de66ecab 7490 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 7491 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 7492 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7493 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7494 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7495
Yassinetaouil 46:b1a9de66ecab 7496 /* Bit 2 : P0.2 pin */
Yassinetaouil 46:b1a9de66ecab 7497 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 7498 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 7499 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7500 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7501 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7502
Yassinetaouil 46:b1a9de66ecab 7503 /* Bit 1 : P0.1 pin */
Yassinetaouil 46:b1a9de66ecab 7504 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 7505 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 7506 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7507 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7508 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7509
Yassinetaouil 46:b1a9de66ecab 7510 /* Bit 0 : P0.0 pin */
Yassinetaouil 46:b1a9de66ecab 7511 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 7512 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 7513 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7514 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7515 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7516
Yassinetaouil 46:b1a9de66ecab 7517 /* Register: GPIO_OUTCLR */
Yassinetaouil 46:b1a9de66ecab 7518 /* Description: Clear individual bits in GPIO port */
Yassinetaouil 46:b1a9de66ecab 7519
Yassinetaouil 46:b1a9de66ecab 7520 /* Bit 31 : P0.31 pin */
Yassinetaouil 46:b1a9de66ecab 7521 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7522 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7523 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7524 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7525 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7526
Yassinetaouil 46:b1a9de66ecab 7527 /* Bit 30 : P0.30 pin */
Yassinetaouil 46:b1a9de66ecab 7528 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7529 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7530 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7531 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7532 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7533
Yassinetaouil 46:b1a9de66ecab 7534 /* Bit 29 : P0.29 pin */
Yassinetaouil 46:b1a9de66ecab 7535 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7536 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7537 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7538 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7539 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7540
Yassinetaouil 46:b1a9de66ecab 7541 /* Bit 28 : P0.28 pin */
Yassinetaouil 46:b1a9de66ecab 7542 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7543 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7544 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7545 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7546 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7547
Yassinetaouil 46:b1a9de66ecab 7548 /* Bit 27 : P0.27 pin */
Yassinetaouil 46:b1a9de66ecab 7549 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7550 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7551 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7552 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7553 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7554
Yassinetaouil 46:b1a9de66ecab 7555 /* Bit 26 : P0.26 pin */
Yassinetaouil 46:b1a9de66ecab 7556 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7557 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7558 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7559 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7560 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7561
Yassinetaouil 46:b1a9de66ecab 7562 /* Bit 25 : P0.25 pin */
Yassinetaouil 46:b1a9de66ecab 7563 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7564 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7565 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7566 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7567 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7568
Yassinetaouil 46:b1a9de66ecab 7569 /* Bit 24 : P0.24 pin */
Yassinetaouil 46:b1a9de66ecab 7570 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7571 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7572 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7573 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7574 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7575
Yassinetaouil 46:b1a9de66ecab 7576 /* Bit 23 : P0.23 pin */
Yassinetaouil 46:b1a9de66ecab 7577 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7578 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7579 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7580 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7581 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7582
Yassinetaouil 46:b1a9de66ecab 7583 /* Bit 22 : P0.22 pin */
Yassinetaouil 46:b1a9de66ecab 7584 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7585 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7586 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7587 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7588 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7589
Yassinetaouil 46:b1a9de66ecab 7590 /* Bit 21 : P0.21 pin */
Yassinetaouil 46:b1a9de66ecab 7591 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 7592 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 7593 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7594 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7595 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7596
Yassinetaouil 46:b1a9de66ecab 7597 /* Bit 20 : P0.20 pin */
Yassinetaouil 46:b1a9de66ecab 7598 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 7599 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 7600 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7601 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7602 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7603
Yassinetaouil 46:b1a9de66ecab 7604 /* Bit 19 : P0.19 pin */
Yassinetaouil 46:b1a9de66ecab 7605 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 7606 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 7607 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7608 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7609 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7610
Yassinetaouil 46:b1a9de66ecab 7611 /* Bit 18 : P0.18 pin */
Yassinetaouil 46:b1a9de66ecab 7612 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 7613 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 7614 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7615 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7616 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7617
Yassinetaouil 46:b1a9de66ecab 7618 /* Bit 17 : P0.17 pin */
Yassinetaouil 46:b1a9de66ecab 7619 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 7620 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 7621 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7622 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7623 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7624
Yassinetaouil 46:b1a9de66ecab 7625 /* Bit 16 : P0.16 pin */
Yassinetaouil 46:b1a9de66ecab 7626 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 7627 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 7628 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7629 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7630 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7631
Yassinetaouil 46:b1a9de66ecab 7632 /* Bit 15 : P0.15 pin */
Yassinetaouil 46:b1a9de66ecab 7633 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 7634 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 7635 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7636 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7637 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7638
Yassinetaouil 46:b1a9de66ecab 7639 /* Bit 14 : P0.14 pin */
Yassinetaouil 46:b1a9de66ecab 7640 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 7641 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 7642 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7643 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7644 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7645
Yassinetaouil 46:b1a9de66ecab 7646 /* Bit 13 : P0.13 pin */
Yassinetaouil 46:b1a9de66ecab 7647 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 7648 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 7649 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7650 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7651 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7652
Yassinetaouil 46:b1a9de66ecab 7653 /* Bit 12 : P0.12 pin */
Yassinetaouil 46:b1a9de66ecab 7654 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 7655 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 7656 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7657 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7658 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7659
Yassinetaouil 46:b1a9de66ecab 7660 /* Bit 11 : P0.11 pin */
Yassinetaouil 46:b1a9de66ecab 7661 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 7662 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 7663 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7664 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7665 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7666
Yassinetaouil 46:b1a9de66ecab 7667 /* Bit 10 : P0.10 pin */
Yassinetaouil 46:b1a9de66ecab 7668 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 7669 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 7670 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7671 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7672 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7673
Yassinetaouil 46:b1a9de66ecab 7674 /* Bit 9 : P0.9 pin */
Yassinetaouil 46:b1a9de66ecab 7675 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 7676 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 7677 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7678 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7679 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7680
Yassinetaouil 46:b1a9de66ecab 7681 /* Bit 8 : P0.8 pin */
Yassinetaouil 46:b1a9de66ecab 7682 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 7683 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 7684 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7685 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7686 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7687
Yassinetaouil 46:b1a9de66ecab 7688 /* Bit 7 : P0.7 pin */
Yassinetaouil 46:b1a9de66ecab 7689 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 7690 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 7691 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7692 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7693 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7694
Yassinetaouil 46:b1a9de66ecab 7695 /* Bit 6 : P0.6 pin */
Yassinetaouil 46:b1a9de66ecab 7696 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 7697 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 7698 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7699 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7700 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7701
Yassinetaouil 46:b1a9de66ecab 7702 /* Bit 5 : P0.5 pin */
Yassinetaouil 46:b1a9de66ecab 7703 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 7704 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 7705 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7706 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7707 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7708
Yassinetaouil 46:b1a9de66ecab 7709 /* Bit 4 : P0.4 pin */
Yassinetaouil 46:b1a9de66ecab 7710 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 7711 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 7712 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7713 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7714 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7715
Yassinetaouil 46:b1a9de66ecab 7716 /* Bit 3 : P0.3 pin */
Yassinetaouil 46:b1a9de66ecab 7717 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 7718 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 7719 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7720 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7721 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7722
Yassinetaouil 46:b1a9de66ecab 7723 /* Bit 2 : P0.2 pin */
Yassinetaouil 46:b1a9de66ecab 7724 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 7725 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 7726 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7727 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7728 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7729
Yassinetaouil 46:b1a9de66ecab 7730 /* Bit 1 : P0.1 pin */
Yassinetaouil 46:b1a9de66ecab 7731 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 7732 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 7733 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7734 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7735 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7736
Yassinetaouil 46:b1a9de66ecab 7737 /* Bit 0 : P0.0 pin */
Yassinetaouil 46:b1a9de66ecab 7738 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 7739 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 7740 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
Yassinetaouil 46:b1a9de66ecab 7741 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
Yassinetaouil 46:b1a9de66ecab 7742 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 7743
Yassinetaouil 46:b1a9de66ecab 7744 /* Register: GPIO_IN */
Yassinetaouil 46:b1a9de66ecab 7745 /* Description: Read GPIO port */
Yassinetaouil 46:b1a9de66ecab 7746
Yassinetaouil 46:b1a9de66ecab 7747 /* Bit 31 : P0.31 pin */
Yassinetaouil 46:b1a9de66ecab 7748 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7749 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7750 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7751 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7752
Yassinetaouil 46:b1a9de66ecab 7753 /* Bit 30 : P0.30 pin */
Yassinetaouil 46:b1a9de66ecab 7754 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7755 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7756 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7757 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7758
Yassinetaouil 46:b1a9de66ecab 7759 /* Bit 29 : P0.29 pin */
Yassinetaouil 46:b1a9de66ecab 7760 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7761 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7762 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7763 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7764
Yassinetaouil 46:b1a9de66ecab 7765 /* Bit 28 : P0.28 pin */
Yassinetaouil 46:b1a9de66ecab 7766 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7767 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7768 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7769 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7770
Yassinetaouil 46:b1a9de66ecab 7771 /* Bit 27 : P0.27 pin */
Yassinetaouil 46:b1a9de66ecab 7772 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7773 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7774 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7775 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7776
Yassinetaouil 46:b1a9de66ecab 7777 /* Bit 26 : P0.26 pin */
Yassinetaouil 46:b1a9de66ecab 7778 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7779 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7780 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7781 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7782
Yassinetaouil 46:b1a9de66ecab 7783 /* Bit 25 : P0.25 pin */
Yassinetaouil 46:b1a9de66ecab 7784 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7785 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7786 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7787 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7788
Yassinetaouil 46:b1a9de66ecab 7789 /* Bit 24 : P0.24 pin */
Yassinetaouil 46:b1a9de66ecab 7790 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7791 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7792 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7793 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7794
Yassinetaouil 46:b1a9de66ecab 7795 /* Bit 23 : P0.23 pin */
Yassinetaouil 46:b1a9de66ecab 7796 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7797 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7798 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7799 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7800
Yassinetaouil 46:b1a9de66ecab 7801 /* Bit 22 : P0.22 pin */
Yassinetaouil 46:b1a9de66ecab 7802 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7803 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7804 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7805 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7806
Yassinetaouil 46:b1a9de66ecab 7807 /* Bit 21 : P0.21 pin */
Yassinetaouil 46:b1a9de66ecab 7808 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 7809 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 7810 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7811 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7812
Yassinetaouil 46:b1a9de66ecab 7813 /* Bit 20 : P0.20 pin */
Yassinetaouil 46:b1a9de66ecab 7814 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 7815 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 7816 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7817 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7818
Yassinetaouil 46:b1a9de66ecab 7819 /* Bit 19 : P0.19 pin */
Yassinetaouil 46:b1a9de66ecab 7820 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 7821 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 7822 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7823 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7824
Yassinetaouil 46:b1a9de66ecab 7825 /* Bit 18 : P0.18 pin */
Yassinetaouil 46:b1a9de66ecab 7826 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 7827 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 7828 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7829 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7830
Yassinetaouil 46:b1a9de66ecab 7831 /* Bit 17 : P0.17 pin */
Yassinetaouil 46:b1a9de66ecab 7832 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 7833 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 7834 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7835 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7836
Yassinetaouil 46:b1a9de66ecab 7837 /* Bit 16 : P0.16 pin */
Yassinetaouil 46:b1a9de66ecab 7838 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 7839 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 7840 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7841 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7842
Yassinetaouil 46:b1a9de66ecab 7843 /* Bit 15 : P0.15 pin */
Yassinetaouil 46:b1a9de66ecab 7844 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 7845 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 7846 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7847 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7848
Yassinetaouil 46:b1a9de66ecab 7849 /* Bit 14 : P0.14 pin */
Yassinetaouil 46:b1a9de66ecab 7850 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 7851 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 7852 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7853 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7854
Yassinetaouil 46:b1a9de66ecab 7855 /* Bit 13 : P0.13 pin */
Yassinetaouil 46:b1a9de66ecab 7856 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 7857 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 7858 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7859 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7860
Yassinetaouil 46:b1a9de66ecab 7861 /* Bit 12 : P0.12 pin */
Yassinetaouil 46:b1a9de66ecab 7862 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 7863 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 7864 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7865 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7866
Yassinetaouil 46:b1a9de66ecab 7867 /* Bit 11 : P0.11 pin */
Yassinetaouil 46:b1a9de66ecab 7868 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 7869 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 7870 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7871 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7872
Yassinetaouil 46:b1a9de66ecab 7873 /* Bit 10 : P0.10 pin */
Yassinetaouil 46:b1a9de66ecab 7874 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 7875 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 7876 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7877 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7878
Yassinetaouil 46:b1a9de66ecab 7879 /* Bit 9 : P0.9 pin */
Yassinetaouil 46:b1a9de66ecab 7880 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 7881 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 7882 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7883 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7884
Yassinetaouil 46:b1a9de66ecab 7885 /* Bit 8 : P0.8 pin */
Yassinetaouil 46:b1a9de66ecab 7886 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 7887 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 7888 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7889 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7890
Yassinetaouil 46:b1a9de66ecab 7891 /* Bit 7 : P0.7 pin */
Yassinetaouil 46:b1a9de66ecab 7892 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 7893 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 7894 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7895 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7896
Yassinetaouil 46:b1a9de66ecab 7897 /* Bit 6 : P0.6 pin */
Yassinetaouil 46:b1a9de66ecab 7898 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 7899 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 7900 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7901 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7902
Yassinetaouil 46:b1a9de66ecab 7903 /* Bit 5 : P0.5 pin */
Yassinetaouil 46:b1a9de66ecab 7904 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 7905 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 7906 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7907 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7908
Yassinetaouil 46:b1a9de66ecab 7909 /* Bit 4 : P0.4 pin */
Yassinetaouil 46:b1a9de66ecab 7910 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 7911 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 7912 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7913 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7914
Yassinetaouil 46:b1a9de66ecab 7915 /* Bit 3 : P0.3 pin */
Yassinetaouil 46:b1a9de66ecab 7916 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 7917 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 7918 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7919 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7920
Yassinetaouil 46:b1a9de66ecab 7921 /* Bit 2 : P0.2 pin */
Yassinetaouil 46:b1a9de66ecab 7922 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 7923 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 7924 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7925 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7926
Yassinetaouil 46:b1a9de66ecab 7927 /* Bit 1 : P0.1 pin */
Yassinetaouil 46:b1a9de66ecab 7928 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 7929 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 7930 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7931 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7932
Yassinetaouil 46:b1a9de66ecab 7933 /* Bit 0 : P0.0 pin */
Yassinetaouil 46:b1a9de66ecab 7934 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 7935 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 7936 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
Yassinetaouil 46:b1a9de66ecab 7937 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
Yassinetaouil 46:b1a9de66ecab 7938
Yassinetaouil 46:b1a9de66ecab 7939 /* Register: GPIO_DIR */
Yassinetaouil 46:b1a9de66ecab 7940 /* Description: Direction of GPIO pins */
Yassinetaouil 46:b1a9de66ecab 7941
Yassinetaouil 46:b1a9de66ecab 7942 /* Bit 31 : P0.31 pin */
Yassinetaouil 46:b1a9de66ecab 7943 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7944 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 7945 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7946 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7947
Yassinetaouil 46:b1a9de66ecab 7948 /* Bit 30 : P0.30 pin */
Yassinetaouil 46:b1a9de66ecab 7949 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7950 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 7951 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7952 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7953
Yassinetaouil 46:b1a9de66ecab 7954 /* Bit 29 : P0.29 pin */
Yassinetaouil 46:b1a9de66ecab 7955 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7956 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 7957 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7958 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7959
Yassinetaouil 46:b1a9de66ecab 7960 /* Bit 28 : P0.28 pin */
Yassinetaouil 46:b1a9de66ecab 7961 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7962 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 7963 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7964 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7965
Yassinetaouil 46:b1a9de66ecab 7966 /* Bit 27 : P0.27 pin */
Yassinetaouil 46:b1a9de66ecab 7967 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7968 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 7969 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7970 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7971
Yassinetaouil 46:b1a9de66ecab 7972 /* Bit 26 : P0.26 pin */
Yassinetaouil 46:b1a9de66ecab 7973 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7974 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 7975 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7976 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7977
Yassinetaouil 46:b1a9de66ecab 7978 /* Bit 25 : P0.25 pin */
Yassinetaouil 46:b1a9de66ecab 7979 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7980 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 7981 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7982 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7983
Yassinetaouil 46:b1a9de66ecab 7984 /* Bit 24 : P0.24 pin */
Yassinetaouil 46:b1a9de66ecab 7985 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7986 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 7987 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7988 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7989
Yassinetaouil 46:b1a9de66ecab 7990 /* Bit 23 : P0.23 pin */
Yassinetaouil 46:b1a9de66ecab 7991 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7992 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 7993 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 7994 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 7995
Yassinetaouil 46:b1a9de66ecab 7996 /* Bit 22 : P0.22 pin */
Yassinetaouil 46:b1a9de66ecab 7997 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7998 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 7999 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8000 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8001
Yassinetaouil 46:b1a9de66ecab 8002 /* Bit 21 : P0.21 pin */
Yassinetaouil 46:b1a9de66ecab 8003 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 8004 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 8005 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8006 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8007
Yassinetaouil 46:b1a9de66ecab 8008 /* Bit 20 : P0.20 pin */
Yassinetaouil 46:b1a9de66ecab 8009 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 8010 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 8011 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8012 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8013
Yassinetaouil 46:b1a9de66ecab 8014 /* Bit 19 : P0.19 pin */
Yassinetaouil 46:b1a9de66ecab 8015 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 8016 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 8017 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8018 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8019
Yassinetaouil 46:b1a9de66ecab 8020 /* Bit 18 : P0.18 pin */
Yassinetaouil 46:b1a9de66ecab 8021 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 8022 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 8023 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8024 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8025
Yassinetaouil 46:b1a9de66ecab 8026 /* Bit 17 : P0.17 pin */
Yassinetaouil 46:b1a9de66ecab 8027 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 8028 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 8029 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8030 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8031
Yassinetaouil 46:b1a9de66ecab 8032 /* Bit 16 : P0.16 pin */
Yassinetaouil 46:b1a9de66ecab 8033 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 8034 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 8035 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8036 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8037
Yassinetaouil 46:b1a9de66ecab 8038 /* Bit 15 : P0.15 pin */
Yassinetaouil 46:b1a9de66ecab 8039 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 8040 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 8041 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8042 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8043
Yassinetaouil 46:b1a9de66ecab 8044 /* Bit 14 : P0.14 pin */
Yassinetaouil 46:b1a9de66ecab 8045 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 8046 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 8047 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8048 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8049
Yassinetaouil 46:b1a9de66ecab 8050 /* Bit 13 : P0.13 pin */
Yassinetaouil 46:b1a9de66ecab 8051 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 8052 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 8053 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8054 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8055
Yassinetaouil 46:b1a9de66ecab 8056 /* Bit 12 : P0.12 pin */
Yassinetaouil 46:b1a9de66ecab 8057 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 8058 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 8059 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8060 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8061
Yassinetaouil 46:b1a9de66ecab 8062 /* Bit 11 : P0.11 pin */
Yassinetaouil 46:b1a9de66ecab 8063 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 8064 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 8065 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8066 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8067
Yassinetaouil 46:b1a9de66ecab 8068 /* Bit 10 : P0.10 pin */
Yassinetaouil 46:b1a9de66ecab 8069 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 8070 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 8071 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8072 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8073
Yassinetaouil 46:b1a9de66ecab 8074 /* Bit 9 : P0.9 pin */
Yassinetaouil 46:b1a9de66ecab 8075 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 8076 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 8077 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8078 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8079
Yassinetaouil 46:b1a9de66ecab 8080 /* Bit 8 : P0.8 pin */
Yassinetaouil 46:b1a9de66ecab 8081 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 8082 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 8083 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8084 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8085
Yassinetaouil 46:b1a9de66ecab 8086 /* Bit 7 : P0.7 pin */
Yassinetaouil 46:b1a9de66ecab 8087 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 8088 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 8089 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8090 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8091
Yassinetaouil 46:b1a9de66ecab 8092 /* Bit 6 : P0.6 pin */
Yassinetaouil 46:b1a9de66ecab 8093 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 8094 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 8095 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8096 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8097
Yassinetaouil 46:b1a9de66ecab 8098 /* Bit 5 : P0.5 pin */
Yassinetaouil 46:b1a9de66ecab 8099 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 8100 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 8101 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8102 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8103
Yassinetaouil 46:b1a9de66ecab 8104 /* Bit 4 : P0.4 pin */
Yassinetaouil 46:b1a9de66ecab 8105 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 8106 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 8107 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8108 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8109
Yassinetaouil 46:b1a9de66ecab 8110 /* Bit 3 : P0.3 pin */
Yassinetaouil 46:b1a9de66ecab 8111 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 8112 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 8113 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8114 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8115
Yassinetaouil 46:b1a9de66ecab 8116 /* Bit 2 : P0.2 pin */
Yassinetaouil 46:b1a9de66ecab 8117 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 8118 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 8119 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8120 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8121
Yassinetaouil 46:b1a9de66ecab 8122 /* Bit 1 : P0.1 pin */
Yassinetaouil 46:b1a9de66ecab 8123 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 8124 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 8125 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8126 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8127
Yassinetaouil 46:b1a9de66ecab 8128 /* Bit 0 : P0.0 pin */
Yassinetaouil 46:b1a9de66ecab 8129 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 8130 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 8131 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
Yassinetaouil 46:b1a9de66ecab 8132 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
Yassinetaouil 46:b1a9de66ecab 8133
Yassinetaouil 46:b1a9de66ecab 8134 /* Register: GPIO_DIRSET */
Yassinetaouil 46:b1a9de66ecab 8135 /* Description: DIR set register */
Yassinetaouil 46:b1a9de66ecab 8136
Yassinetaouil 46:b1a9de66ecab 8137 /* Bit 31 : Set as output pin 31 */
Yassinetaouil 46:b1a9de66ecab 8138 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 8139 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 8140 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8141 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8142 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8143
Yassinetaouil 46:b1a9de66ecab 8144 /* Bit 30 : Set as output pin 30 */
Yassinetaouil 46:b1a9de66ecab 8145 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 8146 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 8147 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8148 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8149 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8150
Yassinetaouil 46:b1a9de66ecab 8151 /* Bit 29 : Set as output pin 29 */
Yassinetaouil 46:b1a9de66ecab 8152 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 8153 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 8154 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8155 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8156 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8157
Yassinetaouil 46:b1a9de66ecab 8158 /* Bit 28 : Set as output pin 28 */
Yassinetaouil 46:b1a9de66ecab 8159 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 8160 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 8161 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8162 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8163 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8164
Yassinetaouil 46:b1a9de66ecab 8165 /* Bit 27 : Set as output pin 27 */
Yassinetaouil 46:b1a9de66ecab 8166 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 8167 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 8168 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8169 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8170 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8171
Yassinetaouil 46:b1a9de66ecab 8172 /* Bit 26 : Set as output pin 26 */
Yassinetaouil 46:b1a9de66ecab 8173 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 8174 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 8175 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8176 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8177 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8178
Yassinetaouil 46:b1a9de66ecab 8179 /* Bit 25 : Set as output pin 25 */
Yassinetaouil 46:b1a9de66ecab 8180 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 8181 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 8182 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8183 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8184 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8185
Yassinetaouil 46:b1a9de66ecab 8186 /* Bit 24 : Set as output pin 24 */
Yassinetaouil 46:b1a9de66ecab 8187 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 8188 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 8189 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8190 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8191 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8192
Yassinetaouil 46:b1a9de66ecab 8193 /* Bit 23 : Set as output pin 23 */
Yassinetaouil 46:b1a9de66ecab 8194 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 8195 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 8196 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8197 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8198 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8199
Yassinetaouil 46:b1a9de66ecab 8200 /* Bit 22 : Set as output pin 22 */
Yassinetaouil 46:b1a9de66ecab 8201 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 8202 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 8203 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8204 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8205 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8206
Yassinetaouil 46:b1a9de66ecab 8207 /* Bit 21 : Set as output pin 21 */
Yassinetaouil 46:b1a9de66ecab 8208 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 8209 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 8210 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8211 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8212 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8213
Yassinetaouil 46:b1a9de66ecab 8214 /* Bit 20 : Set as output pin 20 */
Yassinetaouil 46:b1a9de66ecab 8215 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 8216 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 8217 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8218 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8219 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8220
Yassinetaouil 46:b1a9de66ecab 8221 /* Bit 19 : Set as output pin 19 */
Yassinetaouil 46:b1a9de66ecab 8222 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 8223 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 8224 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8225 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8226 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8227
Yassinetaouil 46:b1a9de66ecab 8228 /* Bit 18 : Set as output pin 18 */
Yassinetaouil 46:b1a9de66ecab 8229 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 8230 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 8231 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8232 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8233 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8234
Yassinetaouil 46:b1a9de66ecab 8235 /* Bit 17 : Set as output pin 17 */
Yassinetaouil 46:b1a9de66ecab 8236 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 8237 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 8238 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8239 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8240 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8241
Yassinetaouil 46:b1a9de66ecab 8242 /* Bit 16 : Set as output pin 16 */
Yassinetaouil 46:b1a9de66ecab 8243 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 8244 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 8245 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8246 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8247 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8248
Yassinetaouil 46:b1a9de66ecab 8249 /* Bit 15 : Set as output pin 15 */
Yassinetaouil 46:b1a9de66ecab 8250 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 8251 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 8252 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8253 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8254 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8255
Yassinetaouil 46:b1a9de66ecab 8256 /* Bit 14 : Set as output pin 14 */
Yassinetaouil 46:b1a9de66ecab 8257 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 8258 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 8259 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8260 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8261 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8262
Yassinetaouil 46:b1a9de66ecab 8263 /* Bit 13 : Set as output pin 13 */
Yassinetaouil 46:b1a9de66ecab 8264 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 8265 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 8266 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8267 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8268 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8269
Yassinetaouil 46:b1a9de66ecab 8270 /* Bit 12 : Set as output pin 12 */
Yassinetaouil 46:b1a9de66ecab 8271 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 8272 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 8273 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8274 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8275 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8276
Yassinetaouil 46:b1a9de66ecab 8277 /* Bit 11 : Set as output pin 11 */
Yassinetaouil 46:b1a9de66ecab 8278 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 8279 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 8280 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8281 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8282 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8283
Yassinetaouil 46:b1a9de66ecab 8284 /* Bit 10 : Set as output pin 10 */
Yassinetaouil 46:b1a9de66ecab 8285 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 8286 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 8287 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8288 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8289 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8290
Yassinetaouil 46:b1a9de66ecab 8291 /* Bit 9 : Set as output pin 9 */
Yassinetaouil 46:b1a9de66ecab 8292 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 8293 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 8294 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8295 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8296 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8297
Yassinetaouil 46:b1a9de66ecab 8298 /* Bit 8 : Set as output pin 8 */
Yassinetaouil 46:b1a9de66ecab 8299 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 8300 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 8301 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8302 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8303 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8304
Yassinetaouil 46:b1a9de66ecab 8305 /* Bit 7 : Set as output pin 7 */
Yassinetaouil 46:b1a9de66ecab 8306 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 8307 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 8308 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8309 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8310 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8311
Yassinetaouil 46:b1a9de66ecab 8312 /* Bit 6 : Set as output pin 6 */
Yassinetaouil 46:b1a9de66ecab 8313 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 8314 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 8315 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8316 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8317 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8318
Yassinetaouil 46:b1a9de66ecab 8319 /* Bit 5 : Set as output pin 5 */
Yassinetaouil 46:b1a9de66ecab 8320 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 8321 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 8322 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8323 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8324 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8325
Yassinetaouil 46:b1a9de66ecab 8326 /* Bit 4 : Set as output pin 4 */
Yassinetaouil 46:b1a9de66ecab 8327 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 8328 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 8329 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8330 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8331 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8332
Yassinetaouil 46:b1a9de66ecab 8333 /* Bit 3 : Set as output pin 3 */
Yassinetaouil 46:b1a9de66ecab 8334 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 8335 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 8336 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8337 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8338 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8339
Yassinetaouil 46:b1a9de66ecab 8340 /* Bit 2 : Set as output pin 2 */
Yassinetaouil 46:b1a9de66ecab 8341 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 8342 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 8343 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8344 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8345 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8346
Yassinetaouil 46:b1a9de66ecab 8347 /* Bit 1 : Set as output pin 1 */
Yassinetaouil 46:b1a9de66ecab 8348 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 8349 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 8350 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8351 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8352 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8353
Yassinetaouil 46:b1a9de66ecab 8354 /* Bit 0 : Set as output pin 0 */
Yassinetaouil 46:b1a9de66ecab 8355 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 8356 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 8357 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8358 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8359 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8360
Yassinetaouil 46:b1a9de66ecab 8361 /* Register: GPIO_DIRCLR */
Yassinetaouil 46:b1a9de66ecab 8362 /* Description: DIR clear register */
Yassinetaouil 46:b1a9de66ecab 8363
Yassinetaouil 46:b1a9de66ecab 8364 /* Bit 31 : Set as input pin 31 */
Yassinetaouil 46:b1a9de66ecab 8365 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 8366 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 8367 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8368 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8369 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8370
Yassinetaouil 46:b1a9de66ecab 8371 /* Bit 30 : Set as input pin 30 */
Yassinetaouil 46:b1a9de66ecab 8372 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 8373 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 8374 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8375 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8376 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8377
Yassinetaouil 46:b1a9de66ecab 8378 /* Bit 29 : Set as input pin 29 */
Yassinetaouil 46:b1a9de66ecab 8379 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 8380 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 8381 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8382 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8383 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8384
Yassinetaouil 46:b1a9de66ecab 8385 /* Bit 28 : Set as input pin 28 */
Yassinetaouil 46:b1a9de66ecab 8386 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 8387 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 8388 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8389 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8390 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8391
Yassinetaouil 46:b1a9de66ecab 8392 /* Bit 27 : Set as input pin 27 */
Yassinetaouil 46:b1a9de66ecab 8393 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 8394 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 8395 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8396 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8397 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8398
Yassinetaouil 46:b1a9de66ecab 8399 /* Bit 26 : Set as input pin 26 */
Yassinetaouil 46:b1a9de66ecab 8400 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 8401 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 8402 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8403 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8404 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8405
Yassinetaouil 46:b1a9de66ecab 8406 /* Bit 25 : Set as input pin 25 */
Yassinetaouil 46:b1a9de66ecab 8407 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 8408 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 8409 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8410 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8411 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8412
Yassinetaouil 46:b1a9de66ecab 8413 /* Bit 24 : Set as input pin 24 */
Yassinetaouil 46:b1a9de66ecab 8414 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 8415 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 8416 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8417 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8418 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8419
Yassinetaouil 46:b1a9de66ecab 8420 /* Bit 23 : Set as input pin 23 */
Yassinetaouil 46:b1a9de66ecab 8421 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 8422 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 8423 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8424 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8425 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8426
Yassinetaouil 46:b1a9de66ecab 8427 /* Bit 22 : Set as input pin 22 */
Yassinetaouil 46:b1a9de66ecab 8428 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 8429 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 8430 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8431 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8432 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8433
Yassinetaouil 46:b1a9de66ecab 8434 /* Bit 21 : Set as input pin 21 */
Yassinetaouil 46:b1a9de66ecab 8435 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 8436 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 8437 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8438 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8439 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8440
Yassinetaouil 46:b1a9de66ecab 8441 /* Bit 20 : Set as input pin 20 */
Yassinetaouil 46:b1a9de66ecab 8442 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 8443 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 8444 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8445 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8446 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8447
Yassinetaouil 46:b1a9de66ecab 8448 /* Bit 19 : Set as input pin 19 */
Yassinetaouil 46:b1a9de66ecab 8449 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 8450 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 8451 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8452 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8453 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8454
Yassinetaouil 46:b1a9de66ecab 8455 /* Bit 18 : Set as input pin 18 */
Yassinetaouil 46:b1a9de66ecab 8456 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 8457 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 8458 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8459 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8460 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8461
Yassinetaouil 46:b1a9de66ecab 8462 /* Bit 17 : Set as input pin 17 */
Yassinetaouil 46:b1a9de66ecab 8463 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 8464 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 8465 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8466 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8467 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8468
Yassinetaouil 46:b1a9de66ecab 8469 /* Bit 16 : Set as input pin 16 */
Yassinetaouil 46:b1a9de66ecab 8470 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 8471 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 8472 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8473 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8474 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8475
Yassinetaouil 46:b1a9de66ecab 8476 /* Bit 15 : Set as input pin 15 */
Yassinetaouil 46:b1a9de66ecab 8477 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 8478 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 8479 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8480 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8481 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8482
Yassinetaouil 46:b1a9de66ecab 8483 /* Bit 14 : Set as input pin 14 */
Yassinetaouil 46:b1a9de66ecab 8484 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 8485 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 8486 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8487 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8488 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8489
Yassinetaouil 46:b1a9de66ecab 8490 /* Bit 13 : Set as input pin 13 */
Yassinetaouil 46:b1a9de66ecab 8491 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 8492 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 8493 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8494 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8495 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8496
Yassinetaouil 46:b1a9de66ecab 8497 /* Bit 12 : Set as input pin 12 */
Yassinetaouil 46:b1a9de66ecab 8498 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 8499 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 8500 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8501 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8502 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8503
Yassinetaouil 46:b1a9de66ecab 8504 /* Bit 11 : Set as input pin 11 */
Yassinetaouil 46:b1a9de66ecab 8505 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 8506 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 8507 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8508 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8509 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8510
Yassinetaouil 46:b1a9de66ecab 8511 /* Bit 10 : Set as input pin 10 */
Yassinetaouil 46:b1a9de66ecab 8512 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 8513 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 8514 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8515 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8516 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8517
Yassinetaouil 46:b1a9de66ecab 8518 /* Bit 9 : Set as input pin 9 */
Yassinetaouil 46:b1a9de66ecab 8519 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 8520 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 8521 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8522 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8523 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8524
Yassinetaouil 46:b1a9de66ecab 8525 /* Bit 8 : Set as input pin 8 */
Yassinetaouil 46:b1a9de66ecab 8526 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 8527 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 8528 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8529 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8530 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8531
Yassinetaouil 46:b1a9de66ecab 8532 /* Bit 7 : Set as input pin 7 */
Yassinetaouil 46:b1a9de66ecab 8533 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 8534 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 8535 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8536 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8537 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8538
Yassinetaouil 46:b1a9de66ecab 8539 /* Bit 6 : Set as input pin 6 */
Yassinetaouil 46:b1a9de66ecab 8540 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 8541 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 8542 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8543 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8544 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8545
Yassinetaouil 46:b1a9de66ecab 8546 /* Bit 5 : Set as input pin 5 */
Yassinetaouil 46:b1a9de66ecab 8547 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 8548 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 8549 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8550 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8551 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8552
Yassinetaouil 46:b1a9de66ecab 8553 /* Bit 4 : Set as input pin 4 */
Yassinetaouil 46:b1a9de66ecab 8554 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 8555 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 8556 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8557 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8558 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8559
Yassinetaouil 46:b1a9de66ecab 8560 /* Bit 3 : Set as input pin 3 */
Yassinetaouil 46:b1a9de66ecab 8561 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 8562 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 8563 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8564 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8565 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8566
Yassinetaouil 46:b1a9de66ecab 8567 /* Bit 2 : Set as input pin 2 */
Yassinetaouil 46:b1a9de66ecab 8568 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 8569 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 8570 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8571 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8572 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8573
Yassinetaouil 46:b1a9de66ecab 8574 /* Bit 1 : Set as input pin 1 */
Yassinetaouil 46:b1a9de66ecab 8575 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 8576 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 8577 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8578 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8579 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8580
Yassinetaouil 46:b1a9de66ecab 8581 /* Bit 0 : Set as input pin 0 */
Yassinetaouil 46:b1a9de66ecab 8582 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 8583 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 8584 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
Yassinetaouil 46:b1a9de66ecab 8585 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
Yassinetaouil 46:b1a9de66ecab 8586 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 8587
Yassinetaouil 46:b1a9de66ecab 8588 /* Register: GPIO_LATCH */
Yassinetaouil 46:b1a9de66ecab 8589 /* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
Yassinetaouil 46:b1a9de66ecab 8590
Yassinetaouil 46:b1a9de66ecab 8591 /* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8592 #define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 8593 #define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Yassinetaouil 46:b1a9de66ecab 8594 #define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8595 #define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8596
Yassinetaouil 46:b1a9de66ecab 8597 /* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8598 #define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 8599 #define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Yassinetaouil 46:b1a9de66ecab 8600 #define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8601 #define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8602
Yassinetaouil 46:b1a9de66ecab 8603 /* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8604 #define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 8605 #define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Yassinetaouil 46:b1a9de66ecab 8606 #define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8607 #define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8608
Yassinetaouil 46:b1a9de66ecab 8609 /* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8610 #define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 8611 #define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Yassinetaouil 46:b1a9de66ecab 8612 #define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8613 #define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8614
Yassinetaouil 46:b1a9de66ecab 8615 /* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8616 #define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 8617 #define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Yassinetaouil 46:b1a9de66ecab 8618 #define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8619 #define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8620
Yassinetaouil 46:b1a9de66ecab 8621 /* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8622 #define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 8623 #define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Yassinetaouil 46:b1a9de66ecab 8624 #define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8625 #define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8626
Yassinetaouil 46:b1a9de66ecab 8627 /* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8628 #define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 8629 #define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Yassinetaouil 46:b1a9de66ecab 8630 #define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8631 #define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8632
Yassinetaouil 46:b1a9de66ecab 8633 /* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8634 #define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 8635 #define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Yassinetaouil 46:b1a9de66ecab 8636 #define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8637 #define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8638
Yassinetaouil 46:b1a9de66ecab 8639 /* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8640 #define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 8641 #define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Yassinetaouil 46:b1a9de66ecab 8642 #define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8643 #define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8644
Yassinetaouil 46:b1a9de66ecab 8645 /* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8646 #define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 8647 #define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Yassinetaouil 46:b1a9de66ecab 8648 #define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8649 #define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8650
Yassinetaouil 46:b1a9de66ecab 8651 /* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8652 #define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 8653 #define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Yassinetaouil 46:b1a9de66ecab 8654 #define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8655 #define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8656
Yassinetaouil 46:b1a9de66ecab 8657 /* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8658 #define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 8659 #define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Yassinetaouil 46:b1a9de66ecab 8660 #define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8661 #define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8662
Yassinetaouil 46:b1a9de66ecab 8663 /* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8664 #define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 8665 #define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Yassinetaouil 46:b1a9de66ecab 8666 #define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8667 #define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8668
Yassinetaouil 46:b1a9de66ecab 8669 /* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8670 #define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 8671 #define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Yassinetaouil 46:b1a9de66ecab 8672 #define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8673 #define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8674
Yassinetaouil 46:b1a9de66ecab 8675 /* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8676 #define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 8677 #define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Yassinetaouil 46:b1a9de66ecab 8678 #define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8679 #define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8680
Yassinetaouil 46:b1a9de66ecab 8681 /* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8682 #define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 8683 #define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Yassinetaouil 46:b1a9de66ecab 8684 #define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8685 #define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8686
Yassinetaouil 46:b1a9de66ecab 8687 /* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8688 #define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 8689 #define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Yassinetaouil 46:b1a9de66ecab 8690 #define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8691 #define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8692
Yassinetaouil 46:b1a9de66ecab 8693 /* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8694 #define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 8695 #define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Yassinetaouil 46:b1a9de66ecab 8696 #define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8697 #define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8698
Yassinetaouil 46:b1a9de66ecab 8699 /* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8700 #define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 8701 #define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Yassinetaouil 46:b1a9de66ecab 8702 #define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8703 #define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8704
Yassinetaouil 46:b1a9de66ecab 8705 /* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8706 #define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 8707 #define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Yassinetaouil 46:b1a9de66ecab 8708 #define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8709 #define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8710
Yassinetaouil 46:b1a9de66ecab 8711 /* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8712 #define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 8713 #define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Yassinetaouil 46:b1a9de66ecab 8714 #define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8715 #define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8716
Yassinetaouil 46:b1a9de66ecab 8717 /* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8718 #define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 8719 #define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Yassinetaouil 46:b1a9de66ecab 8720 #define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8721 #define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8722
Yassinetaouil 46:b1a9de66ecab 8723 /* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8724 #define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 8725 #define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Yassinetaouil 46:b1a9de66ecab 8726 #define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8727 #define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8728
Yassinetaouil 46:b1a9de66ecab 8729 /* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8730 #define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 8731 #define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Yassinetaouil 46:b1a9de66ecab 8732 #define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8733 #define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8734
Yassinetaouil 46:b1a9de66ecab 8735 /* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8736 #define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 8737 #define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Yassinetaouil 46:b1a9de66ecab 8738 #define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8739 #define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8740
Yassinetaouil 46:b1a9de66ecab 8741 /* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8742 #define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 8743 #define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Yassinetaouil 46:b1a9de66ecab 8744 #define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8745 #define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8746
Yassinetaouil 46:b1a9de66ecab 8747 /* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8748 #define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 8749 #define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Yassinetaouil 46:b1a9de66ecab 8750 #define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8751 #define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8752
Yassinetaouil 46:b1a9de66ecab 8753 /* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8754 #define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 8755 #define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Yassinetaouil 46:b1a9de66ecab 8756 #define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8757 #define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8758
Yassinetaouil 46:b1a9de66ecab 8759 /* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8760 #define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 8761 #define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Yassinetaouil 46:b1a9de66ecab 8762 #define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8763 #define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8764
Yassinetaouil 46:b1a9de66ecab 8765 /* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8766 #define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 8767 #define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Yassinetaouil 46:b1a9de66ecab 8768 #define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8769 #define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8770
Yassinetaouil 46:b1a9de66ecab 8771 /* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8772 #define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 8773 #define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Yassinetaouil 46:b1a9de66ecab 8774 #define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8775 #define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8776
Yassinetaouil 46:b1a9de66ecab 8777 /* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
Yassinetaouil 46:b1a9de66ecab 8778 #define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 8779 #define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Yassinetaouil 46:b1a9de66ecab 8780 #define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
Yassinetaouil 46:b1a9de66ecab 8781 #define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
Yassinetaouil 46:b1a9de66ecab 8782
Yassinetaouil 46:b1a9de66ecab 8783 /* Register: GPIO_DETECTMODE */
Yassinetaouil 46:b1a9de66ecab 8784 /* Description: Select between default DETECT signal behaviour and LDETECT mode */
Yassinetaouil 46:b1a9de66ecab 8785
Yassinetaouil 46:b1a9de66ecab 8786 /* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
Yassinetaouil 46:b1a9de66ecab 8787 #define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
Yassinetaouil 46:b1a9de66ecab 8788 #define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
Yassinetaouil 46:b1a9de66ecab 8789 #define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
Yassinetaouil 46:b1a9de66ecab 8790 #define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
Yassinetaouil 46:b1a9de66ecab 8791
Yassinetaouil 46:b1a9de66ecab 8792 /* Register: GPIO_PIN_CNF */
Yassinetaouil 46:b1a9de66ecab 8793 /* Description: Description collection[0]: Configuration of GPIO pins */
Yassinetaouil 46:b1a9de66ecab 8794
Yassinetaouil 46:b1a9de66ecab 8795 /* Bits 17..16 : Pin sensing mechanism */
Yassinetaouil 46:b1a9de66ecab 8796 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
Yassinetaouil 46:b1a9de66ecab 8797 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
Yassinetaouil 46:b1a9de66ecab 8798 #define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 8799 #define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
Yassinetaouil 46:b1a9de66ecab 8800 #define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
Yassinetaouil 46:b1a9de66ecab 8801
Yassinetaouil 46:b1a9de66ecab 8802 /* Bits 10..8 : Drive configuration */
Yassinetaouil 46:b1a9de66ecab 8803 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
Yassinetaouil 46:b1a9de66ecab 8804 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
Yassinetaouil 46:b1a9de66ecab 8805 #define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
Yassinetaouil 46:b1a9de66ecab 8806 #define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
Yassinetaouil 46:b1a9de66ecab 8807 #define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
Yassinetaouil 46:b1a9de66ecab 8808 #define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
Yassinetaouil 46:b1a9de66ecab 8809 #define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
Yassinetaouil 46:b1a9de66ecab 8810 #define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
Yassinetaouil 46:b1a9de66ecab 8811 #define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
Yassinetaouil 46:b1a9de66ecab 8812 #define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
Yassinetaouil 46:b1a9de66ecab 8813
Yassinetaouil 46:b1a9de66ecab 8814 /* Bits 3..2 : Pull configuration */
Yassinetaouil 46:b1a9de66ecab 8815 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
Yassinetaouil 46:b1a9de66ecab 8816 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
Yassinetaouil 46:b1a9de66ecab 8817 #define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
Yassinetaouil 46:b1a9de66ecab 8818 #define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
Yassinetaouil 46:b1a9de66ecab 8819 #define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
Yassinetaouil 46:b1a9de66ecab 8820
Yassinetaouil 46:b1a9de66ecab 8821 /* Bit 1 : Connect or disconnect input buffer */
Yassinetaouil 46:b1a9de66ecab 8822 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
Yassinetaouil 46:b1a9de66ecab 8823 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
Yassinetaouil 46:b1a9de66ecab 8824 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
Yassinetaouil 46:b1a9de66ecab 8825 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
Yassinetaouil 46:b1a9de66ecab 8826
Yassinetaouil 46:b1a9de66ecab 8827 /* Bit 0 : Pin direction. Same physical register as DIR register */
Yassinetaouil 46:b1a9de66ecab 8828 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
Yassinetaouil 46:b1a9de66ecab 8829 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
Yassinetaouil 46:b1a9de66ecab 8830 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
Yassinetaouil 46:b1a9de66ecab 8831 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
Yassinetaouil 46:b1a9de66ecab 8832
Yassinetaouil 46:b1a9de66ecab 8833
Yassinetaouil 46:b1a9de66ecab 8834 /* Peripheral: PDM */
Yassinetaouil 46:b1a9de66ecab 8835 /* Description: Pulse Density Modulation (Digital Microphone) Interface */
Yassinetaouil 46:b1a9de66ecab 8836
Yassinetaouil 46:b1a9de66ecab 8837 /* Register: PDM_INTEN */
Yassinetaouil 46:b1a9de66ecab 8838 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 8839
Yassinetaouil 46:b1a9de66ecab 8840 /* Bit 2 : Enable or disable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 8841 #define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 8842 #define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 8843 #define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 8844 #define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 8845
Yassinetaouil 46:b1a9de66ecab 8846 /* Bit 1 : Enable or disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 8847 #define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 8848 #define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 8849 #define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 8850 #define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 8851
Yassinetaouil 46:b1a9de66ecab 8852 /* Bit 0 : Enable or disable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 8853 #define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 8854 #define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 8855 #define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 8856 #define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 8857
Yassinetaouil 46:b1a9de66ecab 8858 /* Register: PDM_INTENSET */
Yassinetaouil 46:b1a9de66ecab 8859 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 8860
Yassinetaouil 46:b1a9de66ecab 8861 /* Bit 2 : Write '1' to Enable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 8862 #define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 8863 #define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 8864 #define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 8865 #define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 8866 #define PDM_INTENSET_END_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 8867
Yassinetaouil 46:b1a9de66ecab 8868 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 8869 #define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 8870 #define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 8871 #define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 8872 #define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 8873 #define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 8874
Yassinetaouil 46:b1a9de66ecab 8875 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 8876 #define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 8877 #define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 8878 #define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 8879 #define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 8880 #define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 8881
Yassinetaouil 46:b1a9de66ecab 8882 /* Register: PDM_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 8883 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 8884
Yassinetaouil 46:b1a9de66ecab 8885 /* Bit 2 : Write '1' to Disable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 8886 #define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 8887 #define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 8888 #define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 8889 #define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 8890 #define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 8891
Yassinetaouil 46:b1a9de66ecab 8892 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 8893 #define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 8894 #define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 8895 #define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 8896 #define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 8897 #define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 8898
Yassinetaouil 46:b1a9de66ecab 8899 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 8900 #define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 8901 #define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 8902 #define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 8903 #define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 8904 #define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 8905
Yassinetaouil 46:b1a9de66ecab 8906 /* Register: PDM_ENABLE */
Yassinetaouil 46:b1a9de66ecab 8907 /* Description: PDM module enable register */
Yassinetaouil 46:b1a9de66ecab 8908
Yassinetaouil 46:b1a9de66ecab 8909 /* Bit 0 : Enable or disable PDM module */
Yassinetaouil 46:b1a9de66ecab 8910 #define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 8911 #define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 8912 #define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 8913 #define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 8914
Yassinetaouil 46:b1a9de66ecab 8915 /* Register: PDM_PDMCLKCTRL */
Yassinetaouil 46:b1a9de66ecab 8916 /* Description: PDM clock generator control */
Yassinetaouil 46:b1a9de66ecab 8917
Yassinetaouil 46:b1a9de66ecab 8918 /* Bits 31..0 : PDM_CLK frequency */
Yassinetaouil 46:b1a9de66ecab 8919 #define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
Yassinetaouil 46:b1a9de66ecab 8920 #define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
Yassinetaouil 46:b1a9de66ecab 8921 #define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
Yassinetaouil 46:b1a9de66ecab 8922 #define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
Yassinetaouil 46:b1a9de66ecab 8923 #define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
Yassinetaouil 46:b1a9de66ecab 8924
Yassinetaouil 46:b1a9de66ecab 8925 /* Register: PDM_MODE */
Yassinetaouil 46:b1a9de66ecab 8926 /* Description: Defines the routing of the connected PDM microphones' signals */
Yassinetaouil 46:b1a9de66ecab 8927
Yassinetaouil 46:b1a9de66ecab 8928 /* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
Yassinetaouil 46:b1a9de66ecab 8929 #define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
Yassinetaouil 46:b1a9de66ecab 8930 #define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
Yassinetaouil 46:b1a9de66ecab 8931 #define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
Yassinetaouil 46:b1a9de66ecab 8932 #define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
Yassinetaouil 46:b1a9de66ecab 8933
Yassinetaouil 46:b1a9de66ecab 8934 /* Bit 0 : Mono or stereo operation */
Yassinetaouil 46:b1a9de66ecab 8935 #define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
Yassinetaouil 46:b1a9de66ecab 8936 #define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
Yassinetaouil 46:b1a9de66ecab 8937 #define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
Yassinetaouil 46:b1a9de66ecab 8938 #define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
Yassinetaouil 46:b1a9de66ecab 8939
Yassinetaouil 46:b1a9de66ecab 8940 /* Register: PDM_GAINL */
Yassinetaouil 46:b1a9de66ecab 8941 /* Description: Left output gain adjustment */
Yassinetaouil 46:b1a9de66ecab 8942
Yassinetaouil 46:b1a9de66ecab 8943 /* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
Yassinetaouil 46:b1a9de66ecab 8944 #define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
Yassinetaouil 46:b1a9de66ecab 8945 #define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
Yassinetaouil 46:b1a9de66ecab 8946 #define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
Yassinetaouil 46:b1a9de66ecab 8947 #define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
Yassinetaouil 46:b1a9de66ecab 8948 #define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
Yassinetaouil 46:b1a9de66ecab 8949
Yassinetaouil 46:b1a9de66ecab 8950 /* Register: PDM_GAINR */
Yassinetaouil 46:b1a9de66ecab 8951 /* Description: Right output gain adjustment */
Yassinetaouil 46:b1a9de66ecab 8952
Yassinetaouil 46:b1a9de66ecab 8953 /* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
Yassinetaouil 46:b1a9de66ecab 8954 #define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
Yassinetaouil 46:b1a9de66ecab 8955 #define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
Yassinetaouil 46:b1a9de66ecab 8956 #define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
Yassinetaouil 46:b1a9de66ecab 8957 #define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
Yassinetaouil 46:b1a9de66ecab 8958 #define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
Yassinetaouil 46:b1a9de66ecab 8959
Yassinetaouil 46:b1a9de66ecab 8960 /* Register: PDM_PSEL_CLK */
Yassinetaouil 46:b1a9de66ecab 8961 /* Description: Pin number configuration for PDM CLK signal */
Yassinetaouil 46:b1a9de66ecab 8962
Yassinetaouil 46:b1a9de66ecab 8963 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 8964 #define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 8965 #define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 8966 #define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 8967 #define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 8968
Yassinetaouil 46:b1a9de66ecab 8969 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 8970 #define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 8971 #define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 8972
Yassinetaouil 46:b1a9de66ecab 8973 /* Register: PDM_PSEL_DIN */
Yassinetaouil 46:b1a9de66ecab 8974 /* Description: Pin number configuration for PDM DIN signal */
Yassinetaouil 46:b1a9de66ecab 8975
Yassinetaouil 46:b1a9de66ecab 8976 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 8977 #define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 8978 #define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 8979 #define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 8980 #define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 8981
Yassinetaouil 46:b1a9de66ecab 8982 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 8983 #define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 8984 #define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 8985
Yassinetaouil 46:b1a9de66ecab 8986 /* Register: PDM_SAMPLE_PTR */
Yassinetaouil 46:b1a9de66ecab 8987 /* Description: RAM address pointer to write samples to with EasyDMA */
Yassinetaouil 46:b1a9de66ecab 8988
Yassinetaouil 46:b1a9de66ecab 8989 /* Bits 31..0 : Address to write PDM samples to over DMA */
Yassinetaouil 46:b1a9de66ecab 8990 #define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
Yassinetaouil 46:b1a9de66ecab 8991 #define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
Yassinetaouil 46:b1a9de66ecab 8992
Yassinetaouil 46:b1a9de66ecab 8993 /* Register: PDM_SAMPLE_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 8994 /* Description: Number of samples to allocate memory for in EasyDMA mode */
Yassinetaouil 46:b1a9de66ecab 8995
Yassinetaouil 46:b1a9de66ecab 8996 /* Bits 14..0 : Length of DMA RAM allocation in number of samples */
Yassinetaouil 46:b1a9de66ecab 8997 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
Yassinetaouil 46:b1a9de66ecab 8998 #define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
Yassinetaouil 46:b1a9de66ecab 8999
Yassinetaouil 46:b1a9de66ecab 9000
Yassinetaouil 46:b1a9de66ecab 9001 /* Peripheral: POWER */
Yassinetaouil 46:b1a9de66ecab 9002 /* Description: Power control */
Yassinetaouil 46:b1a9de66ecab 9003
Yassinetaouil 46:b1a9de66ecab 9004 /* Register: POWER_INTENSET */
Yassinetaouil 46:b1a9de66ecab 9005 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 9006
Yassinetaouil 46:b1a9de66ecab 9007 /* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
Yassinetaouil 46:b1a9de66ecab 9008 #define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
Yassinetaouil 46:b1a9de66ecab 9009 #define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
Yassinetaouil 46:b1a9de66ecab 9010 #define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 9011 #define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 9012 #define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 9013
Yassinetaouil 46:b1a9de66ecab 9014 /* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
Yassinetaouil 46:b1a9de66ecab 9015 #define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
Yassinetaouil 46:b1a9de66ecab 9016 #define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
Yassinetaouil 46:b1a9de66ecab 9017 #define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 9018 #define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 9019 #define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 9020
Yassinetaouil 46:b1a9de66ecab 9021 /* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
Yassinetaouil 46:b1a9de66ecab 9022 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
Yassinetaouil 46:b1a9de66ecab 9023 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
Yassinetaouil 46:b1a9de66ecab 9024 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 9025 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 9026 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 9027
Yassinetaouil 46:b1a9de66ecab 9028 /* Register: POWER_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 9029 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 9030
Yassinetaouil 46:b1a9de66ecab 9031 /* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
Yassinetaouil 46:b1a9de66ecab 9032 #define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
Yassinetaouil 46:b1a9de66ecab 9033 #define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
Yassinetaouil 46:b1a9de66ecab 9034 #define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 9035 #define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 9036 #define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 9037
Yassinetaouil 46:b1a9de66ecab 9038 /* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
Yassinetaouil 46:b1a9de66ecab 9039 #define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
Yassinetaouil 46:b1a9de66ecab 9040 #define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
Yassinetaouil 46:b1a9de66ecab 9041 #define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 9042 #define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 9043 #define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 9044
Yassinetaouil 46:b1a9de66ecab 9045 /* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
Yassinetaouil 46:b1a9de66ecab 9046 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
Yassinetaouil 46:b1a9de66ecab 9047 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
Yassinetaouil 46:b1a9de66ecab 9048 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 9049 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 9050 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 9051
Yassinetaouil 46:b1a9de66ecab 9052 /* Register: POWER_RESETREAS */
Yassinetaouil 46:b1a9de66ecab 9053 /* Description: Reset reason */
Yassinetaouil 46:b1a9de66ecab 9054
Yassinetaouil 46:b1a9de66ecab 9055 /* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
Yassinetaouil 46:b1a9de66ecab 9056 #define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
Yassinetaouil 46:b1a9de66ecab 9057 #define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
Yassinetaouil 46:b1a9de66ecab 9058 #define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
Yassinetaouil 46:b1a9de66ecab 9059 #define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
Yassinetaouil 46:b1a9de66ecab 9060
Yassinetaouil 46:b1a9de66ecab 9061 /* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
Yassinetaouil 46:b1a9de66ecab 9062 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
Yassinetaouil 46:b1a9de66ecab 9063 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
Yassinetaouil 46:b1a9de66ecab 9064 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
Yassinetaouil 46:b1a9de66ecab 9065 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
Yassinetaouil 46:b1a9de66ecab 9066
Yassinetaouil 46:b1a9de66ecab 9067 /* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
Yassinetaouil 46:b1a9de66ecab 9068 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
Yassinetaouil 46:b1a9de66ecab 9069 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
Yassinetaouil 46:b1a9de66ecab 9070 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
Yassinetaouil 46:b1a9de66ecab 9071 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
Yassinetaouil 46:b1a9de66ecab 9072
Yassinetaouil 46:b1a9de66ecab 9073 /* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
Yassinetaouil 46:b1a9de66ecab 9074 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
Yassinetaouil 46:b1a9de66ecab 9075 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
Yassinetaouil 46:b1a9de66ecab 9076 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
Yassinetaouil 46:b1a9de66ecab 9077 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
Yassinetaouil 46:b1a9de66ecab 9078
Yassinetaouil 46:b1a9de66ecab 9079 /* Bit 3 : Reset from CPU lock-up detected */
Yassinetaouil 46:b1a9de66ecab 9080 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
Yassinetaouil 46:b1a9de66ecab 9081 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
Yassinetaouil 46:b1a9de66ecab 9082 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
Yassinetaouil 46:b1a9de66ecab 9083 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
Yassinetaouil 46:b1a9de66ecab 9084
Yassinetaouil 46:b1a9de66ecab 9085 /* Bit 2 : Reset from soft reset detected */
Yassinetaouil 46:b1a9de66ecab 9086 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
Yassinetaouil 46:b1a9de66ecab 9087 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
Yassinetaouil 46:b1a9de66ecab 9088 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
Yassinetaouil 46:b1a9de66ecab 9089 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
Yassinetaouil 46:b1a9de66ecab 9090
Yassinetaouil 46:b1a9de66ecab 9091 /* Bit 1 : Reset from watchdog detected */
Yassinetaouil 46:b1a9de66ecab 9092 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
Yassinetaouil 46:b1a9de66ecab 9093 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
Yassinetaouil 46:b1a9de66ecab 9094 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
Yassinetaouil 46:b1a9de66ecab 9095 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
Yassinetaouil 46:b1a9de66ecab 9096
Yassinetaouil 46:b1a9de66ecab 9097 /* Bit 0 : Reset from pin-reset detected */
Yassinetaouil 46:b1a9de66ecab 9098 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
Yassinetaouil 46:b1a9de66ecab 9099 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
Yassinetaouil 46:b1a9de66ecab 9100 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
Yassinetaouil 46:b1a9de66ecab 9101 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
Yassinetaouil 46:b1a9de66ecab 9102
Yassinetaouil 46:b1a9de66ecab 9103 /* Register: POWER_RAMSTATUS */
Yassinetaouil 46:b1a9de66ecab 9104 /* Description: Deprecated register - RAM status register */
Yassinetaouil 46:b1a9de66ecab 9105
Yassinetaouil 46:b1a9de66ecab 9106 /* Bit 3 : RAM block 3 is on or off/powering up */
Yassinetaouil 46:b1a9de66ecab 9107 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
Yassinetaouil 46:b1a9de66ecab 9108 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
Yassinetaouil 46:b1a9de66ecab 9109 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9110 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9111
Yassinetaouil 46:b1a9de66ecab 9112 /* Bit 2 : RAM block 2 is on or off/powering up */
Yassinetaouil 46:b1a9de66ecab 9113 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
Yassinetaouil 46:b1a9de66ecab 9114 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
Yassinetaouil 46:b1a9de66ecab 9115 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9116 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9117
Yassinetaouil 46:b1a9de66ecab 9118 /* Bit 1 : RAM block 1 is on or off/powering up */
Yassinetaouil 46:b1a9de66ecab 9119 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
Yassinetaouil 46:b1a9de66ecab 9120 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
Yassinetaouil 46:b1a9de66ecab 9121 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9122 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9123
Yassinetaouil 46:b1a9de66ecab 9124 /* Bit 0 : RAM block 0 is on or off/powering up */
Yassinetaouil 46:b1a9de66ecab 9125 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
Yassinetaouil 46:b1a9de66ecab 9126 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
Yassinetaouil 46:b1a9de66ecab 9127 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9128 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9129
Yassinetaouil 46:b1a9de66ecab 9130 /* Register: POWER_SYSTEMOFF */
Yassinetaouil 46:b1a9de66ecab 9131 /* Description: System OFF register */
Yassinetaouil 46:b1a9de66ecab 9132
Yassinetaouil 46:b1a9de66ecab 9133 /* Bit 0 : Enable System OFF mode */
Yassinetaouil 46:b1a9de66ecab 9134 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
Yassinetaouil 46:b1a9de66ecab 9135 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
Yassinetaouil 46:b1a9de66ecab 9136 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
Yassinetaouil 46:b1a9de66ecab 9137
Yassinetaouil 46:b1a9de66ecab 9138 /* Register: POWER_POFCON */
Yassinetaouil 46:b1a9de66ecab 9139 /* Description: Power failure comparator configuration */
Yassinetaouil 46:b1a9de66ecab 9140
Yassinetaouil 46:b1a9de66ecab 9141 /* Bits 4..1 : Power failure comparator threshold setting */
Yassinetaouil 46:b1a9de66ecab 9142 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
Yassinetaouil 46:b1a9de66ecab 9143 #define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
Yassinetaouil 46:b1a9de66ecab 9144 #define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
Yassinetaouil 46:b1a9de66ecab 9145 #define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
Yassinetaouil 46:b1a9de66ecab 9146 #define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
Yassinetaouil 46:b1a9de66ecab 9147 #define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
Yassinetaouil 46:b1a9de66ecab 9148 #define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
Yassinetaouil 46:b1a9de66ecab 9149 #define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
Yassinetaouil 46:b1a9de66ecab 9150 #define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
Yassinetaouil 46:b1a9de66ecab 9151 #define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
Yassinetaouil 46:b1a9de66ecab 9152 #define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
Yassinetaouil 46:b1a9de66ecab 9153 #define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
Yassinetaouil 46:b1a9de66ecab 9154 #define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
Yassinetaouil 46:b1a9de66ecab 9155 #define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
Yassinetaouil 46:b1a9de66ecab 9156
Yassinetaouil 46:b1a9de66ecab 9157 /* Bit 0 : Enable or disable power failure comparator */
Yassinetaouil 46:b1a9de66ecab 9158 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
Yassinetaouil 46:b1a9de66ecab 9159 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
Yassinetaouil 46:b1a9de66ecab 9160 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 9161 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 9162
Yassinetaouil 46:b1a9de66ecab 9163 /* Register: POWER_GPREGRET */
Yassinetaouil 46:b1a9de66ecab 9164 /* Description: General purpose retention register */
Yassinetaouil 46:b1a9de66ecab 9165
Yassinetaouil 46:b1a9de66ecab 9166 /* Bits 7..0 : General purpose retention register */
Yassinetaouil 46:b1a9de66ecab 9167 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
Yassinetaouil 46:b1a9de66ecab 9168 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
Yassinetaouil 46:b1a9de66ecab 9169
Yassinetaouil 46:b1a9de66ecab 9170 /* Register: POWER_GPREGRET2 */
Yassinetaouil 46:b1a9de66ecab 9171 /* Description: General purpose retention register */
Yassinetaouil 46:b1a9de66ecab 9172
Yassinetaouil 46:b1a9de66ecab 9173 /* Bits 7..0 : General purpose retention register */
Yassinetaouil 46:b1a9de66ecab 9174 #define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
Yassinetaouil 46:b1a9de66ecab 9175 #define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
Yassinetaouil 46:b1a9de66ecab 9176
Yassinetaouil 46:b1a9de66ecab 9177 /* Register: POWER_RAMON */
Yassinetaouil 46:b1a9de66ecab 9178 /* Description: Deprecated register - RAM on/off register (this register is retained) */
Yassinetaouil 46:b1a9de66ecab 9179
Yassinetaouil 46:b1a9de66ecab 9180 /* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
Yassinetaouil 46:b1a9de66ecab 9181 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
Yassinetaouil 46:b1a9de66ecab 9182 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
Yassinetaouil 46:b1a9de66ecab 9183 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9184 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9185
Yassinetaouil 46:b1a9de66ecab 9186 /* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
Yassinetaouil 46:b1a9de66ecab 9187 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
Yassinetaouil 46:b1a9de66ecab 9188 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
Yassinetaouil 46:b1a9de66ecab 9189 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9190 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9191
Yassinetaouil 46:b1a9de66ecab 9192 /* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
Yassinetaouil 46:b1a9de66ecab 9193 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
Yassinetaouil 46:b1a9de66ecab 9194 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
Yassinetaouil 46:b1a9de66ecab 9195 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9196 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9197
Yassinetaouil 46:b1a9de66ecab 9198 /* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
Yassinetaouil 46:b1a9de66ecab 9199 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
Yassinetaouil 46:b1a9de66ecab 9200 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
Yassinetaouil 46:b1a9de66ecab 9201 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9202 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9203
Yassinetaouil 46:b1a9de66ecab 9204 /* Register: POWER_RAMONB */
Yassinetaouil 46:b1a9de66ecab 9205 /* Description: Deprecated register - RAM on/off register (this register is retained) */
Yassinetaouil 46:b1a9de66ecab 9206
Yassinetaouil 46:b1a9de66ecab 9207 /* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
Yassinetaouil 46:b1a9de66ecab 9208 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
Yassinetaouil 46:b1a9de66ecab 9209 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
Yassinetaouil 46:b1a9de66ecab 9210 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9211 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9212
Yassinetaouil 46:b1a9de66ecab 9213 /* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
Yassinetaouil 46:b1a9de66ecab 9214 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
Yassinetaouil 46:b1a9de66ecab 9215 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
Yassinetaouil 46:b1a9de66ecab 9216 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9217 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9218
Yassinetaouil 46:b1a9de66ecab 9219 /* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
Yassinetaouil 46:b1a9de66ecab 9220 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
Yassinetaouil 46:b1a9de66ecab 9221 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
Yassinetaouil 46:b1a9de66ecab 9222 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9223 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9224
Yassinetaouil 46:b1a9de66ecab 9225 /* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
Yassinetaouil 46:b1a9de66ecab 9226 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
Yassinetaouil 46:b1a9de66ecab 9227 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
Yassinetaouil 46:b1a9de66ecab 9228 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9229 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9230
Yassinetaouil 46:b1a9de66ecab 9231 /* Register: POWER_DCDCEN */
Yassinetaouil 46:b1a9de66ecab 9232 /* Description: DC/DC enable register */
Yassinetaouil 46:b1a9de66ecab 9233
Yassinetaouil 46:b1a9de66ecab 9234 /* Bit 0 : Enable or disable DC/DC converter */
Yassinetaouil 46:b1a9de66ecab 9235 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
Yassinetaouil 46:b1a9de66ecab 9236 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
Yassinetaouil 46:b1a9de66ecab 9237 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 9238 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 9239
Yassinetaouil 46:b1a9de66ecab 9240 /* Register: POWER_RAM_POWER */
Yassinetaouil 46:b1a9de66ecab 9241 /* Description: Description cluster[0]: RAM0 power control register */
Yassinetaouil 46:b1a9de66ecab 9242
Yassinetaouil 46:b1a9de66ecab 9243 /* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
Yassinetaouil 46:b1a9de66ecab 9244 #define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9245 #define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9246 #define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9247 #define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9248
Yassinetaouil 46:b1a9de66ecab 9249 /* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
Yassinetaouil 46:b1a9de66ecab 9250 #define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9251 #define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9252 #define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9253 #define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9254
Yassinetaouil 46:b1a9de66ecab 9255 /* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
Yassinetaouil 46:b1a9de66ecab 9256 #define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
Yassinetaouil 46:b1a9de66ecab 9257 #define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
Yassinetaouil 46:b1a9de66ecab 9258 #define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9259 #define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9260
Yassinetaouil 46:b1a9de66ecab 9261 /* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
Yassinetaouil 46:b1a9de66ecab 9262 #define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
Yassinetaouil 46:b1a9de66ecab 9263 #define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
Yassinetaouil 46:b1a9de66ecab 9264 #define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9265 #define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9266
Yassinetaouil 46:b1a9de66ecab 9267 /* Register: POWER_RAM_POWERSET */
Yassinetaouil 46:b1a9de66ecab 9268 /* Description: Description cluster[0]: RAM0 power control set register */
Yassinetaouil 46:b1a9de66ecab 9269
Yassinetaouil 46:b1a9de66ecab 9270 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
Yassinetaouil 46:b1a9de66ecab 9271 #define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9272 #define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9273 #define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9274
Yassinetaouil 46:b1a9de66ecab 9275 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
Yassinetaouil 46:b1a9de66ecab 9276 #define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9277 #define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9278 #define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9279
Yassinetaouil 46:b1a9de66ecab 9280 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
Yassinetaouil 46:b1a9de66ecab 9281 #define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
Yassinetaouil 46:b1a9de66ecab 9282 #define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
Yassinetaouil 46:b1a9de66ecab 9283 #define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9284
Yassinetaouil 46:b1a9de66ecab 9285 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
Yassinetaouil 46:b1a9de66ecab 9286 #define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
Yassinetaouil 46:b1a9de66ecab 9287 #define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
Yassinetaouil 46:b1a9de66ecab 9288 #define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
Yassinetaouil 46:b1a9de66ecab 9289
Yassinetaouil 46:b1a9de66ecab 9290 /* Register: POWER_RAM_POWERCLR */
Yassinetaouil 46:b1a9de66ecab 9291 /* Description: Description cluster[0]: RAM0 power control clear register */
Yassinetaouil 46:b1a9de66ecab 9292
Yassinetaouil 46:b1a9de66ecab 9293 /* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
Yassinetaouil 46:b1a9de66ecab 9294 #define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9295 #define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9296 #define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9297
Yassinetaouil 46:b1a9de66ecab 9298 /* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
Yassinetaouil 46:b1a9de66ecab 9299 #define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9300 #define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
Yassinetaouil 46:b1a9de66ecab 9301 #define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9302
Yassinetaouil 46:b1a9de66ecab 9303 /* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
Yassinetaouil 46:b1a9de66ecab 9304 #define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
Yassinetaouil 46:b1a9de66ecab 9305 #define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
Yassinetaouil 46:b1a9de66ecab 9306 #define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9307
Yassinetaouil 46:b1a9de66ecab 9308 /* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
Yassinetaouil 46:b1a9de66ecab 9309 #define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
Yassinetaouil 46:b1a9de66ecab 9310 #define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
Yassinetaouil 46:b1a9de66ecab 9311 #define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
Yassinetaouil 46:b1a9de66ecab 9312
Yassinetaouil 46:b1a9de66ecab 9313
Yassinetaouil 46:b1a9de66ecab 9314 /* Peripheral: PPI */
Yassinetaouil 46:b1a9de66ecab 9315 /* Description: Programmable Peripheral Interconnect */
Yassinetaouil 46:b1a9de66ecab 9316
Yassinetaouil 46:b1a9de66ecab 9317 /* Register: PPI_CHEN */
Yassinetaouil 46:b1a9de66ecab 9318 /* Description: Channel enable register */
Yassinetaouil 46:b1a9de66ecab 9319
Yassinetaouil 46:b1a9de66ecab 9320 /* Bit 31 : Enable or disable channel 31 */
Yassinetaouil 46:b1a9de66ecab 9321 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
Yassinetaouil 46:b1a9de66ecab 9322 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
Yassinetaouil 46:b1a9de66ecab 9323 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9324 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9325
Yassinetaouil 46:b1a9de66ecab 9326 /* Bit 30 : Enable or disable channel 30 */
Yassinetaouil 46:b1a9de66ecab 9327 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
Yassinetaouil 46:b1a9de66ecab 9328 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
Yassinetaouil 46:b1a9de66ecab 9329 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9330 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9331
Yassinetaouil 46:b1a9de66ecab 9332 /* Bit 29 : Enable or disable channel 29 */
Yassinetaouil 46:b1a9de66ecab 9333 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
Yassinetaouil 46:b1a9de66ecab 9334 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
Yassinetaouil 46:b1a9de66ecab 9335 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9336 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9337
Yassinetaouil 46:b1a9de66ecab 9338 /* Bit 28 : Enable or disable channel 28 */
Yassinetaouil 46:b1a9de66ecab 9339 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
Yassinetaouil 46:b1a9de66ecab 9340 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
Yassinetaouil 46:b1a9de66ecab 9341 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9342 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9343
Yassinetaouil 46:b1a9de66ecab 9344 /* Bit 27 : Enable or disable channel 27 */
Yassinetaouil 46:b1a9de66ecab 9345 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
Yassinetaouil 46:b1a9de66ecab 9346 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
Yassinetaouil 46:b1a9de66ecab 9347 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9348 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9349
Yassinetaouil 46:b1a9de66ecab 9350 /* Bit 26 : Enable or disable channel 26 */
Yassinetaouil 46:b1a9de66ecab 9351 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
Yassinetaouil 46:b1a9de66ecab 9352 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
Yassinetaouil 46:b1a9de66ecab 9353 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9354 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9355
Yassinetaouil 46:b1a9de66ecab 9356 /* Bit 25 : Enable or disable channel 25 */
Yassinetaouil 46:b1a9de66ecab 9357 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
Yassinetaouil 46:b1a9de66ecab 9358 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
Yassinetaouil 46:b1a9de66ecab 9359 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9360 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9361
Yassinetaouil 46:b1a9de66ecab 9362 /* Bit 24 : Enable or disable channel 24 */
Yassinetaouil 46:b1a9de66ecab 9363 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
Yassinetaouil 46:b1a9de66ecab 9364 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
Yassinetaouil 46:b1a9de66ecab 9365 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9366 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9367
Yassinetaouil 46:b1a9de66ecab 9368 /* Bit 23 : Enable or disable channel 23 */
Yassinetaouil 46:b1a9de66ecab 9369 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
Yassinetaouil 46:b1a9de66ecab 9370 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
Yassinetaouil 46:b1a9de66ecab 9371 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9372 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9373
Yassinetaouil 46:b1a9de66ecab 9374 /* Bit 22 : Enable or disable channel 22 */
Yassinetaouil 46:b1a9de66ecab 9375 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
Yassinetaouil 46:b1a9de66ecab 9376 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
Yassinetaouil 46:b1a9de66ecab 9377 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9378 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9379
Yassinetaouil 46:b1a9de66ecab 9380 /* Bit 21 : Enable or disable channel 21 */
Yassinetaouil 46:b1a9de66ecab 9381 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
Yassinetaouil 46:b1a9de66ecab 9382 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
Yassinetaouil 46:b1a9de66ecab 9383 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9384 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9385
Yassinetaouil 46:b1a9de66ecab 9386 /* Bit 20 : Enable or disable channel 20 */
Yassinetaouil 46:b1a9de66ecab 9387 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
Yassinetaouil 46:b1a9de66ecab 9388 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
Yassinetaouil 46:b1a9de66ecab 9389 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9390 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9391
Yassinetaouil 46:b1a9de66ecab 9392 /* Bit 19 : Enable or disable channel 19 */
Yassinetaouil 46:b1a9de66ecab 9393 #define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
Yassinetaouil 46:b1a9de66ecab 9394 #define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
Yassinetaouil 46:b1a9de66ecab 9395 #define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9396 #define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9397
Yassinetaouil 46:b1a9de66ecab 9398 /* Bit 18 : Enable or disable channel 18 */
Yassinetaouil 46:b1a9de66ecab 9399 #define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
Yassinetaouil 46:b1a9de66ecab 9400 #define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
Yassinetaouil 46:b1a9de66ecab 9401 #define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9402 #define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9403
Yassinetaouil 46:b1a9de66ecab 9404 /* Bit 17 : Enable or disable channel 17 */
Yassinetaouil 46:b1a9de66ecab 9405 #define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
Yassinetaouil 46:b1a9de66ecab 9406 #define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
Yassinetaouil 46:b1a9de66ecab 9407 #define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9408 #define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9409
Yassinetaouil 46:b1a9de66ecab 9410 /* Bit 16 : Enable or disable channel 16 */
Yassinetaouil 46:b1a9de66ecab 9411 #define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
Yassinetaouil 46:b1a9de66ecab 9412 #define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
Yassinetaouil 46:b1a9de66ecab 9413 #define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9414 #define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9415
Yassinetaouil 46:b1a9de66ecab 9416 /* Bit 15 : Enable or disable channel 15 */
Yassinetaouil 46:b1a9de66ecab 9417 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
Yassinetaouil 46:b1a9de66ecab 9418 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
Yassinetaouil 46:b1a9de66ecab 9419 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9420 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9421
Yassinetaouil 46:b1a9de66ecab 9422 /* Bit 14 : Enable or disable channel 14 */
Yassinetaouil 46:b1a9de66ecab 9423 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
Yassinetaouil 46:b1a9de66ecab 9424 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
Yassinetaouil 46:b1a9de66ecab 9425 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9426 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9427
Yassinetaouil 46:b1a9de66ecab 9428 /* Bit 13 : Enable or disable channel 13 */
Yassinetaouil 46:b1a9de66ecab 9429 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
Yassinetaouil 46:b1a9de66ecab 9430 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
Yassinetaouil 46:b1a9de66ecab 9431 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9432 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9433
Yassinetaouil 46:b1a9de66ecab 9434 /* Bit 12 : Enable or disable channel 12 */
Yassinetaouil 46:b1a9de66ecab 9435 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
Yassinetaouil 46:b1a9de66ecab 9436 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
Yassinetaouil 46:b1a9de66ecab 9437 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9438 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9439
Yassinetaouil 46:b1a9de66ecab 9440 /* Bit 11 : Enable or disable channel 11 */
Yassinetaouil 46:b1a9de66ecab 9441 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
Yassinetaouil 46:b1a9de66ecab 9442 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
Yassinetaouil 46:b1a9de66ecab 9443 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9444 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9445
Yassinetaouil 46:b1a9de66ecab 9446 /* Bit 10 : Enable or disable channel 10 */
Yassinetaouil 46:b1a9de66ecab 9447 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
Yassinetaouil 46:b1a9de66ecab 9448 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
Yassinetaouil 46:b1a9de66ecab 9449 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9450 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9451
Yassinetaouil 46:b1a9de66ecab 9452 /* Bit 9 : Enable or disable channel 9 */
Yassinetaouil 46:b1a9de66ecab 9453 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
Yassinetaouil 46:b1a9de66ecab 9454 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
Yassinetaouil 46:b1a9de66ecab 9455 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9456 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9457
Yassinetaouil 46:b1a9de66ecab 9458 /* Bit 8 : Enable or disable channel 8 */
Yassinetaouil 46:b1a9de66ecab 9459 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
Yassinetaouil 46:b1a9de66ecab 9460 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
Yassinetaouil 46:b1a9de66ecab 9461 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9462 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9463
Yassinetaouil 46:b1a9de66ecab 9464 /* Bit 7 : Enable or disable channel 7 */
Yassinetaouil 46:b1a9de66ecab 9465 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
Yassinetaouil 46:b1a9de66ecab 9466 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
Yassinetaouil 46:b1a9de66ecab 9467 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9468 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9469
Yassinetaouil 46:b1a9de66ecab 9470 /* Bit 6 : Enable or disable channel 6 */
Yassinetaouil 46:b1a9de66ecab 9471 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
Yassinetaouil 46:b1a9de66ecab 9472 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
Yassinetaouil 46:b1a9de66ecab 9473 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9474 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9475
Yassinetaouil 46:b1a9de66ecab 9476 /* Bit 5 : Enable or disable channel 5 */
Yassinetaouil 46:b1a9de66ecab 9477 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
Yassinetaouil 46:b1a9de66ecab 9478 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
Yassinetaouil 46:b1a9de66ecab 9479 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9480 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9481
Yassinetaouil 46:b1a9de66ecab 9482 /* Bit 4 : Enable or disable channel 4 */
Yassinetaouil 46:b1a9de66ecab 9483 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
Yassinetaouil 46:b1a9de66ecab 9484 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
Yassinetaouil 46:b1a9de66ecab 9485 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9486 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9487
Yassinetaouil 46:b1a9de66ecab 9488 /* Bit 3 : Enable or disable channel 3 */
Yassinetaouil 46:b1a9de66ecab 9489 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
Yassinetaouil 46:b1a9de66ecab 9490 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
Yassinetaouil 46:b1a9de66ecab 9491 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9492 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9493
Yassinetaouil 46:b1a9de66ecab 9494 /* Bit 2 : Enable or disable channel 2 */
Yassinetaouil 46:b1a9de66ecab 9495 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
Yassinetaouil 46:b1a9de66ecab 9496 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
Yassinetaouil 46:b1a9de66ecab 9497 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9498 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9499
Yassinetaouil 46:b1a9de66ecab 9500 /* Bit 1 : Enable or disable channel 1 */
Yassinetaouil 46:b1a9de66ecab 9501 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
Yassinetaouil 46:b1a9de66ecab 9502 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
Yassinetaouil 46:b1a9de66ecab 9503 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9504 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9505
Yassinetaouil 46:b1a9de66ecab 9506 /* Bit 0 : Enable or disable channel 0 */
Yassinetaouil 46:b1a9de66ecab 9507 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
Yassinetaouil 46:b1a9de66ecab 9508 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
Yassinetaouil 46:b1a9de66ecab 9509 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
Yassinetaouil 46:b1a9de66ecab 9510 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
Yassinetaouil 46:b1a9de66ecab 9511
Yassinetaouil 46:b1a9de66ecab 9512 /* Register: PPI_CHENSET */
Yassinetaouil 46:b1a9de66ecab 9513 /* Description: Channel enable set register */
Yassinetaouil 46:b1a9de66ecab 9514
Yassinetaouil 46:b1a9de66ecab 9515 /* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9516 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
Yassinetaouil 46:b1a9de66ecab 9517 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
Yassinetaouil 46:b1a9de66ecab 9518 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9519 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9520 #define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9521
Yassinetaouil 46:b1a9de66ecab 9522 /* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9523 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
Yassinetaouil 46:b1a9de66ecab 9524 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
Yassinetaouil 46:b1a9de66ecab 9525 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9526 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9527 #define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9528
Yassinetaouil 46:b1a9de66ecab 9529 /* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9530 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
Yassinetaouil 46:b1a9de66ecab 9531 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
Yassinetaouil 46:b1a9de66ecab 9532 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9533 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9534 #define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9535
Yassinetaouil 46:b1a9de66ecab 9536 /* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9537 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
Yassinetaouil 46:b1a9de66ecab 9538 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
Yassinetaouil 46:b1a9de66ecab 9539 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9540 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9541 #define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9542
Yassinetaouil 46:b1a9de66ecab 9543 /* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9544 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
Yassinetaouil 46:b1a9de66ecab 9545 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
Yassinetaouil 46:b1a9de66ecab 9546 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9547 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9548 #define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9549
Yassinetaouil 46:b1a9de66ecab 9550 /* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9551 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
Yassinetaouil 46:b1a9de66ecab 9552 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
Yassinetaouil 46:b1a9de66ecab 9553 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9554 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9555 #define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9556
Yassinetaouil 46:b1a9de66ecab 9557 /* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9558 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
Yassinetaouil 46:b1a9de66ecab 9559 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
Yassinetaouil 46:b1a9de66ecab 9560 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9561 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9562 #define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9563
Yassinetaouil 46:b1a9de66ecab 9564 /* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9565 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
Yassinetaouil 46:b1a9de66ecab 9566 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
Yassinetaouil 46:b1a9de66ecab 9567 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9568 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9569 #define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9570
Yassinetaouil 46:b1a9de66ecab 9571 /* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9572 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
Yassinetaouil 46:b1a9de66ecab 9573 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
Yassinetaouil 46:b1a9de66ecab 9574 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9575 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9576 #define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9577
Yassinetaouil 46:b1a9de66ecab 9578 /* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9579 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
Yassinetaouil 46:b1a9de66ecab 9580 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
Yassinetaouil 46:b1a9de66ecab 9581 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9582 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9583 #define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9584
Yassinetaouil 46:b1a9de66ecab 9585 /* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9586 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
Yassinetaouil 46:b1a9de66ecab 9587 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
Yassinetaouil 46:b1a9de66ecab 9588 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9589 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9590 #define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9591
Yassinetaouil 46:b1a9de66ecab 9592 /* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9593 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
Yassinetaouil 46:b1a9de66ecab 9594 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
Yassinetaouil 46:b1a9de66ecab 9595 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9596 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9597 #define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9598
Yassinetaouil 46:b1a9de66ecab 9599 /* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9600 #define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
Yassinetaouil 46:b1a9de66ecab 9601 #define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
Yassinetaouil 46:b1a9de66ecab 9602 #define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9603 #define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9604 #define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9605
Yassinetaouil 46:b1a9de66ecab 9606 /* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9607 #define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
Yassinetaouil 46:b1a9de66ecab 9608 #define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
Yassinetaouil 46:b1a9de66ecab 9609 #define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9610 #define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9611 #define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9612
Yassinetaouil 46:b1a9de66ecab 9613 /* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9614 #define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
Yassinetaouil 46:b1a9de66ecab 9615 #define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
Yassinetaouil 46:b1a9de66ecab 9616 #define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9617 #define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9618 #define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9619
Yassinetaouil 46:b1a9de66ecab 9620 /* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9621 #define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
Yassinetaouil 46:b1a9de66ecab 9622 #define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
Yassinetaouil 46:b1a9de66ecab 9623 #define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9624 #define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9625 #define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9626
Yassinetaouil 46:b1a9de66ecab 9627 /* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9628 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
Yassinetaouil 46:b1a9de66ecab 9629 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
Yassinetaouil 46:b1a9de66ecab 9630 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9631 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9632 #define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9633
Yassinetaouil 46:b1a9de66ecab 9634 /* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9635 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
Yassinetaouil 46:b1a9de66ecab 9636 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
Yassinetaouil 46:b1a9de66ecab 9637 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9638 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9639 #define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9640
Yassinetaouil 46:b1a9de66ecab 9641 /* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9642 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
Yassinetaouil 46:b1a9de66ecab 9643 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
Yassinetaouil 46:b1a9de66ecab 9644 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9645 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9646 #define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9647
Yassinetaouil 46:b1a9de66ecab 9648 /* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9649 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
Yassinetaouil 46:b1a9de66ecab 9650 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
Yassinetaouil 46:b1a9de66ecab 9651 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9652 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9653 #define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9654
Yassinetaouil 46:b1a9de66ecab 9655 /* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9656 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
Yassinetaouil 46:b1a9de66ecab 9657 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
Yassinetaouil 46:b1a9de66ecab 9658 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9659 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9660 #define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9661
Yassinetaouil 46:b1a9de66ecab 9662 /* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9663 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
Yassinetaouil 46:b1a9de66ecab 9664 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
Yassinetaouil 46:b1a9de66ecab 9665 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9666 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9667 #define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9668
Yassinetaouil 46:b1a9de66ecab 9669 /* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9670 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
Yassinetaouil 46:b1a9de66ecab 9671 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
Yassinetaouil 46:b1a9de66ecab 9672 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9673 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9674 #define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9675
Yassinetaouil 46:b1a9de66ecab 9676 /* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9677 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
Yassinetaouil 46:b1a9de66ecab 9678 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
Yassinetaouil 46:b1a9de66ecab 9679 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9680 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9681 #define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9682
Yassinetaouil 46:b1a9de66ecab 9683 /* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9684 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
Yassinetaouil 46:b1a9de66ecab 9685 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
Yassinetaouil 46:b1a9de66ecab 9686 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9687 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9688 #define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9689
Yassinetaouil 46:b1a9de66ecab 9690 /* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9691 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
Yassinetaouil 46:b1a9de66ecab 9692 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
Yassinetaouil 46:b1a9de66ecab 9693 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9694 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9695 #define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9696
Yassinetaouil 46:b1a9de66ecab 9697 /* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9698 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
Yassinetaouil 46:b1a9de66ecab 9699 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
Yassinetaouil 46:b1a9de66ecab 9700 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9701 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9702 #define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9703
Yassinetaouil 46:b1a9de66ecab 9704 /* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9705 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
Yassinetaouil 46:b1a9de66ecab 9706 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
Yassinetaouil 46:b1a9de66ecab 9707 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9708 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9709 #define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9710
Yassinetaouil 46:b1a9de66ecab 9711 /* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9712 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
Yassinetaouil 46:b1a9de66ecab 9713 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
Yassinetaouil 46:b1a9de66ecab 9714 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9715 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9716 #define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9717
Yassinetaouil 46:b1a9de66ecab 9718 /* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9719 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
Yassinetaouil 46:b1a9de66ecab 9720 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
Yassinetaouil 46:b1a9de66ecab 9721 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9722 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9723 #define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9724
Yassinetaouil 46:b1a9de66ecab 9725 /* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9726 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
Yassinetaouil 46:b1a9de66ecab 9727 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
Yassinetaouil 46:b1a9de66ecab 9728 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9729 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9730 #define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9731
Yassinetaouil 46:b1a9de66ecab 9732 /* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9733 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
Yassinetaouil 46:b1a9de66ecab 9734 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
Yassinetaouil 46:b1a9de66ecab 9735 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9736 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9737 #define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
Yassinetaouil 46:b1a9de66ecab 9738
Yassinetaouil 46:b1a9de66ecab 9739 /* Register: PPI_CHENCLR */
Yassinetaouil 46:b1a9de66ecab 9740 /* Description: Channel enable clear register */
Yassinetaouil 46:b1a9de66ecab 9741
Yassinetaouil 46:b1a9de66ecab 9742 /* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9743 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
Yassinetaouil 46:b1a9de66ecab 9744 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
Yassinetaouil 46:b1a9de66ecab 9745 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9746 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9747 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9748
Yassinetaouil 46:b1a9de66ecab 9749 /* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9750 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
Yassinetaouil 46:b1a9de66ecab 9751 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
Yassinetaouil 46:b1a9de66ecab 9752 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9753 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9754 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9755
Yassinetaouil 46:b1a9de66ecab 9756 /* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9757 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
Yassinetaouil 46:b1a9de66ecab 9758 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
Yassinetaouil 46:b1a9de66ecab 9759 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9760 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9761 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9762
Yassinetaouil 46:b1a9de66ecab 9763 /* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9764 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
Yassinetaouil 46:b1a9de66ecab 9765 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
Yassinetaouil 46:b1a9de66ecab 9766 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9767 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9768 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9769
Yassinetaouil 46:b1a9de66ecab 9770 /* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9771 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
Yassinetaouil 46:b1a9de66ecab 9772 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
Yassinetaouil 46:b1a9de66ecab 9773 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9774 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9775 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9776
Yassinetaouil 46:b1a9de66ecab 9777 /* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9778 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
Yassinetaouil 46:b1a9de66ecab 9779 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
Yassinetaouil 46:b1a9de66ecab 9780 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9781 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9782 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9783
Yassinetaouil 46:b1a9de66ecab 9784 /* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9785 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
Yassinetaouil 46:b1a9de66ecab 9786 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
Yassinetaouil 46:b1a9de66ecab 9787 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9788 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9789 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9790
Yassinetaouil 46:b1a9de66ecab 9791 /* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9792 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
Yassinetaouil 46:b1a9de66ecab 9793 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
Yassinetaouil 46:b1a9de66ecab 9794 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9795 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9796 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9797
Yassinetaouil 46:b1a9de66ecab 9798 /* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9799 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
Yassinetaouil 46:b1a9de66ecab 9800 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
Yassinetaouil 46:b1a9de66ecab 9801 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9802 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9803 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9804
Yassinetaouil 46:b1a9de66ecab 9805 /* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9806 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
Yassinetaouil 46:b1a9de66ecab 9807 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
Yassinetaouil 46:b1a9de66ecab 9808 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9809 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9810 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9811
Yassinetaouil 46:b1a9de66ecab 9812 /* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9813 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
Yassinetaouil 46:b1a9de66ecab 9814 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
Yassinetaouil 46:b1a9de66ecab 9815 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9816 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9817 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9818
Yassinetaouil 46:b1a9de66ecab 9819 /* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9820 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
Yassinetaouil 46:b1a9de66ecab 9821 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
Yassinetaouil 46:b1a9de66ecab 9822 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9823 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9824 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9825
Yassinetaouil 46:b1a9de66ecab 9826 /* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9827 #define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
Yassinetaouil 46:b1a9de66ecab 9828 #define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
Yassinetaouil 46:b1a9de66ecab 9829 #define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9830 #define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9831 #define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9832
Yassinetaouil 46:b1a9de66ecab 9833 /* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9834 #define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
Yassinetaouil 46:b1a9de66ecab 9835 #define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
Yassinetaouil 46:b1a9de66ecab 9836 #define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9837 #define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9838 #define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9839
Yassinetaouil 46:b1a9de66ecab 9840 /* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9841 #define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
Yassinetaouil 46:b1a9de66ecab 9842 #define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
Yassinetaouil 46:b1a9de66ecab 9843 #define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9844 #define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9845 #define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9846
Yassinetaouil 46:b1a9de66ecab 9847 /* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9848 #define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
Yassinetaouil 46:b1a9de66ecab 9849 #define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
Yassinetaouil 46:b1a9de66ecab 9850 #define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9851 #define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9852 #define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9853
Yassinetaouil 46:b1a9de66ecab 9854 /* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9855 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
Yassinetaouil 46:b1a9de66ecab 9856 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
Yassinetaouil 46:b1a9de66ecab 9857 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9858 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9859 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9860
Yassinetaouil 46:b1a9de66ecab 9861 /* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9862 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
Yassinetaouil 46:b1a9de66ecab 9863 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
Yassinetaouil 46:b1a9de66ecab 9864 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9865 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9866 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9867
Yassinetaouil 46:b1a9de66ecab 9868 /* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9869 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
Yassinetaouil 46:b1a9de66ecab 9870 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
Yassinetaouil 46:b1a9de66ecab 9871 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9872 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9873 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9874
Yassinetaouil 46:b1a9de66ecab 9875 /* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9876 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
Yassinetaouil 46:b1a9de66ecab 9877 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
Yassinetaouil 46:b1a9de66ecab 9878 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9879 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9880 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9881
Yassinetaouil 46:b1a9de66ecab 9882 /* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9883 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
Yassinetaouil 46:b1a9de66ecab 9884 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
Yassinetaouil 46:b1a9de66ecab 9885 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9886 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9887 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9888
Yassinetaouil 46:b1a9de66ecab 9889 /* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9890 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
Yassinetaouil 46:b1a9de66ecab 9891 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
Yassinetaouil 46:b1a9de66ecab 9892 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9893 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9894 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9895
Yassinetaouil 46:b1a9de66ecab 9896 /* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9897 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
Yassinetaouil 46:b1a9de66ecab 9898 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
Yassinetaouil 46:b1a9de66ecab 9899 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9900 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9901 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9902
Yassinetaouil 46:b1a9de66ecab 9903 /* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9904 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
Yassinetaouil 46:b1a9de66ecab 9905 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
Yassinetaouil 46:b1a9de66ecab 9906 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9907 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9908 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9909
Yassinetaouil 46:b1a9de66ecab 9910 /* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9911 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
Yassinetaouil 46:b1a9de66ecab 9912 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
Yassinetaouil 46:b1a9de66ecab 9913 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9914 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9915 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9916
Yassinetaouil 46:b1a9de66ecab 9917 /* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9918 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
Yassinetaouil 46:b1a9de66ecab 9919 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
Yassinetaouil 46:b1a9de66ecab 9920 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9921 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9922 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9923
Yassinetaouil 46:b1a9de66ecab 9924 /* Bit 5 : Channel 5 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9925 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
Yassinetaouil 46:b1a9de66ecab 9926 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
Yassinetaouil 46:b1a9de66ecab 9927 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9928 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9929 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9930
Yassinetaouil 46:b1a9de66ecab 9931 /* Bit 4 : Channel 4 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9932 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
Yassinetaouil 46:b1a9de66ecab 9933 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
Yassinetaouil 46:b1a9de66ecab 9934 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9935 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9936 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9937
Yassinetaouil 46:b1a9de66ecab 9938 /* Bit 3 : Channel 3 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9939 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
Yassinetaouil 46:b1a9de66ecab 9940 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
Yassinetaouil 46:b1a9de66ecab 9941 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9942 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9943 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9944
Yassinetaouil 46:b1a9de66ecab 9945 /* Bit 2 : Channel 2 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9946 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
Yassinetaouil 46:b1a9de66ecab 9947 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
Yassinetaouil 46:b1a9de66ecab 9948 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9949 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9950 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9951
Yassinetaouil 46:b1a9de66ecab 9952 /* Bit 1 : Channel 1 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9953 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
Yassinetaouil 46:b1a9de66ecab 9954 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
Yassinetaouil 46:b1a9de66ecab 9955 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9956 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9957 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9958
Yassinetaouil 46:b1a9de66ecab 9959 /* Bit 0 : Channel 0 enable clear register. Writing '0' has no effect */
Yassinetaouil 46:b1a9de66ecab 9960 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
Yassinetaouil 46:b1a9de66ecab 9961 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
Yassinetaouil 46:b1a9de66ecab 9962 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
Yassinetaouil 46:b1a9de66ecab 9963 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
Yassinetaouil 46:b1a9de66ecab 9964 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
Yassinetaouil 46:b1a9de66ecab 9965
Yassinetaouil 46:b1a9de66ecab 9966 /* Register: PPI_CH_EEP */
Yassinetaouil 46:b1a9de66ecab 9967 /* Description: Description cluster[0]: Channel 0 event end-point */
Yassinetaouil 46:b1a9de66ecab 9968
Yassinetaouil 46:b1a9de66ecab 9969 /* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
Yassinetaouil 46:b1a9de66ecab 9970 #define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
Yassinetaouil 46:b1a9de66ecab 9971 #define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
Yassinetaouil 46:b1a9de66ecab 9972
Yassinetaouil 46:b1a9de66ecab 9973 /* Register: PPI_CH_TEP */
Yassinetaouil 46:b1a9de66ecab 9974 /* Description: Description cluster[0]: Channel 0 task end-point */
Yassinetaouil 46:b1a9de66ecab 9975
Yassinetaouil 46:b1a9de66ecab 9976 /* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
Yassinetaouil 46:b1a9de66ecab 9977 #define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
Yassinetaouil 46:b1a9de66ecab 9978 #define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
Yassinetaouil 46:b1a9de66ecab 9979
Yassinetaouil 46:b1a9de66ecab 9980 /* Register: PPI_CHG */
Yassinetaouil 46:b1a9de66ecab 9981 /* Description: Description collection[0]: Channel group 0 */
Yassinetaouil 46:b1a9de66ecab 9982
Yassinetaouil 46:b1a9de66ecab 9983 /* Bit 31 : Include or exclude channel 31 */
Yassinetaouil 46:b1a9de66ecab 9984 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
Yassinetaouil 46:b1a9de66ecab 9985 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
Yassinetaouil 46:b1a9de66ecab 9986 #define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 9987 #define PPI_CHG_CH31_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 9988
Yassinetaouil 46:b1a9de66ecab 9989 /* Bit 30 : Include or exclude channel 30 */
Yassinetaouil 46:b1a9de66ecab 9990 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
Yassinetaouil 46:b1a9de66ecab 9991 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
Yassinetaouil 46:b1a9de66ecab 9992 #define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 9993 #define PPI_CHG_CH30_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 9994
Yassinetaouil 46:b1a9de66ecab 9995 /* Bit 29 : Include or exclude channel 29 */
Yassinetaouil 46:b1a9de66ecab 9996 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
Yassinetaouil 46:b1a9de66ecab 9997 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
Yassinetaouil 46:b1a9de66ecab 9998 #define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 9999 #define PPI_CHG_CH29_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10000
Yassinetaouil 46:b1a9de66ecab 10001 /* Bit 28 : Include or exclude channel 28 */
Yassinetaouil 46:b1a9de66ecab 10002 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
Yassinetaouil 46:b1a9de66ecab 10003 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
Yassinetaouil 46:b1a9de66ecab 10004 #define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10005 #define PPI_CHG_CH28_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10006
Yassinetaouil 46:b1a9de66ecab 10007 /* Bit 27 : Include or exclude channel 27 */
Yassinetaouil 46:b1a9de66ecab 10008 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
Yassinetaouil 46:b1a9de66ecab 10009 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
Yassinetaouil 46:b1a9de66ecab 10010 #define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10011 #define PPI_CHG_CH27_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10012
Yassinetaouil 46:b1a9de66ecab 10013 /* Bit 26 : Include or exclude channel 26 */
Yassinetaouil 46:b1a9de66ecab 10014 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
Yassinetaouil 46:b1a9de66ecab 10015 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
Yassinetaouil 46:b1a9de66ecab 10016 #define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10017 #define PPI_CHG_CH26_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10018
Yassinetaouil 46:b1a9de66ecab 10019 /* Bit 25 : Include or exclude channel 25 */
Yassinetaouil 46:b1a9de66ecab 10020 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
Yassinetaouil 46:b1a9de66ecab 10021 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
Yassinetaouil 46:b1a9de66ecab 10022 #define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10023 #define PPI_CHG_CH25_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10024
Yassinetaouil 46:b1a9de66ecab 10025 /* Bit 24 : Include or exclude channel 24 */
Yassinetaouil 46:b1a9de66ecab 10026 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
Yassinetaouil 46:b1a9de66ecab 10027 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
Yassinetaouil 46:b1a9de66ecab 10028 #define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10029 #define PPI_CHG_CH24_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10030
Yassinetaouil 46:b1a9de66ecab 10031 /* Bit 23 : Include or exclude channel 23 */
Yassinetaouil 46:b1a9de66ecab 10032 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
Yassinetaouil 46:b1a9de66ecab 10033 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
Yassinetaouil 46:b1a9de66ecab 10034 #define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10035 #define PPI_CHG_CH23_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10036
Yassinetaouil 46:b1a9de66ecab 10037 /* Bit 22 : Include or exclude channel 22 */
Yassinetaouil 46:b1a9de66ecab 10038 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
Yassinetaouil 46:b1a9de66ecab 10039 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
Yassinetaouil 46:b1a9de66ecab 10040 #define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10041 #define PPI_CHG_CH22_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10042
Yassinetaouil 46:b1a9de66ecab 10043 /* Bit 21 : Include or exclude channel 21 */
Yassinetaouil 46:b1a9de66ecab 10044 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
Yassinetaouil 46:b1a9de66ecab 10045 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
Yassinetaouil 46:b1a9de66ecab 10046 #define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10047 #define PPI_CHG_CH21_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10048
Yassinetaouil 46:b1a9de66ecab 10049 /* Bit 20 : Include or exclude channel 20 */
Yassinetaouil 46:b1a9de66ecab 10050 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
Yassinetaouil 46:b1a9de66ecab 10051 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
Yassinetaouil 46:b1a9de66ecab 10052 #define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10053 #define PPI_CHG_CH20_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10054
Yassinetaouil 46:b1a9de66ecab 10055 /* Bit 19 : Include or exclude channel 19 */
Yassinetaouil 46:b1a9de66ecab 10056 #define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
Yassinetaouil 46:b1a9de66ecab 10057 #define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
Yassinetaouil 46:b1a9de66ecab 10058 #define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10059 #define PPI_CHG_CH19_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10060
Yassinetaouil 46:b1a9de66ecab 10061 /* Bit 18 : Include or exclude channel 18 */
Yassinetaouil 46:b1a9de66ecab 10062 #define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
Yassinetaouil 46:b1a9de66ecab 10063 #define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
Yassinetaouil 46:b1a9de66ecab 10064 #define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10065 #define PPI_CHG_CH18_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10066
Yassinetaouil 46:b1a9de66ecab 10067 /* Bit 17 : Include or exclude channel 17 */
Yassinetaouil 46:b1a9de66ecab 10068 #define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
Yassinetaouil 46:b1a9de66ecab 10069 #define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
Yassinetaouil 46:b1a9de66ecab 10070 #define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10071 #define PPI_CHG_CH17_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10072
Yassinetaouil 46:b1a9de66ecab 10073 /* Bit 16 : Include or exclude channel 16 */
Yassinetaouil 46:b1a9de66ecab 10074 #define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
Yassinetaouil 46:b1a9de66ecab 10075 #define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
Yassinetaouil 46:b1a9de66ecab 10076 #define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10077 #define PPI_CHG_CH16_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10078
Yassinetaouil 46:b1a9de66ecab 10079 /* Bit 15 : Include or exclude channel 15 */
Yassinetaouil 46:b1a9de66ecab 10080 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
Yassinetaouil 46:b1a9de66ecab 10081 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
Yassinetaouil 46:b1a9de66ecab 10082 #define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10083 #define PPI_CHG_CH15_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10084
Yassinetaouil 46:b1a9de66ecab 10085 /* Bit 14 : Include or exclude channel 14 */
Yassinetaouil 46:b1a9de66ecab 10086 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
Yassinetaouil 46:b1a9de66ecab 10087 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
Yassinetaouil 46:b1a9de66ecab 10088 #define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10089 #define PPI_CHG_CH14_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10090
Yassinetaouil 46:b1a9de66ecab 10091 /* Bit 13 : Include or exclude channel 13 */
Yassinetaouil 46:b1a9de66ecab 10092 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
Yassinetaouil 46:b1a9de66ecab 10093 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
Yassinetaouil 46:b1a9de66ecab 10094 #define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10095 #define PPI_CHG_CH13_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10096
Yassinetaouil 46:b1a9de66ecab 10097 /* Bit 12 : Include or exclude channel 12 */
Yassinetaouil 46:b1a9de66ecab 10098 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
Yassinetaouil 46:b1a9de66ecab 10099 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
Yassinetaouil 46:b1a9de66ecab 10100 #define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10101 #define PPI_CHG_CH12_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10102
Yassinetaouil 46:b1a9de66ecab 10103 /* Bit 11 : Include or exclude channel 11 */
Yassinetaouil 46:b1a9de66ecab 10104 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
Yassinetaouil 46:b1a9de66ecab 10105 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
Yassinetaouil 46:b1a9de66ecab 10106 #define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10107 #define PPI_CHG_CH11_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10108
Yassinetaouil 46:b1a9de66ecab 10109 /* Bit 10 : Include or exclude channel 10 */
Yassinetaouil 46:b1a9de66ecab 10110 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
Yassinetaouil 46:b1a9de66ecab 10111 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
Yassinetaouil 46:b1a9de66ecab 10112 #define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10113 #define PPI_CHG_CH10_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10114
Yassinetaouil 46:b1a9de66ecab 10115 /* Bit 9 : Include or exclude channel 9 */
Yassinetaouil 46:b1a9de66ecab 10116 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
Yassinetaouil 46:b1a9de66ecab 10117 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
Yassinetaouil 46:b1a9de66ecab 10118 #define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10119 #define PPI_CHG_CH9_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10120
Yassinetaouil 46:b1a9de66ecab 10121 /* Bit 8 : Include or exclude channel 8 */
Yassinetaouil 46:b1a9de66ecab 10122 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
Yassinetaouil 46:b1a9de66ecab 10123 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
Yassinetaouil 46:b1a9de66ecab 10124 #define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10125 #define PPI_CHG_CH8_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10126
Yassinetaouil 46:b1a9de66ecab 10127 /* Bit 7 : Include or exclude channel 7 */
Yassinetaouil 46:b1a9de66ecab 10128 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
Yassinetaouil 46:b1a9de66ecab 10129 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
Yassinetaouil 46:b1a9de66ecab 10130 #define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10131 #define PPI_CHG_CH7_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10132
Yassinetaouil 46:b1a9de66ecab 10133 /* Bit 6 : Include or exclude channel 6 */
Yassinetaouil 46:b1a9de66ecab 10134 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
Yassinetaouil 46:b1a9de66ecab 10135 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
Yassinetaouil 46:b1a9de66ecab 10136 #define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10137 #define PPI_CHG_CH6_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10138
Yassinetaouil 46:b1a9de66ecab 10139 /* Bit 5 : Include or exclude channel 5 */
Yassinetaouil 46:b1a9de66ecab 10140 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
Yassinetaouil 46:b1a9de66ecab 10141 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
Yassinetaouil 46:b1a9de66ecab 10142 #define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10143 #define PPI_CHG_CH5_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10144
Yassinetaouil 46:b1a9de66ecab 10145 /* Bit 4 : Include or exclude channel 4 */
Yassinetaouil 46:b1a9de66ecab 10146 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
Yassinetaouil 46:b1a9de66ecab 10147 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
Yassinetaouil 46:b1a9de66ecab 10148 #define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10149 #define PPI_CHG_CH4_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10150
Yassinetaouil 46:b1a9de66ecab 10151 /* Bit 3 : Include or exclude channel 3 */
Yassinetaouil 46:b1a9de66ecab 10152 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
Yassinetaouil 46:b1a9de66ecab 10153 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
Yassinetaouil 46:b1a9de66ecab 10154 #define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10155 #define PPI_CHG_CH3_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10156
Yassinetaouil 46:b1a9de66ecab 10157 /* Bit 2 : Include or exclude channel 2 */
Yassinetaouil 46:b1a9de66ecab 10158 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
Yassinetaouil 46:b1a9de66ecab 10159 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
Yassinetaouil 46:b1a9de66ecab 10160 #define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10161 #define PPI_CHG_CH2_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10162
Yassinetaouil 46:b1a9de66ecab 10163 /* Bit 1 : Include or exclude channel 1 */
Yassinetaouil 46:b1a9de66ecab 10164 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
Yassinetaouil 46:b1a9de66ecab 10165 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
Yassinetaouil 46:b1a9de66ecab 10166 #define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10167 #define PPI_CHG_CH1_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10168
Yassinetaouil 46:b1a9de66ecab 10169 /* Bit 0 : Include or exclude channel 0 */
Yassinetaouil 46:b1a9de66ecab 10170 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
Yassinetaouil 46:b1a9de66ecab 10171 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
Yassinetaouil 46:b1a9de66ecab 10172 #define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
Yassinetaouil 46:b1a9de66ecab 10173 #define PPI_CHG_CH0_Included (1UL) /*!< Include */
Yassinetaouil 46:b1a9de66ecab 10174
Yassinetaouil 46:b1a9de66ecab 10175 /* Register: PPI_FORK_TEP */
Yassinetaouil 46:b1a9de66ecab 10176 /* Description: Description cluster[0]: Channel 0 task end-point */
Yassinetaouil 46:b1a9de66ecab 10177
Yassinetaouil 46:b1a9de66ecab 10178 /* Bits 31..0 : Pointer to task register */
Yassinetaouil 46:b1a9de66ecab 10179 #define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
Yassinetaouil 46:b1a9de66ecab 10180 #define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
Yassinetaouil 46:b1a9de66ecab 10181
Yassinetaouil 46:b1a9de66ecab 10182
Yassinetaouil 46:b1a9de66ecab 10183 /* Peripheral: PWM */
Yassinetaouil 46:b1a9de66ecab 10184 /* Description: Pulse Width Modulation Unit 0 */
Yassinetaouil 46:b1a9de66ecab 10185
Yassinetaouil 46:b1a9de66ecab 10186 /* Register: PWM_SHORTS */
Yassinetaouil 46:b1a9de66ecab 10187 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 10188
Yassinetaouil 46:b1a9de66ecab 10189 /* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
Yassinetaouil 46:b1a9de66ecab 10190 #define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10191 #define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10192 #define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10193 #define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10194
Yassinetaouil 46:b1a9de66ecab 10195 /* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
Yassinetaouil 46:b1a9de66ecab 10196 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
Yassinetaouil 46:b1a9de66ecab 10197 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
Yassinetaouil 46:b1a9de66ecab 10198 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10199 #define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10200
Yassinetaouil 46:b1a9de66ecab 10201 /* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
Yassinetaouil 46:b1a9de66ecab 10202 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
Yassinetaouil 46:b1a9de66ecab 10203 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
Yassinetaouil 46:b1a9de66ecab 10204 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10205 #define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10206
Yassinetaouil 46:b1a9de66ecab 10207 /* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
Yassinetaouil 46:b1a9de66ecab 10208 #define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10209 #define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10210 #define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10211 #define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10212
Yassinetaouil 46:b1a9de66ecab 10213 /* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
Yassinetaouil 46:b1a9de66ecab 10214 #define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10215 #define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10216 #define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10217 #define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10218
Yassinetaouil 46:b1a9de66ecab 10219 /* Register: PWM_INTEN */
Yassinetaouil 46:b1a9de66ecab 10220 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 10221
Yassinetaouil 46:b1a9de66ecab 10222 /* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
Yassinetaouil 46:b1a9de66ecab 10223 #define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
Yassinetaouil 46:b1a9de66ecab 10224 #define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
Yassinetaouil 46:b1a9de66ecab 10225 #define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10226 #define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10227
Yassinetaouil 46:b1a9de66ecab 10228 /* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
Yassinetaouil 46:b1a9de66ecab 10229 #define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
Yassinetaouil 46:b1a9de66ecab 10230 #define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
Yassinetaouil 46:b1a9de66ecab 10231 #define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10232 #define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10233
Yassinetaouil 46:b1a9de66ecab 10234 /* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
Yassinetaouil 46:b1a9de66ecab 10235 #define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
Yassinetaouil 46:b1a9de66ecab 10236 #define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
Yassinetaouil 46:b1a9de66ecab 10237 #define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10238 #define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10239
Yassinetaouil 46:b1a9de66ecab 10240 /* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
Yassinetaouil 46:b1a9de66ecab 10241 #define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
Yassinetaouil 46:b1a9de66ecab 10242 #define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
Yassinetaouil 46:b1a9de66ecab 10243 #define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10244 #define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10245
Yassinetaouil 46:b1a9de66ecab 10246 /* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
Yassinetaouil 46:b1a9de66ecab 10247 #define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
Yassinetaouil 46:b1a9de66ecab 10248 #define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
Yassinetaouil 46:b1a9de66ecab 10249 #define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10250 #define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10251
Yassinetaouil 46:b1a9de66ecab 10252 /* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
Yassinetaouil 46:b1a9de66ecab 10253 #define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
Yassinetaouil 46:b1a9de66ecab 10254 #define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
Yassinetaouil 46:b1a9de66ecab 10255 #define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10256 #define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10257
Yassinetaouil 46:b1a9de66ecab 10258 /* Bit 1 : Enable or disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 10259 #define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10260 #define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10261 #define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10262 #define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10263
Yassinetaouil 46:b1a9de66ecab 10264 /* Register: PWM_INTENSET */
Yassinetaouil 46:b1a9de66ecab 10265 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 10266
Yassinetaouil 46:b1a9de66ecab 10267 /* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
Yassinetaouil 46:b1a9de66ecab 10268 #define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
Yassinetaouil 46:b1a9de66ecab 10269 #define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
Yassinetaouil 46:b1a9de66ecab 10270 #define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10271 #define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10272 #define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10273
Yassinetaouil 46:b1a9de66ecab 10274 /* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
Yassinetaouil 46:b1a9de66ecab 10275 #define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
Yassinetaouil 46:b1a9de66ecab 10276 #define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
Yassinetaouil 46:b1a9de66ecab 10277 #define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10278 #define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10279 #define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10280
Yassinetaouil 46:b1a9de66ecab 10281 /* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
Yassinetaouil 46:b1a9de66ecab 10282 #define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
Yassinetaouil 46:b1a9de66ecab 10283 #define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
Yassinetaouil 46:b1a9de66ecab 10284 #define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10285 #define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10286 #define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10287
Yassinetaouil 46:b1a9de66ecab 10288 /* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
Yassinetaouil 46:b1a9de66ecab 10289 #define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
Yassinetaouil 46:b1a9de66ecab 10290 #define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
Yassinetaouil 46:b1a9de66ecab 10291 #define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10292 #define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10293 #define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10294
Yassinetaouil 46:b1a9de66ecab 10295 /* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
Yassinetaouil 46:b1a9de66ecab 10296 #define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
Yassinetaouil 46:b1a9de66ecab 10297 #define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
Yassinetaouil 46:b1a9de66ecab 10298 #define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10299 #define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10300 #define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10301
Yassinetaouil 46:b1a9de66ecab 10302 /* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
Yassinetaouil 46:b1a9de66ecab 10303 #define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
Yassinetaouil 46:b1a9de66ecab 10304 #define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
Yassinetaouil 46:b1a9de66ecab 10305 #define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10306 #define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10307 #define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10308
Yassinetaouil 46:b1a9de66ecab 10309 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 10310 #define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10311 #define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10312 #define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10313 #define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10314 #define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10315
Yassinetaouil 46:b1a9de66ecab 10316 /* Register: PWM_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 10317 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 10318
Yassinetaouil 46:b1a9de66ecab 10319 /* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
Yassinetaouil 46:b1a9de66ecab 10320 #define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
Yassinetaouil 46:b1a9de66ecab 10321 #define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
Yassinetaouil 46:b1a9de66ecab 10322 #define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10323 #define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10324 #define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10325
Yassinetaouil 46:b1a9de66ecab 10326 /* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
Yassinetaouil 46:b1a9de66ecab 10327 #define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
Yassinetaouil 46:b1a9de66ecab 10328 #define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
Yassinetaouil 46:b1a9de66ecab 10329 #define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10330 #define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10331 #define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10332
Yassinetaouil 46:b1a9de66ecab 10333 /* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
Yassinetaouil 46:b1a9de66ecab 10334 #define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
Yassinetaouil 46:b1a9de66ecab 10335 #define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
Yassinetaouil 46:b1a9de66ecab 10336 #define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10337 #define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10338 #define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10339
Yassinetaouil 46:b1a9de66ecab 10340 /* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
Yassinetaouil 46:b1a9de66ecab 10341 #define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
Yassinetaouil 46:b1a9de66ecab 10342 #define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
Yassinetaouil 46:b1a9de66ecab 10343 #define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10344 #define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10345 #define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10346
Yassinetaouil 46:b1a9de66ecab 10347 /* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
Yassinetaouil 46:b1a9de66ecab 10348 #define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
Yassinetaouil 46:b1a9de66ecab 10349 #define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
Yassinetaouil 46:b1a9de66ecab 10350 #define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10351 #define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10352 #define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10353
Yassinetaouil 46:b1a9de66ecab 10354 /* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
Yassinetaouil 46:b1a9de66ecab 10355 #define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
Yassinetaouil 46:b1a9de66ecab 10356 #define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
Yassinetaouil 46:b1a9de66ecab 10357 #define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10358 #define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10359 #define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10360
Yassinetaouil 46:b1a9de66ecab 10361 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 10362 #define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10363 #define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10364 #define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10365 #define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10366 #define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10367
Yassinetaouil 46:b1a9de66ecab 10368 /* Register: PWM_ENABLE */
Yassinetaouil 46:b1a9de66ecab 10369 /* Description: PWM module enable register */
Yassinetaouil 46:b1a9de66ecab 10370
Yassinetaouil 46:b1a9de66ecab 10371 /* Bit 0 : Enable or disable PWM module */
Yassinetaouil 46:b1a9de66ecab 10372 #define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 10373 #define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 10374 #define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 10375 #define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10376
Yassinetaouil 46:b1a9de66ecab 10377 /* Register: PWM_MODE */
Yassinetaouil 46:b1a9de66ecab 10378 /* Description: Selects operating mode of the wave counter */
Yassinetaouil 46:b1a9de66ecab 10379
Yassinetaouil 46:b1a9de66ecab 10380 /* Bit 0 : Selects up or up and down as wave counter mode */
Yassinetaouil 46:b1a9de66ecab 10381 #define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
Yassinetaouil 46:b1a9de66ecab 10382 #define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
Yassinetaouil 46:b1a9de66ecab 10383 #define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
Yassinetaouil 46:b1a9de66ecab 10384 #define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
Yassinetaouil 46:b1a9de66ecab 10385
Yassinetaouil 46:b1a9de66ecab 10386 /* Register: PWM_COUNTERTOP */
Yassinetaouil 46:b1a9de66ecab 10387 /* Description: Value up to which the pulse generator counter counts */
Yassinetaouil 46:b1a9de66ecab 10388
Yassinetaouil 46:b1a9de66ecab 10389 /* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
Yassinetaouil 46:b1a9de66ecab 10390 #define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
Yassinetaouil 46:b1a9de66ecab 10391 #define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
Yassinetaouil 46:b1a9de66ecab 10392
Yassinetaouil 46:b1a9de66ecab 10393 /* Register: PWM_PRESCALER */
Yassinetaouil 46:b1a9de66ecab 10394 /* Description: Configuration for PWM_CLK */
Yassinetaouil 46:b1a9de66ecab 10395
Yassinetaouil 46:b1a9de66ecab 10396 /* Bits 2..0 : Pre-scaler of PWM_CLK */
Yassinetaouil 46:b1a9de66ecab 10397 #define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
Yassinetaouil 46:b1a9de66ecab 10398 #define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
Yassinetaouil 46:b1a9de66ecab 10399 #define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by 1 (16MHz) */
Yassinetaouil 46:b1a9de66ecab 10400 #define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by 2 ( 8MHz) */
Yassinetaouil 46:b1a9de66ecab 10401 #define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by 4 ( 4MHz) */
Yassinetaouil 46:b1a9de66ecab 10402 #define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by 8 ( 2MHz) */
Yassinetaouil 46:b1a9de66ecab 10403 #define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by 16 ( 1MHz) */
Yassinetaouil 46:b1a9de66ecab 10404 #define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by 32 ( 500kHz) */
Yassinetaouil 46:b1a9de66ecab 10405 #define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by 64 ( 250kHz) */
Yassinetaouil 46:b1a9de66ecab 10406 #define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
Yassinetaouil 46:b1a9de66ecab 10407
Yassinetaouil 46:b1a9de66ecab 10408 /* Register: PWM_DECODER */
Yassinetaouil 46:b1a9de66ecab 10409 /* Description: Configuration of the decoder */
Yassinetaouil 46:b1a9de66ecab 10410
Yassinetaouil 46:b1a9de66ecab 10411 /* Bit 8 : Selects source for advancing the active sequence */
Yassinetaouil 46:b1a9de66ecab 10412 #define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
Yassinetaouil 46:b1a9de66ecab 10413 #define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
Yassinetaouil 46:b1a9de66ecab 10414 #define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
Yassinetaouil 46:b1a9de66ecab 10415 #define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
Yassinetaouil 46:b1a9de66ecab 10416
Yassinetaouil 46:b1a9de66ecab 10417 /* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
Yassinetaouil 46:b1a9de66ecab 10418 #define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
Yassinetaouil 46:b1a9de66ecab 10419 #define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
Yassinetaouil 46:b1a9de66ecab 10420 #define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
Yassinetaouil 46:b1a9de66ecab 10421 #define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
Yassinetaouil 46:b1a9de66ecab 10422 #define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
Yassinetaouil 46:b1a9de66ecab 10423 #define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
Yassinetaouil 46:b1a9de66ecab 10424
Yassinetaouil 46:b1a9de66ecab 10425 /* Register: PWM_LOOP */
Yassinetaouil 46:b1a9de66ecab 10426 /* Description: Amount of playback of a loop */
Yassinetaouil 46:b1a9de66ecab 10427
Yassinetaouil 46:b1a9de66ecab 10428 /* Bits 15..0 : Amount of playback of pattern cycles */
Yassinetaouil 46:b1a9de66ecab 10429 #define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
Yassinetaouil 46:b1a9de66ecab 10430 #define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
Yassinetaouil 46:b1a9de66ecab 10431 #define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
Yassinetaouil 46:b1a9de66ecab 10432
Yassinetaouil 46:b1a9de66ecab 10433 /* Register: PWM_SEQ_PTR */
Yassinetaouil 46:b1a9de66ecab 10434 /* Description: Description cluster[0]: Beginning address in Data RAM of sequence A */
Yassinetaouil 46:b1a9de66ecab 10435
Yassinetaouil 46:b1a9de66ecab 10436 /* Bits 31..0 : Beginning address in Data RAM of sequence A */
Yassinetaouil 46:b1a9de66ecab 10437 #define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 10438 #define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 10439
Yassinetaouil 46:b1a9de66ecab 10440 /* Register: PWM_SEQ_CNT */
Yassinetaouil 46:b1a9de66ecab 10441 /* Description: Description cluster[0]: Amount of values (duty cycles) in sequence A */
Yassinetaouil 46:b1a9de66ecab 10442
Yassinetaouil 46:b1a9de66ecab 10443 /* Bits 14..0 : Amount of values (duty cycles) in sequence A */
Yassinetaouil 46:b1a9de66ecab 10444 #define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
Yassinetaouil 46:b1a9de66ecab 10445 #define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
Yassinetaouil 46:b1a9de66ecab 10446 #define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
Yassinetaouil 46:b1a9de66ecab 10447
Yassinetaouil 46:b1a9de66ecab 10448 /* Register: PWM_SEQ_REFRESH */
Yassinetaouil 46:b1a9de66ecab 10449 /* Description: Description cluster[0]: Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
Yassinetaouil 46:b1a9de66ecab 10450
Yassinetaouil 46:b1a9de66ecab 10451 /* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
Yassinetaouil 46:b1a9de66ecab 10452 #define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
Yassinetaouil 46:b1a9de66ecab 10453 #define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
Yassinetaouil 46:b1a9de66ecab 10454 #define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
Yassinetaouil 46:b1a9de66ecab 10455
Yassinetaouil 46:b1a9de66ecab 10456 /* Register: PWM_SEQ_ENDDELAY */
Yassinetaouil 46:b1a9de66ecab 10457 /* Description: Description cluster[0]: Time added after the sequence */
Yassinetaouil 46:b1a9de66ecab 10458
Yassinetaouil 46:b1a9de66ecab 10459 /* Bits 23..0 : Time added after the sequence in PWM periods */
Yassinetaouil 46:b1a9de66ecab 10460 #define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
Yassinetaouil 46:b1a9de66ecab 10461 #define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
Yassinetaouil 46:b1a9de66ecab 10462
Yassinetaouil 46:b1a9de66ecab 10463 /* Register: PWM_PSEL_OUT */
Yassinetaouil 46:b1a9de66ecab 10464 /* Description: Description collection[0]: Output pin select for PWM channel 0 */
Yassinetaouil 46:b1a9de66ecab 10465
Yassinetaouil 46:b1a9de66ecab 10466 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 10467 #define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 10468 #define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 10469 #define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 10470 #define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 10471
Yassinetaouil 46:b1a9de66ecab 10472 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 10473 #define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 10474 #define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 10475
Yassinetaouil 46:b1a9de66ecab 10476
Yassinetaouil 46:b1a9de66ecab 10477 /* Peripheral: QDEC */
Yassinetaouil 46:b1a9de66ecab 10478 /* Description: Quadrature Decoder */
Yassinetaouil 46:b1a9de66ecab 10479
Yassinetaouil 46:b1a9de66ecab 10480 /* Register: QDEC_SHORTS */
Yassinetaouil 46:b1a9de66ecab 10481 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 10482
Yassinetaouil 46:b1a9de66ecab 10483 /* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
Yassinetaouil 46:b1a9de66ecab 10484 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
Yassinetaouil 46:b1a9de66ecab 10485 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
Yassinetaouil 46:b1a9de66ecab 10486 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10487 #define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10488
Yassinetaouil 46:b1a9de66ecab 10489 /* Bit 5 : Shortcut between DBLRDY event and STOP task */
Yassinetaouil 46:b1a9de66ecab 10490 #define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10491 #define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10492 #define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10493 #define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10494
Yassinetaouil 46:b1a9de66ecab 10495 /* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
Yassinetaouil 46:b1a9de66ecab 10496 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
Yassinetaouil 46:b1a9de66ecab 10497 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
Yassinetaouil 46:b1a9de66ecab 10498 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10499 #define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10500
Yassinetaouil 46:b1a9de66ecab 10501 /* Bit 3 : Shortcut between REPORTRDY event and STOP task */
Yassinetaouil 46:b1a9de66ecab 10502 #define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10503 #define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10504 #define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10505 #define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10506
Yassinetaouil 46:b1a9de66ecab 10507 /* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
Yassinetaouil 46:b1a9de66ecab 10508 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
Yassinetaouil 46:b1a9de66ecab 10509 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
Yassinetaouil 46:b1a9de66ecab 10510 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10511 #define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10512
Yassinetaouil 46:b1a9de66ecab 10513 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
Yassinetaouil 46:b1a9de66ecab 10514 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10515 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 10516 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10517 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10518
Yassinetaouil 46:b1a9de66ecab 10519 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
Yassinetaouil 46:b1a9de66ecab 10520 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
Yassinetaouil 46:b1a9de66ecab 10521 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
Yassinetaouil 46:b1a9de66ecab 10522 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10523 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10524
Yassinetaouil 46:b1a9de66ecab 10525 /* Register: QDEC_INTENSET */
Yassinetaouil 46:b1a9de66ecab 10526 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 10527
Yassinetaouil 46:b1a9de66ecab 10528 /* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 10529 #define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10530 #define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10531 #define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10532 #define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10533 #define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10534
Yassinetaouil 46:b1a9de66ecab 10535 /* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
Yassinetaouil 46:b1a9de66ecab 10536 #define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
Yassinetaouil 46:b1a9de66ecab 10537 #define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
Yassinetaouil 46:b1a9de66ecab 10538 #define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10539 #define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10540 #define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10541
Yassinetaouil 46:b1a9de66ecab 10542 /* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
Yassinetaouil 46:b1a9de66ecab 10543 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
Yassinetaouil 46:b1a9de66ecab 10544 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
Yassinetaouil 46:b1a9de66ecab 10545 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10546 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10547 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10548
Yassinetaouil 46:b1a9de66ecab 10549 /* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
Yassinetaouil 46:b1a9de66ecab 10550 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
Yassinetaouil 46:b1a9de66ecab 10551 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
Yassinetaouil 46:b1a9de66ecab 10552 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10553 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10554 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10555
Yassinetaouil 46:b1a9de66ecab 10556 /* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
Yassinetaouil 46:b1a9de66ecab 10557 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
Yassinetaouil 46:b1a9de66ecab 10558 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
Yassinetaouil 46:b1a9de66ecab 10559 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10560 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10561 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10562
Yassinetaouil 46:b1a9de66ecab 10563 /* Register: QDEC_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 10564 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 10565
Yassinetaouil 46:b1a9de66ecab 10566 /* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 10567 #define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10568 #define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 10569 #define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10570 #define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10571 #define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10572
Yassinetaouil 46:b1a9de66ecab 10573 /* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
Yassinetaouil 46:b1a9de66ecab 10574 #define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
Yassinetaouil 46:b1a9de66ecab 10575 #define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
Yassinetaouil 46:b1a9de66ecab 10576 #define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10577 #define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10578 #define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10579
Yassinetaouil 46:b1a9de66ecab 10580 /* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
Yassinetaouil 46:b1a9de66ecab 10581 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
Yassinetaouil 46:b1a9de66ecab 10582 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
Yassinetaouil 46:b1a9de66ecab 10583 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10584 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10585 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10586
Yassinetaouil 46:b1a9de66ecab 10587 /* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
Yassinetaouil 46:b1a9de66ecab 10588 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
Yassinetaouil 46:b1a9de66ecab 10589 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
Yassinetaouil 46:b1a9de66ecab 10590 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10591 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10592 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10593
Yassinetaouil 46:b1a9de66ecab 10594 /* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
Yassinetaouil 46:b1a9de66ecab 10595 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
Yassinetaouil 46:b1a9de66ecab 10596 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
Yassinetaouil 46:b1a9de66ecab 10597 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10598 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10599 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10600
Yassinetaouil 46:b1a9de66ecab 10601 /* Register: QDEC_ENABLE */
Yassinetaouil 46:b1a9de66ecab 10602 /* Description: Enable the quadrature decoder */
Yassinetaouil 46:b1a9de66ecab 10603
Yassinetaouil 46:b1a9de66ecab 10604 /* Bit 0 : Enable or disable the quadrature decoder */
Yassinetaouil 46:b1a9de66ecab 10605 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 10606 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 10607 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10608 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10609
Yassinetaouil 46:b1a9de66ecab 10610 /* Register: QDEC_LEDPOL */
Yassinetaouil 46:b1a9de66ecab 10611 /* Description: LED output pin polarity */
Yassinetaouil 46:b1a9de66ecab 10612
Yassinetaouil 46:b1a9de66ecab 10613 /* Bit 0 : LED output pin polarity */
Yassinetaouil 46:b1a9de66ecab 10614 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
Yassinetaouil 46:b1a9de66ecab 10615 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
Yassinetaouil 46:b1a9de66ecab 10616 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
Yassinetaouil 46:b1a9de66ecab 10617 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
Yassinetaouil 46:b1a9de66ecab 10618
Yassinetaouil 46:b1a9de66ecab 10619 /* Register: QDEC_SAMPLEPER */
Yassinetaouil 46:b1a9de66ecab 10620 /* Description: Sample period */
Yassinetaouil 46:b1a9de66ecab 10621
Yassinetaouil 46:b1a9de66ecab 10622 /* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
Yassinetaouil 46:b1a9de66ecab 10623 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
Yassinetaouil 46:b1a9de66ecab 10624 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
Yassinetaouil 46:b1a9de66ecab 10625 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
Yassinetaouil 46:b1a9de66ecab 10626 #define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
Yassinetaouil 46:b1a9de66ecab 10627 #define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
Yassinetaouil 46:b1a9de66ecab 10628 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
Yassinetaouil 46:b1a9de66ecab 10629 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
Yassinetaouil 46:b1a9de66ecab 10630 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
Yassinetaouil 46:b1a9de66ecab 10631 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
Yassinetaouil 46:b1a9de66ecab 10632 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
Yassinetaouil 46:b1a9de66ecab 10633 #define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
Yassinetaouil 46:b1a9de66ecab 10634 #define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
Yassinetaouil 46:b1a9de66ecab 10635 #define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
Yassinetaouil 46:b1a9de66ecab 10636
Yassinetaouil 46:b1a9de66ecab 10637 /* Register: QDEC_SAMPLE */
Yassinetaouil 46:b1a9de66ecab 10638 /* Description: Motion sample value */
Yassinetaouil 46:b1a9de66ecab 10639
Yassinetaouil 46:b1a9de66ecab 10640 /* Bits 31..0 : Last motion sample */
Yassinetaouil 46:b1a9de66ecab 10641 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 10642 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 10643
Yassinetaouil 46:b1a9de66ecab 10644 /* Register: QDEC_REPORTPER */
Yassinetaouil 46:b1a9de66ecab 10645 /* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
Yassinetaouil 46:b1a9de66ecab 10646
Yassinetaouil 46:b1a9de66ecab 10647 /* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
Yassinetaouil 46:b1a9de66ecab 10648 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
Yassinetaouil 46:b1a9de66ecab 10649 #define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
Yassinetaouil 46:b1a9de66ecab 10650 #define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
Yassinetaouil 46:b1a9de66ecab 10651 #define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
Yassinetaouil 46:b1a9de66ecab 10652 #define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
Yassinetaouil 46:b1a9de66ecab 10653 #define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
Yassinetaouil 46:b1a9de66ecab 10654 #define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
Yassinetaouil 46:b1a9de66ecab 10655 #define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
Yassinetaouil 46:b1a9de66ecab 10656 #define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
Yassinetaouil 46:b1a9de66ecab 10657 #define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
Yassinetaouil 46:b1a9de66ecab 10658 #define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
Yassinetaouil 46:b1a9de66ecab 10659
Yassinetaouil 46:b1a9de66ecab 10660 /* Register: QDEC_ACC */
Yassinetaouil 46:b1a9de66ecab 10661 /* Description: Register accumulating the valid transitions */
Yassinetaouil 46:b1a9de66ecab 10662
Yassinetaouil 46:b1a9de66ecab 10663 /* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
Yassinetaouil 46:b1a9de66ecab 10664 #define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
Yassinetaouil 46:b1a9de66ecab 10665 #define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
Yassinetaouil 46:b1a9de66ecab 10666
Yassinetaouil 46:b1a9de66ecab 10667 /* Register: QDEC_ACCREAD */
Yassinetaouil 46:b1a9de66ecab 10668 /* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
Yassinetaouil 46:b1a9de66ecab 10669
Yassinetaouil 46:b1a9de66ecab 10670 /* Bits 31..0 : Snapshot of the ACC register. */
Yassinetaouil 46:b1a9de66ecab 10671 #define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
Yassinetaouil 46:b1a9de66ecab 10672 #define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
Yassinetaouil 46:b1a9de66ecab 10673
Yassinetaouil 46:b1a9de66ecab 10674 /* Register: QDEC_PSEL_LED */
Yassinetaouil 46:b1a9de66ecab 10675 /* Description: Pin select for LED signal */
Yassinetaouil 46:b1a9de66ecab 10676
Yassinetaouil 46:b1a9de66ecab 10677 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 10678 #define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 10679 #define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 10680 #define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 10681 #define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 10682
Yassinetaouil 46:b1a9de66ecab 10683 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 10684 #define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 10685 #define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 10686
Yassinetaouil 46:b1a9de66ecab 10687 /* Register: QDEC_PSEL_A */
Yassinetaouil 46:b1a9de66ecab 10688 /* Description: Pin select for A signal */
Yassinetaouil 46:b1a9de66ecab 10689
Yassinetaouil 46:b1a9de66ecab 10690 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 10691 #define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 10692 #define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 10693 #define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 10694 #define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 10695
Yassinetaouil 46:b1a9de66ecab 10696 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 10697 #define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 10698 #define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 10699
Yassinetaouil 46:b1a9de66ecab 10700 /* Register: QDEC_PSEL_B */
Yassinetaouil 46:b1a9de66ecab 10701 /* Description: Pin select for B signal */
Yassinetaouil 46:b1a9de66ecab 10702
Yassinetaouil 46:b1a9de66ecab 10703 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 10704 #define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 10705 #define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 10706 #define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 10707 #define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 10708
Yassinetaouil 46:b1a9de66ecab 10709 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 10710 #define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 10711 #define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 10712
Yassinetaouil 46:b1a9de66ecab 10713 /* Register: QDEC_DBFEN */
Yassinetaouil 46:b1a9de66ecab 10714 /* Description: Enable input debounce filters */
Yassinetaouil 46:b1a9de66ecab 10715
Yassinetaouil 46:b1a9de66ecab 10716 /* Bit 0 : Enable input debounce filters */
Yassinetaouil 46:b1a9de66ecab 10717 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
Yassinetaouil 46:b1a9de66ecab 10718 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
Yassinetaouil 46:b1a9de66ecab 10719 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
Yassinetaouil 46:b1a9de66ecab 10720 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
Yassinetaouil 46:b1a9de66ecab 10721
Yassinetaouil 46:b1a9de66ecab 10722 /* Register: QDEC_LEDPRE */
Yassinetaouil 46:b1a9de66ecab 10723 /* Description: Time period the LED is switched ON prior to sampling */
Yassinetaouil 46:b1a9de66ecab 10724
Yassinetaouil 46:b1a9de66ecab 10725 /* Bits 8..0 : Period in us the LED is switched on prior to sampling */
Yassinetaouil 46:b1a9de66ecab 10726 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
Yassinetaouil 46:b1a9de66ecab 10727 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
Yassinetaouil 46:b1a9de66ecab 10728
Yassinetaouil 46:b1a9de66ecab 10729 /* Register: QDEC_ACCDBL */
Yassinetaouil 46:b1a9de66ecab 10730 /* Description: Register accumulating the number of detected double transitions */
Yassinetaouil 46:b1a9de66ecab 10731
Yassinetaouil 46:b1a9de66ecab 10732 /* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
Yassinetaouil 46:b1a9de66ecab 10733 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
Yassinetaouil 46:b1a9de66ecab 10734 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
Yassinetaouil 46:b1a9de66ecab 10735
Yassinetaouil 46:b1a9de66ecab 10736 /* Register: QDEC_ACCDBLREAD */
Yassinetaouil 46:b1a9de66ecab 10737 /* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
Yassinetaouil 46:b1a9de66ecab 10738
Yassinetaouil 46:b1a9de66ecab 10739 /* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
Yassinetaouil 46:b1a9de66ecab 10740 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
Yassinetaouil 46:b1a9de66ecab 10741 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
Yassinetaouil 46:b1a9de66ecab 10742
Yassinetaouil 46:b1a9de66ecab 10743
Yassinetaouil 46:b1a9de66ecab 10744 /* Peripheral: RADIO */
Yassinetaouil 46:b1a9de66ecab 10745 /* Description: 2.4 GHz Radio */
Yassinetaouil 46:b1a9de66ecab 10746
Yassinetaouil 46:b1a9de66ecab 10747 /* Register: RADIO_SHORTS */
Yassinetaouil 46:b1a9de66ecab 10748 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 10749
Yassinetaouil 46:b1a9de66ecab 10750 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
Yassinetaouil 46:b1a9de66ecab 10751 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
Yassinetaouil 46:b1a9de66ecab 10752 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
Yassinetaouil 46:b1a9de66ecab 10753 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10754 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10755
Yassinetaouil 46:b1a9de66ecab 10756 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
Yassinetaouil 46:b1a9de66ecab 10757 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
Yassinetaouil 46:b1a9de66ecab 10758 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
Yassinetaouil 46:b1a9de66ecab 10759 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10760 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10761
Yassinetaouil 46:b1a9de66ecab 10762 /* Bit 5 : Shortcut between END event and START task */
Yassinetaouil 46:b1a9de66ecab 10763 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
Yassinetaouil 46:b1a9de66ecab 10764 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
Yassinetaouil 46:b1a9de66ecab 10765 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10766 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10767
Yassinetaouil 46:b1a9de66ecab 10768 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
Yassinetaouil 46:b1a9de66ecab 10769 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
Yassinetaouil 46:b1a9de66ecab 10770 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
Yassinetaouil 46:b1a9de66ecab 10771 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10772 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10773
Yassinetaouil 46:b1a9de66ecab 10774 /* Bit 3 : Shortcut between DISABLED event and RXEN task */
Yassinetaouil 46:b1a9de66ecab 10775 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
Yassinetaouil 46:b1a9de66ecab 10776 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
Yassinetaouil 46:b1a9de66ecab 10777 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10778 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10779
Yassinetaouil 46:b1a9de66ecab 10780 /* Bit 2 : Shortcut between DISABLED event and TXEN task */
Yassinetaouil 46:b1a9de66ecab 10781 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
Yassinetaouil 46:b1a9de66ecab 10782 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
Yassinetaouil 46:b1a9de66ecab 10783 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10784 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10785
Yassinetaouil 46:b1a9de66ecab 10786 /* Bit 1 : Shortcut between END event and DISABLE task */
Yassinetaouil 46:b1a9de66ecab 10787 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
Yassinetaouil 46:b1a9de66ecab 10788 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
Yassinetaouil 46:b1a9de66ecab 10789 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10790 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10791
Yassinetaouil 46:b1a9de66ecab 10792 /* Bit 0 : Shortcut between READY event and START task */
Yassinetaouil 46:b1a9de66ecab 10793 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
Yassinetaouil 46:b1a9de66ecab 10794 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
Yassinetaouil 46:b1a9de66ecab 10795 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 10796 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 10797
Yassinetaouil 46:b1a9de66ecab 10798 /* Register: RADIO_INTENSET */
Yassinetaouil 46:b1a9de66ecab 10799 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 10800
Yassinetaouil 46:b1a9de66ecab 10801 /* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
Yassinetaouil 46:b1a9de66ecab 10802 #define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
Yassinetaouil 46:b1a9de66ecab 10803 #define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
Yassinetaouil 46:b1a9de66ecab 10804 #define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10805 #define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10806 #define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10807
Yassinetaouil 46:b1a9de66ecab 10808 /* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
Yassinetaouil 46:b1a9de66ecab 10809 #define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
Yassinetaouil 46:b1a9de66ecab 10810 #define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
Yassinetaouil 46:b1a9de66ecab 10811 #define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10812 #define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10813 #define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10814
Yassinetaouil 46:b1a9de66ecab 10815 /* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
Yassinetaouil 46:b1a9de66ecab 10816 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10817 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10818 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10819 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10820 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10821
Yassinetaouil 46:b1a9de66ecab 10822 /* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
Yassinetaouil 46:b1a9de66ecab 10823 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
Yassinetaouil 46:b1a9de66ecab 10824 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
Yassinetaouil 46:b1a9de66ecab 10825 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10826 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10827 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10828
Yassinetaouil 46:b1a9de66ecab 10829 /* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
Yassinetaouil 46:b1a9de66ecab 10830 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
Yassinetaouil 46:b1a9de66ecab 10831 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
Yassinetaouil 46:b1a9de66ecab 10832 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10833 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10834 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10835
Yassinetaouil 46:b1a9de66ecab 10836 /* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
Yassinetaouil 46:b1a9de66ecab 10837 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10838 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10839 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10840 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10841 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10842
Yassinetaouil 46:b1a9de66ecab 10843 /* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
Yassinetaouil 46:b1a9de66ecab 10844 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
Yassinetaouil 46:b1a9de66ecab 10845 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
Yassinetaouil 46:b1a9de66ecab 10846 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10847 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10848 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10849
Yassinetaouil 46:b1a9de66ecab 10850 /* Bit 3 : Write '1' to Enable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 10851 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 10852 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 10853 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10854 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10855 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10856
Yassinetaouil 46:b1a9de66ecab 10857 /* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
Yassinetaouil 46:b1a9de66ecab 10858 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
Yassinetaouil 46:b1a9de66ecab 10859 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
Yassinetaouil 46:b1a9de66ecab 10860 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10861 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10862 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10863
Yassinetaouil 46:b1a9de66ecab 10864 /* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
Yassinetaouil 46:b1a9de66ecab 10865 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 10866 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 10867 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10868 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10869 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10870
Yassinetaouil 46:b1a9de66ecab 10871 /* Bit 0 : Write '1' to Enable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 10872 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 10873 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 10874 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10875 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10876 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 10877
Yassinetaouil 46:b1a9de66ecab 10878 /* Register: RADIO_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 10879 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 10880
Yassinetaouil 46:b1a9de66ecab 10881 /* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
Yassinetaouil 46:b1a9de66ecab 10882 #define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
Yassinetaouil 46:b1a9de66ecab 10883 #define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
Yassinetaouil 46:b1a9de66ecab 10884 #define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10885 #define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10886 #define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10887
Yassinetaouil 46:b1a9de66ecab 10888 /* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
Yassinetaouil 46:b1a9de66ecab 10889 #define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
Yassinetaouil 46:b1a9de66ecab 10890 #define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
Yassinetaouil 46:b1a9de66ecab 10891 #define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10892 #define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10893 #define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10894
Yassinetaouil 46:b1a9de66ecab 10895 /* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
Yassinetaouil 46:b1a9de66ecab 10896 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10897 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10898 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10899 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10900 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10901
Yassinetaouil 46:b1a9de66ecab 10902 /* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
Yassinetaouil 46:b1a9de66ecab 10903 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
Yassinetaouil 46:b1a9de66ecab 10904 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
Yassinetaouil 46:b1a9de66ecab 10905 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10906 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10907 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10908
Yassinetaouil 46:b1a9de66ecab 10909 /* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
Yassinetaouil 46:b1a9de66ecab 10910 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
Yassinetaouil 46:b1a9de66ecab 10911 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
Yassinetaouil 46:b1a9de66ecab 10912 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10913 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10914 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10915
Yassinetaouil 46:b1a9de66ecab 10916 /* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
Yassinetaouil 46:b1a9de66ecab 10917 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10918 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10919 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10920 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10921 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10922
Yassinetaouil 46:b1a9de66ecab 10923 /* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
Yassinetaouil 46:b1a9de66ecab 10924 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
Yassinetaouil 46:b1a9de66ecab 10925 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
Yassinetaouil 46:b1a9de66ecab 10926 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10927 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10928 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10929
Yassinetaouil 46:b1a9de66ecab 10930 /* Bit 3 : Write '1' to Disable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 10931 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 10932 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 10933 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10934 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10935 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10936
Yassinetaouil 46:b1a9de66ecab 10937 /* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
Yassinetaouil 46:b1a9de66ecab 10938 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
Yassinetaouil 46:b1a9de66ecab 10939 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
Yassinetaouil 46:b1a9de66ecab 10940 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10941 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10942 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10943
Yassinetaouil 46:b1a9de66ecab 10944 /* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
Yassinetaouil 46:b1a9de66ecab 10945 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 10946 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 10947 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10948 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10949 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10950
Yassinetaouil 46:b1a9de66ecab 10951 /* Bit 0 : Write '1' to Disable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 10952 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 10953 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 10954 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 10955 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 10956 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 10957
Yassinetaouil 46:b1a9de66ecab 10958 /* Register: RADIO_CRCSTATUS */
Yassinetaouil 46:b1a9de66ecab 10959 /* Description: CRC status */
Yassinetaouil 46:b1a9de66ecab 10960
Yassinetaouil 46:b1a9de66ecab 10961 /* Bit 0 : CRC status of packet received */
Yassinetaouil 46:b1a9de66ecab 10962 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
Yassinetaouil 46:b1a9de66ecab 10963 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
Yassinetaouil 46:b1a9de66ecab 10964 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
Yassinetaouil 46:b1a9de66ecab 10965 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
Yassinetaouil 46:b1a9de66ecab 10966
Yassinetaouil 46:b1a9de66ecab 10967 /* Register: RADIO_RXMATCH */
Yassinetaouil 46:b1a9de66ecab 10968 /* Description: Received address */
Yassinetaouil 46:b1a9de66ecab 10969
Yassinetaouil 46:b1a9de66ecab 10970 /* Bits 2..0 : Received address */
Yassinetaouil 46:b1a9de66ecab 10971 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10972 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
Yassinetaouil 46:b1a9de66ecab 10973
Yassinetaouil 46:b1a9de66ecab 10974 /* Register: RADIO_RXCRC */
Yassinetaouil 46:b1a9de66ecab 10975 /* Description: CRC field of previously received packet */
Yassinetaouil 46:b1a9de66ecab 10976
Yassinetaouil 46:b1a9de66ecab 10977 /* Bits 23..0 : CRC field of previously received packet */
Yassinetaouil 46:b1a9de66ecab 10978 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
Yassinetaouil 46:b1a9de66ecab 10979 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
Yassinetaouil 46:b1a9de66ecab 10980
Yassinetaouil 46:b1a9de66ecab 10981 /* Register: RADIO_DAI */
Yassinetaouil 46:b1a9de66ecab 10982 /* Description: Device address match index */
Yassinetaouil 46:b1a9de66ecab 10983
Yassinetaouil 46:b1a9de66ecab 10984 /* Bits 2..0 : Device address match index */
Yassinetaouil 46:b1a9de66ecab 10985 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
Yassinetaouil 46:b1a9de66ecab 10986 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
Yassinetaouil 46:b1a9de66ecab 10987
Yassinetaouil 46:b1a9de66ecab 10988 /* Register: RADIO_PACKETPTR */
Yassinetaouil 46:b1a9de66ecab 10989 /* Description: Packet pointer */
Yassinetaouil 46:b1a9de66ecab 10990
Yassinetaouil 46:b1a9de66ecab 10991 /* Bits 31..0 : Packet pointer */
Yassinetaouil 46:b1a9de66ecab 10992 #define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
Yassinetaouil 46:b1a9de66ecab 10993 #define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
Yassinetaouil 46:b1a9de66ecab 10994
Yassinetaouil 46:b1a9de66ecab 10995 /* Register: RADIO_FREQUENCY */
Yassinetaouil 46:b1a9de66ecab 10996 /* Description: Frequency */
Yassinetaouil 46:b1a9de66ecab 10997
Yassinetaouil 46:b1a9de66ecab 10998 /* Bit 8 : Channel map selection. */
Yassinetaouil 46:b1a9de66ecab 10999 #define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
Yassinetaouil 46:b1a9de66ecab 11000 #define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
Yassinetaouil 46:b1a9de66ecab 11001 #define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
Yassinetaouil 46:b1a9de66ecab 11002 #define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
Yassinetaouil 46:b1a9de66ecab 11003
Yassinetaouil 46:b1a9de66ecab 11004 /* Bits 6..0 : Radio channel frequency */
Yassinetaouil 46:b1a9de66ecab 11005 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 11006 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 11007
Yassinetaouil 46:b1a9de66ecab 11008 /* Register: RADIO_TXPOWER */
Yassinetaouil 46:b1a9de66ecab 11009 /* Description: Output power */
Yassinetaouil 46:b1a9de66ecab 11010
Yassinetaouil 46:b1a9de66ecab 11011 /* Bits 7..0 : RADIO output power. */
Yassinetaouil 46:b1a9de66ecab 11012 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
Yassinetaouil 46:b1a9de66ecab 11013 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
Yassinetaouil 46:b1a9de66ecab 11014 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
Yassinetaouil 46:b1a9de66ecab 11015 #define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
Yassinetaouil 46:b1a9de66ecab 11016 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
Yassinetaouil 46:b1a9de66ecab 11017 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator - -40 dBm */
Yassinetaouil 46:b1a9de66ecab 11018 #define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
Yassinetaouil 46:b1a9de66ecab 11019 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
Yassinetaouil 46:b1a9de66ecab 11020 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
Yassinetaouil 46:b1a9de66ecab 11021 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
Yassinetaouil 46:b1a9de66ecab 11022 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
Yassinetaouil 46:b1a9de66ecab 11023 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
Yassinetaouil 46:b1a9de66ecab 11024
Yassinetaouil 46:b1a9de66ecab 11025 /* Register: RADIO_MODE */
Yassinetaouil 46:b1a9de66ecab 11026 /* Description: Data rate and modulation */
Yassinetaouil 46:b1a9de66ecab 11027
Yassinetaouil 46:b1a9de66ecab 11028 /* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
Yassinetaouil 46:b1a9de66ecab 11029 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Yassinetaouil 46:b1a9de66ecab 11030 #define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Yassinetaouil 46:b1a9de66ecab 11031 #define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
Yassinetaouil 46:b1a9de66ecab 11032 #define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
Yassinetaouil 46:b1a9de66ecab 11033 #define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode */
Yassinetaouil 46:b1a9de66ecab 11034 #define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
Yassinetaouil 46:b1a9de66ecab 11035
Yassinetaouil 46:b1a9de66ecab 11036 /* Register: RADIO_PCNF0 */
Yassinetaouil 46:b1a9de66ecab 11037 /* Description: Packet configuration register 0 */
Yassinetaouil 46:b1a9de66ecab 11038
Yassinetaouil 46:b1a9de66ecab 11039 /* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
Yassinetaouil 46:b1a9de66ecab 11040 #define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
Yassinetaouil 46:b1a9de66ecab 11041 #define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
Yassinetaouil 46:b1a9de66ecab 11042 #define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
Yassinetaouil 46:b1a9de66ecab 11043 #define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
Yassinetaouil 46:b1a9de66ecab 11044
Yassinetaouil 46:b1a9de66ecab 11045 /* Bit 20 : Include or exclude S1 field in RAM */
Yassinetaouil 46:b1a9de66ecab 11046 #define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
Yassinetaouil 46:b1a9de66ecab 11047 #define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
Yassinetaouil 46:b1a9de66ecab 11048 #define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
Yassinetaouil 46:b1a9de66ecab 11049 #define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
Yassinetaouil 46:b1a9de66ecab 11050
Yassinetaouil 46:b1a9de66ecab 11051 /* Bits 19..16 : Length on air of S1 field in number of bits. */
Yassinetaouil 46:b1a9de66ecab 11052 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
Yassinetaouil 46:b1a9de66ecab 11053 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
Yassinetaouil 46:b1a9de66ecab 11054
Yassinetaouil 46:b1a9de66ecab 11055 /* Bit 8 : Length on air of S0 field in number of bytes. */
Yassinetaouil 46:b1a9de66ecab 11056 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
Yassinetaouil 46:b1a9de66ecab 11057 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
Yassinetaouil 46:b1a9de66ecab 11058
Yassinetaouil 46:b1a9de66ecab 11059 /* Bits 3..0 : Length on air of LENGTH field in number of bits. */
Yassinetaouil 46:b1a9de66ecab 11060 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
Yassinetaouil 46:b1a9de66ecab 11061 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
Yassinetaouil 46:b1a9de66ecab 11062
Yassinetaouil 46:b1a9de66ecab 11063 /* Register: RADIO_PCNF1 */
Yassinetaouil 46:b1a9de66ecab 11064 /* Description: Packet configuration register 1 */
Yassinetaouil 46:b1a9de66ecab 11065
Yassinetaouil 46:b1a9de66ecab 11066 /* Bit 25 : Enable or disable packet whitening */
Yassinetaouil 46:b1a9de66ecab 11067 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
Yassinetaouil 46:b1a9de66ecab 11068 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
Yassinetaouil 46:b1a9de66ecab 11069 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11070 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11071
Yassinetaouil 46:b1a9de66ecab 11072 /* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
Yassinetaouil 46:b1a9de66ecab 11073 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
Yassinetaouil 46:b1a9de66ecab 11074 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
Yassinetaouil 46:b1a9de66ecab 11075 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
Yassinetaouil 46:b1a9de66ecab 11076 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
Yassinetaouil 46:b1a9de66ecab 11077
Yassinetaouil 46:b1a9de66ecab 11078 /* Bits 18..16 : Base address length in number of bytes */
Yassinetaouil 46:b1a9de66ecab 11079 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
Yassinetaouil 46:b1a9de66ecab 11080 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
Yassinetaouil 46:b1a9de66ecab 11081
Yassinetaouil 46:b1a9de66ecab 11082 /* Bits 15..8 : Static length in number of bytes */
Yassinetaouil 46:b1a9de66ecab 11083 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
Yassinetaouil 46:b1a9de66ecab 11084 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
Yassinetaouil 46:b1a9de66ecab 11085
Yassinetaouil 46:b1a9de66ecab 11086 /* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
Yassinetaouil 46:b1a9de66ecab 11087 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
Yassinetaouil 46:b1a9de66ecab 11088 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
Yassinetaouil 46:b1a9de66ecab 11089
Yassinetaouil 46:b1a9de66ecab 11090 /* Register: RADIO_BASE0 */
Yassinetaouil 46:b1a9de66ecab 11091 /* Description: Base address 0 */
Yassinetaouil 46:b1a9de66ecab 11092
Yassinetaouil 46:b1a9de66ecab 11093 /* Bits 31..0 : Base address 0 */
Yassinetaouil 46:b1a9de66ecab 11094 #define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
Yassinetaouil 46:b1a9de66ecab 11095 #define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
Yassinetaouil 46:b1a9de66ecab 11096
Yassinetaouil 46:b1a9de66ecab 11097 /* Register: RADIO_BASE1 */
Yassinetaouil 46:b1a9de66ecab 11098 /* Description: Base address 1 */
Yassinetaouil 46:b1a9de66ecab 11099
Yassinetaouil 46:b1a9de66ecab 11100 /* Bits 31..0 : Base address 1 */
Yassinetaouil 46:b1a9de66ecab 11101 #define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
Yassinetaouil 46:b1a9de66ecab 11102 #define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
Yassinetaouil 46:b1a9de66ecab 11103
Yassinetaouil 46:b1a9de66ecab 11104 /* Register: RADIO_PREFIX0 */
Yassinetaouil 46:b1a9de66ecab 11105 /* Description: Prefixes bytes for logical addresses 0-3 */
Yassinetaouil 46:b1a9de66ecab 11106
Yassinetaouil 46:b1a9de66ecab 11107 /* Bits 31..24 : Address prefix 3. */
Yassinetaouil 46:b1a9de66ecab 11108 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
Yassinetaouil 46:b1a9de66ecab 11109 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
Yassinetaouil 46:b1a9de66ecab 11110
Yassinetaouil 46:b1a9de66ecab 11111 /* Bits 23..16 : Address prefix 2. */
Yassinetaouil 46:b1a9de66ecab 11112 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
Yassinetaouil 46:b1a9de66ecab 11113 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
Yassinetaouil 46:b1a9de66ecab 11114
Yassinetaouil 46:b1a9de66ecab 11115 /* Bits 15..8 : Address prefix 1. */
Yassinetaouil 46:b1a9de66ecab 11116 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
Yassinetaouil 46:b1a9de66ecab 11117 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
Yassinetaouil 46:b1a9de66ecab 11118
Yassinetaouil 46:b1a9de66ecab 11119 /* Bits 7..0 : Address prefix 0. */
Yassinetaouil 46:b1a9de66ecab 11120 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
Yassinetaouil 46:b1a9de66ecab 11121 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
Yassinetaouil 46:b1a9de66ecab 11122
Yassinetaouil 46:b1a9de66ecab 11123 /* Register: RADIO_PREFIX1 */
Yassinetaouil 46:b1a9de66ecab 11124 /* Description: Prefixes bytes for logical addresses 4-7 */
Yassinetaouil 46:b1a9de66ecab 11125
Yassinetaouil 46:b1a9de66ecab 11126 /* Bits 31..24 : Address prefix 7. */
Yassinetaouil 46:b1a9de66ecab 11127 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
Yassinetaouil 46:b1a9de66ecab 11128 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
Yassinetaouil 46:b1a9de66ecab 11129
Yassinetaouil 46:b1a9de66ecab 11130 /* Bits 23..16 : Address prefix 6. */
Yassinetaouil 46:b1a9de66ecab 11131 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
Yassinetaouil 46:b1a9de66ecab 11132 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
Yassinetaouil 46:b1a9de66ecab 11133
Yassinetaouil 46:b1a9de66ecab 11134 /* Bits 15..8 : Address prefix 5. */
Yassinetaouil 46:b1a9de66ecab 11135 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
Yassinetaouil 46:b1a9de66ecab 11136 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
Yassinetaouil 46:b1a9de66ecab 11137
Yassinetaouil 46:b1a9de66ecab 11138 /* Bits 7..0 : Address prefix 4. */
Yassinetaouil 46:b1a9de66ecab 11139 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
Yassinetaouil 46:b1a9de66ecab 11140 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
Yassinetaouil 46:b1a9de66ecab 11141
Yassinetaouil 46:b1a9de66ecab 11142 /* Register: RADIO_TXADDRESS */
Yassinetaouil 46:b1a9de66ecab 11143 /* Description: Transmit address select */
Yassinetaouil 46:b1a9de66ecab 11144
Yassinetaouil 46:b1a9de66ecab 11145 /* Bits 2..0 : Transmit address select */
Yassinetaouil 46:b1a9de66ecab 11146 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 11147 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 11148
Yassinetaouil 46:b1a9de66ecab 11149 /* Register: RADIO_RXADDRESSES */
Yassinetaouil 46:b1a9de66ecab 11150 /* Description: Receive address select */
Yassinetaouil 46:b1a9de66ecab 11151
Yassinetaouil 46:b1a9de66ecab 11152 /* Bit 7 : Enable or disable reception on logical address 7. */
Yassinetaouil 46:b1a9de66ecab 11153 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
Yassinetaouil 46:b1a9de66ecab 11154 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
Yassinetaouil 46:b1a9de66ecab 11155 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11156 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11157
Yassinetaouil 46:b1a9de66ecab 11158 /* Bit 6 : Enable or disable reception on logical address 6. */
Yassinetaouil 46:b1a9de66ecab 11159 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
Yassinetaouil 46:b1a9de66ecab 11160 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
Yassinetaouil 46:b1a9de66ecab 11161 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11162 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11163
Yassinetaouil 46:b1a9de66ecab 11164 /* Bit 5 : Enable or disable reception on logical address 5. */
Yassinetaouil 46:b1a9de66ecab 11165 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
Yassinetaouil 46:b1a9de66ecab 11166 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
Yassinetaouil 46:b1a9de66ecab 11167 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11168 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11169
Yassinetaouil 46:b1a9de66ecab 11170 /* Bit 4 : Enable or disable reception on logical address 4. */
Yassinetaouil 46:b1a9de66ecab 11171 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
Yassinetaouil 46:b1a9de66ecab 11172 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
Yassinetaouil 46:b1a9de66ecab 11173 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11174 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11175
Yassinetaouil 46:b1a9de66ecab 11176 /* Bit 3 : Enable or disable reception on logical address 3. */
Yassinetaouil 46:b1a9de66ecab 11177 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
Yassinetaouil 46:b1a9de66ecab 11178 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
Yassinetaouil 46:b1a9de66ecab 11179 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11180 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11181
Yassinetaouil 46:b1a9de66ecab 11182 /* Bit 2 : Enable or disable reception on logical address 2. */
Yassinetaouil 46:b1a9de66ecab 11183 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
Yassinetaouil 46:b1a9de66ecab 11184 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
Yassinetaouil 46:b1a9de66ecab 11185 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11186 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11187
Yassinetaouil 46:b1a9de66ecab 11188 /* Bit 1 : Enable or disable reception on logical address 1. */
Yassinetaouil 46:b1a9de66ecab 11189 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
Yassinetaouil 46:b1a9de66ecab 11190 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
Yassinetaouil 46:b1a9de66ecab 11191 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11192 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11193
Yassinetaouil 46:b1a9de66ecab 11194 /* Bit 0 : Enable or disable reception on logical address 0. */
Yassinetaouil 46:b1a9de66ecab 11195 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
Yassinetaouil 46:b1a9de66ecab 11196 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
Yassinetaouil 46:b1a9de66ecab 11197 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11198 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11199
Yassinetaouil 46:b1a9de66ecab 11200 /* Register: RADIO_CRCCNF */
Yassinetaouil 46:b1a9de66ecab 11201 /* Description: CRC configuration */
Yassinetaouil 46:b1a9de66ecab 11202
Yassinetaouil 46:b1a9de66ecab 11203 /* Bit 8 : Include or exclude packet address field out of CRC calculation. */
Yassinetaouil 46:b1a9de66ecab 11204 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
Yassinetaouil 46:b1a9de66ecab 11205 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
Yassinetaouil 46:b1a9de66ecab 11206 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
Yassinetaouil 46:b1a9de66ecab 11207 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
Yassinetaouil 46:b1a9de66ecab 11208
Yassinetaouil 46:b1a9de66ecab 11209 /* Bits 1..0 : CRC length in number of bytes. */
Yassinetaouil 46:b1a9de66ecab 11210 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
Yassinetaouil 46:b1a9de66ecab 11211 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
Yassinetaouil 46:b1a9de66ecab 11212 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
Yassinetaouil 46:b1a9de66ecab 11213 #define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
Yassinetaouil 46:b1a9de66ecab 11214 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
Yassinetaouil 46:b1a9de66ecab 11215 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
Yassinetaouil 46:b1a9de66ecab 11216
Yassinetaouil 46:b1a9de66ecab 11217 /* Register: RADIO_CRCPOLY */
Yassinetaouil 46:b1a9de66ecab 11218 /* Description: CRC polynomial */
Yassinetaouil 46:b1a9de66ecab 11219
Yassinetaouil 46:b1a9de66ecab 11220 /* Bits 23..0 : CRC polynomial */
Yassinetaouil 46:b1a9de66ecab 11221 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
Yassinetaouil 46:b1a9de66ecab 11222 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
Yassinetaouil 46:b1a9de66ecab 11223
Yassinetaouil 46:b1a9de66ecab 11224 /* Register: RADIO_CRCINIT */
Yassinetaouil 46:b1a9de66ecab 11225 /* Description: CRC initial value */
Yassinetaouil 46:b1a9de66ecab 11226
Yassinetaouil 46:b1a9de66ecab 11227 /* Bits 23..0 : CRC initial value */
Yassinetaouil 46:b1a9de66ecab 11228 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
Yassinetaouil 46:b1a9de66ecab 11229 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
Yassinetaouil 46:b1a9de66ecab 11230
Yassinetaouil 46:b1a9de66ecab 11231 /* Register: RADIO_TIFS */
Yassinetaouil 46:b1a9de66ecab 11232 /* Description: Inter Frame Spacing in us */
Yassinetaouil 46:b1a9de66ecab 11233
Yassinetaouil 46:b1a9de66ecab 11234 /* Bits 7..0 : Inter Frame Spacing in us */
Yassinetaouil 46:b1a9de66ecab 11235 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
Yassinetaouil 46:b1a9de66ecab 11236 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
Yassinetaouil 46:b1a9de66ecab 11237
Yassinetaouil 46:b1a9de66ecab 11238 /* Register: RADIO_RSSISAMPLE */
Yassinetaouil 46:b1a9de66ecab 11239 /* Description: RSSI sample */
Yassinetaouil 46:b1a9de66ecab 11240
Yassinetaouil 46:b1a9de66ecab 11241 /* Bits 6..0 : RSSI sample */
Yassinetaouil 46:b1a9de66ecab 11242 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 11243 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 11244
Yassinetaouil 46:b1a9de66ecab 11245 /* Register: RADIO_STATE */
Yassinetaouil 46:b1a9de66ecab 11246 /* Description: Current radio state */
Yassinetaouil 46:b1a9de66ecab 11247
Yassinetaouil 46:b1a9de66ecab 11248 /* Bits 3..0 : Current radio state */
Yassinetaouil 46:b1a9de66ecab 11249 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
Yassinetaouil 46:b1a9de66ecab 11250 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
Yassinetaouil 46:b1a9de66ecab 11251 #define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
Yassinetaouil 46:b1a9de66ecab 11252 #define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
Yassinetaouil 46:b1a9de66ecab 11253 #define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
Yassinetaouil 46:b1a9de66ecab 11254 #define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
Yassinetaouil 46:b1a9de66ecab 11255 #define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
Yassinetaouil 46:b1a9de66ecab 11256 #define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
Yassinetaouil 46:b1a9de66ecab 11257 #define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
Yassinetaouil 46:b1a9de66ecab 11258 #define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
Yassinetaouil 46:b1a9de66ecab 11259 #define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
Yassinetaouil 46:b1a9de66ecab 11260
Yassinetaouil 46:b1a9de66ecab 11261 /* Register: RADIO_DATAWHITEIV */
Yassinetaouil 46:b1a9de66ecab 11262 /* Description: Data whitening initial value */
Yassinetaouil 46:b1a9de66ecab 11263
Yassinetaouil 46:b1a9de66ecab 11264 /* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
Yassinetaouil 46:b1a9de66ecab 11265 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
Yassinetaouil 46:b1a9de66ecab 11266 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
Yassinetaouil 46:b1a9de66ecab 11267
Yassinetaouil 46:b1a9de66ecab 11268 /* Register: RADIO_BCC */
Yassinetaouil 46:b1a9de66ecab 11269 /* Description: Bit counter compare */
Yassinetaouil 46:b1a9de66ecab 11270
Yassinetaouil 46:b1a9de66ecab 11271 /* Bits 31..0 : Bit counter compare */
Yassinetaouil 46:b1a9de66ecab 11272 #define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
Yassinetaouil 46:b1a9de66ecab 11273 #define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
Yassinetaouil 46:b1a9de66ecab 11274
Yassinetaouil 46:b1a9de66ecab 11275 /* Register: RADIO_DAB */
Yassinetaouil 46:b1a9de66ecab 11276 /* Description: Description collection[0]: Device address base segment 0 */
Yassinetaouil 46:b1a9de66ecab 11277
Yassinetaouil 46:b1a9de66ecab 11278 /* Bits 31..0 : Device address base segment 0 */
Yassinetaouil 46:b1a9de66ecab 11279 #define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
Yassinetaouil 46:b1a9de66ecab 11280 #define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
Yassinetaouil 46:b1a9de66ecab 11281
Yassinetaouil 46:b1a9de66ecab 11282 /* Register: RADIO_DAP */
Yassinetaouil 46:b1a9de66ecab 11283 /* Description: Description collection[0]: Device address prefix 0 */
Yassinetaouil 46:b1a9de66ecab 11284
Yassinetaouil 46:b1a9de66ecab 11285 /* Bits 15..0 : Device address prefix 0 */
Yassinetaouil 46:b1a9de66ecab 11286 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
Yassinetaouil 46:b1a9de66ecab 11287 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
Yassinetaouil 46:b1a9de66ecab 11288
Yassinetaouil 46:b1a9de66ecab 11289 /* Register: RADIO_DACNF */
Yassinetaouil 46:b1a9de66ecab 11290 /* Description: Device address match configuration */
Yassinetaouil 46:b1a9de66ecab 11291
Yassinetaouil 46:b1a9de66ecab 11292 /* Bit 15 : TxAdd for device address 7 */
Yassinetaouil 46:b1a9de66ecab 11293 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
Yassinetaouil 46:b1a9de66ecab 11294 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
Yassinetaouil 46:b1a9de66ecab 11295
Yassinetaouil 46:b1a9de66ecab 11296 /* Bit 14 : TxAdd for device address 6 */
Yassinetaouil 46:b1a9de66ecab 11297 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
Yassinetaouil 46:b1a9de66ecab 11298 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
Yassinetaouil 46:b1a9de66ecab 11299
Yassinetaouil 46:b1a9de66ecab 11300 /* Bit 13 : TxAdd for device address 5 */
Yassinetaouil 46:b1a9de66ecab 11301 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
Yassinetaouil 46:b1a9de66ecab 11302 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
Yassinetaouil 46:b1a9de66ecab 11303
Yassinetaouil 46:b1a9de66ecab 11304 /* Bit 12 : TxAdd for device address 4 */
Yassinetaouil 46:b1a9de66ecab 11305 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
Yassinetaouil 46:b1a9de66ecab 11306 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
Yassinetaouil 46:b1a9de66ecab 11307
Yassinetaouil 46:b1a9de66ecab 11308 /* Bit 11 : TxAdd for device address 3 */
Yassinetaouil 46:b1a9de66ecab 11309 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
Yassinetaouil 46:b1a9de66ecab 11310 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
Yassinetaouil 46:b1a9de66ecab 11311
Yassinetaouil 46:b1a9de66ecab 11312 /* Bit 10 : TxAdd for device address 2 */
Yassinetaouil 46:b1a9de66ecab 11313 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
Yassinetaouil 46:b1a9de66ecab 11314 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
Yassinetaouil 46:b1a9de66ecab 11315
Yassinetaouil 46:b1a9de66ecab 11316 /* Bit 9 : TxAdd for device address 1 */
Yassinetaouil 46:b1a9de66ecab 11317 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
Yassinetaouil 46:b1a9de66ecab 11318 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
Yassinetaouil 46:b1a9de66ecab 11319
Yassinetaouil 46:b1a9de66ecab 11320 /* Bit 8 : TxAdd for device address 0 */
Yassinetaouil 46:b1a9de66ecab 11321 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
Yassinetaouil 46:b1a9de66ecab 11322 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
Yassinetaouil 46:b1a9de66ecab 11323
Yassinetaouil 46:b1a9de66ecab 11324 /* Bit 7 : Enable or disable device address matching using device address 7 */
Yassinetaouil 46:b1a9de66ecab 11325 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
Yassinetaouil 46:b1a9de66ecab 11326 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
Yassinetaouil 46:b1a9de66ecab 11327 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11328 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11329
Yassinetaouil 46:b1a9de66ecab 11330 /* Bit 6 : Enable or disable device address matching using device address 6 */
Yassinetaouil 46:b1a9de66ecab 11331 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
Yassinetaouil 46:b1a9de66ecab 11332 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
Yassinetaouil 46:b1a9de66ecab 11333 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11334 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11335
Yassinetaouil 46:b1a9de66ecab 11336 /* Bit 5 : Enable or disable device address matching using device address 5 */
Yassinetaouil 46:b1a9de66ecab 11337 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
Yassinetaouil 46:b1a9de66ecab 11338 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
Yassinetaouil 46:b1a9de66ecab 11339 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11340 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11341
Yassinetaouil 46:b1a9de66ecab 11342 /* Bit 4 : Enable or disable device address matching using device address 4 */
Yassinetaouil 46:b1a9de66ecab 11343 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
Yassinetaouil 46:b1a9de66ecab 11344 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
Yassinetaouil 46:b1a9de66ecab 11345 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11346 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11347
Yassinetaouil 46:b1a9de66ecab 11348 /* Bit 3 : Enable or disable device address matching using device address 3 */
Yassinetaouil 46:b1a9de66ecab 11349 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
Yassinetaouil 46:b1a9de66ecab 11350 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
Yassinetaouil 46:b1a9de66ecab 11351 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11352 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11353
Yassinetaouil 46:b1a9de66ecab 11354 /* Bit 2 : Enable or disable device address matching using device address 2 */
Yassinetaouil 46:b1a9de66ecab 11355 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
Yassinetaouil 46:b1a9de66ecab 11356 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
Yassinetaouil 46:b1a9de66ecab 11357 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11358 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11359
Yassinetaouil 46:b1a9de66ecab 11360 /* Bit 1 : Enable or disable device address matching using device address 1 */
Yassinetaouil 46:b1a9de66ecab 11361 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
Yassinetaouil 46:b1a9de66ecab 11362 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
Yassinetaouil 46:b1a9de66ecab 11363 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11364 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11365
Yassinetaouil 46:b1a9de66ecab 11366 /* Bit 0 : Enable or disable device address matching using device address 0 */
Yassinetaouil 46:b1a9de66ecab 11367 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
Yassinetaouil 46:b1a9de66ecab 11368 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
Yassinetaouil 46:b1a9de66ecab 11369 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11370 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11371
Yassinetaouil 46:b1a9de66ecab 11372 /* Register: RADIO_MODECNF0 */
Yassinetaouil 46:b1a9de66ecab 11373 /* Description: Radio mode configuration register 0 */
Yassinetaouil 46:b1a9de66ecab 11374
Yassinetaouil 46:b1a9de66ecab 11375 /* Bits 9..8 : Default TX value */
Yassinetaouil 46:b1a9de66ecab 11376 #define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
Yassinetaouil 46:b1a9de66ecab 11377 #define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
Yassinetaouil 46:b1a9de66ecab 11378 #define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
Yassinetaouil 46:b1a9de66ecab 11379 #define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
Yassinetaouil 46:b1a9de66ecab 11380 #define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
Yassinetaouil 46:b1a9de66ecab 11381
Yassinetaouil 46:b1a9de66ecab 11382 /* Bit 0 : Radio ramp-up time */
Yassinetaouil 46:b1a9de66ecab 11383 #define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
Yassinetaouil 46:b1a9de66ecab 11384 #define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
Yassinetaouil 46:b1a9de66ecab 11385 #define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
Yassinetaouil 46:b1a9de66ecab 11386 #define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
Yassinetaouil 46:b1a9de66ecab 11387
Yassinetaouil 46:b1a9de66ecab 11388 /* Register: RADIO_POWER */
Yassinetaouil 46:b1a9de66ecab 11389 /* Description: Peripheral power control */
Yassinetaouil 46:b1a9de66ecab 11390
Yassinetaouil 46:b1a9de66ecab 11391 /* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
Yassinetaouil 46:b1a9de66ecab 11392 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Yassinetaouil 46:b1a9de66ecab 11393 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Yassinetaouil 46:b1a9de66ecab 11394 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
Yassinetaouil 46:b1a9de66ecab 11395 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
Yassinetaouil 46:b1a9de66ecab 11396
Yassinetaouil 46:b1a9de66ecab 11397
Yassinetaouil 46:b1a9de66ecab 11398 /* Peripheral: RNG */
Yassinetaouil 46:b1a9de66ecab 11399 /* Description: Random Number Generator */
Yassinetaouil 46:b1a9de66ecab 11400
Yassinetaouil 46:b1a9de66ecab 11401 /* Register: RNG_SHORTS */
Yassinetaouil 46:b1a9de66ecab 11402 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 11403
Yassinetaouil 46:b1a9de66ecab 11404 /* Bit 0 : Shortcut between VALRDY event and STOP task */
Yassinetaouil 46:b1a9de66ecab 11405 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 11406 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
Yassinetaouil 46:b1a9de66ecab 11407 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 11408 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 11409
Yassinetaouil 46:b1a9de66ecab 11410 /* Register: RNG_INTENSET */
Yassinetaouil 46:b1a9de66ecab 11411 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 11412
Yassinetaouil 46:b1a9de66ecab 11413 /* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
Yassinetaouil 46:b1a9de66ecab 11414 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
Yassinetaouil 46:b1a9de66ecab 11415 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
Yassinetaouil 46:b1a9de66ecab 11416 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11417 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11418 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11419
Yassinetaouil 46:b1a9de66ecab 11420 /* Register: RNG_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 11421 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 11422
Yassinetaouil 46:b1a9de66ecab 11423 /* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
Yassinetaouil 46:b1a9de66ecab 11424 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
Yassinetaouil 46:b1a9de66ecab 11425 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
Yassinetaouil 46:b1a9de66ecab 11426 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11427 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11428 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11429
Yassinetaouil 46:b1a9de66ecab 11430 /* Register: RNG_CONFIG */
Yassinetaouil 46:b1a9de66ecab 11431 /* Description: Configuration register */
Yassinetaouil 46:b1a9de66ecab 11432
Yassinetaouil 46:b1a9de66ecab 11433 /* Bit 0 : Bias correction */
Yassinetaouil 46:b1a9de66ecab 11434 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
Yassinetaouil 46:b1a9de66ecab 11435 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
Yassinetaouil 46:b1a9de66ecab 11436 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 11437 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 11438
Yassinetaouil 46:b1a9de66ecab 11439 /* Register: RNG_VALUE */
Yassinetaouil 46:b1a9de66ecab 11440 /* Description: Output random number */
Yassinetaouil 46:b1a9de66ecab 11441
Yassinetaouil 46:b1a9de66ecab 11442 /* Bits 7..0 : Generated random number */
Yassinetaouil 46:b1a9de66ecab 11443 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
Yassinetaouil 46:b1a9de66ecab 11444 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
Yassinetaouil 46:b1a9de66ecab 11445
Yassinetaouil 46:b1a9de66ecab 11446
Yassinetaouil 46:b1a9de66ecab 11447 /* Peripheral: RTC */
Yassinetaouil 46:b1a9de66ecab 11448 /* Description: Real time counter 0 */
Yassinetaouil 46:b1a9de66ecab 11449
Yassinetaouil 46:b1a9de66ecab 11450 /* Register: RTC_INTENSET */
Yassinetaouil 46:b1a9de66ecab 11451 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 11452
Yassinetaouil 46:b1a9de66ecab 11453 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
Yassinetaouil 46:b1a9de66ecab 11454 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11455 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11456 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11457 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11458 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11459
Yassinetaouil 46:b1a9de66ecab 11460 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
Yassinetaouil 46:b1a9de66ecab 11461 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11462 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11463 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11464 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11465 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11466
Yassinetaouil 46:b1a9de66ecab 11467 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
Yassinetaouil 46:b1a9de66ecab 11468 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11469 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11470 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11471 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11472 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11473
Yassinetaouil 46:b1a9de66ecab 11474 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
Yassinetaouil 46:b1a9de66ecab 11475 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11476 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11477 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11478 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11479 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11480
Yassinetaouil 46:b1a9de66ecab 11481 /* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
Yassinetaouil 46:b1a9de66ecab 11482 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11483 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11484 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11485 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11486 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11487
Yassinetaouil 46:b1a9de66ecab 11488 /* Bit 0 : Write '1' to Enable interrupt for TICK event */
Yassinetaouil 46:b1a9de66ecab 11489 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11490 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11491 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11492 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11493 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11494
Yassinetaouil 46:b1a9de66ecab 11495 /* Register: RTC_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 11496 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 11497
Yassinetaouil 46:b1a9de66ecab 11498 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
Yassinetaouil 46:b1a9de66ecab 11499 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11500 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11501 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11502 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11503 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11504
Yassinetaouil 46:b1a9de66ecab 11505 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
Yassinetaouil 46:b1a9de66ecab 11506 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11507 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11508 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11509 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11510 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11511
Yassinetaouil 46:b1a9de66ecab 11512 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
Yassinetaouil 46:b1a9de66ecab 11513 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11514 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11515 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11516 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11517 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11518
Yassinetaouil 46:b1a9de66ecab 11519 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
Yassinetaouil 46:b1a9de66ecab 11520 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11521 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11522 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11523 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11524 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11525
Yassinetaouil 46:b1a9de66ecab 11526 /* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
Yassinetaouil 46:b1a9de66ecab 11527 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11528 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11529 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11530 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11531 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11532
Yassinetaouil 46:b1a9de66ecab 11533 /* Bit 0 : Write '1' to Disable interrupt for TICK event */
Yassinetaouil 46:b1a9de66ecab 11534 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11535 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11536 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11537 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11538 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11539
Yassinetaouil 46:b1a9de66ecab 11540 /* Register: RTC_EVTEN */
Yassinetaouil 46:b1a9de66ecab 11541 /* Description: Enable or disable event routing */
Yassinetaouil 46:b1a9de66ecab 11542
Yassinetaouil 46:b1a9de66ecab 11543 /* Bit 19 : Enable or disable event routing for COMPARE[3] event */
Yassinetaouil 46:b1a9de66ecab 11544 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11545 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11546 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11547 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11548
Yassinetaouil 46:b1a9de66ecab 11549 /* Bit 18 : Enable or disable event routing for COMPARE[2] event */
Yassinetaouil 46:b1a9de66ecab 11550 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11551 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11552 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11553 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11554
Yassinetaouil 46:b1a9de66ecab 11555 /* Bit 17 : Enable or disable event routing for COMPARE[1] event */
Yassinetaouil 46:b1a9de66ecab 11556 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11557 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11558 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11559 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11560
Yassinetaouil 46:b1a9de66ecab 11561 /* Bit 16 : Enable or disable event routing for COMPARE[0] event */
Yassinetaouil 46:b1a9de66ecab 11562 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11563 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11564 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11565 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11566
Yassinetaouil 46:b1a9de66ecab 11567 /* Bit 1 : Enable or disable event routing for OVRFLW event */
Yassinetaouil 46:b1a9de66ecab 11568 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11569 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11570 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11571 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11572
Yassinetaouil 46:b1a9de66ecab 11573 /* Bit 0 : Enable or disable event routing for TICK event */
Yassinetaouil 46:b1a9de66ecab 11574 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11575 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11576 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11577 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11578
Yassinetaouil 46:b1a9de66ecab 11579 /* Register: RTC_EVTENSET */
Yassinetaouil 46:b1a9de66ecab 11580 /* Description: Enable event routing */
Yassinetaouil 46:b1a9de66ecab 11581
Yassinetaouil 46:b1a9de66ecab 11582 /* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
Yassinetaouil 46:b1a9de66ecab 11583 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11584 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11585 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11586 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11587 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11588
Yassinetaouil 46:b1a9de66ecab 11589 /* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
Yassinetaouil 46:b1a9de66ecab 11590 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11591 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11592 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11593 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11594 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11595
Yassinetaouil 46:b1a9de66ecab 11596 /* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
Yassinetaouil 46:b1a9de66ecab 11597 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11598 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11599 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11600 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11601 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11602
Yassinetaouil 46:b1a9de66ecab 11603 /* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
Yassinetaouil 46:b1a9de66ecab 11604 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11605 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11606 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11607 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11608 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11609
Yassinetaouil 46:b1a9de66ecab 11610 /* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
Yassinetaouil 46:b1a9de66ecab 11611 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11612 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11613 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11614 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11615 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11616
Yassinetaouil 46:b1a9de66ecab 11617 /* Bit 0 : Write '1' to Enable event routing for TICK event */
Yassinetaouil 46:b1a9de66ecab 11618 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11619 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11620 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11621 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11622 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11623
Yassinetaouil 46:b1a9de66ecab 11624 /* Register: RTC_EVTENCLR */
Yassinetaouil 46:b1a9de66ecab 11625 /* Description: Disable event routing */
Yassinetaouil 46:b1a9de66ecab 11626
Yassinetaouil 46:b1a9de66ecab 11627 /* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
Yassinetaouil 46:b1a9de66ecab 11628 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11629 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 11630 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11631 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11632 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11633
Yassinetaouil 46:b1a9de66ecab 11634 /* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
Yassinetaouil 46:b1a9de66ecab 11635 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11636 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 11637 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11638 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11639 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11640
Yassinetaouil 46:b1a9de66ecab 11641 /* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
Yassinetaouil 46:b1a9de66ecab 11642 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11643 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 11644 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11645 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11646 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11647
Yassinetaouil 46:b1a9de66ecab 11648 /* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
Yassinetaouil 46:b1a9de66ecab 11649 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11650 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 11651 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11652 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11653 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11654
Yassinetaouil 46:b1a9de66ecab 11655 /* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
Yassinetaouil 46:b1a9de66ecab 11656 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11657 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Yassinetaouil 46:b1a9de66ecab 11658 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11659 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11660 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11661
Yassinetaouil 46:b1a9de66ecab 11662 /* Bit 0 : Write '1' to Disable event routing for TICK event */
Yassinetaouil 46:b1a9de66ecab 11663 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11664 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
Yassinetaouil 46:b1a9de66ecab 11665 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11666 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11667 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11668
Yassinetaouil 46:b1a9de66ecab 11669 /* Register: RTC_COUNTER */
Yassinetaouil 46:b1a9de66ecab 11670 /* Description: Current COUNTER value */
Yassinetaouil 46:b1a9de66ecab 11671
Yassinetaouil 46:b1a9de66ecab 11672 /* Bits 23..0 : Counter value */
Yassinetaouil 46:b1a9de66ecab 11673 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
Yassinetaouil 46:b1a9de66ecab 11674 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
Yassinetaouil 46:b1a9de66ecab 11675
Yassinetaouil 46:b1a9de66ecab 11676 /* Register: RTC_PRESCALER */
Yassinetaouil 46:b1a9de66ecab 11677 /* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
Yassinetaouil 46:b1a9de66ecab 11678
Yassinetaouil 46:b1a9de66ecab 11679 /* Bits 11..0 : Prescaler value */
Yassinetaouil 46:b1a9de66ecab 11680 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
Yassinetaouil 46:b1a9de66ecab 11681 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
Yassinetaouil 46:b1a9de66ecab 11682
Yassinetaouil 46:b1a9de66ecab 11683 /* Register: RTC_CC */
Yassinetaouil 46:b1a9de66ecab 11684 /* Description: Description collection[0]: Compare register 0 */
Yassinetaouil 46:b1a9de66ecab 11685
Yassinetaouil 46:b1a9de66ecab 11686 /* Bits 23..0 : Compare value */
Yassinetaouil 46:b1a9de66ecab 11687 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
Yassinetaouil 46:b1a9de66ecab 11688 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
Yassinetaouil 46:b1a9de66ecab 11689
Yassinetaouil 46:b1a9de66ecab 11690
Yassinetaouil 46:b1a9de66ecab 11691 /* Peripheral: SAADC */
Yassinetaouil 46:b1a9de66ecab 11692 /* Description: Analog to Digital Converter */
Yassinetaouil 46:b1a9de66ecab 11693
Yassinetaouil 46:b1a9de66ecab 11694 /* Register: SAADC_INTEN */
Yassinetaouil 46:b1a9de66ecab 11695 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 11696
Yassinetaouil 46:b1a9de66ecab 11697 /* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11698 #define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11699 #define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11700 #define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11701 #define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11702
Yassinetaouil 46:b1a9de66ecab 11703 /* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11704 #define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11705 #define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11706 #define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11707 #define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11708
Yassinetaouil 46:b1a9de66ecab 11709 /* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11710 #define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11711 #define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11712 #define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11713 #define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11714
Yassinetaouil 46:b1a9de66ecab 11715 /* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11716 #define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11717 #define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11718 #define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11719 #define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11720
Yassinetaouil 46:b1a9de66ecab 11721 /* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11722 #define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11723 #define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11724 #define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11725 #define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11726
Yassinetaouil 46:b1a9de66ecab 11727 /* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11728 #define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11729 #define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11730 #define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11731 #define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11732
Yassinetaouil 46:b1a9de66ecab 11733 /* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11734 #define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11735 #define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11736 #define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11737 #define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11738
Yassinetaouil 46:b1a9de66ecab 11739 /* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11740 #define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11741 #define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11742 #define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11743 #define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11744
Yassinetaouil 46:b1a9de66ecab 11745 /* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11746 #define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11747 #define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11748 #define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11749 #define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11750
Yassinetaouil 46:b1a9de66ecab 11751 /* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11752 #define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11753 #define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11754 #define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11755 #define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11756
Yassinetaouil 46:b1a9de66ecab 11757 /* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11758 #define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11759 #define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11760 #define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11761 #define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11762
Yassinetaouil 46:b1a9de66ecab 11763 /* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11764 #define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11765 #define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11766 #define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11767 #define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11768
Yassinetaouil 46:b1a9de66ecab 11769 /* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11770 #define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11771 #define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11772 #define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11773 #define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11774
Yassinetaouil 46:b1a9de66ecab 11775 /* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11776 #define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11777 #define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11778 #define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11779 #define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11780
Yassinetaouil 46:b1a9de66ecab 11781 /* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11782 #define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11783 #define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11784 #define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11785 #define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11786
Yassinetaouil 46:b1a9de66ecab 11787 /* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11788 #define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11789 #define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11790 #define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11791 #define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11792
Yassinetaouil 46:b1a9de66ecab 11793 /* Bit 5 : Enable or disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 11794 #define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 11795 #define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 11796 #define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11797 #define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11798
Yassinetaouil 46:b1a9de66ecab 11799 /* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
Yassinetaouil 46:b1a9de66ecab 11800 #define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
Yassinetaouil 46:b1a9de66ecab 11801 #define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
Yassinetaouil 46:b1a9de66ecab 11802 #define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11803 #define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11804
Yassinetaouil 46:b1a9de66ecab 11805 /* Bit 3 : Enable or disable interrupt for RESULTDONE event */
Yassinetaouil 46:b1a9de66ecab 11806 #define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
Yassinetaouil 46:b1a9de66ecab 11807 #define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
Yassinetaouil 46:b1a9de66ecab 11808 #define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11809 #define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11810
Yassinetaouil 46:b1a9de66ecab 11811 /* Bit 2 : Enable or disable interrupt for DONE event */
Yassinetaouil 46:b1a9de66ecab 11812 #define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
Yassinetaouil 46:b1a9de66ecab 11813 #define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
Yassinetaouil 46:b1a9de66ecab 11814 #define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11815 #define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11816
Yassinetaouil 46:b1a9de66ecab 11817 /* Bit 1 : Enable or disable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 11818 #define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 11819 #define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 11820 #define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11821 #define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11822
Yassinetaouil 46:b1a9de66ecab 11823 /* Bit 0 : Enable or disable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 11824 #define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 11825 #define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 11826 #define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11827 #define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11828
Yassinetaouil 46:b1a9de66ecab 11829 /* Register: SAADC_INTENSET */
Yassinetaouil 46:b1a9de66ecab 11830 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 11831
Yassinetaouil 46:b1a9de66ecab 11832 /* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11833 #define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11834 #define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11835 #define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11836 #define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11837 #define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11838
Yassinetaouil 46:b1a9de66ecab 11839 /* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11840 #define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11841 #define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11842 #define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11843 #define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11844 #define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11845
Yassinetaouil 46:b1a9de66ecab 11846 /* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11847 #define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11848 #define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11849 #define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11850 #define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11851 #define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11852
Yassinetaouil 46:b1a9de66ecab 11853 /* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11854 #define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11855 #define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11856 #define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11857 #define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11858 #define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11859
Yassinetaouil 46:b1a9de66ecab 11860 /* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11861 #define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11862 #define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11863 #define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11864 #define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11865 #define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11866
Yassinetaouil 46:b1a9de66ecab 11867 /* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11868 #define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11869 #define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11870 #define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11871 #define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11872 #define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11873
Yassinetaouil 46:b1a9de66ecab 11874 /* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11875 #define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11876 #define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11877 #define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11878 #define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11879 #define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11880
Yassinetaouil 46:b1a9de66ecab 11881 /* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11882 #define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11883 #define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11884 #define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11885 #define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11886 #define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11887
Yassinetaouil 46:b1a9de66ecab 11888 /* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11889 #define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11890 #define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11891 #define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11892 #define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11893 #define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11894
Yassinetaouil 46:b1a9de66ecab 11895 /* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11896 #define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11897 #define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11898 #define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11899 #define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11900 #define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11901
Yassinetaouil 46:b1a9de66ecab 11902 /* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11903 #define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11904 #define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11905 #define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11906 #define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11907 #define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11908
Yassinetaouil 46:b1a9de66ecab 11909 /* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11910 #define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11911 #define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11912 #define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11913 #define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11914 #define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11915
Yassinetaouil 46:b1a9de66ecab 11916 /* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11917 #define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11918 #define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11919 #define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11920 #define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11921 #define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11922
Yassinetaouil 46:b1a9de66ecab 11923 /* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11924 #define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11925 #define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11926 #define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11927 #define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11928 #define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11929
Yassinetaouil 46:b1a9de66ecab 11930 /* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11931 #define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11932 #define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11933 #define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11934 #define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11935 #define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11936
Yassinetaouil 46:b1a9de66ecab 11937 /* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11938 #define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11939 #define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11940 #define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11941 #define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11942 #define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11943
Yassinetaouil 46:b1a9de66ecab 11944 /* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 11945 #define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 11946 #define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 11947 #define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11948 #define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11949 #define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11950
Yassinetaouil 46:b1a9de66ecab 11951 /* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
Yassinetaouil 46:b1a9de66ecab 11952 #define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
Yassinetaouil 46:b1a9de66ecab 11953 #define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
Yassinetaouil 46:b1a9de66ecab 11954 #define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11955 #define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11956 #define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11957
Yassinetaouil 46:b1a9de66ecab 11958 /* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
Yassinetaouil 46:b1a9de66ecab 11959 #define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
Yassinetaouil 46:b1a9de66ecab 11960 #define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
Yassinetaouil 46:b1a9de66ecab 11961 #define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11962 #define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11963 #define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11964
Yassinetaouil 46:b1a9de66ecab 11965 /* Bit 2 : Write '1' to Enable interrupt for DONE event */
Yassinetaouil 46:b1a9de66ecab 11966 #define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
Yassinetaouil 46:b1a9de66ecab 11967 #define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
Yassinetaouil 46:b1a9de66ecab 11968 #define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11969 #define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11970 #define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11971
Yassinetaouil 46:b1a9de66ecab 11972 /* Bit 1 : Write '1' to Enable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 11973 #define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 11974 #define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 11975 #define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11976 #define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11977 #define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11978
Yassinetaouil 46:b1a9de66ecab 11979 /* Bit 0 : Write '1' to Enable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 11980 #define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 11981 #define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 11982 #define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11983 #define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11984 #define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 11985
Yassinetaouil 46:b1a9de66ecab 11986 /* Register: SAADC_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 11987 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 11988
Yassinetaouil 46:b1a9de66ecab 11989 /* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 11990 #define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11991 #define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 11992 #define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 11993 #define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 11994 #define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 11995
Yassinetaouil 46:b1a9de66ecab 11996 /* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 11997 #define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11998 #define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 11999 #define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12000 #define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12001 #define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12002
Yassinetaouil 46:b1a9de66ecab 12003 /* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 12004 #define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12005 #define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12006 #define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12007 #define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12008 #define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12009
Yassinetaouil 46:b1a9de66ecab 12010 /* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 12011 #define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12012 #define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12013 #define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12014 #define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12015 #define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12016
Yassinetaouil 46:b1a9de66ecab 12017 /* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 12018 #define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12019 #define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12020 #define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12021 #define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12022 #define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12023
Yassinetaouil 46:b1a9de66ecab 12024 /* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 12025 #define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12026 #define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12027 #define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12028 #define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12029 #define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12030
Yassinetaouil 46:b1a9de66ecab 12031 /* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 12032 #define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12033 #define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12034 #define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12035 #define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12036 #define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12037
Yassinetaouil 46:b1a9de66ecab 12038 /* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 12039 #define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12040 #define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12041 #define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12042 #define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12043 #define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12044
Yassinetaouil 46:b1a9de66ecab 12045 /* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 12046 #define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12047 #define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12048 #define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12049 #define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12050 #define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12051
Yassinetaouil 46:b1a9de66ecab 12052 /* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 12053 #define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12054 #define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12055 #define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12056 #define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12057 #define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12058
Yassinetaouil 46:b1a9de66ecab 12059 /* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 12060 #define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12061 #define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12062 #define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12063 #define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12064 #define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12065
Yassinetaouil 46:b1a9de66ecab 12066 /* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 12067 #define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12068 #define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12069 #define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12070 #define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12071 #define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12072
Yassinetaouil 46:b1a9de66ecab 12073 /* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 12074 #define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12075 #define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12076 #define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12077 #define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12078 #define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12079
Yassinetaouil 46:b1a9de66ecab 12080 /* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 12081 #define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12082 #define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12083 #define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12084 #define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12085 #define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12086
Yassinetaouil 46:b1a9de66ecab 12087 /* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
Yassinetaouil 46:b1a9de66ecab 12088 #define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12089 #define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
Yassinetaouil 46:b1a9de66ecab 12090 #define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12091 #define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12092 #define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12093
Yassinetaouil 46:b1a9de66ecab 12094 /* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
Yassinetaouil 46:b1a9de66ecab 12095 #define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12096 #define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
Yassinetaouil 46:b1a9de66ecab 12097 #define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12098 #define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12099 #define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12100
Yassinetaouil 46:b1a9de66ecab 12101 /* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 12102 #define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 12103 #define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 12104 #define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12105 #define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12106 #define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12107
Yassinetaouil 46:b1a9de66ecab 12108 /* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
Yassinetaouil 46:b1a9de66ecab 12109 #define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
Yassinetaouil 46:b1a9de66ecab 12110 #define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
Yassinetaouil 46:b1a9de66ecab 12111 #define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12112 #define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12113 #define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12114
Yassinetaouil 46:b1a9de66ecab 12115 /* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
Yassinetaouil 46:b1a9de66ecab 12116 #define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
Yassinetaouil 46:b1a9de66ecab 12117 #define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
Yassinetaouil 46:b1a9de66ecab 12118 #define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12119 #define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12120 #define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12121
Yassinetaouil 46:b1a9de66ecab 12122 /* Bit 2 : Write '1' to Disable interrupt for DONE event */
Yassinetaouil 46:b1a9de66ecab 12123 #define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
Yassinetaouil 46:b1a9de66ecab 12124 #define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
Yassinetaouil 46:b1a9de66ecab 12125 #define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12126 #define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12127 #define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12128
Yassinetaouil 46:b1a9de66ecab 12129 /* Bit 1 : Write '1' to Disable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 12130 #define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 12131 #define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 12132 #define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12133 #define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12134 #define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12135
Yassinetaouil 46:b1a9de66ecab 12136 /* Bit 0 : Write '1' to Disable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 12137 #define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 12138 #define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 12139 #define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12140 #define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12141 #define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12142
Yassinetaouil 46:b1a9de66ecab 12143 /* Register: SAADC_STATUS */
Yassinetaouil 46:b1a9de66ecab 12144 /* Description: Status */
Yassinetaouil 46:b1a9de66ecab 12145
Yassinetaouil 46:b1a9de66ecab 12146 /* Bit 0 : Status */
Yassinetaouil 46:b1a9de66ecab 12147 #define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
Yassinetaouil 46:b1a9de66ecab 12148 #define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
Yassinetaouil 46:b1a9de66ecab 12149 #define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
Yassinetaouil 46:b1a9de66ecab 12150 #define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
Yassinetaouil 46:b1a9de66ecab 12151
Yassinetaouil 46:b1a9de66ecab 12152 /* Register: SAADC_ENABLE */
Yassinetaouil 46:b1a9de66ecab 12153 /* Description: Enable or disable ADC */
Yassinetaouil 46:b1a9de66ecab 12154
Yassinetaouil 46:b1a9de66ecab 12155 /* Bit 0 : Enable or disable ADC */
Yassinetaouil 46:b1a9de66ecab 12156 #define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 12157 #define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 12158 #define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
Yassinetaouil 46:b1a9de66ecab 12159 #define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
Yassinetaouil 46:b1a9de66ecab 12160
Yassinetaouil 46:b1a9de66ecab 12161 /* Register: SAADC_CH_PSELP */
Yassinetaouil 46:b1a9de66ecab 12162 /* Description: Description cluster[0]: Input positive pin selection for CH[0] */
Yassinetaouil 46:b1a9de66ecab 12163
Yassinetaouil 46:b1a9de66ecab 12164 /* Bits 4..0 : Analog positive input channel */
Yassinetaouil 46:b1a9de66ecab 12165 #define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
Yassinetaouil 46:b1a9de66ecab 12166 #define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
Yassinetaouil 46:b1a9de66ecab 12167 #define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
Yassinetaouil 46:b1a9de66ecab 12168 #define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
Yassinetaouil 46:b1a9de66ecab 12169 #define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
Yassinetaouil 46:b1a9de66ecab 12170 #define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
Yassinetaouil 46:b1a9de66ecab 12171 #define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
Yassinetaouil 46:b1a9de66ecab 12172 #define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
Yassinetaouil 46:b1a9de66ecab 12173 #define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
Yassinetaouil 46:b1a9de66ecab 12174 #define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
Yassinetaouil 46:b1a9de66ecab 12175 #define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
Yassinetaouil 46:b1a9de66ecab 12176 #define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
Yassinetaouil 46:b1a9de66ecab 12177
Yassinetaouil 46:b1a9de66ecab 12178 /* Register: SAADC_CH_PSELN */
Yassinetaouil 46:b1a9de66ecab 12179 /* Description: Description cluster[0]: Input negative pin selection for CH[0] */
Yassinetaouil 46:b1a9de66ecab 12180
Yassinetaouil 46:b1a9de66ecab 12181 /* Bits 4..0 : Analog negative input, enables differential channel */
Yassinetaouil 46:b1a9de66ecab 12182 #define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
Yassinetaouil 46:b1a9de66ecab 12183 #define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
Yassinetaouil 46:b1a9de66ecab 12184 #define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
Yassinetaouil 46:b1a9de66ecab 12185 #define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
Yassinetaouil 46:b1a9de66ecab 12186 #define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
Yassinetaouil 46:b1a9de66ecab 12187 #define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
Yassinetaouil 46:b1a9de66ecab 12188 #define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
Yassinetaouil 46:b1a9de66ecab 12189 #define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
Yassinetaouil 46:b1a9de66ecab 12190 #define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
Yassinetaouil 46:b1a9de66ecab 12191 #define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
Yassinetaouil 46:b1a9de66ecab 12192 #define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
Yassinetaouil 46:b1a9de66ecab 12193 #define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
Yassinetaouil 46:b1a9de66ecab 12194
Yassinetaouil 46:b1a9de66ecab 12195 /* Register: SAADC_CH_CONFIG */
Yassinetaouil 46:b1a9de66ecab 12196 /* Description: Description cluster[0]: Input configuration for CH[0] */
Yassinetaouil 46:b1a9de66ecab 12197
Yassinetaouil 46:b1a9de66ecab 12198 /* Bit 24 : Enable burst mode */
Yassinetaouil 46:b1a9de66ecab 12199 #define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
Yassinetaouil 46:b1a9de66ecab 12200 #define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
Yassinetaouil 46:b1a9de66ecab 12201 #define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
Yassinetaouil 46:b1a9de66ecab 12202 #define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
Yassinetaouil 46:b1a9de66ecab 12203
Yassinetaouil 46:b1a9de66ecab 12204 /* Bit 20 : Enable differential mode */
Yassinetaouil 46:b1a9de66ecab 12205 #define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
Yassinetaouil 46:b1a9de66ecab 12206 #define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
Yassinetaouil 46:b1a9de66ecab 12207 #define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
Yassinetaouil 46:b1a9de66ecab 12208 #define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
Yassinetaouil 46:b1a9de66ecab 12209
Yassinetaouil 46:b1a9de66ecab 12210 /* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
Yassinetaouil 46:b1a9de66ecab 12211 #define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
Yassinetaouil 46:b1a9de66ecab 12212 #define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
Yassinetaouil 46:b1a9de66ecab 12213 #define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
Yassinetaouil 46:b1a9de66ecab 12214 #define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
Yassinetaouil 46:b1a9de66ecab 12215 #define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
Yassinetaouil 46:b1a9de66ecab 12216 #define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
Yassinetaouil 46:b1a9de66ecab 12217 #define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
Yassinetaouil 46:b1a9de66ecab 12218 #define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
Yassinetaouil 46:b1a9de66ecab 12219
Yassinetaouil 46:b1a9de66ecab 12220 /* Bit 12 : Reference control */
Yassinetaouil 46:b1a9de66ecab 12221 #define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
Yassinetaouil 46:b1a9de66ecab 12222 #define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
Yassinetaouil 46:b1a9de66ecab 12223 #define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
Yassinetaouil 46:b1a9de66ecab 12224 #define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
Yassinetaouil 46:b1a9de66ecab 12225
Yassinetaouil 46:b1a9de66ecab 12226 /* Bits 10..8 : Gain control */
Yassinetaouil 46:b1a9de66ecab 12227 #define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
Yassinetaouil 46:b1a9de66ecab 12228 #define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
Yassinetaouil 46:b1a9de66ecab 12229 #define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
Yassinetaouil 46:b1a9de66ecab 12230 #define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
Yassinetaouil 46:b1a9de66ecab 12231 #define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
Yassinetaouil 46:b1a9de66ecab 12232 #define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
Yassinetaouil 46:b1a9de66ecab 12233 #define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
Yassinetaouil 46:b1a9de66ecab 12234 #define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
Yassinetaouil 46:b1a9de66ecab 12235 #define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
Yassinetaouil 46:b1a9de66ecab 12236 #define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
Yassinetaouil 46:b1a9de66ecab 12237
Yassinetaouil 46:b1a9de66ecab 12238 /* Bits 5..4 : Negative channel resistor control */
Yassinetaouil 46:b1a9de66ecab 12239 #define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
Yassinetaouil 46:b1a9de66ecab 12240 #define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
Yassinetaouil 46:b1a9de66ecab 12241 #define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
Yassinetaouil 46:b1a9de66ecab 12242 #define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
Yassinetaouil 46:b1a9de66ecab 12243 #define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
Yassinetaouil 46:b1a9de66ecab 12244 #define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
Yassinetaouil 46:b1a9de66ecab 12245
Yassinetaouil 46:b1a9de66ecab 12246 /* Bits 1..0 : Positive channel resistor control */
Yassinetaouil 46:b1a9de66ecab 12247 #define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
Yassinetaouil 46:b1a9de66ecab 12248 #define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
Yassinetaouil 46:b1a9de66ecab 12249 #define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
Yassinetaouil 46:b1a9de66ecab 12250 #define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
Yassinetaouil 46:b1a9de66ecab 12251 #define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
Yassinetaouil 46:b1a9de66ecab 12252 #define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
Yassinetaouil 46:b1a9de66ecab 12253
Yassinetaouil 46:b1a9de66ecab 12254 /* Register: SAADC_CH_LIMIT */
Yassinetaouil 46:b1a9de66ecab 12255 /* Description: Description cluster[0]: High/low limits for event monitoring a channel */
Yassinetaouil 46:b1a9de66ecab 12256
Yassinetaouil 46:b1a9de66ecab 12257 /* Bits 31..16 : High level limit */
Yassinetaouil 46:b1a9de66ecab 12258 #define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
Yassinetaouil 46:b1a9de66ecab 12259 #define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
Yassinetaouil 46:b1a9de66ecab 12260
Yassinetaouil 46:b1a9de66ecab 12261 /* Bits 15..0 : Low level limit */
Yassinetaouil 46:b1a9de66ecab 12262 #define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
Yassinetaouil 46:b1a9de66ecab 12263 #define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
Yassinetaouil 46:b1a9de66ecab 12264
Yassinetaouil 46:b1a9de66ecab 12265 /* Register: SAADC_RESOLUTION */
Yassinetaouil 46:b1a9de66ecab 12266 /* Description: Resolution configuration */
Yassinetaouil 46:b1a9de66ecab 12267
Yassinetaouil 46:b1a9de66ecab 12268 /* Bits 2..0 : Set the resolution */
Yassinetaouil 46:b1a9de66ecab 12269 #define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
Yassinetaouil 46:b1a9de66ecab 12270 #define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
Yassinetaouil 46:b1a9de66ecab 12271 #define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
Yassinetaouil 46:b1a9de66ecab 12272 #define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
Yassinetaouil 46:b1a9de66ecab 12273 #define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
Yassinetaouil 46:b1a9de66ecab 12274 #define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
Yassinetaouil 46:b1a9de66ecab 12275
Yassinetaouil 46:b1a9de66ecab 12276 /* Register: SAADC_OVERSAMPLE */
Yassinetaouil 46:b1a9de66ecab 12277 /* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
Yassinetaouil 46:b1a9de66ecab 12278
Yassinetaouil 46:b1a9de66ecab 12279 /* Bits 3..0 : Oversample control */
Yassinetaouil 46:b1a9de66ecab 12280 #define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 12281 #define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
Yassinetaouil 46:b1a9de66ecab 12282 #define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
Yassinetaouil 46:b1a9de66ecab 12283 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
Yassinetaouil 46:b1a9de66ecab 12284 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
Yassinetaouil 46:b1a9de66ecab 12285 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
Yassinetaouil 46:b1a9de66ecab 12286 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
Yassinetaouil 46:b1a9de66ecab 12287 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
Yassinetaouil 46:b1a9de66ecab 12288 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
Yassinetaouil 46:b1a9de66ecab 12289 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
Yassinetaouil 46:b1a9de66ecab 12290 #define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
Yassinetaouil 46:b1a9de66ecab 12291
Yassinetaouil 46:b1a9de66ecab 12292 /* Register: SAADC_SAMPLERATE */
Yassinetaouil 46:b1a9de66ecab 12293 /* Description: Controls normal or continuous sample rate */
Yassinetaouil 46:b1a9de66ecab 12294
Yassinetaouil 46:b1a9de66ecab 12295 /* Bit 12 : Select mode for sample rate control */
Yassinetaouil 46:b1a9de66ecab 12296 #define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
Yassinetaouil 46:b1a9de66ecab 12297 #define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
Yassinetaouil 46:b1a9de66ecab 12298 #define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
Yassinetaouil 46:b1a9de66ecab 12299 #define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
Yassinetaouil 46:b1a9de66ecab 12300
Yassinetaouil 46:b1a9de66ecab 12301 /* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
Yassinetaouil 46:b1a9de66ecab 12302 #define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
Yassinetaouil 46:b1a9de66ecab 12303 #define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
Yassinetaouil 46:b1a9de66ecab 12304
Yassinetaouil 46:b1a9de66ecab 12305 /* Register: SAADC_RESULT_PTR */
Yassinetaouil 46:b1a9de66ecab 12306 /* Description: Data pointer */
Yassinetaouil 46:b1a9de66ecab 12307
Yassinetaouil 46:b1a9de66ecab 12308 /* Bits 31..0 : Data pointer */
Yassinetaouil 46:b1a9de66ecab 12309 #define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12310 #define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12311
Yassinetaouil 46:b1a9de66ecab 12312 /* Register: SAADC_RESULT_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 12313 /* Description: Maximum number of buffer words to transfer */
Yassinetaouil 46:b1a9de66ecab 12314
Yassinetaouil 46:b1a9de66ecab 12315 /* Bits 14..0 : Maximum number of buffer words to transfer */
Yassinetaouil 46:b1a9de66ecab 12316 #define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12317 #define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12318
Yassinetaouil 46:b1a9de66ecab 12319 /* Register: SAADC_RESULT_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 12320 /* Description: Number of buffer words transferred since last START */
Yassinetaouil 46:b1a9de66ecab 12321
Yassinetaouil 46:b1a9de66ecab 12322 /* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
Yassinetaouil 46:b1a9de66ecab 12323 #define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12324 #define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12325
Yassinetaouil 46:b1a9de66ecab 12326
Yassinetaouil 46:b1a9de66ecab 12327 /* Peripheral: SPI */
Yassinetaouil 46:b1a9de66ecab 12328 /* Description: Serial Peripheral Interface 0 */
Yassinetaouil 46:b1a9de66ecab 12329
Yassinetaouil 46:b1a9de66ecab 12330 /* Register: SPI_INTENSET */
Yassinetaouil 46:b1a9de66ecab 12331 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 12332
Yassinetaouil 46:b1a9de66ecab 12333 /* Bit 2 : Write '1' to Enable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 12334 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 12335 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 12336 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12337 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12338 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12339
Yassinetaouil 46:b1a9de66ecab 12340 /* Register: SPI_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 12341 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 12342
Yassinetaouil 46:b1a9de66ecab 12343 /* Bit 2 : Write '1' to Disable interrupt for READY event */
Yassinetaouil 46:b1a9de66ecab 12344 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
Yassinetaouil 46:b1a9de66ecab 12345 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Yassinetaouil 46:b1a9de66ecab 12346 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12347 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12348 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12349
Yassinetaouil 46:b1a9de66ecab 12350 /* Register: SPI_ENABLE */
Yassinetaouil 46:b1a9de66ecab 12351 /* Description: Enable SPI */
Yassinetaouil 46:b1a9de66ecab 12352
Yassinetaouil 46:b1a9de66ecab 12353 /* Bits 3..0 : Enable or disable SPI */
Yassinetaouil 46:b1a9de66ecab 12354 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 12355 #define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 12356 #define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
Yassinetaouil 46:b1a9de66ecab 12357 #define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
Yassinetaouil 46:b1a9de66ecab 12358
Yassinetaouil 46:b1a9de66ecab 12359 /* Register: SPI_PSEL_SCK */
Yassinetaouil 46:b1a9de66ecab 12360 /* Description: Pin select for SCK */
Yassinetaouil 46:b1a9de66ecab 12361
Yassinetaouil 46:b1a9de66ecab 12362 /* Bits 31..0 : Pin number configuration for SPI SCK signal */
Yassinetaouil 46:b1a9de66ecab 12363 #define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
Yassinetaouil 46:b1a9de66ecab 12364 #define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
Yassinetaouil 46:b1a9de66ecab 12365 #define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12366
Yassinetaouil 46:b1a9de66ecab 12367 /* Register: SPI_PSEL_MOSI */
Yassinetaouil 46:b1a9de66ecab 12368 /* Description: Pin select for MOSI */
Yassinetaouil 46:b1a9de66ecab 12369
Yassinetaouil 46:b1a9de66ecab 12370 /* Bits 31..0 : Pin number configuration for SPI MOSI signal */
Yassinetaouil 46:b1a9de66ecab 12371 #define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
Yassinetaouil 46:b1a9de66ecab 12372 #define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
Yassinetaouil 46:b1a9de66ecab 12373 #define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12374
Yassinetaouil 46:b1a9de66ecab 12375 /* Register: SPI_PSEL_MISO */
Yassinetaouil 46:b1a9de66ecab 12376 /* Description: Pin select for MISO */
Yassinetaouil 46:b1a9de66ecab 12377
Yassinetaouil 46:b1a9de66ecab 12378 /* Bits 31..0 : Pin number configuration for SPI MISO signal */
Yassinetaouil 46:b1a9de66ecab 12379 #define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
Yassinetaouil 46:b1a9de66ecab 12380 #define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
Yassinetaouil 46:b1a9de66ecab 12381 #define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12382
Yassinetaouil 46:b1a9de66ecab 12383 /* Register: SPI_RXD */
Yassinetaouil 46:b1a9de66ecab 12384 /* Description: RXD register */
Yassinetaouil 46:b1a9de66ecab 12385
Yassinetaouil 46:b1a9de66ecab 12386 /* Bits 7..0 : RX data received. Double buffered */
Yassinetaouil 46:b1a9de66ecab 12387 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Yassinetaouil 46:b1a9de66ecab 12388 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Yassinetaouil 46:b1a9de66ecab 12389
Yassinetaouil 46:b1a9de66ecab 12390 /* Register: SPI_TXD */
Yassinetaouil 46:b1a9de66ecab 12391 /* Description: TXD register */
Yassinetaouil 46:b1a9de66ecab 12392
Yassinetaouil 46:b1a9de66ecab 12393 /* Bits 7..0 : TX data to send. Double buffered */
Yassinetaouil 46:b1a9de66ecab 12394 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Yassinetaouil 46:b1a9de66ecab 12395 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Yassinetaouil 46:b1a9de66ecab 12396
Yassinetaouil 46:b1a9de66ecab 12397 /* Register: SPI_FREQUENCY */
Yassinetaouil 46:b1a9de66ecab 12398 /* Description: SPI frequency */
Yassinetaouil 46:b1a9de66ecab 12399
Yassinetaouil 46:b1a9de66ecab 12400 /* Bits 31..0 : SPI master data rate */
Yassinetaouil 46:b1a9de66ecab 12401 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 12402 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 12403 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
Yassinetaouil 46:b1a9de66ecab 12404 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
Yassinetaouil 46:b1a9de66ecab 12405 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
Yassinetaouil 46:b1a9de66ecab 12406 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
Yassinetaouil 46:b1a9de66ecab 12407 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
Yassinetaouil 46:b1a9de66ecab 12408 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
Yassinetaouil 46:b1a9de66ecab 12409 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
Yassinetaouil 46:b1a9de66ecab 12410
Yassinetaouil 46:b1a9de66ecab 12411 /* Register: SPI_CONFIG */
Yassinetaouil 46:b1a9de66ecab 12412 /* Description: Configuration register */
Yassinetaouil 46:b1a9de66ecab 12413
Yassinetaouil 46:b1a9de66ecab 12414 /* Bit 2 : Serial clock (SCK) polarity */
Yassinetaouil 46:b1a9de66ecab 12415 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
Yassinetaouil 46:b1a9de66ecab 12416 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
Yassinetaouil 46:b1a9de66ecab 12417 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
Yassinetaouil 46:b1a9de66ecab 12418 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
Yassinetaouil 46:b1a9de66ecab 12419
Yassinetaouil 46:b1a9de66ecab 12420 /* Bit 1 : Serial clock (SCK) phase */
Yassinetaouil 46:b1a9de66ecab 12421 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
Yassinetaouil 46:b1a9de66ecab 12422 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
Yassinetaouil 46:b1a9de66ecab 12423 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
Yassinetaouil 46:b1a9de66ecab 12424 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
Yassinetaouil 46:b1a9de66ecab 12425
Yassinetaouil 46:b1a9de66ecab 12426 /* Bit 0 : Bit order */
Yassinetaouil 46:b1a9de66ecab 12427 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
Yassinetaouil 46:b1a9de66ecab 12428 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
Yassinetaouil 46:b1a9de66ecab 12429 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
Yassinetaouil 46:b1a9de66ecab 12430 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
Yassinetaouil 46:b1a9de66ecab 12431
Yassinetaouil 46:b1a9de66ecab 12432
Yassinetaouil 46:b1a9de66ecab 12433 /* Peripheral: SPIM */
Yassinetaouil 46:b1a9de66ecab 12434 /* Description: Serial Peripheral Interface Master with EasyDMA 0 */
Yassinetaouil 46:b1a9de66ecab 12435
Yassinetaouil 46:b1a9de66ecab 12436 /* Register: SPIM_SHORTS */
Yassinetaouil 46:b1a9de66ecab 12437 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 12438
Yassinetaouil 46:b1a9de66ecab 12439 /* Bit 17 : Shortcut between END event and START task */
Yassinetaouil 46:b1a9de66ecab 12440 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
Yassinetaouil 46:b1a9de66ecab 12441 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
Yassinetaouil 46:b1a9de66ecab 12442 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 12443 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 12444
Yassinetaouil 46:b1a9de66ecab 12445 /* Register: SPIM_INTENSET */
Yassinetaouil 46:b1a9de66ecab 12446 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 12447
Yassinetaouil 46:b1a9de66ecab 12448 /* Bit 19 : Write '1' to Enable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 12449 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 12450 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 12451 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12452 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12453 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12454
Yassinetaouil 46:b1a9de66ecab 12455 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
Yassinetaouil 46:b1a9de66ecab 12456 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 12457 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 12458 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12459 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12460 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12461
Yassinetaouil 46:b1a9de66ecab 12462 /* Bit 6 : Write '1' to Enable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 12463 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 12464 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 12465 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12466 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12467 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12468
Yassinetaouil 46:b1a9de66ecab 12469 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 12470 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 12471 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 12472 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12473 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12474 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12475
Yassinetaouil 46:b1a9de66ecab 12476 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 12477 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 12478 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 12479 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12480 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12481 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12482
Yassinetaouil 46:b1a9de66ecab 12483 /* Register: SPIM_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 12484 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 12485
Yassinetaouil 46:b1a9de66ecab 12486 /* Bit 19 : Write '1' to Disable interrupt for STARTED event */
Yassinetaouil 46:b1a9de66ecab 12487 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 12488 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
Yassinetaouil 46:b1a9de66ecab 12489 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12490 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12491 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12492
Yassinetaouil 46:b1a9de66ecab 12493 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
Yassinetaouil 46:b1a9de66ecab 12494 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 12495 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 12496 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12497 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12498 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12499
Yassinetaouil 46:b1a9de66ecab 12500 /* Bit 6 : Write '1' to Disable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 12501 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 12502 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 12503 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12504 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12505 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12506
Yassinetaouil 46:b1a9de66ecab 12507 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 12508 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 12509 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 12510 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12511 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12512 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12513
Yassinetaouil 46:b1a9de66ecab 12514 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 12515 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 12516 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 12517 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12518 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12519 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12520
Yassinetaouil 46:b1a9de66ecab 12521 /* Register: SPIM_ENABLE */
Yassinetaouil 46:b1a9de66ecab 12522 /* Description: Enable SPIM */
Yassinetaouil 46:b1a9de66ecab 12523
Yassinetaouil 46:b1a9de66ecab 12524 /* Bits 3..0 : Enable or disable SPIM */
Yassinetaouil 46:b1a9de66ecab 12525 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 12526 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 12527 #define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
Yassinetaouil 46:b1a9de66ecab 12528 #define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
Yassinetaouil 46:b1a9de66ecab 12529
Yassinetaouil 46:b1a9de66ecab 12530 /* Register: SPIM_PSEL_SCK */
Yassinetaouil 46:b1a9de66ecab 12531 /* Description: Pin select for SCK */
Yassinetaouil 46:b1a9de66ecab 12532
Yassinetaouil 46:b1a9de66ecab 12533 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 12534 #define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12535 #define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12536 #define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 12537 #define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12538
Yassinetaouil 46:b1a9de66ecab 12539 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 12540 #define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12541 #define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12542
Yassinetaouil 46:b1a9de66ecab 12543 /* Register: SPIM_PSEL_MOSI */
Yassinetaouil 46:b1a9de66ecab 12544 /* Description: Pin select for MOSI signal */
Yassinetaouil 46:b1a9de66ecab 12545
Yassinetaouil 46:b1a9de66ecab 12546 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 12547 #define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12548 #define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12549 #define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 12550 #define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12551
Yassinetaouil 46:b1a9de66ecab 12552 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 12553 #define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12554 #define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12555
Yassinetaouil 46:b1a9de66ecab 12556 /* Register: SPIM_PSEL_MISO */
Yassinetaouil 46:b1a9de66ecab 12557 /* Description: Pin select for MISO signal */
Yassinetaouil 46:b1a9de66ecab 12558
Yassinetaouil 46:b1a9de66ecab 12559 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 12560 #define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12561 #define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12562 #define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 12563 #define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12564
Yassinetaouil 46:b1a9de66ecab 12565 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 12566 #define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12567 #define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12568
Yassinetaouil 46:b1a9de66ecab 12569 /* Register: SPIM_FREQUENCY */
Yassinetaouil 46:b1a9de66ecab 12570 /* Description: SPI frequency */
Yassinetaouil 46:b1a9de66ecab 12571
Yassinetaouil 46:b1a9de66ecab 12572 /* Bits 31..0 : SPI master data rate */
Yassinetaouil 46:b1a9de66ecab 12573 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 12574 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 12575 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
Yassinetaouil 46:b1a9de66ecab 12576 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
Yassinetaouil 46:b1a9de66ecab 12577 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
Yassinetaouil 46:b1a9de66ecab 12578 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
Yassinetaouil 46:b1a9de66ecab 12579 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
Yassinetaouil 46:b1a9de66ecab 12580 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
Yassinetaouil 46:b1a9de66ecab 12581 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
Yassinetaouil 46:b1a9de66ecab 12582
Yassinetaouil 46:b1a9de66ecab 12583 /* Register: SPIM_RXD_PTR */
Yassinetaouil 46:b1a9de66ecab 12584 /* Description: Data pointer */
Yassinetaouil 46:b1a9de66ecab 12585
Yassinetaouil 46:b1a9de66ecab 12586 /* Bits 31..0 : Data pointer */
Yassinetaouil 46:b1a9de66ecab 12587 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12588 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12589
Yassinetaouil 46:b1a9de66ecab 12590 /* Register: SPIM_RXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 12591 /* Description: Maximum number of bytes in receive buffer */
Yassinetaouil 46:b1a9de66ecab 12592
Yassinetaouil 46:b1a9de66ecab 12593 /* Bits 7..0 : Maximum number of bytes in receive buffer */
Yassinetaouil 46:b1a9de66ecab 12594 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12595 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12596
Yassinetaouil 46:b1a9de66ecab 12597 /* Register: SPIM_RXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 12598 /* Description: Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 12599
Yassinetaouil 46:b1a9de66ecab 12600 /* Bits 7..0 : Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 12601 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12602 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12603
Yassinetaouil 46:b1a9de66ecab 12604 /* Register: SPIM_RXD_LIST */
Yassinetaouil 46:b1a9de66ecab 12605 /* Description: EasyDMA list type */
Yassinetaouil 46:b1a9de66ecab 12606
Yassinetaouil 46:b1a9de66ecab 12607 /* Bits 2..0 : List type */
Yassinetaouil 46:b1a9de66ecab 12608 #define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
Yassinetaouil 46:b1a9de66ecab 12609 #define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
Yassinetaouil 46:b1a9de66ecab 12610 #define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
Yassinetaouil 46:b1a9de66ecab 12611 #define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
Yassinetaouil 46:b1a9de66ecab 12612
Yassinetaouil 46:b1a9de66ecab 12613 /* Register: SPIM_TXD_PTR */
Yassinetaouil 46:b1a9de66ecab 12614 /* Description: Data pointer */
Yassinetaouil 46:b1a9de66ecab 12615
Yassinetaouil 46:b1a9de66ecab 12616 /* Bits 31..0 : Data pointer */
Yassinetaouil 46:b1a9de66ecab 12617 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12618 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12619
Yassinetaouil 46:b1a9de66ecab 12620 /* Register: SPIM_TXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 12621 /* Description: Maximum number of bytes in transmit buffer */
Yassinetaouil 46:b1a9de66ecab 12622
Yassinetaouil 46:b1a9de66ecab 12623 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
Yassinetaouil 46:b1a9de66ecab 12624 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12625 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12626
Yassinetaouil 46:b1a9de66ecab 12627 /* Register: SPIM_TXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 12628 /* Description: Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 12629
Yassinetaouil 46:b1a9de66ecab 12630 /* Bits 7..0 : Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 12631 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12632 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12633
Yassinetaouil 46:b1a9de66ecab 12634 /* Register: SPIM_TXD_LIST */
Yassinetaouil 46:b1a9de66ecab 12635 /* Description: EasyDMA list type */
Yassinetaouil 46:b1a9de66ecab 12636
Yassinetaouil 46:b1a9de66ecab 12637 /* Bits 2..0 : List type */
Yassinetaouil 46:b1a9de66ecab 12638 #define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
Yassinetaouil 46:b1a9de66ecab 12639 #define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
Yassinetaouil 46:b1a9de66ecab 12640 #define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
Yassinetaouil 46:b1a9de66ecab 12641 #define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
Yassinetaouil 46:b1a9de66ecab 12642
Yassinetaouil 46:b1a9de66ecab 12643 /* Register: SPIM_CONFIG */
Yassinetaouil 46:b1a9de66ecab 12644 /* Description: Configuration register */
Yassinetaouil 46:b1a9de66ecab 12645
Yassinetaouil 46:b1a9de66ecab 12646 /* Bit 2 : Serial clock (SCK) polarity */
Yassinetaouil 46:b1a9de66ecab 12647 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
Yassinetaouil 46:b1a9de66ecab 12648 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
Yassinetaouil 46:b1a9de66ecab 12649 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
Yassinetaouil 46:b1a9de66ecab 12650 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
Yassinetaouil 46:b1a9de66ecab 12651
Yassinetaouil 46:b1a9de66ecab 12652 /* Bit 1 : Serial clock (SCK) phase */
Yassinetaouil 46:b1a9de66ecab 12653 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
Yassinetaouil 46:b1a9de66ecab 12654 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
Yassinetaouil 46:b1a9de66ecab 12655 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
Yassinetaouil 46:b1a9de66ecab 12656 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
Yassinetaouil 46:b1a9de66ecab 12657
Yassinetaouil 46:b1a9de66ecab 12658 /* Bit 0 : Bit order */
Yassinetaouil 46:b1a9de66ecab 12659 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
Yassinetaouil 46:b1a9de66ecab 12660 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
Yassinetaouil 46:b1a9de66ecab 12661 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
Yassinetaouil 46:b1a9de66ecab 12662 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
Yassinetaouil 46:b1a9de66ecab 12663
Yassinetaouil 46:b1a9de66ecab 12664 /* Register: SPIM_ORC */
Yassinetaouil 46:b1a9de66ecab 12665 /* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
Yassinetaouil 46:b1a9de66ecab 12666
Yassinetaouil 46:b1a9de66ecab 12667 /* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
Yassinetaouil 46:b1a9de66ecab 12668 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
Yassinetaouil 46:b1a9de66ecab 12669 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
Yassinetaouil 46:b1a9de66ecab 12670
Yassinetaouil 46:b1a9de66ecab 12671
Yassinetaouil 46:b1a9de66ecab 12672 /* Peripheral: SPIS */
Yassinetaouil 46:b1a9de66ecab 12673 /* Description: SPI Slave 0 */
Yassinetaouil 46:b1a9de66ecab 12674
Yassinetaouil 46:b1a9de66ecab 12675 /* Register: SPIS_SHORTS */
Yassinetaouil 46:b1a9de66ecab 12676 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 12677
Yassinetaouil 46:b1a9de66ecab 12678 /* Bit 2 : Shortcut between END event and ACQUIRE task */
Yassinetaouil 46:b1a9de66ecab 12679 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
Yassinetaouil 46:b1a9de66ecab 12680 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
Yassinetaouil 46:b1a9de66ecab 12681 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 12682 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 12683
Yassinetaouil 46:b1a9de66ecab 12684 /* Register: SPIS_INTENSET */
Yassinetaouil 46:b1a9de66ecab 12685 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 12686
Yassinetaouil 46:b1a9de66ecab 12687 /* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
Yassinetaouil 46:b1a9de66ecab 12688 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
Yassinetaouil 46:b1a9de66ecab 12689 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
Yassinetaouil 46:b1a9de66ecab 12690 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12691 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12692 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12693
Yassinetaouil 46:b1a9de66ecab 12694 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 12695 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 12696 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 12697 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12698 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12699 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12700
Yassinetaouil 46:b1a9de66ecab 12701 /* Bit 1 : Write '1' to Enable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 12702 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 12703 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 12704 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12705 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12706 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12707
Yassinetaouil 46:b1a9de66ecab 12708 /* Register: SPIS_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 12709 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 12710
Yassinetaouil 46:b1a9de66ecab 12711 /* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
Yassinetaouil 46:b1a9de66ecab 12712 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
Yassinetaouil 46:b1a9de66ecab 12713 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
Yassinetaouil 46:b1a9de66ecab 12714 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12715 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12716 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12717
Yassinetaouil 46:b1a9de66ecab 12718 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 12719 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 12720 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 12721 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12722 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12723 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12724
Yassinetaouil 46:b1a9de66ecab 12725 /* Bit 1 : Write '1' to Disable interrupt for END event */
Yassinetaouil 46:b1a9de66ecab 12726 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
Yassinetaouil 46:b1a9de66ecab 12727 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Yassinetaouil 46:b1a9de66ecab 12728 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12729 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12730 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12731
Yassinetaouil 46:b1a9de66ecab 12732 /* Register: SPIS_SEMSTAT */
Yassinetaouil 46:b1a9de66ecab 12733 /* Description: Semaphore status register */
Yassinetaouil 46:b1a9de66ecab 12734
Yassinetaouil 46:b1a9de66ecab 12735 /* Bits 1..0 : Semaphore status */
Yassinetaouil 46:b1a9de66ecab 12736 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
Yassinetaouil 46:b1a9de66ecab 12737 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
Yassinetaouil 46:b1a9de66ecab 12738 #define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
Yassinetaouil 46:b1a9de66ecab 12739 #define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
Yassinetaouil 46:b1a9de66ecab 12740 #define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
Yassinetaouil 46:b1a9de66ecab 12741 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
Yassinetaouil 46:b1a9de66ecab 12742
Yassinetaouil 46:b1a9de66ecab 12743 /* Register: SPIS_STATUS */
Yassinetaouil 46:b1a9de66ecab 12744 /* Description: Status from last transaction */
Yassinetaouil 46:b1a9de66ecab 12745
Yassinetaouil 46:b1a9de66ecab 12746 /* Bit 1 : RX buffer overflow detected, and prevented */
Yassinetaouil 46:b1a9de66ecab 12747 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
Yassinetaouil 46:b1a9de66ecab 12748 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
Yassinetaouil 46:b1a9de66ecab 12749 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 12750 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 12751 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
Yassinetaouil 46:b1a9de66ecab 12752
Yassinetaouil 46:b1a9de66ecab 12753 /* Bit 0 : TX buffer over-read detected, and prevented */
Yassinetaouil 46:b1a9de66ecab 12754 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
Yassinetaouil 46:b1a9de66ecab 12755 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
Yassinetaouil 46:b1a9de66ecab 12756 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 12757 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 12758 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
Yassinetaouil 46:b1a9de66ecab 12759
Yassinetaouil 46:b1a9de66ecab 12760 /* Register: SPIS_ENABLE */
Yassinetaouil 46:b1a9de66ecab 12761 /* Description: Enable SPI slave */
Yassinetaouil 46:b1a9de66ecab 12762
Yassinetaouil 46:b1a9de66ecab 12763 /* Bits 3..0 : Enable or disable SPI slave */
Yassinetaouil 46:b1a9de66ecab 12764 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 12765 #define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 12766 #define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
Yassinetaouil 46:b1a9de66ecab 12767 #define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
Yassinetaouil 46:b1a9de66ecab 12768
Yassinetaouil 46:b1a9de66ecab 12769 /* Register: SPIS_PSEL_SCK */
Yassinetaouil 46:b1a9de66ecab 12770 /* Description: Pin select for SCK */
Yassinetaouil 46:b1a9de66ecab 12771
Yassinetaouil 46:b1a9de66ecab 12772 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 12773 #define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12774 #define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12775 #define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 12776 #define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12777
Yassinetaouil 46:b1a9de66ecab 12778 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 12779 #define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12780 #define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12781
Yassinetaouil 46:b1a9de66ecab 12782 /* Register: SPIS_PSEL_MISO */
Yassinetaouil 46:b1a9de66ecab 12783 /* Description: Pin select for MISO signal */
Yassinetaouil 46:b1a9de66ecab 12784
Yassinetaouil 46:b1a9de66ecab 12785 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 12786 #define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12787 #define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12788 #define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 12789 #define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12790
Yassinetaouil 46:b1a9de66ecab 12791 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 12792 #define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12793 #define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12794
Yassinetaouil 46:b1a9de66ecab 12795 /* Register: SPIS_PSEL_MOSI */
Yassinetaouil 46:b1a9de66ecab 12796 /* Description: Pin select for MOSI signal */
Yassinetaouil 46:b1a9de66ecab 12797
Yassinetaouil 46:b1a9de66ecab 12798 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 12799 #define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12800 #define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12801 #define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 12802 #define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12803
Yassinetaouil 46:b1a9de66ecab 12804 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 12805 #define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12806 #define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12807
Yassinetaouil 46:b1a9de66ecab 12808 /* Register: SPIS_PSEL_CSN */
Yassinetaouil 46:b1a9de66ecab 12809 /* Description: Pin select for CSN signal */
Yassinetaouil 46:b1a9de66ecab 12810
Yassinetaouil 46:b1a9de66ecab 12811 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 12812 #define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12813 #define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 12814 #define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 12815 #define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 12816
Yassinetaouil 46:b1a9de66ecab 12817 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 12818 #define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12819 #define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 12820
Yassinetaouil 46:b1a9de66ecab 12821 /* Register: SPIS_RXD_PTR */
Yassinetaouil 46:b1a9de66ecab 12822 /* Description: RXD data pointer */
Yassinetaouil 46:b1a9de66ecab 12823
Yassinetaouil 46:b1a9de66ecab 12824 /* Bits 31..0 : RXD data pointer */
Yassinetaouil 46:b1a9de66ecab 12825 #define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12826 #define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12827
Yassinetaouil 46:b1a9de66ecab 12828 /* Register: SPIS_RXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 12829 /* Description: Maximum number of bytes in receive buffer */
Yassinetaouil 46:b1a9de66ecab 12830
Yassinetaouil 46:b1a9de66ecab 12831 /* Bits 7..0 : Maximum number of bytes in receive buffer */
Yassinetaouil 46:b1a9de66ecab 12832 #define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12833 #define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12834
Yassinetaouil 46:b1a9de66ecab 12835 /* Register: SPIS_RXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 12836 /* Description: Number of bytes received in last granted transaction */
Yassinetaouil 46:b1a9de66ecab 12837
Yassinetaouil 46:b1a9de66ecab 12838 /* Bits 7..0 : Number of bytes received in the last granted transaction */
Yassinetaouil 46:b1a9de66ecab 12839 #define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12840 #define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12841
Yassinetaouil 46:b1a9de66ecab 12842 /* Register: SPIS_TXD_PTR */
Yassinetaouil 46:b1a9de66ecab 12843 /* Description: TXD data pointer */
Yassinetaouil 46:b1a9de66ecab 12844
Yassinetaouil 46:b1a9de66ecab 12845 /* Bits 31..0 : TXD data pointer */
Yassinetaouil 46:b1a9de66ecab 12846 #define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12847 #define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 12848
Yassinetaouil 46:b1a9de66ecab 12849 /* Register: SPIS_TXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 12850 /* Description: Maximum number of bytes in transmit buffer */
Yassinetaouil 46:b1a9de66ecab 12851
Yassinetaouil 46:b1a9de66ecab 12852 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
Yassinetaouil 46:b1a9de66ecab 12853 #define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12854 #define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 12855
Yassinetaouil 46:b1a9de66ecab 12856 /* Register: SPIS_TXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 12857 /* Description: Number of bytes transmitted in last granted transaction */
Yassinetaouil 46:b1a9de66ecab 12858
Yassinetaouil 46:b1a9de66ecab 12859 /* Bits 7..0 : Number of bytes transmitted in last granted transaction */
Yassinetaouil 46:b1a9de66ecab 12860 #define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12861 #define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 12862
Yassinetaouil 46:b1a9de66ecab 12863 /* Register: SPIS_CONFIG */
Yassinetaouil 46:b1a9de66ecab 12864 /* Description: Configuration register */
Yassinetaouil 46:b1a9de66ecab 12865
Yassinetaouil 46:b1a9de66ecab 12866 /* Bit 2 : Serial clock (SCK) polarity */
Yassinetaouil 46:b1a9de66ecab 12867 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
Yassinetaouil 46:b1a9de66ecab 12868 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
Yassinetaouil 46:b1a9de66ecab 12869 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
Yassinetaouil 46:b1a9de66ecab 12870 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
Yassinetaouil 46:b1a9de66ecab 12871
Yassinetaouil 46:b1a9de66ecab 12872 /* Bit 1 : Serial clock (SCK) phase */
Yassinetaouil 46:b1a9de66ecab 12873 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
Yassinetaouil 46:b1a9de66ecab 12874 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
Yassinetaouil 46:b1a9de66ecab 12875 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
Yassinetaouil 46:b1a9de66ecab 12876 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
Yassinetaouil 46:b1a9de66ecab 12877
Yassinetaouil 46:b1a9de66ecab 12878 /* Bit 0 : Bit order */
Yassinetaouil 46:b1a9de66ecab 12879 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
Yassinetaouil 46:b1a9de66ecab 12880 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
Yassinetaouil 46:b1a9de66ecab 12881 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
Yassinetaouil 46:b1a9de66ecab 12882 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
Yassinetaouil 46:b1a9de66ecab 12883
Yassinetaouil 46:b1a9de66ecab 12884 /* Register: SPIS_DEF */
Yassinetaouil 46:b1a9de66ecab 12885 /* Description: Default character. Character clocked out in case of an ignored transaction. */
Yassinetaouil 46:b1a9de66ecab 12886
Yassinetaouil 46:b1a9de66ecab 12887 /* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
Yassinetaouil 46:b1a9de66ecab 12888 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
Yassinetaouil 46:b1a9de66ecab 12889 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
Yassinetaouil 46:b1a9de66ecab 12890
Yassinetaouil 46:b1a9de66ecab 12891 /* Register: SPIS_ORC */
Yassinetaouil 46:b1a9de66ecab 12892 /* Description: Over-read character */
Yassinetaouil 46:b1a9de66ecab 12893
Yassinetaouil 46:b1a9de66ecab 12894 /* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
Yassinetaouil 46:b1a9de66ecab 12895 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
Yassinetaouil 46:b1a9de66ecab 12896 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
Yassinetaouil 46:b1a9de66ecab 12897
Yassinetaouil 46:b1a9de66ecab 12898
Yassinetaouil 46:b1a9de66ecab 12899 /* Peripheral: TEMP */
Yassinetaouil 46:b1a9de66ecab 12900 /* Description: Temperature Sensor */
Yassinetaouil 46:b1a9de66ecab 12901
Yassinetaouil 46:b1a9de66ecab 12902 /* Register: TEMP_INTENSET */
Yassinetaouil 46:b1a9de66ecab 12903 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 12904
Yassinetaouil 46:b1a9de66ecab 12905 /* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
Yassinetaouil 46:b1a9de66ecab 12906 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
Yassinetaouil 46:b1a9de66ecab 12907 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
Yassinetaouil 46:b1a9de66ecab 12908 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12909 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12910 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 12911
Yassinetaouil 46:b1a9de66ecab 12912 /* Register: TEMP_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 12913 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 12914
Yassinetaouil 46:b1a9de66ecab 12915 /* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
Yassinetaouil 46:b1a9de66ecab 12916 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
Yassinetaouil 46:b1a9de66ecab 12917 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
Yassinetaouil 46:b1a9de66ecab 12918 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 12919 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 12920 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 12921
Yassinetaouil 46:b1a9de66ecab 12922 /* Register: TEMP_TEMP */
Yassinetaouil 46:b1a9de66ecab 12923 /* Description: Temperature in degC (0.25deg steps) */
Yassinetaouil 46:b1a9de66ecab 12924
Yassinetaouil 46:b1a9de66ecab 12925 /* Bits 31..0 : Temperature in degC (0.25deg steps) */
Yassinetaouil 46:b1a9de66ecab 12926 #define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
Yassinetaouil 46:b1a9de66ecab 12927 #define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
Yassinetaouil 46:b1a9de66ecab 12928
Yassinetaouil 46:b1a9de66ecab 12929 /* Register: TEMP_A0 */
Yassinetaouil 46:b1a9de66ecab 12930 /* Description: Slope of 1st piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12931
Yassinetaouil 46:b1a9de66ecab 12932 /* Bits 11..0 : Slope of 1st piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12933 #define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
Yassinetaouil 46:b1a9de66ecab 12934 #define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
Yassinetaouil 46:b1a9de66ecab 12935
Yassinetaouil 46:b1a9de66ecab 12936 /* Register: TEMP_A1 */
Yassinetaouil 46:b1a9de66ecab 12937 /* Description: Slope of 2nd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12938
Yassinetaouil 46:b1a9de66ecab 12939 /* Bits 11..0 : Slope of 2nd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12940 #define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
Yassinetaouil 46:b1a9de66ecab 12941 #define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
Yassinetaouil 46:b1a9de66ecab 12942
Yassinetaouil 46:b1a9de66ecab 12943 /* Register: TEMP_A2 */
Yassinetaouil 46:b1a9de66ecab 12944 /* Description: Slope of 3rd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12945
Yassinetaouil 46:b1a9de66ecab 12946 /* Bits 11..0 : Slope of 3rd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12947 #define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
Yassinetaouil 46:b1a9de66ecab 12948 #define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
Yassinetaouil 46:b1a9de66ecab 12949
Yassinetaouil 46:b1a9de66ecab 12950 /* Register: TEMP_A3 */
Yassinetaouil 46:b1a9de66ecab 12951 /* Description: Slope of 4th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12952
Yassinetaouil 46:b1a9de66ecab 12953 /* Bits 11..0 : Slope of 4th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12954 #define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
Yassinetaouil 46:b1a9de66ecab 12955 #define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
Yassinetaouil 46:b1a9de66ecab 12956
Yassinetaouil 46:b1a9de66ecab 12957 /* Register: TEMP_A4 */
Yassinetaouil 46:b1a9de66ecab 12958 /* Description: Slope of 5th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12959
Yassinetaouil 46:b1a9de66ecab 12960 /* Bits 11..0 : Slope of 5th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12961 #define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
Yassinetaouil 46:b1a9de66ecab 12962 #define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
Yassinetaouil 46:b1a9de66ecab 12963
Yassinetaouil 46:b1a9de66ecab 12964 /* Register: TEMP_A5 */
Yassinetaouil 46:b1a9de66ecab 12965 /* Description: Slope of 6th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12966
Yassinetaouil 46:b1a9de66ecab 12967 /* Bits 11..0 : Slope of 6th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12968 #define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
Yassinetaouil 46:b1a9de66ecab 12969 #define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
Yassinetaouil 46:b1a9de66ecab 12970
Yassinetaouil 46:b1a9de66ecab 12971 /* Register: TEMP_B0 */
Yassinetaouil 46:b1a9de66ecab 12972 /* Description: y-intercept of 1st piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12973
Yassinetaouil 46:b1a9de66ecab 12974 /* Bits 13..0 : y-intercept of 1st piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12975 #define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
Yassinetaouil 46:b1a9de66ecab 12976 #define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
Yassinetaouil 46:b1a9de66ecab 12977
Yassinetaouil 46:b1a9de66ecab 12978 /* Register: TEMP_B1 */
Yassinetaouil 46:b1a9de66ecab 12979 /* Description: y-intercept of 2nd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12980
Yassinetaouil 46:b1a9de66ecab 12981 /* Bits 13..0 : y-intercept of 2nd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12982 #define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
Yassinetaouil 46:b1a9de66ecab 12983 #define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
Yassinetaouil 46:b1a9de66ecab 12984
Yassinetaouil 46:b1a9de66ecab 12985 /* Register: TEMP_B2 */
Yassinetaouil 46:b1a9de66ecab 12986 /* Description: y-intercept of 3rd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12987
Yassinetaouil 46:b1a9de66ecab 12988 /* Bits 13..0 : y-intercept of 3rd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12989 #define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
Yassinetaouil 46:b1a9de66ecab 12990 #define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
Yassinetaouil 46:b1a9de66ecab 12991
Yassinetaouil 46:b1a9de66ecab 12992 /* Register: TEMP_B3 */
Yassinetaouil 46:b1a9de66ecab 12993 /* Description: y-intercept of 4th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12994
Yassinetaouil 46:b1a9de66ecab 12995 /* Bits 13..0 : y-intercept of 4th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 12996 #define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
Yassinetaouil 46:b1a9de66ecab 12997 #define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
Yassinetaouil 46:b1a9de66ecab 12998
Yassinetaouil 46:b1a9de66ecab 12999 /* Register: TEMP_B4 */
Yassinetaouil 46:b1a9de66ecab 13000 /* Description: y-intercept of 5th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13001
Yassinetaouil 46:b1a9de66ecab 13002 /* Bits 13..0 : y-intercept of 5th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13003 #define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
Yassinetaouil 46:b1a9de66ecab 13004 #define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
Yassinetaouil 46:b1a9de66ecab 13005
Yassinetaouil 46:b1a9de66ecab 13006 /* Register: TEMP_B5 */
Yassinetaouil 46:b1a9de66ecab 13007 /* Description: y-intercept of 6th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13008
Yassinetaouil 46:b1a9de66ecab 13009 /* Bits 13..0 : y-intercept of 6th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13010 #define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
Yassinetaouil 46:b1a9de66ecab 13011 #define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
Yassinetaouil 46:b1a9de66ecab 13012
Yassinetaouil 46:b1a9de66ecab 13013 /* Register: TEMP_T0 */
Yassinetaouil 46:b1a9de66ecab 13014 /* Description: End point of 1st piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13015
Yassinetaouil 46:b1a9de66ecab 13016 /* Bits 7..0 : End point of 1st piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13017 #define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
Yassinetaouil 46:b1a9de66ecab 13018 #define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
Yassinetaouil 46:b1a9de66ecab 13019
Yassinetaouil 46:b1a9de66ecab 13020 /* Register: TEMP_T1 */
Yassinetaouil 46:b1a9de66ecab 13021 /* Description: End point of 2nd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13022
Yassinetaouil 46:b1a9de66ecab 13023 /* Bits 7..0 : End point of 2nd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13024 #define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
Yassinetaouil 46:b1a9de66ecab 13025 #define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
Yassinetaouil 46:b1a9de66ecab 13026
Yassinetaouil 46:b1a9de66ecab 13027 /* Register: TEMP_T2 */
Yassinetaouil 46:b1a9de66ecab 13028 /* Description: End point of 3rd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13029
Yassinetaouil 46:b1a9de66ecab 13030 /* Bits 7..0 : End point of 3rd piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13031 #define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
Yassinetaouil 46:b1a9de66ecab 13032 #define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
Yassinetaouil 46:b1a9de66ecab 13033
Yassinetaouil 46:b1a9de66ecab 13034 /* Register: TEMP_T3 */
Yassinetaouil 46:b1a9de66ecab 13035 /* Description: End point of 4th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13036
Yassinetaouil 46:b1a9de66ecab 13037 /* Bits 7..0 : End point of 4th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13038 #define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
Yassinetaouil 46:b1a9de66ecab 13039 #define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
Yassinetaouil 46:b1a9de66ecab 13040
Yassinetaouil 46:b1a9de66ecab 13041 /* Register: TEMP_T4 */
Yassinetaouil 46:b1a9de66ecab 13042 /* Description: End point of 5th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13043
Yassinetaouil 46:b1a9de66ecab 13044 /* Bits 7..0 : End point of 5th piece wise linear function */
Yassinetaouil 46:b1a9de66ecab 13045 #define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
Yassinetaouil 46:b1a9de66ecab 13046 #define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
Yassinetaouil 46:b1a9de66ecab 13047
Yassinetaouil 46:b1a9de66ecab 13048
Yassinetaouil 46:b1a9de66ecab 13049 /* Peripheral: TIMER */
Yassinetaouil 46:b1a9de66ecab 13050 /* Description: Timer/Counter 0 */
Yassinetaouil 46:b1a9de66ecab 13051
Yassinetaouil 46:b1a9de66ecab 13052 /* Register: TIMER_SHORTS */
Yassinetaouil 46:b1a9de66ecab 13053 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 13054
Yassinetaouil 46:b1a9de66ecab 13055 /* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13056 #define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13057 #define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13058 #define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13059 #define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13060
Yassinetaouil 46:b1a9de66ecab 13061 /* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13062 #define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13063 #define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13064 #define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13065 #define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13066
Yassinetaouil 46:b1a9de66ecab 13067 /* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13068 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13069 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13070 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13071 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13072
Yassinetaouil 46:b1a9de66ecab 13073 /* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13074 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13075 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13076 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13077 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13078
Yassinetaouil 46:b1a9de66ecab 13079 /* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13080 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13081 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13082 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13083 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13084
Yassinetaouil 46:b1a9de66ecab 13085 /* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13086 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13087 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13088 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13089 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13090
Yassinetaouil 46:b1a9de66ecab 13091 /* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
Yassinetaouil 46:b1a9de66ecab 13092 #define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13093 #define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13094 #define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13095 #define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13096
Yassinetaouil 46:b1a9de66ecab 13097 /* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
Yassinetaouil 46:b1a9de66ecab 13098 #define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13099 #define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13100 #define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13101 #define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13102
Yassinetaouil 46:b1a9de66ecab 13103 /* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
Yassinetaouil 46:b1a9de66ecab 13104 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13105 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13106 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13107 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13108
Yassinetaouil 46:b1a9de66ecab 13109 /* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
Yassinetaouil 46:b1a9de66ecab 13110 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13111 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13112 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13113 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13114
Yassinetaouil 46:b1a9de66ecab 13115 /* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
Yassinetaouil 46:b1a9de66ecab 13116 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13117 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13118 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13119 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13120
Yassinetaouil 46:b1a9de66ecab 13121 /* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
Yassinetaouil 46:b1a9de66ecab 13122 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13123 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
Yassinetaouil 46:b1a9de66ecab 13124 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13125 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13126
Yassinetaouil 46:b1a9de66ecab 13127 /* Register: TIMER_INTENSET */
Yassinetaouil 46:b1a9de66ecab 13128 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 13129
Yassinetaouil 46:b1a9de66ecab 13130 /* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
Yassinetaouil 46:b1a9de66ecab 13131 #define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
Yassinetaouil 46:b1a9de66ecab 13132 #define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
Yassinetaouil 46:b1a9de66ecab 13133 #define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13134 #define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13135 #define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13136
Yassinetaouil 46:b1a9de66ecab 13137 /* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
Yassinetaouil 46:b1a9de66ecab 13138 #define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
Yassinetaouil 46:b1a9de66ecab 13139 #define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
Yassinetaouil 46:b1a9de66ecab 13140 #define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13141 #define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13142 #define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13143
Yassinetaouil 46:b1a9de66ecab 13144 /* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
Yassinetaouil 46:b1a9de66ecab 13145 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 13146 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 13147 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13148 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13149 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13150
Yassinetaouil 46:b1a9de66ecab 13151 /* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
Yassinetaouil 46:b1a9de66ecab 13152 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 13153 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 13154 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13155 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13156 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13157
Yassinetaouil 46:b1a9de66ecab 13158 /* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
Yassinetaouil 46:b1a9de66ecab 13159 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 13160 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 13161 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13162 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13163 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13164
Yassinetaouil 46:b1a9de66ecab 13165 /* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
Yassinetaouil 46:b1a9de66ecab 13166 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 13167 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 13168 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13169 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13170 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13171
Yassinetaouil 46:b1a9de66ecab 13172 /* Register: TIMER_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 13173 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 13174
Yassinetaouil 46:b1a9de66ecab 13175 /* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
Yassinetaouil 46:b1a9de66ecab 13176 #define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
Yassinetaouil 46:b1a9de66ecab 13177 #define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
Yassinetaouil 46:b1a9de66ecab 13178 #define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13179 #define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13180 #define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13181
Yassinetaouil 46:b1a9de66ecab 13182 /* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
Yassinetaouil 46:b1a9de66ecab 13183 #define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
Yassinetaouil 46:b1a9de66ecab 13184 #define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
Yassinetaouil 46:b1a9de66ecab 13185 #define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13186 #define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13187 #define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13188
Yassinetaouil 46:b1a9de66ecab 13189 /* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
Yassinetaouil 46:b1a9de66ecab 13190 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 13191 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Yassinetaouil 46:b1a9de66ecab 13192 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13193 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13194 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13195
Yassinetaouil 46:b1a9de66ecab 13196 /* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
Yassinetaouil 46:b1a9de66ecab 13197 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 13198 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Yassinetaouil 46:b1a9de66ecab 13199 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13200 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13201 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13202
Yassinetaouil 46:b1a9de66ecab 13203 /* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
Yassinetaouil 46:b1a9de66ecab 13204 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 13205 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Yassinetaouil 46:b1a9de66ecab 13206 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13207 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13208 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13209
Yassinetaouil 46:b1a9de66ecab 13210 /* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
Yassinetaouil 46:b1a9de66ecab 13211 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 13212 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Yassinetaouil 46:b1a9de66ecab 13213 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13214 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13215 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13216
Yassinetaouil 46:b1a9de66ecab 13217 /* Register: TIMER_MODE */
Yassinetaouil 46:b1a9de66ecab 13218 /* Description: Timer mode selection */
Yassinetaouil 46:b1a9de66ecab 13219
Yassinetaouil 46:b1a9de66ecab 13220 /* Bits 1..0 : Timer mode */
Yassinetaouil 46:b1a9de66ecab 13221 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Yassinetaouil 46:b1a9de66ecab 13222 #define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Yassinetaouil 46:b1a9de66ecab 13223 #define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
Yassinetaouil 46:b1a9de66ecab 13224 #define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator - Select Counter mode */
Yassinetaouil 46:b1a9de66ecab 13225 #define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
Yassinetaouil 46:b1a9de66ecab 13226
Yassinetaouil 46:b1a9de66ecab 13227 /* Register: TIMER_BITMODE */
Yassinetaouil 46:b1a9de66ecab 13228 /* Description: Configure the number of bits used by the TIMER */
Yassinetaouil 46:b1a9de66ecab 13229
Yassinetaouil 46:b1a9de66ecab 13230 /* Bits 1..0 : Timer bit width */
Yassinetaouil 46:b1a9de66ecab 13231 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
Yassinetaouil 46:b1a9de66ecab 13232 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
Yassinetaouil 46:b1a9de66ecab 13233 #define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
Yassinetaouil 46:b1a9de66ecab 13234 #define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
Yassinetaouil 46:b1a9de66ecab 13235 #define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
Yassinetaouil 46:b1a9de66ecab 13236 #define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
Yassinetaouil 46:b1a9de66ecab 13237
Yassinetaouil 46:b1a9de66ecab 13238 /* Register: TIMER_PRESCALER */
Yassinetaouil 46:b1a9de66ecab 13239 /* Description: Timer prescaler register */
Yassinetaouil 46:b1a9de66ecab 13240
Yassinetaouil 46:b1a9de66ecab 13241 /* Bits 3..0 : Prescaler value */
Yassinetaouil 46:b1a9de66ecab 13242 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
Yassinetaouil 46:b1a9de66ecab 13243 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
Yassinetaouil 46:b1a9de66ecab 13244
Yassinetaouil 46:b1a9de66ecab 13245 /* Register: TIMER_CC */
Yassinetaouil 46:b1a9de66ecab 13246 /* Description: Description collection[0]: Capture/Compare register 0 */
Yassinetaouil 46:b1a9de66ecab 13247
Yassinetaouil 46:b1a9de66ecab 13248 /* Bits 31..0 : Capture/Compare value */
Yassinetaouil 46:b1a9de66ecab 13249 #define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
Yassinetaouil 46:b1a9de66ecab 13250 #define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
Yassinetaouil 46:b1a9de66ecab 13251
Yassinetaouil 46:b1a9de66ecab 13252
Yassinetaouil 46:b1a9de66ecab 13253 /* Peripheral: TWI */
Yassinetaouil 46:b1a9de66ecab 13254 /* Description: I2C compatible Two-Wire Interface 0 */
Yassinetaouil 46:b1a9de66ecab 13255
Yassinetaouil 46:b1a9de66ecab 13256 /* Register: TWI_SHORTS */
Yassinetaouil 46:b1a9de66ecab 13257 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 13258
Yassinetaouil 46:b1a9de66ecab 13259 /* Bit 1 : Shortcut between BB event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13260 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13261 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13262 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13263 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13264
Yassinetaouil 46:b1a9de66ecab 13265 /* Bit 0 : Shortcut between BB event and SUSPEND task */
Yassinetaouil 46:b1a9de66ecab 13266 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
Yassinetaouil 46:b1a9de66ecab 13267 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
Yassinetaouil 46:b1a9de66ecab 13268 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13269 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13270
Yassinetaouil 46:b1a9de66ecab 13271 /* Register: TWI_INTENSET */
Yassinetaouil 46:b1a9de66ecab 13272 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 13273
Yassinetaouil 46:b1a9de66ecab 13274 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
Yassinetaouil 46:b1a9de66ecab 13275 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13276 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13277 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13278 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13279 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13280
Yassinetaouil 46:b1a9de66ecab 13281 /* Bit 14 : Write '1' to Enable interrupt for BB event */
Yassinetaouil 46:b1a9de66ecab 13282 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
Yassinetaouil 46:b1a9de66ecab 13283 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
Yassinetaouil 46:b1a9de66ecab 13284 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13285 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13286 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13287
Yassinetaouil 46:b1a9de66ecab 13288 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 13289 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13290 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13291 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13292 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13293 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13294
Yassinetaouil 46:b1a9de66ecab 13295 /* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
Yassinetaouil 46:b1a9de66ecab 13296 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
Yassinetaouil 46:b1a9de66ecab 13297 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
Yassinetaouil 46:b1a9de66ecab 13298 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13299 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13300 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13301
Yassinetaouil 46:b1a9de66ecab 13302 /* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
Yassinetaouil 46:b1a9de66ecab 13303 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
Yassinetaouil 46:b1a9de66ecab 13304 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
Yassinetaouil 46:b1a9de66ecab 13305 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13306 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13307 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13308
Yassinetaouil 46:b1a9de66ecab 13309 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 13310 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13311 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13312 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13313 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13314 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13315
Yassinetaouil 46:b1a9de66ecab 13316 /* Register: TWI_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 13317 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 13318
Yassinetaouil 46:b1a9de66ecab 13319 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
Yassinetaouil 46:b1a9de66ecab 13320 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13321 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13322 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13323 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13324 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13325
Yassinetaouil 46:b1a9de66ecab 13326 /* Bit 14 : Write '1' to Disable interrupt for BB event */
Yassinetaouil 46:b1a9de66ecab 13327 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
Yassinetaouil 46:b1a9de66ecab 13328 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
Yassinetaouil 46:b1a9de66ecab 13329 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13330 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13331 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13332
Yassinetaouil 46:b1a9de66ecab 13333 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 13334 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13335 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13336 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13337 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13338 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13339
Yassinetaouil 46:b1a9de66ecab 13340 /* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
Yassinetaouil 46:b1a9de66ecab 13341 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
Yassinetaouil 46:b1a9de66ecab 13342 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
Yassinetaouil 46:b1a9de66ecab 13343 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13344 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13345 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13346
Yassinetaouil 46:b1a9de66ecab 13347 /* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
Yassinetaouil 46:b1a9de66ecab 13348 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
Yassinetaouil 46:b1a9de66ecab 13349 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
Yassinetaouil 46:b1a9de66ecab 13350 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13351 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13352 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13353
Yassinetaouil 46:b1a9de66ecab 13354 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 13355 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13356 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13357 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13358 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13359 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13360
Yassinetaouil 46:b1a9de66ecab 13361 /* Register: TWI_ERRORSRC */
Yassinetaouil 46:b1a9de66ecab 13362 /* Description: Error source */
Yassinetaouil 46:b1a9de66ecab 13363
Yassinetaouil 46:b1a9de66ecab 13364 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 13365 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
Yassinetaouil 46:b1a9de66ecab 13366 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
Yassinetaouil 46:b1a9de66ecab 13367 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 13368 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 13369
Yassinetaouil 46:b1a9de66ecab 13370 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 13371 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
Yassinetaouil 46:b1a9de66ecab 13372 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
Yassinetaouil 46:b1a9de66ecab 13373 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 13374 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 13375
Yassinetaouil 46:b1a9de66ecab 13376 /* Bit 0 : Overrun error */
Yassinetaouil 46:b1a9de66ecab 13377 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
Yassinetaouil 46:b1a9de66ecab 13378 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
Yassinetaouil 46:b1a9de66ecab 13379 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
Yassinetaouil 46:b1a9de66ecab 13380 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
Yassinetaouil 46:b1a9de66ecab 13381
Yassinetaouil 46:b1a9de66ecab 13382 /* Register: TWI_ENABLE */
Yassinetaouil 46:b1a9de66ecab 13383 /* Description: Enable TWI */
Yassinetaouil 46:b1a9de66ecab 13384
Yassinetaouil 46:b1a9de66ecab 13385 /* Bits 3..0 : Enable or disable TWI */
Yassinetaouil 46:b1a9de66ecab 13386 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 13387 #define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 13388 #define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
Yassinetaouil 46:b1a9de66ecab 13389 #define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
Yassinetaouil 46:b1a9de66ecab 13390
Yassinetaouil 46:b1a9de66ecab 13391 /* Register: TWI_PSELSCL */
Yassinetaouil 46:b1a9de66ecab 13392 /* Description: Pin select for SCL */
Yassinetaouil 46:b1a9de66ecab 13393
Yassinetaouil 46:b1a9de66ecab 13394 /* Bits 31..0 : Pin number configuration for TWI SCL signal */
Yassinetaouil 46:b1a9de66ecab 13395 #define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
Yassinetaouil 46:b1a9de66ecab 13396 #define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
Yassinetaouil 46:b1a9de66ecab 13397 #define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 13398
Yassinetaouil 46:b1a9de66ecab 13399 /* Register: TWI_PSELSDA */
Yassinetaouil 46:b1a9de66ecab 13400 /* Description: Pin select for SDA */
Yassinetaouil 46:b1a9de66ecab 13401
Yassinetaouil 46:b1a9de66ecab 13402 /* Bits 31..0 : Pin number configuration for TWI SDA signal */
Yassinetaouil 46:b1a9de66ecab 13403 #define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
Yassinetaouil 46:b1a9de66ecab 13404 #define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
Yassinetaouil 46:b1a9de66ecab 13405 #define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 13406
Yassinetaouil 46:b1a9de66ecab 13407 /* Register: TWI_RXD */
Yassinetaouil 46:b1a9de66ecab 13408 /* Description: RXD register */
Yassinetaouil 46:b1a9de66ecab 13409
Yassinetaouil 46:b1a9de66ecab 13410 /* Bits 7..0 : RXD register */
Yassinetaouil 46:b1a9de66ecab 13411 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Yassinetaouil 46:b1a9de66ecab 13412 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Yassinetaouil 46:b1a9de66ecab 13413
Yassinetaouil 46:b1a9de66ecab 13414 /* Register: TWI_TXD */
Yassinetaouil 46:b1a9de66ecab 13415 /* Description: TXD register */
Yassinetaouil 46:b1a9de66ecab 13416
Yassinetaouil 46:b1a9de66ecab 13417 /* Bits 7..0 : TXD register */
Yassinetaouil 46:b1a9de66ecab 13418 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Yassinetaouil 46:b1a9de66ecab 13419 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Yassinetaouil 46:b1a9de66ecab 13420
Yassinetaouil 46:b1a9de66ecab 13421 /* Register: TWI_FREQUENCY */
Yassinetaouil 46:b1a9de66ecab 13422 /* Description: TWI frequency */
Yassinetaouil 46:b1a9de66ecab 13423
Yassinetaouil 46:b1a9de66ecab 13424 /* Bits 31..0 : TWI master clock frequency */
Yassinetaouil 46:b1a9de66ecab 13425 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 13426 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 13427 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
Yassinetaouil 46:b1a9de66ecab 13428 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
Yassinetaouil 46:b1a9de66ecab 13429 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
Yassinetaouil 46:b1a9de66ecab 13430
Yassinetaouil 46:b1a9de66ecab 13431 /* Register: TWI_ADDRESS */
Yassinetaouil 46:b1a9de66ecab 13432 /* Description: Address used in the TWI transfer */
Yassinetaouil 46:b1a9de66ecab 13433
Yassinetaouil 46:b1a9de66ecab 13434 /* Bits 6..0 : Address used in the TWI transfer */
Yassinetaouil 46:b1a9de66ecab 13435 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 13436 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 13437
Yassinetaouil 46:b1a9de66ecab 13438
Yassinetaouil 46:b1a9de66ecab 13439 /* Peripheral: TWIM */
Yassinetaouil 46:b1a9de66ecab 13440 /* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
Yassinetaouil 46:b1a9de66ecab 13441
Yassinetaouil 46:b1a9de66ecab 13442 /* Register: TWIM_SHORTS */
Yassinetaouil 46:b1a9de66ecab 13443 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 13444
Yassinetaouil 46:b1a9de66ecab 13445 /* Bit 12 : Shortcut between LASTRX event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13446 #define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13447 #define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13448 #define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13449 #define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13450
Yassinetaouil 46:b1a9de66ecab 13451 /* Bit 10 : Shortcut between LASTRX event and STARTTX task */
Yassinetaouil 46:b1a9de66ecab 13452 #define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
Yassinetaouil 46:b1a9de66ecab 13453 #define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
Yassinetaouil 46:b1a9de66ecab 13454 #define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13455 #define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13456
Yassinetaouil 46:b1a9de66ecab 13457 /* Bit 9 : Shortcut between LASTTX event and STOP task */
Yassinetaouil 46:b1a9de66ecab 13458 #define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13459 #define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
Yassinetaouil 46:b1a9de66ecab 13460 #define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13461 #define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13462
Yassinetaouil 46:b1a9de66ecab 13463 /* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
Yassinetaouil 46:b1a9de66ecab 13464 #define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
Yassinetaouil 46:b1a9de66ecab 13465 #define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
Yassinetaouil 46:b1a9de66ecab 13466 #define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13467 #define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13468
Yassinetaouil 46:b1a9de66ecab 13469 /* Bit 7 : Shortcut between LASTTX event and STARTRX task */
Yassinetaouil 46:b1a9de66ecab 13470 #define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
Yassinetaouil 46:b1a9de66ecab 13471 #define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
Yassinetaouil 46:b1a9de66ecab 13472 #define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13473 #define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13474
Yassinetaouil 46:b1a9de66ecab 13475 /* Register: TWIM_INTEN */
Yassinetaouil 46:b1a9de66ecab 13476 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 13477
Yassinetaouil 46:b1a9de66ecab 13478 /* Bit 24 : Enable or disable interrupt for LASTTX event */
Yassinetaouil 46:b1a9de66ecab 13479 #define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
Yassinetaouil 46:b1a9de66ecab 13480 #define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
Yassinetaouil 46:b1a9de66ecab 13481 #define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13482 #define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13483
Yassinetaouil 46:b1a9de66ecab 13484 /* Bit 23 : Enable or disable interrupt for LASTRX event */
Yassinetaouil 46:b1a9de66ecab 13485 #define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
Yassinetaouil 46:b1a9de66ecab 13486 #define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
Yassinetaouil 46:b1a9de66ecab 13487 #define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13488 #define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13489
Yassinetaouil 46:b1a9de66ecab 13490 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13491 #define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13492 #define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13493 #define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13494 #define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13495
Yassinetaouil 46:b1a9de66ecab 13496 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13497 #define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13498 #define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13499 #define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13500 #define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13501
Yassinetaouil 46:b1a9de66ecab 13502 /* Bit 18 : Enable or disable interrupt for SUSPENDED event */
Yassinetaouil 46:b1a9de66ecab 13503 #define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13504 #define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13505 #define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13506 #define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13507
Yassinetaouil 46:b1a9de66ecab 13508 /* Bit 9 : Enable or disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 13509 #define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13510 #define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13511 #define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13512 #define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13513
Yassinetaouil 46:b1a9de66ecab 13514 /* Bit 1 : Enable or disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 13515 #define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13516 #define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13517 #define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13518 #define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13519
Yassinetaouil 46:b1a9de66ecab 13520 /* Register: TWIM_INTENSET */
Yassinetaouil 46:b1a9de66ecab 13521 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 13522
Yassinetaouil 46:b1a9de66ecab 13523 /* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
Yassinetaouil 46:b1a9de66ecab 13524 #define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
Yassinetaouil 46:b1a9de66ecab 13525 #define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
Yassinetaouil 46:b1a9de66ecab 13526 #define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13527 #define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13528 #define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13529
Yassinetaouil 46:b1a9de66ecab 13530 /* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
Yassinetaouil 46:b1a9de66ecab 13531 #define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
Yassinetaouil 46:b1a9de66ecab 13532 #define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
Yassinetaouil 46:b1a9de66ecab 13533 #define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13534 #define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13535 #define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13536
Yassinetaouil 46:b1a9de66ecab 13537 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13538 #define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13539 #define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13540 #define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13541 #define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13542 #define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13543
Yassinetaouil 46:b1a9de66ecab 13544 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13545 #define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13546 #define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13547 #define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13548 #define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13549 #define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13550
Yassinetaouil 46:b1a9de66ecab 13551 /* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
Yassinetaouil 46:b1a9de66ecab 13552 #define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13553 #define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13554 #define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13555 #define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13556 #define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13557
Yassinetaouil 46:b1a9de66ecab 13558 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 13559 #define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13560 #define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13561 #define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13562 #define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13563 #define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13564
Yassinetaouil 46:b1a9de66ecab 13565 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 13566 #define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13567 #define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13568 #define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13569 #define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13570 #define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13571
Yassinetaouil 46:b1a9de66ecab 13572 /* Register: TWIM_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 13573 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 13574
Yassinetaouil 46:b1a9de66ecab 13575 /* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
Yassinetaouil 46:b1a9de66ecab 13576 #define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
Yassinetaouil 46:b1a9de66ecab 13577 #define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
Yassinetaouil 46:b1a9de66ecab 13578 #define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13579 #define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13580 #define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13581
Yassinetaouil 46:b1a9de66ecab 13582 /* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
Yassinetaouil 46:b1a9de66ecab 13583 #define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
Yassinetaouil 46:b1a9de66ecab 13584 #define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
Yassinetaouil 46:b1a9de66ecab 13585 #define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13586 #define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13587 #define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13588
Yassinetaouil 46:b1a9de66ecab 13589 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13590 #define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13591 #define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13592 #define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13593 #define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13594 #define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13595
Yassinetaouil 46:b1a9de66ecab 13596 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13597 #define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13598 #define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13599 #define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13600 #define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13601 #define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13602
Yassinetaouil 46:b1a9de66ecab 13603 /* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
Yassinetaouil 46:b1a9de66ecab 13604 #define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13605 #define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
Yassinetaouil 46:b1a9de66ecab 13606 #define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13607 #define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13608 #define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13609
Yassinetaouil 46:b1a9de66ecab 13610 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 13611 #define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13612 #define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13613 #define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13614 #define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13615 #define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13616
Yassinetaouil 46:b1a9de66ecab 13617 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 13618 #define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13619 #define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13620 #define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13621 #define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13622 #define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13623
Yassinetaouil 46:b1a9de66ecab 13624 /* Register: TWIM_ERRORSRC */
Yassinetaouil 46:b1a9de66ecab 13625 /* Description: Error source */
Yassinetaouil 46:b1a9de66ecab 13626
Yassinetaouil 46:b1a9de66ecab 13627 /* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 13628 #define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
Yassinetaouil 46:b1a9de66ecab 13629 #define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
Yassinetaouil 46:b1a9de66ecab 13630 #define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
Yassinetaouil 46:b1a9de66ecab 13631 #define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
Yassinetaouil 46:b1a9de66ecab 13632
Yassinetaouil 46:b1a9de66ecab 13633 /* Bit 1 : NACK received after sending the address (write '1' to clear) */
Yassinetaouil 46:b1a9de66ecab 13634 #define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
Yassinetaouil 46:b1a9de66ecab 13635 #define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
Yassinetaouil 46:b1a9de66ecab 13636 #define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
Yassinetaouil 46:b1a9de66ecab 13637 #define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
Yassinetaouil 46:b1a9de66ecab 13638
Yassinetaouil 46:b1a9de66ecab 13639 /* Register: TWIM_ENABLE */
Yassinetaouil 46:b1a9de66ecab 13640 /* Description: Enable TWIM */
Yassinetaouil 46:b1a9de66ecab 13641
Yassinetaouil 46:b1a9de66ecab 13642 /* Bits 3..0 : Enable or disable TWIM */
Yassinetaouil 46:b1a9de66ecab 13643 #define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 13644 #define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 13645 #define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
Yassinetaouil 46:b1a9de66ecab 13646 #define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
Yassinetaouil 46:b1a9de66ecab 13647
Yassinetaouil 46:b1a9de66ecab 13648 /* Register: TWIM_PSEL_SCL */
Yassinetaouil 46:b1a9de66ecab 13649 /* Description: Pin select for SCL signal */
Yassinetaouil 46:b1a9de66ecab 13650
Yassinetaouil 46:b1a9de66ecab 13651 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 13652 #define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 13653 #define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 13654 #define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 13655 #define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 13656
Yassinetaouil 46:b1a9de66ecab 13657 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 13658 #define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 13659 #define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 13660
Yassinetaouil 46:b1a9de66ecab 13661 /* Register: TWIM_PSEL_SDA */
Yassinetaouil 46:b1a9de66ecab 13662 /* Description: Pin select for SDA signal */
Yassinetaouil 46:b1a9de66ecab 13663
Yassinetaouil 46:b1a9de66ecab 13664 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 13665 #define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 13666 #define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 13667 #define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 13668 #define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 13669
Yassinetaouil 46:b1a9de66ecab 13670 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 13671 #define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 13672 #define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 13673
Yassinetaouil 46:b1a9de66ecab 13674 /* Register: TWIM_FREQUENCY */
Yassinetaouil 46:b1a9de66ecab 13675 /* Description: TWI frequency */
Yassinetaouil 46:b1a9de66ecab 13676
Yassinetaouil 46:b1a9de66ecab 13677 /* Bits 31..0 : TWI master clock frequency */
Yassinetaouil 46:b1a9de66ecab 13678 #define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 13679 #define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Yassinetaouil 46:b1a9de66ecab 13680 #define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
Yassinetaouil 46:b1a9de66ecab 13681 #define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
Yassinetaouil 46:b1a9de66ecab 13682 #define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
Yassinetaouil 46:b1a9de66ecab 13683
Yassinetaouil 46:b1a9de66ecab 13684 /* Register: TWIM_RXD_PTR */
Yassinetaouil 46:b1a9de66ecab 13685 /* Description: Data pointer */
Yassinetaouil 46:b1a9de66ecab 13686
Yassinetaouil 46:b1a9de66ecab 13687 /* Bits 31..0 : Data pointer */
Yassinetaouil 46:b1a9de66ecab 13688 #define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 13689 #define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 13690
Yassinetaouil 46:b1a9de66ecab 13691 /* Register: TWIM_RXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 13692 /* Description: Maximum number of bytes in receive buffer */
Yassinetaouil 46:b1a9de66ecab 13693
Yassinetaouil 46:b1a9de66ecab 13694 /* Bits 7..0 : Maximum number of bytes in receive buffer */
Yassinetaouil 46:b1a9de66ecab 13695 #define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 13696 #define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 13697
Yassinetaouil 46:b1a9de66ecab 13698 /* Register: TWIM_RXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 13699 /* Description: Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 13700
Yassinetaouil 46:b1a9de66ecab 13701 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
Yassinetaouil 46:b1a9de66ecab 13702 #define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 13703 #define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 13704
Yassinetaouil 46:b1a9de66ecab 13705 /* Register: TWIM_RXD_LIST */
Yassinetaouil 46:b1a9de66ecab 13706 /* Description: EasyDMA list type */
Yassinetaouil 46:b1a9de66ecab 13707
Yassinetaouil 46:b1a9de66ecab 13708 /* Bits 2..0 : List type */
Yassinetaouil 46:b1a9de66ecab 13709 #define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
Yassinetaouil 46:b1a9de66ecab 13710 #define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
Yassinetaouil 46:b1a9de66ecab 13711 #define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
Yassinetaouil 46:b1a9de66ecab 13712 #define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
Yassinetaouil 46:b1a9de66ecab 13713
Yassinetaouil 46:b1a9de66ecab 13714 /* Register: TWIM_TXD_PTR */
Yassinetaouil 46:b1a9de66ecab 13715 /* Description: Data pointer */
Yassinetaouil 46:b1a9de66ecab 13716
Yassinetaouil 46:b1a9de66ecab 13717 /* Bits 31..0 : Data pointer */
Yassinetaouil 46:b1a9de66ecab 13718 #define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 13719 #define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 13720
Yassinetaouil 46:b1a9de66ecab 13721 /* Register: TWIM_TXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 13722 /* Description: Maximum number of bytes in transmit buffer */
Yassinetaouil 46:b1a9de66ecab 13723
Yassinetaouil 46:b1a9de66ecab 13724 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
Yassinetaouil 46:b1a9de66ecab 13725 #define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 13726 #define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 13727
Yassinetaouil 46:b1a9de66ecab 13728 /* Register: TWIM_TXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 13729 /* Description: Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 13730
Yassinetaouil 46:b1a9de66ecab 13731 /* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
Yassinetaouil 46:b1a9de66ecab 13732 #define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 13733 #define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 13734
Yassinetaouil 46:b1a9de66ecab 13735 /* Register: TWIM_TXD_LIST */
Yassinetaouil 46:b1a9de66ecab 13736 /* Description: EasyDMA list type */
Yassinetaouil 46:b1a9de66ecab 13737
Yassinetaouil 46:b1a9de66ecab 13738 /* Bits 2..0 : List type */
Yassinetaouil 46:b1a9de66ecab 13739 #define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
Yassinetaouil 46:b1a9de66ecab 13740 #define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
Yassinetaouil 46:b1a9de66ecab 13741 #define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
Yassinetaouil 46:b1a9de66ecab 13742 #define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
Yassinetaouil 46:b1a9de66ecab 13743
Yassinetaouil 46:b1a9de66ecab 13744 /* Register: TWIM_ADDRESS */
Yassinetaouil 46:b1a9de66ecab 13745 /* Description: Address used in the TWI transfer */
Yassinetaouil 46:b1a9de66ecab 13746
Yassinetaouil 46:b1a9de66ecab 13747 /* Bits 6..0 : Address used in the TWI transfer */
Yassinetaouil 46:b1a9de66ecab 13748 #define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 13749 #define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 13750
Yassinetaouil 46:b1a9de66ecab 13751
Yassinetaouil 46:b1a9de66ecab 13752 /* Peripheral: TWIS */
Yassinetaouil 46:b1a9de66ecab 13753 /* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
Yassinetaouil 46:b1a9de66ecab 13754
Yassinetaouil 46:b1a9de66ecab 13755 /* Register: TWIS_SHORTS */
Yassinetaouil 46:b1a9de66ecab 13756 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 13757
Yassinetaouil 46:b1a9de66ecab 13758 /* Bit 14 : Shortcut between READ event and SUSPEND task */
Yassinetaouil 46:b1a9de66ecab 13759 #define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
Yassinetaouil 46:b1a9de66ecab 13760 #define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
Yassinetaouil 46:b1a9de66ecab 13761 #define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13762 #define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13763
Yassinetaouil 46:b1a9de66ecab 13764 /* Bit 13 : Shortcut between WRITE event and SUSPEND task */
Yassinetaouil 46:b1a9de66ecab 13765 #define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
Yassinetaouil 46:b1a9de66ecab 13766 #define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
Yassinetaouil 46:b1a9de66ecab 13767 #define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 13768 #define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 13769
Yassinetaouil 46:b1a9de66ecab 13770 /* Register: TWIS_INTEN */
Yassinetaouil 46:b1a9de66ecab 13771 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 13772
Yassinetaouil 46:b1a9de66ecab 13773 /* Bit 26 : Enable or disable interrupt for READ event */
Yassinetaouil 46:b1a9de66ecab 13774 #define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
Yassinetaouil 46:b1a9de66ecab 13775 #define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
Yassinetaouil 46:b1a9de66ecab 13776 #define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13777 #define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13778
Yassinetaouil 46:b1a9de66ecab 13779 /* Bit 25 : Enable or disable interrupt for WRITE event */
Yassinetaouil 46:b1a9de66ecab 13780 #define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
Yassinetaouil 46:b1a9de66ecab 13781 #define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
Yassinetaouil 46:b1a9de66ecab 13782 #define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13783 #define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13784
Yassinetaouil 46:b1a9de66ecab 13785 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13786 #define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13787 #define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13788 #define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13789 #define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13790
Yassinetaouil 46:b1a9de66ecab 13791 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13792 #define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13793 #define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13794 #define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13795 #define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13796
Yassinetaouil 46:b1a9de66ecab 13797 /* Bit 9 : Enable or disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 13798 #define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13799 #define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13800 #define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13801 #define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13802
Yassinetaouil 46:b1a9de66ecab 13803 /* Bit 1 : Enable or disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 13804 #define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13805 #define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13806 #define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13807 #define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13808
Yassinetaouil 46:b1a9de66ecab 13809 /* Register: TWIS_INTENSET */
Yassinetaouil 46:b1a9de66ecab 13810 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 13811
Yassinetaouil 46:b1a9de66ecab 13812 /* Bit 26 : Write '1' to Enable interrupt for READ event */
Yassinetaouil 46:b1a9de66ecab 13813 #define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
Yassinetaouil 46:b1a9de66ecab 13814 #define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
Yassinetaouil 46:b1a9de66ecab 13815 #define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13816 #define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13817 #define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13818
Yassinetaouil 46:b1a9de66ecab 13819 /* Bit 25 : Write '1' to Enable interrupt for WRITE event */
Yassinetaouil 46:b1a9de66ecab 13820 #define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
Yassinetaouil 46:b1a9de66ecab 13821 #define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
Yassinetaouil 46:b1a9de66ecab 13822 #define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13823 #define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13824 #define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13825
Yassinetaouil 46:b1a9de66ecab 13826 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13827 #define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13828 #define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13829 #define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13830 #define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13831 #define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13832
Yassinetaouil 46:b1a9de66ecab 13833 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13834 #define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13835 #define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13836 #define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13837 #define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13838 #define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13839
Yassinetaouil 46:b1a9de66ecab 13840 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 13841 #define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13842 #define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13843 #define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13844 #define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13845 #define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13846
Yassinetaouil 46:b1a9de66ecab 13847 /* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 13848 #define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13849 #define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13850 #define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13851 #define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13852 #define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 13853
Yassinetaouil 46:b1a9de66ecab 13854 /* Register: TWIS_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 13855 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 13856
Yassinetaouil 46:b1a9de66ecab 13857 /* Bit 26 : Write '1' to Disable interrupt for READ event */
Yassinetaouil 46:b1a9de66ecab 13858 #define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
Yassinetaouil 46:b1a9de66ecab 13859 #define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
Yassinetaouil 46:b1a9de66ecab 13860 #define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13861 #define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13862 #define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13863
Yassinetaouil 46:b1a9de66ecab 13864 /* Bit 25 : Write '1' to Disable interrupt for WRITE event */
Yassinetaouil 46:b1a9de66ecab 13865 #define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
Yassinetaouil 46:b1a9de66ecab 13866 #define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
Yassinetaouil 46:b1a9de66ecab 13867 #define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13868 #define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13869 #define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13870
Yassinetaouil 46:b1a9de66ecab 13871 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13872 #define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13873 #define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13874 #define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13875 #define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13876 #define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13877
Yassinetaouil 46:b1a9de66ecab 13878 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 13879 #define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13880 #define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 13881 #define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13882 #define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13883 #define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13884
Yassinetaouil 46:b1a9de66ecab 13885 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 13886 #define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13887 #define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 13888 #define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13889 #define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13890 #define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13891
Yassinetaouil 46:b1a9de66ecab 13892 /* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
Yassinetaouil 46:b1a9de66ecab 13893 #define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13894 #define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Yassinetaouil 46:b1a9de66ecab 13895 #define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 13896 #define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 13897 #define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 13898
Yassinetaouil 46:b1a9de66ecab 13899 /* Register: TWIS_ERRORSRC */
Yassinetaouil 46:b1a9de66ecab 13900 /* Description: Error source */
Yassinetaouil 46:b1a9de66ecab 13901
Yassinetaouil 46:b1a9de66ecab 13902 /* Bit 3 : TX buffer over-read detected, and prevented */
Yassinetaouil 46:b1a9de66ecab 13903 #define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
Yassinetaouil 46:b1a9de66ecab 13904 #define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
Yassinetaouil 46:b1a9de66ecab 13905 #define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
Yassinetaouil 46:b1a9de66ecab 13906 #define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
Yassinetaouil 46:b1a9de66ecab 13907
Yassinetaouil 46:b1a9de66ecab 13908 /* Bit 2 : NACK sent after receiving a data byte */
Yassinetaouil 46:b1a9de66ecab 13909 #define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
Yassinetaouil 46:b1a9de66ecab 13910 #define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
Yassinetaouil 46:b1a9de66ecab 13911 #define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
Yassinetaouil 46:b1a9de66ecab 13912 #define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
Yassinetaouil 46:b1a9de66ecab 13913
Yassinetaouil 46:b1a9de66ecab 13914 /* Bit 0 : RX buffer overflow detected, and prevented */
Yassinetaouil 46:b1a9de66ecab 13915 #define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
Yassinetaouil 46:b1a9de66ecab 13916 #define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
Yassinetaouil 46:b1a9de66ecab 13917 #define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
Yassinetaouil 46:b1a9de66ecab 13918 #define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
Yassinetaouil 46:b1a9de66ecab 13919
Yassinetaouil 46:b1a9de66ecab 13920 /* Register: TWIS_MATCH */
Yassinetaouil 46:b1a9de66ecab 13921 /* Description: Status register indicating which address had a match */
Yassinetaouil 46:b1a9de66ecab 13922
Yassinetaouil 46:b1a9de66ecab 13923 /* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
Yassinetaouil 46:b1a9de66ecab 13924 #define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
Yassinetaouil 46:b1a9de66ecab 13925 #define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
Yassinetaouil 46:b1a9de66ecab 13926
Yassinetaouil 46:b1a9de66ecab 13927 /* Register: TWIS_ENABLE */
Yassinetaouil 46:b1a9de66ecab 13928 /* Description: Enable TWIS */
Yassinetaouil 46:b1a9de66ecab 13929
Yassinetaouil 46:b1a9de66ecab 13930 /* Bits 3..0 : Enable or disable TWIS */
Yassinetaouil 46:b1a9de66ecab 13931 #define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 13932 #define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 13933 #define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
Yassinetaouil 46:b1a9de66ecab 13934 #define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
Yassinetaouil 46:b1a9de66ecab 13935
Yassinetaouil 46:b1a9de66ecab 13936 /* Register: TWIS_PSEL_SCL */
Yassinetaouil 46:b1a9de66ecab 13937 /* Description: Pin select for SCL signal */
Yassinetaouil 46:b1a9de66ecab 13938
Yassinetaouil 46:b1a9de66ecab 13939 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 13940 #define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 13941 #define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 13942 #define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 13943 #define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 13944
Yassinetaouil 46:b1a9de66ecab 13945 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 13946 #define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 13947 #define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 13948
Yassinetaouil 46:b1a9de66ecab 13949 /* Register: TWIS_PSEL_SDA */
Yassinetaouil 46:b1a9de66ecab 13950 /* Description: Pin select for SDA signal */
Yassinetaouil 46:b1a9de66ecab 13951
Yassinetaouil 46:b1a9de66ecab 13952 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 13953 #define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 13954 #define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 13955 #define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 13956 #define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 13957
Yassinetaouil 46:b1a9de66ecab 13958 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 13959 #define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 13960 #define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 13961
Yassinetaouil 46:b1a9de66ecab 13962 /* Register: TWIS_RXD_PTR */
Yassinetaouil 46:b1a9de66ecab 13963 /* Description: RXD Data pointer */
Yassinetaouil 46:b1a9de66ecab 13964
Yassinetaouil 46:b1a9de66ecab 13965 /* Bits 31..0 : RXD Data pointer */
Yassinetaouil 46:b1a9de66ecab 13966 #define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 13967 #define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 13968
Yassinetaouil 46:b1a9de66ecab 13969 /* Register: TWIS_RXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 13970 /* Description: Maximum number of bytes in RXD buffer */
Yassinetaouil 46:b1a9de66ecab 13971
Yassinetaouil 46:b1a9de66ecab 13972 /* Bits 7..0 : Maximum number of bytes in RXD buffer */
Yassinetaouil 46:b1a9de66ecab 13973 #define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 13974 #define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 13975
Yassinetaouil 46:b1a9de66ecab 13976 /* Register: TWIS_RXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 13977 /* Description: Number of bytes transferred in the last RXD transaction */
Yassinetaouil 46:b1a9de66ecab 13978
Yassinetaouil 46:b1a9de66ecab 13979 /* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
Yassinetaouil 46:b1a9de66ecab 13980 #define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 13981 #define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 13982
Yassinetaouil 46:b1a9de66ecab 13983 /* Register: TWIS_TXD_PTR */
Yassinetaouil 46:b1a9de66ecab 13984 /* Description: TXD Data pointer */
Yassinetaouil 46:b1a9de66ecab 13985
Yassinetaouil 46:b1a9de66ecab 13986 /* Bits 31..0 : TXD Data pointer */
Yassinetaouil 46:b1a9de66ecab 13987 #define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 13988 #define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 13989
Yassinetaouil 46:b1a9de66ecab 13990 /* Register: TWIS_TXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 13991 /* Description: Maximum number of bytes in TXD buffer */
Yassinetaouil 46:b1a9de66ecab 13992
Yassinetaouil 46:b1a9de66ecab 13993 /* Bits 7..0 : Maximum number of bytes in TXD buffer */
Yassinetaouil 46:b1a9de66ecab 13994 #define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 13995 #define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 13996
Yassinetaouil 46:b1a9de66ecab 13997 /* Register: TWIS_TXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 13998 /* Description: Number of bytes transferred in the last TXD transaction */
Yassinetaouil 46:b1a9de66ecab 13999
Yassinetaouil 46:b1a9de66ecab 14000 /* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
Yassinetaouil 46:b1a9de66ecab 14001 #define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 14002 #define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 14003
Yassinetaouil 46:b1a9de66ecab 14004 /* Register: TWIS_ADDRESS */
Yassinetaouil 46:b1a9de66ecab 14005 /* Description: Description collection[0]: TWI slave address 0 */
Yassinetaouil 46:b1a9de66ecab 14006
Yassinetaouil 46:b1a9de66ecab 14007 /* Bits 6..0 : TWI slave address */
Yassinetaouil 46:b1a9de66ecab 14008 #define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 14009 #define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Yassinetaouil 46:b1a9de66ecab 14010
Yassinetaouil 46:b1a9de66ecab 14011 /* Register: TWIS_CONFIG */
Yassinetaouil 46:b1a9de66ecab 14012 /* Description: Configuration register for the address match mechanism */
Yassinetaouil 46:b1a9de66ecab 14013
Yassinetaouil 46:b1a9de66ecab 14014 /* Bit 1 : Enable or disable address matching on ADDRESS[1] */
Yassinetaouil 46:b1a9de66ecab 14015 #define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
Yassinetaouil 46:b1a9de66ecab 14016 #define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
Yassinetaouil 46:b1a9de66ecab 14017 #define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 14018 #define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 14019
Yassinetaouil 46:b1a9de66ecab 14020 /* Bit 0 : Enable or disable address matching on ADDRESS[0] */
Yassinetaouil 46:b1a9de66ecab 14021 #define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
Yassinetaouil 46:b1a9de66ecab 14022 #define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
Yassinetaouil 46:b1a9de66ecab 14023 #define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 14024 #define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 14025
Yassinetaouil 46:b1a9de66ecab 14026 /* Register: TWIS_ORC */
Yassinetaouil 46:b1a9de66ecab 14027 /* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
Yassinetaouil 46:b1a9de66ecab 14028
Yassinetaouil 46:b1a9de66ecab 14029 /* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
Yassinetaouil 46:b1a9de66ecab 14030 #define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
Yassinetaouil 46:b1a9de66ecab 14031 #define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
Yassinetaouil 46:b1a9de66ecab 14032
Yassinetaouil 46:b1a9de66ecab 14033
Yassinetaouil 46:b1a9de66ecab 14034 /* Peripheral: UART */
Yassinetaouil 46:b1a9de66ecab 14035 /* Description: Universal Asynchronous Receiver/Transmitter */
Yassinetaouil 46:b1a9de66ecab 14036
Yassinetaouil 46:b1a9de66ecab 14037 /* Register: UART_SHORTS */
Yassinetaouil 46:b1a9de66ecab 14038 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 14039
Yassinetaouil 46:b1a9de66ecab 14040 /* Bit 4 : Shortcut between NCTS event and STOPRX task */
Yassinetaouil 46:b1a9de66ecab 14041 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
Yassinetaouil 46:b1a9de66ecab 14042 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
Yassinetaouil 46:b1a9de66ecab 14043 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 14044 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 14045
Yassinetaouil 46:b1a9de66ecab 14046 /* Bit 3 : Shortcut between CTS event and STARTRX task */
Yassinetaouil 46:b1a9de66ecab 14047 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
Yassinetaouil 46:b1a9de66ecab 14048 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
Yassinetaouil 46:b1a9de66ecab 14049 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 14050 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 14051
Yassinetaouil 46:b1a9de66ecab 14052 /* Register: UART_INTENSET */
Yassinetaouil 46:b1a9de66ecab 14053 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 14054
Yassinetaouil 46:b1a9de66ecab 14055 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
Yassinetaouil 46:b1a9de66ecab 14056 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14057 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14058 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14059 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14060 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14061
Yassinetaouil 46:b1a9de66ecab 14062 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 14063 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14064 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14065 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14066 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14067 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14068
Yassinetaouil 46:b1a9de66ecab 14069 /* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
Yassinetaouil 46:b1a9de66ecab 14070 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
Yassinetaouil 46:b1a9de66ecab 14071 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
Yassinetaouil 46:b1a9de66ecab 14072 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14073 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14074 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14075
Yassinetaouil 46:b1a9de66ecab 14076 /* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
Yassinetaouil 46:b1a9de66ecab 14077 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
Yassinetaouil 46:b1a9de66ecab 14078 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
Yassinetaouil 46:b1a9de66ecab 14079 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14080 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14081 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14082
Yassinetaouil 46:b1a9de66ecab 14083 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
Yassinetaouil 46:b1a9de66ecab 14084 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14085 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14086 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14087 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14088 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14089
Yassinetaouil 46:b1a9de66ecab 14090 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
Yassinetaouil 46:b1a9de66ecab 14091 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14092 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14093 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14094 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14095 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14096
Yassinetaouil 46:b1a9de66ecab 14097 /* Register: UART_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 14098 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 14099
Yassinetaouil 46:b1a9de66ecab 14100 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
Yassinetaouil 46:b1a9de66ecab 14101 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14102 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14103 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14104 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14105 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14106
Yassinetaouil 46:b1a9de66ecab 14107 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 14108 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14109 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14110 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14111 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14112 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14113
Yassinetaouil 46:b1a9de66ecab 14114 /* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
Yassinetaouil 46:b1a9de66ecab 14115 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
Yassinetaouil 46:b1a9de66ecab 14116 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
Yassinetaouil 46:b1a9de66ecab 14117 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14118 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14119 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14120
Yassinetaouil 46:b1a9de66ecab 14121 /* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
Yassinetaouil 46:b1a9de66ecab 14122 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
Yassinetaouil 46:b1a9de66ecab 14123 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
Yassinetaouil 46:b1a9de66ecab 14124 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14125 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14126 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14127
Yassinetaouil 46:b1a9de66ecab 14128 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
Yassinetaouil 46:b1a9de66ecab 14129 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14130 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14131 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14132 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14133 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14134
Yassinetaouil 46:b1a9de66ecab 14135 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
Yassinetaouil 46:b1a9de66ecab 14136 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14137 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14138 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14139 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14140 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14141
Yassinetaouil 46:b1a9de66ecab 14142 /* Register: UART_ERRORSRC */
Yassinetaouil 46:b1a9de66ecab 14143 /* Description: Error source */
Yassinetaouil 46:b1a9de66ecab 14144
Yassinetaouil 46:b1a9de66ecab 14145 /* Bit 3 : Break condition */
Yassinetaouil 46:b1a9de66ecab 14146 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
Yassinetaouil 46:b1a9de66ecab 14147 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
Yassinetaouil 46:b1a9de66ecab 14148 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 14149 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 14150
Yassinetaouil 46:b1a9de66ecab 14151 /* Bit 2 : Framing error occurred */
Yassinetaouil 46:b1a9de66ecab 14152 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
Yassinetaouil 46:b1a9de66ecab 14153 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
Yassinetaouil 46:b1a9de66ecab 14154 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 14155 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 14156
Yassinetaouil 46:b1a9de66ecab 14157 /* Bit 1 : Parity error */
Yassinetaouil 46:b1a9de66ecab 14158 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 14159 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 14160 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 14161 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 14162
Yassinetaouil 46:b1a9de66ecab 14163 /* Bit 0 : Overrun error */
Yassinetaouil 46:b1a9de66ecab 14164 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
Yassinetaouil 46:b1a9de66ecab 14165 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
Yassinetaouil 46:b1a9de66ecab 14166 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 14167 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 14168
Yassinetaouil 46:b1a9de66ecab 14169 /* Register: UART_ENABLE */
Yassinetaouil 46:b1a9de66ecab 14170 /* Description: Enable UART */
Yassinetaouil 46:b1a9de66ecab 14171
Yassinetaouil 46:b1a9de66ecab 14172 /* Bits 3..0 : Enable or disable UART */
Yassinetaouil 46:b1a9de66ecab 14173 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 14174 #define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 14175 #define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
Yassinetaouil 46:b1a9de66ecab 14176 #define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
Yassinetaouil 46:b1a9de66ecab 14177
Yassinetaouil 46:b1a9de66ecab 14178 /* Register: UART_PSELRTS */
Yassinetaouil 46:b1a9de66ecab 14179 /* Description: Pin select for RTS */
Yassinetaouil 46:b1a9de66ecab 14180
Yassinetaouil 46:b1a9de66ecab 14181 /* Bits 31..0 : Pin number configuration for UART RTS signal */
Yassinetaouil 46:b1a9de66ecab 14182 #define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
Yassinetaouil 46:b1a9de66ecab 14183 #define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
Yassinetaouil 46:b1a9de66ecab 14184 #define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14185
Yassinetaouil 46:b1a9de66ecab 14186 /* Register: UART_PSELTXD */
Yassinetaouil 46:b1a9de66ecab 14187 /* Description: Pin select for TXD */
Yassinetaouil 46:b1a9de66ecab 14188
Yassinetaouil 46:b1a9de66ecab 14189 /* Bits 31..0 : Pin number configuration for UART TXD signal */
Yassinetaouil 46:b1a9de66ecab 14190 #define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
Yassinetaouil 46:b1a9de66ecab 14191 #define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
Yassinetaouil 46:b1a9de66ecab 14192 #define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14193
Yassinetaouil 46:b1a9de66ecab 14194 /* Register: UART_PSELCTS */
Yassinetaouil 46:b1a9de66ecab 14195 /* Description: Pin select for CTS */
Yassinetaouil 46:b1a9de66ecab 14196
Yassinetaouil 46:b1a9de66ecab 14197 /* Bits 31..0 : Pin number configuration for UART CTS signal */
Yassinetaouil 46:b1a9de66ecab 14198 #define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
Yassinetaouil 46:b1a9de66ecab 14199 #define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
Yassinetaouil 46:b1a9de66ecab 14200 #define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14201
Yassinetaouil 46:b1a9de66ecab 14202 /* Register: UART_PSELRXD */
Yassinetaouil 46:b1a9de66ecab 14203 /* Description: Pin select for RXD */
Yassinetaouil 46:b1a9de66ecab 14204
Yassinetaouil 46:b1a9de66ecab 14205 /* Bits 31..0 : Pin number configuration for UART RXD signal */
Yassinetaouil 46:b1a9de66ecab 14206 #define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
Yassinetaouil 46:b1a9de66ecab 14207 #define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
Yassinetaouil 46:b1a9de66ecab 14208 #define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14209
Yassinetaouil 46:b1a9de66ecab 14210 /* Register: UART_RXD */
Yassinetaouil 46:b1a9de66ecab 14211 /* Description: RXD register */
Yassinetaouil 46:b1a9de66ecab 14212
Yassinetaouil 46:b1a9de66ecab 14213 /* Bits 7..0 : RX data received in previous transfers, double buffered */
Yassinetaouil 46:b1a9de66ecab 14214 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Yassinetaouil 46:b1a9de66ecab 14215 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Yassinetaouil 46:b1a9de66ecab 14216
Yassinetaouil 46:b1a9de66ecab 14217 /* Register: UART_TXD */
Yassinetaouil 46:b1a9de66ecab 14218 /* Description: TXD register */
Yassinetaouil 46:b1a9de66ecab 14219
Yassinetaouil 46:b1a9de66ecab 14220 /* Bits 7..0 : TX data to be transferred */
Yassinetaouil 46:b1a9de66ecab 14221 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Yassinetaouil 46:b1a9de66ecab 14222 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Yassinetaouil 46:b1a9de66ecab 14223
Yassinetaouil 46:b1a9de66ecab 14224 /* Register: UART_BAUDRATE */
Yassinetaouil 46:b1a9de66ecab 14225 /* Description: Baud rate */
Yassinetaouil 46:b1a9de66ecab 14226
Yassinetaouil 46:b1a9de66ecab 14227 /* Bits 31..0 : Baud-rate */
Yassinetaouil 46:b1a9de66ecab 14228 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
Yassinetaouil 46:b1a9de66ecab 14229 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
Yassinetaouil 46:b1a9de66ecab 14230 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
Yassinetaouil 46:b1a9de66ecab 14231 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
Yassinetaouil 46:b1a9de66ecab 14232 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
Yassinetaouil 46:b1a9de66ecab 14233 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
Yassinetaouil 46:b1a9de66ecab 14234 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
Yassinetaouil 46:b1a9de66ecab 14235 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
Yassinetaouil 46:b1a9de66ecab 14236 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
Yassinetaouil 46:b1a9de66ecab 14237 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
Yassinetaouil 46:b1a9de66ecab 14238 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
Yassinetaouil 46:b1a9de66ecab 14239 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
Yassinetaouil 46:b1a9de66ecab 14240 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
Yassinetaouil 46:b1a9de66ecab 14241 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
Yassinetaouil 46:b1a9de66ecab 14242 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
Yassinetaouil 46:b1a9de66ecab 14243 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
Yassinetaouil 46:b1a9de66ecab 14244 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
Yassinetaouil 46:b1a9de66ecab 14245 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
Yassinetaouil 46:b1a9de66ecab 14246
Yassinetaouil 46:b1a9de66ecab 14247 /* Register: UART_CONFIG */
Yassinetaouil 46:b1a9de66ecab 14248 /* Description: Configuration of parity and hardware flow control */
Yassinetaouil 46:b1a9de66ecab 14249
Yassinetaouil 46:b1a9de66ecab 14250 /* Bits 3..1 : Parity */
Yassinetaouil 46:b1a9de66ecab 14251 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 14252 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 14253 #define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
Yassinetaouil 46:b1a9de66ecab 14254 #define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
Yassinetaouil 46:b1a9de66ecab 14255
Yassinetaouil 46:b1a9de66ecab 14256 /* Bit 0 : Hardware flow control */
Yassinetaouil 46:b1a9de66ecab 14257 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
Yassinetaouil 46:b1a9de66ecab 14258 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
Yassinetaouil 46:b1a9de66ecab 14259 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 14260 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 14261
Yassinetaouil 46:b1a9de66ecab 14262
Yassinetaouil 46:b1a9de66ecab 14263 /* Peripheral: UARTE */
Yassinetaouil 46:b1a9de66ecab 14264 /* Description: UART with EasyDMA */
Yassinetaouil 46:b1a9de66ecab 14265
Yassinetaouil 46:b1a9de66ecab 14266 /* Register: UARTE_SHORTS */
Yassinetaouil 46:b1a9de66ecab 14267 /* Description: Shortcut register */
Yassinetaouil 46:b1a9de66ecab 14268
Yassinetaouil 46:b1a9de66ecab 14269 /* Bit 6 : Shortcut between ENDRX event and STOPRX task */
Yassinetaouil 46:b1a9de66ecab 14270 #define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
Yassinetaouil 46:b1a9de66ecab 14271 #define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
Yassinetaouil 46:b1a9de66ecab 14272 #define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 14273 #define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 14274
Yassinetaouil 46:b1a9de66ecab 14275 /* Bit 5 : Shortcut between ENDRX event and STARTRX task */
Yassinetaouil 46:b1a9de66ecab 14276 #define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
Yassinetaouil 46:b1a9de66ecab 14277 #define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
Yassinetaouil 46:b1a9de66ecab 14278 #define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
Yassinetaouil 46:b1a9de66ecab 14279 #define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
Yassinetaouil 46:b1a9de66ecab 14280
Yassinetaouil 46:b1a9de66ecab 14281 /* Register: UARTE_INTEN */
Yassinetaouil 46:b1a9de66ecab 14282 /* Description: Enable or disable interrupt */
Yassinetaouil 46:b1a9de66ecab 14283
Yassinetaouil 46:b1a9de66ecab 14284 /* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
Yassinetaouil 46:b1a9de66ecab 14285 #define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
Yassinetaouil 46:b1a9de66ecab 14286 #define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
Yassinetaouil 46:b1a9de66ecab 14287 #define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14288 #define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14289
Yassinetaouil 46:b1a9de66ecab 14290 /* Bit 20 : Enable or disable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 14291 #define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14292 #define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14293 #define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14294 #define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14295
Yassinetaouil 46:b1a9de66ecab 14296 /* Bit 19 : Enable or disable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 14297 #define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14298 #define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14299 #define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14300 #define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14301
Yassinetaouil 46:b1a9de66ecab 14302 /* Bit 17 : Enable or disable interrupt for RXTO event */
Yassinetaouil 46:b1a9de66ecab 14303 #define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14304 #define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14305 #define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14306 #define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14307
Yassinetaouil 46:b1a9de66ecab 14308 /* Bit 9 : Enable or disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 14309 #define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14310 #define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14311 #define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14312 #define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14313
Yassinetaouil 46:b1a9de66ecab 14314 /* Bit 8 : Enable or disable interrupt for ENDTX event */
Yassinetaouil 46:b1a9de66ecab 14315 #define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 14316 #define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 14317 #define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14318 #define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14319
Yassinetaouil 46:b1a9de66ecab 14320 /* Bit 4 : Enable or disable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 14321 #define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 14322 #define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 14323 #define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14324 #define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14325
Yassinetaouil 46:b1a9de66ecab 14326 /* Bit 1 : Enable or disable interrupt for NCTS event */
Yassinetaouil 46:b1a9de66ecab 14327 #define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14328 #define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14329 #define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14330 #define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14331
Yassinetaouil 46:b1a9de66ecab 14332 /* Bit 0 : Enable or disable interrupt for CTS event */
Yassinetaouil 46:b1a9de66ecab 14333 #define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14334 #define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14335 #define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14336 #define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14337
Yassinetaouil 46:b1a9de66ecab 14338 /* Register: UARTE_INTENSET */
Yassinetaouil 46:b1a9de66ecab 14339 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 14340
Yassinetaouil 46:b1a9de66ecab 14341 /* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
Yassinetaouil 46:b1a9de66ecab 14342 #define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
Yassinetaouil 46:b1a9de66ecab 14343 #define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
Yassinetaouil 46:b1a9de66ecab 14344 #define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14345 #define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14346 #define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14347
Yassinetaouil 46:b1a9de66ecab 14348 /* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 14349 #define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14350 #define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14351 #define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14352 #define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14353 #define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14354
Yassinetaouil 46:b1a9de66ecab 14355 /* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 14356 #define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14357 #define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14358 #define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14359 #define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14360 #define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14361
Yassinetaouil 46:b1a9de66ecab 14362 /* Bit 17 : Write '1' to Enable interrupt for RXTO event */
Yassinetaouil 46:b1a9de66ecab 14363 #define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14364 #define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14365 #define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14366 #define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14367 #define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14368
Yassinetaouil 46:b1a9de66ecab 14369 /* Bit 9 : Write '1' to Enable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 14370 #define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14371 #define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14372 #define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14373 #define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14374 #define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14375
Yassinetaouil 46:b1a9de66ecab 14376 /* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
Yassinetaouil 46:b1a9de66ecab 14377 #define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 14378 #define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 14379 #define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14380 #define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14381 #define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14382
Yassinetaouil 46:b1a9de66ecab 14383 /* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 14384 #define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 14385 #define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 14386 #define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14387 #define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14388 #define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14389
Yassinetaouil 46:b1a9de66ecab 14390 /* Bit 1 : Write '1' to Enable interrupt for NCTS event */
Yassinetaouil 46:b1a9de66ecab 14391 #define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14392 #define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14393 #define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14394 #define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14395 #define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14396
Yassinetaouil 46:b1a9de66ecab 14397 /* Bit 0 : Write '1' to Enable interrupt for CTS event */
Yassinetaouil 46:b1a9de66ecab 14398 #define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14399 #define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14400 #define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14401 #define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14402 #define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14403
Yassinetaouil 46:b1a9de66ecab 14404 /* Register: UARTE_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 14405 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 14406
Yassinetaouil 46:b1a9de66ecab 14407 /* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
Yassinetaouil 46:b1a9de66ecab 14408 #define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
Yassinetaouil 46:b1a9de66ecab 14409 #define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
Yassinetaouil 46:b1a9de66ecab 14410 #define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14411 #define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14412 #define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14413
Yassinetaouil 46:b1a9de66ecab 14414 /* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 14415 #define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14416 #define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14417 #define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14418 #define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14419 #define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14420
Yassinetaouil 46:b1a9de66ecab 14421 /* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
Yassinetaouil 46:b1a9de66ecab 14422 #define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14423 #define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
Yassinetaouil 46:b1a9de66ecab 14424 #define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14425 #define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14426 #define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14427
Yassinetaouil 46:b1a9de66ecab 14428 /* Bit 17 : Write '1' to Disable interrupt for RXTO event */
Yassinetaouil 46:b1a9de66ecab 14429 #define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14430 #define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
Yassinetaouil 46:b1a9de66ecab 14431 #define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14432 #define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14433 #define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14434
Yassinetaouil 46:b1a9de66ecab 14435 /* Bit 9 : Write '1' to Disable interrupt for ERROR event */
Yassinetaouil 46:b1a9de66ecab 14436 #define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14437 #define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Yassinetaouil 46:b1a9de66ecab 14438 #define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14439 #define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14440 #define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14441
Yassinetaouil 46:b1a9de66ecab 14442 /* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
Yassinetaouil 46:b1a9de66ecab 14443 #define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 14444 #define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
Yassinetaouil 46:b1a9de66ecab 14445 #define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14446 #define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14447 #define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14448
Yassinetaouil 46:b1a9de66ecab 14449 /* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
Yassinetaouil 46:b1a9de66ecab 14450 #define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 14451 #define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
Yassinetaouil 46:b1a9de66ecab 14452 #define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14453 #define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14454 #define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14455
Yassinetaouil 46:b1a9de66ecab 14456 /* Bit 1 : Write '1' to Disable interrupt for NCTS event */
Yassinetaouil 46:b1a9de66ecab 14457 #define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14458 #define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
Yassinetaouil 46:b1a9de66ecab 14459 #define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14460 #define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14461 #define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14462
Yassinetaouil 46:b1a9de66ecab 14463 /* Bit 0 : Write '1' to Disable interrupt for CTS event */
Yassinetaouil 46:b1a9de66ecab 14464 #define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14465 #define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
Yassinetaouil 46:b1a9de66ecab 14466 #define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14467 #define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14468 #define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14469
Yassinetaouil 46:b1a9de66ecab 14470 /* Register: UARTE_ERRORSRC */
Yassinetaouil 46:b1a9de66ecab 14471 /* Description: Error source */
Yassinetaouil 46:b1a9de66ecab 14472
Yassinetaouil 46:b1a9de66ecab 14473 /* Bit 3 : Break condition */
Yassinetaouil 46:b1a9de66ecab 14474 #define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
Yassinetaouil 46:b1a9de66ecab 14475 #define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
Yassinetaouil 46:b1a9de66ecab 14476 #define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 14477 #define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 14478
Yassinetaouil 46:b1a9de66ecab 14479 /* Bit 2 : Framing error occurred */
Yassinetaouil 46:b1a9de66ecab 14480 #define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
Yassinetaouil 46:b1a9de66ecab 14481 #define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
Yassinetaouil 46:b1a9de66ecab 14482 #define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 14483 #define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 14484
Yassinetaouil 46:b1a9de66ecab 14485 /* Bit 1 : Parity error */
Yassinetaouil 46:b1a9de66ecab 14486 #define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 14487 #define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 14488 #define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 14489 #define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 14490
Yassinetaouil 46:b1a9de66ecab 14491 /* Bit 0 : Overrun error */
Yassinetaouil 46:b1a9de66ecab 14492 #define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
Yassinetaouil 46:b1a9de66ecab 14493 #define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
Yassinetaouil 46:b1a9de66ecab 14494 #define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
Yassinetaouil 46:b1a9de66ecab 14495 #define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
Yassinetaouil 46:b1a9de66ecab 14496
Yassinetaouil 46:b1a9de66ecab 14497 /* Register: UARTE_ENABLE */
Yassinetaouil 46:b1a9de66ecab 14498 /* Description: Enable UART */
Yassinetaouil 46:b1a9de66ecab 14499
Yassinetaouil 46:b1a9de66ecab 14500 /* Bits 3..0 : Enable or disable UARTE */
Yassinetaouil 46:b1a9de66ecab 14501 #define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 14502 #define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Yassinetaouil 46:b1a9de66ecab 14503 #define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
Yassinetaouil 46:b1a9de66ecab 14504 #define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
Yassinetaouil 46:b1a9de66ecab 14505
Yassinetaouil 46:b1a9de66ecab 14506 /* Register: UARTE_PSEL_RTS */
Yassinetaouil 46:b1a9de66ecab 14507 /* Description: Pin select for RTS signal */
Yassinetaouil 46:b1a9de66ecab 14508
Yassinetaouil 46:b1a9de66ecab 14509 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 14510 #define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14511 #define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14512 #define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 14513 #define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14514
Yassinetaouil 46:b1a9de66ecab 14515 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 14516 #define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14517 #define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14518
Yassinetaouil 46:b1a9de66ecab 14519 /* Register: UARTE_PSEL_TXD */
Yassinetaouil 46:b1a9de66ecab 14520 /* Description: Pin select for TXD signal */
Yassinetaouil 46:b1a9de66ecab 14521
Yassinetaouil 46:b1a9de66ecab 14522 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 14523 #define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14524 #define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14525 #define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 14526 #define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14527
Yassinetaouil 46:b1a9de66ecab 14528 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 14529 #define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14530 #define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14531
Yassinetaouil 46:b1a9de66ecab 14532 /* Register: UARTE_PSEL_CTS */
Yassinetaouil 46:b1a9de66ecab 14533 /* Description: Pin select for CTS signal */
Yassinetaouil 46:b1a9de66ecab 14534
Yassinetaouil 46:b1a9de66ecab 14535 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 14536 #define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14537 #define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14538 #define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 14539 #define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14540
Yassinetaouil 46:b1a9de66ecab 14541 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 14542 #define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14543 #define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14544
Yassinetaouil 46:b1a9de66ecab 14545 /* Register: UARTE_PSEL_RXD */
Yassinetaouil 46:b1a9de66ecab 14546 /* Description: Pin select for RXD signal */
Yassinetaouil 46:b1a9de66ecab 14547
Yassinetaouil 46:b1a9de66ecab 14548 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 14549 #define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14550 #define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14551 #define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 14552 #define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14553
Yassinetaouil 46:b1a9de66ecab 14554 /* Bits 4..0 : Pin number */
Yassinetaouil 46:b1a9de66ecab 14555 #define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14556 #define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14557
Yassinetaouil 46:b1a9de66ecab 14558 /* Register: UARTE_BAUDRATE */
Yassinetaouil 46:b1a9de66ecab 14559 /* Description: Baud rate */
Yassinetaouil 46:b1a9de66ecab 14560
Yassinetaouil 46:b1a9de66ecab 14561 /* Bits 31..0 : Baud-rate */
Yassinetaouil 46:b1a9de66ecab 14562 #define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
Yassinetaouil 46:b1a9de66ecab 14563 #define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
Yassinetaouil 46:b1a9de66ecab 14564 #define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
Yassinetaouil 46:b1a9de66ecab 14565 #define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
Yassinetaouil 46:b1a9de66ecab 14566 #define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
Yassinetaouil 46:b1a9de66ecab 14567 #define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
Yassinetaouil 46:b1a9de66ecab 14568 #define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
Yassinetaouil 46:b1a9de66ecab 14569 #define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
Yassinetaouil 46:b1a9de66ecab 14570 #define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
Yassinetaouil 46:b1a9de66ecab 14571 #define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
Yassinetaouil 46:b1a9de66ecab 14572 #define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
Yassinetaouil 46:b1a9de66ecab 14573 #define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
Yassinetaouil 46:b1a9de66ecab 14574 #define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
Yassinetaouil 46:b1a9de66ecab 14575 #define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
Yassinetaouil 46:b1a9de66ecab 14576 #define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
Yassinetaouil 46:b1a9de66ecab 14577 #define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
Yassinetaouil 46:b1a9de66ecab 14578 #define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
Yassinetaouil 46:b1a9de66ecab 14579 #define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
Yassinetaouil 46:b1a9de66ecab 14580
Yassinetaouil 46:b1a9de66ecab 14581 /* Register: UARTE_RXD_PTR */
Yassinetaouil 46:b1a9de66ecab 14582 /* Description: Data pointer */
Yassinetaouil 46:b1a9de66ecab 14583
Yassinetaouil 46:b1a9de66ecab 14584 /* Bits 31..0 : Data pointer */
Yassinetaouil 46:b1a9de66ecab 14585 #define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 14586 #define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 14587
Yassinetaouil 46:b1a9de66ecab 14588 /* Register: UARTE_RXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 14589 /* Description: Maximum number of bytes in receive buffer */
Yassinetaouil 46:b1a9de66ecab 14590
Yassinetaouil 46:b1a9de66ecab 14591 /* Bits 7..0 : Maximum number of bytes in receive buffer */
Yassinetaouil 46:b1a9de66ecab 14592 #define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 14593 #define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 14594
Yassinetaouil 46:b1a9de66ecab 14595 /* Register: UARTE_RXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 14596 /* Description: Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 14597
Yassinetaouil 46:b1a9de66ecab 14598 /* Bits 7..0 : Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 14599 #define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 14600 #define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 14601
Yassinetaouil 46:b1a9de66ecab 14602 /* Register: UARTE_TXD_PTR */
Yassinetaouil 46:b1a9de66ecab 14603 /* Description: Data pointer */
Yassinetaouil 46:b1a9de66ecab 14604
Yassinetaouil 46:b1a9de66ecab 14605 /* Bits 31..0 : Data pointer */
Yassinetaouil 46:b1a9de66ecab 14606 #define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
Yassinetaouil 46:b1a9de66ecab 14607 #define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
Yassinetaouil 46:b1a9de66ecab 14608
Yassinetaouil 46:b1a9de66ecab 14609 /* Register: UARTE_TXD_MAXCNT */
Yassinetaouil 46:b1a9de66ecab 14610 /* Description: Maximum number of bytes in transmit buffer */
Yassinetaouil 46:b1a9de66ecab 14611
Yassinetaouil 46:b1a9de66ecab 14612 /* Bits 7..0 : Maximum number of bytes in transmit buffer */
Yassinetaouil 46:b1a9de66ecab 14613 #define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 14614 #define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
Yassinetaouil 46:b1a9de66ecab 14615
Yassinetaouil 46:b1a9de66ecab 14616 /* Register: UARTE_TXD_AMOUNT */
Yassinetaouil 46:b1a9de66ecab 14617 /* Description: Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 14618
Yassinetaouil 46:b1a9de66ecab 14619 /* Bits 7..0 : Number of bytes transferred in the last transaction */
Yassinetaouil 46:b1a9de66ecab 14620 #define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 14621 #define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
Yassinetaouil 46:b1a9de66ecab 14622
Yassinetaouil 46:b1a9de66ecab 14623 /* Register: UARTE_CONFIG */
Yassinetaouil 46:b1a9de66ecab 14624 /* Description: Configuration of parity and hardware flow control */
Yassinetaouil 46:b1a9de66ecab 14625
Yassinetaouil 46:b1a9de66ecab 14626 /* Bits 3..1 : Parity */
Yassinetaouil 46:b1a9de66ecab 14627 #define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 14628 #define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
Yassinetaouil 46:b1a9de66ecab 14629 #define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
Yassinetaouil 46:b1a9de66ecab 14630 #define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
Yassinetaouil 46:b1a9de66ecab 14631
Yassinetaouil 46:b1a9de66ecab 14632 /* Bit 0 : Hardware flow control */
Yassinetaouil 46:b1a9de66ecab 14633 #define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
Yassinetaouil 46:b1a9de66ecab 14634 #define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
Yassinetaouil 46:b1a9de66ecab 14635 #define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
Yassinetaouil 46:b1a9de66ecab 14636 #define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
Yassinetaouil 46:b1a9de66ecab 14637
Yassinetaouil 46:b1a9de66ecab 14638
Yassinetaouil 46:b1a9de66ecab 14639 /* Peripheral: UICR */
Yassinetaouil 46:b1a9de66ecab 14640 /* Description: User Information Configuration Registers */
Yassinetaouil 46:b1a9de66ecab 14641
Yassinetaouil 46:b1a9de66ecab 14642 /* Register: UICR_NRFFW */
Yassinetaouil 46:b1a9de66ecab 14643 /* Description: Description collection[0]: Reserved for Nordic firmware design */
Yassinetaouil 46:b1a9de66ecab 14644
Yassinetaouil 46:b1a9de66ecab 14645 /* Bits 31..0 : Reserved for Nordic firmware design */
Yassinetaouil 46:b1a9de66ecab 14646 #define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
Yassinetaouil 46:b1a9de66ecab 14647 #define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
Yassinetaouil 46:b1a9de66ecab 14648
Yassinetaouil 46:b1a9de66ecab 14649 /* Register: UICR_NRFHW */
Yassinetaouil 46:b1a9de66ecab 14650 /* Description: Description collection[0]: Reserved for Nordic hardware design */
Yassinetaouil 46:b1a9de66ecab 14651
Yassinetaouil 46:b1a9de66ecab 14652 /* Bits 31..0 : Reserved for Nordic hardware design */
Yassinetaouil 46:b1a9de66ecab 14653 #define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
Yassinetaouil 46:b1a9de66ecab 14654 #define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
Yassinetaouil 46:b1a9de66ecab 14655
Yassinetaouil 46:b1a9de66ecab 14656 /* Register: UICR_CUSTOMER */
Yassinetaouil 46:b1a9de66ecab 14657 /* Description: Description collection[0]: Reserved for customer */
Yassinetaouil 46:b1a9de66ecab 14658
Yassinetaouil 46:b1a9de66ecab 14659 /* Bits 31..0 : Reserved for customer */
Yassinetaouil 46:b1a9de66ecab 14660 #define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
Yassinetaouil 46:b1a9de66ecab 14661 #define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
Yassinetaouil 46:b1a9de66ecab 14662
Yassinetaouil 46:b1a9de66ecab 14663 /* Register: UICR_PSELRESET */
Yassinetaouil 46:b1a9de66ecab 14664 /* Description: Description collection[0]: Mapping of the nRESET function (see POWER chapter for details) */
Yassinetaouil 46:b1a9de66ecab 14665
Yassinetaouil 46:b1a9de66ecab 14666 /* Bit 31 : Connection */
Yassinetaouil 46:b1a9de66ecab 14667 #define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14668 #define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
Yassinetaouil 46:b1a9de66ecab 14669 #define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
Yassinetaouil 46:b1a9de66ecab 14670 #define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
Yassinetaouil 46:b1a9de66ecab 14671
Yassinetaouil 46:b1a9de66ecab 14672 /* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
Yassinetaouil 46:b1a9de66ecab 14673 #define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14674 #define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
Yassinetaouil 46:b1a9de66ecab 14675
Yassinetaouil 46:b1a9de66ecab 14676 /* Register: UICR_APPROTECT */
Yassinetaouil 46:b1a9de66ecab 14677 /* Description: Access Port protection */
Yassinetaouil 46:b1a9de66ecab 14678
Yassinetaouil 46:b1a9de66ecab 14679 /* Bits 7..0 : Enable or disable Access Port protection. */
Yassinetaouil 46:b1a9de66ecab 14680 #define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
Yassinetaouil 46:b1a9de66ecab 14681 #define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
Yassinetaouil 46:b1a9de66ecab 14682 #define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14683 #define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14684
Yassinetaouil 46:b1a9de66ecab 14685 /* Register: UICR_NFCPINS */
Yassinetaouil 46:b1a9de66ecab 14686 /* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
Yassinetaouil 46:b1a9de66ecab 14687
Yassinetaouil 46:b1a9de66ecab 14688 /* Bit 0 : Setting of pins dedicated to NFC functionality */
Yassinetaouil 46:b1a9de66ecab 14689 #define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
Yassinetaouil 46:b1a9de66ecab 14690 #define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
Yassinetaouil 46:b1a9de66ecab 14691 #define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
Yassinetaouil 46:b1a9de66ecab 14692 #define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
Yassinetaouil 46:b1a9de66ecab 14693
Yassinetaouil 46:b1a9de66ecab 14694
Yassinetaouil 46:b1a9de66ecab 14695 /* Peripheral: WDT */
Yassinetaouil 46:b1a9de66ecab 14696 /* Description: Watchdog Timer */
Yassinetaouil 46:b1a9de66ecab 14697
Yassinetaouil 46:b1a9de66ecab 14698 /* Register: WDT_INTENSET */
Yassinetaouil 46:b1a9de66ecab 14699 /* Description: Enable interrupt */
Yassinetaouil 46:b1a9de66ecab 14700
Yassinetaouil 46:b1a9de66ecab 14701 /* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
Yassinetaouil 46:b1a9de66ecab 14702 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
Yassinetaouil 46:b1a9de66ecab 14703 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
Yassinetaouil 46:b1a9de66ecab 14704 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14705 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14706 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
Yassinetaouil 46:b1a9de66ecab 14707
Yassinetaouil 46:b1a9de66ecab 14708 /* Register: WDT_INTENCLR */
Yassinetaouil 46:b1a9de66ecab 14709 /* Description: Disable interrupt */
Yassinetaouil 46:b1a9de66ecab 14710
Yassinetaouil 46:b1a9de66ecab 14711 /* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
Yassinetaouil 46:b1a9de66ecab 14712 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
Yassinetaouil 46:b1a9de66ecab 14713 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
Yassinetaouil 46:b1a9de66ecab 14714 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
Yassinetaouil 46:b1a9de66ecab 14715 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
Yassinetaouil 46:b1a9de66ecab 14716 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
Yassinetaouil 46:b1a9de66ecab 14717
Yassinetaouil 46:b1a9de66ecab 14718 /* Register: WDT_RUNSTATUS */
Yassinetaouil 46:b1a9de66ecab 14719 /* Description: Run status */
Yassinetaouil 46:b1a9de66ecab 14720
Yassinetaouil 46:b1a9de66ecab 14721 /* Bit 0 : Indicates whether or not the watchdog is running */
Yassinetaouil 46:b1a9de66ecab 14722 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
Yassinetaouil 46:b1a9de66ecab 14723 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
Yassinetaouil 46:b1a9de66ecab 14724 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
Yassinetaouil 46:b1a9de66ecab 14725 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
Yassinetaouil 46:b1a9de66ecab 14726
Yassinetaouil 46:b1a9de66ecab 14727 /* Register: WDT_REQSTATUS */
Yassinetaouil 46:b1a9de66ecab 14728 /* Description: Request status */
Yassinetaouil 46:b1a9de66ecab 14729
Yassinetaouil 46:b1a9de66ecab 14730 /* Bit 7 : Request status for RR[7] register */
Yassinetaouil 46:b1a9de66ecab 14731 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
Yassinetaouil 46:b1a9de66ecab 14732 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
Yassinetaouil 46:b1a9de66ecab 14733 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
Yassinetaouil 46:b1a9de66ecab 14734 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
Yassinetaouil 46:b1a9de66ecab 14735
Yassinetaouil 46:b1a9de66ecab 14736 /* Bit 6 : Request status for RR[6] register */
Yassinetaouil 46:b1a9de66ecab 14737 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
Yassinetaouil 46:b1a9de66ecab 14738 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
Yassinetaouil 46:b1a9de66ecab 14739 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
Yassinetaouil 46:b1a9de66ecab 14740 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
Yassinetaouil 46:b1a9de66ecab 14741
Yassinetaouil 46:b1a9de66ecab 14742 /* Bit 5 : Request status for RR[5] register */
Yassinetaouil 46:b1a9de66ecab 14743 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
Yassinetaouil 46:b1a9de66ecab 14744 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
Yassinetaouil 46:b1a9de66ecab 14745 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
Yassinetaouil 46:b1a9de66ecab 14746 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
Yassinetaouil 46:b1a9de66ecab 14747
Yassinetaouil 46:b1a9de66ecab 14748 /* Bit 4 : Request status for RR[4] register */
Yassinetaouil 46:b1a9de66ecab 14749 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
Yassinetaouil 46:b1a9de66ecab 14750 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
Yassinetaouil 46:b1a9de66ecab 14751 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
Yassinetaouil 46:b1a9de66ecab 14752 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
Yassinetaouil 46:b1a9de66ecab 14753
Yassinetaouil 46:b1a9de66ecab 14754 /* Bit 3 : Request status for RR[3] register */
Yassinetaouil 46:b1a9de66ecab 14755 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
Yassinetaouil 46:b1a9de66ecab 14756 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
Yassinetaouil 46:b1a9de66ecab 14757 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
Yassinetaouil 46:b1a9de66ecab 14758 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
Yassinetaouil 46:b1a9de66ecab 14759
Yassinetaouil 46:b1a9de66ecab 14760 /* Bit 2 : Request status for RR[2] register */
Yassinetaouil 46:b1a9de66ecab 14761 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
Yassinetaouil 46:b1a9de66ecab 14762 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
Yassinetaouil 46:b1a9de66ecab 14763 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
Yassinetaouil 46:b1a9de66ecab 14764 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
Yassinetaouil 46:b1a9de66ecab 14765
Yassinetaouil 46:b1a9de66ecab 14766 /* Bit 1 : Request status for RR[1] register */
Yassinetaouil 46:b1a9de66ecab 14767 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
Yassinetaouil 46:b1a9de66ecab 14768 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
Yassinetaouil 46:b1a9de66ecab 14769 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
Yassinetaouil 46:b1a9de66ecab 14770 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
Yassinetaouil 46:b1a9de66ecab 14771
Yassinetaouil 46:b1a9de66ecab 14772 /* Bit 0 : Request status for RR[0] register */
Yassinetaouil 46:b1a9de66ecab 14773 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
Yassinetaouil 46:b1a9de66ecab 14774 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
Yassinetaouil 46:b1a9de66ecab 14775 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
Yassinetaouil 46:b1a9de66ecab 14776 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
Yassinetaouil 46:b1a9de66ecab 14777
Yassinetaouil 46:b1a9de66ecab 14778 /* Register: WDT_CRV */
Yassinetaouil 46:b1a9de66ecab 14779 /* Description: Counter reload value */
Yassinetaouil 46:b1a9de66ecab 14780
Yassinetaouil 46:b1a9de66ecab 14781 /* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
Yassinetaouil 46:b1a9de66ecab 14782 #define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
Yassinetaouil 46:b1a9de66ecab 14783 #define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
Yassinetaouil 46:b1a9de66ecab 14784
Yassinetaouil 46:b1a9de66ecab 14785 /* Register: WDT_RREN */
Yassinetaouil 46:b1a9de66ecab 14786 /* Description: Enable register for reload request registers */
Yassinetaouil 46:b1a9de66ecab 14787
Yassinetaouil 46:b1a9de66ecab 14788 /* Bit 7 : Enable or disable RR[7] register */
Yassinetaouil 46:b1a9de66ecab 14789 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
Yassinetaouil 46:b1a9de66ecab 14790 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
Yassinetaouil 46:b1a9de66ecab 14791 #define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
Yassinetaouil 46:b1a9de66ecab 14792 #define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
Yassinetaouil 46:b1a9de66ecab 14793
Yassinetaouil 46:b1a9de66ecab 14794 /* Bit 6 : Enable or disable RR[6] register */
Yassinetaouil 46:b1a9de66ecab 14795 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
Yassinetaouil 46:b1a9de66ecab 14796 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
Yassinetaouil 46:b1a9de66ecab 14797 #define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
Yassinetaouil 46:b1a9de66ecab 14798 #define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
Yassinetaouil 46:b1a9de66ecab 14799
Yassinetaouil 46:b1a9de66ecab 14800 /* Bit 5 : Enable or disable RR[5] register */
Yassinetaouil 46:b1a9de66ecab 14801 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
Yassinetaouil 46:b1a9de66ecab 14802 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
Yassinetaouil 46:b1a9de66ecab 14803 #define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
Yassinetaouil 46:b1a9de66ecab 14804 #define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
Yassinetaouil 46:b1a9de66ecab 14805
Yassinetaouil 46:b1a9de66ecab 14806 /* Bit 4 : Enable or disable RR[4] register */
Yassinetaouil 46:b1a9de66ecab 14807 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
Yassinetaouil 46:b1a9de66ecab 14808 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
Yassinetaouil 46:b1a9de66ecab 14809 #define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
Yassinetaouil 46:b1a9de66ecab 14810 #define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
Yassinetaouil 46:b1a9de66ecab 14811
Yassinetaouil 46:b1a9de66ecab 14812 /* Bit 3 : Enable or disable RR[3] register */
Yassinetaouil 46:b1a9de66ecab 14813 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
Yassinetaouil 46:b1a9de66ecab 14814 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
Yassinetaouil 46:b1a9de66ecab 14815 #define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
Yassinetaouil 46:b1a9de66ecab 14816 #define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
Yassinetaouil 46:b1a9de66ecab 14817
Yassinetaouil 46:b1a9de66ecab 14818 /* Bit 2 : Enable or disable RR[2] register */
Yassinetaouil 46:b1a9de66ecab 14819 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
Yassinetaouil 46:b1a9de66ecab 14820 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
Yassinetaouil 46:b1a9de66ecab 14821 #define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
Yassinetaouil 46:b1a9de66ecab 14822 #define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
Yassinetaouil 46:b1a9de66ecab 14823
Yassinetaouil 46:b1a9de66ecab 14824 /* Bit 1 : Enable or disable RR[1] register */
Yassinetaouil 46:b1a9de66ecab 14825 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
Yassinetaouil 46:b1a9de66ecab 14826 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
Yassinetaouil 46:b1a9de66ecab 14827 #define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
Yassinetaouil 46:b1a9de66ecab 14828 #define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
Yassinetaouil 46:b1a9de66ecab 14829
Yassinetaouil 46:b1a9de66ecab 14830 /* Bit 0 : Enable or disable RR[0] register */
Yassinetaouil 46:b1a9de66ecab 14831 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
Yassinetaouil 46:b1a9de66ecab 14832 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
Yassinetaouil 46:b1a9de66ecab 14833 #define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
Yassinetaouil 46:b1a9de66ecab 14834 #define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
Yassinetaouil 46:b1a9de66ecab 14835
Yassinetaouil 46:b1a9de66ecab 14836 /* Register: WDT_CONFIG */
Yassinetaouil 46:b1a9de66ecab 14837 /* Description: Configuration register */
Yassinetaouil 46:b1a9de66ecab 14838
Yassinetaouil 46:b1a9de66ecab 14839 /* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
Yassinetaouil 46:b1a9de66ecab 14840 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
Yassinetaouil 46:b1a9de66ecab 14841 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
Yassinetaouil 46:b1a9de66ecab 14842 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
Yassinetaouil 46:b1a9de66ecab 14843 #define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
Yassinetaouil 46:b1a9de66ecab 14844
Yassinetaouil 46:b1a9de66ecab 14845 /* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
Yassinetaouil 46:b1a9de66ecab 14846 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
Yassinetaouil 46:b1a9de66ecab 14847 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
Yassinetaouil 46:b1a9de66ecab 14848 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
Yassinetaouil 46:b1a9de66ecab 14849 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
Yassinetaouil 46:b1a9de66ecab 14850
Yassinetaouil 46:b1a9de66ecab 14851 /* Register: WDT_RR */
Yassinetaouil 46:b1a9de66ecab 14852 /* Description: Description collection[0]: Reload request 0 */
Yassinetaouil 46:b1a9de66ecab 14853
Yassinetaouil 46:b1a9de66ecab 14854 /* Bits 31..0 : Reload request register */
Yassinetaouil 46:b1a9de66ecab 14855 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
Yassinetaouil 46:b1a9de66ecab 14856 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
Yassinetaouil 46:b1a9de66ecab 14857 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
Yassinetaouil 46:b1a9de66ecab 14858
Yassinetaouil 46:b1a9de66ecab 14859
Yassinetaouil 46:b1a9de66ecab 14860 /*lint --flb "Leave library region" */
Yassinetaouil 46:b1a9de66ecab 14861 #endif
Yassinetaouil 46:b1a9de66ecab 14862