nrf52-sdk - Nordic nrf51 sdk sources. Mirrored from https://g…

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Nordic nrf51 sdk sources. Mirrored from https://github.com/ARMmbed/nrf51-sdk.

Fork of nrf51-sdk by Nordic Semiconductor

source/nordic_sdk/components/device/nrf52.h@46:b1a9de66ecab, 2016-11-02 (annotated)

Committer:: Yassinetaouil
Date:: Wed Nov 02 15:29:13 2016 +0000
Revision:: 46:b1a9de66ecab

f1;

Who changed what in which revision?

User	Revision	Line number	New contents of line
Yassinetaouil	46:b1a9de66ecab	1
Yassinetaouil	46:b1a9de66ecab	2	/**************************************************************************************************//
Yassinetaouil	46:b1a9de66ecab	3	* @file nrf52.h
Yassinetaouil	46:b1a9de66ecab	4	*
Yassinetaouil	46:b1a9de66ecab	5	* @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
Yassinetaouil	46:b1a9de66ecab	6	* nrf52 from Nordic Semiconductor.
Yassinetaouil	46:b1a9de66ecab	7	*
Yassinetaouil	46:b1a9de66ecab	8	* @version V1
Yassinetaouil	46:b1a9de66ecab	9	* @date 23. February 2016
Yassinetaouil	46:b1a9de66ecab	10	*
Yassinetaouil	46:b1a9de66ecab	11	* @note Generated with SVDConv V2.81d
Yassinetaouil	46:b1a9de66ecab	12	* from CMSIS SVD File 'nrf52.svd' Version 1,
Yassinetaouil	46:b1a9de66ecab	13	*
Yassinetaouil	46:b1a9de66ecab	14	* @par Copyright (c) 2015, Nordic Semiconductor ASA
Yassinetaouil	46:b1a9de66ecab	15	* All rights reserved.
Yassinetaouil	46:b1a9de66ecab	16	*
Yassinetaouil	46:b1a9de66ecab	17	* Redistribution and use in source and binary forms, with or without
Yassinetaouil	46:b1a9de66ecab	18	* modification, are permitted provided that the following conditions are met:
Yassinetaouil	46:b1a9de66ecab	19	*
Yassinetaouil	46:b1a9de66ecab	20	* * Redistributions of source code must retain the above copyright notice, this
Yassinetaouil	46:b1a9de66ecab	21	* list of conditions and the following disclaimer.
Yassinetaouil	46:b1a9de66ecab	22	*
Yassinetaouil	46:b1a9de66ecab	23	* * Redistributions in binary form must reproduce the above copyright notice,
Yassinetaouil	46:b1a9de66ecab	24	* this list of conditions and the following disclaimer in the documentation
Yassinetaouil	46:b1a9de66ecab	25	* and/or other materials provided with the distribution.
Yassinetaouil	46:b1a9de66ecab	26	*
Yassinetaouil	46:b1a9de66ecab	27	* * Neither the name of Nordic Semiconductor ASA nor the names of its
Yassinetaouil	46:b1a9de66ecab	28	* contributors may be used to endorse or promote products derived from
Yassinetaouil	46:b1a9de66ecab	29	* this software without specific prior written permission.
Yassinetaouil	46:b1a9de66ecab	30	*
Yassinetaouil	46:b1a9de66ecab	31	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Yassinetaouil	46:b1a9de66ecab	32	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Yassinetaouil	46:b1a9de66ecab	33	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Yassinetaouil	46:b1a9de66ecab	34	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Yassinetaouil	46:b1a9de66ecab	35	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Yassinetaouil	46:b1a9de66ecab	36	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Yassinetaouil	46:b1a9de66ecab	37	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Yassinetaouil	46:b1a9de66ecab	38	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Yassinetaouil	46:b1a9de66ecab	39	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Yassinetaouil	46:b1a9de66ecab	40	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Yassinetaouil	46:b1a9de66ecab	41	*
Yassinetaouil	46:b1a9de66ecab	42	*
Yassinetaouil	46:b1a9de66ecab	43	*******************************************************************************************************/
Yassinetaouil	46:b1a9de66ecab	44
Yassinetaouil	46:b1a9de66ecab	45
Yassinetaouil	46:b1a9de66ecab	46
Yassinetaouil	46:b1a9de66ecab	47	/** @addtogroup Nordic Semiconductor
Yassinetaouil	46:b1a9de66ecab	48	* @{
Yassinetaouil	46:b1a9de66ecab	49	*/
Yassinetaouil	46:b1a9de66ecab	50
Yassinetaouil	46:b1a9de66ecab	51	/** @addtogroup nrf52
Yassinetaouil	46:b1a9de66ecab	52	* @{
Yassinetaouil	46:b1a9de66ecab	53	*/
Yassinetaouil	46:b1a9de66ecab	54
Yassinetaouil	46:b1a9de66ecab	55	#ifndef NRF52_H
Yassinetaouil	46:b1a9de66ecab	56	#define NRF52_H
Yassinetaouil	46:b1a9de66ecab	57
Yassinetaouil	46:b1a9de66ecab	58	#ifdef __cplusplus
Yassinetaouil	46:b1a9de66ecab	59	extern "C" {
Yassinetaouil	46:b1a9de66ecab	60	#endif
Yassinetaouil	46:b1a9de66ecab	61
Yassinetaouil	46:b1a9de66ecab	62
Yassinetaouil	46:b1a9de66ecab	63	/* ------------------------- Interrupt Number Definition ------------------------ */
Yassinetaouil	46:b1a9de66ecab	64
Yassinetaouil	46:b1a9de66ecab	65	typedef enum {
Yassinetaouil	46:b1a9de66ecab	66	/* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
Yassinetaouil	46:b1a9de66ecab	67	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
Yassinetaouil	46:b1a9de66ecab	68	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
Yassinetaouil	46:b1a9de66ecab	69	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
Yassinetaouil	46:b1a9de66ecab	70	MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
Yassinetaouil	46:b1a9de66ecab	71	and No Match */
Yassinetaouil	46:b1a9de66ecab	72	BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
Yassinetaouil	46:b1a9de66ecab	73	related Fault */
Yassinetaouil	46:b1a9de66ecab	74	UsageFault_IRQn = -10, /!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition /
Yassinetaouil	46:b1a9de66ecab	75	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
Yassinetaouil	46:b1a9de66ecab	76	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
Yassinetaouil	46:b1a9de66ecab	77	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
Yassinetaouil	46:b1a9de66ecab	78	SysTick_IRQn = -1, /!< 15 System Tick Timer /
Yassinetaouil	46:b1a9de66ecab	79	/* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */
Yassinetaouil	46:b1a9de66ecab	80	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
Yassinetaouil	46:b1a9de66ecab	81	RADIO_IRQn = 1, /!< 1 RADIO /
Yassinetaouil	46:b1a9de66ecab	82	UARTE0_UART0_IRQn = 2, /!< 2 UARTE0_UART0 /
Yassinetaouil	46:b1a9de66ecab	83	SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 /
Yassinetaouil	46:b1a9de66ecab	84	SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 /
Yassinetaouil	46:b1a9de66ecab	85	NFCT_IRQn = 5, /!< 5 NFCT /
Yassinetaouil	46:b1a9de66ecab	86	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
Yassinetaouil	46:b1a9de66ecab	87	SAADC_IRQn = 7, /!< 7 SAADC /
Yassinetaouil	46:b1a9de66ecab	88	TIMER0_IRQn = 8, /!< 8 TIMER0 /
Yassinetaouil	46:b1a9de66ecab	89	TIMER1_IRQn = 9, /!< 9 TIMER1 /
Yassinetaouil	46:b1a9de66ecab	90	TIMER2_IRQn = 10, /!< 10 TIMER2 /
Yassinetaouil	46:b1a9de66ecab	91	RTC0_IRQn = 11, /!< 11 RTC0 /
Yassinetaouil	46:b1a9de66ecab	92	TEMP_IRQn = 12, /!< 12 TEMP /
Yassinetaouil	46:b1a9de66ecab	93	RNG_IRQn = 13, /!< 13 RNG /
Yassinetaouil	46:b1a9de66ecab	94	ECB_IRQn = 14, /!< 14 ECB /
Yassinetaouil	46:b1a9de66ecab	95	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
Yassinetaouil	46:b1a9de66ecab	96	WDT_IRQn = 16, /!< 16 WDT /
Yassinetaouil	46:b1a9de66ecab	97	RTC1_IRQn = 17, /!< 17 RTC1 /
Yassinetaouil	46:b1a9de66ecab	98	QDEC_IRQn = 18, /!< 18 QDEC /
Yassinetaouil	46:b1a9de66ecab	99	COMP_LPCOMP_IRQn = 19, /!< 19 COMP_LPCOMP /
Yassinetaouil	46:b1a9de66ecab	100	SWI0_EGU0_IRQn = 20, /!< 20 SWI0_EGU0 /
Yassinetaouil	46:b1a9de66ecab	101	SWI1_EGU1_IRQn = 21, /!< 21 SWI1_EGU1 /
Yassinetaouil	46:b1a9de66ecab	102	SWI2_EGU2_IRQn = 22, /!< 22 SWI2_EGU2 /
Yassinetaouil	46:b1a9de66ecab	103	SWI3_EGU3_IRQn = 23, /!< 23 SWI3_EGU3 /
Yassinetaouil	46:b1a9de66ecab	104	SWI4_EGU4_IRQn = 24, /!< 24 SWI4_EGU4 /
Yassinetaouil	46:b1a9de66ecab	105	SWI5_EGU5_IRQn = 25, /!< 25 SWI5_EGU5 /
Yassinetaouil	46:b1a9de66ecab	106	TIMER3_IRQn = 26, /!< 26 TIMER3 /
Yassinetaouil	46:b1a9de66ecab	107	TIMER4_IRQn = 27, /!< 27 TIMER4 /
Yassinetaouil	46:b1a9de66ecab	108	PWM0_IRQn = 28, /!< 28 PWM0 /
Yassinetaouil	46:b1a9de66ecab	109	PDM_IRQn = 29, /!< 29 PDM /
Yassinetaouil	46:b1a9de66ecab	110	MWU_IRQn = 32, /!< 32 MWU /
Yassinetaouil	46:b1a9de66ecab	111	PWM1_IRQn = 33, /!< 33 PWM1 /
Yassinetaouil	46:b1a9de66ecab	112	PWM2_IRQn = 34, /!< 34 PWM2 /
Yassinetaouil	46:b1a9de66ecab	113	SPIM2_SPIS2_SPI2_IRQn = 35, /!< 35 SPIM2_SPIS2_SPI2 /
Yassinetaouil	46:b1a9de66ecab	114	RTC2_IRQn = 36, /!< 36 RTC2 /
Yassinetaouil	46:b1a9de66ecab	115	I2S_IRQn = 37, /!< 37 I2S /
Yassinetaouil	46:b1a9de66ecab	116	FPU_IRQn = 38 /!< 38 FPU /
Yassinetaouil	46:b1a9de66ecab	117	} IRQn_Type;
Yassinetaouil	46:b1a9de66ecab	118
Yassinetaouil	46:b1a9de66ecab	119
Yassinetaouil	46:b1a9de66ecab	120	/** @addtogroup Configuration_of_CMSIS
Yassinetaouil	46:b1a9de66ecab	121	* @{
Yassinetaouil	46:b1a9de66ecab	122	*/
Yassinetaouil	46:b1a9de66ecab	123
Yassinetaouil	46:b1a9de66ecab	124
Yassinetaouil	46:b1a9de66ecab	125	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	126	/* ================ Processor and Core Peripheral Section ================ */
Yassinetaouil	46:b1a9de66ecab	127	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	128
Yassinetaouil	46:b1a9de66ecab	129	/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
Yassinetaouil	46:b1a9de66ecab	130	#define __CM4_REV 0x0001 /!< Cortex-M4 Core Revision /
Yassinetaouil	46:b1a9de66ecab	131	#define __MPU_PRESENT 1 /!< MPU present or not /
Yassinetaouil	46:b1a9de66ecab	132	#define __NVIC_PRIO_BITS 3 /!< Number of Bits used for Priority Levels /
Yassinetaouil	46:b1a9de66ecab	133	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Yassinetaouil	46:b1a9de66ecab	134	#define __FPU_PRESENT 1 /!< FPU present or not /
Yassinetaouil	46:b1a9de66ecab	135	/** @} / / End of group Configuration_of_CMSIS */
Yassinetaouil	46:b1a9de66ecab	136
Yassinetaouil	46:b1a9de66ecab	137	#include "core_cm4.h" /!< Cortex-M4 processor and core peripherals /
Yassinetaouil	46:b1a9de66ecab	138	#include "system_nrf52.h" /!< nrf52 System /
Yassinetaouil	46:b1a9de66ecab	139
Yassinetaouil	46:b1a9de66ecab	140
Yassinetaouil	46:b1a9de66ecab	141	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	142	/* ================ Device Specific Peripheral Section ================ */
Yassinetaouil	46:b1a9de66ecab	143	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	144
Yassinetaouil	46:b1a9de66ecab	145
Yassinetaouil	46:b1a9de66ecab	146	/** @addtogroup Device_Peripheral_Registers
Yassinetaouil	46:b1a9de66ecab	147	* @{
Yassinetaouil	46:b1a9de66ecab	148	*/
Yassinetaouil	46:b1a9de66ecab	149
Yassinetaouil	46:b1a9de66ecab	150
Yassinetaouil	46:b1a9de66ecab	151	/* ------------------- Start of section using anonymous unions ------------------ */
Yassinetaouil	46:b1a9de66ecab	152	#if defined(__CC_ARM)
Yassinetaouil	46:b1a9de66ecab	153	#pragma push
Yassinetaouil	46:b1a9de66ecab	154	#pragma anon_unions
Yassinetaouil	46:b1a9de66ecab	155	#elif defined(__ICCARM__)
Yassinetaouil	46:b1a9de66ecab	156	#pragma language=extended
Yassinetaouil	46:b1a9de66ecab	157	#elif defined(__GNUC__)
Yassinetaouil	46:b1a9de66ecab	158	/* anonymous unions are enabled by default */
Yassinetaouil	46:b1a9de66ecab	159	#elif defined(__TMS470__)
Yassinetaouil	46:b1a9de66ecab	160	/* anonymous unions are enabled by default */
Yassinetaouil	46:b1a9de66ecab	161	#elif defined(__TASKING__)
Yassinetaouil	46:b1a9de66ecab	162	#pragma warning 586
Yassinetaouil	46:b1a9de66ecab	163	#else
Yassinetaouil	46:b1a9de66ecab	164	#warning Not supported compiler type
Yassinetaouil	46:b1a9de66ecab	165	#endif
Yassinetaouil	46:b1a9de66ecab	166
Yassinetaouil	46:b1a9de66ecab	167
Yassinetaouil	46:b1a9de66ecab	168	typedef struct {
Yassinetaouil	46:b1a9de66ecab	169	__I uint32_t PART; /!< Part code /
Yassinetaouil	46:b1a9de66ecab	170	__I uint32_t VARIANT; /!< Part Variant, Hardware version and Production configuration /
Yassinetaouil	46:b1a9de66ecab	171	__I uint32_t PACKAGE; /!< Package option /
Yassinetaouil	46:b1a9de66ecab	172	__I uint32_t RAM; /!< RAM variant /
Yassinetaouil	46:b1a9de66ecab	173	__I uint32_t FLASH; /!< Flash variant /
Yassinetaouil	46:b1a9de66ecab	174	__IO uint32_t UNUSED0[3]; /!< Description collection[0]: Unspecified /
Yassinetaouil	46:b1a9de66ecab	175	} FICR_INFO_Type;
Yassinetaouil	46:b1a9de66ecab	176
Yassinetaouil	46:b1a9de66ecab	177	typedef struct {
Yassinetaouil	46:b1a9de66ecab	178	__I uint32_t A0; /!< Slope definition A0. /
Yassinetaouil	46:b1a9de66ecab	179	__I uint32_t A1; /!< Slope definition A1. /
Yassinetaouil	46:b1a9de66ecab	180	__I uint32_t A2; /!< Slope definition A2. /
Yassinetaouil	46:b1a9de66ecab	181	__I uint32_t A3; /!< Slope definition A3. /
Yassinetaouil	46:b1a9de66ecab	182	__I uint32_t A4; /!< Slope definition A4. /
Yassinetaouil	46:b1a9de66ecab	183	__I uint32_t A5; /!< Slope definition A5. /
Yassinetaouil	46:b1a9de66ecab	184	__I uint32_t B0; /!< y-intercept B0. /
Yassinetaouil	46:b1a9de66ecab	185	__I uint32_t B1; /!< y-intercept B1. /
Yassinetaouil	46:b1a9de66ecab	186	__I uint32_t B2; /!< y-intercept B2. /
Yassinetaouil	46:b1a9de66ecab	187	__I uint32_t B3; /!< y-intercept B3. /
Yassinetaouil	46:b1a9de66ecab	188	__I uint32_t B4; /!< y-intercept B4. /
Yassinetaouil	46:b1a9de66ecab	189	__I uint32_t B5; /!< y-intercept B5. /
Yassinetaouil	46:b1a9de66ecab	190	__I uint32_t T0; /!< Segment end T0. /
Yassinetaouil	46:b1a9de66ecab	191	__I uint32_t T1; /!< Segment end T1. /
Yassinetaouil	46:b1a9de66ecab	192	__I uint32_t T2; /!< Segment end T2. /
Yassinetaouil	46:b1a9de66ecab	193	__I uint32_t T3; /!< Segment end T3. /
Yassinetaouil	46:b1a9de66ecab	194	__I uint32_t T4; /!< Segment end T4. /
Yassinetaouil	46:b1a9de66ecab	195	} FICR_TEMP_Type;
Yassinetaouil	46:b1a9de66ecab	196
Yassinetaouil	46:b1a9de66ecab	197	typedef struct {
Yassinetaouil	46:b1a9de66ecab	198	__I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to
Yassinetaouil	46:b1a9de66ecab	199	populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Yassinetaouil	46:b1a9de66ecab	200	__I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to
Yassinetaouil	46:b1a9de66ecab	201	populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Yassinetaouil	46:b1a9de66ecab	202	__I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to
Yassinetaouil	46:b1a9de66ecab	203	populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Yassinetaouil	46:b1a9de66ecab	204	__I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to
Yassinetaouil	46:b1a9de66ecab	205	populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Yassinetaouil	46:b1a9de66ecab	206	} FICR_NFC_Type;
Yassinetaouil	46:b1a9de66ecab	207
Yassinetaouil	46:b1a9de66ecab	208	typedef struct {
Yassinetaouil	46:b1a9de66ecab	209	__IO uint32_t POWER; /!< Description cluster[0]: RAM0 power control register /
Yassinetaouil	46:b1a9de66ecab	210	__O uint32_t POWERSET; /!< Description cluster[0]: RAM0 power control set register /
Yassinetaouil	46:b1a9de66ecab	211	__O uint32_t POWERCLR; /!< Description cluster[0]: RAM0 power control clear register /
Yassinetaouil	46:b1a9de66ecab	212	__I uint32_t RESERVED0;
Yassinetaouil	46:b1a9de66ecab	213	} POWER_RAM_Type;
Yassinetaouil	46:b1a9de66ecab	214
Yassinetaouil	46:b1a9de66ecab	215	typedef struct {
Yassinetaouil	46:b1a9de66ecab	216	__IO uint32_t CPU0; /!< AHB bus master priority register for CPU0 /
Yassinetaouil	46:b1a9de66ecab	217	__IO uint32_t SPIS1; /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and
Yassinetaouil	46:b1a9de66ecab	218	TWIS1 */
Yassinetaouil	46:b1a9de66ecab	219	__IO uint32_t RADIO; /!< AHB bus master priority register for RADIO /
Yassinetaouil	46:b1a9de66ecab	220	__IO uint32_t ECB; /!< AHB bus master priority register for ECB /
Yassinetaouil	46:b1a9de66ecab	221	__IO uint32_t CCM; /!< AHB bus master priority register for CCM /
Yassinetaouil	46:b1a9de66ecab	222	__IO uint32_t AAR; /!< AHB bus master priority register for AAR /
Yassinetaouil	46:b1a9de66ecab	223	__IO uint32_t SAADC; /!< AHB bus master priority register for SAADC /
Yassinetaouil	46:b1a9de66ecab	224	__IO uint32_t UARTE; /!< AHB bus master priority register for UARTE /
Yassinetaouil	46:b1a9de66ecab	225	__IO uint32_t SERIAL0; /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and
Yassinetaouil	46:b1a9de66ecab	226	TWIS0 */
Yassinetaouil	46:b1a9de66ecab	227	__IO uint32_t SERIAL2; /!< AHB bus master priority register for SPIM2 and SPIS2 /
Yassinetaouil	46:b1a9de66ecab	228	__IO uint32_t NFCT; /!< AHB bus master priority register for NFCT /
Yassinetaouil	46:b1a9de66ecab	229	__IO uint32_t I2S; /!< AHB bus master priority register for I2S /
Yassinetaouil	46:b1a9de66ecab	230	__IO uint32_t PDM; /!< AHB bus master priority register for PDM /
Yassinetaouil	46:b1a9de66ecab	231	__IO uint32_t PWM; /!< AHB bus master priority register for PWM0, PWM1 and PWM2 /
Yassinetaouil	46:b1a9de66ecab	232	} AMLI_RAMPRI_Type;
Yassinetaouil	46:b1a9de66ecab	233
Yassinetaouil	46:b1a9de66ecab	234	typedef struct {
Yassinetaouil	46:b1a9de66ecab	235	__IO uint32_t RTS; /!< Pin select for RTS signal /
Yassinetaouil	46:b1a9de66ecab	236	__IO uint32_t TXD; /!< Pin select for TXD signal /
Yassinetaouil	46:b1a9de66ecab	237	__IO uint32_t CTS; /!< Pin select for CTS signal /
Yassinetaouil	46:b1a9de66ecab	238	__IO uint32_t RXD; /!< Pin select for RXD signal /
Yassinetaouil	46:b1a9de66ecab	239	} UARTE_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	240
Yassinetaouil	46:b1a9de66ecab	241	typedef struct {
Yassinetaouil	46:b1a9de66ecab	242	__IO uint32_t PTR; /!< Data pointer /
Yassinetaouil	46:b1a9de66ecab	243	__IO uint32_t MAXCNT; /!< Maximum number of bytes in receive buffer /
Yassinetaouil	46:b1a9de66ecab	244	__I uint32_t AMOUNT; /!< Number of bytes transferred in the last transaction /
Yassinetaouil	46:b1a9de66ecab	245	} UARTE_RXD_Type;
Yassinetaouil	46:b1a9de66ecab	246
Yassinetaouil	46:b1a9de66ecab	247	typedef struct {
Yassinetaouil	46:b1a9de66ecab	248	__IO uint32_t PTR; /!< Data pointer /
Yassinetaouil	46:b1a9de66ecab	249	__IO uint32_t MAXCNT; /!< Maximum number of bytes in transmit buffer /
Yassinetaouil	46:b1a9de66ecab	250	__I uint32_t AMOUNT; /!< Number of bytes transferred in the last transaction /
Yassinetaouil	46:b1a9de66ecab	251	} UARTE_TXD_Type;
Yassinetaouil	46:b1a9de66ecab	252
Yassinetaouil	46:b1a9de66ecab	253	typedef struct {
Yassinetaouil	46:b1a9de66ecab	254	__IO uint32_t SCK; /!< Pin select for SCK /
Yassinetaouil	46:b1a9de66ecab	255	__IO uint32_t MOSI; /!< Pin select for MOSI signal /
Yassinetaouil	46:b1a9de66ecab	256	__IO uint32_t MISO; /!< Pin select for MISO signal /
Yassinetaouil	46:b1a9de66ecab	257	} SPIM_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	258
Yassinetaouil	46:b1a9de66ecab	259	typedef struct {
Yassinetaouil	46:b1a9de66ecab	260	__IO uint32_t PTR; /!< Data pointer /
Yassinetaouil	46:b1a9de66ecab	261	__IO uint32_t MAXCNT; /!< Maximum number of bytes in receive buffer /
Yassinetaouil	46:b1a9de66ecab	262	__I uint32_t AMOUNT; /!< Number of bytes transferred in the last transaction /
Yassinetaouil	46:b1a9de66ecab	263	__IO uint32_t LIST; /!< EasyDMA list type /
Yassinetaouil	46:b1a9de66ecab	264	} SPIM_RXD_Type;
Yassinetaouil	46:b1a9de66ecab	265
Yassinetaouil	46:b1a9de66ecab	266	typedef struct {
Yassinetaouil	46:b1a9de66ecab	267	__IO uint32_t PTR; /!< Data pointer /
Yassinetaouil	46:b1a9de66ecab	268	__IO uint32_t MAXCNT; /!< Maximum number of bytes in transmit buffer /
Yassinetaouil	46:b1a9de66ecab	269	__I uint32_t AMOUNT; /!< Number of bytes transferred in the last transaction /
Yassinetaouil	46:b1a9de66ecab	270	__IO uint32_t LIST; /!< EasyDMA list type /
Yassinetaouil	46:b1a9de66ecab	271	} SPIM_TXD_Type;
Yassinetaouil	46:b1a9de66ecab	272
Yassinetaouil	46:b1a9de66ecab	273	typedef struct {
Yassinetaouil	46:b1a9de66ecab	274	__IO uint32_t SCK; /!< Pin select for SCK /
Yassinetaouil	46:b1a9de66ecab	275	__IO uint32_t MISO; /!< Pin select for MISO signal /
Yassinetaouil	46:b1a9de66ecab	276	__IO uint32_t MOSI; /!< Pin select for MOSI signal /
Yassinetaouil	46:b1a9de66ecab	277	__IO uint32_t CSN; /!< Pin select for CSN signal /
Yassinetaouil	46:b1a9de66ecab	278	} SPIS_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	279
Yassinetaouil	46:b1a9de66ecab	280	typedef struct {
Yassinetaouil	46:b1a9de66ecab	281	__IO uint32_t PTR; /!< RXD data pointer /
Yassinetaouil	46:b1a9de66ecab	282	__IO uint32_t MAXCNT; /!< Maximum number of bytes in receive buffer /
Yassinetaouil	46:b1a9de66ecab	283	__I uint32_t AMOUNT; /!< Number of bytes received in last granted transaction /
Yassinetaouil	46:b1a9de66ecab	284	} SPIS_RXD_Type;
Yassinetaouil	46:b1a9de66ecab	285
Yassinetaouil	46:b1a9de66ecab	286	typedef struct {
Yassinetaouil	46:b1a9de66ecab	287	__IO uint32_t PTR; /!< TXD data pointer /
Yassinetaouil	46:b1a9de66ecab	288	__IO uint32_t MAXCNT; /!< Maximum number of bytes in transmit buffer /
Yassinetaouil	46:b1a9de66ecab	289	__I uint32_t AMOUNT; /!< Number of bytes transmitted in last granted transaction /
Yassinetaouil	46:b1a9de66ecab	290	} SPIS_TXD_Type;
Yassinetaouil	46:b1a9de66ecab	291
Yassinetaouil	46:b1a9de66ecab	292	typedef struct {
Yassinetaouil	46:b1a9de66ecab	293	__IO uint32_t SCL; /!< Pin select for SCL signal /
Yassinetaouil	46:b1a9de66ecab	294	__IO uint32_t SDA; /!< Pin select for SDA signal /
Yassinetaouil	46:b1a9de66ecab	295	} TWIM_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	296
Yassinetaouil	46:b1a9de66ecab	297	typedef struct {
Yassinetaouil	46:b1a9de66ecab	298	__IO uint32_t PTR; /!< Data pointer /
Yassinetaouil	46:b1a9de66ecab	299	__IO uint32_t MAXCNT; /!< Maximum number of bytes in receive buffer /
Yassinetaouil	46:b1a9de66ecab	300	__I uint32_t AMOUNT; /!< Number of bytes transferred in the last transaction /
Yassinetaouil	46:b1a9de66ecab	301	__IO uint32_t LIST; /!< EasyDMA list type /
Yassinetaouil	46:b1a9de66ecab	302	} TWIM_RXD_Type;
Yassinetaouil	46:b1a9de66ecab	303
Yassinetaouil	46:b1a9de66ecab	304	typedef struct {
Yassinetaouil	46:b1a9de66ecab	305	__IO uint32_t PTR; /!< Data pointer /
Yassinetaouil	46:b1a9de66ecab	306	__IO uint32_t MAXCNT; /!< Maximum number of bytes in transmit buffer /
Yassinetaouil	46:b1a9de66ecab	307	__I uint32_t AMOUNT; /!< Number of bytes transferred in the last transaction /
Yassinetaouil	46:b1a9de66ecab	308	__IO uint32_t LIST; /!< EasyDMA list type /
Yassinetaouil	46:b1a9de66ecab	309	} TWIM_TXD_Type;
Yassinetaouil	46:b1a9de66ecab	310
Yassinetaouil	46:b1a9de66ecab	311	typedef struct {
Yassinetaouil	46:b1a9de66ecab	312	__IO uint32_t SCL; /!< Pin select for SCL signal /
Yassinetaouil	46:b1a9de66ecab	313	__IO uint32_t SDA; /!< Pin select for SDA signal /
Yassinetaouil	46:b1a9de66ecab	314	} TWIS_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	315
Yassinetaouil	46:b1a9de66ecab	316	typedef struct {
Yassinetaouil	46:b1a9de66ecab	317	__IO uint32_t PTR; /!< RXD Data pointer /
Yassinetaouil	46:b1a9de66ecab	318	__IO uint32_t MAXCNT; /!< Maximum number of bytes in RXD buffer /
Yassinetaouil	46:b1a9de66ecab	319	__I uint32_t AMOUNT; /!< Number of bytes transferred in the last RXD transaction /
Yassinetaouil	46:b1a9de66ecab	320	} TWIS_RXD_Type;
Yassinetaouil	46:b1a9de66ecab	321
Yassinetaouil	46:b1a9de66ecab	322	typedef struct {
Yassinetaouil	46:b1a9de66ecab	323	__IO uint32_t PTR; /!< TXD Data pointer /
Yassinetaouil	46:b1a9de66ecab	324	__IO uint32_t MAXCNT; /!< Maximum number of bytes in TXD buffer /
Yassinetaouil	46:b1a9de66ecab	325	__I uint32_t AMOUNT; /!< Number of bytes transferred in the last TXD transaction /
Yassinetaouil	46:b1a9de66ecab	326	} TWIS_TXD_Type;
Yassinetaouil	46:b1a9de66ecab	327
Yassinetaouil	46:b1a9de66ecab	328	typedef struct {
Yassinetaouil	46:b1a9de66ecab	329	__IO uint32_t SCK; /!< Pin select for SCK /
Yassinetaouil	46:b1a9de66ecab	330	__IO uint32_t MOSI; /!< Pin select for MOSI /
Yassinetaouil	46:b1a9de66ecab	331	__IO uint32_t MISO; /!< Pin select for MISO /
Yassinetaouil	46:b1a9de66ecab	332	} SPI_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	333
Yassinetaouil	46:b1a9de66ecab	334	typedef struct {
Yassinetaouil	46:b1a9de66ecab	335	__IO uint32_t RX; /!< Result of last incoming frames /
Yassinetaouil	46:b1a9de66ecab	336	} NFCT_FRAMESTATUS_Type;
Yassinetaouil	46:b1a9de66ecab	337
Yassinetaouil	46:b1a9de66ecab	338	typedef struct {
Yassinetaouil	46:b1a9de66ecab	339	__IO uint32_t FRAMECONFIG; /!< Configuration of outgoing frames /
Yassinetaouil	46:b1a9de66ecab	340	__IO uint32_t AMOUNT; /!< Size of outgoing frame /
Yassinetaouil	46:b1a9de66ecab	341	} NFCT_TXD_Type;
Yassinetaouil	46:b1a9de66ecab	342
Yassinetaouil	46:b1a9de66ecab	343	typedef struct {
Yassinetaouil	46:b1a9de66ecab	344	__IO uint32_t FRAMECONFIG; /!< Configuration of incoming frames /
Yassinetaouil	46:b1a9de66ecab	345	__I uint32_t AMOUNT; /!< Size of last incoming frame /
Yassinetaouil	46:b1a9de66ecab	346	} NFCT_RXD_Type;
Yassinetaouil	46:b1a9de66ecab	347
Yassinetaouil	46:b1a9de66ecab	348	typedef struct {
Yassinetaouil	46:b1a9de66ecab	349	__IO uint32_t LIMITH; /!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH /
Yassinetaouil	46:b1a9de66ecab	350	__IO uint32_t LIMITL; /!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW /
Yassinetaouil	46:b1a9de66ecab	351	} SAADC_EVENTS_CH_Type;
Yassinetaouil	46:b1a9de66ecab	352
Yassinetaouil	46:b1a9de66ecab	353	typedef struct {
Yassinetaouil	46:b1a9de66ecab	354	__IO uint32_t PSELP; /!< Description cluster[0]: Input positive pin selection for CH[0] /
Yassinetaouil	46:b1a9de66ecab	355	__IO uint32_t PSELN; /!< Description cluster[0]: Input negative pin selection for CH[0] /
Yassinetaouil	46:b1a9de66ecab	356	__IO uint32_t CONFIG; /!< Description cluster[0]: Input configuration for CH[0] /
Yassinetaouil	46:b1a9de66ecab	357	__IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring
Yassinetaouil	46:b1a9de66ecab	358	a channel */
Yassinetaouil	46:b1a9de66ecab	359	} SAADC_CH_Type;
Yassinetaouil	46:b1a9de66ecab	360
Yassinetaouil	46:b1a9de66ecab	361	typedef struct {
Yassinetaouil	46:b1a9de66ecab	362	__IO uint32_t PTR; /!< Data pointer /
Yassinetaouil	46:b1a9de66ecab	363	__IO uint32_t MAXCNT; /!< Maximum number of buffer words to transfer /
Yassinetaouil	46:b1a9de66ecab	364	__I uint32_t AMOUNT; /!< Number of buffer words transferred since last START /
Yassinetaouil	46:b1a9de66ecab	365	} SAADC_RESULT_Type;
Yassinetaouil	46:b1a9de66ecab	366
Yassinetaouil	46:b1a9de66ecab	367	typedef struct {
Yassinetaouil	46:b1a9de66ecab	368	__IO uint32_t LED; /!< Pin select for LED signal /
Yassinetaouil	46:b1a9de66ecab	369	__IO uint32_t A; /!< Pin select for A signal /
Yassinetaouil	46:b1a9de66ecab	370	__IO uint32_t B; /!< Pin select for B signal /
Yassinetaouil	46:b1a9de66ecab	371	} QDEC_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	372
Yassinetaouil	46:b1a9de66ecab	373	typedef struct {
Yassinetaouil	46:b1a9de66ecab	374	__IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence
Yassinetaouil	46:b1a9de66ecab	375	A */
Yassinetaouil	46:b1a9de66ecab	376	__IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence
Yassinetaouil	46:b1a9de66ecab	377	A */
Yassinetaouil	46:b1a9de66ecab	378	__IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between
Yassinetaouil	46:b1a9de66ecab	379	samples loaded to compare register (load every CNT+1 PWM periods) */
Yassinetaouil	46:b1a9de66ecab	380	__IO uint32_t ENDDELAY; /!< Description cluster[0]: Time added after the sequence /
Yassinetaouil	46:b1a9de66ecab	381	__I uint32_t RESERVED1[4];
Yassinetaouil	46:b1a9de66ecab	382	} PWM_SEQ_Type;
Yassinetaouil	46:b1a9de66ecab	383
Yassinetaouil	46:b1a9de66ecab	384	typedef struct {
Yassinetaouil	46:b1a9de66ecab	385	__IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel
Yassinetaouil	46:b1a9de66ecab	386	0 */
Yassinetaouil	46:b1a9de66ecab	387	} PWM_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	388
Yassinetaouil	46:b1a9de66ecab	389	typedef struct {
Yassinetaouil	46:b1a9de66ecab	390	__IO uint32_t CLK; /!< Pin number configuration for PDM CLK signal /
Yassinetaouil	46:b1a9de66ecab	391	__IO uint32_t DIN; /!< Pin number configuration for PDM DIN signal /
Yassinetaouil	46:b1a9de66ecab	392	} PDM_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	393
Yassinetaouil	46:b1a9de66ecab	394	typedef struct {
Yassinetaouil	46:b1a9de66ecab	395	__IO uint32_t PTR; /!< RAM address pointer to write samples to with EasyDMA /
Yassinetaouil	46:b1a9de66ecab	396	__IO uint32_t MAXCNT; /!< Number of samples to allocate memory for in EasyDMA mode /
Yassinetaouil	46:b1a9de66ecab	397	} PDM_SAMPLE_Type;
Yassinetaouil	46:b1a9de66ecab	398
Yassinetaouil	46:b1a9de66ecab	399	typedef struct {
Yassinetaouil	46:b1a9de66ecab	400	__O uint32_t EN; /!< Description cluster[0]: Enable channel group 0 /
Yassinetaouil	46:b1a9de66ecab	401	__O uint32_t DIS; /!< Description cluster[0]: Disable channel group 0 /
Yassinetaouil	46:b1a9de66ecab	402	} PPI_TASKS_CHG_Type;
Yassinetaouil	46:b1a9de66ecab	403
Yassinetaouil	46:b1a9de66ecab	404	typedef struct {
Yassinetaouil	46:b1a9de66ecab	405	__IO uint32_t EEP; /!< Description cluster[0]: Channel 0 event end-point /
Yassinetaouil	46:b1a9de66ecab	406	__IO uint32_t TEP; /!< Description cluster[0]: Channel 0 task end-point /
Yassinetaouil	46:b1a9de66ecab	407	} PPI_CH_Type;
Yassinetaouil	46:b1a9de66ecab	408
Yassinetaouil	46:b1a9de66ecab	409	typedef struct {
Yassinetaouil	46:b1a9de66ecab	410	__IO uint32_t TEP; /!< Description cluster[0]: Channel 0 task end-point /
Yassinetaouil	46:b1a9de66ecab	411	} PPI_FORK_Type;
Yassinetaouil	46:b1a9de66ecab	412
Yassinetaouil	46:b1a9de66ecab	413	typedef struct {
Yassinetaouil	46:b1a9de66ecab	414	__IO uint32_t WA; /!< Description cluster[0]: Write access to region 0 detected /
Yassinetaouil	46:b1a9de66ecab	415	__IO uint32_t RA; /!< Description cluster[0]: Read access to region 0 detected /
Yassinetaouil	46:b1a9de66ecab	416	} MWU_EVENTS_REGION_Type;
Yassinetaouil	46:b1a9de66ecab	417
Yassinetaouil	46:b1a9de66ecab	418	typedef struct {
Yassinetaouil	46:b1a9de66ecab	419	__IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0
Yassinetaouil	46:b1a9de66ecab	420	detected */
Yassinetaouil	46:b1a9de66ecab	421	__IO uint32_t RA; /!< Description cluster[0]: Read access to peripheral region 0 detected /
Yassinetaouil	46:b1a9de66ecab	422	} MWU_EVENTS_PREGION_Type;
Yassinetaouil	46:b1a9de66ecab	423
Yassinetaouil	46:b1a9de66ecab	424	typedef struct {
Yassinetaouil	46:b1a9de66ecab	425	__IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region
Yassinetaouil	46:b1a9de66ecab	426	0, write access detected while corresponding subregion was enabled
Yassinetaouil	46:b1a9de66ecab	427	for watching */
Yassinetaouil	46:b1a9de66ecab	428	__IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region
Yassinetaouil	46:b1a9de66ecab	429	0, read access detected while corresponding subregion was enabled
Yassinetaouil	46:b1a9de66ecab	430	for watching */
Yassinetaouil	46:b1a9de66ecab	431	} MWU_PERREGION_Type;
Yassinetaouil	46:b1a9de66ecab	432
Yassinetaouil	46:b1a9de66ecab	433	typedef struct {
Yassinetaouil	46:b1a9de66ecab	434	__IO uint32_t START; /!< Description cluster[0]: Start address for region 0 /
Yassinetaouil	46:b1a9de66ecab	435	__IO uint32_t END; /!< Description cluster[0]: End address of region 0 /
Yassinetaouil	46:b1a9de66ecab	436	__I uint32_t RESERVED2[2];
Yassinetaouil	46:b1a9de66ecab	437	} MWU_REGION_Type;
Yassinetaouil	46:b1a9de66ecab	438
Yassinetaouil	46:b1a9de66ecab	439	typedef struct {
Yassinetaouil	46:b1a9de66ecab	440	__I uint32_t START; /!< Description cluster[0]: Reserved for future use /
Yassinetaouil	46:b1a9de66ecab	441	__I uint32_t END; /!< Description cluster[0]: Reserved for future use /
Yassinetaouil	46:b1a9de66ecab	442	__IO uint32_t SUBS; /!< Description cluster[0]: Subregions of region 0 /
Yassinetaouil	46:b1a9de66ecab	443	__I uint32_t RESERVED3;
Yassinetaouil	46:b1a9de66ecab	444	} MWU_PREGION_Type;
Yassinetaouil	46:b1a9de66ecab	445
Yassinetaouil	46:b1a9de66ecab	446	typedef struct {
Yassinetaouil	46:b1a9de66ecab	447	__IO uint32_t MODE; /!< I2S mode. /
Yassinetaouil	46:b1a9de66ecab	448	__IO uint32_t RXEN; /!< Reception (RX) enable. /
Yassinetaouil	46:b1a9de66ecab	449	__IO uint32_t TXEN; /!< Transmission (TX) enable. /
Yassinetaouil	46:b1a9de66ecab	450	__IO uint32_t MCKEN; /!< Master clock generator enable. /
Yassinetaouil	46:b1a9de66ecab	451	__IO uint32_t MCKFREQ; /!< Master clock generator frequency. /
Yassinetaouil	46:b1a9de66ecab	452	__IO uint32_t RATIO; /!< MCK / LRCK ratio. /
Yassinetaouil	46:b1a9de66ecab	453	__IO uint32_t SWIDTH; /!< Sample width. /
Yassinetaouil	46:b1a9de66ecab	454	__IO uint32_t ALIGN; /!< Alignment of sample within a frame. /
Yassinetaouil	46:b1a9de66ecab	455	__IO uint32_t FORMAT; /!< Frame format. /
Yassinetaouil	46:b1a9de66ecab	456	__IO uint32_t CHANNELS; /!< Enable channels. /
Yassinetaouil	46:b1a9de66ecab	457	} I2S_CONFIG_Type;
Yassinetaouil	46:b1a9de66ecab	458
Yassinetaouil	46:b1a9de66ecab	459	typedef struct {
Yassinetaouil	46:b1a9de66ecab	460	__IO uint32_t PTR; /!< Receive buffer RAM start address. /
Yassinetaouil	46:b1a9de66ecab	461	} I2S_RXD_Type;
Yassinetaouil	46:b1a9de66ecab	462
Yassinetaouil	46:b1a9de66ecab	463	typedef struct {
Yassinetaouil	46:b1a9de66ecab	464	__IO uint32_t PTR; /!< Transmit buffer RAM start address. /
Yassinetaouil	46:b1a9de66ecab	465	} I2S_TXD_Type;
Yassinetaouil	46:b1a9de66ecab	466
Yassinetaouil	46:b1a9de66ecab	467	typedef struct {
Yassinetaouil	46:b1a9de66ecab	468	__IO uint32_t MAXCNT; /!< Size of RXD and TXD buffers. /
Yassinetaouil	46:b1a9de66ecab	469	} I2S_RXTXD_Type;
Yassinetaouil	46:b1a9de66ecab	470
Yassinetaouil	46:b1a9de66ecab	471	typedef struct {
Yassinetaouil	46:b1a9de66ecab	472	__IO uint32_t MCK; /!< Pin select for MCK signal. /
Yassinetaouil	46:b1a9de66ecab	473	__IO uint32_t SCK; /!< Pin select for SCK signal. /
Yassinetaouil	46:b1a9de66ecab	474	__IO uint32_t LRCK; /!< Pin select for LRCK signal. /
Yassinetaouil	46:b1a9de66ecab	475	__IO uint32_t SDIN; /!< Pin select for SDIN signal. /
Yassinetaouil	46:b1a9de66ecab	476	__IO uint32_t SDOUT; /!< Pin select for SDOUT signal. /
Yassinetaouil	46:b1a9de66ecab	477	} I2S_PSEL_Type;
Yassinetaouil	46:b1a9de66ecab	478
Yassinetaouil	46:b1a9de66ecab	479
Yassinetaouil	46:b1a9de66ecab	480	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	481	/* ================ FICR ================ */
Yassinetaouil	46:b1a9de66ecab	482	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	483
Yassinetaouil	46:b1a9de66ecab	484
Yassinetaouil	46:b1a9de66ecab	485	/**
Yassinetaouil	46:b1a9de66ecab	486	* @brief Factory Information Configuration Registers (FICR)
Yassinetaouil	46:b1a9de66ecab	487	*/
Yassinetaouil	46:b1a9de66ecab	488
Yassinetaouil	46:b1a9de66ecab	489	typedef struct { /!< FICR Structure /
Yassinetaouil	46:b1a9de66ecab	490	__I uint32_t RESERVED0[4];
Yassinetaouil	46:b1a9de66ecab	491	__I uint32_t CODEPAGESIZE; /!< Code memory page size /
Yassinetaouil	46:b1a9de66ecab	492	__I uint32_t CODESIZE; /!< Code memory size /
Yassinetaouil	46:b1a9de66ecab	493	__I uint32_t RESERVED1[18];
Yassinetaouil	46:b1a9de66ecab	494	__I uint32_t DEVICEID[2]; /!< Description collection[0]: Device identifier /
Yassinetaouil	46:b1a9de66ecab	495	__I uint32_t RESERVED2[6];
Yassinetaouil	46:b1a9de66ecab	496	__I uint32_t ER[4]; /!< Description collection[0]: Encryption Root, word 0 /
Yassinetaouil	46:b1a9de66ecab	497	__I uint32_t IR[4]; /!< Description collection[0]: Identity Root, word 0 /
Yassinetaouil	46:b1a9de66ecab	498	__I uint32_t DEVICEADDRTYPE; /!< Device address type /
Yassinetaouil	46:b1a9de66ecab	499	__I uint32_t DEVICEADDR[2]; /!< Description collection[0]: Device address 0 /
Yassinetaouil	46:b1a9de66ecab	500	__I uint32_t RESERVED3[21];
Yassinetaouil	46:b1a9de66ecab	501	FICR_INFO_Type INFO; /!< Device info /
Yassinetaouil	46:b1a9de66ecab	502	__I uint32_t RESERVED4[185];
Yassinetaouil	46:b1a9de66ecab	503	FICR_TEMP_Type TEMP; /!< Registers storing factory TEMP module linearization coefficients /
Yassinetaouil	46:b1a9de66ecab	504	__I uint32_t RESERVED5[2];
Yassinetaouil	46:b1a9de66ecab	505	FICR_NFC_Type NFC; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	506	} NRF_FICR_Type;
Yassinetaouil	46:b1a9de66ecab	507
Yassinetaouil	46:b1a9de66ecab	508
Yassinetaouil	46:b1a9de66ecab	509	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	510	/* ================ UICR ================ */
Yassinetaouil	46:b1a9de66ecab	511	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	512
Yassinetaouil	46:b1a9de66ecab	513
Yassinetaouil	46:b1a9de66ecab	514	/**
Yassinetaouil	46:b1a9de66ecab	515	* @brief User Information Configuration Registers (UICR)
Yassinetaouil	46:b1a9de66ecab	516	*/
Yassinetaouil	46:b1a9de66ecab	517
Yassinetaouil	46:b1a9de66ecab	518	typedef struct { /!< UICR Structure /
Yassinetaouil	46:b1a9de66ecab	519	__IO uint32_t UNUSED0; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	520	__IO uint32_t UNUSED1; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	521	__IO uint32_t UNUSED2; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	522	__I uint32_t RESERVED0;
Yassinetaouil	46:b1a9de66ecab	523	__IO uint32_t UNUSED3; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	524	__IO uint32_t NRFFW[15]; /!< Description collection[0]: Reserved for Nordic firmware design /
Yassinetaouil	46:b1a9de66ecab	525	__IO uint32_t NRFHW[12]; /!< Description collection[0]: Reserved for Nordic hardware design /
Yassinetaouil	46:b1a9de66ecab	526	__IO uint32_t CUSTOMER[32]; /!< Description collection[0]: Reserved for customer /
Yassinetaouil	46:b1a9de66ecab	527	__I uint32_t RESERVED1[64];
Yassinetaouil	46:b1a9de66ecab	528	__IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see
Yassinetaouil	46:b1a9de66ecab	529	POWER chapter for details) */
Yassinetaouil	46:b1a9de66ecab	530	__IO uint32_t APPROTECT; /!< Access Port protection /
Yassinetaouil	46:b1a9de66ecab	531	__IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna
Yassinetaouil	46:b1a9de66ecab	532	or GPIO */
Yassinetaouil	46:b1a9de66ecab	533	} NRF_UICR_Type;
Yassinetaouil	46:b1a9de66ecab	534
Yassinetaouil	46:b1a9de66ecab	535
Yassinetaouil	46:b1a9de66ecab	536	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	537	/* ================ BPROT ================ */
Yassinetaouil	46:b1a9de66ecab	538	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	539
Yassinetaouil	46:b1a9de66ecab	540
Yassinetaouil	46:b1a9de66ecab	541	/**
Yassinetaouil	46:b1a9de66ecab	542	* @brief Block Protect (BPROT)
Yassinetaouil	46:b1a9de66ecab	543	*/
Yassinetaouil	46:b1a9de66ecab	544
Yassinetaouil	46:b1a9de66ecab	545	typedef struct { /!< BPROT Structure /
Yassinetaouil	46:b1a9de66ecab	546	__I uint32_t RESERVED0[384];
Yassinetaouil	46:b1a9de66ecab	547	__IO uint32_t CONFIG0; /!< Block protect configuration register 0 /
Yassinetaouil	46:b1a9de66ecab	548	__IO uint32_t CONFIG1; /!< Block protect configuration register 1 /
Yassinetaouil	46:b1a9de66ecab	549	__IO uint32_t DISABLEINDEBUG; /!< Disable protection mechanism in debug interface mode /
Yassinetaouil	46:b1a9de66ecab	550	__IO uint32_t UNUSED0; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	551	__IO uint32_t CONFIG2; /!< Block protect configuration register 2 /
Yassinetaouil	46:b1a9de66ecab	552	__IO uint32_t CONFIG3; /!< Block protect configuration register 3 /
Yassinetaouil	46:b1a9de66ecab	553	} NRF_BPROT_Type;
Yassinetaouil	46:b1a9de66ecab	554
Yassinetaouil	46:b1a9de66ecab	555
Yassinetaouil	46:b1a9de66ecab	556	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	557	/* ================ POWER ================ */
Yassinetaouil	46:b1a9de66ecab	558	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	559
Yassinetaouil	46:b1a9de66ecab	560
Yassinetaouil	46:b1a9de66ecab	561	/**
Yassinetaouil	46:b1a9de66ecab	562	* @brief Power control (POWER)
Yassinetaouil	46:b1a9de66ecab	563	*/
Yassinetaouil	46:b1a9de66ecab	564
Yassinetaouil	46:b1a9de66ecab	565	typedef struct { /!< POWER Structure /
Yassinetaouil	46:b1a9de66ecab	566	__I uint32_t RESERVED0[30];
Yassinetaouil	46:b1a9de66ecab	567	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode /
Yassinetaouil	46:b1a9de66ecab	568	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency) /
Yassinetaouil	46:b1a9de66ecab	569	__I uint32_t RESERVED1[34];
Yassinetaouil	46:b1a9de66ecab	570	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning /
Yassinetaouil	46:b1a9de66ecab	571	__I uint32_t RESERVED2[2];
Yassinetaouil	46:b1a9de66ecab	572	__IO uint32_t EVENTS_SLEEPENTER; /!< CPU entered WFI/WFE sleep /
Yassinetaouil	46:b1a9de66ecab	573	__IO uint32_t EVENTS_SLEEPEXIT; /!< CPU exited WFI/WFE sleep /
Yassinetaouil	46:b1a9de66ecab	574	__I uint32_t RESERVED3[122];
Yassinetaouil	46:b1a9de66ecab	575	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	576	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	577	__I uint32_t RESERVED4[61];
Yassinetaouil	46:b1a9de66ecab	578	__IO uint32_t RESETREAS; /!< Reset reason /
Yassinetaouil	46:b1a9de66ecab	579	__I uint32_t RESERVED5[9];
Yassinetaouil	46:b1a9de66ecab	580	__I uint32_t RAMSTATUS; /!< Deprecated register - RAM status register /
Yassinetaouil	46:b1a9de66ecab	581	__I uint32_t RESERVED6[53];
Yassinetaouil	46:b1a9de66ecab	582	__O uint32_t SYSTEMOFF; /!< System OFF register /
Yassinetaouil	46:b1a9de66ecab	583	__I uint32_t RESERVED7[3];
Yassinetaouil	46:b1a9de66ecab	584	__IO uint32_t POFCON; /!< Power failure comparator configuration /
Yassinetaouil	46:b1a9de66ecab	585	__I uint32_t RESERVED8[2];
Yassinetaouil	46:b1a9de66ecab	586	__IO uint32_t GPREGRET; /!< General purpose retention register /
Yassinetaouil	46:b1a9de66ecab	587	__IO uint32_t GPREGRET2; /!< General purpose retention register /
Yassinetaouil	46:b1a9de66ecab	588	__IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is
Yassinetaouil	46:b1a9de66ecab	589	retained) */
Yassinetaouil	46:b1a9de66ecab	590	__I uint32_t RESERVED9[11];
Yassinetaouil	46:b1a9de66ecab	591	__IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is
Yassinetaouil	46:b1a9de66ecab	592	retained) */
Yassinetaouil	46:b1a9de66ecab	593	__I uint32_t RESERVED10[8];
Yassinetaouil	46:b1a9de66ecab	594	__IO uint32_t DCDCEN; /!< DC/DC enable register /
Yassinetaouil	46:b1a9de66ecab	595	__I uint32_t RESERVED11[225];
Yassinetaouil	46:b1a9de66ecab	596	POWER_RAM_Type RAM[8]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	597	} NRF_POWER_Type;
Yassinetaouil	46:b1a9de66ecab	598
Yassinetaouil	46:b1a9de66ecab	599
Yassinetaouil	46:b1a9de66ecab	600	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	601	/* ================ CLOCK ================ */
Yassinetaouil	46:b1a9de66ecab	602	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	603
Yassinetaouil	46:b1a9de66ecab	604
Yassinetaouil	46:b1a9de66ecab	605	/**
Yassinetaouil	46:b1a9de66ecab	606	* @brief Clock control (CLOCK)
Yassinetaouil	46:b1a9de66ecab	607	*/
Yassinetaouil	46:b1a9de66ecab	608
Yassinetaouil	46:b1a9de66ecab	609	typedef struct { /!< CLOCK Structure /
Yassinetaouil	46:b1a9de66ecab	610	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK crystal oscillator /
Yassinetaouil	46:b1a9de66ecab	611	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK crystal oscillator /
Yassinetaouil	46:b1a9de66ecab	612	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK source /
Yassinetaouil	46:b1a9de66ecab	613	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK source /
Yassinetaouil	46:b1a9de66ecab	614	__O uint32_t TASKS_CAL; /!< Start calibration of LFRC oscillator /
Yassinetaouil	46:b1a9de66ecab	615	__O uint32_t TASKS_CTSTART; /!< Start calibration timer /
Yassinetaouil	46:b1a9de66ecab	616	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer /
Yassinetaouil	46:b1a9de66ecab	617	__I uint32_t RESERVED0[57];
Yassinetaouil	46:b1a9de66ecab	618	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started /
Yassinetaouil	46:b1a9de66ecab	619	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK started /
Yassinetaouil	46:b1a9de66ecab	620	__I uint32_t RESERVED1;
Yassinetaouil	46:b1a9de66ecab	621	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator complete event /
Yassinetaouil	46:b1a9de66ecab	622	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout /
Yassinetaouil	46:b1a9de66ecab	623	__I uint32_t RESERVED2[124];
Yassinetaouil	46:b1a9de66ecab	624	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	625	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	626	__I uint32_t RESERVED3[63];
Yassinetaouil	46:b1a9de66ecab	627	__I uint32_t HFCLKRUN; /!< Status indicating that HFCLKSTART task has been triggered /
Yassinetaouil	46:b1a9de66ecab	628	__I uint32_t HFCLKSTAT; /!< HFCLK status /
Yassinetaouil	46:b1a9de66ecab	629	__I uint32_t RESERVED4;
Yassinetaouil	46:b1a9de66ecab	630	__I uint32_t LFCLKRUN; /!< Status indicating that LFCLKSTART task has been triggered /
Yassinetaouil	46:b1a9de66ecab	631	__I uint32_t LFCLKSTAT; /!< LFCLK status /
Yassinetaouil	46:b1a9de66ecab	632	__I uint32_t LFCLKSRCCOPY; /!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered /
Yassinetaouil	46:b1a9de66ecab	633	__I uint32_t RESERVED5[62];
Yassinetaouil	46:b1a9de66ecab	634	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK /
Yassinetaouil	46:b1a9de66ecab	635	__I uint32_t RESERVED6[7];
Yassinetaouil	46:b1a9de66ecab	636	__IO uint32_t CTIV; /*!< Calibration timer interval (retained register, same reset behaviour
Yassinetaouil	46:b1a9de66ecab	637	as RESETREAS) */
Yassinetaouil	46:b1a9de66ecab	638	__I uint32_t RESERVED7[8];
Yassinetaouil	46:b1a9de66ecab	639	__IO uint32_t TRACECONFIG; /!< Clocking options for the Trace Port debug interface /
Yassinetaouil	46:b1a9de66ecab	640	} NRF_CLOCK_Type;
Yassinetaouil	46:b1a9de66ecab	641
Yassinetaouil	46:b1a9de66ecab	642
Yassinetaouil	46:b1a9de66ecab	643	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	644	/* ================ AMLI ================ */
Yassinetaouil	46:b1a9de66ecab	645	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	646
Yassinetaouil	46:b1a9de66ecab	647
Yassinetaouil	46:b1a9de66ecab	648	/**
Yassinetaouil	46:b1a9de66ecab	649	* @brief AHB Multi-Layer Interface (AMLI)
Yassinetaouil	46:b1a9de66ecab	650	*/
Yassinetaouil	46:b1a9de66ecab	651
Yassinetaouil	46:b1a9de66ecab	652	typedef struct { /!< AMLI Structure /
Yassinetaouil	46:b1a9de66ecab	653	__I uint32_t RESERVED0[896];
Yassinetaouil	46:b1a9de66ecab	654	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure /
Yassinetaouil	46:b1a9de66ecab	655	} NRF_AMLI_Type;
Yassinetaouil	46:b1a9de66ecab	656
Yassinetaouil	46:b1a9de66ecab	657
Yassinetaouil	46:b1a9de66ecab	658	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	659	/* ================ RADIO ================ */
Yassinetaouil	46:b1a9de66ecab	660	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	661
Yassinetaouil	46:b1a9de66ecab	662
Yassinetaouil	46:b1a9de66ecab	663	/**
Yassinetaouil	46:b1a9de66ecab	664	* @brief 2.4 GHz Radio (RADIO)
Yassinetaouil	46:b1a9de66ecab	665	*/
Yassinetaouil	46:b1a9de66ecab	666
Yassinetaouil	46:b1a9de66ecab	667	typedef struct { /!< RADIO Structure /
Yassinetaouil	46:b1a9de66ecab	668	__O uint32_t TASKS_TXEN; /!< Enable RADIO in TX mode /
Yassinetaouil	46:b1a9de66ecab	669	__O uint32_t TASKS_RXEN; /!< Enable RADIO in RX mode /
Yassinetaouil	46:b1a9de66ecab	670	__O uint32_t TASKS_START; /!< Start RADIO /
Yassinetaouil	46:b1a9de66ecab	671	__O uint32_t TASKS_STOP; /!< Stop RADIO /
Yassinetaouil	46:b1a9de66ecab	672	__O uint32_t TASKS_DISABLE; /!< Disable RADIO /
Yassinetaouil	46:b1a9de66ecab	673	__O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal
Yassinetaouil	46:b1a9de66ecab	674	strength. */
Yassinetaouil	46:b1a9de66ecab	675	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement /
Yassinetaouil	46:b1a9de66ecab	676	__O uint32_t TASKS_BCSTART; /!< Start the bit counter /
Yassinetaouil	46:b1a9de66ecab	677	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter /
Yassinetaouil	46:b1a9de66ecab	678	__I uint32_t RESERVED0[55];
Yassinetaouil	46:b1a9de66ecab	679	__IO uint32_t EVENTS_READY; /!< RADIO has ramped up and is ready to be started /
Yassinetaouil	46:b1a9de66ecab	680	__IO uint32_t EVENTS_ADDRESS; /!< Address sent or received /
Yassinetaouil	46:b1a9de66ecab	681	__IO uint32_t EVENTS_PAYLOAD; /!< Packet payload sent or received /
Yassinetaouil	46:b1a9de66ecab	682	__IO uint32_t EVENTS_END; /!< Packet sent or received /
Yassinetaouil	46:b1a9de66ecab	683	__IO uint32_t EVENTS_DISABLED; /!< RADIO has been disabled /
Yassinetaouil	46:b1a9de66ecab	684	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet /
Yassinetaouil	46:b1a9de66ecab	685	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet /
Yassinetaouil	46:b1a9de66ecab	686	__IO uint32_t EVENTS_RSSIEND; /!< Sampling of receive signal strength complete. /
Yassinetaouil	46:b1a9de66ecab	687	__I uint32_t RESERVED1[2];
Yassinetaouil	46:b1a9de66ecab	688	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value. /
Yassinetaouil	46:b1a9de66ecab	689	__I uint32_t RESERVED2;
Yassinetaouil	46:b1a9de66ecab	690	__IO uint32_t EVENTS_CRCOK; /!< Packet received with CRC ok /
Yassinetaouil	46:b1a9de66ecab	691	__IO uint32_t EVENTS_CRCERROR; /!< Packet received with CRC error /
Yassinetaouil	46:b1a9de66ecab	692	__I uint32_t RESERVED3[50];
Yassinetaouil	46:b1a9de66ecab	693	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	694	__I uint32_t RESERVED4[64];
Yassinetaouil	46:b1a9de66ecab	695	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	696	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	697	__I uint32_t RESERVED5[61];
Yassinetaouil	46:b1a9de66ecab	698	__I uint32_t CRCSTATUS; /!< CRC status /
Yassinetaouil	46:b1a9de66ecab	699	__I uint32_t RESERVED6;
Yassinetaouil	46:b1a9de66ecab	700	__I uint32_t RXMATCH; /!< Received address /
Yassinetaouil	46:b1a9de66ecab	701	__I uint32_t RXCRC; /!< CRC field of previously received packet /
Yassinetaouil	46:b1a9de66ecab	702	__I uint32_t DAI; /!< Device address match index /
Yassinetaouil	46:b1a9de66ecab	703	__I uint32_t RESERVED7[60];
Yassinetaouil	46:b1a9de66ecab	704	__IO uint32_t PACKETPTR; /!< Packet pointer /
Yassinetaouil	46:b1a9de66ecab	705	__IO uint32_t FREQUENCY; /!< Frequency /
Yassinetaouil	46:b1a9de66ecab	706	__IO uint32_t TXPOWER; /!< Output power /
Yassinetaouil	46:b1a9de66ecab	707	__IO uint32_t MODE; /!< Data rate and modulation /
Yassinetaouil	46:b1a9de66ecab	708	__IO uint32_t PCNF0; /!< Packet configuration register 0 /
Yassinetaouil	46:b1a9de66ecab	709	__IO uint32_t PCNF1; /!< Packet configuration register 1 /
Yassinetaouil	46:b1a9de66ecab	710	__IO uint32_t BASE0; /!< Base address 0 /
Yassinetaouil	46:b1a9de66ecab	711	__IO uint32_t BASE1; /!< Base address 1 /
Yassinetaouil	46:b1a9de66ecab	712	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0-3 /
Yassinetaouil	46:b1a9de66ecab	713	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4-7 /
Yassinetaouil	46:b1a9de66ecab	714	__IO uint32_t TXADDRESS; /!< Transmit address select /
Yassinetaouil	46:b1a9de66ecab	715	__IO uint32_t RXADDRESSES; /!< Receive address select /
Yassinetaouil	46:b1a9de66ecab	716	__IO uint32_t CRCCNF; /!< CRC configuration /
Yassinetaouil	46:b1a9de66ecab	717	__IO uint32_t CRCPOLY; /!< CRC polynomial /
Yassinetaouil	46:b1a9de66ecab	718	__IO uint32_t CRCINIT; /!< CRC initial value /
Yassinetaouil	46:b1a9de66ecab	719	__IO uint32_t UNUSED0; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	720	__IO uint32_t TIFS; /!< Inter Frame Spacing in us /
Yassinetaouil	46:b1a9de66ecab	721	__I uint32_t RSSISAMPLE; /!< RSSI sample /
Yassinetaouil	46:b1a9de66ecab	722	__I uint32_t RESERVED8;
Yassinetaouil	46:b1a9de66ecab	723	__I uint32_t STATE; /!< Current radio state /
Yassinetaouil	46:b1a9de66ecab	724	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value /
Yassinetaouil	46:b1a9de66ecab	725	__I uint32_t RESERVED9[2];
Yassinetaouil	46:b1a9de66ecab	726	__IO uint32_t BCC; /!< Bit counter compare /
Yassinetaouil	46:b1a9de66ecab	727	__I uint32_t RESERVED10[39];
Yassinetaouil	46:b1a9de66ecab	728	__IO uint32_t DAB[8]; /!< Description collection[0]: Device address base segment 0 /
Yassinetaouil	46:b1a9de66ecab	729	__IO uint32_t DAP[8]; /!< Description collection[0]: Device address prefix 0 /
Yassinetaouil	46:b1a9de66ecab	730	__IO uint32_t DACNF; /!< Device address match configuration /
Yassinetaouil	46:b1a9de66ecab	731	__I uint32_t RESERVED11[3];
Yassinetaouil	46:b1a9de66ecab	732	__IO uint32_t MODECNF0; /!< Radio mode configuration register 0 /
Yassinetaouil	46:b1a9de66ecab	733	__I uint32_t RESERVED12[618];
Yassinetaouil	46:b1a9de66ecab	734	__IO uint32_t POWER; /!< Peripheral power control /
Yassinetaouil	46:b1a9de66ecab	735	} NRF_RADIO_Type;
Yassinetaouil	46:b1a9de66ecab	736
Yassinetaouil	46:b1a9de66ecab	737
Yassinetaouil	46:b1a9de66ecab	738	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	739	/* ================ UARTE ================ */
Yassinetaouil	46:b1a9de66ecab	740	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	741
Yassinetaouil	46:b1a9de66ecab	742
Yassinetaouil	46:b1a9de66ecab	743	/**
Yassinetaouil	46:b1a9de66ecab	744	* @brief UART with EasyDMA (UARTE)
Yassinetaouil	46:b1a9de66ecab	745	*/
Yassinetaouil	46:b1a9de66ecab	746
Yassinetaouil	46:b1a9de66ecab	747	typedef struct { /!< UARTE Structure /
Yassinetaouil	46:b1a9de66ecab	748	__O uint32_t TASKS_STARTRX; /!< Start UART receiver /
Yassinetaouil	46:b1a9de66ecab	749	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver /
Yassinetaouil	46:b1a9de66ecab	750	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter /
Yassinetaouil	46:b1a9de66ecab	751	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter /
Yassinetaouil	46:b1a9de66ecab	752	__I uint32_t RESERVED0[7];
Yassinetaouil	46:b1a9de66ecab	753	__O uint32_t TASKS_FLUSHRX; /!< Flush RX FIFO into RX buffer /
Yassinetaouil	46:b1a9de66ecab	754	__I uint32_t RESERVED1[52];
Yassinetaouil	46:b1a9de66ecab	755	__IO uint32_t EVENTS_CTS; /!< CTS is activated (set low). Clear To Send. /
Yassinetaouil	46:b1a9de66ecab	756	__IO uint32_t EVENTS_NCTS; /!< CTS is deactivated (set high). Not Clear To Send. /
Yassinetaouil	46:b1a9de66ecab	757	__I uint32_t RESERVED2[2];
Yassinetaouil	46:b1a9de66ecab	758	__IO uint32_t EVENTS_ENDRX; /!< Receive buffer is filled up /
Yassinetaouil	46:b1a9de66ecab	759	__I uint32_t RESERVED3[3];
Yassinetaouil	46:b1a9de66ecab	760	__IO uint32_t EVENTS_ENDTX; /!< Last TX byte transmitted /
Yassinetaouil	46:b1a9de66ecab	761	__IO uint32_t EVENTS_ERROR; /!< Error detected /
Yassinetaouil	46:b1a9de66ecab	762	__I uint32_t RESERVED4[7];
Yassinetaouil	46:b1a9de66ecab	763	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout /
Yassinetaouil	46:b1a9de66ecab	764	__I uint32_t RESERVED5;
Yassinetaouil	46:b1a9de66ecab	765	__IO uint32_t EVENTS_RXSTARTED; /!< UART receiver has started /
Yassinetaouil	46:b1a9de66ecab	766	__IO uint32_t EVENTS_TXSTARTED; /!< UART transmitter has started /
Yassinetaouil	46:b1a9de66ecab	767	__I uint32_t RESERVED6;
Yassinetaouil	46:b1a9de66ecab	768	__IO uint32_t EVENTS_TXSTOPPED; /!< Transmitter stopped /
Yassinetaouil	46:b1a9de66ecab	769	__I uint32_t RESERVED7[41];
Yassinetaouil	46:b1a9de66ecab	770	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	771	__I uint32_t RESERVED8[63];
Yassinetaouil	46:b1a9de66ecab	772	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	773	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	774	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	775	__I uint32_t RESERVED9[93];
Yassinetaouil	46:b1a9de66ecab	776	__IO uint32_t ERRORSRC; /!< Error source /
Yassinetaouil	46:b1a9de66ecab	777	__I uint32_t RESERVED10[31];
Yassinetaouil	46:b1a9de66ecab	778	__IO uint32_t ENABLE; /!< Enable UART /
Yassinetaouil	46:b1a9de66ecab	779	__I uint32_t RESERVED11;
Yassinetaouil	46:b1a9de66ecab	780	UARTE_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	781	__I uint32_t RESERVED12[3];
Yassinetaouil	46:b1a9de66ecab	782	__IO uint32_t BAUDRATE; /!< Baud rate /
Yassinetaouil	46:b1a9de66ecab	783	__I uint32_t RESERVED13[3];
Yassinetaouil	46:b1a9de66ecab	784	UARTE_RXD_Type RXD; /!< RXD EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	785	__I uint32_t RESERVED14;
Yassinetaouil	46:b1a9de66ecab	786	UARTE_TXD_Type TXD; /!< TXD EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	787	__I uint32_t RESERVED15[7];
Yassinetaouil	46:b1a9de66ecab	788	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control /
Yassinetaouil	46:b1a9de66ecab	789	} NRF_UARTE_Type;
Yassinetaouil	46:b1a9de66ecab	790
Yassinetaouil	46:b1a9de66ecab	791
Yassinetaouil	46:b1a9de66ecab	792	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	793	/* ================ UART ================ */
Yassinetaouil	46:b1a9de66ecab	794	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	795
Yassinetaouil	46:b1a9de66ecab	796
Yassinetaouil	46:b1a9de66ecab	797	/**
Yassinetaouil	46:b1a9de66ecab	798	* @brief Universal Asynchronous Receiver/Transmitter (UART)
Yassinetaouil	46:b1a9de66ecab	799	*/
Yassinetaouil	46:b1a9de66ecab	800
Yassinetaouil	46:b1a9de66ecab	801	typedef struct { /!< UART Structure /
Yassinetaouil	46:b1a9de66ecab	802	__O uint32_t TASKS_STARTRX; /!< Start UART receiver /
Yassinetaouil	46:b1a9de66ecab	803	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver /
Yassinetaouil	46:b1a9de66ecab	804	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter /
Yassinetaouil	46:b1a9de66ecab	805	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter /
Yassinetaouil	46:b1a9de66ecab	806	__I uint32_t RESERVED0[3];
Yassinetaouil	46:b1a9de66ecab	807	__O uint32_t TASKS_SUSPEND; /!< Suspend UART /
Yassinetaouil	46:b1a9de66ecab	808	__I uint32_t RESERVED1[56];
Yassinetaouil	46:b1a9de66ecab	809	__IO uint32_t EVENTS_CTS; /!< CTS is activated (set low). Clear To Send. /
Yassinetaouil	46:b1a9de66ecab	810	__IO uint32_t EVENTS_NCTS; /!< CTS is deactivated (set high). Not Clear To Send. /
Yassinetaouil	46:b1a9de66ecab	811	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD /
Yassinetaouil	46:b1a9de66ecab	812	__I uint32_t RESERVED2[4];
Yassinetaouil	46:b1a9de66ecab	813	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD /
Yassinetaouil	46:b1a9de66ecab	814	__I uint32_t RESERVED3;
Yassinetaouil	46:b1a9de66ecab	815	__IO uint32_t EVENTS_ERROR; /!< Error detected /
Yassinetaouil	46:b1a9de66ecab	816	__I uint32_t RESERVED4[7];
Yassinetaouil	46:b1a9de66ecab	817	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout /
Yassinetaouil	46:b1a9de66ecab	818	__I uint32_t RESERVED5[46];
Yassinetaouil	46:b1a9de66ecab	819	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	820	__I uint32_t RESERVED6[64];
Yassinetaouil	46:b1a9de66ecab	821	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	822	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	823	__I uint32_t RESERVED7[93];
Yassinetaouil	46:b1a9de66ecab	824	__IO uint32_t ERRORSRC; /!< Error source /
Yassinetaouil	46:b1a9de66ecab	825	__I uint32_t RESERVED8[31];
Yassinetaouil	46:b1a9de66ecab	826	__IO uint32_t ENABLE; /!< Enable UART /
Yassinetaouil	46:b1a9de66ecab	827	__I uint32_t RESERVED9;
Yassinetaouil	46:b1a9de66ecab	828	__IO uint32_t PSELRTS; /!< Pin select for RTS /
Yassinetaouil	46:b1a9de66ecab	829	__IO uint32_t PSELTXD; /!< Pin select for TXD /
Yassinetaouil	46:b1a9de66ecab	830	__IO uint32_t PSELCTS; /!< Pin select for CTS /
Yassinetaouil	46:b1a9de66ecab	831	__IO uint32_t PSELRXD; /!< Pin select for RXD /
Yassinetaouil	46:b1a9de66ecab	832	__I uint32_t RXD; /!< RXD register /
Yassinetaouil	46:b1a9de66ecab	833	__O uint32_t TXD; /!< TXD register /
Yassinetaouil	46:b1a9de66ecab	834	__I uint32_t RESERVED10;
Yassinetaouil	46:b1a9de66ecab	835	__IO uint32_t BAUDRATE; /!< Baud rate /
Yassinetaouil	46:b1a9de66ecab	836	__I uint32_t RESERVED11[17];
Yassinetaouil	46:b1a9de66ecab	837	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control /
Yassinetaouil	46:b1a9de66ecab	838	} NRF_UART_Type;
Yassinetaouil	46:b1a9de66ecab	839
Yassinetaouil	46:b1a9de66ecab	840
Yassinetaouil	46:b1a9de66ecab	841	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	842	/* ================ SPIM ================ */
Yassinetaouil	46:b1a9de66ecab	843	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	844
Yassinetaouil	46:b1a9de66ecab	845
Yassinetaouil	46:b1a9de66ecab	846	/**
Yassinetaouil	46:b1a9de66ecab	847	* @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
Yassinetaouil	46:b1a9de66ecab	848	*/
Yassinetaouil	46:b1a9de66ecab	849
Yassinetaouil	46:b1a9de66ecab	850	typedef struct { /!< SPIM Structure /
Yassinetaouil	46:b1a9de66ecab	851	__I uint32_t RESERVED0[4];
Yassinetaouil	46:b1a9de66ecab	852	__O uint32_t TASKS_START; /!< Start SPI transaction /
Yassinetaouil	46:b1a9de66ecab	853	__O uint32_t TASKS_STOP; /!< Stop SPI transaction /
Yassinetaouil	46:b1a9de66ecab	854	__I uint32_t RESERVED1;
Yassinetaouil	46:b1a9de66ecab	855	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction /
Yassinetaouil	46:b1a9de66ecab	856	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction /
Yassinetaouil	46:b1a9de66ecab	857	__I uint32_t RESERVED2[56];
Yassinetaouil	46:b1a9de66ecab	858	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped /
Yassinetaouil	46:b1a9de66ecab	859	__I uint32_t RESERVED3[2];
Yassinetaouil	46:b1a9de66ecab	860	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached /
Yassinetaouil	46:b1a9de66ecab	861	__I uint32_t RESERVED4;
Yassinetaouil	46:b1a9de66ecab	862	__IO uint32_t EVENTS_END; /!< End of RXD buffer and TXD buffer reached /
Yassinetaouil	46:b1a9de66ecab	863	__I uint32_t RESERVED5;
Yassinetaouil	46:b1a9de66ecab	864	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached /
Yassinetaouil	46:b1a9de66ecab	865	__I uint32_t RESERVED6[10];
Yassinetaouil	46:b1a9de66ecab	866	__IO uint32_t EVENTS_STARTED; /!< Transaction started /
Yassinetaouil	46:b1a9de66ecab	867	__I uint32_t RESERVED7[44];
Yassinetaouil	46:b1a9de66ecab	868	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	869	__I uint32_t RESERVED8[64];
Yassinetaouil	46:b1a9de66ecab	870	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	871	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	872	__I uint32_t RESERVED9[125];
Yassinetaouil	46:b1a9de66ecab	873	__IO uint32_t ENABLE; /!< Enable SPIM /
Yassinetaouil	46:b1a9de66ecab	874	__I uint32_t RESERVED10;
Yassinetaouil	46:b1a9de66ecab	875	SPIM_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	876	__I uint32_t RESERVED11[4];
Yassinetaouil	46:b1a9de66ecab	877	__IO uint32_t FREQUENCY; /!< SPI frequency /
Yassinetaouil	46:b1a9de66ecab	878	__I uint32_t RESERVED12[3];
Yassinetaouil	46:b1a9de66ecab	879	SPIM_RXD_Type RXD; /!< RXD EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	880	SPIM_TXD_Type TXD; /!< TXD EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	881	__IO uint32_t CONFIG; /!< Configuration register /
Yassinetaouil	46:b1a9de66ecab	882	__I uint32_t RESERVED13[26];
Yassinetaouil	46:b1a9de66ecab	883	__IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read
Yassinetaouil	46:b1a9de66ecab	884	of the TXD buffer. */
Yassinetaouil	46:b1a9de66ecab	885	} NRF_SPIM_Type;
Yassinetaouil	46:b1a9de66ecab	886
Yassinetaouil	46:b1a9de66ecab	887
Yassinetaouil	46:b1a9de66ecab	888	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	889	/* ================ SPIS ================ */
Yassinetaouil	46:b1a9de66ecab	890	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	891
Yassinetaouil	46:b1a9de66ecab	892
Yassinetaouil	46:b1a9de66ecab	893	/**
Yassinetaouil	46:b1a9de66ecab	894	* @brief SPI Slave 0 (SPIS)
Yassinetaouil	46:b1a9de66ecab	895	*/
Yassinetaouil	46:b1a9de66ecab	896
Yassinetaouil	46:b1a9de66ecab	897	typedef struct { /!< SPIS Structure /
Yassinetaouil	46:b1a9de66ecab	898	__I uint32_t RESERVED0[9];
Yassinetaouil	46:b1a9de66ecab	899	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore /
Yassinetaouil	46:b1a9de66ecab	900	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore, enabling the SPI slave to acquire it /
Yassinetaouil	46:b1a9de66ecab	901	__I uint32_t RESERVED1[54];
Yassinetaouil	46:b1a9de66ecab	902	__IO uint32_t EVENTS_END; /!< Granted transaction completed /
Yassinetaouil	46:b1a9de66ecab	903	__I uint32_t RESERVED2[2];
Yassinetaouil	46:b1a9de66ecab	904	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached /
Yassinetaouil	46:b1a9de66ecab	905	__I uint32_t RESERVED3[5];
Yassinetaouil	46:b1a9de66ecab	906	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired /
Yassinetaouil	46:b1a9de66ecab	907	__I uint32_t RESERVED4[53];
Yassinetaouil	46:b1a9de66ecab	908	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	909	__I uint32_t RESERVED5[64];
Yassinetaouil	46:b1a9de66ecab	910	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	911	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	912	__I uint32_t RESERVED6[61];
Yassinetaouil	46:b1a9de66ecab	913	__I uint32_t SEMSTAT; /!< Semaphore status register /
Yassinetaouil	46:b1a9de66ecab	914	__I uint32_t RESERVED7[15];
Yassinetaouil	46:b1a9de66ecab	915	__IO uint32_t STATUS; /!< Status from last transaction /
Yassinetaouil	46:b1a9de66ecab	916	__I uint32_t RESERVED8[47];
Yassinetaouil	46:b1a9de66ecab	917	__IO uint32_t ENABLE; /!< Enable SPI slave /
Yassinetaouil	46:b1a9de66ecab	918	__I uint32_t RESERVED9;
Yassinetaouil	46:b1a9de66ecab	919	SPIS_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	920	__I uint32_t RESERVED10[7];
Yassinetaouil	46:b1a9de66ecab	921	SPIS_RXD_Type RXD; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	922	__I uint32_t RESERVED11;
Yassinetaouil	46:b1a9de66ecab	923	SPIS_TXD_Type TXD; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	924	__I uint32_t RESERVED12;
Yassinetaouil	46:b1a9de66ecab	925	__IO uint32_t CONFIG; /!< Configuration register /
Yassinetaouil	46:b1a9de66ecab	926	__I uint32_t RESERVED13;
Yassinetaouil	46:b1a9de66ecab	927	__IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored
Yassinetaouil	46:b1a9de66ecab	928	transaction. */
Yassinetaouil	46:b1a9de66ecab	929	__I uint32_t RESERVED14[24];
Yassinetaouil	46:b1a9de66ecab	930	__IO uint32_t ORC; /!< Over-read character /
Yassinetaouil	46:b1a9de66ecab	931	} NRF_SPIS_Type;
Yassinetaouil	46:b1a9de66ecab	932
Yassinetaouil	46:b1a9de66ecab	933
Yassinetaouil	46:b1a9de66ecab	934	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	935	/* ================ TWIM ================ */
Yassinetaouil	46:b1a9de66ecab	936	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	937
Yassinetaouil	46:b1a9de66ecab	938
Yassinetaouil	46:b1a9de66ecab	939	/**
Yassinetaouil	46:b1a9de66ecab	940	* @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
Yassinetaouil	46:b1a9de66ecab	941	*/
Yassinetaouil	46:b1a9de66ecab	942
Yassinetaouil	46:b1a9de66ecab	943	typedef struct { /!< TWIM Structure /
Yassinetaouil	46:b1a9de66ecab	944	__O uint32_t TASKS_STARTRX; /!< Start TWI receive sequence /
Yassinetaouil	46:b1a9de66ecab	945	__I uint32_t RESERVED0;
Yassinetaouil	46:b1a9de66ecab	946	__O uint32_t TASKS_STARTTX; /!< Start TWI transmit sequence /
Yassinetaouil	46:b1a9de66ecab	947	__I uint32_t RESERVED1[2];
Yassinetaouil	46:b1a9de66ecab	948	__O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is
Yassinetaouil	46:b1a9de66ecab	949	not suspended. */
Yassinetaouil	46:b1a9de66ecab	950	__I uint32_t RESERVED2;
Yassinetaouil	46:b1a9de66ecab	951	__O uint32_t TASKS_SUSPEND; /!< Suspend TWI transaction /
Yassinetaouil	46:b1a9de66ecab	952	__O uint32_t TASKS_RESUME; /!< Resume TWI transaction /
Yassinetaouil	46:b1a9de66ecab	953	__I uint32_t RESERVED3[56];
Yassinetaouil	46:b1a9de66ecab	954	__IO uint32_t EVENTS_STOPPED; /!< TWI stopped /
Yassinetaouil	46:b1a9de66ecab	955	__I uint32_t RESERVED4[7];
Yassinetaouil	46:b1a9de66ecab	956	__IO uint32_t EVENTS_ERROR; /!< TWI error /
Yassinetaouil	46:b1a9de66ecab	957	__I uint32_t RESERVED5[8];
Yassinetaouil	46:b1a9de66ecab	958	__IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been
Yassinetaouil	46:b1a9de66ecab	959	issued, TWI traffic is now suspended. */
Yassinetaouil	46:b1a9de66ecab	960	__IO uint32_t EVENTS_RXSTARTED; /!< Receive sequence started /
Yassinetaouil	46:b1a9de66ecab	961	__IO uint32_t EVENTS_TXSTARTED; /!< Transmit sequence started /
Yassinetaouil	46:b1a9de66ecab	962	__I uint32_t RESERVED6[2];
Yassinetaouil	46:b1a9de66ecab	963	__IO uint32_t EVENTS_LASTRX; /!< Byte boundary, starting to receive the last byte /
Yassinetaouil	46:b1a9de66ecab	964	__IO uint32_t EVENTS_LASTTX; /!< Byte boundary, starting to transmit the last byte /
Yassinetaouil	46:b1a9de66ecab	965	__I uint32_t RESERVED7[39];
Yassinetaouil	46:b1a9de66ecab	966	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	967	__I uint32_t RESERVED8[63];
Yassinetaouil	46:b1a9de66ecab	968	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	969	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	970	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	971	__I uint32_t RESERVED9[110];
Yassinetaouil	46:b1a9de66ecab	972	__IO uint32_t ERRORSRC; /!< Error source /
Yassinetaouil	46:b1a9de66ecab	973	__I uint32_t RESERVED10[14];
Yassinetaouil	46:b1a9de66ecab	974	__IO uint32_t ENABLE; /!< Enable TWIM /
Yassinetaouil	46:b1a9de66ecab	975	__I uint32_t RESERVED11;
Yassinetaouil	46:b1a9de66ecab	976	TWIM_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	977	__I uint32_t RESERVED12[5];
Yassinetaouil	46:b1a9de66ecab	978	__IO uint32_t FREQUENCY; /!< TWI frequency /
Yassinetaouil	46:b1a9de66ecab	979	__I uint32_t RESERVED13[3];
Yassinetaouil	46:b1a9de66ecab	980	TWIM_RXD_Type RXD; /!< RXD EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	981	TWIM_TXD_Type TXD; /!< TXD EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	982	__I uint32_t RESERVED14[13];
Yassinetaouil	46:b1a9de66ecab	983	__IO uint32_t ADDRESS; /!< Address used in the TWI transfer /
Yassinetaouil	46:b1a9de66ecab	984	} NRF_TWIM_Type;
Yassinetaouil	46:b1a9de66ecab	985
Yassinetaouil	46:b1a9de66ecab	986
Yassinetaouil	46:b1a9de66ecab	987	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	988	/* ================ TWIS ================ */
Yassinetaouil	46:b1a9de66ecab	989	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	990
Yassinetaouil	46:b1a9de66ecab	991
Yassinetaouil	46:b1a9de66ecab	992	/**
Yassinetaouil	46:b1a9de66ecab	993	* @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
Yassinetaouil	46:b1a9de66ecab	994	*/
Yassinetaouil	46:b1a9de66ecab	995
Yassinetaouil	46:b1a9de66ecab	996	typedef struct { /!< TWIS Structure /
Yassinetaouil	46:b1a9de66ecab	997	__I uint32_t RESERVED0[5];
Yassinetaouil	46:b1a9de66ecab	998	__O uint32_t TASKS_STOP; /!< Stop TWI transaction /
Yassinetaouil	46:b1a9de66ecab	999	__I uint32_t RESERVED1;
Yassinetaouil	46:b1a9de66ecab	1000	__O uint32_t TASKS_SUSPEND; /!< Suspend TWI transaction /
Yassinetaouil	46:b1a9de66ecab	1001	__O uint32_t TASKS_RESUME; /!< Resume TWI transaction /
Yassinetaouil	46:b1a9de66ecab	1002	__I uint32_t RESERVED2[3];
Yassinetaouil	46:b1a9de66ecab	1003	__O uint32_t TASKS_PREPARERX; /!< Prepare the TWI slave to respond to a write command /
Yassinetaouil	46:b1a9de66ecab	1004	__O uint32_t TASKS_PREPARETX; /!< Prepare the TWI slave to respond to a read command /
Yassinetaouil	46:b1a9de66ecab	1005	__I uint32_t RESERVED3[51];
Yassinetaouil	46:b1a9de66ecab	1006	__IO uint32_t EVENTS_STOPPED; /!< TWI stopped /
Yassinetaouil	46:b1a9de66ecab	1007	__I uint32_t RESERVED4[7];
Yassinetaouil	46:b1a9de66ecab	1008	__IO uint32_t EVENTS_ERROR; /!< TWI error /
Yassinetaouil	46:b1a9de66ecab	1009	__I uint32_t RESERVED5[9];
Yassinetaouil	46:b1a9de66ecab	1010	__IO uint32_t EVENTS_RXSTARTED; /!< Receive sequence started /
Yassinetaouil	46:b1a9de66ecab	1011	__IO uint32_t EVENTS_TXSTARTED; /!< Transmit sequence started /
Yassinetaouil	46:b1a9de66ecab	1012	__I uint32_t RESERVED6[4];
Yassinetaouil	46:b1a9de66ecab	1013	__IO uint32_t EVENTS_WRITE; /!< Write command received /
Yassinetaouil	46:b1a9de66ecab	1014	__IO uint32_t EVENTS_READ; /!< Read command received /
Yassinetaouil	46:b1a9de66ecab	1015	__I uint32_t RESERVED7[37];
Yassinetaouil	46:b1a9de66ecab	1016	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1017	__I uint32_t RESERVED8[63];
Yassinetaouil	46:b1a9de66ecab	1018	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1019	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1020	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1021	__I uint32_t RESERVED9[113];
Yassinetaouil	46:b1a9de66ecab	1022	__IO uint32_t ERRORSRC; /!< Error source /
Yassinetaouil	46:b1a9de66ecab	1023	__I uint32_t MATCH; /!< Status register indicating which address had a match /
Yassinetaouil	46:b1a9de66ecab	1024	__I uint32_t RESERVED10[10];
Yassinetaouil	46:b1a9de66ecab	1025	__IO uint32_t ENABLE; /!< Enable TWIS /
Yassinetaouil	46:b1a9de66ecab	1026	__I uint32_t RESERVED11;
Yassinetaouil	46:b1a9de66ecab	1027	TWIS_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1028	__I uint32_t RESERVED12[9];
Yassinetaouil	46:b1a9de66ecab	1029	TWIS_RXD_Type RXD; /!< RXD EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	1030	__I uint32_t RESERVED13;
Yassinetaouil	46:b1a9de66ecab	1031	TWIS_TXD_Type TXD; /!< TXD EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	1032	__I uint32_t RESERVED14[14];
Yassinetaouil	46:b1a9de66ecab	1033	__IO uint32_t ADDRESS[2]; /!< Description collection[0]: TWI slave address 0 /
Yassinetaouil	46:b1a9de66ecab	1034	__I uint32_t RESERVED15;
Yassinetaouil	46:b1a9de66ecab	1035	__IO uint32_t CONFIG; /!< Configuration register for the address match mechanism /
Yassinetaouil	46:b1a9de66ecab	1036	__I uint32_t RESERVED16[10];
Yassinetaouil	46:b1a9de66ecab	1037	__IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read
Yassinetaouil	46:b1a9de66ecab	1038	of the transmit buffer. */
Yassinetaouil	46:b1a9de66ecab	1039	} NRF_TWIS_Type;
Yassinetaouil	46:b1a9de66ecab	1040
Yassinetaouil	46:b1a9de66ecab	1041
Yassinetaouil	46:b1a9de66ecab	1042	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1043	/* ================ SPI ================ */
Yassinetaouil	46:b1a9de66ecab	1044	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1045
Yassinetaouil	46:b1a9de66ecab	1046
Yassinetaouil	46:b1a9de66ecab	1047	/**
Yassinetaouil	46:b1a9de66ecab	1048	* @brief Serial Peripheral Interface 0 (SPI)
Yassinetaouil	46:b1a9de66ecab	1049	*/
Yassinetaouil	46:b1a9de66ecab	1050
Yassinetaouil	46:b1a9de66ecab	1051	typedef struct { /!< SPI Structure /
Yassinetaouil	46:b1a9de66ecab	1052	__I uint32_t RESERVED0[66];
Yassinetaouil	46:b1a9de66ecab	1053	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received /
Yassinetaouil	46:b1a9de66ecab	1054	__I uint32_t RESERVED1[126];
Yassinetaouil	46:b1a9de66ecab	1055	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1056	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1057	__I uint32_t RESERVED2[125];
Yassinetaouil	46:b1a9de66ecab	1058	__IO uint32_t ENABLE; /!< Enable SPI /
Yassinetaouil	46:b1a9de66ecab	1059	__I uint32_t RESERVED3;
Yassinetaouil	46:b1a9de66ecab	1060	SPI_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1061	__I uint32_t RESERVED4;
Yassinetaouil	46:b1a9de66ecab	1062	__I uint32_t RXD; /!< RXD register /
Yassinetaouil	46:b1a9de66ecab	1063	__IO uint32_t TXD; /!< TXD register /
Yassinetaouil	46:b1a9de66ecab	1064	__I uint32_t RESERVED5;
Yassinetaouil	46:b1a9de66ecab	1065	__IO uint32_t FREQUENCY; /!< SPI frequency /
Yassinetaouil	46:b1a9de66ecab	1066	__I uint32_t RESERVED6[11];
Yassinetaouil	46:b1a9de66ecab	1067	__IO uint32_t CONFIG; /!< Configuration register /
Yassinetaouil	46:b1a9de66ecab	1068	} NRF_SPI_Type;
Yassinetaouil	46:b1a9de66ecab	1069
Yassinetaouil	46:b1a9de66ecab	1070
Yassinetaouil	46:b1a9de66ecab	1071	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1072	/* ================ TWI ================ */
Yassinetaouil	46:b1a9de66ecab	1073	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1074
Yassinetaouil	46:b1a9de66ecab	1075
Yassinetaouil	46:b1a9de66ecab	1076	/**
Yassinetaouil	46:b1a9de66ecab	1077	* @brief I2C compatible Two-Wire Interface 0 (TWI)
Yassinetaouil	46:b1a9de66ecab	1078	*/
Yassinetaouil	46:b1a9de66ecab	1079
Yassinetaouil	46:b1a9de66ecab	1080	typedef struct { /!< TWI Structure /
Yassinetaouil	46:b1a9de66ecab	1081	__O uint32_t TASKS_STARTRX; /!< Start TWI receive sequence /
Yassinetaouil	46:b1a9de66ecab	1082	__I uint32_t RESERVED0;
Yassinetaouil	46:b1a9de66ecab	1083	__O uint32_t TASKS_STARTTX; /!< Start TWI transmit sequence /
Yassinetaouil	46:b1a9de66ecab	1084	__I uint32_t RESERVED1[2];
Yassinetaouil	46:b1a9de66ecab	1085	__O uint32_t TASKS_STOP; /!< Stop TWI transaction /
Yassinetaouil	46:b1a9de66ecab	1086	__I uint32_t RESERVED2;
Yassinetaouil	46:b1a9de66ecab	1087	__O uint32_t TASKS_SUSPEND; /!< Suspend TWI transaction /
Yassinetaouil	46:b1a9de66ecab	1088	__O uint32_t TASKS_RESUME; /!< Resume TWI transaction /
Yassinetaouil	46:b1a9de66ecab	1089	__I uint32_t RESERVED3[56];
Yassinetaouil	46:b1a9de66ecab	1090	__IO uint32_t EVENTS_STOPPED; /!< TWI stopped /
Yassinetaouil	46:b1a9de66ecab	1091	__IO uint32_t EVENTS_RXDREADY; /!< TWI RXD byte received /
Yassinetaouil	46:b1a9de66ecab	1092	__I uint32_t RESERVED4[4];
Yassinetaouil	46:b1a9de66ecab	1093	__IO uint32_t EVENTS_TXDSENT; /!< TWI TXD byte sent /
Yassinetaouil	46:b1a9de66ecab	1094	__I uint32_t RESERVED5;
Yassinetaouil	46:b1a9de66ecab	1095	__IO uint32_t EVENTS_ERROR; /!< TWI error /
Yassinetaouil	46:b1a9de66ecab	1096	__I uint32_t RESERVED6[4];
Yassinetaouil	46:b1a9de66ecab	1097	__IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or
Yassinetaouil	46:b1a9de66ecab	1098	received */
Yassinetaouil	46:b1a9de66ecab	1099	__I uint32_t RESERVED7[3];
Yassinetaouil	46:b1a9de66ecab	1100	__IO uint32_t EVENTS_SUSPENDED; /!< TWI entered the suspended state /
Yassinetaouil	46:b1a9de66ecab	1101	__I uint32_t RESERVED8[45];
Yassinetaouil	46:b1a9de66ecab	1102	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1103	__I uint32_t RESERVED9[64];
Yassinetaouil	46:b1a9de66ecab	1104	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1105	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1106	__I uint32_t RESERVED10[110];
Yassinetaouil	46:b1a9de66ecab	1107	__IO uint32_t ERRORSRC; /!< Error source /
Yassinetaouil	46:b1a9de66ecab	1108	__I uint32_t RESERVED11[14];
Yassinetaouil	46:b1a9de66ecab	1109	__IO uint32_t ENABLE; /!< Enable TWI /
Yassinetaouil	46:b1a9de66ecab	1110	__I uint32_t RESERVED12;
Yassinetaouil	46:b1a9de66ecab	1111	__IO uint32_t PSELSCL; /!< Pin select for SCL /
Yassinetaouil	46:b1a9de66ecab	1112	__IO uint32_t PSELSDA; /!< Pin select for SDA /
Yassinetaouil	46:b1a9de66ecab	1113	__I uint32_t RESERVED13[2];
Yassinetaouil	46:b1a9de66ecab	1114	__I uint32_t RXD; /!< RXD register /
Yassinetaouil	46:b1a9de66ecab	1115	__IO uint32_t TXD; /!< TXD register /
Yassinetaouil	46:b1a9de66ecab	1116	__I uint32_t RESERVED14;
Yassinetaouil	46:b1a9de66ecab	1117	__IO uint32_t FREQUENCY; /!< TWI frequency /
Yassinetaouil	46:b1a9de66ecab	1118	__I uint32_t RESERVED15[24];
Yassinetaouil	46:b1a9de66ecab	1119	__IO uint32_t ADDRESS; /!< Address used in the TWI transfer /
Yassinetaouil	46:b1a9de66ecab	1120	} NRF_TWI_Type;
Yassinetaouil	46:b1a9de66ecab	1121
Yassinetaouil	46:b1a9de66ecab	1122
Yassinetaouil	46:b1a9de66ecab	1123	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1124	/* ================ NFCT ================ */
Yassinetaouil	46:b1a9de66ecab	1125	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1126
Yassinetaouil	46:b1a9de66ecab	1127
Yassinetaouil	46:b1a9de66ecab	1128	/**
Yassinetaouil	46:b1a9de66ecab	1129	* @brief NFC-A compatible radio (NFCT)
Yassinetaouil	46:b1a9de66ecab	1130	*/
Yassinetaouil	46:b1a9de66ecab	1131
Yassinetaouil	46:b1a9de66ecab	1132	typedef struct { /!< NFCT Structure /
Yassinetaouil	46:b1a9de66ecab	1133	__O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change
Yassinetaouil	46:b1a9de66ecab	1134	state to activated */
Yassinetaouil	46:b1a9de66ecab	1135	__O uint32_t TASKS_DISABLE; /!< Disable NFC peripheral /
Yassinetaouil	46:b1a9de66ecab	1136	__O uint32_t TASKS_SENSE; /!< Enable NFC sense field mode, change state to sense mode /
Yassinetaouil	46:b1a9de66ecab	1137	__O uint32_t TASKS_STARTTX; /!< Start transmission of a outgoing frame, change state to transmit /
Yassinetaouil	46:b1a9de66ecab	1138	__I uint32_t RESERVED0[3];
Yassinetaouil	46:b1a9de66ecab	1139	__O uint32_t TASKS_ENABLERXDATA; /!< Initializes the EasyDMA for receive. /
Yassinetaouil	46:b1a9de66ecab	1140	__I uint32_t RESERVED1;
Yassinetaouil	46:b1a9de66ecab	1141	__O uint32_t TASKS_GOIDLE; /!< Force state machine to IDLE state /
Yassinetaouil	46:b1a9de66ecab	1142	__O uint32_t TASKS_GOSLEEP; /!< Force state machine to SLEEP_A state /
Yassinetaouil	46:b1a9de66ecab	1143	__I uint32_t RESERVED2[53];
Yassinetaouil	46:b1a9de66ecab	1144	__IO uint32_t EVENTS_READY; /!< The NFC peripheral is ready to receive and send frames /
Yassinetaouil	46:b1a9de66ecab	1145	__IO uint32_t EVENTS_FIELDDETECTED; /!< Remote NFC field detected /
Yassinetaouil	46:b1a9de66ecab	1146	__IO uint32_t EVENTS_FIELDLOST; /!< Remote NFC field lost /
Yassinetaouil	46:b1a9de66ecab	1147	__IO uint32_t EVENTS_TXFRAMESTART; /!< Marks the start of the first symbol of a transmitted frame /
Yassinetaouil	46:b1a9de66ecab	1148	__IO uint32_t EVENTS_TXFRAMEEND; /!< Marks the end of the last transmitted on-air symbol of a frame /
Yassinetaouil	46:b1a9de66ecab	1149	__IO uint32_t EVENTS_RXFRAMESTART; /!< Marks the end of the first symbol of a received frame /
Yassinetaouil	46:b1a9de66ecab	1150	__IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred
Yassinetaouil	46:b1a9de66ecab	1151	to RAM, and EasyDMA has ended accessing the RX buffer */
Yassinetaouil	46:b1a9de66ecab	1152	__IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details
Yassinetaouil	46:b1a9de66ecab	1153	on the source of the error. */
Yassinetaouil	46:b1a9de66ecab	1154	__I uint32_t RESERVED3[2];
Yassinetaouil	46:b1a9de66ecab	1155	__IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
Yassinetaouil	46:b1a9de66ecab	1156	details on the source of the error. */
Yassinetaouil	46:b1a9de66ecab	1157	__IO uint32_t EVENTS_ENDRX; /!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. /
Yassinetaouil	46:b1a9de66ecab	1158	__IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended
Yassinetaouil	46:b1a9de66ecab	1159	accessing the TX buffer */
Yassinetaouil	46:b1a9de66ecab	1160	__I uint32_t RESERVED4;
Yassinetaouil	46:b1a9de66ecab	1161	__IO uint32_t EVENTS_AUTOCOLRESSTARTED; /!< Auto collision resolution process has started /
Yassinetaouil	46:b1a9de66ecab	1162	__I uint32_t RESERVED5[3];
Yassinetaouil	46:b1a9de66ecab	1163	__IO uint32_t EVENTS_COLLISION; /!< NFC Auto collision resolution error reported. /
Yassinetaouil	46:b1a9de66ecab	1164	__IO uint32_t EVENTS_SELECTED; /!< NFC Auto collision resolution successfully completed /
Yassinetaouil	46:b1a9de66ecab	1165	__IO uint32_t EVENTS_STARTED; /!< EasyDMA is ready to receive or send frames. /
Yassinetaouil	46:b1a9de66ecab	1166	__I uint32_t RESERVED6[43];
Yassinetaouil	46:b1a9de66ecab	1167	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1168	__I uint32_t RESERVED7[63];
Yassinetaouil	46:b1a9de66ecab	1169	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1170	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1171	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1172	__I uint32_t RESERVED8[62];
Yassinetaouil	46:b1a9de66ecab	1173	__IO uint32_t ERRORSTATUS; /!< NFC Error Status register /
Yassinetaouil	46:b1a9de66ecab	1174	__I uint32_t RESERVED9;
Yassinetaouil	46:b1a9de66ecab	1175	NFCT_FRAMESTATUS_Type FRAMESTATUS; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1176	__I uint32_t RESERVED10[8];
Yassinetaouil	46:b1a9de66ecab	1177	__I uint32_t CURRENTLOADCTRL; /!< Current value driven to the NFC Load Control /
Yassinetaouil	46:b1a9de66ecab	1178	__I uint32_t RESERVED11[2];
Yassinetaouil	46:b1a9de66ecab	1179	__I uint32_t FIELDPRESENT; /!< Indicates the presence or not of a valid field /
Yassinetaouil	46:b1a9de66ecab	1180	__I uint32_t RESERVED12[49];
Yassinetaouil	46:b1a9de66ecab	1181	__IO uint32_t FRAMEDELAYMIN; /!< Minimum frame delay /
Yassinetaouil	46:b1a9de66ecab	1182	__IO uint32_t FRAMEDELAYMAX; /!< Maximum frame delay /
Yassinetaouil	46:b1a9de66ecab	1183	__IO uint32_t FRAMEDELAYMODE; /!< Configuration register for the Frame Delay Timer /
Yassinetaouil	46:b1a9de66ecab	1184	__IO uint32_t PACKETPTR; /!< Packet pointer for TXD and RXD data storage in Data RAM /
Yassinetaouil	46:b1a9de66ecab	1185	__IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data
Yassinetaouil	46:b1a9de66ecab	1186	RAM */
Yassinetaouil	46:b1a9de66ecab	1187	NFCT_TXD_Type TXD; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1188	NFCT_RXD_Type RXD; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1189	__I uint32_t RESERVED13[26];
Yassinetaouil	46:b1a9de66ecab	1190	__IO uint32_t NFCID1_LAST; /!< Last NFCID1 part (4, 7 or 10 bytes ID) /
Yassinetaouil	46:b1a9de66ecab	1191	__IO uint32_t NFCID1_2ND_LAST; /!< Second last NFCID1 part (7 or 10 bytes ID) /
Yassinetaouil	46:b1a9de66ecab	1192	__IO uint32_t NFCID1_3RD_LAST; /!< Third last NFCID1 part (10 bytes ID) /
Yassinetaouil	46:b1a9de66ecab	1193	__I uint32_t RESERVED14;
Yassinetaouil	46:b1a9de66ecab	1194	__IO uint32_t SENSRES; /!< NFC-A SENS_RES auto-response settings /
Yassinetaouil	46:b1a9de66ecab	1195	__IO uint32_t SELRES; /!< NFC-A SEL_RES auto-response settings /
Yassinetaouil	46:b1a9de66ecab	1196	} NRF_NFCT_Type;
Yassinetaouil	46:b1a9de66ecab	1197
Yassinetaouil	46:b1a9de66ecab	1198
Yassinetaouil	46:b1a9de66ecab	1199	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1200	/* ================ GPIOTE ================ */
Yassinetaouil	46:b1a9de66ecab	1201	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1202
Yassinetaouil	46:b1a9de66ecab	1203
Yassinetaouil	46:b1a9de66ecab	1204	/**
Yassinetaouil	46:b1a9de66ecab	1205	* @brief GPIO Tasks and Events (GPIOTE)
Yassinetaouil	46:b1a9de66ecab	1206	*/
Yassinetaouil	46:b1a9de66ecab	1207
Yassinetaouil	46:b1a9de66ecab	1208	typedef struct { /!< GPIOTE Structure /
Yassinetaouil	46:b1a9de66ecab	1209	__O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified
Yassinetaouil	46:b1a9de66ecab	1210	in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
Yassinetaouil	46:b1a9de66ecab	1211	__I uint32_t RESERVED0[4];
Yassinetaouil	46:b1a9de66ecab	1212	__O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified
Yassinetaouil	46:b1a9de66ecab	1213	in CONFIG[0].PSEL. Action on pin is to set it high. */
Yassinetaouil	46:b1a9de66ecab	1214	__I uint32_t RESERVED1[4];
Yassinetaouil	46:b1a9de66ecab	1215	__O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified
Yassinetaouil	46:b1a9de66ecab	1216	in CONFIG[0].PSEL. Action on pin is to set it low. */
Yassinetaouil	46:b1a9de66ecab	1217	__I uint32_t RESERVED2[32];
Yassinetaouil	46:b1a9de66ecab	1218	__IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified
Yassinetaouil	46:b1a9de66ecab	1219	in CONFIG[0].PSEL */
Yassinetaouil	46:b1a9de66ecab	1220	__I uint32_t RESERVED3[23];
Yassinetaouil	46:b1a9de66ecab	1221	__IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism
Yassinetaouil	46:b1a9de66ecab	1222	enabled */
Yassinetaouil	46:b1a9de66ecab	1223	__I uint32_t RESERVED4[97];
Yassinetaouil	46:b1a9de66ecab	1224	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1225	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1226	__I uint32_t RESERVED5[129];
Yassinetaouil	46:b1a9de66ecab	1227	__IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n]
Yassinetaouil	46:b1a9de66ecab	1228	and CLR[n] tasks and IN[n] event */
Yassinetaouil	46:b1a9de66ecab	1229	} NRF_GPIOTE_Type;
Yassinetaouil	46:b1a9de66ecab	1230
Yassinetaouil	46:b1a9de66ecab	1231
Yassinetaouil	46:b1a9de66ecab	1232	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1233	/* ================ SAADC ================ */
Yassinetaouil	46:b1a9de66ecab	1234	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1235
Yassinetaouil	46:b1a9de66ecab	1236
Yassinetaouil	46:b1a9de66ecab	1237	/**
Yassinetaouil	46:b1a9de66ecab	1238	* @brief Analog to Digital Converter (SAADC)
Yassinetaouil	46:b1a9de66ecab	1239	*/
Yassinetaouil	46:b1a9de66ecab	1240
Yassinetaouil	46:b1a9de66ecab	1241	typedef struct { /!< SAADC Structure /
Yassinetaouil	46:b1a9de66ecab	1242	__O uint32_t TASKS_START; /!< Start the ADC and prepare the result buffer in RAM /
Yassinetaouil	46:b1a9de66ecab	1243	__O uint32_t TASKS_SAMPLE; /!< Take one ADC sample, if scan is enabled all channels are sampled /
Yassinetaouil	46:b1a9de66ecab	1244	__O uint32_t TASKS_STOP; /!< Stop the ADC and terminate any on-going conversion /
Yassinetaouil	46:b1a9de66ecab	1245	__O uint32_t TASKS_CALIBRATEOFFSET; /!< Starts offset auto-calibration /
Yassinetaouil	46:b1a9de66ecab	1246	__I uint32_t RESERVED0[60];
Yassinetaouil	46:b1a9de66ecab	1247	__IO uint32_t EVENTS_STARTED; /!< The ADC has started /
Yassinetaouil	46:b1a9de66ecab	1248	__IO uint32_t EVENTS_END; /!< The ADC has filled up the Result buffer /
Yassinetaouil	46:b1a9de66ecab	1249	__IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode,
Yassinetaouil	46:b1a9de66ecab	1250	multiple conversions might be needed for a result to be transferred
Yassinetaouil	46:b1a9de66ecab	1251	to RAM. */
Yassinetaouil	46:b1a9de66ecab	1252	__IO uint32_t EVENTS_RESULTDONE; /!< A result is ready to get transferred to RAM. /
Yassinetaouil	46:b1a9de66ecab	1253	__IO uint32_t EVENTS_CALIBRATEDONE; /!< Calibration is complete /
Yassinetaouil	46:b1a9de66ecab	1254	__IO uint32_t EVENTS_STOPPED; /!< The ADC has stopped /
Yassinetaouil	46:b1a9de66ecab	1255	SAADC_EVENTS_CH_Type EVENTS_CH[8]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1256	__I uint32_t RESERVED1[106];
Yassinetaouil	46:b1a9de66ecab	1257	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1258	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1259	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1260	__I uint32_t RESERVED2[61];
Yassinetaouil	46:b1a9de66ecab	1261	__I uint32_t STATUS; /!< Status /
Yassinetaouil	46:b1a9de66ecab	1262	__I uint32_t RESERVED3[63];
Yassinetaouil	46:b1a9de66ecab	1263	__IO uint32_t ENABLE; /!< Enable or disable ADC /
Yassinetaouil	46:b1a9de66ecab	1264	__I uint32_t RESERVED4[3];
Yassinetaouil	46:b1a9de66ecab	1265	SAADC_CH_Type CH[8]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1266	__I uint32_t RESERVED5[24];
Yassinetaouil	46:b1a9de66ecab	1267	__IO uint32_t RESOLUTION; /!< Resolution configuration /
Yassinetaouil	46:b1a9de66ecab	1268	__IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined
Yassinetaouil	46:b1a9de66ecab	1269	with SCAN. The RESOLUTION is applied before averaging, thus
Yassinetaouil	46:b1a9de66ecab	1270	for high OVERSAMPLE a higher RESOLUTION should be used. */
Yassinetaouil	46:b1a9de66ecab	1271	__IO uint32_t SAMPLERATE; /!< Controls normal or continuous sample rate /
Yassinetaouil	46:b1a9de66ecab	1272	__I uint32_t RESERVED6[12];
Yassinetaouil	46:b1a9de66ecab	1273	SAADC_RESULT_Type RESULT; /!< RESULT EasyDMA channel /
Yassinetaouil	46:b1a9de66ecab	1274	} NRF_SAADC_Type;
Yassinetaouil	46:b1a9de66ecab	1275
Yassinetaouil	46:b1a9de66ecab	1276
Yassinetaouil	46:b1a9de66ecab	1277	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1278	/* ================ TIMER ================ */
Yassinetaouil	46:b1a9de66ecab	1279	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1280
Yassinetaouil	46:b1a9de66ecab	1281
Yassinetaouil	46:b1a9de66ecab	1282	/**
Yassinetaouil	46:b1a9de66ecab	1283	* @brief Timer/Counter 0 (TIMER)
Yassinetaouil	46:b1a9de66ecab	1284	*/
Yassinetaouil	46:b1a9de66ecab	1285
Yassinetaouil	46:b1a9de66ecab	1286	typedef struct { /!< TIMER Structure /
Yassinetaouil	46:b1a9de66ecab	1287	__O uint32_t TASKS_START; /!< Start Timer /
Yassinetaouil	46:b1a9de66ecab	1288	__O uint32_t TASKS_STOP; /!< Stop Timer /
Yassinetaouil	46:b1a9de66ecab	1289	__O uint32_t TASKS_COUNT; /!< Increment Timer (Counter mode only) /
Yassinetaouil	46:b1a9de66ecab	1290	__O uint32_t TASKS_CLEAR; /!< Clear time /
Yassinetaouil	46:b1a9de66ecab	1291	__O uint32_t TASKS_SHUTDOWN; /!< Deprecated register - Shut down timer /
Yassinetaouil	46:b1a9de66ecab	1292	__I uint32_t RESERVED0[11];
Yassinetaouil	46:b1a9de66ecab	1293	__O uint32_t TASKS_CAPTURE[6]; /!< Description collection[0]: Capture Timer value to CC[0] register /
Yassinetaouil	46:b1a9de66ecab	1294	__I uint32_t RESERVED1[58];
Yassinetaouil	46:b1a9de66ecab	1295	__IO uint32_t EVENTS_COMPARE[6]; /!< Description collection[0]: Compare event on CC[0] match /
Yassinetaouil	46:b1a9de66ecab	1296	__I uint32_t RESERVED2[42];
Yassinetaouil	46:b1a9de66ecab	1297	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1298	__I uint32_t RESERVED3[64];
Yassinetaouil	46:b1a9de66ecab	1299	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1300	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1301	__I uint32_t RESERVED4[126];
Yassinetaouil	46:b1a9de66ecab	1302	__IO uint32_t MODE; /!< Timer mode selection /
Yassinetaouil	46:b1a9de66ecab	1303	__IO uint32_t BITMODE; /!< Configure the number of bits used by the TIMER /
Yassinetaouil	46:b1a9de66ecab	1304	__I uint32_t RESERVED5;
Yassinetaouil	46:b1a9de66ecab	1305	__IO uint32_t PRESCALER; /!< Timer prescaler register /
Yassinetaouil	46:b1a9de66ecab	1306	__I uint32_t RESERVED6[11];
Yassinetaouil	46:b1a9de66ecab	1307	__IO uint32_t CC[6]; /!< Description collection[0]: Capture/Compare register 0 /
Yassinetaouil	46:b1a9de66ecab	1308	} NRF_TIMER_Type;
Yassinetaouil	46:b1a9de66ecab	1309
Yassinetaouil	46:b1a9de66ecab	1310
Yassinetaouil	46:b1a9de66ecab	1311	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1312	/* ================ RTC ================ */
Yassinetaouil	46:b1a9de66ecab	1313	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1314
Yassinetaouil	46:b1a9de66ecab	1315
Yassinetaouil	46:b1a9de66ecab	1316	/**
Yassinetaouil	46:b1a9de66ecab	1317	* @brief Real time counter 0 (RTC)
Yassinetaouil	46:b1a9de66ecab	1318	*/
Yassinetaouil	46:b1a9de66ecab	1319
Yassinetaouil	46:b1a9de66ecab	1320	typedef struct { /!< RTC Structure /
Yassinetaouil	46:b1a9de66ecab	1321	__O uint32_t TASKS_START; /!< Start RTC COUNTER /
Yassinetaouil	46:b1a9de66ecab	1322	__O uint32_t TASKS_STOP; /!< Stop RTC COUNTER /
Yassinetaouil	46:b1a9de66ecab	1323	__O uint32_t TASKS_CLEAR; /!< Clear RTC COUNTER /
Yassinetaouil	46:b1a9de66ecab	1324	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFF0 /
Yassinetaouil	46:b1a9de66ecab	1325	__I uint32_t RESERVED0[60];
Yassinetaouil	46:b1a9de66ecab	1326	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment /
Yassinetaouil	46:b1a9de66ecab	1327	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow /
Yassinetaouil	46:b1a9de66ecab	1328	__I uint32_t RESERVED1[14];
Yassinetaouil	46:b1a9de66ecab	1329	__IO uint32_t EVENTS_COMPARE[4]; /!< Description collection[0]: Compare event on CC[0] match /
Yassinetaouil	46:b1a9de66ecab	1330	__I uint32_t RESERVED2[109];
Yassinetaouil	46:b1a9de66ecab	1331	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1332	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1333	__I uint32_t RESERVED3[13];
Yassinetaouil	46:b1a9de66ecab	1334	__IO uint32_t EVTEN; /!< Enable or disable event routing /
Yassinetaouil	46:b1a9de66ecab	1335	__IO uint32_t EVTENSET; /!< Enable event routing /
Yassinetaouil	46:b1a9de66ecab	1336	__IO uint32_t EVTENCLR; /!< Disable event routing /
Yassinetaouil	46:b1a9de66ecab	1337	__I uint32_t RESERVED4[110];
Yassinetaouil	46:b1a9de66ecab	1338	__I uint32_t COUNTER; /!< Current COUNTER value /
Yassinetaouil	46:b1a9de66ecab	1339	__IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
Yassinetaouil	46:b1a9de66ecab	1340	be written when RTC is stopped */
Yassinetaouil	46:b1a9de66ecab	1341	__I uint32_t RESERVED5[13];
Yassinetaouil	46:b1a9de66ecab	1342	__IO uint32_t CC[4]; /!< Description collection[0]: Compare register 0 /
Yassinetaouil	46:b1a9de66ecab	1343	} NRF_RTC_Type;
Yassinetaouil	46:b1a9de66ecab	1344
Yassinetaouil	46:b1a9de66ecab	1345
Yassinetaouil	46:b1a9de66ecab	1346	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1347	/* ================ TEMP ================ */
Yassinetaouil	46:b1a9de66ecab	1348	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1349
Yassinetaouil	46:b1a9de66ecab	1350
Yassinetaouil	46:b1a9de66ecab	1351	/**
Yassinetaouil	46:b1a9de66ecab	1352	* @brief Temperature Sensor (TEMP)
Yassinetaouil	46:b1a9de66ecab	1353	*/
Yassinetaouil	46:b1a9de66ecab	1354
Yassinetaouil	46:b1a9de66ecab	1355	typedef struct { /!< TEMP Structure /
Yassinetaouil	46:b1a9de66ecab	1356	__O uint32_t TASKS_START; /!< Start temperature measurement /
Yassinetaouil	46:b1a9de66ecab	1357	__O uint32_t TASKS_STOP; /!< Stop temperature measurement /
Yassinetaouil	46:b1a9de66ecab	1358	__I uint32_t RESERVED0[62];
Yassinetaouil	46:b1a9de66ecab	1359	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready /
Yassinetaouil	46:b1a9de66ecab	1360	__I uint32_t RESERVED1[128];
Yassinetaouil	46:b1a9de66ecab	1361	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1362	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1363	__I uint32_t RESERVED2[127];
Yassinetaouil	46:b1a9de66ecab	1364	__I int32_t TEMP; /!< Temperature in degC (0.25deg steps) /
Yassinetaouil	46:b1a9de66ecab	1365	__I uint32_t RESERVED3[5];
Yassinetaouil	46:b1a9de66ecab	1366	__IO uint32_t A0; /!< Slope of 1st piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1367	__IO uint32_t A1; /!< Slope of 2nd piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1368	__IO uint32_t A2; /!< Slope of 3rd piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1369	__IO uint32_t A3; /!< Slope of 4th piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1370	__IO uint32_t A4; /!< Slope of 5th piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1371	__IO uint32_t A5; /!< Slope of 6th piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1372	__I uint32_t RESERVED4[2];
Yassinetaouil	46:b1a9de66ecab	1373	__IO uint32_t B0; /!< y-intercept of 1st piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1374	__IO uint32_t B1; /!< y-intercept of 2nd piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1375	__IO uint32_t B2; /!< y-intercept of 3rd piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1376	__IO uint32_t B3; /!< y-intercept of 4th piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1377	__IO uint32_t B4; /!< y-intercept of 5th piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1378	__IO uint32_t B5; /!< y-intercept of 6th piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1379	__I uint32_t RESERVED5[2];
Yassinetaouil	46:b1a9de66ecab	1380	__IO uint32_t T0; /!< End point of 1st piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1381	__IO uint32_t T1; /!< End point of 2nd piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1382	__IO uint32_t T2; /!< End point of 3rd piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1383	__IO uint32_t T3; /!< End point of 4th piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1384	__IO uint32_t T4; /!< End point of 5th piece wise linear function /
Yassinetaouil	46:b1a9de66ecab	1385	} NRF_TEMP_Type;
Yassinetaouil	46:b1a9de66ecab	1386
Yassinetaouil	46:b1a9de66ecab	1387
Yassinetaouil	46:b1a9de66ecab	1388	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1389	/* ================ RNG ================ */
Yassinetaouil	46:b1a9de66ecab	1390	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1391
Yassinetaouil	46:b1a9de66ecab	1392
Yassinetaouil	46:b1a9de66ecab	1393	/**
Yassinetaouil	46:b1a9de66ecab	1394	* @brief Random Number Generator (RNG)
Yassinetaouil	46:b1a9de66ecab	1395	*/
Yassinetaouil	46:b1a9de66ecab	1396
Yassinetaouil	46:b1a9de66ecab	1397	typedef struct { /!< RNG Structure /
Yassinetaouil	46:b1a9de66ecab	1398	__O uint32_t TASKS_START; /!< Task starting the random number generator /
Yassinetaouil	46:b1a9de66ecab	1399	__O uint32_t TASKS_STOP; /!< Task stopping the random number generator /
Yassinetaouil	46:b1a9de66ecab	1400	__I uint32_t RESERVED0[62];
Yassinetaouil	46:b1a9de66ecab	1401	__IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to
Yassinetaouil	46:b1a9de66ecab	1402	the VALUE register */
Yassinetaouil	46:b1a9de66ecab	1403	__I uint32_t RESERVED1[63];
Yassinetaouil	46:b1a9de66ecab	1404	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1405	__I uint32_t RESERVED2[64];
Yassinetaouil	46:b1a9de66ecab	1406	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1407	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1408	__I uint32_t RESERVED3[126];
Yassinetaouil	46:b1a9de66ecab	1409	__IO uint32_t CONFIG; /!< Configuration register /
Yassinetaouil	46:b1a9de66ecab	1410	__I uint32_t VALUE; /!< Output random number /
Yassinetaouil	46:b1a9de66ecab	1411	} NRF_RNG_Type;
Yassinetaouil	46:b1a9de66ecab	1412
Yassinetaouil	46:b1a9de66ecab	1413
Yassinetaouil	46:b1a9de66ecab	1414	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1415	/* ================ ECB ================ */
Yassinetaouil	46:b1a9de66ecab	1416	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1417
Yassinetaouil	46:b1a9de66ecab	1418
Yassinetaouil	46:b1a9de66ecab	1419	/**
Yassinetaouil	46:b1a9de66ecab	1420	* @brief AES ECB Mode Encryption (ECB)
Yassinetaouil	46:b1a9de66ecab	1421	*/
Yassinetaouil	46:b1a9de66ecab	1422
Yassinetaouil	46:b1a9de66ecab	1423	typedef struct { /!< ECB Structure /
Yassinetaouil	46:b1a9de66ecab	1424	__O uint32_t TASKS_STARTECB; /!< Start ECB block encrypt /
Yassinetaouil	46:b1a9de66ecab	1425	__O uint32_t TASKS_STOPECB; /!< Abort a possible executing ECB operation /
Yassinetaouil	46:b1a9de66ecab	1426	__I uint32_t RESERVED0[62];
Yassinetaouil	46:b1a9de66ecab	1427	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete /
Yassinetaouil	46:b1a9de66ecab	1428	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to
Yassinetaouil	46:b1a9de66ecab	1429	an error */
Yassinetaouil	46:b1a9de66ecab	1430	__I uint32_t RESERVED1[127];
Yassinetaouil	46:b1a9de66ecab	1431	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1432	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1433	__I uint32_t RESERVED2[126];
Yassinetaouil	46:b1a9de66ecab	1434	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointers /
Yassinetaouil	46:b1a9de66ecab	1435	} NRF_ECB_Type;
Yassinetaouil	46:b1a9de66ecab	1436
Yassinetaouil	46:b1a9de66ecab	1437
Yassinetaouil	46:b1a9de66ecab	1438	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1439	/* ================ CCM ================ */
Yassinetaouil	46:b1a9de66ecab	1440	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1441
Yassinetaouil	46:b1a9de66ecab	1442
Yassinetaouil	46:b1a9de66ecab	1443	/**
Yassinetaouil	46:b1a9de66ecab	1444	* @brief AES CCM Mode Encryption (CCM)
Yassinetaouil	46:b1a9de66ecab	1445	*/
Yassinetaouil	46:b1a9de66ecab	1446
Yassinetaouil	46:b1a9de66ecab	1447	typedef struct { /!< CCM Structure /
Yassinetaouil	46:b1a9de66ecab	1448	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Yassinetaouil	46:b1a9de66ecab	1449	itself when completed. */
Yassinetaouil	46:b1a9de66ecab	1450	__O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself
Yassinetaouil	46:b1a9de66ecab	1451	when completed. */
Yassinetaouil	46:b1a9de66ecab	1452	__O uint32_t TASKS_STOP; /!< Stop encryption/decryption /
Yassinetaouil	46:b1a9de66ecab	1453	__I uint32_t RESERVED0[61];
Yassinetaouil	46:b1a9de66ecab	1454	__IO uint32_t EVENTS_ENDKSGEN; /!< Key-stream generation complete /
Yassinetaouil	46:b1a9de66ecab	1455	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt complete /
Yassinetaouil	46:b1a9de66ecab	1456	__IO uint32_t EVENTS_ERROR; /!< CCM error event /
Yassinetaouil	46:b1a9de66ecab	1457	__I uint32_t RESERVED1[61];
Yassinetaouil	46:b1a9de66ecab	1458	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1459	__I uint32_t RESERVED2[64];
Yassinetaouil	46:b1a9de66ecab	1460	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1461	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1462	__I uint32_t RESERVED3[61];
Yassinetaouil	46:b1a9de66ecab	1463	__I uint32_t MICSTATUS; /!< MIC check result /
Yassinetaouil	46:b1a9de66ecab	1464	__I uint32_t RESERVED4[63];
Yassinetaouil	46:b1a9de66ecab	1465	__IO uint32_t ENABLE; /!< Enable /
Yassinetaouil	46:b1a9de66ecab	1466	__IO uint32_t MODE; /!< Operation mode /
Yassinetaouil	46:b1a9de66ecab	1467	__IO uint32_t CNFPTR; /!< Pointer to data structure holding AES key and NONCE vector /
Yassinetaouil	46:b1a9de66ecab	1468	__IO uint32_t INPTR; /!< Input pointer /
Yassinetaouil	46:b1a9de66ecab	1469	__IO uint32_t OUTPTR; /!< Output pointer /
Yassinetaouil	46:b1a9de66ecab	1470	__IO uint32_t SCRATCHPTR; /!< Pointer to data area used for temporary storage /
Yassinetaouil	46:b1a9de66ecab	1471	} NRF_CCM_Type;
Yassinetaouil	46:b1a9de66ecab	1472
Yassinetaouil	46:b1a9de66ecab	1473
Yassinetaouil	46:b1a9de66ecab	1474	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1475	/* ================ AAR ================ */
Yassinetaouil	46:b1a9de66ecab	1476	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1477
Yassinetaouil	46:b1a9de66ecab	1478
Yassinetaouil	46:b1a9de66ecab	1479	/**
Yassinetaouil	46:b1a9de66ecab	1480	* @brief Accelerated Address Resolver (AAR)
Yassinetaouil	46:b1a9de66ecab	1481	*/
Yassinetaouil	46:b1a9de66ecab	1482
Yassinetaouil	46:b1a9de66ecab	1483	typedef struct { /!< AAR Structure /
Yassinetaouil	46:b1a9de66ecab	1484	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Yassinetaouil	46:b1a9de66ecab	1485	data structure */
Yassinetaouil	46:b1a9de66ecab	1486	__I uint32_t RESERVED0;
Yassinetaouil	46:b1a9de66ecab	1487	__O uint32_t TASKS_STOP; /!< Stop resolving addresses /
Yassinetaouil	46:b1a9de66ecab	1488	__I uint32_t RESERVED1[61];
Yassinetaouil	46:b1a9de66ecab	1489	__IO uint32_t EVENTS_END; /!< Address resolution procedure complete /
Yassinetaouil	46:b1a9de66ecab	1490	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved /
Yassinetaouil	46:b1a9de66ecab	1491	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved /
Yassinetaouil	46:b1a9de66ecab	1492	__I uint32_t RESERVED2[126];
Yassinetaouil	46:b1a9de66ecab	1493	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1494	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1495	__I uint32_t RESERVED3[61];
Yassinetaouil	46:b1a9de66ecab	1496	__I uint32_t STATUS; /!< Resolution status /
Yassinetaouil	46:b1a9de66ecab	1497	__I uint32_t RESERVED4[63];
Yassinetaouil	46:b1a9de66ecab	1498	__IO uint32_t ENABLE; /!< Enable AAR /
Yassinetaouil	46:b1a9de66ecab	1499	__IO uint32_t NIRK; /!< Number of IRKs /
Yassinetaouil	46:b1a9de66ecab	1500	__IO uint32_t IRKPTR; /!< Pointer to IRK data structure /
Yassinetaouil	46:b1a9de66ecab	1501	__I uint32_t RESERVED5;
Yassinetaouil	46:b1a9de66ecab	1502	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address /
Yassinetaouil	46:b1a9de66ecab	1503	__IO uint32_t SCRATCHPTR; /!< Pointer to data area used for temporary storage /
Yassinetaouil	46:b1a9de66ecab	1504	} NRF_AAR_Type;
Yassinetaouil	46:b1a9de66ecab	1505
Yassinetaouil	46:b1a9de66ecab	1506
Yassinetaouil	46:b1a9de66ecab	1507	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1508	/* ================ WDT ================ */
Yassinetaouil	46:b1a9de66ecab	1509	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1510
Yassinetaouil	46:b1a9de66ecab	1511
Yassinetaouil	46:b1a9de66ecab	1512	/**
Yassinetaouil	46:b1a9de66ecab	1513	* @brief Watchdog Timer (WDT)
Yassinetaouil	46:b1a9de66ecab	1514	*/
Yassinetaouil	46:b1a9de66ecab	1515
Yassinetaouil	46:b1a9de66ecab	1516	typedef struct { /!< WDT Structure /
Yassinetaouil	46:b1a9de66ecab	1517	__O uint32_t TASKS_START; /!< Start the watchdog /
Yassinetaouil	46:b1a9de66ecab	1518	__I uint32_t RESERVED0[63];
Yassinetaouil	46:b1a9de66ecab	1519	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout /
Yassinetaouil	46:b1a9de66ecab	1520	__I uint32_t RESERVED1[128];
Yassinetaouil	46:b1a9de66ecab	1521	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1522	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1523	__I uint32_t RESERVED2[61];
Yassinetaouil	46:b1a9de66ecab	1524	__I uint32_t RUNSTATUS; /!< Run status /
Yassinetaouil	46:b1a9de66ecab	1525	__I uint32_t REQSTATUS; /!< Request status /
Yassinetaouil	46:b1a9de66ecab	1526	__I uint32_t RESERVED3[63];
Yassinetaouil	46:b1a9de66ecab	1527	__IO uint32_t CRV; /!< Counter reload value /
Yassinetaouil	46:b1a9de66ecab	1528	__IO uint32_t RREN; /!< Enable register for reload request registers /
Yassinetaouil	46:b1a9de66ecab	1529	__IO uint32_t CONFIG; /!< Configuration register /
Yassinetaouil	46:b1a9de66ecab	1530	__I uint32_t RESERVED4[60];
Yassinetaouil	46:b1a9de66ecab	1531	__O uint32_t RR[8]; /!< Description collection[0]: Reload request 0 /
Yassinetaouil	46:b1a9de66ecab	1532	} NRF_WDT_Type;
Yassinetaouil	46:b1a9de66ecab	1533
Yassinetaouil	46:b1a9de66ecab	1534
Yassinetaouil	46:b1a9de66ecab	1535	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1536	/* ================ QDEC ================ */
Yassinetaouil	46:b1a9de66ecab	1537	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1538
Yassinetaouil	46:b1a9de66ecab	1539
Yassinetaouil	46:b1a9de66ecab	1540	/**
Yassinetaouil	46:b1a9de66ecab	1541	* @brief Quadrature Decoder (QDEC)
Yassinetaouil	46:b1a9de66ecab	1542	*/
Yassinetaouil	46:b1a9de66ecab	1543
Yassinetaouil	46:b1a9de66ecab	1544	typedef struct { /!< QDEC Structure /
Yassinetaouil	46:b1a9de66ecab	1545	__O uint32_t TASKS_START; /!< Task starting the quadrature decoder /
Yassinetaouil	46:b1a9de66ecab	1546	__O uint32_t TASKS_STOP; /!< Task stopping the quadrature decoder /
Yassinetaouil	46:b1a9de66ecab	1547	__O uint32_t TASKS_READCLRACC; /!< Read and clear ACC and ACCDBL /
Yassinetaouil	46:b1a9de66ecab	1548	__O uint32_t TASKS_RDCLRACC; /!< Read and clear ACC /
Yassinetaouil	46:b1a9de66ecab	1549	__O uint32_t TASKS_RDCLRDBL; /!< Read and clear ACCDBL /
Yassinetaouil	46:b1a9de66ecab	1550	__I uint32_t RESERVED0[59];
Yassinetaouil	46:b1a9de66ecab	1551	__IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to
Yassinetaouil	46:b1a9de66ecab	1552	the SAMPLE register */
Yassinetaouil	46:b1a9de66ecab	1553	__IO uint32_t EVENTS_REPORTRDY; /!< Non-null report ready /
Yassinetaouil	46:b1a9de66ecab	1554	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow /
Yassinetaouil	46:b1a9de66ecab	1555	__IO uint32_t EVENTS_DBLRDY; /!< Double displacement(s) detected /
Yassinetaouil	46:b1a9de66ecab	1556	__IO uint32_t EVENTS_STOPPED; /!< QDEC has been stopped /
Yassinetaouil	46:b1a9de66ecab	1557	__I uint32_t RESERVED1[59];
Yassinetaouil	46:b1a9de66ecab	1558	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1559	__I uint32_t RESERVED2[64];
Yassinetaouil	46:b1a9de66ecab	1560	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1561	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1562	__I uint32_t RESERVED3[125];
Yassinetaouil	46:b1a9de66ecab	1563	__IO uint32_t ENABLE; /!< Enable the quadrature decoder /
Yassinetaouil	46:b1a9de66ecab	1564	__IO uint32_t LEDPOL; /!< LED output pin polarity /
Yassinetaouil	46:b1a9de66ecab	1565	__IO uint32_t SAMPLEPER; /!< Sample period /
Yassinetaouil	46:b1a9de66ecab	1566	__I int32_t SAMPLE; /!< Motion sample value /
Yassinetaouil	46:b1a9de66ecab	1567	__IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
Yassinetaouil	46:b1a9de66ecab	1568	can be generated */
Yassinetaouil	46:b1a9de66ecab	1569	__I int32_t ACC; /!< Register accumulating the valid transitions /
Yassinetaouil	46:b1a9de66ecab	1570	__I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
Yassinetaouil	46:b1a9de66ecab	1571	task */
Yassinetaouil	46:b1a9de66ecab	1572	QDEC_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1573	__IO uint32_t DBFEN; /!< Enable input debounce filters /
Yassinetaouil	46:b1a9de66ecab	1574	__I uint32_t RESERVED4[5];
Yassinetaouil	46:b1a9de66ecab	1575	__IO uint32_t LEDPRE; /!< Time period the LED is switched ON prior to sampling /
Yassinetaouil	46:b1a9de66ecab	1576	__I uint32_t ACCDBL; /!< Register accumulating the number of detected double transitions /
Yassinetaouil	46:b1a9de66ecab	1577	__I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
Yassinetaouil	46:b1a9de66ecab	1578	task */
Yassinetaouil	46:b1a9de66ecab	1579	} NRF_QDEC_Type;
Yassinetaouil	46:b1a9de66ecab	1580
Yassinetaouil	46:b1a9de66ecab	1581
Yassinetaouil	46:b1a9de66ecab	1582	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1583	/* ================ COMP ================ */
Yassinetaouil	46:b1a9de66ecab	1584	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1585
Yassinetaouil	46:b1a9de66ecab	1586
Yassinetaouil	46:b1a9de66ecab	1587	/**
Yassinetaouil	46:b1a9de66ecab	1588	* @brief Comparator (COMP)
Yassinetaouil	46:b1a9de66ecab	1589	*/
Yassinetaouil	46:b1a9de66ecab	1590
Yassinetaouil	46:b1a9de66ecab	1591	typedef struct { /!< COMP Structure /
Yassinetaouil	46:b1a9de66ecab	1592	__O uint32_t TASKS_START; /!< Start comparator /
Yassinetaouil	46:b1a9de66ecab	1593	__O uint32_t TASKS_STOP; /!< Stop comparator /
Yassinetaouil	46:b1a9de66ecab	1594	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value /
Yassinetaouil	46:b1a9de66ecab	1595	__I uint32_t RESERVED0[61];
Yassinetaouil	46:b1a9de66ecab	1596	__IO uint32_t EVENTS_READY; /!< COMP is ready and output is valid /
Yassinetaouil	46:b1a9de66ecab	1597	__IO uint32_t EVENTS_DOWN; /!< Downward crossing /
Yassinetaouil	46:b1a9de66ecab	1598	__IO uint32_t EVENTS_UP; /!< Upward crossing /
Yassinetaouil	46:b1a9de66ecab	1599	__IO uint32_t EVENTS_CROSS; /!< Downward or upward crossing /
Yassinetaouil	46:b1a9de66ecab	1600	__I uint32_t RESERVED1[60];
Yassinetaouil	46:b1a9de66ecab	1601	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1602	__I uint32_t RESERVED2[63];
Yassinetaouil	46:b1a9de66ecab	1603	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1604	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1605	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1606	__I uint32_t RESERVED3[61];
Yassinetaouil	46:b1a9de66ecab	1607	__I uint32_t RESULT; /!< Compare result /
Yassinetaouil	46:b1a9de66ecab	1608	__I uint32_t RESERVED4[63];
Yassinetaouil	46:b1a9de66ecab	1609	__IO uint32_t ENABLE; /!< COMP enable /
Yassinetaouil	46:b1a9de66ecab	1610	__IO uint32_t PSEL; /!< Pin select /
Yassinetaouil	46:b1a9de66ecab	1611	__IO uint32_t REFSEL; /!< Reference source select /
Yassinetaouil	46:b1a9de66ecab	1612	__IO uint32_t EXTREFSEL; /!< External reference select /
Yassinetaouil	46:b1a9de66ecab	1613	__I uint32_t RESERVED5[8];
Yassinetaouil	46:b1a9de66ecab	1614	__IO uint32_t TH; /!< Threshold configuration for hysteresis unit /
Yassinetaouil	46:b1a9de66ecab	1615	__IO uint32_t MODE; /!< Mode configuration /
Yassinetaouil	46:b1a9de66ecab	1616	__IO uint32_t HYST; /!< Comparator hysteresis enable /
Yassinetaouil	46:b1a9de66ecab	1617	__IO uint32_t ISOURCE; /!< Current source select on analog input /
Yassinetaouil	46:b1a9de66ecab	1618	} NRF_COMP_Type;
Yassinetaouil	46:b1a9de66ecab	1619
Yassinetaouil	46:b1a9de66ecab	1620
Yassinetaouil	46:b1a9de66ecab	1621	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1622	/* ================ LPCOMP ================ */
Yassinetaouil	46:b1a9de66ecab	1623	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1624
Yassinetaouil	46:b1a9de66ecab	1625
Yassinetaouil	46:b1a9de66ecab	1626	/**
Yassinetaouil	46:b1a9de66ecab	1627	* @brief Low Power Comparator (LPCOMP)
Yassinetaouil	46:b1a9de66ecab	1628	*/
Yassinetaouil	46:b1a9de66ecab	1629
Yassinetaouil	46:b1a9de66ecab	1630	typedef struct { /!< LPCOMP Structure /
Yassinetaouil	46:b1a9de66ecab	1631	__O uint32_t TASKS_START; /!< Start comparator /
Yassinetaouil	46:b1a9de66ecab	1632	__O uint32_t TASKS_STOP; /!< Stop comparator /
Yassinetaouil	46:b1a9de66ecab	1633	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value /
Yassinetaouil	46:b1a9de66ecab	1634	__I uint32_t RESERVED0[61];
Yassinetaouil	46:b1a9de66ecab	1635	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid /
Yassinetaouil	46:b1a9de66ecab	1636	__IO uint32_t EVENTS_DOWN; /!< Downward crossing /
Yassinetaouil	46:b1a9de66ecab	1637	__IO uint32_t EVENTS_UP; /!< Upward crossing /
Yassinetaouil	46:b1a9de66ecab	1638	__IO uint32_t EVENTS_CROSS; /!< Downward or upward crossing /
Yassinetaouil	46:b1a9de66ecab	1639	__I uint32_t RESERVED1[60];
Yassinetaouil	46:b1a9de66ecab	1640	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1641	__I uint32_t RESERVED2[64];
Yassinetaouil	46:b1a9de66ecab	1642	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1643	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1644	__I uint32_t RESERVED3[61];
Yassinetaouil	46:b1a9de66ecab	1645	__I uint32_t RESULT; /!< Compare result /
Yassinetaouil	46:b1a9de66ecab	1646	__I uint32_t RESERVED4[63];
Yassinetaouil	46:b1a9de66ecab	1647	__IO uint32_t ENABLE; /!< Enable LPCOMP /
Yassinetaouil	46:b1a9de66ecab	1648	__IO uint32_t PSEL; /!< Input pin select /
Yassinetaouil	46:b1a9de66ecab	1649	__IO uint32_t REFSEL; /!< Reference select /
Yassinetaouil	46:b1a9de66ecab	1650	__IO uint32_t EXTREFSEL; /!< External reference select /
Yassinetaouil	46:b1a9de66ecab	1651	__I uint32_t RESERVED5[4];
Yassinetaouil	46:b1a9de66ecab	1652	__IO uint32_t ANADETECT; /!< Analog detect configuration /
Yassinetaouil	46:b1a9de66ecab	1653	__I uint32_t RESERVED6[5];
Yassinetaouil	46:b1a9de66ecab	1654	__IO uint32_t HYST; /!< Comparator hysteresis enable /
Yassinetaouil	46:b1a9de66ecab	1655	} NRF_LPCOMP_Type;
Yassinetaouil	46:b1a9de66ecab	1656
Yassinetaouil	46:b1a9de66ecab	1657
Yassinetaouil	46:b1a9de66ecab	1658	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1659	/* ================ SWI ================ */
Yassinetaouil	46:b1a9de66ecab	1660	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1661
Yassinetaouil	46:b1a9de66ecab	1662
Yassinetaouil	46:b1a9de66ecab	1663	/**
Yassinetaouil	46:b1a9de66ecab	1664	* @brief Software interrupt 0 (SWI)
Yassinetaouil	46:b1a9de66ecab	1665	*/
Yassinetaouil	46:b1a9de66ecab	1666
Yassinetaouil	46:b1a9de66ecab	1667	typedef struct { /!< SWI Structure /
Yassinetaouil	46:b1a9de66ecab	1668	__I uint32_t UNUSED; /!< Unused. /
Yassinetaouil	46:b1a9de66ecab	1669	} NRF_SWI_Type;
Yassinetaouil	46:b1a9de66ecab	1670
Yassinetaouil	46:b1a9de66ecab	1671
Yassinetaouil	46:b1a9de66ecab	1672	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1673	/* ================ EGU ================ */
Yassinetaouil	46:b1a9de66ecab	1674	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1675
Yassinetaouil	46:b1a9de66ecab	1676
Yassinetaouil	46:b1a9de66ecab	1677	/**
Yassinetaouil	46:b1a9de66ecab	1678	* @brief Event Generator Unit 0 (EGU)
Yassinetaouil	46:b1a9de66ecab	1679	*/
Yassinetaouil	46:b1a9de66ecab	1680
Yassinetaouil	46:b1a9de66ecab	1681	typedef struct { /!< EGU Structure /
Yassinetaouil	46:b1a9de66ecab	1682	__O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding
Yassinetaouil	46:b1a9de66ecab	1683	TRIGGERED[0] event */
Yassinetaouil	46:b1a9de66ecab	1684	__I uint32_t RESERVED0[48];
Yassinetaouil	46:b1a9de66ecab	1685	__IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering
Yassinetaouil	46:b1a9de66ecab	1686	the corresponding TRIGGER[0] task */
Yassinetaouil	46:b1a9de66ecab	1687	__I uint32_t RESERVED1[112];
Yassinetaouil	46:b1a9de66ecab	1688	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1689	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1690	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1691	} NRF_EGU_Type;
Yassinetaouil	46:b1a9de66ecab	1692
Yassinetaouil	46:b1a9de66ecab	1693
Yassinetaouil	46:b1a9de66ecab	1694	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1695	/* ================ PWM ================ */
Yassinetaouil	46:b1a9de66ecab	1696	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1697
Yassinetaouil	46:b1a9de66ecab	1698
Yassinetaouil	46:b1a9de66ecab	1699	/**
Yassinetaouil	46:b1a9de66ecab	1700	* @brief Pulse Width Modulation Unit 0 (PWM)
Yassinetaouil	46:b1a9de66ecab	1701	*/
Yassinetaouil	46:b1a9de66ecab	1702
Yassinetaouil	46:b1a9de66ecab	1703	typedef struct { /!< PWM Structure /
Yassinetaouil	46:b1a9de66ecab	1704	__I uint32_t RESERVED0;
Yassinetaouil	46:b1a9de66ecab	1705	__O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current
Yassinetaouil	46:b1a9de66ecab	1706	PWM period, and stops sequence playback */
Yassinetaouil	46:b1a9de66ecab	1707	__O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all
Yassinetaouil	46:b1a9de66ecab	1708	enabled channels from sequence 0, and starts playing that sequence
Yassinetaouil	46:b1a9de66ecab	1709	at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
Yassinetaouil	46:b1a9de66ecab	1710	PWM generation to start it was not running. */
Yassinetaouil	46:b1a9de66ecab	1711	__O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels
Yassinetaouil	46:b1a9de66ecab	1712	if DECODER.MODE=NextStep. Does not cause PWM generation to start
Yassinetaouil	46:b1a9de66ecab	1713	it was not running. */
Yassinetaouil	46:b1a9de66ecab	1714	__I uint32_t RESERVED1[60];
Yassinetaouil	46:b1a9de66ecab	1715	__IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer
Yassinetaouil	46:b1a9de66ecab	1716	generated */
Yassinetaouil	46:b1a9de66ecab	1717	__IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence
Yassinetaouil	46:b1a9de66ecab	1718	0 */
Yassinetaouil	46:b1a9de66ecab	1719	__IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence
Yassinetaouil	46:b1a9de66ecab	1720	0, when last value from RAM has been applied to wave counter */
Yassinetaouil	46:b1a9de66ecab	1721	__IO uint32_t EVENTS_PWMPERIODEND; /!< Emitted at the end of each PWM period /
Yassinetaouil	46:b1a9de66ecab	1722	__IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times
Yassinetaouil	46:b1a9de66ecab	1723	defined in LOOP.CNT */
Yassinetaouil	46:b1a9de66ecab	1724	__I uint32_t RESERVED2[56];
Yassinetaouil	46:b1a9de66ecab	1725	__IO uint32_t SHORTS; /!< Shortcut register /
Yassinetaouil	46:b1a9de66ecab	1726	__I uint32_t RESERVED3[63];
Yassinetaouil	46:b1a9de66ecab	1727	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1728	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1729	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1730	__I uint32_t RESERVED4[125];
Yassinetaouil	46:b1a9de66ecab	1731	__IO uint32_t ENABLE; /!< PWM module enable register /
Yassinetaouil	46:b1a9de66ecab	1732	__IO uint32_t MODE; /!< Selects operating mode of the wave counter /
Yassinetaouil	46:b1a9de66ecab	1733	__IO uint32_t COUNTERTOP; /!< Value up to which the pulse generator counter counts /
Yassinetaouil	46:b1a9de66ecab	1734	__IO uint32_t PRESCALER; /!< Configuration for PWM_CLK /
Yassinetaouil	46:b1a9de66ecab	1735	__IO uint32_t DECODER; /!< Configuration of the decoder /
Yassinetaouil	46:b1a9de66ecab	1736	__IO uint32_t LOOP; /!< Amount of playback of a loop /
Yassinetaouil	46:b1a9de66ecab	1737	__I uint32_t RESERVED5[2];
Yassinetaouil	46:b1a9de66ecab	1738	PWM_SEQ_Type SEQ[2]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1739	PWM_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1740	} NRF_PWM_Type;
Yassinetaouil	46:b1a9de66ecab	1741
Yassinetaouil	46:b1a9de66ecab	1742
Yassinetaouil	46:b1a9de66ecab	1743	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1744	/* ================ PDM ================ */
Yassinetaouil	46:b1a9de66ecab	1745	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1746
Yassinetaouil	46:b1a9de66ecab	1747
Yassinetaouil	46:b1a9de66ecab	1748	/**
Yassinetaouil	46:b1a9de66ecab	1749	* @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
Yassinetaouil	46:b1a9de66ecab	1750	*/
Yassinetaouil	46:b1a9de66ecab	1751
Yassinetaouil	46:b1a9de66ecab	1752	typedef struct { /!< PDM Structure /
Yassinetaouil	46:b1a9de66ecab	1753	__O uint32_t TASKS_START; /!< Starts continuous PDM transfer /
Yassinetaouil	46:b1a9de66ecab	1754	__O uint32_t TASKS_STOP; /!< Stops PDM transfer /
Yassinetaouil	46:b1a9de66ecab	1755	__I uint32_t RESERVED0[62];
Yassinetaouil	46:b1a9de66ecab	1756	__IO uint32_t EVENTS_STARTED; /!< PDM transfer has started /
Yassinetaouil	46:b1a9de66ecab	1757	__IO uint32_t EVENTS_STOPPED; /!< PDM transfer has finished /
Yassinetaouil	46:b1a9de66ecab	1758	__IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
Yassinetaouil	46:b1a9de66ecab	1759	(or the last sample after a STOP task has been received) to
Yassinetaouil	46:b1a9de66ecab	1760	Data RAM */
Yassinetaouil	46:b1a9de66ecab	1761	__I uint32_t RESERVED1[125];
Yassinetaouil	46:b1a9de66ecab	1762	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1763	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1764	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1765	__I uint32_t RESERVED2[125];
Yassinetaouil	46:b1a9de66ecab	1766	__IO uint32_t ENABLE; /!< PDM module enable register /
Yassinetaouil	46:b1a9de66ecab	1767	__IO uint32_t PDMCLKCTRL; /!< PDM clock generator control /
Yassinetaouil	46:b1a9de66ecab	1768	__IO uint32_t MODE; /!< Defines the routing of the connected PDM microphones' signals /
Yassinetaouil	46:b1a9de66ecab	1769	__I uint32_t RESERVED3[3];
Yassinetaouil	46:b1a9de66ecab	1770	__IO uint32_t GAINL; /!< Left output gain adjustment /
Yassinetaouil	46:b1a9de66ecab	1771	__IO uint32_t GAINR; /!< Right output gain adjustment /
Yassinetaouil	46:b1a9de66ecab	1772	__I uint32_t RESERVED4[8];
Yassinetaouil	46:b1a9de66ecab	1773	PDM_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1774	__I uint32_t RESERVED5[6];
Yassinetaouil	46:b1a9de66ecab	1775	PDM_SAMPLE_Type SAMPLE; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1776	} NRF_PDM_Type;
Yassinetaouil	46:b1a9de66ecab	1777
Yassinetaouil	46:b1a9de66ecab	1778
Yassinetaouil	46:b1a9de66ecab	1779	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1780	/* ================ NVMC ================ */
Yassinetaouil	46:b1a9de66ecab	1781	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1782
Yassinetaouil	46:b1a9de66ecab	1783
Yassinetaouil	46:b1a9de66ecab	1784	/**
Yassinetaouil	46:b1a9de66ecab	1785	* @brief Non Volatile Memory Controller (NVMC)
Yassinetaouil	46:b1a9de66ecab	1786	*/
Yassinetaouil	46:b1a9de66ecab	1787
Yassinetaouil	46:b1a9de66ecab	1788	typedef struct { /!< NVMC Structure /
Yassinetaouil	46:b1a9de66ecab	1789	__I uint32_t RESERVED0[256];
Yassinetaouil	46:b1a9de66ecab	1790	__I uint32_t READY; /!< Ready flag /
Yassinetaouil	46:b1a9de66ecab	1791	__I uint32_t RESERVED1[64];
Yassinetaouil	46:b1a9de66ecab	1792	__IO uint32_t CONFIG; /!< Configuration register /
Yassinetaouil	46:b1a9de66ecab	1793
Yassinetaouil	46:b1a9de66ecab	1794	union {
Yassinetaouil	46:b1a9de66ecab	1795	__IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area.
Yassinetaouil	46:b1a9de66ecab	1796	Equivalent to ERASEPAGE. */
Yassinetaouil	46:b1a9de66ecab	1797	__IO uint32_t ERASEPAGE; /!< Register for erasing a page in Code area /
Yassinetaouil	46:b1a9de66ecab	1798	};
Yassinetaouil	46:b1a9de66ecab	1799	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory /
Yassinetaouil	46:b1a9de66ecab	1800	__IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area.
Yassinetaouil	46:b1a9de66ecab	1801	Equivalent to ERASEPAGE. */
Yassinetaouil	46:b1a9de66ecab	1802	__IO uint32_t ERASEUICR; /!< Register for erasing User Information Configuration Registers /
Yassinetaouil	46:b1a9de66ecab	1803	__I uint32_t RESERVED2[10];
Yassinetaouil	46:b1a9de66ecab	1804	__IO uint32_t ICACHECNF; /!< I-Code cache configuration register. /
Yassinetaouil	46:b1a9de66ecab	1805	__I uint32_t RESERVED3;
Yassinetaouil	46:b1a9de66ecab	1806	__IO uint32_t IHIT; /!< I-Code cache hit counter. /
Yassinetaouil	46:b1a9de66ecab	1807	__IO uint32_t IMISS; /!< I-Code cache miss counter. /
Yassinetaouil	46:b1a9de66ecab	1808	} NRF_NVMC_Type;
Yassinetaouil	46:b1a9de66ecab	1809
Yassinetaouil	46:b1a9de66ecab	1810
Yassinetaouil	46:b1a9de66ecab	1811	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1812	/* ================ PPI ================ */
Yassinetaouil	46:b1a9de66ecab	1813	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1814
Yassinetaouil	46:b1a9de66ecab	1815
Yassinetaouil	46:b1a9de66ecab	1816	/**
Yassinetaouil	46:b1a9de66ecab	1817	* @brief Programmable Peripheral Interconnect (PPI)
Yassinetaouil	46:b1a9de66ecab	1818	*/
Yassinetaouil	46:b1a9de66ecab	1819
Yassinetaouil	46:b1a9de66ecab	1820	typedef struct { /!< PPI Structure /
Yassinetaouil	46:b1a9de66ecab	1821	PPI_TASKS_CHG_Type TASKS_CHG[6]; /!< Channel group tasks /
Yassinetaouil	46:b1a9de66ecab	1822	__I uint32_t RESERVED0[308];
Yassinetaouil	46:b1a9de66ecab	1823	__IO uint32_t CHEN; /!< Channel enable register /
Yassinetaouil	46:b1a9de66ecab	1824	__IO uint32_t CHENSET; /!< Channel enable set register /
Yassinetaouil	46:b1a9de66ecab	1825	__IO uint32_t CHENCLR; /!< Channel enable clear register /
Yassinetaouil	46:b1a9de66ecab	1826	__I uint32_t RESERVED1;
Yassinetaouil	46:b1a9de66ecab	1827	PPI_CH_Type CH[20]; /!< PPI Channel /
Yassinetaouil	46:b1a9de66ecab	1828	__I uint32_t RESERVED2[148];
Yassinetaouil	46:b1a9de66ecab	1829	__IO uint32_t CHG[6]; /!< Description collection[0]: Channel group 0 /
Yassinetaouil	46:b1a9de66ecab	1830	__I uint32_t RESERVED3[62];
Yassinetaouil	46:b1a9de66ecab	1831	PPI_FORK_Type FORK[32]; /!< Fork /
Yassinetaouil	46:b1a9de66ecab	1832	} NRF_PPI_Type;
Yassinetaouil	46:b1a9de66ecab	1833
Yassinetaouil	46:b1a9de66ecab	1834
Yassinetaouil	46:b1a9de66ecab	1835	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1836	/* ================ MWU ================ */
Yassinetaouil	46:b1a9de66ecab	1837	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1838
Yassinetaouil	46:b1a9de66ecab	1839
Yassinetaouil	46:b1a9de66ecab	1840	/**
Yassinetaouil	46:b1a9de66ecab	1841	* @brief Memory Watch Unit (MWU)
Yassinetaouil	46:b1a9de66ecab	1842	*/
Yassinetaouil	46:b1a9de66ecab	1843
Yassinetaouil	46:b1a9de66ecab	1844	typedef struct { /!< MWU Structure /
Yassinetaouil	46:b1a9de66ecab	1845	__I uint32_t RESERVED0[64];
Yassinetaouil	46:b1a9de66ecab	1846	MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1847	__I uint32_t RESERVED1[16];
Yassinetaouil	46:b1a9de66ecab	1848	MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1849	__I uint32_t RESERVED2[100];
Yassinetaouil	46:b1a9de66ecab	1850	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1851	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1852	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1853	__I uint32_t RESERVED3[5];
Yassinetaouil	46:b1a9de66ecab	1854	__IO uint32_t NMIEN; /!< Enable or disable non-maskable interrupt /
Yassinetaouil	46:b1a9de66ecab	1855	__IO uint32_t NMIENSET; /!< Enable non-maskable interrupt /
Yassinetaouil	46:b1a9de66ecab	1856	__IO uint32_t NMIENCLR; /!< Disable non-maskable interrupt /
Yassinetaouil	46:b1a9de66ecab	1857	__I uint32_t RESERVED4[53];
Yassinetaouil	46:b1a9de66ecab	1858	MWU_PERREGION_Type PERREGION[2]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1859	__I uint32_t RESERVED5[64];
Yassinetaouil	46:b1a9de66ecab	1860	__IO uint32_t REGIONEN; /!< Enable/disable regions watch /
Yassinetaouil	46:b1a9de66ecab	1861	__IO uint32_t REGIONENSET; /!< Enable regions watch /
Yassinetaouil	46:b1a9de66ecab	1862	__IO uint32_t REGIONENCLR; /!< Disable regions watch /
Yassinetaouil	46:b1a9de66ecab	1863	__I uint32_t RESERVED6[57];
Yassinetaouil	46:b1a9de66ecab	1864	MWU_REGION_Type REGION[4]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1865	__I uint32_t RESERVED7[32];
Yassinetaouil	46:b1a9de66ecab	1866	MWU_PREGION_Type PREGION[2]; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1867	} NRF_MWU_Type;
Yassinetaouil	46:b1a9de66ecab	1868
Yassinetaouil	46:b1a9de66ecab	1869
Yassinetaouil	46:b1a9de66ecab	1870	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1871	/* ================ I2S ================ */
Yassinetaouil	46:b1a9de66ecab	1872	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1873
Yassinetaouil	46:b1a9de66ecab	1874
Yassinetaouil	46:b1a9de66ecab	1875	/**
Yassinetaouil	46:b1a9de66ecab	1876	* @brief Inter-IC Sound (I2S)
Yassinetaouil	46:b1a9de66ecab	1877	*/
Yassinetaouil	46:b1a9de66ecab	1878
Yassinetaouil	46:b1a9de66ecab	1879	typedef struct { /!< I2S Structure /
Yassinetaouil	46:b1a9de66ecab	1880	__O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when
Yassinetaouil	46:b1a9de66ecab	1881	this is enabled. */
Yassinetaouil	46:b1a9de66ecab	1882	__O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
Yassinetaouil	46:b1a9de66ecab	1883	task will cause the {event:STOPPED} event to be generated. */
Yassinetaouil	46:b1a9de66ecab	1884	__I uint32_t RESERVED0[63];
Yassinetaouil	46:b1a9de66ecab	1885	__IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers.
Yassinetaouil	46:b1a9de66ecab	1886	When the I2S module is started and RX is enabled, this event
Yassinetaouil	46:b1a9de66ecab	1887	will be generated for every RXTXD.MAXCNT words that are received
Yassinetaouil	46:b1a9de66ecab	1888	on the SDIN pin. */
Yassinetaouil	46:b1a9de66ecab	1889	__IO uint32_t EVENTS_STOPPED; /!< I2S transfer stopped. /
Yassinetaouil	46:b1a9de66ecab	1890	__I uint32_t RESERVED1[2];
Yassinetaouil	46:b1a9de66ecab	1891	__IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers.
Yassinetaouil	46:b1a9de66ecab	1892	When the I2S module is started and TX is enabled, this event
Yassinetaouil	46:b1a9de66ecab	1893	will be generated for every RXTXD.MAXCNT words that are sent
Yassinetaouil	46:b1a9de66ecab	1894	on the SDOUT pin. */
Yassinetaouil	46:b1a9de66ecab	1895	__I uint32_t RESERVED2[122];
Yassinetaouil	46:b1a9de66ecab	1896	__IO uint32_t INTEN; /!< Enable or disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1897	__IO uint32_t INTENSET; /!< Enable interrupt /
Yassinetaouil	46:b1a9de66ecab	1898	__IO uint32_t INTENCLR; /!< Disable interrupt /
Yassinetaouil	46:b1a9de66ecab	1899	__I uint32_t RESERVED3[125];
Yassinetaouil	46:b1a9de66ecab	1900	__IO uint32_t ENABLE; /!< Enable I2S module. /
Yassinetaouil	46:b1a9de66ecab	1901	I2S_CONFIG_Type CONFIG; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1902	__I uint32_t RESERVED4[3];
Yassinetaouil	46:b1a9de66ecab	1903	I2S_RXD_Type RXD; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1904	__I uint32_t RESERVED5;
Yassinetaouil	46:b1a9de66ecab	1905	I2S_TXD_Type TXD; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1906	__I uint32_t RESERVED6[3];
Yassinetaouil	46:b1a9de66ecab	1907	I2S_RXTXD_Type RXTXD; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1908	__I uint32_t RESERVED7[3];
Yassinetaouil	46:b1a9de66ecab	1909	I2S_PSEL_Type PSEL; /!< Unspecified /
Yassinetaouil	46:b1a9de66ecab	1910	} NRF_I2S_Type;
Yassinetaouil	46:b1a9de66ecab	1911
Yassinetaouil	46:b1a9de66ecab	1912
Yassinetaouil	46:b1a9de66ecab	1913	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1914	/* ================ FPU ================ */
Yassinetaouil	46:b1a9de66ecab	1915	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1916
Yassinetaouil	46:b1a9de66ecab	1917
Yassinetaouil	46:b1a9de66ecab	1918	/**
Yassinetaouil	46:b1a9de66ecab	1919	* @brief FPU (FPU)
Yassinetaouil	46:b1a9de66ecab	1920	*/
Yassinetaouil	46:b1a9de66ecab	1921
Yassinetaouil	46:b1a9de66ecab	1922	typedef struct { /!< FPU Structure /
Yassinetaouil	46:b1a9de66ecab	1923	__I uint32_t UNUSED; /!< Unused. /
Yassinetaouil	46:b1a9de66ecab	1924	} NRF_FPU_Type;
Yassinetaouil	46:b1a9de66ecab	1925
Yassinetaouil	46:b1a9de66ecab	1926
Yassinetaouil	46:b1a9de66ecab	1927	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1928	/* ================ GPIO ================ */
Yassinetaouil	46:b1a9de66ecab	1929	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1930
Yassinetaouil	46:b1a9de66ecab	1931
Yassinetaouil	46:b1a9de66ecab	1932	/**
Yassinetaouil	46:b1a9de66ecab	1933	* @brief GPIO Port 1 (GPIO)
Yassinetaouil	46:b1a9de66ecab	1934	*/
Yassinetaouil	46:b1a9de66ecab	1935
Yassinetaouil	46:b1a9de66ecab	1936	typedef struct { /!< GPIO Structure /
Yassinetaouil	46:b1a9de66ecab	1937	__I uint32_t RESERVED0[321];
Yassinetaouil	46:b1a9de66ecab	1938	__IO uint32_t OUT; /!< Write GPIO port /
Yassinetaouil	46:b1a9de66ecab	1939	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port /
Yassinetaouil	46:b1a9de66ecab	1940	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port /
Yassinetaouil	46:b1a9de66ecab	1941	__I uint32_t IN; /!< Read GPIO port /
Yassinetaouil	46:b1a9de66ecab	1942	__IO uint32_t DIR; /!< Direction of GPIO pins /
Yassinetaouil	46:b1a9de66ecab	1943	__IO uint32_t DIRSET; /!< DIR set register /
Yassinetaouil	46:b1a9de66ecab	1944	__IO uint32_t DIRCLR; /!< DIR clear register /
Yassinetaouil	46:b1a9de66ecab	1945	__IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria
Yassinetaouil	46:b1a9de66ecab	1946	set in the PIN_CNF[n].SENSE registers */
Yassinetaouil	46:b1a9de66ecab	1947	__IO uint32_t DETECTMODE; /!< Select between default DETECT signal behaviour and LDETECT mode /
Yassinetaouil	46:b1a9de66ecab	1948	__I uint32_t RESERVED1[118];
Yassinetaouil	46:b1a9de66ecab	1949	__IO uint32_t PIN_CNF[32]; /!< Description collection[0]: Configuration of GPIO pins /
Yassinetaouil	46:b1a9de66ecab	1950	} NRF_GPIO_Type;
Yassinetaouil	46:b1a9de66ecab	1951
Yassinetaouil	46:b1a9de66ecab	1952
Yassinetaouil	46:b1a9de66ecab	1953	/* -------------------- End of section using anonymous unions ------------------- */
Yassinetaouil	46:b1a9de66ecab	1954	#if defined(__CC_ARM)
Yassinetaouil	46:b1a9de66ecab	1955	#pragma pop
Yassinetaouil	46:b1a9de66ecab	1956	#elif defined(__ICCARM__)
Yassinetaouil	46:b1a9de66ecab	1957	/* leave anonymous unions enabled */
Yassinetaouil	46:b1a9de66ecab	1958	#elif defined(__GNUC__)
Yassinetaouil	46:b1a9de66ecab	1959	/* anonymous unions are enabled by default */
Yassinetaouil	46:b1a9de66ecab	1960	#elif defined(__TMS470__)
Yassinetaouil	46:b1a9de66ecab	1961	/* anonymous unions are enabled by default */
Yassinetaouil	46:b1a9de66ecab	1962	#elif defined(__TASKING__)
Yassinetaouil	46:b1a9de66ecab	1963	#pragma warning restore
Yassinetaouil	46:b1a9de66ecab	1964	#else
Yassinetaouil	46:b1a9de66ecab	1965	#warning Not supported compiler type
Yassinetaouil	46:b1a9de66ecab	1966	#endif
Yassinetaouil	46:b1a9de66ecab	1967
Yassinetaouil	46:b1a9de66ecab	1968
Yassinetaouil	46:b1a9de66ecab	1969
Yassinetaouil	46:b1a9de66ecab	1970
Yassinetaouil	46:b1a9de66ecab	1971	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1972	/* ================ Peripheral memory map ================ */
Yassinetaouil	46:b1a9de66ecab	1973	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	1974
Yassinetaouil	46:b1a9de66ecab	1975	#define NRF_FICR_BASE 0x10000000UL
Yassinetaouil	46:b1a9de66ecab	1976	#define NRF_UICR_BASE 0x10001000UL
Yassinetaouil	46:b1a9de66ecab	1977	#define NRF_BPROT_BASE 0x40000000UL
Yassinetaouil	46:b1a9de66ecab	1978	#define NRF_POWER_BASE 0x40000000UL
Yassinetaouil	46:b1a9de66ecab	1979	#define NRF_CLOCK_BASE 0x40000000UL
Yassinetaouil	46:b1a9de66ecab	1980	#define NRF_AMLI_BASE 0x40000000UL
Yassinetaouil	46:b1a9de66ecab	1981	#define NRF_RADIO_BASE 0x40001000UL
Yassinetaouil	46:b1a9de66ecab	1982	#define NRF_UARTE0_BASE 0x40002000UL
Yassinetaouil	46:b1a9de66ecab	1983	#define NRF_UART0_BASE 0x40002000UL
Yassinetaouil	46:b1a9de66ecab	1984	#define NRF_SPIM0_BASE 0x40003000UL
Yassinetaouil	46:b1a9de66ecab	1985	#define NRF_SPIS0_BASE 0x40003000UL
Yassinetaouil	46:b1a9de66ecab	1986	#define NRF_TWIM0_BASE 0x40003000UL
Yassinetaouil	46:b1a9de66ecab	1987	#define NRF_TWIS0_BASE 0x40003000UL
Yassinetaouil	46:b1a9de66ecab	1988	#define NRF_SPI0_BASE 0x40003000UL
Yassinetaouil	46:b1a9de66ecab	1989	#define NRF_TWI0_BASE 0x40003000UL
Yassinetaouil	46:b1a9de66ecab	1990	#define NRF_SPIM1_BASE 0x40004000UL
Yassinetaouil	46:b1a9de66ecab	1991	#define NRF_SPIS1_BASE 0x40004000UL
Yassinetaouil	46:b1a9de66ecab	1992	#define NRF_TWIM1_BASE 0x40004000UL
Yassinetaouil	46:b1a9de66ecab	1993	#define NRF_TWIS1_BASE 0x40004000UL
Yassinetaouil	46:b1a9de66ecab	1994	#define NRF_SPI1_BASE 0x40004000UL
Yassinetaouil	46:b1a9de66ecab	1995	#define NRF_TWI1_BASE 0x40004000UL
Yassinetaouil	46:b1a9de66ecab	1996	#define NRF_NFCT_BASE 0x40005000UL
Yassinetaouil	46:b1a9de66ecab	1997	#define NRF_GPIOTE_BASE 0x40006000UL
Yassinetaouil	46:b1a9de66ecab	1998	#define NRF_SAADC_BASE 0x40007000UL
Yassinetaouil	46:b1a9de66ecab	1999	#define NRF_TIMER0_BASE 0x40008000UL
Yassinetaouil	46:b1a9de66ecab	2000	#define NRF_TIMER1_BASE 0x40009000UL
Yassinetaouil	46:b1a9de66ecab	2001	#define NRF_TIMER2_BASE 0x4000A000UL
Yassinetaouil	46:b1a9de66ecab	2002	#define NRF_RTC0_BASE 0x4000B000UL
Yassinetaouil	46:b1a9de66ecab	2003	#define NRF_TEMP_BASE 0x4000C000UL
Yassinetaouil	46:b1a9de66ecab	2004	#define NRF_RNG_BASE 0x4000D000UL
Yassinetaouil	46:b1a9de66ecab	2005	#define NRF_ECB_BASE 0x4000E000UL
Yassinetaouil	46:b1a9de66ecab	2006	#define NRF_CCM_BASE 0x4000F000UL
Yassinetaouil	46:b1a9de66ecab	2007	#define NRF_AAR_BASE 0x4000F000UL
Yassinetaouil	46:b1a9de66ecab	2008	#define NRF_WDT_BASE 0x40010000UL
Yassinetaouil	46:b1a9de66ecab	2009	#define NRF_RTC1_BASE 0x40011000UL
Yassinetaouil	46:b1a9de66ecab	2010	#define NRF_QDEC_BASE 0x40012000UL
Yassinetaouil	46:b1a9de66ecab	2011	#define NRF_COMP_BASE 0x40013000UL
Yassinetaouil	46:b1a9de66ecab	2012	#define NRF_LPCOMP_BASE 0x40013000UL
Yassinetaouil	46:b1a9de66ecab	2013	#define NRF_SWI0_BASE 0x40014000UL
Yassinetaouil	46:b1a9de66ecab	2014	#define NRF_EGU0_BASE 0x40014000UL
Yassinetaouil	46:b1a9de66ecab	2015	#define NRF_SWI1_BASE 0x40015000UL
Yassinetaouil	46:b1a9de66ecab	2016	#define NRF_EGU1_BASE 0x40015000UL
Yassinetaouil	46:b1a9de66ecab	2017	#define NRF_SWI2_BASE 0x40016000UL
Yassinetaouil	46:b1a9de66ecab	2018	#define NRF_EGU2_BASE 0x40016000UL
Yassinetaouil	46:b1a9de66ecab	2019	#define NRF_SWI3_BASE 0x40017000UL
Yassinetaouil	46:b1a9de66ecab	2020	#define NRF_EGU3_BASE 0x40017000UL
Yassinetaouil	46:b1a9de66ecab	2021	#define NRF_SWI4_BASE 0x40018000UL
Yassinetaouil	46:b1a9de66ecab	2022	#define NRF_EGU4_BASE 0x40018000UL
Yassinetaouil	46:b1a9de66ecab	2023	#define NRF_SWI5_BASE 0x40019000UL
Yassinetaouil	46:b1a9de66ecab	2024	#define NRF_EGU5_BASE 0x40019000UL
Yassinetaouil	46:b1a9de66ecab	2025	#define NRF_TIMER3_BASE 0x4001A000UL
Yassinetaouil	46:b1a9de66ecab	2026	#define NRF_TIMER4_BASE 0x4001B000UL
Yassinetaouil	46:b1a9de66ecab	2027	#define NRF_PWM0_BASE 0x4001C000UL
Yassinetaouil	46:b1a9de66ecab	2028	#define NRF_PDM_BASE 0x4001D000UL
Yassinetaouil	46:b1a9de66ecab	2029	#define NRF_NVMC_BASE 0x4001E000UL
Yassinetaouil	46:b1a9de66ecab	2030	#define NRF_PPI_BASE 0x4001F000UL
Yassinetaouil	46:b1a9de66ecab	2031	#define NRF_MWU_BASE 0x40020000UL
Yassinetaouil	46:b1a9de66ecab	2032	#define NRF_PWM1_BASE 0x40021000UL
Yassinetaouil	46:b1a9de66ecab	2033	#define NRF_PWM2_BASE 0x40022000UL
Yassinetaouil	46:b1a9de66ecab	2034	#define NRF_SPIM2_BASE 0x40023000UL
Yassinetaouil	46:b1a9de66ecab	2035	#define NRF_SPIS2_BASE 0x40023000UL
Yassinetaouil	46:b1a9de66ecab	2036	#define NRF_SPI2_BASE 0x40023000UL
Yassinetaouil	46:b1a9de66ecab	2037	#define NRF_RTC2_BASE 0x40024000UL
Yassinetaouil	46:b1a9de66ecab	2038	#define NRF_I2S_BASE 0x40025000UL
Yassinetaouil	46:b1a9de66ecab	2039	#define NRF_FPU_BASE 0x40026000UL
Yassinetaouil	46:b1a9de66ecab	2040	#define NRF_P0_BASE 0x50000000UL
Yassinetaouil	46:b1a9de66ecab	2041
Yassinetaouil	46:b1a9de66ecab	2042
Yassinetaouil	46:b1a9de66ecab	2043	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	2044	/* ================ Peripheral declaration ================ */
Yassinetaouil	46:b1a9de66ecab	2045	/* ================================================================================ */
Yassinetaouil	46:b1a9de66ecab	2046
Yassinetaouil	46:b1a9de66ecab	2047	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Yassinetaouil	46:b1a9de66ecab	2048	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Yassinetaouil	46:b1a9de66ecab	2049	#define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE)
Yassinetaouil	46:b1a9de66ecab	2050	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Yassinetaouil	46:b1a9de66ecab	2051	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Yassinetaouil	46:b1a9de66ecab	2052	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Yassinetaouil	46:b1a9de66ecab	2053	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Yassinetaouil	46:b1a9de66ecab	2054	#define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE)
Yassinetaouil	46:b1a9de66ecab	2055	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Yassinetaouil	46:b1a9de66ecab	2056	#define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE)
Yassinetaouil	46:b1a9de66ecab	2057	#define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE)
Yassinetaouil	46:b1a9de66ecab	2058	#define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE)
Yassinetaouil	46:b1a9de66ecab	2059	#define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE)
Yassinetaouil	46:b1a9de66ecab	2060	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Yassinetaouil	46:b1a9de66ecab	2061	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Yassinetaouil	46:b1a9de66ecab	2062	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
Yassinetaouil	46:b1a9de66ecab	2063	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Yassinetaouil	46:b1a9de66ecab	2064	#define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE)
Yassinetaouil	46:b1a9de66ecab	2065	#define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE)
Yassinetaouil	46:b1a9de66ecab	2066	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Yassinetaouil	46:b1a9de66ecab	2067	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Yassinetaouil	46:b1a9de66ecab	2068	#define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE)
Yassinetaouil	46:b1a9de66ecab	2069	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Yassinetaouil	46:b1a9de66ecab	2070	#define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE)
Yassinetaouil	46:b1a9de66ecab	2071	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Yassinetaouil	46:b1a9de66ecab	2072	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Yassinetaouil	46:b1a9de66ecab	2073	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Yassinetaouil	46:b1a9de66ecab	2074	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Yassinetaouil	46:b1a9de66ecab	2075	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Yassinetaouil	46:b1a9de66ecab	2076	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Yassinetaouil	46:b1a9de66ecab	2077	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Yassinetaouil	46:b1a9de66ecab	2078	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Yassinetaouil	46:b1a9de66ecab	2079	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Yassinetaouil	46:b1a9de66ecab	2080	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Yassinetaouil	46:b1a9de66ecab	2081	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Yassinetaouil	46:b1a9de66ecab	2082	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Yassinetaouil	46:b1a9de66ecab	2083	#define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
Yassinetaouil	46:b1a9de66ecab	2084	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Yassinetaouil	46:b1a9de66ecab	2085	#define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE)
Yassinetaouil	46:b1a9de66ecab	2086	#define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE)
Yassinetaouil	46:b1a9de66ecab	2087	#define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE)
Yassinetaouil	46:b1a9de66ecab	2088	#define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE)
Yassinetaouil	46:b1a9de66ecab	2089	#define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE)
Yassinetaouil	46:b1a9de66ecab	2090	#define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE)
Yassinetaouil	46:b1a9de66ecab	2091	#define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE)
Yassinetaouil	46:b1a9de66ecab	2092	#define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE)
Yassinetaouil	46:b1a9de66ecab	2093	#define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE)
Yassinetaouil	46:b1a9de66ecab	2094	#define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE)
Yassinetaouil	46:b1a9de66ecab	2095	#define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE)
Yassinetaouil	46:b1a9de66ecab	2096	#define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE)
Yassinetaouil	46:b1a9de66ecab	2097	#define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE)
Yassinetaouil	46:b1a9de66ecab	2098	#define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE)
Yassinetaouil	46:b1a9de66ecab	2099	#define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE)
Yassinetaouil	46:b1a9de66ecab	2100	#define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE)
Yassinetaouil	46:b1a9de66ecab	2101	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Yassinetaouil	46:b1a9de66ecab	2102	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Yassinetaouil	46:b1a9de66ecab	2103	#define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE)
Yassinetaouil	46:b1a9de66ecab	2104	#define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE)
Yassinetaouil	46:b1a9de66ecab	2105	#define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE)
Yassinetaouil	46:b1a9de66ecab	2106	#define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE)
Yassinetaouil	46:b1a9de66ecab	2107	#define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE)
Yassinetaouil	46:b1a9de66ecab	2108	#define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE)
Yassinetaouil	46:b1a9de66ecab	2109	#define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE)
Yassinetaouil	46:b1a9de66ecab	2110	#define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE)
Yassinetaouil	46:b1a9de66ecab	2111	#define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE)
Yassinetaouil	46:b1a9de66ecab	2112	#define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE)
Yassinetaouil	46:b1a9de66ecab	2113
Yassinetaouil	46:b1a9de66ecab	2114
Yassinetaouil	46:b1a9de66ecab	2115	/** @} / / End of group Device_Peripheral_Registers */
Yassinetaouil	46:b1a9de66ecab	2116	/** @} / / End of group nrf52 */
Yassinetaouil	46:b1a9de66ecab	2117	/** @} / / End of group Nordic Semiconductor */
Yassinetaouil	46:b1a9de66ecab	2118
Yassinetaouil	46:b1a9de66ecab	2119	#ifdef __cplusplus
Yassinetaouil	46:b1a9de66ecab	2120	}
Yassinetaouil	46:b1a9de66ecab	2121	#endif
Yassinetaouil	46:b1a9de66ecab	2122
Yassinetaouil	46:b1a9de66ecab	2123
Yassinetaouil	46:b1a9de66ecab	2124	#endif /* nrf52_H */
Yassinetaouil	46:b1a9de66ecab	2125
Yassinetaouil	46:b1a9de66ecab	2126

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Type:	Program
Created:	02 Nov 2016
Imports:	23
Forks:	0
Commits:	47
Dependents:	0
Dependencies:	0
Followers:	1

source/nordic_sdk/components/device/nrf52.h@46:b1a9de66ecab, 2016-11-02 (annotated)

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