Y SI
Counts signal transitions on p30(CAP2.0) or p29(CAP2.1) for LPC1768 target. Can detecte rising, falling or both signal edge. Return the signal edge count during a period in seconds. In theory (Shannon's theorem) input signal frequency can up to 48 MHz with 96 MHz CCLK. But only tested with frequencys up to 20 MHz and it work.
Changes
| Revision | Date | Who | Commit message |
|---|---|---|---|
| 5:b5e68cd91f09 | 2020-12-02 | YSI | add split start and stop count |
| 4:b873a2fda102 | 2020-01-07 | YSI | add switch default |
| 3:20dd01b1a1fd | 2020-01-07 | YSI | wait() in getCount() has been modified in wait_us() |
| 2:cc5b11ec50ad | 2019-11-21 | YSI | Up Doc |
| 1:bdbac277828a | 2019-11-21 | YSI | lib_ClockCounter |
| 0:d3c997729db1 | 2019-11-21 | YSI | lib_ClockCounter |