Y SI
Counts signal transitions on p30(CAP2.0) or p29(CAP2.1) for LPC1768 target. Can detecte rising, falling or both signal edge. Return the signal edge count during a period in seconds. In theory (Shannon's theorem) input signal frequency can up to 48 MHz with 96 MHz CCLK. But only tested with frequencys up to 20 MHz and it work.
History
add split start and stop count
2020-12-02, by YSI [Wed, 02 Dec 2020 15:48:45 +0000] rev 5
add split start and stop count
add switch default
2020-01-07, by YSI [Tue, 07 Jan 2020 15:00:14 +0000] rev 4
add switch default
wait() in getCount() has been modified in wait_us()
2020-01-07, by YSI [Tue, 07 Jan 2020 14:55:10 +0000] rev 3
wait() in getCount() has been modified in wait_us()
Up Doc
2019-11-21, by YSI [Thu, 21 Nov 2019 09:25:58 +0000] rev 2
Up Doc
lib_ClockCounter
2019-11-21, by YSI [Thu, 21 Nov 2019 09:18:40 +0000] rev 1
lib_ClockCounter
lib_ClockCounter
2019-11-21, by YSI [Thu, 21 Nov 2019 09:17:25 +0000] rev 0
lib_ClockCounter