Yash Kuntavalli / SpiFlash25

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Fork of SpiFlash25 by MultiTech

SpiFlash25.h@1:17246d2dfff3, 2014-12-11 (annotated)

Committer:
Mike Fiore
Date:
Thu Dec 11 14:37:34 2014 -0600
Revision:
1:17246d2dfff3
Parent:
0:137807d94795
Child:
3:b173ba8ad165
add optional pins for W and HOLD

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mfiore 0:137807d94795 1 /* Library for SPI flash 25* devices.
mfiore 0:137807d94795 2 * Copyright (c) 2014 Multi-Tech Systems
mfiore 0:137807d94795 3 *
mfiore 0:137807d94795 4 * Permission is hereby granted, free of charge, to any person obtaining a copy
mfiore 0:137807d94795 5 * of this software and associated documentation files (the "Software"), to deal
mfiore 0:137807d94795 6 * in the Software without restriction, including without limitation the rights
mfiore 0:137807d94795 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
mfiore 0:137807d94795 8 * copies of the Software, and to permit persons to whom the Software is
mfiore 0:137807d94795 9 * furnished to do so, subject to the following conditions:
mfiore 0:137807d94795 10 *
mfiore 0:137807d94795 11 * The above copyright notice and this permission notice shall be included in
mfiore 0:137807d94795 12 * all copies or substantial portions of the Software.
mfiore 0:137807d94795 13 *
mfiore 0:137807d94795 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
mfiore 0:137807d94795 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
mfiore 0:137807d94795 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
mfiore 0:137807d94795 17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
mfiore 0:137807d94795 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
mfiore 0:137807d94795 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
mfiore 0:137807d94795 20 * SOFTWARE.
mfiore 0:137807d94795 21 */
mfiore 0:137807d94795 22
mfiore 0:137807d94795 23 #ifndef SPIFLASH25_H
mfiore 0:137807d94795 24 #define SPIFLASH25_H
mfiore 0:137807d94795 25
mfiore 0:137807d94795 26 #include "mbed.h"
mfiore 0:137807d94795 27
mfiore 0:137807d94795 28 class SpiFlash25 {
mfiore 0:137807d94795 29 public:
Mike Fiore 1:17246d2dfff3 30 SpiFlash25(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName W = NC, PinName HOLD = NC, int page_size = 256);
mfiore 0:137807d94795 31
mfiore 0:137807d94795 32 /* Set the page size (default 256) */
mfiore 0:137807d94795 33 void set_page_size(int size);
mfiore 0:137807d94795 34
mfiore 0:137807d94795 35 /* Set up the internal SPI object */
mfiore 0:137807d94795 36 void format(int bits, int mode);
mfiore 0:137807d94795 37 void frequency(int hz);
mfiore 0:137807d94795 38
mfiore 0:137807d94795 39 /* Reads and writes can be across page boundaries */
mfiore 0:137807d94795 40 bool read(int addr, int len, char* data);
mfiore 0:137807d94795 41 bool write(int addr, int len, const char* data);
mfiore 0:137807d94795 42
mfiore 0:137807d94795 43 /* Read ID and status registers */
mfiore 0:137807d94795 44 char* read_id();
mfiore 0:137807d94795 45 char read_status();
mfiore 0:137807d94795 46
mfiore 0:137807d94795 47 /* Erase methods */
mfiore 0:137807d94795 48 void clear_sector(int addr);
mfiore 0:137807d94795 49 void clear_mem();
mfiore 0:137807d94795 50
mfiore 0:137807d94795 51 private:
mfiore 0:137807d94795 52 enum {
mfiore 0:137807d94795 53 WRITE_ENABLE = 0x06,
mfiore 0:137807d94795 54 WRITE_DISABLE = 0x04,
mfiore 0:137807d94795 55 READ_IDENTIFICATION = 0x9F,
mfiore 0:137807d94795 56 READ_STATUS = 0x05,
mfiore 0:137807d94795 57 WRITE_STATUS = 0x01,
mfiore 0:137807d94795 58 READ_DATA = 0x03,
mfiore 0:137807d94795 59 READ_DATA_FAST = 0x0B,
mfiore 0:137807d94795 60 PAGE_PROGRAM = 0x02,
mfiore 0:137807d94795 61 SECTOR_ERASE = 0xD8,
mfiore 0:137807d94795 62 BULK_ERASE = 0xC7,
mfiore 0:137807d94795 63 DEEP_POWER_DOWN = 0xB9,
mfiore 0:137807d94795 64 DEEP_POWER_DOWN_RELEASE = 0xAB,
mfiore 0:137807d94795 65 };
mfiore 0:137807d94795 66
mfiore 0:137807d94795 67 enum {
mfiore 0:137807d94795 68 STATUS_SRWD = 0x80, // 0b 1000 0000
mfiore 0:137807d94795 69 STATUS_BP2 = 0x10, // 0b 0001 0000
mfiore 0:137807d94795 70 STATUS_BP1 = 0x08, // 0b 0000 1000
mfiore 0:137807d94795 71 STATUS_BP0 = 0x04, // 0b 0000 0100
mfiore 0:137807d94795 72 STATUS_WEL = 0x02, // 0b 0000 0010
mfiore 0:137807d94795 73 STATUS_WIP = 0x01, // 0b 0000 0001
mfiore 0:137807d94795 74 };
mfiore 0:137807d94795 75
mfiore 0:137807d94795 76 enum {
mfiore 0:137807d94795 77 ID_MANUFACTURER = 0,
mfiore 0:137807d94795 78 ID_MEM_TYPE = 1,
mfiore 0:137807d94795 79 ID_MEM_SIZE = 2,
mfiore 0:137807d94795 80 };
mfiore 0:137807d94795 81
mfiore 0:137807d94795 82 bool write_page(int addr, int len, const char* data);
mfiore 0:137807d94795 83 void enable_write();
mfiore 0:137807d94795 84 void wait_for_write();
mfiore 0:137807d94795 85
mfiore 0:137807d94795 86 static inline char high_byte(int addr) {
mfiore 0:137807d94795 87 return ((addr & 0xff0000) >> 16);
mfiore 0:137807d94795 88 }
mfiore 0:137807d94795 89 static inline char mid_byte(int addr) {
mfiore 0:137807d94795 90 return ((addr & 0xff00) >> 8);
mfiore 0:137807d94795 91 }
mfiore 0:137807d94795 92 static inline char low_byte(int addr) {
mfiore 0:137807d94795 93 return (addr & 0xff);
mfiore 0:137807d94795 94 }
mfiore 0:137807d94795 95
mfiore 0:137807d94795 96 SPI _spi;
mfiore 0:137807d94795 97 DigitalOut _cs;
Mike Fiore 1:17246d2dfff3 98 DigitalOut _w;
Mike Fiore 1:17246d2dfff3 99 DigitalOut _hold;
mfiore 0:137807d94795 100 int _mem_size;
mfiore 0:137807d94795 101 int _page_size;
mfiore 0:137807d94795 102 char _id[3];
mfiore 0:137807d94795 103 };
Mike Fiore 1:17246d2dfff3 104 #endif