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mbed-os/targets/TARGET_ONSEMI/TARGET_NCS36510/uart_16c550_map.h@0:9b3d4731edbb, 2018-06-21 (annotated)

Committer:
WFKnight
Date:
Thu Jun 21 13:51:43 2018 +0000
Revision:
0:9b3d4731edbb
UART, RTOS, LED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
WFKnight 0:9b3d4731edbb 1 /**
WFKnight 0:9b3d4731edbb 2 ******************************************************************************
WFKnight 0:9b3d4731edbb 3 * @file uart_16c550_map.h
WFKnight 0:9b3d4731edbb 4 * @brief UART module hardware register map.
WFKnight 0:9b3d4731edbb 5 * @internal
WFKnight 0:9b3d4731edbb 6 * @author ON Semiconductor.
WFKnight 0:9b3d4731edbb 7 * $Rev: 2615 $
WFKnight 0:9b3d4731edbb 8 * $Date: 2013-12-13 13:17:21 +0530 (Fri, 13 Dec 2013) $
WFKnight 0:9b3d4731edbb 9 ******************************************************************************
WFKnight 0:9b3d4731edbb 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
WFKnight 0:9b3d4731edbb 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
WFKnight 0:9b3d4731edbb 12 * under limited terms and conditions. The terms and conditions pertaining to the software
WFKnight 0:9b3d4731edbb 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
WFKnight 0:9b3d4731edbb 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
WFKnight 0:9b3d4731edbb 15 * if applicable the software license agreement. Do not use this software and/or
WFKnight 0:9b3d4731edbb 16 * documentation unless you have carefully read and you agree to the limited terms and
WFKnight 0:9b3d4731edbb 17 * conditions. By using this software and/or documentation, you agree to the limited
WFKnight 0:9b3d4731edbb 18 * terms and conditions.
WFKnight 0:9b3d4731edbb 19 *
WFKnight 0:9b3d4731edbb 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
WFKnight 0:9b3d4731edbb 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
WFKnight 0:9b3d4731edbb 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
WFKnight 0:9b3d4731edbb 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
WFKnight 0:9b3d4731edbb 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
WFKnight 0:9b3d4731edbb 25 * @endinternal
WFKnight 0:9b3d4731edbb 26 *
WFKnight 0:9b3d4731edbb 27 * @ingroup uart_16c550
WFKnight 0:9b3d4731edbb 28 *
WFKnight 0:9b3d4731edbb 29 * @details
WFKnight 0:9b3d4731edbb 30 * <h1> Reference document(s) </h1>
WFKnight 0:9b3d4731edbb 31 * <p>
WFKnight 0:9b3d4731edbb 32 * <a href="../pdf/IPC7202_UART_APB_DS_v1P4.pdf" target="_blank">
WFKnight 0:9b3d4731edbb 33 * IPC7202 APB UART Design Specification v1.4 </a>
WFKnight 0:9b3d4731edbb 34 * </p>
WFKnight 0:9b3d4731edbb 35 */
WFKnight 0:9b3d4731edbb 36
WFKnight 0:9b3d4731edbb 37 #ifndef UART_16C550_MAP_H_
WFKnight 0:9b3d4731edbb 38 #define UART_16C550_MAP_H_
WFKnight 0:9b3d4731edbb 39
WFKnight 0:9b3d4731edbb 40 #include "architecture.h"
WFKnight 0:9b3d4731edbb 41
WFKnight 0:9b3d4731edbb 42 #if defined ( __CC_ARM )
WFKnight 0:9b3d4731edbb 43 #pragma anon_unions
WFKnight 0:9b3d4731edbb 44 #endif
WFKnight 0:9b3d4731edbb 45
WFKnight 0:9b3d4731edbb 46 #define DCTS (uint8_t)0x01
WFKnight 0:9b3d4731edbb 47 #define DDSR (uint8_t)0x02
WFKnight 0:9b3d4731edbb 48 #define TERI (uint8_t)0x04
WFKnight 0:9b3d4731edbb 49 #define DDCD (uint8_t)0x08
WFKnight 0:9b3d4731edbb 50 //#define CTS (uint8_t)0x10
WFKnight 0:9b3d4731edbb 51 #define DSR (uint8_t)0x20
WFKnight 0:9b3d4731edbb 52 #define RI (uint8_t)0x40
WFKnight 0:9b3d4731edbb 53 #define DCD (uint8_t)0x80
WFKnight 0:9b3d4731edbb 54 #define IER_PWRDNENACTIVE ((uint8_t)(1<<5))
WFKnight 0:9b3d4731edbb 55 #define IER_MSI ((uint8_t)(1<<3))
WFKnight 0:9b3d4731edbb 56 #define IER_RLSI ((uint8_t)(1<<2))
WFKnight 0:9b3d4731edbb 57 #define IER_THRI ((uint8_t)(1<<1))
WFKnight 0:9b3d4731edbb 58 #define IER_RDAI ((uint8_t)(1<<0))
WFKnight 0:9b3d4731edbb 59 #define FCR_RXFIFOTRIGGERLEVEL_1 ((uint8_t)(0x00))
WFKnight 0:9b3d4731edbb 60 #define FCR_RXFIFOTRIGGERLEVEL_4 ((uint8_t)(0x40))
WFKnight 0:9b3d4731edbb 61 #define FCR_RXFIFOTRIGGERLEVEL_8 ((uint8_t)(0x80))
WFKnight 0:9b3d4731edbb 62 #define FCR_RXFIFOTRIGGERLEVEL_14 ((uint8_t)(0xC0))
WFKnight 0:9b3d4731edbb 63 #define FCR_DMA_MODE_0 ((uint8_t)(0<<3))
WFKnight 0:9b3d4731edbb 64 #define FCR_DMA_MODE_1 ((uint8_t)(1<<3))
WFKnight 0:9b3d4731edbb 65 #define FCR_TXFIFO_RESET ((uint8_t)(1<<2))
WFKnight 0:9b3d4731edbb 66 #define FCR_RXFIFO_RESET ((uint8_t)(1<<1))
WFKnight 0:9b3d4731edbb 67 #define FCR_FIFO_ENABLE ((uint8_t)(1<<0))
WFKnight 0:9b3d4731edbb 68
WFKnight 0:9b3d4731edbb 69 /** UART HW Structure Overlay */
WFKnight 0:9b3d4731edbb 70 typedef struct {
WFKnight 0:9b3d4731edbb 71 /** Base address + 0x0: Receive, transmit and divisor_LSB offset */
WFKnight 0:9b3d4731edbb 72 union {
WFKnight 0:9b3d4731edbb 73 __I uint32_t RBR; /**< Received data (8 bits wide) / read only */
WFKnight 0:9b3d4731edbb 74 __O uint32_t THR; /**< Data to be transmitted (8 bits wide) / write only */
WFKnight 0:9b3d4731edbb 75 __IO uint32_t DLL; /**< If DLAB = 1. LS byte for input to baud rate generator */
WFKnight 0:9b3d4731edbb 76 };
WFKnight 0:9b3d4731edbb 77 /** Base address + 0x4: Interrupt enable and divisor_MSB offset */
WFKnight 0:9b3d4731edbb 78 union {
WFKnight 0:9b3d4731edbb 79 union {
WFKnight 0:9b3d4731edbb 80 struct {
WFKnight 0:9b3d4731edbb 81 __IO uint32_t RX_DATA_INT :1; /**< Enables the received data interrupt, write 1 to enable */
WFKnight 0:9b3d4731edbb 82 __IO uint32_t TX_HOLD_INT :1; /**< Enables the transmitter holding interrupt, write 1 to enable */
WFKnight 0:9b3d4731edbb 83 __IO uint32_t RX_STATUS_INT :1; /**< Enables the receiver line status interrupt, write 1 to enable */
WFKnight 0:9b3d4731edbb 84 __IO uint32_t MODEM_STATUS_INT :1; /**< Enables the modem status interrupt, write 1 to enable */
WFKnight 0:9b3d4731edbb 85 __IO uint32_t PAD0 :1;
WFKnight 0:9b3d4731edbb 86 __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in MCR is set also */
WFKnight 0:9b3d4731edbb 87 __IO uint32_t PAD1 :2;
WFKnight 0:9b3d4731edbb 88 } BITS;
WFKnight 0:9b3d4731edbb 89 __IO uint32_t WORD;
WFKnight 0:9b3d4731edbb 90 } IER; /** Interrupt enable offset 0x04 */
WFKnight 0:9b3d4731edbb 91 __IO uint32_t DLM; /**< If DLAB = 1. MS byte for input to baud rate generator */
WFKnight 0:9b3d4731edbb 92 };
WFKnight 0:9b3d4731edbb 93 /** Base address + 0x8: Interrupt status and fifo control offset*/
WFKnight 0:9b3d4731edbb 94 union {
WFKnight 0:9b3d4731edbb 95 union {
WFKnight 0:9b3d4731edbb 96 struct {
WFKnight 0:9b3d4731edbb 97 __I uint32_t INT_PEND :1; /**< Interrupt is pending if 1 */
WFKnight 0:9b3d4731edbb 98 __I uint32_t INT_ID :3; /**< Interrupt identification: 011-RX Line, 010-Rx Data, 110-char TO, 001-TX empty, 000-Modem status*/
WFKnight 0:9b3d4731edbb 99 __I uint32_t PAD0 :2;
WFKnight 0:9b3d4731edbb 100 __I uint32_t FIFO_EN :2; /**< Fifos enabled: 00-disabled, 01/10-undefined, 11-enabled */
WFKnight 0:9b3d4731edbb 101 } BITS;
WFKnight 0:9b3d4731edbb 102 __I uint32_t WORD;
WFKnight 0:9b3d4731edbb 103 } IIR; /** Interrupt status and fifo status offset 0x08 */
WFKnight 0:9b3d4731edbb 104 union {
WFKnight 0:9b3d4731edbb 105 struct {
WFKnight 0:9b3d4731edbb 106 __O uint32_t FIFO_EN :1; /**< FIFO enable, write 1 to enable */
WFKnight 0:9b3d4731edbb 107 __O uint32_t RX_FIFO_RST :1; /**< RX FIFO reset, write 1 to reset */
WFKnight 0:9b3d4731edbb 108 __O uint32_t TX_FIFO_RST :1; /**< TX FIFO reset, write 1 to reset */
WFKnight 0:9b3d4731edbb 109 __O uint32_t DMA_SEL :1; /**< DMA mode select */
WFKnight 0:9b3d4731edbb 110 __O uint32_t PAD0 :2;
WFKnight 0:9b3d4731edbb 111 __O uint32_t RX_FIFO_TRIG :2; /**< Receiver FIFO trigger level:00-1byte, 01-4bytes, 10-8bytes, 11-14bytes */
WFKnight 0:9b3d4731edbb 112 } BITS;
WFKnight 0:9b3d4731edbb 113 __O uint32_t WORD;
WFKnight 0:9b3d4731edbb 114 } FCR; /** Fifo control offset 0x08 */
WFKnight 0:9b3d4731edbb 115 };
WFKnight 0:9b3d4731edbb 116 /** Base address + 0xC: Line control offset */
WFKnight 0:9b3d4731edbb 117 union {
WFKnight 0:9b3d4731edbb 118 struct {
WFKnight 0:9b3d4731edbb 119 __IO uint32_t CHAR_LEN :2; /**< Number of bits per character: 00-5bits, 01-6bits, 10:7bits, 11:8bits */
WFKnight 0:9b3d4731edbb 120 __IO uint32_t NUM_STOP :1; /**< Number of stop bits: 0-1bit, 1-2bits */
WFKnight 0:9b3d4731edbb 121 __IO uint32_t PARITY :3; /**< Parity: xx0-disable, 001-odd, 011-even, 101-stick generated/checked as 1, 111-stick generated/checked as 0 */
WFKnight 0:9b3d4731edbb 122 __IO uint32_t BREAK :1; /**< Set to 1 to force output to 0, set to 0 to return to normal operation */
WFKnight 0:9b3d4731edbb 123 __IO uint32_t DLAB :1; /**< Set to 1 to enable the DLL, DLM registers at 0x00 and 0x04 */
WFKnight 0:9b3d4731edbb 124 } BITS;
WFKnight 0:9b3d4731edbb 125 __IO uint32_t WORD;
WFKnight 0:9b3d4731edbb 126 } LCR; /** Line control offset 0x0C */
WFKnight 0:9b3d4731edbb 127 /** Base address + 0x10: Modem control offset */
WFKnight 0:9b3d4731edbb 128 union {
WFKnight 0:9b3d4731edbb 129 struct {
WFKnight 0:9b3d4731edbb 130 __IO uint32_t DTR :1; /**< Data terminal ready. Write 1 to set DTR high (de-asserted), or read DTR */
WFKnight 0:9b3d4731edbb 131 __IO uint32_t RTS :1; /**< Request to send. Write 1 to set RTS high (de-asserted), or read RTS */
WFKnight 0:9b3d4731edbb 132 __IO uint32_t OUTN_CTRL :2; /**< Direct control of out2N and out1N */
WFKnight 0:9b3d4731edbb 133 __IO uint32_t LOOPBACK :1; /**< Write 1 to enable loop back */
WFKnight 0:9b3d4731edbb 134 __IO uint32_t PAD0 :3;
WFKnight 0:9b3d4731edbb 135 __IO uint32_t PD_EN :1; /**< Power down enable active bit, write 1 to enable. Only enabled if PD_EN in IER is set also */
WFKnight 0:9b3d4731edbb 136 } BITS;
WFKnight 0:9b3d4731edbb 137 __IO uint32_t WORD;
WFKnight 0:9b3d4731edbb 138 } MCR; /**< Modem control offset 0x10 */
WFKnight 0:9b3d4731edbb 139 /** Base address + 0x14: Line status offset */
WFKnight 0:9b3d4731edbb 140 union {
WFKnight 0:9b3d4731edbb 141 struct {
WFKnight 0:9b3d4731edbb 142 __O uint32_t READY :1; /**< Rx data available */
WFKnight 0:9b3d4731edbb 143 __O uint32_t OVERRUN_ERR :1; /**< Overrun error */
WFKnight 0:9b3d4731edbb 144 __O uint32_t PARITY_ERR :1; /**< Parity error */
WFKnight 0:9b3d4731edbb 145 __O uint32_t FRAME_ERR :1; /**< Framing error */
WFKnight 0:9b3d4731edbb 146 __O uint32_t BREAK_INT :1; /**< Break interrupt is set when output is kept to 0 for more than 1 bit time */
WFKnight 0:9b3d4731edbb 147 __O uint32_t TX_HOLD_EMPTY :1; /**< Transmit holding register empty */
WFKnight 0:9b3d4731edbb 148 __O uint32_t TX_EMPTY :1; /**< Transmitter empty */
WFKnight 0:9b3d4731edbb 149 __O uint32_t FIFO_ERR :1; /**< Receive fifo error */
WFKnight 0:9b3d4731edbb 150 } BITS;
WFKnight 0:9b3d4731edbb 151 __O uint32_t WORD;
WFKnight 0:9b3d4731edbb 152 } LSR; /**< Line status offset 0x14 */
WFKnight 0:9b3d4731edbb 153 /** Base address + 0x18: Modem status offset */
WFKnight 0:9b3d4731edbb 154 union {
WFKnight 0:9b3d4731edbb 155 struct {
WFKnight 0:9b3d4731edbb 156 __O uint32_t CHG_CTSN :1; /**< CTS change since last MSR read */
WFKnight 0:9b3d4731edbb 157 __O uint32_t CHG_DSRN :1; /**< DSR change since last MSR read */
WFKnight 0:9b3d4731edbb 158 __O uint32_t CHG_RIN :1; /**< RI change since last MSR read */
WFKnight 0:9b3d4731edbb 159 __O uint32_t CHG_DCDN :1; /**< DCD change since last MSR read */
WFKnight 0:9b3d4731edbb 160 __O uint32_t CURR_CTSN :1; /**< CTS current state, 0 = asserted, 1 = de-asserted */
WFKnight 0:9b3d4731edbb 161 __O uint32_t CURR_DSRN :1; /**< DSR current state */
WFKnight 0:9b3d4731edbb 162 __O uint32_t CURR_RIN :1; /**< RI current state */
WFKnight 0:9b3d4731edbb 163 __O uint32_t CURR_DCDN :1; /**< DCD current state */
WFKnight 0:9b3d4731edbb 164 } BITS;
WFKnight 0:9b3d4731edbb 165 __O uint32_t WORD;
WFKnight 0:9b3d4731edbb 166 } MSR; /**< Modem status offset 0x18 */
WFKnight 0:9b3d4731edbb 167 /** Base address + 0x1C: Scratch offset*/
WFKnight 0:9b3d4731edbb 168 __IO uint32_t SCR; /**< Scratch pad register */
WFKnight 0:9b3d4731edbb 169 } Uart16C550Reg_t, *Uart16C550Reg_pt;
WFKnight 0:9b3d4731edbb 170
WFKnight 0:9b3d4731edbb 171 #endif /* UART_16C550_MAP_H_ */