Knight KE / Mbed OS Game_Master

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

mbed-os/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/config/adi_spi_config.h@0:9b3d4731edbb, 2018-06-21 (annotated)

Committer:
WFKnight
Date:
Thu Jun 21 13:51:43 2018 +0000
Revision:
0:9b3d4731edbb
UART, RTOS, LED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
WFKnight 0:9b3d4731edbb 1 /*!
WFKnight 0:9b3d4731edbb 2 *****************************************************************************
WFKnight 0:9b3d4731edbb 3 @file: adi_spi_config.h
WFKnight 0:9b3d4731edbb 4 @brief: Configuration options for SPI driver.
WFKnight 0:9b3d4731edbb 5 This is specific to the SPI driver and will be included by the driver.
WFKnight 0:9b3d4731edbb 6 It is not required for the application to include this header file.
WFKnight 0:9b3d4731edbb 7 -----------------------------------------------------------------------------
WFKnight 0:9b3d4731edbb 8
WFKnight 0:9b3d4731edbb 9 Copyright (c) 2016 Analog Devices, Inc.
WFKnight 0:9b3d4731edbb 10
WFKnight 0:9b3d4731edbb 11 All rights reserved.
WFKnight 0:9b3d4731edbb 12
WFKnight 0:9b3d4731edbb 13 Redistribution and use in source and binary forms, with or without modification,
WFKnight 0:9b3d4731edbb 14 are permitted provided that the following conditions are met:
WFKnight 0:9b3d4731edbb 15 - Redistributions of source code must retain the above copyright notice,
WFKnight 0:9b3d4731edbb 16 this list of conditions and the following disclaimer.
WFKnight 0:9b3d4731edbb 17 - Redistributions in binary form must reproduce the above copyright notice,
WFKnight 0:9b3d4731edbb 18 this list of conditions and the following disclaimer in the documentation
WFKnight 0:9b3d4731edbb 19 and/or other materials provided with the distribution.
WFKnight 0:9b3d4731edbb 20 - Modified versions of the software must be conspicuously marked as such.
WFKnight 0:9b3d4731edbb 21 - This software is licensed solely and exclusively for use with processors
WFKnight 0:9b3d4731edbb 22 manufactured by or for Analog Devices, Inc.
WFKnight 0:9b3d4731edbb 23 - This software may not be combined or merged with other code in any manner
WFKnight 0:9b3d4731edbb 24 that would cause the software to become subject to terms and conditions
WFKnight 0:9b3d4731edbb 25 which differ from those listed here.
WFKnight 0:9b3d4731edbb 26 - Neither the name of Analog Devices, Inc. nor the names of its
WFKnight 0:9b3d4731edbb 27 contributors may be used to endorse or promote products derived
WFKnight 0:9b3d4731edbb 28 from this software without specific prior written permission.
WFKnight 0:9b3d4731edbb 29 - The use of this software may or may not infringe the patent rights of one
WFKnight 0:9b3d4731edbb 30 or more patent holders. This license does not release you from the
WFKnight 0:9b3d4731edbb 31 requirement that you obtain separate licenses from these patent holders
WFKnight 0:9b3d4731edbb 32 to use this software.
WFKnight 0:9b3d4731edbb 33
WFKnight 0:9b3d4731edbb 34 THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES, INC. AND CONTRIBUTORS "AS IS" AND ANY
WFKnight 0:9b3d4731edbb 35 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
WFKnight 0:9b3d4731edbb 36 TITLE, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
WFKnight 0:9b3d4731edbb 37 NO EVENT SHALL ANALOG DEVICES, INC. OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
WFKnight 0:9b3d4731edbb 38 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, PUNITIVE OR CONSEQUENTIAL DAMAGES
WFKnight 0:9b3d4731edbb 39 (INCLUDING, BUT NOT LIMITED TO, DAMAGES ARISING OUT OF CLAIMS OF INTELLECTUAL
WFKnight 0:9b3d4731edbb 40 PROPERTY RIGHTS INFRINGEMENT; PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
WFKnight 0:9b3d4731edbb 41 OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
WFKnight 0:9b3d4731edbb 42 THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
WFKnight 0:9b3d4731edbb 43 NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
WFKnight 0:9b3d4731edbb 44 EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
WFKnight 0:9b3d4731edbb 45
WFKnight 0:9b3d4731edbb 46 *****************************************************************************/
WFKnight 0:9b3d4731edbb 47
WFKnight 0:9b3d4731edbb 48 #ifndef ADI_SPI_CONFIG_H__
WFKnight 0:9b3d4731edbb 49 #define ADI_SPI_CONFIG_H__
WFKnight 0:9b3d4731edbb 50 #include <adi_global_config.h>
WFKnight 0:9b3d4731edbb 51 /** @addtogroup SPI_Driver_Config Static Configuration
WFKnight 0:9b3d4731edbb 52 * @ingroup SPI_Driver
WFKnight 0:9b3d4731edbb 53 * @{
WFKnight 0:9b3d4731edbb 54 */
WFKnight 0:9b3d4731edbb 55
WFKnight 0:9b3d4731edbb 56
WFKnight 0:9b3d4731edbb 57 /*! Set this macro to the system clock frequency in hertz*/
WFKnight 0:9b3d4731edbb 58 #define ADI_CFG_SYSTEM_CLOCK_HZ (26000000u)
WFKnight 0:9b3d4731edbb 59
WFKnight 0:9b3d4731edbb 60 /************* SPI controller configurations ***************/
WFKnight 0:9b3d4731edbb 61
WFKnight 0:9b3d4731edbb 62 /* There are three SPI instances SPI0, SPI1 and SPI2 */
WFKnight 0:9b3d4731edbb 63 /* Each SPI has its own configuration macros */
WFKnight 0:9b3d4731edbb 64
WFKnight 0:9b3d4731edbb 65
WFKnight 0:9b3d4731edbb 66 /*----------------------------------------------------------*/
WFKnight 0:9b3d4731edbb 67 /* -------------------- SPI0 -------------------------------*/
WFKnight 0:9b3d4731edbb 68 /*----------------------------------------------------------*/
WFKnight 0:9b3d4731edbb 69
WFKnight 0:9b3d4731edbb 70 /** @addtogroup SPI_Driver_Config_SPI0 SPI0 Static Configuration
WFKnight 0:9b3d4731edbb 71 * @ingroup SPI_Driver_Config
WFKnight 0:9b3d4731edbb 72 * @{
WFKnight 0:9b3d4731edbb 73 */
WFKnight 0:9b3d4731edbb 74
WFKnight 0:9b3d4731edbb 75 /*! If using SPI0 in master mode set this macro to 1. For slave mode set this macro to 0. */
WFKnight 0:9b3d4731edbb 76 #define ADI_SPI0_MASTER_MODE (1u)
WFKnight 0:9b3d4731edbb 77
WFKnight 0:9b3d4731edbb 78
WFKnight 0:9b3d4731edbb 79 /*! Set this macro to the SPI0 bit rate in hertz */
WFKnight 0:9b3d4731edbb 80 #define ADI_SPI0_CFG_BIT_RATE (2000000u)
WFKnight 0:9b3d4731edbb 81
WFKnight 0:9b3d4731edbb 82 /*! SPI0 enable\n
WFKnight 0:9b3d4731edbb 83 SPI configuration register: Bit[0]\n
WFKnight 0:9b3d4731edbb 84 1 - Enable SPI\n
WFKnight 0:9b3d4731edbb 85 0 - Disable SPI */
WFKnight 0:9b3d4731edbb 86 #define ADI_SPI0_CFG_ENABLE (0u)
WFKnight 0:9b3d4731edbb 87
WFKnight 0:9b3d4731edbb 88 /*! SPI0 clock phase mode\n
WFKnight 0:9b3d4731edbb 89 SPI configuration register: Bit[2]\n
WFKnight 0:9b3d4731edbb 90 1 - Serial clock pulses at the beginning of each serial bit transfer.\n
WFKnight 0:9b3d4731edbb 91 0 - Serial clock pulses at the end of each serial bit transfer. */
WFKnight 0:9b3d4731edbb 92 #define ADI_SPI0_CFG_CLK_PHASE (0u)
WFKnight 0:9b3d4731edbb 93
WFKnight 0:9b3d4731edbb 94
WFKnight 0:9b3d4731edbb 95
WFKnight 0:9b3d4731edbb 96
WFKnight 0:9b3d4731edbb 97
WFKnight 0:9b3d4731edbb 98 /*! SPI0 clock polarity\n
WFKnight 0:9b3d4731edbb 99 SPI configuration register: Bit[3]\n
WFKnight 0:9b3d4731edbb 100 1 - Serial clock idles high.\n
WFKnight 0:9b3d4731edbb 101 0 - Serial clock idles low. */
WFKnight 0:9b3d4731edbb 102 #define ADI_SPI0_CFG_CLK_POLARITY (0u)
WFKnight 0:9b3d4731edbb 103
WFKnight 0:9b3d4731edbb 104
WFKnight 0:9b3d4731edbb 105 /*! SPI0 wired OR mode\n
WFKnight 0:9b3d4731edbb 106 SPI configuration register: Bit[4]\n
WFKnight 0:9b3d4731edbb 107 1 - Enables open circuit output enable.\n
WFKnight 0:9b3d4731edbb 108 0 - Normal output levels. */
WFKnight 0:9b3d4731edbb 109 #define ADI_SPI0_CFG_WIRED_OR (0u)
WFKnight 0:9b3d4731edbb 110
WFKnight 0:9b3d4731edbb 111
WFKnight 0:9b3d4731edbb 112 /*! SPI0 LSB/MSB\n
WFKnight 0:9b3d4731edbb 113 SPI configuration register: Bit[5]\n
WFKnight 0:9b3d4731edbb 114 1 - MSB transmitted first.\n
WFKnight 0:9b3d4731edbb 115 0 - LSB transmitted first. */
WFKnight 0:9b3d4731edbb 116 #define ADI_SPI0_CFG_LSB_MSB (0u)
WFKnight 0:9b3d4731edbb 117
WFKnight 0:9b3d4731edbb 118
WFKnight 0:9b3d4731edbb 119 /*! SPI0 transfer initiate\n
WFKnight 0:9b3d4731edbb 120 SPI configuration register: Bit[6]\n
WFKnight 0:9b3d4731edbb 121 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
WFKnight 0:9b3d4731edbb 122 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
WFKnight 0:9b3d4731edbb 123 #define ADI_SPI0_CFG_TRANSFER_INITIATE (0u)
WFKnight 0:9b3d4731edbb 124
WFKnight 0:9b3d4731edbb 125
WFKnight 0:9b3d4731edbb 126 /*! SPI0 Tx FIFO transfers zeros or last bit upon underflow\n
WFKnight 0:9b3d4731edbb 127 SPI configuration register: Bit[7]\n
WFKnight 0:9b3d4731edbb 128 1 - Tx FIFO sends zeros upon underflow.\n
WFKnight 0:9b3d4731edbb 129 0 - Tx FIFO repeats last bit upon underflow. */
WFKnight 0:9b3d4731edbb 130 #define ADI_SPI0_CFG_TX_UNDERFLOW (0u)
WFKnight 0:9b3d4731edbb 131
WFKnight 0:9b3d4731edbb 132
WFKnight 0:9b3d4731edbb 133 /*! SPI0 Rx FIFO overflows with received data or data is discarded\n
WFKnight 0:9b3d4731edbb 134 SPI configuration register: Bit[8]\n
WFKnight 0:9b3d4731edbb 135 1 - Rx FIFO receives data upon overflow.\n
WFKnight 0:9b3d4731edbb 136 0 - Rx FIFO discards received data upon overflow. */
WFKnight 0:9b3d4731edbb 137 #define ADI_SPI0_CFG_RX_OVERFLOW (0u)
WFKnight 0:9b3d4731edbb 138
WFKnight 0:9b3d4731edbb 139
WFKnight 0:9b3d4731edbb 140 /*! SPI0 slave mode MISO enable\n
WFKnight 0:9b3d4731edbb 141 SPI configuration register: Bit[9]\n
WFKnight 0:9b3d4731edbb 142 1 - MISO operates as normal in slave mode.\n
WFKnight 0:9b3d4731edbb 143 0 - MISO is disabled in slave mode. */
WFKnight 0:9b3d4731edbb 144 #define ADI_SPI0_CFG_MISO_ENABLE (0u)
WFKnight 0:9b3d4731edbb 145
WFKnight 0:9b3d4731edbb 146
WFKnight 0:9b3d4731edbb 147 /*! SPI0 internal loopback enable\n
WFKnight 0:9b3d4731edbb 148 SPI configuration register: Bit[10]\n
WFKnight 0:9b3d4731edbb 149 1 - MISO and MOSI is loopbacked internally.\n
WFKnight 0:9b3d4731edbb 150 0 - MISO and MOSI operates normally. */
WFKnight 0:9b3d4731edbb 151 #define ADI_SPI0_CFG_LOOPBACK (0u)
WFKnight 0:9b3d4731edbb 152
WFKnight 0:9b3d4731edbb 153 /*! SPI0 transfer and interrupt mode\n
WFKnight 0:9b3d4731edbb 154 SPI configuration register: Bit[11]\n
WFKnight 0:9b3d4731edbb 155 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
WFKnight 0:9b3d4731edbb 156 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
WFKnight 0:9b3d4731edbb 157 #define ADI_SPI0_CFG_CONTINUOUS (0u)
WFKnight 0:9b3d4731edbb 158
WFKnight 0:9b3d4731edbb 159 /*! SPI0 Rx FIFO flush enable\n
WFKnight 0:9b3d4731edbb 160 SPI configuration register: Bit[12]\n
WFKnight 0:9b3d4731edbb 161 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
WFKnight 0:9b3d4731edbb 162 0 - Rx FIFO flush is disabled. */
WFKnight 0:9b3d4731edbb 163 #define ADI_SPI0_CFG_RX_FLUSH (0u)
WFKnight 0:9b3d4731edbb 164
WFKnight 0:9b3d4731edbb 165
WFKnight 0:9b3d4731edbb 166 /*! SPI0 Tx FIFO flush enable\n
WFKnight 0:9b3d4731edbb 167 SPI configuration register: Bit[13]\n
WFKnight 0:9b3d4731edbb 168 1 - Tx FIFO is flushed.\n
WFKnight 0:9b3d4731edbb 169 0 - Tx FIFO flush is disabled. */
WFKnight 0:9b3d4731edbb 170 #define ADI_SPI0_CFG_TX_FLUSH (0u)
WFKnight 0:9b3d4731edbb 171
WFKnight 0:9b3d4731edbb 172
WFKnight 0:9b3d4731edbb 173 /*! Reset Mode for CSERR. \n
WFKnight 0:9b3d4731edbb 174 SPI0 configuration register: Bit[14]\n
WFKnight 0:9b3d4731edbb 175 0 - To continue from where it stopped. SPI can receive the remaining bits
WFKnight 0:9b3d4731edbb 176 when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
WFKnight 0:9b3d4731edbb 177 1 - To enable resetting the bit counter and reset if there is a
WFKnight 0:9b3d4731edbb 178 CS error condition and the Cortex is expected to clear the SPI_EN bit.
WFKnight 0:9b3d4731edbb 179 */
WFKnight 0:9b3d4731edbb 180 #define ADI_SPI0_CFG_CSERR_RESET (0u)
WFKnight 0:9b3d4731edbb 181
WFKnight 0:9b3d4731edbb 182
WFKnight 0:9b3d4731edbb 183 /*! SPI0 clock divide\n
WFKnight 0:9b3d4731edbb 184 SPI baud rate selection register: Bit[0:5]\n
WFKnight 0:9b3d4731edbb 185 Value between 0-63 that is used to divide the UCLK to generate
WFKnight 0:9b3d4731edbb 186 the SPI serial clock. */
WFKnight 0:9b3d4731edbb 187 #define ADI_SPI0_CFG_CLK_DIV (0u)
WFKnight 0:9b3d4731edbb 188
WFKnight 0:9b3d4731edbb 189
WFKnight 0:9b3d4731edbb 190 /*! SPI0 high frequency mode\n
WFKnight 0:9b3d4731edbb 191 SPI baud rate selection register: Bit[6]\n
WFKnight 0:9b3d4731edbb 192 1 - High frequency mode enabled.\n
WFKnight 0:9b3d4731edbb 193 0 - High frequency mode disabled. */
WFKnight 0:9b3d4731edbb 194 #define ADI_SPI0_CFG_HFM (0u)
WFKnight 0:9b3d4731edbb 195
WFKnight 0:9b3d4731edbb 196
WFKnight 0:9b3d4731edbb 197 /*! SPI0 reset mode for CSERR\n
WFKnight 0:9b3d4731edbb 198 SPI baud rate selection register: Bit[7]\n
WFKnight 0:9b3d4731edbb 199 1 - clear bit counter on CS error.\n
WFKnight 0:9b3d4731edbb 200 0 - do not clear bit counter on CS error. */
WFKnight 0:9b3d4731edbb 201 #define ADI_SPI0_CFG_CS_ERR (0u)
WFKnight 0:9b3d4731edbb 202
WFKnight 0:9b3d4731edbb 203
WFKnight 0:9b3d4731edbb 204 /*! SPI0 CS interrupt\n
WFKnight 0:9b3d4731edbb 205 SPI baud rate selection register: Bit[8]\n
WFKnight 0:9b3d4731edbb 206 1 - In continuous mode, generate interrupt on CS.\n
WFKnight 0:9b3d4731edbb 207 0 - In continuous mode, do not generate interrupt on CS. */
WFKnight 0:9b3d4731edbb 208 #define ADI_SPI0_CFG_CS_IRQ (0u)
WFKnight 0:9b3d4731edbb 209
WFKnight 0:9b3d4731edbb 210
WFKnight 0:9b3d4731edbb 211 /*! @} */
WFKnight 0:9b3d4731edbb 212
WFKnight 0:9b3d4731edbb 213 /*----------------------------------------------------------*/
WFKnight 0:9b3d4731edbb 214 /* -------------------- SPI1 -------------------------------*/
WFKnight 0:9b3d4731edbb 215 /*----------------------------------------------------------*/
WFKnight 0:9b3d4731edbb 216
WFKnight 0:9b3d4731edbb 217 /** @addtogroup SPI_Driver_Config_SPI1 SPI1 Static Configuration
WFKnight 0:9b3d4731edbb 218 * @ingroup SPI_Driver_Config
WFKnight 0:9b3d4731edbb 219 * @{
WFKnight 0:9b3d4731edbb 220 */
WFKnight 0:9b3d4731edbb 221
WFKnight 0:9b3d4731edbb 222 /*! If using SPI1 in master mode set this macro to 1. For slave mode set this macro to 0. */
WFKnight 0:9b3d4731edbb 223 #define ADI_SPI1_MASTER_MODE (1u)
WFKnight 0:9b3d4731edbb 224
WFKnight 0:9b3d4731edbb 225 /*! Set this macro to the SPI1 bit rate in hertz */
WFKnight 0:9b3d4731edbb 226 #define ADI_SPI1_CFG_BIT_RATE (2000000u)
WFKnight 0:9b3d4731edbb 227
WFKnight 0:9b3d4731edbb 228 /*! SPI1 enable\n
WFKnight 0:9b3d4731edbb 229 SPI configuration register: Bit[0]\n
WFKnight 0:9b3d4731edbb 230 1 - Enable SPI\n
WFKnight 0:9b3d4731edbb 231 0 - Disable SPI */
WFKnight 0:9b3d4731edbb 232 #define ADI_SPI1_CFG_ENABLE (0u)
WFKnight 0:9b3d4731edbb 233
WFKnight 0:9b3d4731edbb 234 /*! SPI1 clock phase mode\n
WFKnight 0:9b3d4731edbb 235 SPI configuration register: Bit[2]\n
WFKnight 0:9b3d4731edbb 236 1 - Serial clock pulses at the beginning of each serial bit transfer.\n
WFKnight 0:9b3d4731edbb 237 0 - Serial clock pulses at the end of each serial bit transfer. */
WFKnight 0:9b3d4731edbb 238 #define ADI_SPI1_CFG_CLK_PHASE (0u)
WFKnight 0:9b3d4731edbb 239
WFKnight 0:9b3d4731edbb 240
WFKnight 0:9b3d4731edbb 241
WFKnight 0:9b3d4731edbb 242
WFKnight 0:9b3d4731edbb 243
WFKnight 0:9b3d4731edbb 244 /*! SPI1 clock polarity\n
WFKnight 0:9b3d4731edbb 245 SPI configuration register: Bit[3]\n
WFKnight 0:9b3d4731edbb 246 1 - Serial clock idles high.\n
WFKnight 0:9b3d4731edbb 247 0 - Serial clock idles low. */
WFKnight 0:9b3d4731edbb 248 #define ADI_SPI1_CFG_CLK_POLARITY (0u)
WFKnight 0:9b3d4731edbb 249
WFKnight 0:9b3d4731edbb 250
WFKnight 0:9b3d4731edbb 251 /*! SPI1 wired OR mode\n
WFKnight 0:9b3d4731edbb 252 SPI configuration register: Bit[4]\n
WFKnight 0:9b3d4731edbb 253 1 - Enables open circuit output enable.\n
WFKnight 0:9b3d4731edbb 254 0 - Normal output levels. */
WFKnight 0:9b3d4731edbb 255 #define ADI_SPI1_CFG_WIRED_OR (0u)
WFKnight 0:9b3d4731edbb 256
WFKnight 0:9b3d4731edbb 257
WFKnight 0:9b3d4731edbb 258 /*! SPI1 LSB/MSB\n
WFKnight 0:9b3d4731edbb 259 SPI configuration register: Bit[5]\n
WFKnight 0:9b3d4731edbb 260 1 - MSB transmitted first.\n
WFKnight 0:9b3d4731edbb 261 0 - LSB transmitted first. */
WFKnight 0:9b3d4731edbb 262 #define ADI_SPI1_CFG_LSB_MSB (0u)
WFKnight 0:9b3d4731edbb 263
WFKnight 0:9b3d4731edbb 264
WFKnight 0:9b3d4731edbb 265 /*! SPI1 transfer initiate\n
WFKnight 0:9b3d4731edbb 266 SPI configuration register: Bit[6]\n
WFKnight 0:9b3d4731edbb 267 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
WFKnight 0:9b3d4731edbb 268 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
WFKnight 0:9b3d4731edbb 269 #define ADI_SPI1_CFG_TRANSFER_INITIATE (0u)
WFKnight 0:9b3d4731edbb 270
WFKnight 0:9b3d4731edbb 271
WFKnight 0:9b3d4731edbb 272 /*! SPI1 Tx FIFO transfers zeros or last bit upon underflow\n
WFKnight 0:9b3d4731edbb 273 SPI configuration register: Bit[7]\n
WFKnight 0:9b3d4731edbb 274 1 - Tx FIFO sends zeros upon underflow.\n
WFKnight 0:9b3d4731edbb 275 0 - Tx FIFO repeats last bit upon underflow. */
WFKnight 0:9b3d4731edbb 276 #define ADI_SPI1_CFG_TX_UNDERFLOW (0u)
WFKnight 0:9b3d4731edbb 277
WFKnight 0:9b3d4731edbb 278
WFKnight 0:9b3d4731edbb 279 /*! SPI1 Rx FIFO overflows with received data or data is discarded\n
WFKnight 0:9b3d4731edbb 280 SPI configuration register: Bit[8]\n
WFKnight 0:9b3d4731edbb 281 1 - Rx FIFO receives data upon overflow.\n
WFKnight 0:9b3d4731edbb 282 0 - Rx FIFO discards received data upon overflow. */
WFKnight 0:9b3d4731edbb 283 #define ADI_SPI1_CFG_RX_OVERFLOW (0u)
WFKnight 0:9b3d4731edbb 284
WFKnight 0:9b3d4731edbb 285
WFKnight 0:9b3d4731edbb 286 /*! SPI1 slave mode MISO enable\n
WFKnight 0:9b3d4731edbb 287 SPI configuration register: Bit[9]\n
WFKnight 0:9b3d4731edbb 288 1 - MISO operates as normal in slave mode.\n
WFKnight 0:9b3d4731edbb 289 0 - MISO is disabled in slave mode. */
WFKnight 0:9b3d4731edbb 290 #define ADI_SPI1_CFG_MISO_ENABLE (0u)
WFKnight 0:9b3d4731edbb 291
WFKnight 0:9b3d4731edbb 292
WFKnight 0:9b3d4731edbb 293 /*! SPI1 internal loopback enable\n
WFKnight 0:9b3d4731edbb 294 SPI configuration register: Bit[10]\n
WFKnight 0:9b3d4731edbb 295 1 - MISO and MOSI is loopbacked internally.\n
WFKnight 0:9b3d4731edbb 296 0 - MISO and MOSI operates normally. */
WFKnight 0:9b3d4731edbb 297 #define ADI_SPI1_CFG_LOOPBACK (0u)
WFKnight 0:9b3d4731edbb 298
WFKnight 0:9b3d4731edbb 299 /*! SPI1 transfer and interrupt mode\n
WFKnight 0:9b3d4731edbb 300 SPI configuration register: Bit[11]\n
WFKnight 0:9b3d4731edbb 301 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
WFKnight 0:9b3d4731edbb 302 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
WFKnight 0:9b3d4731edbb 303 #define ADI_SPI1_CFG_CONTINUOUS (0u)
WFKnight 0:9b3d4731edbb 304
WFKnight 0:9b3d4731edbb 305 /*! SPI1 Rx FIFO flush enable\n
WFKnight 0:9b3d4731edbb 306 SPI configuration register: Bit[12]\n
WFKnight 0:9b3d4731edbb 307 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
WFKnight 0:9b3d4731edbb 308 0 - Rx FIFO flush is disabled. */
WFKnight 0:9b3d4731edbb 309 #define ADI_SPI1_CFG_RX_FLUSH (0u)
WFKnight 0:9b3d4731edbb 310
WFKnight 0:9b3d4731edbb 311
WFKnight 0:9b3d4731edbb 312 /*! SPI1 Tx FIFO flush enable\n
WFKnight 0:9b3d4731edbb 313 SPI configuration register: Bit[13]\n
WFKnight 0:9b3d4731edbb 314 1 - Tx FIFO is flushed.\n
WFKnight 0:9b3d4731edbb 315 0 - Tx FIFO flush is disabled. */
WFKnight 0:9b3d4731edbb 316 #define ADI_SPI1_CFG_TX_FLUSH (0u)
WFKnight 0:9b3d4731edbb 317
WFKnight 0:9b3d4731edbb 318
WFKnight 0:9b3d4731edbb 319 /*! Reset Mode for CSERR. \n
WFKnight 0:9b3d4731edbb 320 SPI1 configuration register: Bit[14]\n
WFKnight 0:9b3d4731edbb 321 0 - To continue from where it stopped. SPI can receive the remaining bits
WFKnight 0:9b3d4731edbb 322 when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
WFKnight 0:9b3d4731edbb 323 1 - To enable resetting the bit counter and reset if there is a
WFKnight 0:9b3d4731edbb 324 CS error condition and the Cortex is expected to clear the SPI_EN bit.
WFKnight 0:9b3d4731edbb 325 */
WFKnight 0:9b3d4731edbb 326 #define ADI_SPI1_CFG_CSERR_RESET (0u)
WFKnight 0:9b3d4731edbb 327
WFKnight 0:9b3d4731edbb 328
WFKnight 0:9b3d4731edbb 329 /*! SPI1 clock divide\n
WFKnight 0:9b3d4731edbb 330 SPI baud rate selection register: Bit[0:5]\n
WFKnight 0:9b3d4731edbb 331 Value between 0-63 that is used to divide the UCLK to generate
WFKnight 0:9b3d4731edbb 332 the SPI serial clock. */
WFKnight 0:9b3d4731edbb 333 #define ADI_SPI1_CFG_CLK_DIV (0u)
WFKnight 0:9b3d4731edbb 334
WFKnight 0:9b3d4731edbb 335
WFKnight 0:9b3d4731edbb 336 /*! SPI1 high frequency mode\n
WFKnight 0:9b3d4731edbb 337 SPI baud rate selection register: Bit[6]\n
WFKnight 0:9b3d4731edbb 338 1 - High frequency mode enabled.\n
WFKnight 0:9b3d4731edbb 339 0 - High frequency mode disabled. */
WFKnight 0:9b3d4731edbb 340 #define ADI_SPI1_CFG_HFM (0u)
WFKnight 0:9b3d4731edbb 341
WFKnight 0:9b3d4731edbb 342
WFKnight 0:9b3d4731edbb 343 /*! SPI1 reset mode for CSERR\n
WFKnight 0:9b3d4731edbb 344 SPI baud rate selection register: Bit[7]\n
WFKnight 0:9b3d4731edbb 345 1 - clear bit counter on CS error.\n
WFKnight 0:9b3d4731edbb 346 0 - do not clear bit counter on CS error. */
WFKnight 0:9b3d4731edbb 347 #define ADI_SPI1_CFG_CS_ERR (0u)
WFKnight 0:9b3d4731edbb 348
WFKnight 0:9b3d4731edbb 349
WFKnight 0:9b3d4731edbb 350 /*! SPI1 CS interrupt\n
WFKnight 0:9b3d4731edbb 351 SPI baud rate selection register: Bit[8]\n
WFKnight 0:9b3d4731edbb 352 1 - In continuous mode, generate interrupt on CS.\n
WFKnight 0:9b3d4731edbb 353 0 - In continuous mode, do not generate interrupt on CS. */
WFKnight 0:9b3d4731edbb 354 #define ADI_SPI1_CFG_CS_IRQ
WFKnight 0:9b3d4731edbb 355
WFKnight 0:9b3d4731edbb 356 /*! @} */
WFKnight 0:9b3d4731edbb 357
WFKnight 0:9b3d4731edbb 358 /*----------------------------------------------------------*/
WFKnight 0:9b3d4731edbb 359 /* -------------------- SPI2 -------------------------------*/
WFKnight 0:9b3d4731edbb 360 /*----------------------------------------------------------*/
WFKnight 0:9b3d4731edbb 361
WFKnight 0:9b3d4731edbb 362 /** @addtogroup SPI_Driver_Config_SPI2 SPI2 Static Configuration
WFKnight 0:9b3d4731edbb 363 * @ingroup SP2_Driver_Config
WFKnight 0:9b3d4731edbb 364 * @{
WFKnight 0:9b3d4731edbb 365 */
WFKnight 0:9b3d4731edbb 366
WFKnight 0:9b3d4731edbb 367 /*! If using SPI2 in master mode set this macro to 1. For slave mode set this macro to 0. */
WFKnight 0:9b3d4731edbb 368 #define ADI_SPI2_MASTER_MODE (1u)
WFKnight 0:9b3d4731edbb 369
WFKnight 0:9b3d4731edbb 370 /*! Set this macro to the SPI2 bit rate in hertz */
WFKnight 0:9b3d4731edbb 371 #define ADI_SPI2_CFG_BIT_RATE (2000000u)
WFKnight 0:9b3d4731edbb 372
WFKnight 0:9b3d4731edbb 373 /*! SPI2 enable\n
WFKnight 0:9b3d4731edbb 374 SPI configuration register: Bit[0]\n
WFKnight 0:9b3d4731edbb 375 1 - Enable SPI\n
WFKnight 0:9b3d4731edbb 376 0 - Disable SPI */
WFKnight 0:9b3d4731edbb 377 #define ADI_SPI2_CFG_ENABLE (0u)
WFKnight 0:9b3d4731edbb 378
WFKnight 0:9b3d4731edbb 379 /*! SPI2 clock phase mode\n
WFKnight 0:9b3d4731edbb 380 SPI configuration register: Bit[2]\n
WFKnight 0:9b3d4731edbb 381 1 - Serial clock pulses at the beginning of each serial bit transfer.\n
WFKnight 0:9b3d4731edbb 382 0 - Serial clock pulses at the end of each serial bit transfer. */
WFKnight 0:9b3d4731edbb 383 #define ADI_SPI2_CFG_CLK_PHASE (0u)
WFKnight 0:9b3d4731edbb 384
WFKnight 0:9b3d4731edbb 385
WFKnight 0:9b3d4731edbb 386
WFKnight 0:9b3d4731edbb 387
WFKnight 0:9b3d4731edbb 388
WFKnight 0:9b3d4731edbb 389 /*! SPI2 clock polarity\n
WFKnight 0:9b3d4731edbb 390 SPI configuration register: Bit[3]\n
WFKnight 0:9b3d4731edbb 391 1 - Serial clock idles high.\n
WFKnight 0:9b3d4731edbb 392 0 - Serial clock idles low. */
WFKnight 0:9b3d4731edbb 393 #define ADI_SPI2_CFG_CLK_POLARITY (0u)
WFKnight 0:9b3d4731edbb 394
WFKnight 0:9b3d4731edbb 395
WFKnight 0:9b3d4731edbb 396 /*! SPI2 wired OR mode\n
WFKnight 0:9b3d4731edbb 397 SPI configuration register: Bit[4]\n
WFKnight 0:9b3d4731edbb 398 1 - Enables open circuit output enable.\n
WFKnight 0:9b3d4731edbb 399 0 - Normal output levels. */
WFKnight 0:9b3d4731edbb 400 #define ADI_SPI2_CFG_WIRED_OR (0u)
WFKnight 0:9b3d4731edbb 401
WFKnight 0:9b3d4731edbb 402
WFKnight 0:9b3d4731edbb 403 /*! SPI2 LSB/MSB\n
WFKnight 0:9b3d4731edbb 404 SPI configuration register: Bit[5]\n
WFKnight 0:9b3d4731edbb 405 1 - MSB transmitted first.\n
WFKnight 0:9b3d4731edbb 406 0 - LSB transmitted first. */
WFKnight 0:9b3d4731edbb 407 #define ADI_SPI2_CFG_LSB_MSB (0u)
WFKnight 0:9b3d4731edbb 408
WFKnight 0:9b3d4731edbb 409
WFKnight 0:9b3d4731edbb 410 /*! SPI2 transfer initiate\n
WFKnight 0:9b3d4731edbb 411 SPI configuration register: Bit[6]\n
WFKnight 0:9b3d4731edbb 412 1 - SPI transfer is initiated with write to Tx FIFO register. Interrupts when Tx is empty.\n
WFKnight 0:9b3d4731edbb 413 0 - SPI transfer is initiated with a read of the Rx FIFO register. Interrupts when Rx is full.*/
WFKnight 0:9b3d4731edbb 414 #define ADI_SPI2_CFG_TRANSFER_INITIATE (0u)
WFKnight 0:9b3d4731edbb 415
WFKnight 0:9b3d4731edbb 416
WFKnight 0:9b3d4731edbb 417 /*! SPI2 Tx FIFO transfers zeros or last bit upon underflow\n
WFKnight 0:9b3d4731edbb 418 SPI configuration register: Bit[7]\n
WFKnight 0:9b3d4731edbb 419 1 - Tx FIFO sends zeros upon underflow.\n
WFKnight 0:9b3d4731edbb 420 0 - Tx FIFO repeats last bit upon underflow. */
WFKnight 0:9b3d4731edbb 421 #define ADI_SPI2_CFG_TX_UNDERFLOW (0u)
WFKnight 0:9b3d4731edbb 422
WFKnight 0:9b3d4731edbb 423
WFKnight 0:9b3d4731edbb 424 /*! SPI2 Rx FIFO overflows with received data or data is discarded\n
WFKnight 0:9b3d4731edbb 425 SPI configuration register: Bit[8]\n
WFKnight 0:9b3d4731edbb 426 1 - Rx FIFO receives data upon overflow.\n
WFKnight 0:9b3d4731edbb 427 0 - Rx FIFO discards received data upon overflow. */
WFKnight 0:9b3d4731edbb 428 #define ADI_SPI2_CFG_RX_OVERFLOW (0u)
WFKnight 0:9b3d4731edbb 429
WFKnight 0:9b3d4731edbb 430
WFKnight 0:9b3d4731edbb 431 /*! SPI2 slave mode MISO enable\n
WFKnight 0:9b3d4731edbb 432 SPI configuration register: Bit[9]\n
WFKnight 0:9b3d4731edbb 433 1 - MISO operates as normal in slave mode.\n
WFKnight 0:9b3d4731edbb 434 0 - MISO is disabled in slave mode. */
WFKnight 0:9b3d4731edbb 435 #define ADI_SPI2_CFG_MISO_ENABLE (0u)
WFKnight 0:9b3d4731edbb 436
WFKnight 0:9b3d4731edbb 437
WFKnight 0:9b3d4731edbb 438 /*! SPI2 internal loopback enable\n
WFKnight 0:9b3d4731edbb 439 SPI configuration register: Bit[10]\n
WFKnight 0:9b3d4731edbb 440 1 - MISO and MOSI is loopbacked internally.\n
WFKnight 0:9b3d4731edbb 441 0 - MISO and MOSI operates normally. */
WFKnight 0:9b3d4731edbb 442 #define ADI_SPI2_CFG_LOOPBACK (0u)
WFKnight 0:9b3d4731edbb 443
WFKnight 0:9b3d4731edbb 444 /*! SPI2 transfer and interrupt mode\n
WFKnight 0:9b3d4731edbb 445 SPI configuration register: Bit[11]\n
WFKnight 0:9b3d4731edbb 446 1 - SPI continuous transfers in which CS remains asserted until Tx is empty.\n
WFKnight 0:9b3d4731edbb 447 0 - SPI disable continuous transfer, each transfer consists of 8 bits of data.*/
WFKnight 0:9b3d4731edbb 448 #define ADI_SPI2_CFG_CONTINUOUS (0u)
WFKnight 0:9b3d4731edbb 449
WFKnight 0:9b3d4731edbb 450 /*! SPI2 Rx FIFO flush enable\n
WFKnight 0:9b3d4731edbb 451 SPI configuration register: Bit[12]\n
WFKnight 0:9b3d4731edbb 452 1 - Rx FIFO is flushed and all rx data is ignored and no interrupts are generated.\n
WFKnight 0:9b3d4731edbb 453 0 - Rx FIFO flush is disabled. */
WFKnight 0:9b3d4731edbb 454 #define ADI_SPI2_CFG_RX_FLUSH (0u)
WFKnight 0:9b3d4731edbb 455
WFKnight 0:9b3d4731edbb 456
WFKnight 0:9b3d4731edbb 457 /*! SPI2 Tx FIFO flush enable\n
WFKnight 0:9b3d4731edbb 458 SPI configuration register: Bit[13]\n
WFKnight 0:9b3d4731edbb 459 1 - Tx FIFO is flushed.\n
WFKnight 0:9b3d4731edbb 460 0 - Tx FIFO flush is disabled. */
WFKnight 0:9b3d4731edbb 461 #define ADI_SPI2_CFG_TX_FLUSH (0u)
WFKnight 0:9b3d4731edbb 462
WFKnight 0:9b3d4731edbb 463
WFKnight 0:9b3d4731edbb 464 /*! Reset Mode for CSERR. \n
WFKnight 0:9b3d4731edbb 465 SPI2 configuration register: Bit[14]\n
WFKnight 0:9b3d4731edbb 466 0 - To continue from where it stopped. SPI can receive the remaining bits
WFKnight 0:9b3d4731edbb 467 when CS gets asserted and Cortex has to ignore the CSERR interrupt.\n
WFKnight 0:9b3d4731edbb 468 1 - To enable resetting the bit counter and reset if there is a
WFKnight 0:9b3d4731edbb 469 CS error condition and the Cortex is expected to clear the SPI_EN bit.
WFKnight 0:9b3d4731edbb 470 */
WFKnight 0:9b3d4731edbb 471 #define ADI_SPI2_CFG_CSERR_RESET (0u)
WFKnight 0:9b3d4731edbb 472
WFKnight 0:9b3d4731edbb 473
WFKnight 0:9b3d4731edbb 474 /*! SPI2 clock divide\n
WFKnight 0:9b3d4731edbb 475 SPI baud rate selection register: Bit[0:5]\n
WFKnight 0:9b3d4731edbb 476 Value between 0-63 that is used to divide the UCLK to generate
WFKnight 0:9b3d4731edbb 477 the SPI serial clock. */
WFKnight 0:9b3d4731edbb 478 #define ADI_SPI2_CFG_CLK_DIV (0u)
WFKnight 0:9b3d4731edbb 479
WFKnight 0:9b3d4731edbb 480
WFKnight 0:9b3d4731edbb 481 /*! SPI2 high frequency mode\n
WFKnight 0:9b3d4731edbb 482 SPI baud rate selection register: Bit[6]\n
WFKnight 0:9b3d4731edbb 483 1 - High frequency mode enabled.\n
WFKnight 0:9b3d4731edbb 484 0 - High frequency mode disabled. */
WFKnight 0:9b3d4731edbb 485 #define ADI_SPI2_CFG_HFM (0u)
WFKnight 0:9b3d4731edbb 486
WFKnight 0:9b3d4731edbb 487
WFKnight 0:9b3d4731edbb 488 /*! SPI2 reset mode for CSERR\n
WFKnight 0:9b3d4731edbb 489 SPI baud rate selection register: Bit[7]\n
WFKnight 0:9b3d4731edbb 490 1 - clear bit counter on CS error.\n
WFKnight 0:9b3d4731edbb 491 0 - do not clear bit counter on CS error. */
WFKnight 0:9b3d4731edbb 492 #define ADI_SPI2_CFG_CS_ERR (0u)
WFKnight 0:9b3d4731edbb 493
WFKnight 0:9b3d4731edbb 494
WFKnight 0:9b3d4731edbb 495 /*! SPI2 CS interrupt\n
WFKnight 0:9b3d4731edbb 496 SPI baud rate selection register: Bit[8]\n
WFKnight 0:9b3d4731edbb 497 1 - In continuous mode, generate interrupt on CS.\n
WFKnight 0:9b3d4731edbb 498 0 - In continuous mode, do not generate interrupt on CS. */
WFKnight 0:9b3d4731edbb 499 #define ADI_SPI2_CFG_CS_IRQ
WFKnight 0:9b3d4731edbb 500
WFKnight 0:9b3d4731edbb 501 /*! @} */
WFKnight 0:9b3d4731edbb 502
WFKnight 0:9b3d4731edbb 503 /************** Macro validation *****************************/
WFKnight 0:9b3d4731edbb 504
WFKnight 0:9b3d4731edbb 505 #if ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \
WFKnight 0:9b3d4731edbb 506 ( ADI_SPI0_CFG_BIT_RATE > (13000000u) ) || \
WFKnight 0:9b3d4731edbb 507 ( ADI_SPI0_CFG_BIT_RATE > (13000000u) )
WFKnight 0:9b3d4731edbb 508 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 509 #endif
WFKnight 0:9b3d4731edbb 510
WFKnight 0:9b3d4731edbb 511 #if ( ADI_SPI0_CFG_ENABLE > 1u ) || \
WFKnight 0:9b3d4731edbb 512 ( ADI_SPI1_CFG_ENABLE > 1u ) || \
WFKnight 0:9b3d4731edbb 513 ( ADI_SPI2_CFG_ENABLE > 1u )
WFKnight 0:9b3d4731edbb 514 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 515 #endif
WFKnight 0:9b3d4731edbb 516
WFKnight 0:9b3d4731edbb 517 #if ( ADI_SPI0_CFG_CLK_PHASE > 1u ) || \
WFKnight 0:9b3d4731edbb 518 ( ADI_SPI1_CFG_CLK_PHASE > 1u ) || \
WFKnight 0:9b3d4731edbb 519 ( ADI_SPI2_CFG_CLK_PHASE > 1u )
WFKnight 0:9b3d4731edbb 520 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 521 #endif
WFKnight 0:9b3d4731edbb 522
WFKnight 0:9b3d4731edbb 523 #if ( ADI_SPI0_CFG_CLK_POLARITY > 1u ) || \
WFKnight 0:9b3d4731edbb 524 ( ADI_SPI1_CFG_CLK_POLARITY > 1u ) || \
WFKnight 0:9b3d4731edbb 525 ( ADI_SPI2_CFG_CLK_POLARITY > 1u )
WFKnight 0:9b3d4731edbb 526 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 527 #endif
WFKnight 0:9b3d4731edbb 528
WFKnight 0:9b3d4731edbb 529 #if ( ADI_SPI0_CFG_WIRED_OR > 1u ) || \
WFKnight 0:9b3d4731edbb 530 ( ADI_SPI1_CFG_WIRED_OR > 1u ) || \
WFKnight 0:9b3d4731edbb 531 ( ADI_SPI2_CFG_WIRED_OR > 1u )
WFKnight 0:9b3d4731edbb 532 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 533 #endif
WFKnight 0:9b3d4731edbb 534
WFKnight 0:9b3d4731edbb 535 #if ( ADI_SPI0_CFG_LSB_MSB > 1u ) || \
WFKnight 0:9b3d4731edbb 536 ( ADI_SPI1_CFG_LSB_MSB > 1u ) || \
WFKnight 0:9b3d4731edbb 537 ( ADI_SPI2_CFG_LSB_MSB > 1u )
WFKnight 0:9b3d4731edbb 538 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 539 #endif
WFKnight 0:9b3d4731edbb 540
WFKnight 0:9b3d4731edbb 541 #if ( ADI_SPI0_CFG_TRANSFER_INITIATE > 1u ) || \
WFKnight 0:9b3d4731edbb 542 ( ADI_SPI1_CFG_TRANSFER_INITIATE > 1u ) || \
WFKnight 0:9b3d4731edbb 543 ( ADI_SPI2_CFG_TRANSFER_INITIATE > 1u )
WFKnight 0:9b3d4731edbb 544 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 545 #endif
WFKnight 0:9b3d4731edbb 546
WFKnight 0:9b3d4731edbb 547 #if ( ADI_SPI0_CFG_TX_UNDERFLOW > 1u ) || \
WFKnight 0:9b3d4731edbb 548 ( ADI_SPI1_CFG_TX_UNDERFLOW > 1u ) || \
WFKnight 0:9b3d4731edbb 549 ( ADI_SPI2_CFG_TX_UNDERFLOW > 1u )
WFKnight 0:9b3d4731edbb 550 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 551 #endif
WFKnight 0:9b3d4731edbb 552
WFKnight 0:9b3d4731edbb 553 #if ( ADI_SPI0_CFG_RX_OVERFLOW > 1u ) || \
WFKnight 0:9b3d4731edbb 554 ( ADI_SPI1_CFG_RX_OVERFLOW > 1u ) || \
WFKnight 0:9b3d4731edbb 555 ( ADI_SPI2_CFG_RX_OVERFLOW > 1u )
WFKnight 0:9b3d4731edbb 556 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 557 #endif
WFKnight 0:9b3d4731edbb 558
WFKnight 0:9b3d4731edbb 559 #if ( ADI_SPI0_CFG_MISO_ENABLE > 1u ) || \
WFKnight 0:9b3d4731edbb 560 ( ADI_SPI1_CFG_MISO_ENABLE > 1u ) || \
WFKnight 0:9b3d4731edbb 561 ( ADI_SPI2_CFG_MISO_ENABLE > 1u )
WFKnight 0:9b3d4731edbb 562 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 563 #endif
WFKnight 0:9b3d4731edbb 564
WFKnight 0:9b3d4731edbb 565 #if ( ADI_SPI0_CFG_LOOPBACK > 1u ) || \
WFKnight 0:9b3d4731edbb 566 ( ADI_SPI1_CFG_LOOPBACK > 1u ) || \
WFKnight 0:9b3d4731edbb 567 ( ADI_SPI2_CFG_LOOPBACK > 1u )
WFKnight 0:9b3d4731edbb 568 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 569 #endif
WFKnight 0:9b3d4731edbb 570
WFKnight 0:9b3d4731edbb 571 #if ( ADI_SPI0_CFG_CONTINUOUS > 1u ) || \
WFKnight 0:9b3d4731edbb 572 ( ADI_SPI1_CFG_CONTINUOUS > 1u ) || \
WFKnight 0:9b3d4731edbb 573 ( ADI_SPI2_CFG_CONTINUOUS > 1u )
WFKnight 0:9b3d4731edbb 574 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 575 #endif
WFKnight 0:9b3d4731edbb 576
WFKnight 0:9b3d4731edbb 577 #if ( ADI_SPI0_CFG_RX_FLUSH > 1u ) || \
WFKnight 0:9b3d4731edbb 578 ( ADI_SPI1_CFG_RX_FLUSH > 1u ) || \
WFKnight 0:9b3d4731edbb 579 ( ADI_SPI2_CFG_RX_FLUSH > 1u )
WFKnight 0:9b3d4731edbb 580 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 581 #endif
WFKnight 0:9b3d4731edbb 582
WFKnight 0:9b3d4731edbb 583 #if ( ADI_SPI0_CFG_TX_FLUSH > 1u ) || \
WFKnight 0:9b3d4731edbb 584 ( ADI_SPI1_CFG_TX_FLUSH > 1u ) || \
WFKnight 0:9b3d4731edbb 585 ( ADI_SPI2_CFG_TX_FLUSH > 1u )
WFKnight 0:9b3d4731edbb 586 #error "Invalid configuration"
WFKnight 0:9b3d4731edbb 587 #endif
WFKnight 0:9b3d4731edbb 588
WFKnight 0:9b3d4731edbb 589
WFKnight 0:9b3d4731edbb 590 /*! @} */
WFKnight 0:9b3d4731edbb 591
WFKnight 0:9b3d4731edbb 592 #endif /* ADI_SPI_CONFIG_H__ */