Vybhav Kadaba
/
EV-PRO-MW1001_test1
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Revision 32:52445bef314d, committed 2019-10-25
- Comitter:
- Vkadaba
- Date:
- Fri Oct 25 05:08:19 2019 +0000
- Parent:
- 31:8ab5d9a29a9f
- Child:
- 33:df7a00f1b8e1
- Commit message:
- Register map updated.; Files changed:; 1. ADMW1001_REGISTERS.h; 2.ADMW1001_REGISTERS_typedefs.h; 3.admw_api.h; ; Changes are done to support the new register map. ; Files changed:; 1.utils.c; 2.admw1001.c; ; admw_spi.cpp file is changed to test DRDY issue ;
Changed in this revision
--- a/common/utils.c Wed Oct 23 16:18:50 2019 +0000
+++ b/common/utils.c Fri Oct 25 05:08:19 2019 +0000
@@ -101,32 +101,20 @@
ADMW_LOG_INFO("\t\t\tLast Alert Code: %u (0x%X)",
pStatus->channelAlertCodes[i],
pStatus->channelAlertCodes[i]);
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_TIMEOUT)
- ADMW_LOG_INFO("\t\t\tTimeout alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_UNDER_RANGE)
- ADMW_LOG_INFO("\t\t\tUnder Range alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_OVER_RANGE)
- ADMW_LOG_INFO("\t\t\tOver Range alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_LOW_LIMIT)
- ADMW_LOG_INFO("\t\t\tLow limit alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_HIGH_LIMIT)
- ADMW_LOG_INFO("\t\t\tHigh Limit alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_SENSOR_OPEN)
- ADMW_LOG_INFO("\t\t\tSensor Fault alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_REF_DETECT)
- ADMW_LOG_INFO("\t\t\tReference Detection alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_CONFIG_ERR)
- ADMW_LOG_INFO("\t\t\tConfiguration Error alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_LUT_ERR)
- ADMW_LOG_INFO("\t\t\tLook-Up Table Error alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_SENSOR_NOT_READY)
- ADMW_LOG_INFO("\t\t\tSensor Not Ready alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_COMP_NOT_READY)
- ADMW_LOG_INFO("\t\t\tCompensation Channel Not Ready alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_LUT_UNDER_RANGE)
- ADMW_LOG_INFO("\t\t\tUnder Look-Up Table Range alert detected");
- if (pStatus->channelAlerts[i] & ADMW_CHANNEL_ALERT_LUT_OVER_RANGE)
- ADMW_LOG_INFO("\t\t\tOver Look-Up Table Range alert detected");
+ if (pStatus->channelAlerts[i] & ADMW_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE)
+ ADMW_LOG_INFO("\t\t\ADC near overrange detected");
+ if (pStatus->channelAlerts[i] & ADMW_ALERT_DETAIL_CH_SENSOR_UNDERRANGE)
+ ADMW_LOG_INFO("\t\t\tSensor underrange detected");
+ if (pStatus->channelAlerts[i] & ADMW_ALERT_DETAIL_CH_SENSOR_OVERRANGE)
+ ADMW_LOG_INFO("\t\t\tSensor overrange detected");
+ if (pStatus->channelAlerts[i] & ADMW_ALERT_DETAIL_CH_CJ_SOFT_FAULT)
+ ADMW_LOG_INFO("\t\t\tCJC soft fault alert detected");
+ if (pStatus->channelAlerts[i] & ADMW_ALERT_DETAIL_CH_CJ_HARD_FAULT)
+ ADMW_LOG_INFO("\t\t\tCJC hard fault alert detected");
+ if (pStatus->channelAlerts[i] & ADMW_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE)
+ ADMW_LOG_INFO("\t\t\tADC input overranage alert detected");
+ if (pStatus->channelAlerts[i] & ADMW_ALERT_DETAIL_CH_SENSOR_HARDFAULT)
+ ADMW_LOG_INFO("\t\t\tChannel sensor hardfault alert detected");
}
}
--- a/i2c0_sensirionSHT3X_config.c Wed Oct 23 16:18:50 2019 +0000
+++ b/i2c0_sensirionSHT3X_config.c Fri Oct 25 05:08:19 2019 +0000
@@ -70,7 +70,6 @@
.extraSettlingTime = 99500.0014663674,
.i2cChannelConfig = {
.sensor = ADMW1001_I2C_SENSOR_HUMIDITY_B,
- .dataFormat.coding = ADMW1001_DIGITAL_SENSOR_DATA_CODING_UNIPOLAR,
},
}
},
--- a/inc/admw1001/ADMW1001_REGISTERS.h Wed Oct 23 16:18:50 2019 +0000
+++ b/inc/admw1001/ADMW1001_REGISTERS.h Fri Oct 25 05:08:19 2019 +0000
@@ -1,16 +1,24 @@
/* ================================================================================
+
+ Created by :
+ Created on : 2019 Oct 08, 09:43 GMT Daylight Time
Project : ADMW1001_REGISTERS
File : ADMW1001_REGISTERS.h
Description : Register Definitions
- Date : Jun 19, 2019
+ !! ADI Confidential !!
+ INTERNAL USE ONLY
Copyright (c) 2019 Analog Devices, Inc. All Rights Reserved.
This software is proprietary and confidential to Analog Devices, Inc. and
its licensors.
This file was auto-generated. Do not make local changes to this file.
+
+ Auto generation script information:
+ Script: C:\Program Files (x86)\Yoda-19.05.01\generators\inc\genHeaders
+ Last modified: 26-SEP-2017
================================================================================ */
@@ -36,12 +44,12 @@
/* ============================================================================================================================
SPI
============================================================================================================================ */
+#define MOD_SPI_BASE 0x00000000 /* */
+#define MOD_SPI_MASK 0x00007FFF /* */
#define REG_SPI_INTERFACE_CONFIG_A_RESET 0x00000030 /* Reset Value for Interface_Config_A */
#define REG_SPI_INTERFACE_CONFIG_A 0x00000000 /* SPI Interface Configuration A */
#define REG_SPI_INTERFACE_CONFIG_B_RESET 0x00000000 /* Reset Value for Interface_Config_B */
#define REG_SPI_INTERFACE_CONFIG_B 0x00000001 /* SPI Interface Configuration B */
-#define REG_SPI_DEVICE_CONFIG_RESET 0x00000000 /* Reset Value for Device_Config */
-#define REG_SPI_DEVICE_CONFIG 0x00000002 /* SPI Device Configuration */
#define REG_SPI_CHIP_TYPE_RESET 0x00000007 /* Reset Value for Chip_Type */
#define REG_SPI_CHIP_TYPE 0x00000003 /* SPI Chip Type */
#define REG_SPI_PRODUCT_ID_L_RESET 0x00000020 /* Reset Value for Product_ID_L */
@@ -73,14 +81,14 @@
/* -------------------------------------------------------------------------------------------------------------------------
SPI_INTERFACE_CONFIG_A Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESET 7 /* First of Two of SW_RESET Bits. */
+#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESET 7 /* First of Two of the SW_RESET Bits. */
#define BITP_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 5 /* Determines Sequential Addressing Behavior */
-#define BITP_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 /* SDO Pin Enable */
-#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 /* Second of Two of SW_RESET Bits. */
-#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 /* First of Two of SW_RESET Bits. */
+#define BITP_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 4 /* Serial Data Output Pin Enable */
+#define BITP_SPI_INTERFACE_CONFIG_A_SW_RESETX 0 /* Second of Two of the SW_RESET Bits. */
+#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESET 0x00000080 /* First of Two of the SW_RESET Bits. */
#define BITM_SPI_INTERFACE_CONFIG_A_ADDR_ASCENSION 0x00000020 /* Determines Sequential Addressing Behavior */
-#define BITM_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 /* SDO Pin Enable */
-#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 /* Second of Two of SW_RESET Bits. */
+#define BITM_SPI_INTERFACE_CONFIG_A_SDO_ENABLE 0x00000010 /* Serial Data Output Pin Enable */
+#define BITM_SPI_INTERFACE_CONFIG_A_SW_RESETX 0x00000001 /* Second of Two of the SW_RESET Bits. */
#define ENUM_SPI_INTERFACE_CONFIG_A_DESCEND 0x00000000 /* Addr_Ascension: Address accessed is decremented by one for each data byte when streaming */
#define ENUM_SPI_INTERFACE_CONFIG_A_ASCEND 0x00000020 /* Addr_Ascension: Address accessed is incremented by one for each data byte when streaming */
@@ -93,14 +101,6 @@
#define ENUM_SPI_INTERFACE_CONFIG_B_SINGLE_INSTRUCTION_MODE 0x00000080 /* Single_Inst: Single Instruction mode is enabled */
/* -------------------------------------------------------------------------------------------------------------------------
- SPI_DEVICE_CONFIG Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_DEVICE_CONFIG_OPERATING_MODES 0 /* Power Modes */
-#define BITM_SPI_DEVICE_CONFIG_OPERATING_MODES 0x00000003 /* Power Modes */
-#define ENUM_SPI_DEVICE_CONFIG_NORMAL 0x00000000 /* Operating_Modes: Normal Operating Mode */
-#define ENUM_SPI_DEVICE_CONFIG_SLEEP 0x00000003 /* Operating_Modes: Low Power Mode */
-
-/* -------------------------------------------------------------------------------------------------------------------------
SPI_CHIP_TYPE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_CHIP_TYPE_CHIP_TYPE 0 /* Precision ADC */
@@ -109,22 +109,24 @@
/* -------------------------------------------------------------------------------------------------------------------------
SPI_PRODUCT_ID_L Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID 0 /* This is Device Chip Type/Family */
-#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID 0x000000FF /* This is Device Chip Type/Family */
+#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 4 /* These Bits are Fixed on Die Configured for Multiple Generics */
+#define BITP_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0 /* These Bits Vary on Die Configured for Multiple Generics */
+#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_FIXED_BITS 0x000000F0 /* These Bits are Fixed on Die Configured for Multiple Generics */
+#define BITM_SPI_PRODUCT_ID_L_PRODUCT_ID_TRIM_BITS 0x0000000F /* These Bits Vary on Die Configured for Multiple Generics */
/* -------------------------------------------------------------------------------------------------------------------------
SPI_PRODUCT_ID_H Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID 0 /* This is Device Chip Type/Family */
-#define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID 0x000000FF /* This is Device Chip Type/Family */
+#define BITP_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0 /* These Bits are Fixed on Die Configured for Multiple Generics */
+#define BITM_SPI_PRODUCT_ID_H_PRODUCT_ID_FIXED_BITS 0x000000FF /* These Bits are Fixed on Die Configured for Multiple Generics */
/* -------------------------------------------------------------------------------------------------------------------------
SPI_CHIP_GRADE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_CHIP_GRADE_GRADE 4 /* This is the Device Performance Grade */
-#define BITP_SPI_CHIP_GRADE_DEVICE_REVISION 0 /* This is the Device Hardware Revision */
-#define BITM_SPI_CHIP_GRADE_GRADE 0x000000F0 /* This is the Device Performance Grade */
-#define BITM_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F /* This is the Device Hardware Revision */
+#define BITP_SPI_CHIP_GRADE_GRADE 4 /* Device Performance Grade */
+#define BITP_SPI_CHIP_GRADE_DEVICE_REVISION 0 /* Device Hardware Revision */
+#define BITM_SPI_CHIP_GRADE_GRADE 0x000000F0 /* Device Performance Grade */
+#define BITM_SPI_CHIP_GRADE_DEVICE_REVISION 0x0000000F /* Device Hardware Revision */
/* -------------------------------------------------------------------------------------------------------------------------
SPI_SCRATCH_PAD Pos/Masks Description
@@ -139,8 +141,8 @@
#define BITP_SPI_SPI_REVISION_VERSION 0 /* SPI Version */
#define BITM_SPI_SPI_REVISION_SPI_TYPE 0x000000C0 /* Always Reads as 0x2 */
#define BITM_SPI_SPI_REVISION_VERSION 0x0000003F /* SPI Version */
-#define ENUM_SPI_SPI_REVISION_ADI_SPI 0x00000000
-#define ENUM_SPI_SPI_REVISION_LPT_SPI 0x00000080
+#define ENUM_SPI_SPI_REVISION_ADI_SPI 0x00000000 /* SPI_Type: ADI_SPI */
+#define ENUM_SPI_SPI_REVISION_LPT_SPI 0x00000080 /* SPI_Type: LPT_SPI */
#define ENUM_SPI_SPI_REVISION_REV1_0 0x00000002 /* Version: Revision 1.0 */
/* -------------------------------------------------------------------------------------------------------------------------
@@ -158,14 +160,14 @@
/* -------------------------------------------------------------------------------------------------------------------------
SPI_STREAM_MODE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_STREAM_MODE_LOOP_COUNT 0 /* Sets the Data Byte Count Before Looping to Start Address */
-#define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF /* Sets the Data Byte Count Before Looping to Start Address */
+#define BITP_SPI_STREAM_MODE_LOOP_COUNT 0 /* Set the Data Byte Count Before Looping to Start Address */
+#define BITM_SPI_STREAM_MODE_LOOP_COUNT 0x000000FF /* Set the Data Byte Count Before Looping to Start Address */
/* -------------------------------------------------------------------------------------------------------------------------
SPI_TRANSFER_CONFIG Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_SPI_TRANSFER_CONFIG_STREAM_MODE 1 /* When Streaming, Controls Master-Slave Transfer */
-#define BITM_SPI_TRANSFER_CONFIG_STREAM_MODE 0x00000002 /* When Streaming, Controls Master-Slave Transfer */
+#define BITP_SPI_TRANSFER_CONFIG_STREAM_MODE 1 /* When Streaming, Control Master to Slave Transfer */
+#define BITM_SPI_TRANSFER_CONFIG_STREAM_MODE 0x00000002 /* When Streaming, Control Master to Slave Transfer */
#define ENUM_SPI_TRANSFER_CONFIG_UPDATE_ON_WRITE 0x00000000 /* Stream_Mode: Transfers after each byte/mulit-byte register */
#define ENUM_SPI_TRANSFER_CONFIG_UPDATE_ON_ADDRESS_LOOP 0x00000002 /* Stream_Mode: Transfers when address loops */
@@ -173,12 +175,12 @@
SPI_INTERFACE_CONFIG_C Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 6 /* CRC Enable */
-#define BITP_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 5 /* Multi-byte Registers Must Be Read/Written in Full */
-#define BITP_SPI_INTERFACE_CONFIG_C_SEND_STATUS 4 /* Enables Sending of Status in 4-wire Mode */
+#define BITP_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 5 /* Multibyte Registers Must Be Read or Written in Full */
+#define BITP_SPI_INTERFACE_CONFIG_C_SEND_STATUS 4 /* Sends Status in 4-Wire Mode When Enabled */
#define BITP_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0 /* Inverted CRC Enable */
#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLE 0x000000C0 /* CRC Enable */
-#define BITM_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 0x00000020 /* Multi-byte Registers Must Be Read/Written in Full */
-#define BITM_SPI_INTERFACE_CONFIG_C_SEND_STATUS 0x00000010 /* Enables Sending of Status in 4-wire Mode */
+#define BITM_SPI_INTERFACE_CONFIG_C_STRICT_REGISTER_ACCESS 0x00000020 /* Multibyte Registers Must Be Read or Written in Full */
+#define BITM_SPI_INTERFACE_CONFIG_C_SEND_STATUS 0x00000010 /* Sends Status in 4-Wire Mode When Enabled */
#define BITM_SPI_INTERFACE_CONFIG_C_CRC_ENABLEB 0x00000003 /* Inverted CRC Enable */
#define ENUM_SPI_INTERFACE_CONFIG_C_DISABLED 0x00000000 /* CRC_Enable: CRC Disabled */
#define ENUM_SPI_INTERFACE_CONFIG_C_ENABLED 0x00000040 /* CRC_Enable: CRC Enabled */
@@ -191,40 +193,40 @@
#define BITP_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 7 /* Device Not Ready for Transaction */
#define BITP_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 4 /* Incorrect Number of Clocks Detected in a Transaction */
#define BITP_SPI_INTERFACE_STATUS_A_CRC_ERROR 3 /* Invalid/No CRC Received */
-#define BITP_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 /* Write to Read-Only Register Attempted */
+#define BITP_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 2 /* Write to Read Only Register Attempted */
#define BITP_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 1 /* Set When Fewer Than Expected Number of Bytes Read/Written */
-#define BITP_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 /* Attempt to Read/Write Non-existent Register Address */
+#define BITP_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0 /* Attempt to Read/Write Nonexistent Register Address */
#define BITM_SPI_INTERFACE_STATUS_A_NOT_READY_ERROR 0x00000080 /* Device Not Ready for Transaction */
#define BITM_SPI_INTERFACE_STATUS_A_CLOCK_COUNT_ERROR 0x00000010 /* Incorrect Number of Clocks Detected in a Transaction */
#define BITM_SPI_INTERFACE_STATUS_A_CRC_ERROR 0x00000008 /* Invalid/No CRC Received */
-#define BITM_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 /* Write to Read-Only Register Attempted */
+#define BITM_SPI_INTERFACE_STATUS_A_WR_TO_RD_ONLY_REG_ERROR 0x00000004 /* Write to Read Only Register Attempted */
#define BITM_SPI_INTERFACE_STATUS_A_REGISTER_PARTIAL_ACCESS_ERROR 0x00000002 /* Set When Fewer Than Expected Number of Bytes Read/Written */
-#define BITM_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 /* Attempt to Read/Write Non-existent Register Address */
+#define BITM_SPI_INTERFACE_STATUS_A_ADDRESS_INVALID_ERROR 0x00000001 /* Attempt to Read/Write Nonexistent Register Address */
/* ============================================================================================================================
- ADMW1001 Core Registers
+ ADISENSE1000 Core Registers
============================================================================================================================ */
/* ============================================================================================================================
CORE
============================================================================================================================ */
+#define MOD_CORE_BASE 0x00000010 /* ADISENSE1000 Core Registers */
+#define MOD_CORE_MASK 0x00007FFF /* ADISENSE1000 Core Registers */
#define REG_CORE_COMMAND_RESET 0x00000000 /* Reset Value for Command */
-#define REG_CORE_COMMAND 0x00000014 /* CORE Special Command */
+#define REG_CORE_COMMAND 0x00000014 /* CORE Special Command Register */
#define REG_CORE_MODE_RESET 0x00000000 /* Reset Value for Mode */
#define REG_CORE_MODE 0x00000016 /* CORE Operating Mode and DRDY Control */
#define REG_CORE_POWER_CONFIG_RESET 0x00000000 /* Reset Value for Power_Config */
-#define REG_CORE_POWER_CONFIG 0x00000017 /* CORE General Configuration */
+#define REG_CORE_POWER_CONFIG 0x00000017 /* CORE Power Configuration */
#define REG_CORE_CYCLE_CONTROL_RESET 0x00000000 /* Reset Value for Cycle_Control */
#define REG_CORE_CYCLE_CONTROL 0x00000018 /* CORE Measurement Cycle */
+#define REG_CORE_FIFO_NUM_CYCLES_RESET 0x00000001 /* Reset Value for Fifo_Num_Cycles */
+#define REG_CORE_FIFO_NUM_CYCLES 0x0000001A /* CORE Number of Measurement Cycles to Store in FIFO */
#define REG_CORE_STATUS_RESET 0x00000000 /* Reset Value for Status */
#define REG_CORE_STATUS 0x00000020 /* CORE General Status */
-#define REG_CORE_DIAGNOSTICS_STATUS_RESET 0x00000000 /* Reset Value for Diagnostics_Status */
-#define REG_CORE_DIAGNOSTICS_STATUS 0x00000024 /* CORE Diagnostics Status */
#define REG_CORE_CHANNEL_ALERT_STATUS_RESET 0x00000000 /* Reset Value for Channel_Alert_Status */
#define REG_CORE_CHANNEL_ALERT_STATUS 0x00000026 /* CORE Alert Status Summary */
-#define REG_CORE_ALERT_STATUS_2_RESET 0x00000000 /* Reset Value for Alert_Status_2 */
-#define REG_CORE_ALERT_STATUS_2 0x00000028 /* CORE Additional Alert Status Information */
#define REG_CORE_ALERT_DETAIL_CHn_RESET 0x00000000 /* Reset Value for Alert_Detail_Ch[n] */
#define REG_CORE_ALERT_DETAIL_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH0 */
#define REG_CORE_ALERT_DETAIL_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH1 */
@@ -239,44 +241,40 @@
#define REG_CORE_ALERT_DETAIL_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH10 */
#define REG_CORE_ALERT_DETAIL_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH11 */
#define REG_CORE_ALERT_DETAIL_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_DETAIL_CH12 */
-#define REG_CORE_ALERT_DETAIL_CH0 0x0000002A /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH1 0x0000002C /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH2 0x0000002E /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH3 0x00000030 /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH4 0x00000032 /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH5 0x00000034 /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH6 0x00000036 /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH7 0x00000038 /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH8 0x0000003A /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH9 0x0000003C /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH10 0x0000003E /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH11 0x00000040 /* CORE Detailed Error Information */
-#define REG_CORE_ALERT_DETAIL_CH12 0x00000042 /* CORE Detailed Error Information */
+#define REG_CORE_ALERT_DETAIL_CH0 0x0000002A /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH1 0x0000002C /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH2 0x0000002E /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH3 0x00000030 /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH4 0x00000032 /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH5 0x00000034 /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH6 0x00000036 /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH7 0x00000038 /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH8 0x0000003A /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH9 0x0000003C /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH10 0x0000003E /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH11 0x00000040 /* CORE Detailed Channel Error Information */
+#define REG_CORE_ALERT_DETAIL_CH12 0x00000042 /* CORE Detailed Channel Error Information */
#define REG_CORE_ALERT_DETAIL_CHn(i) (REG_CORE_ALERT_DETAIL_CH0 + ((i) * 2))
#define REG_CORE_ALERT_DETAIL_CHn_COUNT 13
#define REG_CORE_ERROR_CODE_RESET 0x00000000 /* Reset Value for Error_Code */
#define REG_CORE_ERROR_CODE 0x0000004C /* CORE Code Indicating Source of Error */
-#define REG_CORE_ALERT_CODE_RESET 0x00000000 /* Reset Value for Alert_Code */
-#define REG_CORE_ALERT_CODE 0x0000004E /* CORE Code Indicating Source of Alert */
-#define REG_CORE_EXTERNAL_REFERENCE_RESISTOR_RESET 0x00000000 /* Reset Value for External_Reference_Resistor */
-#define REG_CORE_EXTERNAL_REFERENCE_RESISTOR 0x00000050 /* CORE External Reference Information */
-#define REG_CORE_EXTERNAL_VOLTAGE_REFERENCE_RESET 0x00000000 /* Reset Value for External_Voltage_Reference */
-#define REG_CORE_EXTERNAL_VOLTAGE_REFERENCE 0x00000054 /* CORE External Reference Information */
+#define REG_CORE_EXTERNAL_REFERENCE_RESISTOR_RESET 0x447A0000 /* Reset Value for External_Reference_Resistor */
+#define REG_CORE_EXTERNAL_REFERENCE_RESISTOR 0x00000050 /* CORE External Reference Resistor Value */
#define REG_CORE_DIAGNOSTICS_CONTROL_RESET 0x00000000 /* Reset Value for Diagnostics_Control */
#define REG_CORE_DIAGNOSTICS_CONTROL 0x0000005C /* CORE Diagnostic Control */
#define REG_CORE_DATA_FIFO_RESET 0x00000000 /* Reset Value for Data_FIFO */
#define REG_CORE_DATA_FIFO 0x00000060 /* CORE FIFO Buffer of Sensor Results */
#define REG_CORE_DEBUG_CODE_RESET 0x00000000 /* Reset Value for Debug_Code */
#define REG_CORE_DEBUG_CODE 0x00000064 /* CORE Additional Information on Source of Alert or Errors */
-#define REG_CORE_ADVANCED_SENSOR_ACCESS_RESET 0x00000000 /* Reset Value for Advanced_Sensor_Access */
-#define REG_CORE_ADVANCED_SENSOR_ACCESS 0x0000006E /* CORE Enables Access to Advanced Sensor Configuration */
+#define REG_CORE_TEST_REG_ACCESS_RESET 0x00000000 /* Reset Value for Test_Reg_Access */
+#define REG_CORE_TEST_REG_ACCESS 0x0000006C /* CORE Allows Access to Test (Hidden) Registers and Features */
#define REG_CORE_LUT_SELECT_RESET 0x00000000 /* Reset Value for LUT_Select */
-#define REG_CORE_LUT_SELECT 0x00000070 /* CORE Read/Write Strobe */
+#define REG_CORE_LUT_SELECT 0x00000070 /* CORE LUT Read/Write Strobe */
#define REG_CORE_LUT_OFFSET_RESET 0x00000000 /* Reset Value for LUT_Offset */
#define REG_CORE_LUT_OFFSET 0x00000072 /* CORE Offset into Selected LUT */
#define REG_CORE_LUT_DATA_RESET 0x00000000 /* Reset Value for LUT_Data */
#define REG_CORE_LUT_DATA 0x00000074 /* CORE Data to Read/Write from Addressed LUT Entry */
-#define REG_CORE_REVISION_RESET 0x00000000 /* Reset Value for Revision */
+#define REG_CORE_REVISION_RESET 0x01000000 /* Reset Value for Revision */
#define REG_CORE_REVISION 0x0000008C /* CORE Hardware, Firmware Revision */
#define REG_CORE_CHANNEL_COUNTn_RESET 0x00000000 /* Reset Value for Channel_Count[n] */
#define REG_CORE_CHANNEL_COUNT0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_COUNT0 */
@@ -321,19 +319,19 @@
#define REG_CORE_CHANNEL_OPTIONS10_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS10 */
#define REG_CORE_CHANNEL_OPTIONS11_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS11 */
#define REG_CORE_CHANNEL_OPTIONS12_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_OPTIONS12 */
-#define REG_CORE_CHANNEL_OPTIONS0 0x00000091 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS1 0x000000D1 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS2 0x00000111 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS3 0x00000151 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS4 0x00000191 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS5 0x000001D1 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS6 0x00000211 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS7 0x00000251 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS8 0x00000291 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS9 0x000002D1 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS10 0x00000311 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS11 0x00000351 /* CORE Position of Channel Within Sequence and Enable for FFT */
-#define REG_CORE_CHANNEL_OPTIONS12 0x00000391 /* CORE Position of Channel Within Sequence and Enable for FFT */
+#define REG_CORE_CHANNEL_OPTIONS0 0x00000091 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS1 0x000000D1 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS2 0x00000111 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS3 0x00000151 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS4 0x00000191 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS5 0x000001D1 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS6 0x00000211 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS7 0x00000251 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS8 0x00000291 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS9 0x000002D1 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS10 0x00000311 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS11 0x00000351 /* CORE Position of Channel Within Sequence */
+#define REG_CORE_CHANNEL_OPTIONS12 0x00000391 /* CORE Position of Channel Within Sequence */
#define REG_CORE_CHANNEL_OPTIONSn(i) (REG_CORE_CHANNEL_OPTIONS0 + ((i) * 64))
#define REG_CORE_CHANNEL_OPTIONSn_COUNT 13
#define REG_CORE_SENSOR_TYPEn_RESET 0x00000000 /* Reset Value for Sensor_Type[n] */
@@ -466,35 +464,35 @@
#define REG_CORE_MEASUREMENT_SETUP10_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP10 */
#define REG_CORE_MEASUREMENT_SETUP11_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP11 */
#define REG_CORE_MEASUREMENT_SETUP12_RESET 0x00000000 /* Reset Value for REG_CORE_MEASUREMENT_SETUP12 */
-#define REG_CORE_MEASUREMENT_SETUP0 0x0000009C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP1 0x000000DC /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP2 0x0000011C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP3 0x0000015C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP4 0x0000019C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP5 0x000001DC /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP6 0x0000021C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP7 0x0000025C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP8 0x0000029C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP9 0x000002DC /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP10 0x0000031C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP11 0x0000035C /* CORE ADC Digital Filter Selection */
-#define REG_CORE_MEASUREMENT_SETUP12 0x0000039C /* CORE ADC Digital Filter Selection */
+#define REG_CORE_MEASUREMENT_SETUP0 0x0000009C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP1 0x000000DC /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP2 0x0000011C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP3 0x0000015C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP4 0x0000019C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP5 0x000001DC /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP6 0x0000021C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP7 0x0000025C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP8 0x0000029C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP9 0x000002DC /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP10 0x0000031C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP11 0x0000035C /* CORE ADC Measurement Setup */
+#define REG_CORE_MEASUREMENT_SETUP12 0x0000039C /* CORE ADC Measurement Setup */
#define REG_CORE_MEASUREMENT_SETUPn(i) (REG_CORE_MEASUREMENT_SETUP0 + ((i) * 64))
#define REG_CORE_MEASUREMENT_SETUPn_COUNT 13
-#define REG_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x00000000 /* Reset Value for High_Threshold_Limit[n] */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT0 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT1 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT2 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT3 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT4 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT5 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT6 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT7 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT8 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT9 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT10 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT11 */
-#define REG_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x00000000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT12 */
+#define REG_CORE_HIGH_THRESHOLD_LIMITn_RESET 0x7F800000 /* Reset Value for High_Threshold_Limit[n] */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT0_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT0 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT1_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT1 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT2_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT2 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT3_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT3 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT4_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT4 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT5_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT5 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT6_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT6 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT7_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT7 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT8_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT8 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT9_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT9 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT10_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT10 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT11_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT11 */
+#define REG_CORE_HIGH_THRESHOLD_LIMIT12_RESET 0x7F800000 /* Reset Value for REG_CORE_HIGH_THRESHOLD_LIMIT12 */
#define REG_CORE_HIGH_THRESHOLD_LIMIT0 0x000000A0 /* CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT1 0x000000E0 /* CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMIT2 0x00000120 /* CORE High Threshold */
@@ -510,20 +508,20 @@
#define REG_CORE_HIGH_THRESHOLD_LIMIT12 0x000003A0 /* CORE High Threshold */
#define REG_CORE_HIGH_THRESHOLD_LIMITn(i) (REG_CORE_HIGH_THRESHOLD_LIMIT0 + ((i) * 64))
#define REG_CORE_HIGH_THRESHOLD_LIMITn_COUNT 13
-#define REG_CORE_LOW_THRESHOLD_LIMITn_RESET 0x00000000 /* Reset Value for Low_Threshold_Limit[n] */
-#define REG_CORE_LOW_THRESHOLD_LIMIT0_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT0 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT1_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT1 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT2_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT2 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT3_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT3 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT4_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT4 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT5_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT5 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT6_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT6 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT7_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT7 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT8_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT8 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT9_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT9 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT10_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT10 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT11_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT11 */
-#define REG_CORE_LOW_THRESHOLD_LIMIT12_RESET 0x00000000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT12 */
+#define REG_CORE_LOW_THRESHOLD_LIMITn_RESET 0xFF800000 /* Reset Value for Low_Threshold_Limit[n] */
+#define REG_CORE_LOW_THRESHOLD_LIMIT0_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT0 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT1_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT1 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT2_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT2 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT3_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT3 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT4_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT4 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT5_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT5 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT6_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT6 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT7_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT7 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT8_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT8 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT9_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT9 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT10_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT10 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT11_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT11 */
+#define REG_CORE_LOW_THRESHOLD_LIMIT12_RESET 0xFF800000 /* Reset Value for REG_CORE_LOW_THRESHOLD_LIMIT12 */
#define REG_CORE_LOW_THRESHOLD_LIMIT0 0x000000A4 /* CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT1 0x000000E4 /* CORE Low Threshold */
#define REG_CORE_LOW_THRESHOLD_LIMIT2 0x00000124 /* CORE Low Threshold */
@@ -568,20 +566,20 @@
#define REG_CORE_SENSOR_OFFSET12 0x000003A8 /* CORE Sensor Offset Adjustment */
#define REG_CORE_SENSOR_OFFSETn(i) (REG_CORE_SENSOR_OFFSET0 + ((i) * 64))
#define REG_CORE_SENSOR_OFFSETn_COUNT 13
-#define REG_CORE_SENSOR_GAINn_RESET 0x00000000 /* Reset Value for Sensor_Gain[n] */
-#define REG_CORE_SENSOR_GAIN0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN0 */
-#define REG_CORE_SENSOR_GAIN1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN1 */
-#define REG_CORE_SENSOR_GAIN2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN2 */
-#define REG_CORE_SENSOR_GAIN3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN3 */
-#define REG_CORE_SENSOR_GAIN4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN4 */
-#define REG_CORE_SENSOR_GAIN5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN5 */
-#define REG_CORE_SENSOR_GAIN6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN6 */
-#define REG_CORE_SENSOR_GAIN7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN7 */
-#define REG_CORE_SENSOR_GAIN8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN8 */
-#define REG_CORE_SENSOR_GAIN9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN9 */
-#define REG_CORE_SENSOR_GAIN10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN10 */
-#define REG_CORE_SENSOR_GAIN11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN11 */
-#define REG_CORE_SENSOR_GAIN12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_GAIN12 */
+#define REG_CORE_SENSOR_GAINn_RESET 0x3F800000 /* Reset Value for Sensor_Gain[n] */
+#define REG_CORE_SENSOR_GAIN0_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN0 */
+#define REG_CORE_SENSOR_GAIN1_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN1 */
+#define REG_CORE_SENSOR_GAIN2_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN2 */
+#define REG_CORE_SENSOR_GAIN3_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN3 */
+#define REG_CORE_SENSOR_GAIN4_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN4 */
+#define REG_CORE_SENSOR_GAIN5_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN5 */
+#define REG_CORE_SENSOR_GAIN6_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN6 */
+#define REG_CORE_SENSOR_GAIN7_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN7 */
+#define REG_CORE_SENSOR_GAIN8_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN8 */
+#define REG_CORE_SENSOR_GAIN9_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN9 */
+#define REG_CORE_SENSOR_GAIN10_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN10 */
+#define REG_CORE_SENSOR_GAIN11_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN11 */
+#define REG_CORE_SENSOR_GAIN12_RESET 0x3F800000 /* Reset Value for REG_CORE_SENSOR_GAIN12 */
#define REG_CORE_SENSOR_GAIN0 0x000000AC /* CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN1 0x000000EC /* CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAIN2 0x0000012C /* CORE Sensor Gain Adjustment */
@@ -597,35 +595,6 @@
#define REG_CORE_SENSOR_GAIN12 0x000003AC /* CORE Sensor Gain Adjustment */
#define REG_CORE_SENSOR_GAINn(i) (REG_CORE_SENSOR_GAIN0 + ((i) * 64))
#define REG_CORE_SENSOR_GAINn_COUNT 13
-#define REG_CORE_ALERT_CODE_CHn_RESET 0x00000000 /* Reset Value for Alert_Code_Ch[n] */
-#define REG_CORE_ALERT_CODE_CH0_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH0 */
-#define REG_CORE_ALERT_CODE_CH1_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH1 */
-#define REG_CORE_ALERT_CODE_CH2_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH2 */
-#define REG_CORE_ALERT_CODE_CH3_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH3 */
-#define REG_CORE_ALERT_CODE_CH4_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH4 */
-#define REG_CORE_ALERT_CODE_CH5_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH5 */
-#define REG_CORE_ALERT_CODE_CH6_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH6 */
-#define REG_CORE_ALERT_CODE_CH7_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH7 */
-#define REG_CORE_ALERT_CODE_CH8_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH8 */
-#define REG_CORE_ALERT_CODE_CH9_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH9 */
-#define REG_CORE_ALERT_CODE_CH10_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH10 */
-#define REG_CORE_ALERT_CODE_CH11_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH11 */
-#define REG_CORE_ALERT_CODE_CH12_RESET 0x00000000 /* Reset Value for REG_CORE_ALERT_CODE_CH12 */
-#define REG_CORE_ALERT_CODE_CH0 0x000000B0 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH1 0x000000F0 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH2 0x00000130 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH3 0x00000170 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH4 0x000001B0 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH5 0x000001F0 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH6 0x00000230 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH7 0x00000270 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH8 0x000002B0 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH9 0x000002F0 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH10 0x00000330 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH11 0x00000370 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CH12 0x000003B0 /* CORE Per-Channel Detailed Alert-Code Information */
-#define REG_CORE_ALERT_CODE_CHn(i) (REG_CORE_ALERT_CODE_CH0 + ((i) * 64))
-#define REG_CORE_ALERT_CODE_CHn_COUNT 13
#define REG_CORE_CHANNEL_SKIPn_RESET 0x00000000 /* Reset Value for Channel_Skip[n] */
#define REG_CORE_CHANNEL_SKIP0_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP0 */
#define REG_CORE_CHANNEL_SKIP1_RESET 0x00000000 /* Reset Value for REG_CORE_CHANNEL_SKIP1 */
@@ -655,64 +624,6 @@
#define REG_CORE_CHANNEL_SKIP12 0x000003B2 /* CORE Indicates If Channel Will Skip Some Measurement Cycles */
#define REG_CORE_CHANNEL_SKIPn(i) (REG_CORE_CHANNEL_SKIP0 + ((i) * 64))
#define REG_CORE_CHANNEL_SKIPn_COUNT 13
-#define REG_CORE_SENSOR_PARAMETERn_RESET 0x00000000 /* Reset Value for Sensor_Parameter[n] */
-#define REG_CORE_SENSOR_PARAMETER0_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER0 */
-#define REG_CORE_SENSOR_PARAMETER1_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER1 */
-#define REG_CORE_SENSOR_PARAMETER2_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER2 */
-#define REG_CORE_SENSOR_PARAMETER3_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER3 */
-#define REG_CORE_SENSOR_PARAMETER4_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER4 */
-#define REG_CORE_SENSOR_PARAMETER5_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER5 */
-#define REG_CORE_SENSOR_PARAMETER6_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER6 */
-#define REG_CORE_SENSOR_PARAMETER7_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER7 */
-#define REG_CORE_SENSOR_PARAMETER8_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER8 */
-#define REG_CORE_SENSOR_PARAMETER9_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER9 */
-#define REG_CORE_SENSOR_PARAMETER10_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER10 */
-#define REG_CORE_SENSOR_PARAMETER11_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER11 */
-#define REG_CORE_SENSOR_PARAMETER12_RESET 0x00000000 /* Reset Value for REG_CORE_SENSOR_PARAMETER12 */
-#define REG_CORE_SENSOR_PARAMETER0 0x000000B4 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER1 0x000000F4 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER2 0x00000134 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER3 0x00000174 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER4 0x000001B4 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER5 0x000001F4 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER6 0x00000234 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER7 0x00000274 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER8 0x000002B4 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER9 0x000002F4 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER10 0x00000334 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER11 0x00000374 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETER12 0x000003B4 /* CORE Sensor Parameter Adjustment */
-#define REG_CORE_SENSOR_PARAMETERn(i) (REG_CORE_SENSOR_PARAMETER0 + ((i) * 64))
-#define REG_CORE_SENSOR_PARAMETERn_COUNT 13
-#define REG_CORE_CALIBRATION_PARAMETERn_RESET 0x00000000 /* Reset Value for Calibration_Parameter[n] */
-#define REG_CORE_CALIBRATION_PARAMETER0_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER0 */
-#define REG_CORE_CALIBRATION_PARAMETER1_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER1 */
-#define REG_CORE_CALIBRATION_PARAMETER2_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER2 */
-#define REG_CORE_CALIBRATION_PARAMETER3_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER3 */
-#define REG_CORE_CALIBRATION_PARAMETER4_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER4 */
-#define REG_CORE_CALIBRATION_PARAMETER5_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER5 */
-#define REG_CORE_CALIBRATION_PARAMETER6_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER6 */
-#define REG_CORE_CALIBRATION_PARAMETER7_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER7 */
-#define REG_CORE_CALIBRATION_PARAMETER8_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER8 */
-#define REG_CORE_CALIBRATION_PARAMETER9_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER9 */
-#define REG_CORE_CALIBRATION_PARAMETER10_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER10 */
-#define REG_CORE_CALIBRATION_PARAMETER11_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER11 */
-#define REG_CORE_CALIBRATION_PARAMETER12_RESET 0x00000000 /* Reset Value for REG_CORE_CALIBRATION_PARAMETER12 */
-#define REG_CORE_CALIBRATION_PARAMETER0 0x000000B8 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER1 0x000000F8 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER2 0x00000138 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER3 0x00000178 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER4 0x000001B8 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER5 0x000001F8 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER6 0x00000238 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER7 0x00000278 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER8 0x000002B8 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER9 0x000002F8 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER10 0x00000338 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER11 0x00000378 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETER12 0x000003B8 /* CORE Calibration Parameter Value */
-#define REG_CORE_CALIBRATION_PARAMETERn(i) (REG_CORE_CALIBRATION_PARAMETER0 + ((i) * 64))
-#define REG_CORE_CALIBRATION_PARAMETERn_COUNT 13
#define REG_CORE_DIGITAL_SENSOR_CONFIGn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Config[n] */
#define REG_CORE_DIGITAL_SENSOR_CONFIG0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG0 */
#define REG_CORE_DIGITAL_SENSOR_CONFIG1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_CONFIG1 */
@@ -771,35 +682,6 @@
#define REG_CORE_DIGITAL_SENSOR_ADDRESS12 0x000003BE /* CORE Sensor Address */
#define REG_CORE_DIGITAL_SENSOR_ADDRESSn(i) (REG_CORE_DIGITAL_SENSOR_ADDRESS0 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_ADDRESSn_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDSn_RESET 0x00000000 /* Reset Value for Digital_Sensor_Num_Cmds[n] */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS0_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS0 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS1_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS1 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS2_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS2 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS3_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS3 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS4_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS4 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS5_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS5 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS6_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS6 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS7_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS7 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS8_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS8 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS9_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS9 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS10 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS11 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_NUM_CMDS12 */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS0 0x000000BF /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS1 0x000000FF /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS2 0x0000013F /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS3 0x0000017F /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS4 0x000001BF /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS5 0x000001FF /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS6 0x0000023F /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS7 0x0000027F /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS8 0x000002BF /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS9 0x000002FF /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS10 0x0000033F /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS11 0x0000037F /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDS12 0x000003BF /* CORE Number of Configuration, Read Commands for Digital Sensors */
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDSn(i) (REG_CORE_DIGITAL_SENSOR_NUM_CMDS0 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_NUM_CMDSn_COUNT 13
#define REG_CORE_DIGITAL_SENSOR_COMMSn_RESET 0x00000006 /* Reset Value for Digital_Sensor_Comms[n] */
#define REG_CORE_DIGITAL_SENSOR_COMMS0_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS0 */
#define REG_CORE_DIGITAL_SENSOR_COMMS1_RESET 0x00000006 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMS1 */
@@ -829,412 +711,6 @@
#define REG_CORE_DIGITAL_SENSOR_COMMS12 0x000003C0 /* CORE Digital Sensor Communication Clock Configuration */
#define REG_CORE_DIGITAL_SENSOR_COMMSn(i) (REG_CORE_DIGITAL_SENSOR_COMMS0 + ((i) * 64))
#define REG_CORE_DIGITAL_SENSOR_COMMSn_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_COMMAND1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command1[n] */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND10 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND11 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND12 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND13 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND14 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND15 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND16_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND16 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND17_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND17 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND18_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND18 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND19_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND19 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND110_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND110 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND111_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND111 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND112_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND112 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND10 0x000000C2 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND11 0x00000102 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND12 0x00000142 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND13 0x00000182 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND14 0x000001C2 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND15 0x00000202 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND16 0x00000242 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND17 0x00000282 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND18 0x000002C2 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND19 0x00000302 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND110 0x00000342 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND111 0x00000382 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND112 0x000003C2 /* CORE Sensor Configuration Command1 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND1n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND10 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_COMMAND1n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_COMMAND2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command2[n] */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND20_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND20 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND21_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND21 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND22_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND22 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND23_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND23 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND24_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND24 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND25_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND25 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND26_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND26 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND27_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND27 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND28_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND28 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND29_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND29 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND210_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND210 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND211_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND211 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND212_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND212 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND20 0x000000C3 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND21 0x00000103 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND22 0x00000143 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND23 0x00000183 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND24 0x000001C3 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND25 0x00000203 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND26 0x00000243 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND27 0x00000283 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND28 0x000002C3 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND29 0x00000303 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND210 0x00000343 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND211 0x00000383 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND212 0x000003C3 /* CORE Sensor Configuration Command2 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND2n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND20 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_COMMAND2n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_COMMAND3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command3[n] */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND30_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND30 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND31_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND31 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND32_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND32 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND33_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND33 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND34_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND34 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND35_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND35 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND36_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND36 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND37_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND37 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND38_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND38 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND39_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND39 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND310_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND310 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND311_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND311 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND312_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND312 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND30 0x000000C4 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND31 0x00000104 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND32 0x00000144 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND33 0x00000184 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND34 0x000001C4 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND35 0x00000204 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND36 0x00000244 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND37 0x00000284 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND38 0x000002C4 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND39 0x00000304 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND310 0x00000344 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND311 0x00000384 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND312 0x000003C4 /* CORE Sensor Configuration Command3 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND3n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND30 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_COMMAND3n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_COMMAND4n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command4[n] */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND40_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND40 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND41_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND41 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND42_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND42 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND43_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND43 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND44_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND44 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND45_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND45 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND46_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND46 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND47_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND47 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND48_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND48 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND49_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND49 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND410_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND410 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND411_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND411 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND412_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND412 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND40 0x000000C5 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND41 0x00000105 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND42 0x00000145 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND43 0x00000185 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND44 0x000001C5 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND45 0x00000205 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND46 0x00000245 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND47 0x00000285 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND48 0x000002C5 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND49 0x00000305 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND410 0x00000345 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND411 0x00000385 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND412 0x000003C5 /* CORE Sensor Configuration Command4 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND4n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND40 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_COMMAND4n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_COMMAND5n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command5[n] */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND50_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND50 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND51_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND51 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND52_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND52 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND53_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND53 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND54_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND54 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND55_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND55 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND56_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND56 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND57_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND57 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND58_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND58 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND59_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND59 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND510_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND510 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND511_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND511 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND512_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND512 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND50 0x000000C6 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND51 0x00000106 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND52 0x00000146 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND53 0x00000186 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND54 0x000001C6 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND55 0x00000206 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND56 0x00000246 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND57 0x00000286 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND58 0x000002C6 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND59 0x00000306 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND510 0x00000346 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND511 0x00000386 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND512 0x000003C6 /* CORE Sensor Configuration Command5 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND5n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND50 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_COMMAND5n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_COMMAND6n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command6[n] */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND60_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND60 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND61_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND61 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND62_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND62 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND63_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND63 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND64_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND64 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND65_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND65 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND66_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND66 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND67_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND67 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND68_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND68 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND69_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND69 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND610_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND610 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND611_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND611 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND612_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND612 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND60 0x000000C7 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND61 0x00000107 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND62 0x00000147 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND63 0x00000187 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND64 0x000001C7 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND65 0x00000207 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND66 0x00000247 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND67 0x00000287 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND68 0x000002C7 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND69 0x00000307 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND610 0x00000347 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND611 0x00000387 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND612 0x000003C7 /* CORE Sensor Configuration Command6 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND6n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND60 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_COMMAND6n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_COMMAND7n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Command7[n] */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND70_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND70 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND71_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND71 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND72_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND72 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND73_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND73 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND74_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND74 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND75_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND75 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND76_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND76 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND77_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND77 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND78_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND78 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND79_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND79 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND710_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND710 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND711_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND711 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND712_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_COMMAND712 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND70 0x000000C8 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND71 0x00000108 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND72 0x00000148 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND73 0x00000188 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND74 0x000001C8 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND75 0x00000208 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND76 0x00000248 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND77 0x00000288 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND78 0x000002C8 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND79 0x00000308 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND710 0x00000348 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND711 0x00000388 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND712 0x000003C8 /* CORE Sensor Configuration Command7 */
-#define REG_CORE_DIGITAL_SENSOR_COMMAND7n(i) (REG_CORE_DIGITAL_SENSOR_COMMAND70 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_COMMAND7n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD1n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd1[n] */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD10_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD10 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD11_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD11 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD12_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD12 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD13_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD13 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD14_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD14 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD15_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD15 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD16_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD16 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD17_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD17 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD18_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD18 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD19_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD19 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD110_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD110 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD111_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD111 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD112_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD112 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD10 0x000000C9 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD11 0x00000109 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD12 0x00000149 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD13 0x00000189 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD14 0x000001C9 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD15 0x00000209 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD16 0x00000249 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD17 0x00000289 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD18 0x000002C9 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD19 0x00000309 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD110 0x00000349 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD111 0x00000389 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD112 0x000003C9 /* CORE Sensor Read Command1 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD1n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD10 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD1n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD2n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd2[n] */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD20_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD20 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD21_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD21 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD22_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD22 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD23_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD23 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD24_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD24 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD25_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD25 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD26_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD26 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD27_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD27 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD28_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD28 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD29_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD29 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD210_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD210 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD211_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD211 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD212_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD212 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD20 0x000000CA /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD21 0x0000010A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD22 0x0000014A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD23 0x0000018A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD24 0x000001CA /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD25 0x0000020A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD26 0x0000024A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD27 0x0000028A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD28 0x000002CA /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD29 0x0000030A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD210 0x0000034A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD211 0x0000038A /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD212 0x000003CA /* CORE Sensor Read Command2 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD2n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD20 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD2n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD3n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd3[n] */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD30_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD30 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD31_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD31 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD32_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD32 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD33_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD33 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD34_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD34 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD35_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD35 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD36_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD36 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD37_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD37 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD38_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD38 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD39_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD39 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD310_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD310 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD311_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD311 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD312_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD312 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD30 0x000000CB /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD31 0x0000010B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD32 0x0000014B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD33 0x0000018B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD34 0x000001CB /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD35 0x0000020B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD36 0x0000024B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD37 0x0000028B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD38 0x000002CB /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD39 0x0000030B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD310 0x0000034B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD311 0x0000038B /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD312 0x000003CB /* CORE Sensor Read Command3 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD3n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD30 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD3n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD4n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd4[n] */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD40_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD40 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD41_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD41 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD42_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD42 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD43_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD43 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD44_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD44 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD45_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD45 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD46_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD46 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD47_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD47 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD48_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD48 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD49_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD49 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD410_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD410 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD411_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD411 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD412_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD412 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD40 0x000000CC /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD41 0x0000010C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD42 0x0000014C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD43 0x0000018C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD44 0x000001CC /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD45 0x0000020C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD46 0x0000024C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD47 0x0000028C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD48 0x000002CC /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD49 0x0000030C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD410 0x0000034C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD411 0x0000038C /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD412 0x000003CC /* CORE Sensor Read Command4 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD4n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD40 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD4n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD5n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd5[n] */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD50_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD50 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD51_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD51 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD52_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD52 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD53_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD53 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD54_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD54 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD55_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD55 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD56_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD56 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD57_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD57 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD58_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD58 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD59_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD59 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD510_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD510 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD511_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD511 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD512_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD512 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD50 0x000000CD /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD51 0x0000010D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD52 0x0000014D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD53 0x0000018D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD54 0x000001CD /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD55 0x0000020D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD56 0x0000024D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD57 0x0000028D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD58 0x000002CD /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD59 0x0000030D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD510 0x0000034D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD511 0x0000038D /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD512 0x000003CD /* CORE Sensor Read Command5 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD5n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD50 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD5n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD6n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd6[n] */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD60_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD60 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD61_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD61 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD62_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD62 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD63_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD63 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD64_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD64 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD65_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD65 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD66_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD66 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD67_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD67 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD68_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD68 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD69_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD69 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD610_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD610 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD611_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD611 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD612_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD612 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD60 0x000000CE /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD61 0x0000010E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD62 0x0000014E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD63 0x0000018E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD64 0x000001CE /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD65 0x0000020E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD66 0x0000024E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD67 0x0000028E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD68 0x000002CE /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD69 0x0000030E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD610 0x0000034E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD611 0x0000038E /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD612 0x000003CE /* CORE Sensor Read Command6 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD6n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD60 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD6n_COUNT 13
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD7n_RESET 0x00000000 /* Reset Value for Digital_Sensor_Read_Cmd7[n] */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD70_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD70 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD71_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD71 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD72_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD72 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD73_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD73 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD74_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD74 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD75_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD75 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD76_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD76 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD77_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD77 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD78_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD78 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD79_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD79 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD710_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD710 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD711_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD711 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD712_RESET 0x00000000 /* Reset Value for REG_CORE_DIGITAL_SENSOR_READ_CMD712 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD70 0x000000CF /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD71 0x0000010F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD72 0x0000014F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD73 0x0000018F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD74 0x000001CF /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD75 0x0000020F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD76 0x0000024F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD77 0x0000028F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD78 0x000002CF /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD79 0x0000030F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD710 0x0000034F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD711 0x0000038F /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD712 0x000003CF /* CORE Sensor Read Command7 */
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD7n(i) (REG_CORE_DIGITAL_SENSOR_READ_CMD70 + ((i) * 64))
-#define REG_CORE_DIGITAL_SENSOR_READ_CMD7n_COUNT 13
/* ============================================================================================================================
CORE Register BitMasks, Positions & Enumerations
@@ -1244,157 +720,125 @@
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_COMMAND_SPECIAL_COMMAND 0 /* Special Command */
#define BITM_CORE_COMMAND_SPECIAL_COMMAND 0x000000FF /* Special Command */
-#define ENUM_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No Command */
-#define ENUM_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC Conversions */
-#define ENUM_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start Conversions with Added RAW ADC Data */
-#define ENUM_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Latch Configuration. */
-#define ENUM_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from FLASH */
-#define ENUM_CORE_COMMAND_SAVE_LUT 0x00000009 /* Special_Command: Save LUT to FLASH */
-#define ENUM_CORE_COMMAND_POWER_DOWN 0x00000014 /* Special_Command: Enter Low Power State */
-#define ENUM_CORE_COMMAND_LOAD_CONFIG_1 0x00000018 /* Special_Command: Load Registers with Configuration#1 from FLASH */
-#define ENUM_CORE_COMMAND_SAVE_CONFIG_1 0x00000019 /* Special_Command: Store Current Registers to FLASH Configuration#1 */
+#define ENUM_CORE_COMMAND_NOP 0x00000000 /* Special_Command: No command */
+#define ENUM_CORE_COMMAND_CONVERT 0x00000001 /* Special_Command: Start ADC conversions */
+#define ENUM_CORE_COMMAND_CONVERT_WITH_RAW 0x00000002 /* Special_Command: Start conversions with added raw ADC data */
+#define ENUM_CORE_COMMAND_LATCH_CONFIG 0x00000007 /* Special_Command: Latch configuration. */
+#define ENUM_CORE_COMMAND_LOAD_LUT 0x00000008 /* Special_Command: Load LUT from flash */
+#define ENUM_CORE_COMMAND_SAVE_LUT 0x00000009 /* Special_Command: Save LUT to flash */
+#define ENUM_CORE_COMMAND_LOAD_CONFIG_1 0x00000018 /* Special_Command: Load registers with configuration from flash */
+#define ENUM_CORE_COMMAND_SAVE_CONFIG_1 0x00000019 /* Special_Command: Store current registers to flash configuration */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_MODE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY with Respect to FIFO State */
+#define BITP_CORE_MODE_DRDY_MODE 2 /* Indicates Behavior of DRDY Pin */
#define BITP_CORE_MODE_CONVERSION_MODE 0 /* Conversion Mode */
-#define BITM_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY with Respect to FIFO State */
+#define BITM_CORE_MODE_DRDY_MODE 0x0000000C /* Indicates Behavior of DRDY Pin */
#define BITM_CORE_MODE_CONVERSION_MODE 0x00000003 /* Conversion Mode */
-#define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data Ready Per Conversion */
-#define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data Ready Per Cycle */
-#define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single Cycle */
-#define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous Conversion */
+#define ENUM_CORE_MODE_DRDY_PER_CONVERSION 0x00000000 /* Drdy_Mode: Data ready per conversion */
+#define ENUM_CORE_MODE_DRDY_PER_CYCLE 0x00000004 /* Drdy_Mode: Data ready per cycle */
+#define ENUM_CORE_MODE_SINGLECYCLE 0x00000000 /* Conversion_Mode: Single cycle conversion mode. A cycle is completed every time a convert command is issued */
+#define ENUM_CORE_MODE_RESERVED 0x00000001 /* Conversion_Mode: Reserved for future use */
+#define ENUM_CORE_MODE_CONTINUOUS 0x00000002 /* Conversion_Mode: Continuous conversion mode. A cycle is started repeatedly at time specified in cycle time */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_POWER_CONFIG Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_POWER_CONFIG_POWER_MODE_MCU 0 /* MCU Power Mode */
#define BITM_CORE_POWER_CONFIG_POWER_MODE_MCU 0x00000001 /* MCU Power Mode */
-#define ENUM_CORE_POWER_CONFIG_ACTIVE_MODE 0x00000000 /* Power_Mode_MCU: Part is fully powered up and either cycling through a sequence or awaiting a configuration */
-#define ENUM_CORE_POWER_CONFIG_HIBERNATION 0x00000001 /* Power_Mode_MCU: module has entede hibernation mode. All analog circuitry is disabled. All peripherals disabled apart from the Wake-up pin functionality. */
+#define ENUM_CORE_POWER_CONFIG_ACTIVE_MODE 0x00000000 /* Power_Mode_MCU: ADMW1001 is fully power up and ready to convert */
+#define ENUM_CORE_POWER_CONFIG_HIBERNATION 0x00000001 /* Power_Mode_MCU: Lowest power mode. wakeup pin required to enter active mode. SPI powered down */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_CYCLE_CONTROL Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 14 /* Units for Cycle Time */
#define BITP_CORE_CYCLE_CONTROL_VBIAS 13 /* Voltage Bias Global Enable */
-#define BITP_CORE_CYCLE_CONTROL_CYCLE_TYPE 12 /* Type of Measurement Cycle */
-#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Duration of a Full Measurement Cycle */
-#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x0000C000 /* Units for Cycle Time */
+#define BITP_CORE_CYCLE_CONTROL_CYCLE_TIME 0 /* Time Between Measurement Cycles */
+#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME_UNITS 0x00004000 /* Units for Cycle Time */
#define BITM_CORE_CYCLE_CONTROL_VBIAS 0x00002000 /* Voltage Bias Global Enable */
-#define BITM_CORE_CYCLE_CONTROL_CYCLE_TYPE 0x00001000 /* Type of Measurement Cycle */
-#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Duration of a Full Measurement Cycle */
-#define ENUM_CORE_CYCLE_CONTROL_MILLISECONDS 0x00000000 /* Cycle_Time_Units: Milli-Seconds */
+#define BITM_CORE_CYCLE_CONTROL_CYCLE_TIME 0x00000FFF /* Time Between Measurement Cycles */
+#define ENUM_CORE_CYCLE_CONTROL_MILLISECONDS 0x00000000 /* Cycle_Time_Units: Milli-seconds */
#define ENUM_CORE_CYCLE_CONTROL_SECONDS 0x00004000 /* Cycle_Time_Units: Seconds */
-#define ENUM_CORE_CYCLE_CONTROL_VBIAS_DISABLE 0x00000000 /* Vbias: Vbias Disabled */
-#define ENUM_CORE_CYCLE_CONTROL_VBIAS_ENABLE 0x00002000 /* Vbias: Enable Vbias Output For the Duration of a Cycle */
-#define ENUM_CORE_CYCLE_CONTROL_SWITCH 0x00000000 /* Cycle_Type: Switch Channels After Every Conversion */
-#define ENUM_CORE_CYCLE_CONTROL_FULL 0x00001000 /* Cycle_Type: Perform Full Number Of Conversions On A Channel Consecutively */
+#define ENUM_CORE_CYCLE_CONTROL_VBIAS_DISABLE 0x00000000 /* Vbias: Vbias disabled */
+#define ENUM_CORE_CYCLE_CONTROL_VBIAS_ENABLE 0x00002000 /* Vbias: Enable Vbias output for the duration of a cycle */
+
+/* -------------------------------------------------------------------------------------------------------------------------
+ CORE_FIFO_NUM_CYCLES Pos/Masks Description
+ ------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0 /* Number of Cycles to Fill the FIFO */
+#define BITM_CORE_FIFO_NUM_CYCLES_FIFO_NUM_CYCLES 0x000000FF /* Number of Cycles to Fill the FIFO */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_STATUS Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
+#define BITP_CORE_STATUS_LUT_ERROR 7 /* Indicates Error with One or More Lookup Tables */
+#define BITP_CORE_STATUS_DIAG_CHECKSUM_ERROR 6 /* Indicates Error on Internal Checksum Calculations */
#define BITP_CORE_STATUS_FIFO_ERROR 5 /* Indicates Error with FIFO */
-#define BITP_CORE_STATUS_CMD_RUNNING 4 /* Indicates a Special Command is Active */
-#define BITP_CORE_STATUS_DRDY 3 /* Indicates a New Sensor Result is Available to Be Read */
+#define BITP_CORE_STATUS_CMD_RUNNING 4 /* Indicates Special Command Active */
+#define BITP_CORE_STATUS_DRDY 3 /* Indicates New Sensor Result Available to Read */
#define BITP_CORE_STATUS_ERROR 2 /* Indicates an Error */
-#define BITP_CORE_STATUS_ALERT_ACTIVE 1 /* Indicates One or More Sensors Alerts are Active */
+#define BITP_CORE_STATUS_ALERT_ACTIVE 1 /* Indicates One or More Sensor Alerts Active */
+#define BITP_CORE_STATUS_CONFIGURATION_ERROR 0 /* Indicates Error with Programmed Configuration */
+#define BITM_CORE_STATUS_LUT_ERROR 0x00000080 /* Indicates Error with One or More Lookup Tables */
+#define BITM_CORE_STATUS_DIAG_CHECKSUM_ERROR 0x00000040 /* Indicates Error on Internal Checksum Calculations */
#define BITM_CORE_STATUS_FIFO_ERROR 0x00000020 /* Indicates Error with FIFO */
-#define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates a Special Command is Active */
-#define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates a New Sensor Result is Available to Be Read */
+#define BITM_CORE_STATUS_CMD_RUNNING 0x00000010 /* Indicates Special Command Active */
+#define BITM_CORE_STATUS_DRDY 0x00000008 /* Indicates New Sensor Result Available to Read */
#define BITM_CORE_STATUS_ERROR 0x00000004 /* Indicates an Error */
-#define BITM_CORE_STATUS_ALERT_ACTIVE 0x00000002 /* Indicates One or More Sensors Alerts are Active */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIAGNOSTICS_STATUS Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_CALIBRATION_ERROR 13 /* Indicates Error During Internal Device Calibrations */
-#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_CONVERSION_ERROR 12 /* Indicates Error During Internal ADC Conversions */
-#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_OV_ERROR 11 /* Indicates Over-Voltage Error on Positive Analog Input */
-#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_UV_ERROR 10 /* Indicates Under-Voltage Error on Positive Analog Input */
-#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_OV_ERROR 9 /* Indicates Over-Voltage Error on Negative Analog Input */
-#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_UV_ERROR 8 /* Indicates Under-Voltage Error on Negative Analog Input */
-#define BITP_CORE_DIAGNOSTICS_STATUS_DIAG_CHECKSUM_ERROR 0 /* Indicates Error on Internal Checksum Calculations */
-#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_CALIBRATION_ERROR 0x00002000 /* Indicates Error During Internal Device Calibrations */
-#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_CONVERSION_ERROR 0x00001000 /* Indicates Error During Internal ADC Conversions */
-#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_OV_ERROR 0x00000800 /* Indicates Over-Voltage Error on Positive Analog Input */
-#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_AINP_UV_ERROR 0x00000400 /* Indicates Under-Voltage Error on Positive Analog Input */
-#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_OV_ERROR 0x00000200 /* Indicates Over-Voltage Error on Negative Analog Input */
-#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_AINM_UV_ERROR 0x00000100 /* Indicates Under-Voltage Error on Negative Analog Input */
-#define BITM_CORE_DIAGNOSTICS_STATUS_DIAG_CHECKSUM_ERROR 0x00000001 /* Indicates Error on Internal Checksum Calculations */
+#define BITM_CORE_STATUS_ALERT_ACTIVE 0x00000002 /* Indicates One or More Sensor Alerts Active */
+#define BITM_CORE_STATUS_CONFIGURATION_ERROR 0x00000001 /* Indicates Error with Programmed Configuration */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_CHANNEL_ALERT_STATUS Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel Alert is Active */
-#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel Alert is Active */
-#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel Alert is Active */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_ALERT_STATUS_2 Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_ALERT_STATUS_2_CONFIGURATION_ERROR 2 /* Indicates Error with Programmed Configuration */
-#define BITP_CORE_ALERT_STATUS_2_LUT_ERROR 1 /* Indicates Error with One or More Look-Up-Tables */
-#define BITM_CORE_ALERT_STATUS_2_CONFIGURATION_ERROR 0x00000004 /* Indicates Error with Programmed Configuration */
-#define BITM_CORE_ALERT_STATUS_2_LUT_ERROR 0x00000002 /* Indicates Error with One or More Look-Up-Tables */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 12 /* Indicates Channel 12 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 11 /* Indicates Channel 11 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 10 /* Indicates Channel 10 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 9 /* Indicates Channel 9 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 8 /* Indicates Channel 8 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 7 /* Indicates Channel 7 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 6 /* Indicates Channel 6 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 5 /* Indicates Channel 5Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 4 /* Indicates Channel 4 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 3 /* Indicates Channel 3 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 2 /* Indicates Channel 2 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 1 /* Indicates Channel 1 Alert Active */
+#define BITP_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0 /* Indicates Channel 0 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH12 0x00001000 /* Indicates Channel 12 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH11 0x00000800 /* Indicates Channel 11 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH10 0x00000400 /* Indicates Channel 10 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH9 0x00000200 /* Indicates Channel 9 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH8 0x00000100 /* Indicates Channel 8 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH7 0x00000080 /* Indicates Channel 7 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH6 0x00000040 /* Indicates Channel 6 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH5 0x00000020 /* Indicates Channel 5Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH4 0x00000010 /* Indicates Channel 4 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH3 0x00000008 /* Indicates Channel 3 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH2 0x00000004 /* Indicates Channel 2 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH1 0x00000002 /* Indicates Channel 1 Alert Active */
+#define BITM_CORE_CHANNEL_ALERT_STATUS_ALERT_CH0 0x00000001 /* Indicates Channel 0 Alert Active */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_ALERT_DETAIL_CH[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_ALERT_DETAIL_CH_COMP_NOT_READY 15 /* Indicates Compensation Channel Not Ready When Required */
-#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_NOT_READY 14 /* Indicates Digital Sensor Not Ready When Read */
-#define BITP_CORE_ALERT_DETAIL_CH_CORRECTION_OVERRANGE 13 /* Indicates Result Larger Than LUT/Equation Range */
-#define BITP_CORE_ALERT_DETAIL_CH_CORRECTION_UNDERRANGE 12 /* Indicates Result Less Than LUT/Equation Range */
-#define BITP_CORE_ALERT_DETAIL_CH_OVER_VOLTAGE 11 /* Indicates Channel Over-Voltage */
-#define BITP_CORE_ALERT_DETAIL_CH_UNDER_VOLTAGE 10 /* Indicates Channel Under-Voltage */
-#define BITP_CORE_ALERT_DETAIL_CH_LUT_ERROR_CH 9 /* Indicates Error with Channel Look-Up-Table */
-#define BITP_CORE_ALERT_DETAIL_CH_CONFIG_ERR 8 /* Indicates Configuration Error on Channel */
-#define BITP_CORE_ALERT_DETAIL_CH_CALIBRATION_INVALID 7 /* Indicates Problem During Calibration of Channel */
-#define BITP_CORE_ALERT_DETAIL_CH_REF_DETECT 6 /* Indicates Whether ADC Reference is Valid */
-#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 5 /* Indicates Sensor Input is Open Circuit */
-#define BITP_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 4 /* Indicates Sensor Result is Greater Than High Limit */
-#define BITP_CORE_ALERT_DETAIL_CH_LOW_LIMIT 3 /* Indicates Sensor Result is Less Than Low Limit */
-#define BITP_CORE_ALERT_DETAIL_CH_OVER_RANGE 2 /* Indicates Channel Over-Range */
-#define BITP_CORE_ALERT_DETAIL_CH_UNDER_RANGE 1 /* Indicates Channel Under-Range */
-#define BITP_CORE_ALERT_DETAIL_CH_TIME_OUT 0 /* Indicates Time-Out Error from Digital Sensor */
-#define BITM_CORE_ALERT_DETAIL_CH_COMP_NOT_READY 0x00008000 /* Indicates Compensation Channel Not Ready When Required */
-#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_NOT_READY 0x00004000 /* Indicates Digital Sensor Not Ready When Read */
-#define BITM_CORE_ALERT_DETAIL_CH_CORRECTION_OVERRANGE 0x00002000 /* Indicates Result Larger Than LUT/Equation Range */
-#define BITM_CORE_ALERT_DETAIL_CH_CORRECTION_UNDERRANGE 0x00001000 /* Indicates Result Less Than LUT/Equation Range */
-#define BITM_CORE_ALERT_DETAIL_CH_OVER_VOLTAGE 0x00000800 /* Indicates Channel Over-Voltage */
-#define BITM_CORE_ALERT_DETAIL_CH_UNDER_VOLTAGE 0x00000400 /* Indicates Channel Under-Voltage */
-#define BITM_CORE_ALERT_DETAIL_CH_LUT_ERROR_CH 0x00000200 /* Indicates Error with Channel Look-Up-Table */
-#define BITM_CORE_ALERT_DETAIL_CH_CONFIG_ERR 0x00000100 /* Indicates Configuration Error on Channel */
-#define BITM_CORE_ALERT_DETAIL_CH_CALIBRATION_INVALID 0x00000080 /* Indicates Problem During Calibration of Channel */
-#define BITM_CORE_ALERT_DETAIL_CH_REF_DETECT 0x00000040 /* Indicates Whether ADC Reference is Valid */
-#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_OPEN 0x00000020 /* Indicates Sensor Input is Open Circuit */
-#define BITM_CORE_ALERT_DETAIL_CH_HIGH_LIMIT 0x00000010 /* Indicates Sensor Result is Greater Than High Limit */
-#define BITM_CORE_ALERT_DETAIL_CH_LOW_LIMIT 0x00000008 /* Indicates Sensor Result is Less Than Low Limit */
-#define BITM_CORE_ALERT_DETAIL_CH_OVER_RANGE 0x00000004 /* Indicates Channel Over-Range */
-#define BITM_CORE_ALERT_DETAIL_CH_UNDER_RANGE 0x00000002 /* Indicates Channel Under-Range */
-#define BITM_CORE_ALERT_DETAIL_CH_TIME_OUT 0x00000001 /* Indicates Time-Out Error from Digital Sensor */
+#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_HARDFAULT 7 /* Indicates Sensor Hard Fault */
+#define BITP_CORE_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE 6 /* Indicates the ADC Input is Overrange */
+#define BITP_CORE_ALERT_DETAIL_CH_CJ_HARD_FAULT 5 /* Cold Junction Hard Fault */
+#define BITP_CORE_ALERT_DETAIL_CH_CJ_SOFT_FAULT 4 /* Cold Junction Soft Fault */
+#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_OVERRANGE 3 /* Indicates If the Sensor is Overrange */
+#define BITP_CORE_ALERT_DETAIL_CH_SENSOR_UNDERRANGE 2 /* Indicates If the Sensor is Underrange */
+#define BITP_CORE_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE 1 /* Indicates If the ADC is Near Overrange */
+#define BITP_CORE_ALERT_DETAIL_CH_RESULT_VALID 0 /* Set If a Result is Valid */
+#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_HARDFAULT 0x00000080 /* Indicates Sensor Hard Fault */
+#define BITM_CORE_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE 0x00000040 /* Indicates the ADC Input is Overrange */
+#define BITM_CORE_ALERT_DETAIL_CH_CJ_HARD_FAULT 0x00000020 /* Cold Junction Hard Fault */
+#define BITM_CORE_ALERT_DETAIL_CH_CJ_SOFT_FAULT 0x00000010 /* Cold Junction Soft Fault */
+#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_OVERRANGE 0x00000008 /* Indicates If the Sensor is Overrange */
+#define BITM_CORE_ALERT_DETAIL_CH_SENSOR_UNDERRANGE 0x00000004 /* Indicates If the Sensor is Underrange */
+#define BITM_CORE_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE 0x00000002 /* Indicates If the ADC is Near Overrange */
+#define BITM_CORE_ALERT_DETAIL_CH_RESULT_VALID 0x00000001 /* Set If a Result is Valid */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_ERROR_CODE Pos/Masks Description
@@ -1403,74 +847,60 @@
#define BITM_CORE_ERROR_CODE_ERROR_CODE 0x0000FFFF /* Code Indicating Type of Error */
/* -------------------------------------------------------------------------------------------------------------------------
- CORE_ALERT_CODE Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_ALERT_CODE_ALERT_CODE 0 /* Code Indicating Type of Alert */
-#define BITM_CORE_ALERT_CODE_ALERT_CODE 0x0000FFFF /* Code Indicating Type of Alert */
-
-/* -------------------------------------------------------------------------------------------------------------------------
CORE_EXTERNAL_REFERENCE_RESISTOR Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_EXTERNAL_REFERENCE_RESISTOR_EXT_REFIN1_VALUE 0 /* Refin1 Value */
-#define BITM_CORE_EXTERNAL_REFERENCE_RESISTOR_EXT_REFIN1_VALUE 0x00000000 /* Refin1 Value */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_EXTERNAL_VOLTAGE_REFERENCE Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_EXTERNAL_VOLTAGE_REFERENCE_EXT_REFIN2_VALUE 0 /* Refin2 Value */
-#define BITM_CORE_EXTERNAL_VOLTAGE_REFERENCE_EXT_REFIN2_VALUE 0x00000000 /* Refin2 Value */
+#define BITP_CORE_EXTERNAL_REFERENCE_RESISTOR_EXT_REFIN1_VALUE 0 /* External Reference Resistor Value */
+#define BITM_CORE_EXTERNAL_REFERENCE_RESISTOR_EXT_REFIN1_VALUE 0xFFFFFFFF /* External Reference Resistor Value */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_DIAGNOSTICS_CONTROL Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 2 /* Diagnostics Open Sensor Detect Frequency */
-#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 1 /* Diagnostics Measure Enable */
-#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0 /* Diagnostics Global Enable */
-#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x0000000C /* Diagnostics Open Sensor Detect Frequency */
-#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000002 /* Diagnostics Measure Enable */
-#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_GLOBAL_EN 0x00000001 /* Diagnostics Global Enable */
+#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 1 /* Diagnostics Open Sensor Detect Frequency */
+#define BITP_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0 /* Diagnostics Measure Enable */
+#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_OSD_FREQ 0x00000006 /* Diagnostics Open Sensor Detect Frequency */
+#define BITM_CORE_DIAGNOSTICS_CONTROL_DIAG_MEAS_EN 0x00000001 /* Diagnostics Measure Enable */
#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_OFF 0x00000000 /* Diag_OSD_Freq: No Open-Circuit Detection During Measurement */
-#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE 0x00000004 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Measurement Cycle */
-#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES 0x00000008 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */
-#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1000_CYCLES 0x0000000C /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Thousand Measurement Cycles */
+#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE 0x00000002 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Measurement Cycle */
+#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_10_CYCLES 0x00000004 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Ten Measurement Cycles */
+#define ENUM_CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES 0x00000006 /* Diag_OSD_Freq: Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_DATA_FIFO Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DATA_FIFO_DATA_FIFO 0 /* Fifo Buffer of Sensor Results */
-#define BITM_CORE_DATA_FIFO_DATA_FIFO 0x000000FF /* Fifo Buffer of Sensor Results */
+#define BITP_CORE_DATA_FIFO_DATA_FIFO 0 /* FIFO Buffer of Sensor Results */
+#define BITM_CORE_DATA_FIFO_DATA_FIFO 0x000000FF /* FIFO Buffer of Sensor Results */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_DEBUG_CODE Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DEBUG_CODE_DEBUG_CODE 0 /* Additional Information on Source of Alert or Errors */
-#define BITM_CORE_DEBUG_CODE_DEBUG_CODE 0x00000000 /* Additional Information on Source of Alert or Errors */
+#define BITM_CORE_DEBUG_CODE_DEBUG_CODE 0xFFFFFFFF /* Additional Information on Source of Alert or Errors */
/* -------------------------------------------------------------------------------------------------------------------------
- CORE_ADVANCED_SENSOR_ACCESS Pos/Masks Description
+ CORE_TEST_REG_ACCESS Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_ADVANCED_SENSOR_ACCESS_ADVANCED_SENSOR_ACCESS 0 /* Write Specific Key Value to Access Advanced Sensors */
-#define BITM_CORE_ADVANCED_SENSOR_ACCESS_ADVANCED_SENSOR_ACCESS 0x0000FFFF /* Write Specific Key Value to Access Advanced Sensors */
+#define BITP_CORE_TEST_REG_ACCESS_TEST_ACCESS 0 /* Test Register Access. Specific Write Sequence Required */
+#define BITM_CORE_TEST_REG_ACCESS_TEST_ACCESS 0x0000FFFF /* Test Register Access. Specific Write Sequence Required */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_LUT_SELECT Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_LUT_SELECT_LUT_RW 7 /* Read or Write LUT Data */
#define BITM_CORE_LUT_SELECT_LUT_RW 0x00000080 /* Read or Write LUT Data */
-#define ENUM_CORE_LUT_SELECT_LUT_READ 0x00000000 /* LUT_RW: Read Addressed LUT Data */
-#define ENUM_CORE_LUT_SELECT_LUT_WRITE 0x00000080 /* LUT_RW: Write Addressed LUT Data */
+#define ENUM_CORE_LUT_SELECT_LUT_READ 0x00000000 /* LUT_RW: Read addressed LUT data */
+#define ENUM_CORE_LUT_SELECT_LUT_WRITE 0x00000080 /* LUT_RW: Write addressed LUT data */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_LUT_OFFSET Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into Look-Up-Table */
-#define BITM_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into Look-Up-Table */
+#define BITP_CORE_LUT_OFFSET_LUT_OFFSET 0 /* Offset into the Lookup Table */
+#define BITM_CORE_LUT_OFFSET_LUT_OFFSET 0x00003FFF /* Offset into the Lookup Table */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_LUT_DATA Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to / Read from Look-Up-Table */
-#define BITM_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to / Read from Look-Up-Table */
+#define BITP_CORE_LUT_DATA_LUT_DATA 0 /* Data Byte to Write to and Read from the Lookup Table */
+#define BITM_CORE_LUT_DATA_LUT_DATA 0x000000FF /* Data Byte to Write to and Read from the Lookup Table */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_REVISION Pos/Masks Description
@@ -1486,9 +916,9 @@
CORE_CHANNEL_COUNT[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 7 /* Enable Channel in Measurement Cycle */
-#define BITP_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Should Appear in One Cycle */
+#define BITP_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0 /* How Many Times Channel Appears in One Cycle */
#define BITM_CORE_CHANNEL_COUNT_CHANNEL_ENABLE 0x00000080 /* Enable Channel in Measurement Cycle */
-#define BITM_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Should Appear in One Cycle */
+#define BITM_CORE_CHANNEL_COUNT_CHANNEL_COUNT 0x0000007F /* How Many Times Channel Appears in One Cycle */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_CHANNEL_OPTIONS[n] Pos/Masks Description
@@ -1501,59 +931,44 @@
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_TYPE_SENSOR_TYPE 0 /* Sensor Type */
#define BITM_CORE_SENSOR_TYPE_SENSOR_TYPE 0x00000FFF /* Sensor Type */
-#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_T 0x00000000 /* Sensor_Type: Thermocouple T-Type Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_J 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_K 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT100 0x00000020 /* Sensor_Type: RTD 2 Wire PT100 Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT1000 0x00000021 /* Sensor_Type: RTD 2 Wire PT1000 Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT100 0x00000040 /* Sensor_Type: RTD 3 Wire PT100 Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT1000 0x00000041 /* Sensor_Type: RTD 3 Wire PT1000 Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT100 0x00000060 /* Sensor_Type: RTD 4 Wire PT100 Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT1000 0x00000061 /* Sensor_Type: RTD 4 Wire PT1000 Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_A_10K 0x00000080 /* Sensor_Type: Thermistor Type A 10kOhm Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_THERMISTOR_B_10K 0x00000081 /* Sensor_Type: Thermistor Type B 10kOhm Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_BRIDGE_4W_2 0x000000A9 /* Sensor_Type: Bridge 4 Wire Sensor 2 Defined Level 2 */
-#define ENUM_CORE_SENSOR_TYPE_BRIDGE_6W_1 0x000000C8 /* Sensor_Type: Bridge 6 Wire Sensor 1 Defined Level 2 */
-#define ENUM_CORE_SENSOR_TYPE_BRIDGE_6W_2 0x000000C9 /* Sensor_Type: Bridge 6 Wire Sensor 2 Defined Level 2 */
-#define ENUM_CORE_SENSOR_TYPE_DIODE_2C_TYPEA 0x000000E0 /* Sensor_Type: Diode 2 Current Type A Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_DIODE_3C_TYPEA 0x000000E1 /* Sensor_Type: Diode 3 Current Type A Sensor Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_DIODE_2C_1 0x000000E8 /* Sensor_Type: Diode 2 Current Sensor 1 Defined Level 2 */
-#define ENUM_CORE_SENSOR_TYPE_DIODE_3C_1 0x000000E9 /* Sensor_Type: Diode 3 Current Sensor 1 Defined Level 2 */
-#define ENUM_CORE_SENSOR_TYPE_VOLTAGE 0x00000200 /* Sensor_Type: Voltage Input */
-#define ENUM_CORE_SENSOR_TYPE_VOLTAGE_PRESSURE_A 0x00000220 /* Sensor_Type: Voltage Output Pressure Sensor A Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_VOLTAGE_PRESSURE_B 0x00000221 /* Sensor_Type: Voltage Output Pressure Sensor B Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_CURRENT 0x00000300 /* Sensor_Type: Current Input */
-#define ENUM_CORE_SENSOR_TYPE_I2C_PRESSURE_A 0x00000800 /* Sensor_Type: I2C Pressure Sensor A Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_I2C_PRESSURE_B 0x00000801 /* Sensor_Type: I2C Pressure Sensor B Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_I2C_HUMIDITY_A 0x00000840 /* Sensor_Type: I2C Humidity Sensor A Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_I2C_HUMIDITY_B 0x00000841 /* Sensor_Type: I2C Humidity Sensor B Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_SPI_ACCELEROMETER_A 0x00000C80 /* Sensor_Type: SPI Accelerometer Sensor A 3-Axis Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_SPI_ACCELEROMETER_B 0x00000C81 /* Sensor_Type: SPI Accelerometer Sensor B 3-Axis Defined Level 1 */
-#define ENUM_CORE_SENSOR_TYPE_CO2_A_DEF 0x00000E00 /* Sensor_Type: CO2 Sensor A Defined Level 1 */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_T 0x00000000 /* Sensor_Type: Thermocouple T-Type sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_J 0x00000001 /* Sensor_Type: Thermocouple J-Type Sensor */
+#define ENUM_CORE_SENSOR_TYPE_THERMOCOUPLE_K 0x00000002 /* Sensor_Type: Thermocouple K-Type Sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT100 0x00000020 /* Sensor_Type: RTD 2 wire PT100 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_2W_PT1000 0x00000021 /* Sensor_Type: RTD 2 wire PT1000 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT100 0x00000040 /* Sensor_Type: RTD 3 wire PT100 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_3W_PT1000 0x00000041 /* Sensor_Type: RTD 3 wire PT1000 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT100 0x00000060 /* Sensor_Type: RTD 4 wire PT100 sensor */
+#define ENUM_CORE_SENSOR_TYPE_RTD_4W_PT1000 0x00000061 /* Sensor_Type: RTD 4 wire PT1000 sensor */
+#define ENUM_CORE_SENSOR_TYPE_BRIDGE_4W 0x000000A9 /* Sensor_Type: Bridge 4 wire sensor */
+#define ENUM_CORE_SENSOR_TYPE_CUSTOM1 0x00000400 /* Sensor_Type: Custom1 */
+#define ENUM_CORE_SENSOR_TYPE_I2C_HUMIDITY_B 0x00000841 /* Sensor_Type: I2C humidity sensor B */
+#define ENUM_CORE_SENSOR_TYPE_SENSOR_RESERVED_1 0x00000FE0 /* Sensor_Type: RESERVED. NOT TO BE USED */
+#define ENUM_CORE_SENSOR_TYPE_SENSOR_RESERVED_2 0x00000FFF /* Sensor_Type: RESERVED. NOT TO BE USED */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_SENSOR_DETAILS[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 31 /* Indicates Compensation Data Should Not Be Used */
-#define BITP_CORE_SENSOR_DETAILS_RTD_CURVE 27 /* Select RTD Curve for Linearisation */
+#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 31 /* This Bit Indicates Compensation Data Must Not Be Used */
+#define BITP_CORE_SENSOR_DETAILS_RTD_CURVE 27 /* Select RTD Curve for Linearization */
#define BITP_CORE_SENSOR_DETAILS_PGA_GAIN 24 /* PGA Gain */
#define BITP_CORE_SENSOR_DETAILS_REFERENCE_SELECT 20 /* Reference Selection */
#define BITP_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 17 /* Do Not Publish Channel Result */
#define BITP_CORE_SENSOR_DETAILS_LUT_SELECT 15 /* Lookup Table Select */
-#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel is Used to Compensate Sensor Result */
+#define BITP_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 4 /* Indicates Which Channel Used to Compensate the Sensor Result */
#define BITP_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0 /* Units of Sensor Measurement */
-#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 0x80000000 /* Indicates Compensation Data Should Not Be Used */
-#define BITM_CORE_SENSOR_DETAILS_RTD_CURVE 0x18000000 /* Select RTD Curve for Linearisation */
+#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_DISABLE 0x80000000 /* This Bit Indicates Compensation Data Must Not Be Used */
+#define BITM_CORE_SENSOR_DETAILS_RTD_CURVE 0x18000000 /* Select RTD Curve for Linearization */
#define BITM_CORE_SENSOR_DETAILS_PGA_GAIN 0x07000000 /* PGA Gain */
#define BITM_CORE_SENSOR_DETAILS_REFERENCE_SELECT 0x00F00000 /* Reference Selection */
#define BITM_CORE_SENSOR_DETAILS_DO_NOT_PUBLISH 0x00020000 /* Do Not Publish Channel Result */
#define BITM_CORE_SENSOR_DETAILS_LUT_SELECT 0x00018000 /* Lookup Table Select */
-#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel is Used to Compensate Sensor Result */
+#define BITM_CORE_SENSOR_DETAILS_COMPENSATION_CHANNEL 0x000000F0 /* Indicates Which Channel Used to Compensate the Sensor Result */
#define BITM_CORE_SENSOR_DETAILS_MEASUREMENT_UNITS 0x0000000F /* Units of Sensor Measurement */
-#define ENUM_CORE_SENSOR_DETAILS_EUROPEAN_CURVE 0x00000000 /* RTD_Curve: European Curve */
-#define ENUM_CORE_SENSOR_DETAILS_AMERICAN_CURVE 0x08000000 /* RTD_Curve: American Curve */
-#define ENUM_CORE_SENSOR_DETAILS_JAPANESE_CURVE 0x10000000 /* RTD_Curve: Japanese Curve */
-#define ENUM_CORE_SENSOR_DETAILS_ITS90_CURVE 0x18000000 /* RTD_Curve: ITS-90 Curve */
+#define ENUM_CORE_SENSOR_DETAILS_EUROPEAN_CURVE 0x00000000 /* RTD_Curve: European curve */
+#define ENUM_CORE_SENSOR_DETAILS_AMERICAN_CURVE 0x08000000 /* RTD_Curve: American curve */
+#define ENUM_CORE_SENSOR_DETAILS_JAPANESE_CURVE 0x10000000 /* RTD_Curve: Japanese curve */
+#define ENUM_CORE_SENSOR_DETAILS_ITS90_CURVE 0x18000000 /* RTD_Curve: ITS-90 curve */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_1 0x00000000 /* PGA_Gain: Gain of 1 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_2 0x01000000 /* PGA_Gain: Gain of 2 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_4 0x02000000 /* PGA_Gain: Gain of 4 */
@@ -1563,11 +978,11 @@
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_64 0x06000000 /* PGA_Gain: Gain of 64 */
#define ENUM_CORE_SENSOR_DETAILS_PGA_GAIN_128 0x07000000 /* PGA_Gain: Gain of 128 */
#define ENUM_CORE_SENSOR_DETAILS_REF_VINT 0x00000000 /* Reference_Select: Internal voltage reference (1.2V) */
-#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00100000 /* Reference_Select: External Voltage reference applied to VERF+ and VREF- */
-#define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00300000 /* Reference_Select: AVDD Supply Used as Excitation and Internally applied as Reference */
-#define ENUM_CORE_SENSOR_DETAILS_LUT_DEFAULT 0x00000000 /* LUT_Select: Default Lookup Table for Selected Sensor Type */
-#define ENUM_CORE_SENSOR_DETAILS_LUT_UNITY 0x00008000 /* LUT_Select: Unity Lookup Table. 1:1 Mapping From Input to Output */
-#define ENUM_CORE_SENSOR_DETAILS_LUT_CUSTOM 0x00010000 /* LUT_Select: User Defined Custom Lookup Table. */
+#define ENUM_CORE_SENSOR_DETAILS_REF_VEXT1 0x00100000 /* Reference_Select: External voltage reference applied to VERF+ and VREF- */
+#define ENUM_CORE_SENSOR_DETAILS_REF_AVDD 0x00300000 /* Reference_Select: AVDD supply internally used as reference */
+#define ENUM_CORE_SENSOR_DETAILS_LUT_DEFAULT 0x00000000 /* LUT_Select: Default lookup table for selected sensor type */
+#define ENUM_CORE_SENSOR_DETAILS_LUT_UNITY 0x00008000 /* LUT_Select: Unity lookup table. 1:1 mapping from input to output */
+#define ENUM_CORE_SENSOR_DETAILS_LUT_CUSTOM 0x00010000 /* LUT_Select: User defined custom lookup table. */
#define ENUM_CORE_SENSOR_DETAILS_LUT_RESERVED 0x00018000 /* LUT_Select: Reserved */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_UNSPECIFIED 0x00000000 /* Measurement_Units: Not Specified */
#define ENUM_CORE_SENSOR_DETAILS_UNITS_RESERVED 0x00000001 /* Measurement_Units: Reserved */
@@ -1577,19 +992,9 @@
/* -------------------------------------------------------------------------------------------------------------------------
CORE_CHANNEL_EXCITATION[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_CHANNEL_EXCITATION_IOUT_DIODE_RATIO 6 /* Modify Current Ratios Used for Diode Sensor */
#define BITP_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0 /* Current Source Value */
-#define BITM_CORE_CHANNEL_EXCITATION_IOUT_DIODE_RATIO 0x000001C0 /* Modify Current Ratios Used for Diode Sensor */
#define BITM_CORE_CHANNEL_EXCITATION_IOUT_EXCITATION_CURRENT 0x0000000F /* Current Source Value */
-#define ENUM_CORE_CHANNEL_EXCITATION_DIODE_2PT_10UA_100UA 0x00000000 /* IOUT_Diode_Ratio: 2 Current measurement 10uA 100uA */
-#define ENUM_CORE_CHANNEL_EXCITATION_DIODE_2PT_20UA_160UA 0x00000040 /* IOUT_Diode_Ratio: 2 Current measurement 20uA 160uA */
-#define ENUM_CORE_CHANNEL_EXCITATION_DIODE_2PT_50UA_300UA 0x00000080 /* IOUT_Diode_Ratio: 2 Current measurement 50uA 300uA */
-#define ENUM_CORE_CHANNEL_EXCITATION_DIODE_2PT_100UA_600UA 0x000000C0 /* IOUT_Diode_Ratio: 2 Current measurement 100uA 600uA */
-#define ENUM_CORE_CHANNEL_EXCITATION_DIODE_3PT_10UA_50UA_100UA 0x00000100 /* IOUT_Diode_Ratio: 3 current measuremet 10uA 50uA 100uA */
-#define ENUM_CORE_CHANNEL_EXCITATION_DIODE_3PT_20UA_100UA_160UA 0x00000140 /* IOUT_Diode_Ratio: 3 current measuremet 20uA 100uA 160uA */
-#define ENUM_CORE_CHANNEL_EXCITATION_DIODE_3PT_50UA_150UA_300UA 0x00000180 /* IOUT_Diode_Ratio: 3 current measuremet 50uA 150uA 300uA */
-#define ENUM_CORE_CHANNEL_EXCITATION_DIODE_3PT_100UA_300UA_600UA 0x000001C0 /* IOUT_Diode_Ratio: 3 current measuremet 100uA 300uA 600uA */
-#define ENUM_CORE_CHANNEL_EXCITATION_EXTERNAL 0x00000000 /* IOUT_Excitation_Current: External Current Sourced */
+#define ENUM_CORE_CHANNEL_EXCITATION_NONE 0x00000000 /* IOUT_Excitation_Current: Excitation Current Disabled */
#define ENUM_CORE_CHANNEL_EXCITATION_RESERVED 0x00000001 /* IOUT_Excitation_Current: Reserved */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_10UA 0x00000002 /* IOUT_Excitation_Current: 10 \mu;A */
#define ENUM_CORE_CHANNEL_EXCITATION_RESERVED2 0x00000003 /* IOUT_Excitation_Current: Reserved */
@@ -1598,6 +1003,7 @@
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_250UA 0x00000006 /* IOUT_Excitation_Current: 250 \mu;A */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_500UA 0x00000007 /* IOUT_Excitation_Current: 500 \mu;A */
#define ENUM_CORE_CHANNEL_EXCITATION_IEXC_1000UA 0x00000008 /* IOUT_Excitation_Current: 1000 \mu;A */
+#define ENUM_CORE_CHANNEL_EXCITATION_EXTERNAL 0x0000000F /* IOUT_Excitation_Current: External current sourced */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_SETTLING_TIME[n] Pos/Masks Description
@@ -1606,75 +1012,66 @@
#define BITP_CORE_SETTLING_TIME_SETTLING_TIME 0 /* Settling Time to Allow When Switching to Channel */
#define BITM_CORE_SETTLING_TIME_SETTLING_TIME_UNITS 0x0000C000 /* Units for Settling Time */
#define BITM_CORE_SETTLING_TIME_SETTLING_TIME 0x00003FFF /* Settling Time to Allow When Switching to Channel */
-#define ENUM_CORE_SETTLING_TIME_MICROSECONDS 0x00000000 /* Settling_Time_Units: Micro-Seconds */
-#define ENUM_CORE_SETTLING_TIME_MILLISECONDS 0x00004000 /* Settling_Time_Units: Milli-Seconds */
+#define ENUM_CORE_SETTLING_TIME_MICROSECONDS 0x00000000 /* Settling_Time_Units: Micro-seconds */
+#define ENUM_CORE_SETTLING_TIME_MILLISECONDS 0x00004000 /* Settling_Time_Units: Milli-seconds */
#define ENUM_CORE_SETTLING_TIME_SECONDS 0x00008000 /* Settling_Time_Units: Seconds */
+#define ENUM_CORE_SETTLING_TIME_UNDEFINED 0x0000C000 /* Settling_Time_Units: Undefined */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_MEASUREMENT_SETUP[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_MEASUREMENT_SETUP_BUFFER_BYPASS 15 /* Disable Buffers */
-#define BITP_CORE_MEASUREMENT_SETUP_GND_SW 13 /* GND_SW */
+#define BITP_CORE_MEASUREMENT_SETUP_GND_SW 13 /* Ground Switch Selection */
#define BITP_CORE_MEASUREMENT_SETUP_ADC_FILTER_TYPE 12 /* ADC Digital Filter Type */
#define BITP_CORE_MEASUREMENT_SETUP_CHOP_MODE 10 /* Enabled and Disable Chop Mode */
-#define BITP_CORE_MEASUREMENT_SETUP_PST_MEAS_EXC_CTRL 9 /* Disabled Current Sources After Measurement Has Been Complete */
+#define BITP_CORE_MEASUREMENT_SETUP_PST_MEAS_EXC_CTRL 9 /* Disable Current Sources After Measurement Completes */
#define BITP_CORE_MEASUREMENT_SETUP_NOTCH_EN_2 8 /* Enable Notch 2 Filter Mode */
-#define BITP_CORE_MEASUREMENT_SETUP_CUSTOM_CALIBRATION 7 /* Enables Custom Calibration for Selected Sensor */
-#define BITP_CORE_MEASUREMENT_SETUP_ADC_SF 0 /* ADC Digital Filter Select */
+#define BITP_CORE_MEASUREMENT_SETUP_ADC_SF 0 /* ADC Digital Filter Speed */
#define BITM_CORE_MEASUREMENT_SETUP_BUFFER_BYPASS 0x00008000 /* Disable Buffers */
-#define BITM_CORE_MEASUREMENT_SETUP_GND_SW 0x00006000 /* GND_SW */
+#define BITM_CORE_MEASUREMENT_SETUP_GND_SW 0x00006000 /* Ground Switch Selection */
#define BITM_CORE_MEASUREMENT_SETUP_ADC_FILTER_TYPE 0x00001000 /* ADC Digital Filter Type */
#define BITM_CORE_MEASUREMENT_SETUP_CHOP_MODE 0x00000C00 /* Enabled and Disable Chop Mode */
-#define BITM_CORE_MEASUREMENT_SETUP_PST_MEAS_EXC_CTRL 0x00000200 /* Disabled Current Sources After Measurement Has Been Complete */
+#define BITM_CORE_MEASUREMENT_SETUP_PST_MEAS_EXC_CTRL 0x00000200 /* Disable Current Sources After Measurement Completes */
#define BITM_CORE_MEASUREMENT_SETUP_NOTCH_EN_2 0x00000100 /* Enable Notch 2 Filter Mode */
-#define BITM_CORE_MEASUREMENT_SETUP_CUSTOM_CALIBRATION 0x00000080 /* Enables Custom Calibration for Selected Sensor */
-#define BITM_CORE_MEASUREMENT_SETUP_ADC_SF 0x0000007F /* ADC Digital Filter Select */
-#define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED 0x00000000
-#define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_DISABLED 0x00008000
-#define ENUM_CORE_MEASUREMENT_SETUP_GND_SW_OPEN 0x00000000 /* GND_SW: GND_SW Open. The GND SW is not enabled for the sensor measurement */
-#define ENUM_CORE_MEASUREMENT_SETUP_GND_SW_CLOSED 0x00002000 /* GND_SW: GND_SW Closed. The GND SW is enabled for the sensor measurement, bit wiil Remain Closed After the Measurement */
-#define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC4 0x00000000 /* ADC_Filter_Type: Enabled SINC4 Filter */
-#define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC3 0x00001000 /* ADC_Filter_Type: Enabled SINC3 Filter */
-#define ENUM_CORE_MEASUREMENT_SETUP_DISABLE_CHOP 0x00000000 /* Chop_Mode: Chop Mode Disabled */
-#define ENUM_CORE_MEASUREMENT_SETUP_HW_CHOP 0x00000400 /* Chop_Mode: Chop Mode Enabled */
-#define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_CHOP 0x00000800 /* Chop_Mode: Chop Mode Enabled */
-#define ENUM_CORE_MEASUREMENT_SETUP_HW_SW_CHOP 0x00000C00 /* Chop_Mode: Chop Mode Enabled */
+#define BITM_CORE_MEASUREMENT_SETUP_ADC_SF 0x0000007F /* ADC Digital Filter Speed */
+#define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED 0x00000000 /* Buffer_Bypass: Input buffers enabled */
+#define ENUM_CORE_MEASUREMENT_SETUP_BUFFERS_DISABLED 0x00008000 /* Buffer_Bypass: Input buffers disabled */
+#define ENUM_CORE_MEASUREMENT_SETUP_GND_SW_OPEN 0x00000000 /* GND_SW: GND_SW Open. The ground switch is not enabled for the sensor measurement */
+#define ENUM_CORE_MEASUREMENT_SETUP_GND_SW_CLOSED 0x00002000 /* GND_SW: GND_SW Closed. The ground switch is enabled for the sensor measurement, bit wiil Remain Closed After the Measurement */
+#define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC4 0x00000000 /* ADC_Filter_Type: Enabled SINC4 filter */
+#define ENUM_CORE_MEASUREMENT_SETUP_ENABLE_SINC3 0x00001000 /* ADC_Filter_Type: Enabled SINC3 filter */
+#define ENUM_CORE_MEASUREMENT_SETUP_DISABLE_CHOP 0x00000000 /* Chop_Mode: ADC front end chopping disabled */
+#define ENUM_CORE_MEASUREMENT_SETUP_HW_CHOP 0x00000400 /* Chop_Mode: Hardware chopping enabled */
+#define ENUM_CORE_MEASUREMENT_SETUP_SW_CHOP 0x00000800 /* Chop_Mode: SW chop enabled */
+#define ENUM_CORE_MEASUREMENT_SETUP_HW_SW_CHOP 0x00000C00 /* Chop_Mode: Hardware and software chop enabled */
#define ENUM_CORE_MEASUREMENT_SETUP_POWERCYCLE 0x00000000
#define ENUM_CORE_MEASUREMENT_SETUP_ALWAYSON 0x00000200
-#define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_DIS 0x00000000 /* NOTCH_EN_2: Disable Notch Filter */
-#define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_EN 0x00000100 /* NOTCH_EN_2: Enable Notch 2 Filter option. Places a addtional notch at 1.2X ODR. Can be used for 50 and 60Hz rejection simultaneously */
-#define ENUM_CORE_MEASUREMENT_SETUP_INTERNAL_CALIBRATION 0x00000000
-#define ENUM_CORE_MEASUREMENT_SETUP_CUSTOM_CALIBRATION 0x00000080
+#define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_DIS 0x00000000 /* NOTCH_EN_2: Disable notch filter */
+#define ENUM_CORE_MEASUREMENT_SETUP_NOTCH_EN 0x00000100 /* NOTCH_EN_2: Enable notch 2 filter option. */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_HIGH_THRESHOLD_LIMIT[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0 /* Upper Limit for Sensor Alert Comparison */
-#define BITM_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0x00000000 /* Upper Limit for Sensor Alert Comparison */
+#define BITM_CORE_HIGH_THRESHOLD_LIMIT_HIGH_THRESHOLD 0xFFFFFFFF /* Upper Limit for Sensor Alert Comparison */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_LOW_THRESHOLD_LIMIT[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0 /* Lower Limit for Sensor Alert Comparison */
-#define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0x00000000 /* Lower Limit for Sensor Alert Comparison */
+#define BITM_CORE_LOW_THRESHOLD_LIMIT_LOW_THRESHOLD 0xFFFFFFFF /* Lower Limit for Sensor Alert Comparison */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_SENSOR_OFFSET[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0 /* Sensor Offset Adjustment */
-#define BITM_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0x00000000 /* Sensor Offset Adjustment */
+#define BITM_CORE_SENSOR_OFFSET_SENSOR_OFFSET 0xFFFFFFFF /* Sensor Offset Adjustment */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_SENSOR_GAIN[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_SENSOR_GAIN_SENSOR_GAIN 0 /* Sensor Gain Adjustment */
-#define BITM_CORE_SENSOR_GAIN_SENSOR_GAIN 0x00000000 /* Sensor Gain Adjustment */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_ALERT_CODE_CH[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_ALERT_CODE_CH_ALERT_CODE_CH 0 /* Per-Channel Code Indicating Type of Alert */
-#define BITM_CORE_ALERT_CODE_CH_ALERT_CODE_CH 0x0000FFFF /* Per-Channel Code Indicating Type of Alert */
+#define BITM_CORE_SENSOR_GAIN_SENSOR_GAIN 0xFFFFFFFF /* Sensor Gain Adjustment */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_CHANNEL_SKIP[n] Pos/Masks Description
@@ -1683,20 +1080,6 @@
#define BITM_CORE_CHANNEL_SKIP_CHANNEL_SKIP 0x000000FF /* Indicates If Channel Will Skip Some Measurement Cycles */
/* -------------------------------------------------------------------------------------------------------------------------
- CORE_SENSOR_PARAMETER[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_SENSOR_PARAMETER_SENSOR_PARAMETER 0 /* Sensor Parameter Adjustment */
-#define BITM_CORE_SENSOR_PARAMETER_SENSOR_PARAMETER 0x00000000 /* Sensor Parameter Adjustment */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_CALIBRATION_PARAMETER[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER_ENABLE 24 /* Enables Use of Calibration_Parameter */
-#define BITP_CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER 0 /* Calibration Parameter Value */
-#define BITM_CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER_ENABLE 0x01000000 /* Enables Use of Calibration_Parameter */
-#define BITM_CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER 0x00FFFFFF /* Calibration Parameter Value */
-
-/* -------------------------------------------------------------------------------------------------------------------------
CORE_DIGITAL_SENSOR_CONFIG[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_DATA_BITS 11 /* Number of Relevant Data Bits */
@@ -1713,8 +1096,8 @@
#define BITM_CORE_DIGITAL_SENSOR_CONFIG_DIGITAL_SENSOR_CODING 0x00000003 /* Data Encoding of Sensor Result */
#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE 0x00000000 /* Digital_Sensor_Coding: None/Invalid */
#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR 0x00000001 /* Digital_Sensor_Coding: Unipolar */
-#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL 0x00000002 /* Digital_Sensor_Coding: Twos Complement */
-#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY 0x00000003 /* Digital_Sensor_Coding: Offset Binary */
+#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL 0x00000002 /* Digital_Sensor_Coding: Twos complement */
+#define ENUM_CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY 0x00000003 /* Digital_Sensor_Coding: Offset binary */
/* -------------------------------------------------------------------------------------------------------------------------
CORE_DIGITAL_SENSOR_ADDRESS[n] Pos/Masks Description
@@ -1723,28 +1106,20 @@
#define BITM_CORE_DIGITAL_SENSOR_ADDRESS_DIGITAL_SENSOR_ADDRESS 0x000000FF /* I2C Address or Write Address Command for SPI Sensor */
/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_NUM_CMDS[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS 4 /* Number of Read Commands for Digital Sensor */
-#define BITP_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS 0 /* Number of Configuration Commands for Digital Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS 0x00000070 /* Number of Read Commands for Digital Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS 0x00000007 /* Number of Configuration Commands for Digital Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
CORE_DIGITAL_SENSOR_COMMS[n] Pos/Masks Description
------------------------------------------------------------------------------------------------------------------------- */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 10 /* Configuration for Sensor SPI Protocol */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 5 /* Controls SCLK Frequency for I2C Sensors */
#define BITP_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 1 /* Controls Clock Frequency for SPI Sensors */
-#define BITP_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0 /* Enable Digital Sensor Comms Register Parameters */
+#define BITP_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0 /* Enable Digital Sensor Communications Register Parameters */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE 0x00000C00 /* Configuration for Sensor SPI Protocol */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_I2C_CLOCK 0x00000060 /* Controls SCLK Frequency for I2C Sensors */
#define BITM_CORE_DIGITAL_SENSOR_COMMS_SPI_CLOCK 0x0000001E /* Controls Clock Frequency for SPI Sensors */
-#define BITM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0x00000001 /* Enable Digital Sensor Comms Register Parameters */
-#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 0x00000000 /* SPI_Mode: Clock Polarity = 0 Clock Phase = 0 */
-#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 0x00000400 /* SPI_Mode: Clock Polarity = 0 Clock Phase = 1 */
-#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 0x00000800 /* SPI_Mode: Clock Polarity = 1 Clock Phase = 0 */
-#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 0x00000C00 /* SPI_Mode: Clock Polarity = 1 Clock Phase = 1 */
+#define BITM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_SENSOR_COMMS_EN 0x00000001 /* Enable Digital Sensor Communications Register Parameters */
+#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 0x00000000 /* SPI_Mode: Clock polarity = 0 Clock phase = 0 */
+#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 0x00000400 /* SPI_Mode: Clock polarity = 0 Clock phase = 1 */
+#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 0x00000800 /* SPI_Mode: Clock polarity = 1 Clock phase = 0 */
+#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 0x00000C00 /* SPI_Mode: Clock polarity = 1 Clock phase = 1 */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_100K 0x00000000 /* I2C_Clock: 100kHz SCL */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_400K 0x00000020 /* I2C_Clock: 400kHz SCL */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 0x00000040 /* I2C_Clock: Reserved */
@@ -1765,92 +1140,60 @@
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_977HZ 0x0000001A /* SPI_Clock: 977Hz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_488HZ 0x0000001C /* SPI_Clock: 488Hz */
#define ENUM_CORE_DIGITAL_SENSOR_COMMS_SPI_244HZ 0x0000001E /* SPI_Clock: 244Hz */
-#define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT 0x00000000 /* Digital_Sensor_Comms_En: Default Parameters Used for Digital Sensor Communications */
-#define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER 0x00000001 /* Digital_Sensor_Comms_En: User Supplied Parameters Used for Digital Sensor Communications */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_COMMAND1[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_COMMAND1_DIGITAL_SENSOR_COMMAND1 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_COMMAND2[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_COMMAND2_DIGITAL_SENSOR_COMMAND2 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_COMMAND3[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_COMMAND3_DIGITAL_SENSOR_COMMAND3 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_COMMAND4[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_COMMAND4_DIGITAL_SENSOR_COMMAND4 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_COMMAND4_DIGITAL_SENSOR_COMMAND4 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_COMMAND5[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_COMMAND5_DIGITAL_SENSOR_COMMAND5 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_COMMAND5_DIGITAL_SENSOR_COMMAND5 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_COMMAND6[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_COMMAND6_DIGITAL_SENSOR_COMMAND6 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_COMMAND6_DIGITAL_SENSOR_COMMAND6 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_COMMAND7[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_COMMAND7_DIGITAL_SENSOR_COMMAND7 0 /* Configuration Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_COMMAND7_DIGITAL_SENSOR_COMMAND7 0x000000FF /* Configuration Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_READ_CMD1[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_READ_CMD1_DIGITAL_SENSOR_READ_CMD1 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_READ_CMD1_DIGITAL_SENSOR_READ_CMD1 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_READ_CMD2[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_READ_CMD2_DIGITAL_SENSOR_READ_CMD2 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_READ_CMD2_DIGITAL_SENSOR_READ_CMD2 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_READ_CMD3[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_READ_CMD3_DIGITAL_SENSOR_READ_CMD3 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_READ_CMD3_DIGITAL_SENSOR_READ_CMD3 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_READ_CMD4[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_READ_CMD4_DIGITAL_SENSOR_READ_CMD4 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_READ_CMD4_DIGITAL_SENSOR_READ_CMD4 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_READ_CMD5[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_READ_CMD5_DIGITAL_SENSOR_READ_CMD5 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_READ_CMD5_DIGITAL_SENSOR_READ_CMD5 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_READ_CMD6[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_READ_CMD6_DIGITAL_SENSOR_READ_CMD6 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_READ_CMD6_DIGITAL_SENSOR_READ_CMD6 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-
-/* -------------------------------------------------------------------------------------------------------------------------
- CORE_DIGITAL_SENSOR_READ_CMD7[n] Pos/Masks Description
- ------------------------------------------------------------------------------------------------------------------------- */
-#define BITP_CORE_DIGITAL_SENSOR_READ_CMD7_DIGITAL_SENSOR_READ_CMD7 0 /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
-#define BITM_CORE_DIGITAL_SENSOR_READ_CMD7_DIGITAL_SENSOR_READ_CMD7 0x000000FF /* Per Conversion Command to Send to Digital I2C/SPI Sensor */
+#define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT 0x00000000 /* Digital_Sensor_Comms_En: Default parameters used for digital sensor communications */
+#define ENUM_CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER 0x00000001 /* Digital_Sensor_Comms_En: User supplied parameters used for digital sensor communications */
+/* SPI Parameters */
+
+/***** SPI */
+#define PARAM_SPI_SPI_STANDARD "LPT" /* A part must declare which SPI Standard it follows, either ADI or LPT */
+#define PARAM_SPI_CHIP_GRADE_VALUE 0 /* This is used to indicate speed grades/linearity. */
+#define PARAM_SPI_CHIP_REVISION_VALUE 0 /* This is used to indicate the silicon revision */
+#define PARAM_SPI_HAS_M_S_REGISTERS 0 /* If a design uses Master-Slave registers this must be set to true to enable relevant control bit fields */
+#define PARAM_SPI_M_S_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS the M-S Transfer bit field */
+#define PARAM_SPI_STREAM_MODE_TRANSFER_BF_EXISTS 0 /* Used to set EXISTS of the stream mode transfer bit field */
+#define PARAM_SPI_MSB_AND_LSB_FIRST_SUPPORT 0 /* Determines if the parts supports MSB and LSB first options */
+#define PARAM_SPI_WIRE_MODE_SUPPORT "_4_WIRE" /* Configures which hardware SPI modes are supported */
+#define PARAM_SPI_WIRE_MODE_DEFAULT "_4_WIRE" /* Sets the default hardware SPI mode */
+#define PARAM_SPI_MULTI_IO_CHANNELS 1 /* Defines the number of SDIO pins supported by the SPI in Multi-IO Mode. Should be 1,2,4, or 8. */
+#define PARAM_SPI_LPT_STANDARD_VERSION "REV1_0" /* This is a string from the LPT_STANDARD_VERSION_OPTIONS array for the active LPT SPI Standard version */
+#define PARAM_SPI_HAS_CSB_PIN 1 /* Does the part have a csb pin? */
+#define PARAM_SPI_BUS_MODE_SUPPORT 1 /* When set to true, Bus mode is supported. */
+#define PARAM_SPI_ISOLATED_3_WIRE_SUPPORT 0 /* Does the part support the 3-wire isolate mode of operation */
+#define PARAM_SPI_DAISY_CHAIN_MODE_SUPPORT 0 /* When set to true, Daisy chain mode is supported. */
+#define PARAM_SPI_CHECK_GTE_1_MODE_SUPPORTED 1 /* This is used to check that at least mode is enabled */
+#define PARAM_SPI_INTERFACE_MODE_SWITCH "None" /* Valid options are 'None', 'HW' or 'SW' */
+#define PARAM_SPI_CRC_SUPPORT "CRC_CONFIGURABLE" /* Set to true to enable bit fields related to CRC. */
+#define PARAM_SPI_CRC_SUPPORT_ENABLED 0 /* Verilog output parameter for 'define */
+#define PARAM_SPI_CRC_SUPPORT_ENABLE 1 /* Configures if CRC features are enabled in the module */
+#define PARAM_SPI_LPT_STANDARD_VERSION_VALUE 2 /* Index value of the active LPT SPI Standard version */
+#define PARAM_SPI_ADDRESS_MODE_SUPPORT "_15_BIT" /* Configures which addressing modes are supported */
+#define PARAM_SPI_ADDRESS_MODE_DEFAULT "_15_BIT" /* Sets the default addressing mode */
+#define PARAM_SPI_ADDRESS_BUS_WIDTH 15 /* Verilog output parameter for 'define */
+#define PARAM_SPI_SLOW_IFACE_CTRL_SUPPORT 0 /* Does the part support the Slow Interface Control feature */
+#define PARAM_SPI_SOFT_RESET_0_BF_EXISTS 0 /* Used to control if the SOFT_RESET_0 bit field exists */
+#define PARAM_SPI_SOFT_RESET_1_BF_EXISTS 0 /* Used to control if the SOFT_RESET_1 bit field exists */
+#define PARAM_SPI_SEND_STATUS_SUPPORT "SEND_STATUS_CONFIGURABLE" /* Determines if and how the part supports the SEND_STATUS feature */
+#define PARAM_SPI_SEND_STATUS_SUPPORT_ENABLE 1 /* This is used to enable various send status features */
+#define PARAM_SPI_SPI_STANDARD_VERSION_VALUE 2 /* Value for SPI Standard VERSION bit field */
+#define PARAM_SPI_ENTITY_ACCESS_SUPPORT "ENTITY_ACCESS_ALWAYS" /* Configures which entity access mode(s) are supported */
+#define PARAM_SPI_ENTITY_ACCESS_SUPPORT_ENABLE 1 /* This is used to enable/disable Strict Entity Access features */
+#define PARAM_SPI_ENTITY_ACCESS_DEFAULT 1 /* Sets the default entity access mode */
+#define PARAM_SPI_CHIP_INDEX_EXISTS 0 /* Used to control if the CHIP_INDEX register and related bit field exists */
+#define PARAM_SPI_OFFSET_DEV_INDEX_EXISTS 0 /* Used to control if the OFFSET_DEV_INDEX bit field and registers exists */
+#define PARAM_SPI_DEV_INDEX_EXISTS 0 /* Used to control if the DEV_INDEX bit field and register exists */
+#define PARAM_SPI_STATUS_BIT_0_EXISTS 0 /* Sets EXIST for Status Bit 0 */
+#define PARAM_SPI_STATUS_BIT_1_EXISTS 0 /* Sets EXIST for Status Bit 1 */
+#define PARAM_SPI_STATUS_BIT_2_EXISTS 0 /* Sets EXIST for Status Bit 2 */
+#define PARAM_SPI_STATUS_BIT_3_EXISTS 0 /* Sets EXIST for Status Bit 3 */
+#define PARAM_SPI_STATUS_BIT_0_SWNAME "Status_Bit_0" /* Software Name for Status Bit 0 */
+#define PARAM_SPI_STATUS_BIT_1_SWNAME "Status_Bit_1" /* Software Name for Status Bit 1 */
+#define PARAM_SPI_STATUS_BIT_2_SWNAME "Status_Bit_2" /* Software Name for Status Bit 2 */
+#define PARAM_SPI_STATUS_BIT_3_SWNAME "Status_Bit_3" /* Software Name for Status Bit 3 */
+#define PARAM_SPI_CHIP_TYPE "P_ADC" /* This is a string that corresponds to one of the values in the CHIP_TYPE_OPTIONS array and corresponds to the type of chip being developed */
+#define PARAM_SPI_CHIP_TYPE_VALUE 7 /* Integer value corresponding to selected CHIP_TYPE, and is used as bit field enum value */
+#define PARAM_SPI_PRODUCT_ID_VALUE 32 /* This value is used to identify a specific generic. */
+#define PARAM_SPI_PRODUCT_ID_TRIM_BITS 4 /* This defines the number of PRODUCT_ID bits that can be fuse/trimmed. */
+
#endif /* end ifndef _DEF_ADMW1001_REGISTERS_H */
--- a/inc/admw1001/ADMW1001_REGISTERS_typedefs.h Wed Oct 23 16:18:50 2019 +0000
+++ b/inc/admw1001/ADMW1001_REGISTERS_typedefs.h Fri Oct 25 05:08:19 2019 +0000
@@ -1,16 +1,24 @@
/* ================================================================================
+
+ Created by :
+ Created on : 2019 Oct 08, 09:43 GMT Daylight Time
Project : ADMW1001_REGISTERS
File : ADMW1001_REGISTERS_typedefs.h
Description : C Register Structures
- Date : Jun 19, 2019
+ !! ADI Confidential !!
+ INTERNAL USE ONLY
Copyright (c) 2019 Analog Devices, Inc. All Rights Reserved.
This software is proprietary and confidential to Analog Devices, Inc. and
its licensors.
This file was auto-generated. Do not make local changes to this file.
+
+ Auto generation script information:
+ Script: C:\Program Files (x86)\Yoda-19.05.01\generators\inc\genHeaders
+ Last modified: 26-SEP-2017
================================================================================ */
@@ -50,12 +58,12 @@
typedef struct _ADMW_SPI_Interface_Config_A_t {
union {
struct {
- uint8_t SW_ResetX : 1; /**< Second of Two of SW_RESET Bits. */
+ uint8_t SW_ResetX : 1; /**< Second of Two of the SW_RESET Bits. */
uint8_t reserved1 : 3;
- uint8_t SDO_Enable : 1; /**< SDO Pin Enable */
+ uint8_t SDO_Enable : 1; /**< Serial Data Output Pin Enable */
uint8_t Addr_Ascension : 1; /**< Determines Sequential Addressing Behavior */
uint8_t reserved6 : 1;
- uint8_t SW_Reset : 1; /**< First of Two of SW_RESET Bits. */
+ uint8_t SW_Reset : 1; /**< First of Two of the SW_RESET Bits. */
};
uint8_t VALUE8;
};
@@ -95,38 +103,6 @@
/*@}*/
-/** @defgroup Device_Config Device Configuration (Device_Config) Register
- * Device Configuration (Device_Config) Register.
- * @{
- */
-
-/* =========================================================================
- *! \enum ADMW_SPI_Device_Config_Operating_Modes
- *! \brief Power Modes (Operating_Modes) Enumerations
- * ========================================================================= */
-typedef enum
-{
- SPI_DEVICE_CONFIG_NORMAL = 0, /**< Normal Operating Mode */
- SPI_DEVICE_CONFIG_SLEEP = 3 /**< Low Power Mode */
-} ADMW_SPI_Device_Config_Operating_Modes;
-
-
-/* ==========================================================================
- *! \struct ADMW_SPI_Device_Config_Struct
- *! \brief Device Configuration Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_SPI_Device_Config_t {
- union {
- struct {
- uint8_t Operating_Modes : 2; /**< Power Modes */
- uint8_t reserved2 : 6;
- };
- uint8_t VALUE8;
- };
-} ADMW_SPI_Device_Config_t;
-
-/*@}*/
-
/** @defgroup Chip_Type Chip Type (Chip_Type) Register
* Chip Type (Chip_Type) Register.
* @{
@@ -160,7 +136,8 @@
typedef struct _ADMW_SPI_Product_ID_L_t {
union {
struct {
- uint8_t Product_ID : 8; /**< Product_ID[7:0] This is Device Chip Type/Family */
+ uint8_t Product_ID_Trim_Bits : 4; /**< These Bits Vary on Die Configured for Multiple Generics */
+ uint8_t Product_ID_Fixed_Bits : 4; /**< Product_ID_Fixed_Bits[3:0] These Bits are Fixed on Die Configured for Multiple Generics */
};
uint8_t VALUE8;
};
@@ -180,7 +157,7 @@
typedef struct _ADMW_SPI_Product_ID_H_t {
union {
struct {
- uint8_t Product_ID : 8; /**< Product_ID[15:8] This is Device Chip Type/Family */
+ uint8_t Product_ID_Fixed_Bits : 8; /**< Product_ID_Fixed_Bits[11:4] These Bits are Fixed on Die Configured for Multiple Generics */
};
uint8_t VALUE8;
};
@@ -200,8 +177,8 @@
typedef struct _ADMW_SPI_Chip_Grade_t {
union {
struct {
- uint8_t Device_Revision : 4; /**< This is the Device Hardware Revision */
- uint8_t Grade : 4; /**< This is the Device Performance Grade */
+ uint8_t Device_Revision : 4; /**< Device Hardware Revision */
+ uint8_t Grade : 4; /**< Device Performance Grade */
};
uint8_t VALUE8;
};
@@ -250,8 +227,8 @@
* ========================================================================= */
typedef enum
{
- SPI_SPI_REVISION_ADI_SPI = 0, /**< */
- SPI_SPI_REVISION_LPT_SPI = 2 /**< */
+ SPI_SPI_REVISION_ADI_SPI = 0, /**< ADI_SPI */
+ SPI_SPI_REVISION_LPT_SPI = 2 /**< LPT_SPI */
} ADMW_SPI_SPI_Revision_SPI_Type;
@@ -323,7 +300,7 @@
typedef struct _ADMW_SPI_Stream_Mode_t {
union {
struct {
- uint8_t Loop_Count : 8; /**< Sets the Data Byte Count Before Looping to Start Address */
+ uint8_t Loop_Count : 8; /**< Set the Data Byte Count Before Looping to Start Address */
};
uint8_t VALUE8;
};
@@ -338,7 +315,7 @@
/* =========================================================================
*! \enum ADMW_SPI_Transfer_Config_Stream_Mode
- *! \brief When Streaming, Controls Master-Slave Transfer (Stream_Mode) Enumerations
+ *! \brief When Streaming, Control Master to Slave Transfer (Stream_Mode) Enumerations
* ========================================================================= */
typedef enum
{
@@ -355,7 +332,7 @@
union {
struct {
uint8_t reserved0 : 1;
- uint8_t Stream_Mode : 1; /**< When Streaming, Controls Master-Slave Transfer */
+ uint8_t Stream_Mode : 1; /**< When Streaming, Control Master to Slave Transfer */
uint8_t reserved2 : 6;
};
uint8_t VALUE8;
@@ -371,7 +348,7 @@
/* =========================================================================
*! \enum ADMW_SPI_Interface_Config_C_Strict_Register_Access
- *! \brief Multi-byte Registers Must Be Read/Written in Full (Strict_Register_Access) Enumerations
+ *! \brief Multibyte Registers Must Be Read or Written in Full (Strict_Register_Access) Enumerations
* ========================================================================= */
typedef enum
{
@@ -400,8 +377,8 @@
struct {
uint8_t CRC_EnableB : 2; /**< Inverted CRC Enable */
uint8_t reserved2 : 2;
- uint8_t Send_Status : 1; /**< Enables Sending of Status in 4-wire Mode */
- uint8_t Strict_Register_Access : 1; /**< Multi-byte Registers Must Be Read/Written in Full */
+ uint8_t Send_Status : 1; /**< Sends Status in 4-Wire Mode When Enabled */
+ uint8_t Strict_Register_Access : 1; /**< Multibyte Registers Must Be Read or Written in Full */
uint8_t CRC_Enable : 2; /**< CRC Enable */
};
uint8_t VALUE8;
@@ -422,9 +399,9 @@
typedef struct _ADMW_SPI_Interface_Status_A_t {
union {
struct {
- uint8_t Address_Invalid_Error : 1; /**< Attempt to Read/Write Non-existent Register Address */
+ uint8_t Address_Invalid_Error : 1; /**< Attempt to Read/Write Nonexistent Register Address */
uint8_t Register_Partial_Access_Error : 1; /**< Set When Fewer Than Expected Number of Bytes Read/Written */
- uint8_t Wr_To_Rd_Only_Reg_Error : 1; /**< Write to Read-Only Register Attempted */
+ uint8_t Wr_To_Rd_Only_Reg_Error : 1; /**< Write to Read Only Register Attempted */
uint8_t CRC_Error : 1; /**< Invalid/No CRC Received */
uint8_t Clock_Count_Error : 1; /**< Incorrect Number of Clocks Detected in a Transaction */
uint8_t reserved5 : 2;
@@ -436,8 +413,8 @@
/*@}*/
-/** @defgroup Command Special Command (Command) Register
- * Special Command (Command) Register.
+/** @defgroup Command Special Command Register (Command) Register
+ * Special Command Register (Command) Register.
* @{
*/
@@ -447,15 +424,15 @@
* ========================================================================= */
typedef enum
{
- CORE_COMMAND_NOP = 0, /**< No Command */
- CORE_COMMAND_CONVERT = 1, /**< Start ADC Conversions */
- CORE_COMMAND_CONVERT_WITH_RAW = 2, /**< Start Conversions with Added RAW ADC Data */
- CORE_COMMAND_LATCH_CONFIG = 7, /**< Latch Configuration. */
- CORE_COMMAND_LOAD_LUT = 8, /**< Load LUT from FLASH */
- CORE_COMMAND_SAVE_LUT = 9, /**< Save LUT to FLASH */
- CORE_COMMAND_POWER_DOWN = 20, /**< Enter Low Power State */
- CORE_COMMAND_LOAD_CONFIG_1 = 24, /**< Load Registers with Configuration#1 from FLASH */
- CORE_COMMAND_SAVE_CONFIG_1 = 25 /**< Store Current Registers to FLASH Configuration#1 */
+ CORE_COMMAND_NOP = 0, /**< No command */
+ CORE_COMMAND_CONVERT = 1, /**< Start ADC conversions */
+ CORE_COMMAND_CONVERT_WITH_RAW = 2, /**< Start conversions with added raw ADC data */
+ CORE_COMMAND_LATCH_CONFIG = 7, /**< Latch configuration. */
+ CORE_COMMAND_LOAD_LUT = 8, /**< Load LUT from flash */
+ CORE_COMMAND_SAVE_LUT = 9, /**< Save LUT to flash */
+ CORE_COMMAND_POWER_DOWN = 20, /**< Enter Low Power State */
+ CORE_COMMAND_LOAD_CONFIG_1 = 24, /**< Load registers with configuration from flash */
+ CORE_COMMAND_SAVE_CONFIG_1 = 25 /**< Store current registers to flash configuration */
} ADMW_CORE_Command_Special_Command;
@@ -485,19 +462,20 @@
* ========================================================================= */
typedef enum
{
- CORE_MODE_SINGLECYCLE = 0, /**< Single Cycle */
- CORE_MODE_CONTINUOUS = 2 /**< Continuous Conversion */
+ CORE_MODE_SINGLECYCLE = 0, /**< Single cycle conversion mode. A cycle is completed every time a convert command is issued */
+ CORE_MODE_RESERVED = 1, /**< Reserved for future use */
+ CORE_MODE_CONTINUOUS = 2 /**< Continuous conversion mode. A cycle is started repeatedly at time specified in cycle time */
} ADMW_CORE_Mode_Conversion_Mode;
/* =========================================================================
*! \enum ADMW_CORE_Mode_Drdy_Mode
- *! \brief Indicates Behavior of DRDY with Respect to FIFO State (Drdy_Mode) Enumerations
+ *! \brief Indicates Behavior of DRDY Pin (Drdy_Mode) Enumerations
* ========================================================================= */
typedef enum
{
- CORE_MODE_DRDY_PER_CONVERSION = 0, /**< Data Ready Per Conversion */
- CORE_MODE_DRDY_PER_CYCLE = 1 /**< Data Ready Per Cycle */
+ CORE_MODE_DRDY_PER_CONVERSION = 0, /**< Data ready per conversion */
+ CORE_MODE_DRDY_PER_CYCLE = 1 /**< Data ready per cycle */
} ADMW_CORE_Mode_Drdy_Mode;
@@ -509,7 +487,7 @@
union {
struct {
uint8_t Conversion_Mode : 2; /**< Conversion Mode */
- uint8_t Drdy_Mode : 2; /**< Indicates Behavior of DRDY with Respect to FIFO State */
+ uint8_t Drdy_Mode : 2; /**< Indicates Behavior of DRDY Pin */
uint8_t reserved4 : 4;
};
uint8_t VALUE8;
@@ -518,8 +496,8 @@
/*@}*/
-/** @defgroup Power_Config General Configuration (Power_Config) Register
- * General Configuration (Power_Config) Register.
+/** @defgroup Power_Config Power Configuration (Power_Config) Register
+ * Power Configuration (Power_Config) Register.
* @{
*/
@@ -529,14 +507,14 @@
* ========================================================================= */
typedef enum
{
- CORE_POWER_CONFIG_ACTIVE_MODE = 0, /**< Part is fully powered up and either cycling through a sequence or awaiting a configuration */
- CORE_POWER_CONFIG_HIBERNATION = 1 /**< module has entede hibernation mode. All analog circuitry is disabled. All peripherals disabled apart from the Wake-up pin functionality. */
+ CORE_POWER_CONFIG_ACTIVE_MODE = 0, /**< ADMW1001 is fully power up and ready to convert */
+ CORE_POWER_CONFIG_HIBERNATION = 1 /**< Lowest power mode. wakeup pin required to enter active mode. SPI powered down */
} ADMW_CORE_Power_Config_Power_Mode_MCU;
/* ==========================================================================
*! \struct ADMW_CORE_Power_Config_Struct
- *! \brief General Configuration Register bit field structure
+ *! \brief Power Configuration Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Power_Config_t {
union {
@@ -556,24 +534,13 @@
*/
/* =========================================================================
- *! \enum ADMW_CORE_Cycle_Control_Cycle_Type
- *! \brief Type of Measurement Cycle (Cycle_Type) Enumerations
- * ========================================================================= */
-typedef enum
-{
- CORE_CYCLE_CONTROL_SWITCH = 0, /**< Switch Channels After Every Conversion */
- CORE_CYCLE_CONTROL_FULL = 1 /**< Perform Full Number Of Conversions On A Channel Consecutively */
-} ADMW_CORE_Cycle_Control_Cycle_Type;
-
-
-/* =========================================================================
*! \enum ADMW_CORE_Cycle_Control_Vbias
*! \brief Voltage Bias Global Enable (Vbias) Enumerations
* ========================================================================= */
typedef enum
{
- CORE_CYCLE_CONTROL_VBIAS_DISABLE = 0, /**< Vbias Disabled */
- CORE_CYCLE_CONTROL_VBIAS_ENABLE = 1 /**< Enable Vbias Output For the Duration of a Cycle */
+ CORE_CYCLE_CONTROL_VBIAS_DISABLE = 0, /**< Vbias disabled */
+ CORE_CYCLE_CONTROL_VBIAS_ENABLE = 1 /**< Enable Vbias output for the duration of a cycle */
} ADMW_CORE_Cycle_Control_Vbias;
@@ -583,7 +550,7 @@
* ========================================================================= */
typedef enum
{
- CORE_CYCLE_CONTROL_MILLISECONDS = 0, /**< Milli-Seconds */
+ CORE_CYCLE_CONTROL_MILLISECONDS = 0, /**< Milli-seconds */
CORE_CYCLE_CONTROL_SECONDS = 1 /**< Seconds */
} ADMW_CORE_Cycle_Control_Cycle_Time_Units;
@@ -595,10 +562,11 @@
typedef struct _ADMW_CORE_Cycle_Control_t {
union {
struct {
- uint16_t Cycle_Time : 12; /**< Duration of a Full Measurement Cycle */
- uint16_t Cycle_Type : 1; /**< Type of Measurement Cycle */
+ uint16_t Cycle_Time : 12; /**< Time Between Measurement Cycles */
+ uint16_t reserved12 : 1;
uint16_t Vbias : 1; /**< Voltage Bias Global Enable */
- uint16_t Cycle_Time_Units : 2; /**< Units for Cycle Time */
+ uint16_t Cycle_Time_Units : 1; /**< Units for Cycle Time */
+ uint16_t reserved15 : 1;
};
uint16_t VALUE16;
};
@@ -606,6 +574,26 @@
/*@}*/
+/** @defgroup Fifo_Num_Cycles Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register
+ * Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register.
+ * @{
+ */
+
+/* ==========================================================================
+ *! \struct ADMW_CORE_Fifo_Num_Cycles_Struct
+ *! \brief Number of Measurement Cycles to Store in FIFO Register bit field structure
+ * ========================================================================== */
+typedef struct _ADMW_CORE_Fifo_Num_Cycles_t {
+ union {
+ struct {
+ uint8_t Fifo_Num_Cycles : 8; /**< Number of Cycles to Fill the FIFO */
+ };
+ uint8_t VALUE8;
+ };
+} ADMW_CORE_Fifo_Num_Cycles_t;
+
+/*@}*/
+
/** @defgroup Status General Status (Status) Register
* General Status (Status) Register.
* @{
@@ -618,13 +606,14 @@
typedef struct _ADMW_CORE_Status_t {
union {
struct {
- uint8_t reserved0 : 1;
- uint8_t Alert_Active : 1; /**< Indicates One or More Sensors Alerts are Active */
- uint8_t Error : 1; /**< Indicates an Error */
- uint8_t Drdy : 1; /**< Indicates a New Sensor Result is Available to Be Read */
- uint8_t Cmd_Running : 1; /**< Indicates a Special Command is Active */
- uint8_t FIFO_Error : 1; /**< Indicates Error with FIFO */
- uint8_t reserved6 : 2;
+ uint8_t Configuration_Error : 1; /**< Indicates Error with Programmed Configuration */
+ uint8_t Alert_Active : 1; /**< Indicates One or More Sensor Alerts Active */
+ uint8_t Error : 1; /**< Indicates an Error */
+ uint8_t Drdy : 1; /**< Indicates New Sensor Result Available to Read */
+ uint8_t Cmd_Running : 1; /**< Indicates Special Command Active */
+ uint8_t FIFO_Error : 1; /**< Indicates Error with FIFO */
+ uint8_t Diag_Checksum_Error : 1; /**< Indicates Error on Internal Checksum Calculations */
+ uint8_t LUT_Error : 1; /**< Indicates Error with One or More Lookup Tables */
};
uint8_t VALUE8;
};
@@ -632,34 +621,6 @@
/*@}*/
-/** @defgroup Diagnostics_Status Diagnostics Status (Diagnostics_Status) Register
- * Diagnostics Status (Diagnostics_Status) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Diagnostics_Status_Struct
- *! \brief Diagnostics Status Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Diagnostics_Status_t {
- union {
- struct {
- uint16_t Diag_Checksum_Error : 1; /**< Indicates Error on Internal Checksum Calculations */
- uint16_t reserved1 : 7;
- uint16_t Diag_Ainm_UV_Error : 1; /**< Indicates Under-Voltage Error on Negative Analog Input */
- uint16_t Diag_Ainm_OV_Error : 1; /**< Indicates Over-Voltage Error on Negative Analog Input */
- uint16_t Diag_Ainp_UV_Error : 1; /**< Indicates Under-Voltage Error on Positive Analog Input */
- uint16_t Diag_Ainp_OV_Error : 1; /**< Indicates Over-Voltage Error on Positive Analog Input */
- uint16_t Diag_Conversion_Error : 1; /**< Indicates Error During Internal ADC Conversions */
- uint16_t Diag_Calibration_Error : 1; /**< Indicates Error During Internal Device Calibrations */
- uint16_t reserved14 : 2;
- };
- uint16_t VALUE16;
- };
-} ADMW_CORE_Diagnostics_Status_t;
-
-/*@}*/
-
/** @defgroup Channel_Alert_Status Alert Status Summary (Channel_Alert_Status) Register
* Alert Status Summary (Channel_Alert_Status) Register.
* @{
@@ -672,19 +633,20 @@
typedef struct _ADMW_CORE_Channel_Alert_Status_t {
union {
struct {
- uint16_t Alert_Ch0 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch1 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch2 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch3 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch4 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch5 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch6 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch7 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch8 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch9 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch10 : 1; /**< Indicates Channel Alert is Active */
- uint16_t Alert_Ch11 : 1; /**< Indicates Channel Alert is Active */
- uint16_t reserved12 : 4;
+ uint16_t Alert_Ch0 : 1; /**< Indicates Channel 0 Alert Active */
+ uint16_t Alert_Ch1 : 1; /**< Indicates Channel 1 Alert Active */
+ uint16_t Alert_Ch2 : 1; /**< Indicates Channel 2 Alert Active */
+ uint16_t Alert_Ch3 : 1; /**< Indicates Channel 3 Alert Active */
+ uint16_t Alert_Ch4 : 1; /**< Indicates Channel 4 Alert Active */
+ uint16_t Alert_Ch5 : 1; /**< Indicates Channel 5Alert Active */
+ uint16_t Alert_Ch6 : 1; /**< Indicates Channel 6 Alert Active */
+ uint16_t Alert_Ch7 : 1; /**< Indicates Channel 7 Alert Active */
+ uint16_t Alert_Ch8 : 1; /**< Indicates Channel 8 Alert Active */
+ uint16_t Alert_Ch9 : 1; /**< Indicates Channel 9 Alert Active */
+ uint16_t Alert_Ch10 : 1; /**< Indicates Channel 10 Alert Active */
+ uint16_t Alert_Ch11 : 1; /**< Indicates Channel 11 Alert Active */
+ uint16_t Alert_Ch12 : 1; /**< Indicates Channel 12 Alert Active */
+ uint16_t reserved13 : 3;
};
uint16_t VALUE16;
};
@@ -692,57 +654,27 @@
/*@}*/
-/** @defgroup Alert_Status_2 Additional Alert Status Information (Alert_Status_2) Register
- * Additional Alert Status Information (Alert_Status_2) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Alert_Status_2_Struct
- *! \brief Additional Alert Status Information Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Alert_Status_2_t {
- union {
- struct {
- uint16_t reserved0 : 1;
- uint16_t LUT_Error : 1; /**< Indicates Error with One or More Look-Up-Tables */
- uint16_t Configuration_Error : 1; /**< Indicates Error with Programmed Configuration */
- uint16_t reserved3 : 13;
- };
- uint16_t VALUE16;
- };
-} ADMW_CORE_Alert_Status_2_t;
-
-/*@}*/
-
-/** @defgroup Alert_Detail_Ch Detailed Error Information (Alert_Detail_Ch) Register
- * Detailed Error Information (Alert_Detail_Ch) Register.
+/** @defgroup Alert_Detail_Ch Detailed Channel Error Information (Alert_Detail_Ch) Register
+ * Detailed Channel Error Information (Alert_Detail_Ch) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Alert_Detail_Ch_Struct
- *! \brief Detailed Error Information Register bit field structure
+ *! \brief Detailed Channel Error Information Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Alert_Detail_Ch_t {
union {
struct {
- uint16_t Time_Out : 1; /**< Indicates Time-Out Error from Digital Sensor */
- uint16_t Under_Range : 1; /**< Indicates Channel Under-Range */
- uint16_t Over_Range : 1; /**< Indicates Channel Over-Range */
- uint16_t Low_Limit : 1; /**< Indicates Sensor Result is Less Than Low Limit */
- uint16_t High_Limit : 1; /**< Indicates Sensor Result is Greater Than High Limit */
- uint16_t Sensor_Open : 1; /**< Indicates Sensor Input is Open Circuit */
- uint16_t Ref_Detect : 1; /**< Indicates Whether ADC Reference is Valid */
- uint16_t Calibration_Invalid : 1; /**< Indicates Problem During Calibration of Channel */
- uint16_t Config_Err : 1; /**< Indicates Configuration Error on Channel */
- uint16_t LUT_Error_Ch : 1; /**< Indicates Error with Channel Look-Up-Table */
- uint16_t Under_Voltage : 1; /**< Indicates Channel Under-Voltage */
- uint16_t Over_Voltage : 1; /**< Indicates Channel Over-Voltage */
- uint16_t Correction_UnderRange : 1; /**< Indicates Result Less Than LUT/Equation Range */
- uint16_t Correction_OverRange : 1; /**< Indicates Result Larger Than LUT/Equation Range */
- uint16_t Sensor_Not_Ready : 1; /**< Indicates Digital Sensor Not Ready When Read */
- uint16_t Comp_Not_Ready : 1; /**< Indicates Compensation Channel Not Ready When Required */
+ uint16_t Result_Valid : 1; /**< Set If a Result is Valid */
+ uint16_t ADC_Near_Overrange : 1; /**< Indicates If the ADC is Near Overrange */
+ uint16_t Sensor_UnderRange : 1; /**< Indicates If the Sensor is Underrange */
+ uint16_t Sensor_OverRange : 1; /**< Indicates If the Sensor is Overrange */
+ uint16_t CJ_Soft_Fault : 1; /**< Cold Junction Soft Fault */
+ uint16_t CJ_Hard_Fault : 1; /**< Cold Junction Hard Fault */
+ uint16_t ADC_Input_OverRange : 1; /**< Indicates the ADC Input is Overrange */
+ uint16_t Sensor_HardFault : 1; /**< Indicates Sensor Hard Fault */
+ uint16_t reserved8 : 8;
};
uint16_t VALUE16;
};
@@ -770,39 +702,19 @@
/*@}*/
-/** @defgroup Alert_Code Code Indicating Source of Alert (Alert_Code) Register
- * Code Indicating Source of Alert (Alert_Code) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Alert_Code_Struct
- *! \brief Code Indicating Source of Alert Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Alert_Code_t {
- union {
- struct {
- uint16_t Alert_Code : 16; /**< Code Indicating Type of Alert */
- };
- uint16_t VALUE16;
- };
-} ADMW_CORE_Alert_Code_t;
-
-/*@}*/
-
-/** @defgroup External_Reference_Resistor External Reference Information (External_Reference_Resistor) Register
- * External Reference Information (External_Reference_Resistor) Register.
+/** @defgroup External_Reference_Resistor External Reference Resistor Value (External_Reference_Resistor) Register
+ * External Reference Resistor Value (External_Reference_Resistor) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_External_Reference_Resistor_Struct
- *! \brief External Reference Information Register bit field structure
+ *! \brief External Reference Resistor Value Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_External_Reference_Resistor_t {
union {
struct {
- float Ext_Refin1_Value; /**< Refin1 Value */
+ float Ext_Refin1_Value; /**< External Reference Resistor Value */
};
float VALUE32;
};
@@ -810,26 +722,6 @@
/*@}*/
-/** @defgroup External_Voltage_Reference External Reference Information (External_Voltage_Reference) Register
- * External Reference Information (External_Voltage_Reference) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_External_Voltage_Reference_Struct
- *! \brief External Reference Information Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_External_Voltage_Reference_t {
- union {
- struct {
- float Ext_Refin2_Value; /**< Refin2 Value */
- };
- float VALUE32;
- };
-} ADMW_CORE_External_Voltage_Reference_t;
-
-/*@}*/
-
/** @defgroup Diagnostics_Control Diagnostic Control (Diagnostics_Control) Register
* Diagnostic Control (Diagnostics_Control) Register.
* @{
@@ -841,10 +733,10 @@
* ========================================================================= */
typedef enum
{
- CORE_DIAGNOSTICS_CONTROL_OCD_OFF = 0, /**< No Open-Circuit Detection During Measurement */
- CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE = 1, /**< Open-Circuit Detection Performed Once Per Measurement Cycle */
- CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES = 2, /**< Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */
- CORE_DIAGNOSTICS_CONTROL_OCD_PER_1000_CYCLES = 3 /**< Open-Circuit Detection Performed Once Per Thousand Measurement Cycles */
+ CORE_DIAGNOSTICS_CONTROL_OCD_OFF = 0, /**< No Open-Circuit Detection During Measurement */
+ CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE = 1, /**< Open-Circuit Detection Performed Once Per Measurement Cycle */
+ CORE_DIAGNOSTICS_CONTROL_OCD_PER_10_CYCLES = 2, /**< Open-Circuit Detection Performed Once Per Ten Measurement Cycles */
+ CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES = 3 /**< Open-Circuit Detection Performed Once Per Hundred Measurement Cycles */
} ADMW_CORE_Diagnostics_Control_Diag_OSD_Freq;
@@ -855,12 +747,11 @@
typedef struct _ADMW_CORE_Diagnostics_Control_t {
union {
struct {
- uint16_t Diag_Global_En : 1; /**< Diagnostics Global Enable */
- uint16_t Diag_Meas_En : 1; /**< Diagnostics Measure Enable */
- uint16_t Diag_OSD_Freq : 2; /**< Diagnostics Open Sensor Detect Frequency */
- uint16_t reserved4 : 12;
+ uint8_t Diag_Meas_En : 1; /**< Diagnostics Measure Enable */
+ uint8_t Diag_OSD_Freq : 2; /**< Diagnostics Open Sensor Detect Frequency */
+ uint8_t reserved3 : 5;
};
- uint16_t VALUE16;
+ uint8_t VALUE8;
};
} ADMW_CORE_Diagnostics_Control_t;
@@ -878,7 +769,7 @@
typedef struct _ADMW_CORE_Data_FIFO_t {
union {
struct {
- uint8_t Data_Fifo : 8; /**< Fifo Buffer of Sensor Results */
+ uint8_t Data_Fifo : 8; /**< FIFO Buffer of Sensor Results */
};
uint8_t VALUE8;
};
@@ -906,28 +797,28 @@
/*@}*/
-/** @defgroup Advanced_Sensor_Access Enables Access to Advanced Sensor Configuration (Advanced_Sensor_Access) Register
- * Enables Access to Advanced Sensor Configuration (Advanced_Sensor_Access) Register.
+/** @defgroup Test_Reg_Access Allows Access to Test (Hidden) Registers and Features (Test_Reg_Access) Register
+ * Allows Access to Test (Hidden) Registers and Features (Test_Reg_Access) Register.
* @{
*/
/* ==========================================================================
- *! \struct ADMW_CORE_Advanced_Sensor_Access_Struct
- *! \brief Enables Access to Advanced Sensor Configuration Register bit field structure
+ *! \struct ADMW_CORE_Test_Reg_Access_Struct
+ *! \brief Allows Access to Test (Hidden) Registers and Features Register bit field structure
* ========================================================================== */
-typedef struct _ADMW_CORE_Advanced_Sensor_Access_t {
+typedef struct _ADMW_CORE_Test_Reg_Access_t {
union {
struct {
- uint16_t Advanced_Sensor_Access : 16; /**< Write Specific Key Value to Access Advanced Sensors */
+ uint16_t Test_Access : 16; /**< Test Register Access. Specific Write Sequence Required */
};
uint16_t VALUE16;
};
-} ADMW_CORE_Advanced_Sensor_Access_t;
+} ADMW_CORE_Test_Reg_Access_t;
/*@}*/
-/** @defgroup LUT_Select Read/Write Strobe (LUT_Select) Register
- * Read/Write Strobe (LUT_Select) Register.
+/** @defgroup LUT_Select LUT Read/Write Strobe (LUT_Select) Register
+ * LUT Read/Write Strobe (LUT_Select) Register.
* @{
*/
@@ -937,14 +828,14 @@
* ========================================================================= */
typedef enum
{
- CORE_LUT_SELECT_LUT_READ = 0, /**< Read Addressed LUT Data */
- CORE_LUT_SELECT_LUT_WRITE = 1 /**< Write Addressed LUT Data */
+ CORE_LUT_SELECT_LUT_READ = 0, /**< Read addressed LUT data */
+ CORE_LUT_SELECT_LUT_WRITE = 1 /**< Write addressed LUT data */
} ADMW_CORE_LUT_Select_LUT_RW;
/* ==========================================================================
*! \struct ADMW_CORE_LUT_Select_Struct
- *! \brief Read/Write Strobe Register bit field structure
+ *! \brief LUT Read/Write Strobe Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_LUT_Select_t {
union {
@@ -970,7 +861,7 @@
typedef struct _ADMW_CORE_LUT_Offset_t {
union {
struct {
- uint16_t LUT_Offset : 14; /**< Offset into Look-Up-Table */
+ uint16_t LUT_Offset : 14; /**< Offset into the Lookup Table */
uint16_t reserved14 : 2;
};
uint16_t VALUE16;
@@ -991,7 +882,7 @@
typedef struct _ADMW_CORE_LUT_Data_t {
union {
struct {
- uint8_t LUT_Data : 8; /**< Data Byte to Write to / Read from Look-Up-Table */
+ uint8_t LUT_Data : 8; /**< Data Byte to Write to and Read from the Lookup Table */
};
uint8_t VALUE8;
};
@@ -1033,7 +924,7 @@
typedef struct _ADMW_CORE_Channel_Count_t {
union {
struct {
- uint8_t Channel_Count : 7; /**< How Many Times Channel Should Appear in One Cycle */
+ uint8_t Channel_Count : 7; /**< How Many Times Channel Appears in One Cycle */
uint8_t Channel_Enable : 1; /**< Enable Channel in Measurement Cycle */
};
uint8_t VALUE8;
@@ -1042,14 +933,14 @@
/*@}*/
-/** @defgroup Channel_Options Position of Channel Within Sequence and Enable for FFT (Channel_Options) Register
- * Position of Channel Within Sequence and Enable for FFT (Channel_Options) Register.
+/** @defgroup Channel_Options Position of Channel Within Sequence (Channel_Options) Register
+ * Position of Channel Within Sequence (Channel_Options) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Channel_Options_Struct
- *! \brief Position of Channel Within Sequence and Enable for FFT Register bit field structure
+ *! \brief Position of Channel Within Sequence Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Channel_Options_t {
union {
@@ -1074,35 +965,20 @@
* ========================================================================= */
typedef enum
{
- CORE_SENSOR_TYPE_THERMOCOUPLE_T = 0, /**< Thermocouple T-Type Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_THERMOCOUPLE_J = 1, /**< Thermocouple J-Type Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_THERMOCOUPLE_K = 2, /**< Thermocouple K-Type Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_RTD_2W_PT100 = 32, /**< RTD 2 Wire PT100 Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_RTD_2W_PT1000 = 33, /**< RTD 2 Wire PT1000 Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_RTD_3W_PT100 = 64, /**< RTD 3 Wire PT100 Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_RTD_3W_PT1000 = 65, /**< RTD 3 Wire PT1000 Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_RTD_4W_PT100 = 96, /**< RTD 4 Wire PT100 Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_RTD_4W_PT1000 = 97, /**< RTD 4 Wire PT1000 Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_THERMISTOR_A_10K = 128, /**< Thermistor Type A 10kOhm Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_THERMISTOR_B_10K = 129, /**< Thermistor Type B 10kOhm Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_BRIDGE_4W_2 = 169, /**< Bridge 4 Wire Sensor 2 Defined Level 2 */
- CORE_SENSOR_TYPE_BRIDGE_6W_1 = 200, /**< Bridge 6 Wire Sensor 1 Defined Level 2 */
- CORE_SENSOR_TYPE_BRIDGE_6W_2 = 201, /**< Bridge 6 Wire Sensor 2 Defined Level 2 */
- CORE_SENSOR_TYPE_DIODE_2C_TYPEA = 224, /**< Diode 2 Current Type A Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_DIODE_3C_TYPEA = 225, /**< Diode 3 Current Type A Sensor Defined Level 1 */
- CORE_SENSOR_TYPE_DIODE_2C_1 = 232, /**< Diode 2 Current Sensor 1 Defined Level 2 */
- CORE_SENSOR_TYPE_DIODE_3C_1 = 233, /**< Diode 3 Current Sensor 1 Defined Level 2 */
- CORE_SENSOR_TYPE_VOLTAGE = 512, /**< Voltage Input */
- CORE_SENSOR_TYPE_VOLTAGE_PRESSURE_A = 544, /**< Voltage Output Pressure Sensor A Defined Level 1 */
- CORE_SENSOR_TYPE_VOLTAGE_PRESSURE_B = 545, /**< Voltage Output Pressure Sensor B Defined Level 1 */
- CORE_SENSOR_TYPE_CURRENT = 768, /**< Current Input */
- CORE_SENSOR_TYPE_I2C_PRESSURE_A = 2048, /**< I2C Pressure Sensor A Defined Level 1 */
- CORE_SENSOR_TYPE_I2C_PRESSURE_B = 2049, /**< I2C Pressure Sensor B Defined Level 1 */
- CORE_SENSOR_TYPE_I2C_HUMIDITY_A = 2112, /**< I2C Humidity Sensor A Defined Level 1 */
- CORE_SENSOR_TYPE_I2C_HUMIDITY_B = 2113, /**< I2C Humidity Sensor B Defined Level 1 */
- CORE_SENSOR_TYPE_SPI_ACCELEROMETER_A = 3200, /**< SPI Accelerometer Sensor A 3-Axis Defined Level 1 */
- CORE_SENSOR_TYPE_SPI_ACCELEROMETER_B = 3201, /**< SPI Accelerometer Sensor B 3-Axis Defined Level 1 */
- CORE_SENSOR_TYPE_CO2_A_DEF = 3584 /**< CO2 Sensor A Defined Level 1 */
+ CORE_SENSOR_TYPE_THERMOCOUPLE_T = 0, /**< Thermocouple T-Type sensor */
+ CORE_SENSOR_TYPE_THERMOCOUPLE_J = 1, /**< Thermocouple J-Type Sensor */
+ CORE_SENSOR_TYPE_THERMOCOUPLE_K = 2, /**< Thermocouple K-Type Sensor */
+ CORE_SENSOR_TYPE_RTD_2W_PT100 = 32, /**< RTD 2 wire PT100 sensor */
+ CORE_SENSOR_TYPE_RTD_2W_PT1000 = 33, /**< RTD 2 wire PT1000 sensor */
+ CORE_SENSOR_TYPE_RTD_3W_PT100 = 64, /**< RTD 3 wire PT100 sensor */
+ CORE_SENSOR_TYPE_RTD_3W_PT1000 = 65, /**< RTD 3 wire PT1000 sensor */
+ CORE_SENSOR_TYPE_RTD_4W_PT100 = 96, /**< RTD 4 wire PT100 sensor */
+ CORE_SENSOR_TYPE_RTD_4W_PT1000 = 97, /**< RTD 4 wire PT1000 sensor */
+ CORE_SENSOR_TYPE_BRIDGE_4W = 169, /**< Bridge 4 wire sensor */
+ CORE_SENSOR_TYPE_CUSTOM1 = 1024, /**< Custom1 */
+ CORE_SENSOR_TYPE_I2C_HUMIDITY_B = 2113, /**< I2C humidity sensor B */
+ CORE_SENSOR_TYPE_SENSOR_RESERVED_1 = 4064, /**< RESERVED. NOT TO BE USED */
+ CORE_SENSOR_TYPE_SENSOR_RESERVED_2 = 4095 /**< RESERVED. NOT TO BE USED */
} ADMW_CORE_Sensor_Type_Sensor_Type;
@@ -1146,9 +1022,9 @@
* ========================================================================= */
typedef enum
{
- CORE_SENSOR_DETAILS_LUT_DEFAULT = 0, /**< Default Lookup Table for Selected Sensor Type */
- CORE_SENSOR_DETAILS_LUT_UNITY = 1, /**< Unity Lookup Table. 1:1 Mapping From Input to Output */
- CORE_SENSOR_DETAILS_LUT_CUSTOM = 2, /**< User Defined Custom Lookup Table. */
+ CORE_SENSOR_DETAILS_LUT_DEFAULT = 0, /**< Default lookup table for selected sensor type */
+ CORE_SENSOR_DETAILS_LUT_UNITY = 1, /**< Unity lookup table. 1:1 mapping from input to output */
+ CORE_SENSOR_DETAILS_LUT_CUSTOM = 2, /**< User defined custom lookup table. */
CORE_SENSOR_DETAILS_LUT_RESERVED = 3 /**< Reserved */
} ADMW_CORE_Sensor_Details_LUT_Select;
@@ -1159,11 +1035,9 @@
* ========================================================================= */
typedef enum
{
- CORE_SENSOR_DETAILS_REF_VINT = 0, /**< Internal voltage reference (1.2V) */
- CORE_SENSOR_DETAILS_REF_VEXT1 = 1, /**< External Voltage reference applied to VERF+ and VREF- */
- CORE_SENSOR_DETAILS_REF_VRESERVED = 2, /**< ExReserved for future use. */
- CORE_SENSOR_DETAILS_REF_AVDD = 3, /**< AVDD Supply Used as Excitation and Internally applied as Reference */
- CORE_SENSOR_DETAILS_REF_NUM /**< Number of reference options. */
+ CORE_SENSOR_DETAILS_REF_VINT = 0, /**< Internal voltage reference (1.2V) */
+ CORE_SENSOR_DETAILS_REF_VEXT1 = 1, /**< External voltage reference applied to VERF+ and VREF- */
+ CORE_SENSOR_DETAILS_REF_AVDD = 3 /**< AVDD supply internally used as reference */
} ADMW_CORE_Sensor_Details_Reference_Select;
@@ -1186,14 +1060,14 @@
/* =========================================================================
*! \enum ADMW_CORE_Sensor_Details_RTD_Curve
- *! \brief Select RTD Curve for Linearisation (RTD_Curve) Enumerations
+ *! \brief Select RTD Curve for Linearization (RTD_Curve) Enumerations
* ========================================================================= */
typedef enum
{
- CORE_SENSOR_DETAILS_EUROPEAN_CURVE = 0, /**< European Curve */
- CORE_SENSOR_DETAILS_AMERICAN_CURVE = 1, /**< American Curve */
- CORE_SENSOR_DETAILS_JAPANESE_CURVE = 2, /**< Japanese Curve */
- CORE_SENSOR_DETAILS_ITS90_CURVE = 3 /**< ITS-90 Curve */
+ CORE_SENSOR_DETAILS_EUROPEAN_CURVE = 0, /**< European curve */
+ CORE_SENSOR_DETAILS_AMERICAN_CURVE = 1, /**< American curve */
+ CORE_SENSOR_DETAILS_JAPANESE_CURVE = 2, /**< Japanese curve */
+ CORE_SENSOR_DETAILS_ITS90_CURVE = 3 /**< ITS-90 curve */
} ADMW_CORE_Sensor_Details_RTD_Curve;
@@ -1205,16 +1079,16 @@
union {
struct {
uint32_t Measurement_Units : 4; /**< Units of Sensor Measurement */
- uint32_t Compensation_Channel : 4; /**< Indicates Which Channel is Used to Compensate Sensor Result */
+ uint32_t Compensation_Channel : 4; /**< Indicates Which Channel Used to Compensate the Sensor Result */
uint32_t reserved8 : 7;
uint32_t LUT_Select : 2; /**< Lookup Table Select */
uint32_t Do_Not_Publish : 1; /**< Do Not Publish Channel Result */
uint32_t reserved18 : 2;
uint32_t Reference_Select : 4; /**< Reference Selection */
uint32_t PGA_Gain : 3; /**< PGA Gain */
- uint32_t RTD_Curve : 2; /**< Select RTD Curve for Linearisation */
+ uint32_t RTD_Curve : 2; /**< Select RTD Curve for Linearization */
uint32_t reserved29 : 2;
- uint32_t Compensation_Disable : 1; /**< Indicates Compensation Data Should Not Be Used */
+ uint32_t Compensation_Disable : 1; /**< This Bit Indicates Compensation Data Must Not Be Used */
};
uint32_t VALUE32;
};
@@ -1233,36 +1107,19 @@
* ========================================================================= */
typedef enum
{
- CORE_CHANNEL_EXCITATION_NONE =-1, /**< No External urrent Source */
- CORE_CHANNEL_EXCITATION_EXTERNAL = 0, /**< External Current Sourced */
- CORE_CHANNEL_EXCITATION_RESERVED = 1, /**< Reserved */
- CORE_CHANNEL_EXCITATION_IEXC_10UA = 2, /**< 10 \mu;A */
- CORE_CHANNEL_EXCITATION_RESERVED2 = 3, /**< Reserved */
- CORE_CHANNEL_EXCITATION_IEXC_50UA = 4, /**< 50 \mu;A */
- CORE_CHANNEL_EXCITATION_IEXC_100UA = 5, /**< 100 \mu;A */
- CORE_CHANNEL_EXCITATION_IEXC_250UA = 6, /**< 250 \mu;A */
- CORE_CHANNEL_EXCITATION_IEXC_500UA = 7, /**< 500 \mu;A */
- CORE_CHANNEL_EXCITATION_IEXC_1000UA = 8 /**< 1000 \mu;A */
+ CORE_CHANNEL_EXCITATION_NONE = 0, /**< Excitation Current Disabled */
+ CORE_CHANNEL_EXCITATION_RESERVED = 1, /**< Reserved */
+ CORE_CHANNEL_EXCITATION_IEXC_10UA = 2, /**< 10 \mu;A */
+ CORE_CHANNEL_EXCITATION_RESERVED2 = 3, /**< Reserved */
+ CORE_CHANNEL_EXCITATION_IEXC_50UA = 4, /**< 50 \mu;A */
+ CORE_CHANNEL_EXCITATION_IEXC_100UA = 5, /**< 100 \mu;A */
+ CORE_CHANNEL_EXCITATION_IEXC_250UA = 6, /**< 250 \mu;A */
+ CORE_CHANNEL_EXCITATION_IEXC_500UA = 7, /**< 500 \mu;A */
+ CORE_CHANNEL_EXCITATION_IEXC_1000UA = 8, /**< 1000 \mu;A */
+ CORE_CHANNEL_EXCITATION_EXTERNAL = 15 /**< External current sourced */
} ADMW_CORE_Channel_Excitation_IOUT_Excitation_Current;
-/* =========================================================================
- *! \enum ADMW_CORE_Channel_Excitation_IOUT_Diode_Ratio
- *! \brief Modify Current Ratios Used for Diode Sensor (IOUT_Diode_Ratio) Enumerations
- * ========================================================================= */
-typedef enum
-{
- CORE_CHANNEL_EXCITATION_DIODE_2PT_10UA_100UA = 0, /**< 2 Current measurement 10uA 100uA */
- CORE_CHANNEL_EXCITATION_DIODE_2PT_20UA_160UA = 1, /**< 2 Current measurement 20uA 160uA */
- CORE_CHANNEL_EXCITATION_DIODE_2PT_50UA_300UA = 2, /**< 2 Current measurement 50uA 300uA */
- CORE_CHANNEL_EXCITATION_DIODE_2PT_100UA_600UA = 3, /**< 2 Current measurement 100uA 600uA */
- CORE_CHANNEL_EXCITATION_DIODE_3PT_10UA_50UA_100UA = 4, /**< 3 current measuremet 10uA 50uA 100uA */
- CORE_CHANNEL_EXCITATION_DIODE_3PT_20UA_100UA_160UA = 5, /**< 3 current measuremet 20uA 100uA 160uA */
- CORE_CHANNEL_EXCITATION_DIODE_3PT_50UA_150UA_300UA = 6, /**< 3 current measuremet 50uA 150uA 300uA */
- CORE_CHANNEL_EXCITATION_DIODE_3PT_100UA_300UA_600UA = 7 /**< 3 current measuremet 100uA 300uA 600uA */
-} ADMW_CORE_Channel_Excitation_IOUT_Diode_Ratio;
-
-
/* ==========================================================================
*! \struct ADMW_CORE_Channel_Excitation_Struct
*! \brief Excitation Current Register bit field structure
@@ -1271,9 +1128,7 @@
union {
struct {
uint16_t IOUT_Excitation_Current : 4; /**< Current Source Value */
- uint16_t reserved4 : 2;
- uint16_t IOUT_Diode_Ratio : 3; /**< Modify Current Ratios Used for Diode Sensor */
- uint16_t reserved9 : 7;
+ uint16_t reserved4 : 12;
};
uint16_t VALUE16;
};
@@ -1292,9 +1147,10 @@
* ========================================================================= */
typedef enum
{
- CORE_SETTLING_TIME_MICROSECONDS = 0, /**< Micro-Seconds */
- CORE_SETTLING_TIME_MILLISECONDS = 1, /**< Milli-Seconds */
- CORE_SETTLING_TIME_SECONDS = 2 /**< Seconds */
+ CORE_SETTLING_TIME_MICROSECONDS = 0, /**< Micro-seconds */
+ CORE_SETTLING_TIME_MILLISECONDS = 1, /**< Milli-seconds */
+ CORE_SETTLING_TIME_SECONDS = 2, /**< Seconds */
+ CORE_SETTLING_TIME_UNDEFINED = 3 /**< Undefined */
} ADMW_CORE_Settling_Time_Settling_Time_Units;
@@ -1314,36 +1170,25 @@
/*@}*/
-/** @defgroup Measurement_Setup ADC Digital Filter Selection (Measurement_Setup) Register
- * ADC Digital Filter Selection (Measurement_Setup) Register.
+/** @defgroup Measurement_Setup ADC Measurement Setup (Measurement_Setup) Register
+ * ADC Measurement Setup (Measurement_Setup) Register.
* @{
*/
/* =========================================================================
- *! \enum ADMW_CORE_Measurement_Setup_Custom_Calibration
- *! \brief Enables Custom Calibration for Selected Sensor (Custom_Calibration) Enumerations
- * ========================================================================= */
-typedef enum
-{
- CORE_MEASUREMENT_SETUP_INTERNAL_CALIBRATION = 0, /**< */
- CORE_MEASUREMENT_SETUP_CUSTOM_CALIBRATION = 1 /**< */
-} ADMW_CORE_Measurement_Setup_Custom_Calibration;
-
-
-/* =========================================================================
*! \enum ADMW_CORE_Measurement_Setup_NOTCH_EN_2
*! \brief Enable Notch 2 Filter Mode (NOTCH_EN_2) Enumerations
* ========================================================================= */
typedef enum
{
- CORE_MEASUREMENT_SETUP_NOTCH_DIS = 0, /**< Disable Notch Filter */
- CORE_MEASUREMENT_SETUP_NOTCH_EN = 1 /**< Enable Notch 2 Filter option. Places a addtional notch at 1.2X ODR. Can be used for 50 and 60Hz rejection simultaneously */
+ CORE_MEASUREMENT_SETUP_NOTCH_DIS = 0, /**< Disable notch filter */
+ CORE_MEASUREMENT_SETUP_NOTCH_EN = 1 /**< Enable notch 2 filter option. */
} ADMW_CORE_Measurement_Setup_NOTCH_EN_2;
/* =========================================================================
*! \enum ADMW_CORE_Measurement_Setup_PST_MEAS_EXC_CTRL
- *! \brief Disabled Current Sources After Measurement Has Been Complete (PST_MEAS_EXC_CTRL) Enumerations
+ *! \brief Disable Current Sources After Measurement Completes (PST_MEAS_EXC_CTRL) Enumerations
* ========================================================================= */
typedef enum
{
@@ -1358,10 +1203,10 @@
* ========================================================================= */
typedef enum
{
- CORE_MEASUREMENT_SETUP_DISABLE_CHOP = 0, /**< Chop Mode Disabled */
- CORE_MEASUREMENT_SETUP_HW_CHOP = 1, /**< Chop Mode Enabled */
- CORE_MEASUREMENT_SETUP_ENABLE_CHOP = 2, /**< Chop Mode Enabled */
- CORE_MEASUREMENT_SETUP_HW_SW_CHOP = 3 /**< Chop Mode Enabled */
+ CORE_MEASUREMENT_SETUP_DISABLE_CHOP = 0, /**< ADC front end chopping disabled */
+ CORE_MEASUREMENT_SETUP_HW_CHOP = 1, /**< Hardware chopping enabled */
+ CORE_MEASUREMENT_SETUP_SW_CHOP = 2, /**< SW chop enabled */
+ CORE_MEASUREMENT_SETUP_HW_SW_CHOP = 3 /**< Hardware and software chop enabled */
} ADMW_CORE_Measurement_Setup_Chop_Mode;
@@ -1371,19 +1216,19 @@
* ========================================================================= */
typedef enum
{
- CORE_MEASUREMENT_SETUP_ENABLE_SINC4 = 0, /**< Enabled SINC4 Filter */
- CORE_MEASUREMENT_SETUP_ENABLE_SINC3 = 1 /**< Enabled SINC3 Filter */
+ CORE_MEASUREMENT_SETUP_ENABLE_SINC4 = 0, /**< Enabled SINC4 filter */
+ CORE_MEASUREMENT_SETUP_ENABLE_SINC3 = 1 /**< Enabled SINC3 filter */
} ADMW_CORE_Measurement_Setup_ADC_Filter_Type;
/* =========================================================================
*! \enum ADMW_CORE_Measurement_Setup_GND_SW
- *! \brief GND_SW (GND_SW) Enumerations
+ *! \brief Ground Switch Selection (GND_SW) Enumerations
* ========================================================================= */
typedef enum
{
- CORE_MEASUREMENT_SETUP_GND_SW_OPEN = 0, /**< GND_SW Open. The GND SW is not enabled for the sensor measurement */
- CORE_MEASUREMENT_SETUP_GND_SW_CLOSED = 1 /**< GND_SW Closed. The GND SW is enabled for the sensor measurement, bit wiil Remain Closed After the Measurement */
+ CORE_MEASUREMENT_SETUP_GND_SW_OPEN = 0, /**< GND_SW Open. The ground switch is not enabled for the sensor measurement */
+ CORE_MEASUREMENT_SETUP_GND_SW_CLOSED = 1 /**< GND_SW Closed. The ground switch is enabled for the sensor measurement, bit wiil Remain Closed After the Measurement */
} ADMW_CORE_Measurement_Setup_GND_SW;
@@ -1393,27 +1238,27 @@
* ========================================================================= */
typedef enum
{
- CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED = 0, /**< */
- CORE_MEASUREMENT_SETUP_BUFFERS_DISABLED = 1 /**< */
+ CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED = 0, /**< Input buffers enabled */
+ CORE_MEASUREMENT_SETUP_BUFFERS_DISABLED = 1 /**< Input buffers disabled */
} ADMW_CORE_Measurement_Setup_Buffer_Bypass;
/* ==========================================================================
*! \struct ADMW_CORE_Measurement_Setup_Struct
- *! \brief ADC Digital Filter Selection Register bit field structure
+ *! \brief ADC Measurement Setup Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Measurement_Setup_t {
union {
struct {
- uint32_t ADC_SF : 7; /**< ADC Digital Filter Select */
- uint32_t Custom_Calibration : 1; /**< Enables Custom Calibration for Selected Sensor */
- uint32_t NOTCH_EN_2 : 1; /**< Enable Notch 2 Filter Mode */
- uint32_t PST_MEAS_EXC_CTRL : 1; /**< Disabled Current Sources After Measurement Has Been Complete */
- uint32_t Chop_Mode : 2; /**< Enabled and Disable Chop Mode */
- uint32_t ADC_Filter_Type : 1; /**< ADC Digital Filter Type */
- uint32_t GND_SW : 2; /**< GND_SW */
- uint32_t Buffer_Bypass : 1; /**< Disable Buffers */
- uint32_t reserved16 : 16;
+ uint32_t ADC_SF : 7; /**< ADC Digital Filter Speed */
+ uint32_t reserved7 : 1;
+ uint32_t NOTCH_EN_2 : 1; /**< Enable Notch 2 Filter Mode */
+ uint32_t PST_MEAS_EXC_CTRL : 1; /**< Disable Current Sources After Measurement Completes */
+ uint32_t Chop_Mode : 2; /**< Enabled and Disable Chop Mode */
+ uint32_t ADC_Filter_Type : 1; /**< ADC Digital Filter Type */
+ uint32_t GND_SW : 2; /**< Ground Switch Selection */
+ uint32_t Buffer_Bypass : 1; /**< Disable Buffers */
+ uint32_t reserved16 : 16;
};
uint32_t VALUE32;
};
@@ -1501,26 +1346,6 @@
/*@}*/
-/** @defgroup Alert_Code_Ch Per-Channel Detailed Alert-Code Information (Alert_Code_Ch) Register
- * Per-Channel Detailed Alert-Code Information (Alert_Code_Ch) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Alert_Code_Ch_Struct
- *! \brief Per-Channel Detailed Alert-Code Information Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Alert_Code_Ch_t {
- union {
- struct {
- uint16_t Alert_Code_Ch : 16; /**< Per-Channel Code Indicating Type of Alert */
- };
- uint16_t VALUE16;
- };
-} ADMW_CORE_Alert_Code_Ch_t;
-
-/*@}*/
-
/** @defgroup Channel_Skip Indicates If Channel Will Skip Some Measurement Cycles (Channel_Skip) Register
* Indicates If Channel Will Skip Some Measurement Cycles (Channel_Skip) Register.
* @{
@@ -1542,48 +1367,6 @@
/*@}*/
-/** @defgroup Sensor_Parameter Sensor Parameter Adjustment (Sensor_Parameter) Register
- * Sensor Parameter Adjustment (Sensor_Parameter) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Sensor_Parameter_Struct
- *! \brief Sensor Parameter Adjustment Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Sensor_Parameter_t {
- union {
- struct {
- float Sensor_Parameter; /**< Sensor Parameter Adjustment */
- };
- float VALUE32;
- };
-} ADMW_CORE_Sensor_Parameter_t;
-
-/*@}*/
-
-/** @defgroup Calibration_Parameter Calibration Parameter Value (Calibration_Parameter) Register
- * Calibration Parameter Value (Calibration_Parameter) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Calibration_Parameter_Struct
- *! \brief Calibration Parameter Value Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Calibration_Parameter_t {
- union {
- struct {
- uint32_t Calibration_Parameter : 24; /**< Calibration Parameter Value */
- uint32_t Calibration_Parameter_Enable : 1; /**< Enables Use of Calibration_Parameter */
- uint32_t reserved25 : 7;
- };
- uint32_t VALUE32;
- };
-} ADMW_CORE_Calibration_Parameter_t;
-
-/*@}*/
-
/** @defgroup Digital_Sensor_Config Digital Sensor Data Coding (Digital_Sensor_Config) Register
* Digital Sensor Data Coding (Digital_Sensor_Config) Register.
* @{
@@ -1597,8 +1380,8 @@
{
CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE = 0, /**< None/Invalid */
CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR = 1, /**< Unipolar */
- CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL = 2, /**< Twos Complement */
- CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY = 3 /**< Offset Binary */
+ CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL = 2, /**< Twos complement */
+ CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY = 3 /**< Offset binary */
} ADMW_CORE_Digital_Sensor_Config_Digital_Sensor_Coding;
@@ -1642,29 +1425,6 @@
/*@}*/
-/** @defgroup Digital_Sensor_Num_Cmds Number of Configuration, Read Commands for Digital Sensors (Digital_Sensor_Num_Cmds) Register
- * Number of Configuration, Read Commands for Digital Sensors (Digital_Sensor_Num_Cmds) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Num_Cmds_Struct
- *! \brief Number of Configuration, Read Commands for Digital Sensors Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Num_Cmds_t {
- union {
- struct {
- uint8_t Digital_Sensor_Num_Cfg_Cmds : 3; /**< Number of Configuration Commands for Digital Sensor */
- uint8_t reserved3 : 1;
- uint8_t Digital_Sensor_Num_Read_Cmds : 3; /**< Number of Read Commands for Digital Sensor */
- uint8_t reserved7 : 1;
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Num_Cmds_t;
-
-/*@}*/
-
/** @defgroup Digital_Sensor_Comms Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register
* Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register.
* @{
@@ -1672,12 +1432,12 @@
/* =========================================================================
*! \enum ADMW_CORE_Digital_Sensor_Comms_Digital_Sensor_Comms_En
- *! \brief Enable Digital Sensor Comms Register Parameters (Digital_Sensor_Comms_En) Enumerations
+ *! \brief Enable Digital Sensor Communications Register Parameters (Digital_Sensor_Comms_En) Enumerations
* ========================================================================= */
typedef enum
{
- CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT = 0, /**< Default Parameters Used for Digital Sensor Communications */
- CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER = 1 /**< User Supplied Parameters Used for Digital Sensor Communications */
+ CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_DEFAULT = 0, /**< Default parameters used for digital sensor communications */
+ CORE_DIGITAL_SENSOR_COMMS_DIGITAL_COMMS_USER = 1 /**< User supplied parameters used for digital sensor communications */
} ADMW_CORE_Digital_Sensor_Comms_Digital_Sensor_Comms_En;
@@ -1725,10 +1485,10 @@
* ========================================================================= */
typedef enum
{
- CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 = 0, /**< Clock Polarity = 0 Clock Phase = 0 */
- CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 = 1, /**< Clock Polarity = 0 Clock Phase = 1 */
- CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 = 2, /**< Clock Polarity = 1 Clock Phase = 0 */
- CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 = 3 /**< Clock Polarity = 1 Clock Phase = 1 */
+ CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 = 0, /**< Clock polarity = 0 Clock phase = 0 */
+ CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 = 1, /**< Clock polarity = 0 Clock phase = 1 */
+ CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 = 2, /**< Clock polarity = 1 Clock phase = 0 */
+ CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 = 3 /**< Clock polarity = 1 Clock phase = 1 */
} ADMW_CORE_Digital_Sensor_Comms_SPI_Mode;
@@ -1739,7 +1499,7 @@
typedef struct _ADMW_CORE_Digital_Sensor_Comms_t {
union {
struct {
- uint16_t Digital_Sensor_Comms_En : 1; /**< Enable Digital Sensor Comms Register Parameters */
+ uint16_t Digital_Sensor_Comms_En : 1; /**< Enable Digital Sensor Communications Register Parameters */
uint16_t SPI_Clock : 4; /**< Controls Clock Frequency for SPI Sensors */
uint16_t I2C_Clock : 2; /**< Controls SCLK Frequency for I2C Sensors */
uint16_t reserved7 : 3;
@@ -1752,286 +1512,6 @@
/*@}*/
-/** @defgroup Digital_Sensor_Command1 Sensor Configuration Command1 (Digital_Sensor_Command1) Register
- * Sensor Configuration Command1 (Digital_Sensor_Command1) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Command1_Struct
- *! \brief Sensor Configuration Command1 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Command1_t {
- union {
- struct {
- uint8_t Digital_Sensor_Command1 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Command1_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Command2 Sensor Configuration Command2 (Digital_Sensor_Command2) Register
- * Sensor Configuration Command2 (Digital_Sensor_Command2) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Command2_Struct
- *! \brief Sensor Configuration Command2 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Command2_t {
- union {
- struct {
- uint8_t Digital_Sensor_Command2 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Command2_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Command3 Sensor Configuration Command3 (Digital_Sensor_Command3) Register
- * Sensor Configuration Command3 (Digital_Sensor_Command3) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Command3_Struct
- *! \brief Sensor Configuration Command3 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Command3_t {
- union {
- struct {
- uint8_t Digital_Sensor_Command3 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Command3_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Command4 Sensor Configuration Command4 (Digital_Sensor_Command4) Register
- * Sensor Configuration Command4 (Digital_Sensor_Command4) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Command4_Struct
- *! \brief Sensor Configuration Command4 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Command4_t {
- union {
- struct {
- uint8_t Digital_Sensor_Command4 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Command4_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Command5 Sensor Configuration Command5 (Digital_Sensor_Command5) Register
- * Sensor Configuration Command5 (Digital_Sensor_Command5) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Command5_Struct
- *! \brief Sensor Configuration Command5 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Command5_t {
- union {
- struct {
- uint8_t Digital_Sensor_Command5 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Command5_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Command6 Sensor Configuration Command6 (Digital_Sensor_Command6) Register
- * Sensor Configuration Command6 (Digital_Sensor_Command6) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Command6_Struct
- *! \brief Sensor Configuration Command6 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Command6_t {
- union {
- struct {
- uint8_t Digital_Sensor_Command6 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Command6_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Command7 Sensor Configuration Command7 (Digital_Sensor_Command7) Register
- * Sensor Configuration Command7 (Digital_Sensor_Command7) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Command7_Struct
- *! \brief Sensor Configuration Command7 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Command7_t {
- union {
- struct {
- uint8_t Digital_Sensor_Command7 : 8; /**< Configuration Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Command7_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Read_Cmd1 Sensor Read Command1 (Digital_Sensor_Read_Cmd1) Register
- * Sensor Read Command1 (Digital_Sensor_Read_Cmd1) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Read_Cmd1_Struct
- *! \brief Sensor Read Command1 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Read_Cmd1_t {
- union {
- struct {
- uint8_t Digital_Sensor_Read_Cmd1 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Read_Cmd1_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Read_Cmd2 Sensor Read Command2 (Digital_Sensor_Read_Cmd2) Register
- * Sensor Read Command2 (Digital_Sensor_Read_Cmd2) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Read_Cmd2_Struct
- *! \brief Sensor Read Command2 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Read_Cmd2_t {
- union {
- struct {
- uint8_t Digital_Sensor_Read_Cmd2 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Read_Cmd2_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Read_Cmd3 Sensor Read Command3 (Digital_Sensor_Read_Cmd3) Register
- * Sensor Read Command3 (Digital_Sensor_Read_Cmd3) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Read_Cmd3_Struct
- *! \brief Sensor Read Command3 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Read_Cmd3_t {
- union {
- struct {
- uint8_t Digital_Sensor_Read_Cmd3 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Read_Cmd3_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Read_Cmd4 Sensor Read Command4 (Digital_Sensor_Read_Cmd4) Register
- * Sensor Read Command4 (Digital_Sensor_Read_Cmd4) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Read_Cmd4_Struct
- *! \brief Sensor Read Command4 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Read_Cmd4_t {
- union {
- struct {
- uint8_t Digital_Sensor_Read_Cmd4 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Read_Cmd4_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Read_Cmd5 Sensor Read Command5 (Digital_Sensor_Read_Cmd5) Register
- * Sensor Read Command5 (Digital_Sensor_Read_Cmd5) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Read_Cmd5_Struct
- *! \brief Sensor Read Command5 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Read_Cmd5_t {
- union {
- struct {
- uint8_t Digital_Sensor_Read_Cmd5 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Read_Cmd5_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Read_Cmd6 Sensor Read Command6 (Digital_Sensor_Read_Cmd6) Register
- * Sensor Read Command6 (Digital_Sensor_Read_Cmd6) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Read_Cmd6_Struct
- *! \brief Sensor Read Command6 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Read_Cmd6_t {
- union {
- struct {
- uint8_t Digital_Sensor_Read_Cmd6 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Read_Cmd6_t;
-
-/*@}*/
-
-/** @defgroup Digital_Sensor_Read_Cmd7 Sensor Read Command7 (Digital_Sensor_Read_Cmd7) Register
- * Sensor Read Command7 (Digital_Sensor_Read_Cmd7) Register.
- * @{
- */
-
-/* ==========================================================================
- *! \struct ADMW_CORE_Digital_Sensor_Read_Cmd7_Struct
- *! \brief Sensor Read Command7 Register bit field structure
- * ========================================================================== */
-typedef struct _ADMW_CORE_Digital_Sensor_Read_Cmd7_t {
- union {
- struct {
- uint8_t Digital_Sensor_Read_Cmd7 : 8; /**< Per Conversion Command to Send to Digital I2C/SPI Sensor */
- };
- uint8_t VALUE8;
- };
-} ADMW_CORE_Digital_Sensor_Read_Cmd7_t;
-
-/*@}*/
-
#if defined (__CC_ARM)
#pragma pop
--- a/inc/admw1001/admw1001_host_comms.h Wed Oct 23 16:18:50 2019 +0000
+++ b/inc/admw1001/admw1001_host_comms.h Fri Oct 25 05:08:19 2019 +0000
@@ -75,6 +75,12 @@
*/
#define ADMW1001_HOST_COMMS_XFER_DELAY (60)
+/*
+ * The following defines the maximum number of retries before aborting a transfer.
+ */
+#define ADMW1001_HOST_COMMS_MAX_RETRIES (10)
+
+
/*! ADMW1001 Sensor Result bit field structure */
typedef struct ADMW1001_Sensor_Result_t {
union {
--- a/inc/admw_api.h Wed Oct 23 16:18:50 2019 +0000
+++ b/inc/admw_api.h Fri Oct 25 05:08:19 2019 +0000
@@ -50,6 +50,7 @@
#include "inc/admw_spi.h"
#include "inc/admw_log.h"
#include "inc/admw_time.h"
+#include "inc/admw1001/admw1001_sensor_types.h"
/*! @defgroup ADMW_Api ADMW Host Library API
* Host library API common to the ADMW product family.
@@ -60,17 +61,9 @@
extern "C" {
#endif
-/*! The maximum number of channels supported by this API
- * @note Specific ADMW products may implement a lower number of channels */
-#define ADMW_MAX_CHANNELS 16
-
/*! A handle used in all API functions to identify the ADMW device. */
-
typedef void* ADMW_DEVICE_HANDLE;
-#define ADMW_FORMATTED_VERSION_SIZE 11u
-#define ADMW_VERSION_REG_VAL_SIZE 4u
-#define ADMW1001_FIRMWARE_VERSION_DEFAULT "00.00.0000"
#define SPI_BUFFER_SIZE 100u
#define SFL_READ_STATUS_HDR_SIZE 14u
@@ -78,13 +71,16 @@
#define SFL_READ_STATUS_RESPONSE_SIZE 42u
/*! Supported connection types for communication with the ADMW device. */
-typedef enum {
+typedef enum
+{
ADMW_CONNECTION_TYPE_SPI = 1,
/*!< Serial Peripheral Interface (SPI) connection type */
-} ADMW_CONNECTION_TYPE;
+
+} ADMW_CONNECTION_TYPE;
/*! Connection details for communication with a ADMW device instance. */
-typedef struct {
+typedef struct
+{
ADMW_CONNECTION_TYPE type;
/*!< Connection type selection */
ADMW_PLATFORM_SPI_CONFIG spi;
@@ -93,10 +89,12 @@
/*!< GPIO connection parameters, for device reset and status I/O signals */
ADMW_PLATFORM_LOG_CONFIG log;
/*!< Log interface connection parameters, for display/routing of log messages */
-} ADMW_CONNECTION;
+
+} ADMW_CONNECTION;
/*! Bit masks (flags) for the different device status indicators. */
-typedef enum {
+typedef enum
+{
ADMW_DEVICE_STATUS_BUSY = (1 << 0),
/*!< Indicates that a command is currently running on the device */
ADMW_DEVICE_STATUS_DATAREADY = (1 << 1),
@@ -111,100 +109,110 @@
/*!< Indicates that a configuration error condition has been detected by the device */
ADMW_DEVICE_STATUS_LUT_ERROR = (1 << 6),
/*!< Indicates that a look-up table error condition has been detected by the device */
-} ADMW_DEVICE_STATUS_FLAGS;
+
+} ADMW_DEVICE_STATUS_FLAGS;
/*! Bit masks (flags) for the different diagnostics status indicators. */
-typedef enum {
+typedef enum
+{
ADMW_DIAGNOSTICS_STATUS_CHECKSUM_ERROR = (1 << 0),
/*!< Indicates Error on Internal Checksum Calculations */
ADMW_DIAGNOSTICS_STATUS_CONVERSION_ERROR = (1 << 8),
/*!< Indicates Error During Internal ADC Conversions */
ADMW_DIAGNOSTICS_STATUS_CALIBRATION_ERROR = (1 << 9),
/*!< Indicates Error During Internal Device Calibrations */
-} ADMW_DIAGNOSTICS_STATUS_FLAGS;
+
+} ADMW_DIAGNOSTICS_STATUS_FLAGS;
/*! Bit masks (flags) for the different channel alert indicators. */
-typedef enum {
- ADMW_CHANNEL_ALERT_TIMEOUT = (1 << 0),
- /*!< Indicates timeout condition detected on the channel */
- ADMW_CHANNEL_ALERT_UNDER_RANGE = (1 << 1),
- /*!< Indicates raw sample under valid input range, possibly clamped */
- ADMW_CHANNEL_ALERT_OVER_RANGE = (1 << 2),
- /*!< Indicates raw sample over valid input range, possibly clamped */
- ADMW_CHANNEL_ALERT_LOW_LIMIT = (1 << 3),
- /*!< Indicates measurement result was below configured minimum threshold */
- ADMW_CHANNEL_ALERT_HIGH_LIMIT = (1 << 4),
- /*!< Indicates measurement result was above configured maximum threshold */
- ADMW_CHANNEL_ALERT_SENSOR_OPEN = (1 << 5),
- /*!< Indicates open circuit or mis-wire condition detected on the channel */
- ADMW_CHANNEL_ALERT_REF_DETECT = (1 << 6),
- /*!< Indicates reference-detect error condition detected on the channel */
- ADMW_CHANNEL_ALERT_CONFIG_ERR = (1 << 7),
- /*!< Indicates configuration error condition detected on the channel */
- ADMW_CHANNEL_ALERT_LUT_ERR = (1 << 8),
- /*!< Indicates look-up table error condition detected on the channel */
- ADMW_CHANNEL_ALERT_SENSOR_NOT_READY = (1 << 9),
- /*!< Indicates digital sensor not-ready error condition detected on the channel */
- ADMW_CHANNEL_ALERT_COMP_NOT_READY = (1 << 10),
- /*!< Indicates compensation channel not-ready error condition detected on the channel */
- ADMW_CHANNEL_ALERT_LUT_UNDER_RANGE = (1 << 13),
- /*!< Indicates raw sample was under the available LUT/equation range */
- ADMW_CHANNEL_ALERT_LUT_OVER_RANGE = (1 << 14),
- /*!< Indicates raw sample was over the available LUT/equation range */
-} ADMW_CHANNEL_ALERT_FLAGS;
+typedef enum
+{
+ ADMW_ALERT_DETAIL_CH_RESULT_VALID = (1 << 0),
+ /*!< Indicates valid result in the channel */
+ ADMW_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE = (1 << 1),
+ /*!< Indicates ADC is near overrange in the channel */
+ ADMW_ALERT_DETAIL_CH_SENSOR_UNDERRANGE = (1 << 2),
+ /*!< Indicates sensor underrange in the channel */
+ ADMW_ALERT_DETAIL_CH_SENSOR_OVERRANGE = (1 << 3),
+ /*!< Indicates sensor overrange in the channel */
+ ADMW_ALERT_DETAIL_CH_CJ_SOFT_FAULT = (1 << 4),
+ /*!< Indicates Cold Junction soft fault in the channel */
+ ADMW_ALERT_DETAIL_CH_CJ_HARD_FAULT = (1 << 5),
+ /*!< Indicates Cold Junction Hard Fault in the channel */
+ ADMW_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE = (1 << 6),
+ /*!< Indicates ADC Input overrange in the channel */
+ ADMW_ALERT_DETAIL_CH_SENSOR_HARDFAULT = (1 << 7),
+ /*!< Indicates Hard Fault in the channel */
+} ADMW_CHANNEL_ALERT_FLAGS;
/*! Status details retreived from the ADMW device. */
-typedef struct {
+typedef struct
+{
ADMW_DEVICE_STATUS_FLAGS deviceStatus;
/*!< General summary status information from the device */
ADMW_DIAGNOSTICS_STATUS_FLAGS diagnosticsStatus;
/*!< Diagnostic error status information from the device */
- ADMW_CHANNEL_ALERT_FLAGS channelAlerts[ADMW_MAX_CHANNELS];
+ ADMW_CHANNEL_ALERT_FLAGS channelAlerts[ADMW1001_MAX_CHANNELS];
/*!< Per-channel alert status information from the device */
- uint32_t errorCode;
+ uint32_t errorCode;
/*!< Code identifying the last error signalled by the device */
- uint32_t alertCode;
+ uint32_t alertCode;
/*!< Code identifying the last alert signalled by the device */
- uint32_t debugCode;
+ uint32_t debugCode;
/*!< Supplementary code related to the last error/alert */
- uint32_t channelAlertCodes[ADMW_MAX_CHANNELS];
+ uint32_t channelAlertCodes[ADMW1001_MAX_CHANNELS];
/*!< Per-channel code identifying the last alert signalled for each channel */
-} ADMW_STATUS;
+
+} ADMW_STATUS;
/*! Data sample details retreived from the ADMW device. */
-typedef struct {
+typedef struct
+{
ADMW_DEVICE_STATUS_FLAGS status;
/*!< Device summary status snapshot when the sample was recorded */
- uint32_t channelId;
+ uint32_t channelId;
/*!< The measurement channel from which this sample was obtained */
- uint32_t rawValue;
+ uint32_t rawValue;
/*!< The raw (unprocessed) value obtained directly from the measurement
* channel, if available
*/
- float32_t processedValue;
+ float32_t processedValue;
/*!< The processed value obtained from the measurement channel, as a final
* measurement value, following calibration and linearisation correction,
* and conversion into an appropriate unit of measurement.
*/
-} ADMW_DATA_SAMPLE;
+
+} ADMW_DATA_SAMPLE;
/*! Measurement mode options for the ADMW device.
* @ref admw_StartMeasurement
*/
-typedef enum {
+typedef enum
+{
ADMW_MEASUREMENT_MODE_NORMAL = 0,
/*!< In this mode, normal measurement cycle(s) are executed and data samples
* are returned with raw measurement values included. */
ADMW_MEASUREMENT_MODE_OMIT_RAW,
/*!< In this mode, normal measurement cycle(s) are executed and data samples
* are returned with raw measurement values omitted for efficiency. */
-} ADMW_MEASUREMENT_MODE;
+
+} ADMW_MEASUREMENT_MODE;
/*! Identifiers for the user configuration slots in persistent memory. */
-typedef enum {
+typedef enum
+{
ADMW_FLASH_CONFIG_1,
-} ADMW_USER_CONFIG_SLOT;
+
+} ADMW_USER_CONFIG_SLOT;
+
+
+typedef struct
+{
+ unsigned nDeviceIndex;
+ ADMW_SPI_HANDLE hSpi;
+ ADMW_GPIO_HANDLE hGpio;
+} ADMW_DEVICE_CONTEXT;
/******************************************************************************
* ADMW High-Level API function prototypes
@@ -227,7 +235,7 @@
* - #ADMW_INVALID_DEVICE_NUM Invalid device index specified
*
* @details Configure and initialise the Log interface and the SPI/GPIO
- * communication interface to the ADMW1001 module.
+ * communication interface to the ADISense module.
*/
ADMW_RESULT admw_Open(
unsigned const nDeviceIndex,
@@ -681,7 +689,9 @@
ADMW_DEVICE_HANDLE hDevice,
bool *pbCommandRunning);
+ADMW_RESULT admw1001_sendRun( ADMW_DEVICE_HANDLE const hDevice);
ADMW_RESULT deviceInformation(ADMW_DEVICE_HANDLE hDevice);
+
#ifdef __cplusplus
}
#endif
--- a/inc/admw_gpio.h Wed Oct 23 16:18:50 2019 +0000
+++ b/inc/admw_gpio.h Fri Oct 25 05:08:19 2019 +0000
@@ -58,6 +58,7 @@
ADMW_GPIO_PIN_RESET = 0, /*!< RESET GPIO output signal */
ADMW_GPIO_PIN_ALERT_ERROR, /*!< ALERT GPIO input signal */
ADMW_GPIO_PIN_DATAREADY, /*!< DATAREADY GPIO input signal */
+ ADMW_GPIO_PIN_CS, /*!< CS GPIO output signal */
} ADMW_GPIO_PIN;
/*!
--- a/inc/mbed/admw_platform.h Wed Oct 23 16:18:50 2019 +0000
+++ b/inc/mbed/admw_platform.h Fri Oct 25 05:08:19 2019 +0000
@@ -61,6 +61,7 @@
typedef struct {
int resetPin;
+ int csPin;
int alertErrorPin;
int datareadyPin;
} ADMW_PLATFORM_GPIO_CONFIG;
--- a/main.cpp Wed Oct 23 16:18:50 2019 +0000 +++ b/main.cpp Fri Oct 25 05:08:19 2019 +0000 @@ -53,13 +53,12 @@ extern ADMW_CONFIG sensor3_typeJ_cjc0_config; extern ADMW_CONFIG i2c0_sensirionSHT3X_config; extern ADMW_CONFIG multichannel_continuous_config; -extern ADMW_CONFIG multichannel_multicycle_config; extern ADMW_CONFIG multichannel_singlecycle_config; extern ADMW_CONFIG sensor2_bridge_4w_load_cell_config; extern ADMW_CONFIG rtd_4w_config; extern ADMW_CONFIG config; /* Change the following pointer to select any of the configurations above */ -static ADMW_CONFIG *pSelectedConfig = &sensor0_typeK_cjc0_config; +static ADMW_CONFIG *pSelectedConfig = &sensor2_bridge_4w_load_cell_config; static ADMW_CONNECTION connectionInfo = PLATFORM_CONNECTION_INFO;
--- a/src/admw_1001.c Wed Oct 23 16:18:50 2019 +0000
+++ b/src/admw_1001.c Fri Oct 25 05:08:19 2019 +0000
@@ -58,7 +58,10 @@
#define VERSIONID_MINOR 0
uint32_t getDataCnt = 0;
+#define ADMW_VERSION_REG_VAL_SIZE 4u
+#define ADMW_FORMATTED_VERSION_SIZE 11u
+#define ADMW_SFL_READ_STATUS_SIZE 42u
/*
* The following macros are used to encapsulate the register access code
* to improve readability in the functions further below in this file
@@ -184,12 +187,12 @@
#define ADMW1001_CHANNEL_IS_VIRTUAL(c) \
((c) == ADMW1001_CH_ID_DIG_SPI_1 || (c) == ADMW1001_CH_ID_DIG_SPI_2)
-typedef struct {
- unsigned nDeviceIndex;
- ADMW_SPI_HANDLE hSpi;
- ADMW_GPIO_HANDLE hGpio;
-
-} ADMW_DEVICE_CONTEXT;
+//typedef struct {
+// unsigned nDeviceIndex;
+// ADMW_SPI_HANDLE hSpi;
+// ADMW_GPIO_HANDLE hGpio;
+//
+//} ADMW_DEVICE_CONTEXT;
static ADMW_DEVICE_CONTEXT gDeviceCtx[ADMW_PLATFORM_MAX_DEVICES];
@@ -312,9 +315,6 @@
ADMW_CORE_Status_t statusReg;
READ_REG_U8(hDevice, statusReg.VALUE8, CORE_STATUS);
- ADMW_CORE_Alert_Status_2_t alert2Reg;
- READ_REG_U16(hDevice, alert2Reg.VALUE16, CORE_ALERT_STATUS_2);
-
memset(pStatus, 0, sizeof(*pStatus));
if (!statusReg.Cmd_Running) /* Active-low, so invert it */
@@ -326,56 +326,37 @@
if (statusReg.Alert_Active) {
pStatus->deviceStatus |= ADMW_DEVICE_STATUS_ALERT;
- ADMW_CORE_Alert_Code_t alertCodeReg;
- READ_REG_U16(hDevice, alertCodeReg.VALUE16, CORE_ALERT_CODE);
- pStatus->alertCode = alertCodeReg.Alert_Code;
-
ADMW_CORE_Channel_Alert_Status_t channelAlertStatusReg;
READ_REG_U16(hDevice, channelAlertStatusReg.VALUE16,
CORE_CHANNEL_ALERT_STATUS);
for (unsigned i = 0; i < ADMW1001_MAX_CHANNELS; i++) {
if (channelAlertStatusReg.VALUE16 & (1 << i)) {
- ADMW_CORE_Alert_Code_Ch_t channelAlertCodeReg;
- READ_REG_U16(hDevice, channelAlertCodeReg.VALUE16, CORE_ALERT_CODE_CHn(i));
- pStatus->channelAlertCodes[i] = channelAlertCodeReg.Alert_Code_Ch;
-
ADMW_CORE_Alert_Detail_Ch_t alertDetailReg;
READ_REG_U16(hDevice, alertDetailReg.VALUE16,
CORE_ALERT_DETAIL_CHn(i));
- if (alertDetailReg.Time_Out)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_TIMEOUT;
- if (alertDetailReg.Under_Range)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_UNDER_RANGE;
- if (alertDetailReg.Over_Range)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_OVER_RANGE;
- if (alertDetailReg.Low_Limit)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_LOW_LIMIT;
- if (alertDetailReg.High_Limit)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_HIGH_LIMIT;
- if (alertDetailReg.Sensor_Open)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_SENSOR_OPEN;
- if (alertDetailReg.Ref_Detect)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_REF_DETECT;
- if (alertDetailReg.Config_Err)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_CONFIG_ERR;
- if (alertDetailReg.LUT_Error_Ch)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_LUT_ERR;
- if (alertDetailReg.Sensor_Not_Ready)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_SENSOR_NOT_READY;
- if (alertDetailReg.Comp_Not_Ready)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_COMP_NOT_READY;
- if (alertDetailReg.Correction_UnderRange)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_LUT_UNDER_RANGE;
- if (alertDetailReg.Correction_OverRange)
- pStatus->channelAlerts[i] |= ADMW_CHANNEL_ALERT_LUT_OVER_RANGE;
+ if (alertDetailReg.ADC_Near_Overrange)
+ pStatus->channelAlerts[i] |= ADMW_ALERT_DETAIL_CH_ADC_NEAR_OVERRANGE;
+ if (alertDetailReg.Sensor_UnderRange)
+ pStatus->channelAlerts[i] |= ADMW_ALERT_DETAIL_CH_SENSOR_UNDERRANGE;
+ if (alertDetailReg.Sensor_OverRange)
+ pStatus->channelAlerts[i] |= ADMW_ALERT_DETAIL_CH_SENSOR_OVERRANGE ;
+ if (alertDetailReg.CJ_Soft_Fault)
+ pStatus->channelAlerts[i] |= ADMW_ALERT_DETAIL_CH_CJ_SOFT_FAULT ;
+ if (alertDetailReg.CJ_Hard_Fault)
+ pStatus->channelAlerts[i] |= ADMW_ALERT_DETAIL_CH_CJ_HARD_FAULT;
+ if (alertDetailReg.ADC_Input_OverRange)
+ pStatus->channelAlerts[i] |= ADMW_ALERT_DETAIL_CH_ADC_INPUT_OVERRANGE ;
+ if (alertDetailReg.Sensor_HardFault)
+ pStatus->channelAlerts[i] |= ADMW_ALERT_DETAIL_CH_SENSOR_HARDFAULT;
+
}
}
- if (alert2Reg.Configuration_Error)
+ if (statusReg.Configuration_Error)
pStatus->deviceStatus |= ADMW_DEVICE_STATUS_CONFIG_ERROR;
- if (alert2Reg.LUT_Error)
+ if (statusReg.LUT_Error)
pStatus->deviceStatus |= ADMW_DEVICE_STATUS_LUT_ERROR;
}
@@ -386,23 +367,7 @@
READ_REG_U16(hDevice, errorCodeReg.VALUE16, CORE_ERROR_CODE);
pStatus->errorCode = errorCodeReg.Error_Code;
- ADMW_CORE_Diagnostics_Status_t diagStatusReg;
- READ_REG_U16(hDevice, diagStatusReg.VALUE16, CORE_DIAGNOSTICS_STATUS);
-
- if (diagStatusReg.Diag_Checksum_Error)
- pStatus->diagnosticsStatus |= ADMW_DIAGNOSTICS_STATUS_CHECKSUM_ERROR;
- if (diagStatusReg.Diag_Conversion_Error)
- pStatus->diagnosticsStatus |= ADMW_DIAGNOSTICS_STATUS_CONVERSION_ERROR;
- if (diagStatusReg.Diag_Calibration_Error)
- pStatus->diagnosticsStatus |= ADMW_DIAGNOSTICS_STATUS_CALIBRATION_ERROR;
}
-
- if (statusReg.Alert_Active || statusReg.Error) {
- ADMW_CORE_Debug_Code_t debugCodeReg;
- READ_REG_U32(hDevice, debugCodeReg.VALUE32, CORE_DEBUG_CODE);
- pStatus->debugCode = debugCodeReg.Debug_Code;
- }
-
return ADMW_SUCCESS;
}
@@ -423,6 +388,23 @@
return ADMW_SUCCESS;
}
+ADMW_RESULT deviceInformation(ADMW_DEVICE_HANDLE hDevice)
+{
+ uint16_t nAddress = REG_CORE_REVISION;
+ char nData[ADMW_VERSION_REG_VAL_SIZE]; //4 Bytes of version register data
+ ADMW_RESULT res;
+ res=admw1001_ReadRegister(hDevice,nAddress,nData,sizeof(nData));
+ if(res != ADMW_SUCCESS) {
+ //if reading version register failed, sending 00.00.0000 as ADMW1001 firmware version
+ //strcat(nData, ADMW1001_FIRMWARE_VERSION_DEFAULT);
+ ADMW_LOG_INFO("Firmware Version Id is %X.%X",nData[2],nData[0]);
+ } else {
+ char buffer[ADMW_FORMATTED_VERSION_SIZE]; //00.00.0000 8 digits + 2 Bytes "." + one null character at the end
+ strcat(nData, buffer);
+ ADMW_LOG_INFO("Firmware Version Id is %X.%X",nData[2],nData[0]);
+ }
+ return ADMW_SUCCESS;
+}
static ADMW_RESULT executeCommand(
ADMW_DEVICE_HANDLE const hDevice,
ADMW_CORE_Command_Special_Command const command,
@@ -463,13 +445,6 @@
return ADMW_SUCCESS;
}
-ADMW_RESULT admw_Shutdown(
- ADMW_DEVICE_HANDLE const hDevice)
-{
- return executeCommand(hDevice, CORE_COMMAND_POWER_DOWN, false);
-}
-
-
ADMW_RESULT admw_ApplyConfigUpdates(
ADMW_DEVICE_HANDLE const hDevice)
{
@@ -577,9 +552,69 @@
}
/*
+ *
+ */
+ADMW_RESULT admw1001_sendRun( ADMW_DEVICE_HANDLE const hDevice)
+{
+ bool bitCommand;
+ ADMW_RESULT eRet;
+ uint8_t pinreg = 0x1;
+
+ ADMW_DEVICE_CONTEXT *pCtx = hDevice;
+ static uint8_t DataBuffer[SPI_BUFFER_SIZE] = {0};
+ uint16_t nSize;
+
+ //Construct Read Status command
+ DataBuffer[0] = 0x07;
+ DataBuffer[1] = 0x0E; //Packet ID
+
+ DataBuffer[2] = 0x00;
+ DataBuffer[3] = 0x00; //Data words
+
+ DataBuffer[4] = 0x45;
+ DataBuffer[5] = 0x00; //Command ID
+
+ DataBuffer[6] = 0x00;
+ DataBuffer[7] = 0x50;
+ DataBuffer[8] = 0x00;
+ DataBuffer[9] = 0x00; //Address
+
+ DataBuffer[10] = 0x95;
+ DataBuffer[11] = 0x00;
+ DataBuffer[12] = 0x00;
+ DataBuffer[13] = 0x00; //Checksum
+
+ nSize = SFL_READ_STATUS_HDR_SIZE;
+
+ do {
+ // Get the SFL command irq pin to check if SFL is ready to receive commands
+ // Status pin is not checked since SFL is just booted, there should not be any issue with SFL
+ eRet = admw_GetGpioState( hDevice, ADMW_GPIO_PIN_DATAREADY, &bitCommand );
+ if( eRet != ADMW_SUCCESS) {
+ return eRet;
+ }
+
+ // Command IRQ pin should be low and Status IRQ pin should be high for SFL to be in good state and ready to recieve commands
+ // pinreg == '0x00' - Error occured in SFL
+ // pinreg == '0x01' - SFL is ready to recieve commands
+ // pinreg == '0x02' - Error occured in handling any commands in SFL
+ // pinreg == '0x03' - SFL not booted
+
+ pinreg = (bitCommand);
+
+ } while(pinreg != 0x0u);
+
+ eRet = admw_SpiTransfer(pCtx->hSpi, DataBuffer, NULL,
+ nSize, false);
+
+ return eRet;
+}
+
+/*
* Read a set of data samples from the device.
* This may be called at any time.
*/
+
ADMW_RESULT admw_GetData(
ADMW_DEVICE_HANDLE const hDevice,
ADMW_MEASUREMENT_MODE const eMeasurementMode,
@@ -903,12 +938,16 @@
* active when those sensors are selected and we use the count
* from the corresponding "physical" channel
*/
+#if 0 /* SPI sensors arent supported at present to be added back once there is
+ * support for these sensors
+ */
if ((sensorTypeReg.Sensor_Type >=
CORE_SENSOR_TYPE_SPI_ACCELEROMETER_A) &&
(sensorTypeReg.Sensor_Type <=
CORE_SENSOR_TYPE_SPI_ACCELEROMETER_B)) {
nActualChannels += 2;
}
+#endif
}
nChannelsEnabled += nActualChannels;
@@ -1094,47 +1133,7 @@
return ADMW_SUCCESS;
}
-ADMW_RESULT admw1001_SetDiagnosticsConfig(
- ADMW_DEVICE_HANDLE hDevice,
- ADMW1001_DIAGNOSTICS_CONFIG *pDiagnosticsConfig)
-{
- ADMW_CORE_Diagnostics_Control_t diagnosticsControlReg;
- diagnosticsControlReg.VALUE16 = REG_RESET_VAL(CORE_DIAGNOSTICS_CONTROL);
-
- if (pDiagnosticsConfig->disableGlobalDiag)
- diagnosticsControlReg.Diag_Global_En = 0;
- else
- diagnosticsControlReg.Diag_Global_En = 1;
-
- if (pDiagnosticsConfig->disableMeasurementDiag)
- diagnosticsControlReg.Diag_Meas_En = 0;
- else
- diagnosticsControlReg.Diag_Meas_En = 1;
-
- switch (pDiagnosticsConfig->osdFrequency) {
- case ADMW1001_OPEN_SENSOR_DIAGNOSTICS_DISABLED:
- diagnosticsControlReg.Diag_OSD_Freq = CORE_DIAGNOSTICS_CONTROL_OCD_OFF;
- break;
- case ADMW1001_OPEN_SENSOR_DIAGNOSTICS_PER_CYCLE:
- diagnosticsControlReg.Diag_OSD_Freq = CORE_DIAGNOSTICS_CONTROL_OCD_PER_1_CYCLE;
- break;
- case ADMW1001_OPEN_SENSOR_DIAGNOSTICS_PER_100_CYCLES:
- diagnosticsControlReg.Diag_OSD_Freq = CORE_DIAGNOSTICS_CONTROL_OCD_PER_100_CYCLES;
- break;
- case ADMW1001_OPEN_SENSOR_DIAGNOSTICS_PER_1000_CYCLES:
- diagnosticsControlReg.Diag_OSD_Freq = CORE_DIAGNOSTICS_CONTROL_OCD_PER_1000_CYCLES;
- break;
- default:
- ADMW_LOG_ERROR("Invalid open-sensor diagnostic frequency %d specified",
- pDiagnosticsConfig->osdFrequency);
- return ADMW_INVALID_PARAM;
- }
-
- WRITE_REG_U16(hDevice, diagnosticsControlReg.VALUE16, CORE_DIAGNOSTICS_CONTROL);
-
- return ADMW_SUCCESS;
-}
ADMW_RESULT admw1001_SetChannelCount(
ADMW_DEVICE_HANDLE hDevice,
@@ -1504,39 +1503,6 @@
return ADMW_INVALID_PARAM;
}
-
-
- switch(pCurrentConfig->diodeRatio) {
- case ADMW1001_ADC_EXC_CURRENT_IOUT_DIODE_10UA_100UA:
- channelExcitationReg.IOUT_Diode_Ratio = CORE_CHANNEL_EXCITATION_DIODE_2PT_10UA_100UA;
- break;
- case ADMW1001_ADC_EXC_CURRENT_IOUT_DIODE_20UA_160UA:
- channelExcitationReg.IOUT_Diode_Ratio = CORE_CHANNEL_EXCITATION_DIODE_2PT_20UA_160UA;
- break;
- case ADMW1001_ADC_EXC_CURRENT_IOUT_DIODE_50UA_300UA:
- channelExcitationReg.IOUT_Diode_Ratio = CORE_CHANNEL_EXCITATION_DIODE_2PT_50UA_300UA;
- break;
- case ADMW1001_ADC_EXC_CURRENT_IOUT_DIODE_100UA_600UA:
- channelExcitationReg.IOUT_Diode_Ratio = CORE_CHANNEL_EXCITATION_DIODE_2PT_100UA_600UA;
- break;
- case ADMW1001_ADC_EXC_CURRENT_IOUT_DIODE_10UA_50UA_100UA:
- channelExcitationReg.IOUT_Diode_Ratio = CORE_CHANNEL_EXCITATION_DIODE_3PT_10UA_50UA_100UA;
- break;
- case ADMW1001_ADC_EXC_CURRENT_IOUT_DIODE_20UA_100UA_160UA:
- channelExcitationReg.IOUT_Diode_Ratio = CORE_CHANNEL_EXCITATION_DIODE_3PT_20UA_100UA_160UA;
- break;
- case ADMW1001_ADC_EXC_CURRENT_IOUT_DIODE_50UA_150UA_300UA:
- channelExcitationReg.IOUT_Diode_Ratio = CORE_CHANNEL_EXCITATION_DIODE_3PT_50UA_150UA_300UA;
- break;
- case ADMW1001_ADC_EXC_CURRENT_IOUT_DIODE_100UA_300UA_600UA:
- channelExcitationReg.IOUT_Diode_Ratio = CORE_CHANNEL_EXCITATION_DIODE_3PT_100UA_300UA_600UA;
- break;
- default:
- ADMW_LOG_ERROR("Invalid diode ratio %d specified",
- pCurrentConfig->diodeRatio);
- return ADMW_INVALID_PARAM;
- }
-
WRITE_REG_U16(hDevice, channelExcitationReg.VALUE16, CORE_CHANNEL_EXCITATIONn(eChannelId));
return ADMW_SUCCESS;
@@ -1620,88 +1586,6 @@
return ADMW_SUCCESS;
}
-static ADMW_RESULT admw_SetDigitalSensorCommands(
- ADMW_DEVICE_HANDLE hDevice,
- ADMW1001_CH_ID eChannelId,
- ADMW1001_DIGITAL_SENSOR_COMMAND *pConfigCommand,
- ADMW1001_DIGITAL_SENSOR_COMMAND *pDataRequestCommand)
-{
- ADMW_CORE_Digital_Sensor_Num_Cmds_t numCmdsReg;
-
- numCmdsReg.VALUE8 = REG_RESET_VAL(CORE_DIGITAL_SENSOR_NUM_CMDSn);
-
- CHECK_REG_FIELD_VAL(CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_CFG_CMDS,
- pConfigCommand->commandLength);
- CHECK_REG_FIELD_VAL(CORE_DIGITAL_SENSOR_NUM_CMDS_DIGITAL_SENSOR_NUM_READ_CMDS,
- pDataRequestCommand->commandLength);
-
- numCmdsReg.Digital_Sensor_Num_Cfg_Cmds = pConfigCommand->commandLength;
- numCmdsReg.Digital_Sensor_Num_Read_Cmds = pDataRequestCommand->commandLength;
-
- WRITE_REG_U8(hDevice, numCmdsReg.VALUE8,
- CORE_DIGITAL_SENSOR_NUM_CMDSn(eChannelId));
-
- /*
- * NOTE - the fall-through cases in the switch statement below are
- * intentional.
- */
- switch (pConfigCommand->commandLength) {
- case 7:
- WRITE_REG_U8(hDevice, pConfigCommand->command[6],
- CORE_DIGITAL_SENSOR_COMMAND7n(eChannelId));
- case 6:
- WRITE_REG_U8(hDevice, pConfigCommand->command[5],
- CORE_DIGITAL_SENSOR_COMMAND6n(eChannelId));
- case 5:
- WRITE_REG_U8(hDevice, pConfigCommand->command[4],
- CORE_DIGITAL_SENSOR_COMMAND5n(eChannelId));
- case 4:
- WRITE_REG_U8(hDevice, pConfigCommand->command[3],
- CORE_DIGITAL_SENSOR_COMMAND4n(eChannelId));
- case 3:
- WRITE_REG_U8(hDevice, pConfigCommand->command[2],
- CORE_DIGITAL_SENSOR_COMMAND3n(eChannelId));
- case 2:
- WRITE_REG_U8(hDevice, pConfigCommand->command[1],
- CORE_DIGITAL_SENSOR_COMMAND2n(eChannelId));
- case 1:
- WRITE_REG_U8(hDevice, pConfigCommand->command[0],
- CORE_DIGITAL_SENSOR_COMMAND1n(eChannelId));
- case 0:
- default:
- break;
- };
-
- switch (pDataRequestCommand->commandLength) {
- case 7:
- WRITE_REG_U8(hDevice, pDataRequestCommand->command[6],
- CORE_DIGITAL_SENSOR_READ_CMD7n(eChannelId));
- case 6:
- WRITE_REG_U8(hDevice, pDataRequestCommand->command[5],
- CORE_DIGITAL_SENSOR_READ_CMD6n(eChannelId));
- case 5:
- WRITE_REG_U8(hDevice, pDataRequestCommand->command[4],
- CORE_DIGITAL_SENSOR_READ_CMD5n(eChannelId));
- case 4:
- WRITE_REG_U8(hDevice, pDataRequestCommand->command[3],
- CORE_DIGITAL_SENSOR_READ_CMD4n(eChannelId));
- case 3:
- WRITE_REG_U8(hDevice, pDataRequestCommand->command[2],
- CORE_DIGITAL_SENSOR_READ_CMD3n(eChannelId));
- case 2:
- WRITE_REG_U8(hDevice, pDataRequestCommand->command[1],
- CORE_DIGITAL_SENSOR_READ_CMD2n(eChannelId));
- case 1:
- WRITE_REG_U8(hDevice, pDataRequestCommand->command[0],
- CORE_DIGITAL_SENSOR_READ_CMD1n(eChannelId));
- case 0:
- default:
- break;
- };
-
- return ADMW_SUCCESS;
-}
-
static ADMW_RESULT admw_SetDigitalSensorFormat(
ADMW_DEVICE_HANDLE hDevice,
ADMW1001_CH_ID eChannelId,
@@ -1764,23 +1648,23 @@
ADMW1001_CH_ID eChannelId,
ADMW1001_DIGITAL_CALIBRATION_COMMAND *pCalibrationParam)
{
- ADMW_CORE_Calibration_Parameter_t calibrationParamReg;
-
- calibrationParamReg.VALUE32 = REG_RESET_VAL(CORE_CALIBRATION_PARAMETERn);
-
- if (pCalibrationParam->enableCalibrationParam == false)
- calibrationParamReg.Calibration_Parameter_Enable = 0;
- else
- calibrationParamReg.Calibration_Parameter_Enable = 1;
-
- CHECK_REG_FIELD_VAL(CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER,
- pCalibrationParam->calibrationParam);
-
- calibrationParamReg.Calibration_Parameter = pCalibrationParam->calibrationParam;
-
- WRITE_REG_U32(hDevice, calibrationParamReg.VALUE32,
- CORE_CALIBRATION_PARAMETERn(eChannelId));
-
+// ADMW_CORE_Calibration_Parameter_t calibrationParamReg;
+//
+// calibrationParamReg.VALUE32 = REG_RESET_VAL(CORE_CALIBRATION_PARAMETERn);
+//
+// if (pCalibrationParam->enableCalibrationParam == false)
+// calibrationParamReg.Calibration_Parameter_Enable = 0;
+// else
+// calibrationParamReg.Calibration_Parameter_Enable = 1;
+//
+// CHECK_REG_FIELD_VAL(CORE_CALIBRATION_PARAMETER_CALIBRATION_PARAMETER,
+// pCalibrationParam->calibrationParam);
+//
+// calibrationParamReg.Calibration_Parameter = pCalibrationParam->calibrationParam;
+//
+// WRITE_REG_U32(hDevice, calibrationParamReg.VALUE32,
+// CORE_CALIBRATION_PARAMETERn(eChannelId));
+//
return ADMW_SUCCESS;
}
@@ -1952,15 +1836,6 @@
return eRet;
}
- eRet = admw_SetDigitalSensorCommands(hDevice, eChannelId,
- &pI2cChannelConfig->configurationCommand,
- &pI2cChannelConfig->dataRequestCommand);
- if (eRet != ADMW_SUCCESS) {
- ADMW_LOG_ERROR("Failed to set I2C sensor commands for channel %d",
- eChannelId);
- return eRet;
- }
-
eRet = admw_SetDigitalSensorFormat(hDevice, eChannelId,
&pI2cChannelConfig->dataFormat);
if (eRet != ADMW_SUCCESS) {
@@ -2040,15 +1915,6 @@
return eRet;
}
- eRet = admw_SetDigitalSensorCommands(hDevice, eChannelId,
- &pSpiChannelConfig->configurationCommand,
- &pSpiChannelConfig->dataRequestCommand);
- if (eRet != ADMW_SUCCESS) {
- ADMW_LOG_ERROR("Failed to set SPI sensor commands for channel %d",
- eChannelId);
- return eRet;
- }
-
eRet = admw_SetDigitalSensorFormat(hDevice, eChannelId,
&pSpiChannelConfig->dataFormat);
if (eRet != ADMW_SUCCESS) {
@@ -2130,7 +1996,7 @@
if (fSensorParam == 0.0f)
fSensorParam = NAN;
- WRITE_REG_FLOAT(hDevice, fSensorParam, CORE_SENSOR_PARAMETERn(eChannelId));
+ //WRITE_REG_FLOAT(hDevice, fSensorParam, CORE_SENSOR_PARAMETERn(eChannelId));
return ADMW_SUCCESS;
}
@@ -2211,7 +2077,17 @@
break;
default:
ADMW_LOG_ERROR("Invalid channel ID %d specified", eChannelId);
- return ADMW_INVALID_PARAM;
+ eRet = ADMW_INVALID_PARAM;
+#if 0
+ /* when using i2c sensors there is an error ( dataformat->length=0)
+ the code below catches this error and this causes further problems.*/
+ break;
+ }
+ if (eRet != ADMW_SUCCESS) {
+ ADMW_LOG_ERROR("Failed to set config for channel %d",
+ eChannelId);
+ return eRet;
+#endif
}
eRet = admw1001_SetChannelSettlingTime(hDevice, eChannelId,
@@ -2306,11 +2182,12 @@
return eRet;
}
- eRet = admw1001_SetDiagnosticsConfig(hDevice, &pDeviceConfig->diagnostics);
- if (eRet) {
- ADMW_LOG_ERROR("Failed to set diagnostics configuration");
- return eRet;
- }
+// eRet = admw1001_SetDiagnosticsConfig(hDevice, &pDeviceConfig->diagnostics);
+// if (eRet)
+// {
+// ADMW_LOG_ERROR("Failed to set diagnostics configuration");
+// return eRet;
+// }
for (ADMW1001_CH_ID id = ADMW1001_CH_ID_ANLG_1_UNIVERSAL;
id < ADMW1001_MAX_CHANNELS;
@@ -2518,161 +2395,3 @@
return ADMW_SUCCESS;
}
-
-ADMW_RESULT deviceInformation(ADMW_DEVICE_HANDLE hDevice)
-{
- uint16_t nAddress = REG_CORE_REVISION;
- char nData[ADMW_VERSION_REG_VAL_SIZE]; //4 Bytes of version register data
- ADMW_RESULT res;
- res=admw1001_ReadRegister(hDevice,nAddress,nData,sizeof(nData));
- if(res != ADMW_SUCCESS) {
- //if reading version register failed, sending 00.00.0000 as ADMW1001 firmware version
- //strcat(nData, ADMW1001_FIRMWARE_VERSION_DEFAULT);
- ADMW_LOG_INFO("Firmware Version Id is %X.%X",nData[2],nData[0]);
- } else {
- char buffer[ADMW_FORMATTED_VERSION_SIZE]; //00.00.0000 8 digits + 2 Bytes "." + one null character at the end
- strcat(nData, buffer);
- ADMW_LOG_INFO("Firmware Version Id is %X.%X",nData[2],nData[0]);
- }
- return ADMW_SUCCESS;
-}
-
-ADMW_RESULT admw1001_getFirmwareStatus(
- ADMW_DEVICE_HANDLE const hDevice,
- bool * const bFirmwareStatus)
-{
- bool bitCommand;
- ADMW_RESULT eRet;
- uint8_t pinreg = 0x1;
-
- ADMW_DEVICE_CONTEXT *pCtx = hDevice;
- static uint8_t DataBuffer[SPI_BUFFER_SIZE] = {0};
- uint16_t nSize;
-
- //Construct Read Status command
- DataBuffer[0] = 0x07;
- DataBuffer[1] = 0x0E; //Packet ID
-
- DataBuffer[2] = 0x00;
- DataBuffer[3] = 0x00; //Data words
-
- DataBuffer[4] = 0x53;
- DataBuffer[5] = 0x00; //Command ID
-
- DataBuffer[6] = 0x00;
- DataBuffer[7] = 0x00;
- DataBuffer[8] = 0x00;
- DataBuffer[9] = 0x00; //Address
-
- DataBuffer[10] = 0x53;
- DataBuffer[11] = 0x00;
- DataBuffer[12] = 0x00;
- DataBuffer[13] = 0x00; //Checksum
-
- nSize = SFL_READ_STATUS_HDR_SIZE;
-
- do {
- // Get the SFL command irq pin to check if SFL is ready to receive commands
- // Status pin is not checked since SFL is just booted, there should not be any issue with SFL
- eRet = admw_GetGpioState( hDevice, ADMW_GPIO_PIN_DATAREADY, &bitCommand );
- if( eRet != ADMW_SUCCESS) {
- return eRet;
- }
-
- // Command IRQ pin should be low and Status IRQ pin should be high for SFL to be in good state and ready to recieve commands
- // pinreg == '0x00' - Error occured in SFL
- // pinreg == '0x01' - SFL is ready to recieve commands
- // pinreg == '0x02' - Error occured in handling any commands in SFL
- // pinreg == '0x03' - SFL not booted
-
- pinreg = (bitCommand);
-
- } while(pinreg != 0x0u);
-
- eRet = admw_SpiTransfer(pCtx->hSpi, DataBuffer, NULL,
- nSize, false);
- if (eRet) {
- return eRet;
- }
-
- //wait for command irq line to go low after sending read status header
- wait_ms( 100 );
-
- do {
- // Get the SFL command irq pin to check if SFL is ready to receive commands
- // Status pin is not checked since SFL is just booted, there should not be any issue with SFL
- eRet = admw_GetGpioState( hDevice, ADMW_GPIO_PIN_DATAREADY, &bitCommand );
- if( eRet != ADMW_SUCCESS) {
- return eRet;
- }
-
- // Command IRQ pin should be low and Status IRQ pin should be high for SFL to be in good state and ready to recieve commands
- // pinreg == '0x00' - Error occured in SFL
- // pinreg == '0x01' - SFL is ready to recieve commands
- // pinreg == '0x02' - Error occured in handling any commands in SFL
- // pinreg == '0x03' - SFL not booted
-
- pinreg = (bitCommand);
-
- } while(pinreg != 0x0u);
-
- nSize = SFL_READ_STATUS_RESPONSE_SIZE;
-
- eRet = admw_SpiReceive(pCtx->hSpi, NULL, DataBuffer,
- nSize, false);
-
- if (eRet) {
- return eRet;
- }
-
- //Verifying the application version from the response to check if firmware is present or not
- /*
- Flash Memory description
- ______________
- | Secure | 0x0000 0000
- | Flashloader |
- |______________| 0x0000 3BFF
- | Security |------------------
- | Page | 0x0000 3C00
- | |
- |______________| 0x0000 3FFF
- | |------------------
- | App Info | 0x0000 4000
- | Page |
- |______________| 0x0000 4800
- | |------------------
- | Application |
- | Image | Application resides only in this region
- |______________|------------------
- | Reserved | 0x0003 FFF8
- | for | Reserved memory region
- | Signature | 0x0003 FFFF
- |______________|------------------
-
- Application version is stored in the App Info Page, the app version is updated in this region everytime the new application firmware is downloaded.
- Here we verify if Application version is present in the Read Status response
- If the app version bytes value is 0xFFFFFFFF then there is no firmware else there exist a firmware
-
- Read Status Response:
- ____________________________________________________________________________________________________________________________________
- | | | | | |
- |uint16_t nFlashLoaderVersion | uint16_t nStatus | uint32_t nApplicationVersion | uint32_t nApplicationHash[8] | uint16_t nChecksum |
- |_____________________________|__________________|______________________________|______________________________|_____________________|
-
- */
-
- if( ((DataBuffer[4] == 0xFF) &&
- (DataBuffer[5] == 0xFF) &&
- (DataBuffer[6] == 0xFF) &&
- (DataBuffer[7] == 0xFF)) ||
- ((DataBuffer[4] == 0x00) &&
- (DataBuffer[5] == 0x00) &&
- (DataBuffer[6] == 0x00) &&
- (DataBuffer[7] == 0x00))) {
- *bFirmwareStatus = false;
- } else {
- *bFirmwareStatus = true;
- }
-
- return eRet;
-}
\ No newline at end of file
--- a/src/mbed/admw_gpio.cpp Wed Oct 23 16:18:50 2019 +0000
+++ b/src/mbed/admw_gpio.cpp Fri Oct 25 05:08:19 2019 +0000
@@ -1,5 +1,5 @@
/******************************************************************************
-Copyright 2017 (c) Analog Devices, Inc.
+Copyright 2019 (c) Analog Devices, Inc.
All rights reserved.
@@ -51,9 +51,11 @@
public:
GpioContext(
PinName resetPin,
+ PinName csPin,
PinName alertErrorPin,
PinName datareadyPin)
: _reset(resetPin),
+ _cs(csPin),
_alertError(alertErrorPin),
_dataready(datareadyPin),
_alertErrorIrq(alertErrorPin),
@@ -77,7 +79,8 @@
private:
DigitalOut _reset;
-
+ DigitalOut _cs;
+
DigitalIn _alertError;
DigitalIn _dataready;
@@ -104,18 +107,22 @@
ADMW_GPIO_PIN ePinId,
bool *pState)
{
- switch(ePinId) {
- case ADMW_GPIO_PIN_ALERT_ERROR:
- *pState = _alertError;
- return ADMW_SUCCESS;
- case ADMW_GPIO_PIN_DATAREADY:
- *pState = _dataready;
- return ADMW_SUCCESS;
- case ADMW_GPIO_PIN_RESET:
- *pState = _reset;
- return ADMW_SUCCESS;
- default:
- return ADMW_INVALID_DEVICE_NUM;
+ switch(ePinId)
+ {
+ case ADMW_GPIO_PIN_ALERT_ERROR:
+ *pState = _alertError;
+ return ADMW_SUCCESS;
+ case ADMW_GPIO_PIN_DATAREADY:
+ *pState = _dataready;
+ return ADMW_SUCCESS;
+ case ADMW_GPIO_PIN_RESET:
+ *pState = _reset;
+ return ADMW_SUCCESS;
+ case ADMW_GPIO_PIN_CS:
+ *pState = _cs;
+ return ADMW_SUCCESS;
+ default:
+ return ADMW_INVALID_DEVICE_NUM;
}
}
@@ -123,12 +130,16 @@
ADMW_GPIO_PIN ePinId,
bool state)
{
- switch(ePinId) {
- case ADMW_GPIO_PIN_RESET:
- _reset = state;
- break;
- default:
- return ADMW_INVALID_DEVICE_NUM;
+ switch(ePinId)
+ {
+ case ADMW_GPIO_PIN_RESET:
+ _reset = state;
+ break;
+ case ADMW_GPIO_PIN_CS:
+ _cs = state;
+ break;
+ default:
+ return ADMW_INVALID_DEVICE_NUM;
}
return ADMW_SUCCESS;
@@ -139,19 +150,20 @@
ADMW_GPIO_CALLBACK callbackFn,
void *pArg)
{
- switch(ePinId) {
- case ADMW_GPIO_PIN_ALERT_ERROR:
- _alertErrorIrqCallback = callbackFn;
- _alertErrorIrqArg = pArg;
- _alertErrorIrq.rise(callback(this, &GpioContext::_alertErrorIrqHandler));
- return ADMW_SUCCESS;
- case ADMW_GPIO_PIN_DATAREADY:
- _datareadyIrqCallback = callbackFn;
- _datareadyIrqArg = pArg;
- _datareadyIrq.rise(callback(this, &GpioContext::_datareadyIrqHandler));
- return ADMW_SUCCESS;
- default:
- return ADMW_INVALID_DEVICE_NUM;
+ switch(ePinId)
+ {
+ case ADMW_GPIO_PIN_ALERT_ERROR:
+ _alertErrorIrqCallback = callbackFn;
+ _alertErrorIrqArg = pArg;
+ _alertErrorIrq.rise(callback(this, &GpioContext::_alertErrorIrqHandler));
+ return ADMW_SUCCESS;
+ case ADMW_GPIO_PIN_DATAREADY:
+ _datareadyIrqCallback = callbackFn;
+ _datareadyIrqArg = pArg;
+ _datareadyIrq.rise(callback(this, &GpioContext::_datareadyIrqHandler));
+ return ADMW_SUCCESS;
+ default:
+ return ADMW_INVALID_DEVICE_NUM;
}
}
@@ -182,6 +194,7 @@
ADMW_GPIO_HANDLE *phDevice)
{
GpioContext *pCtx = new GpioContext((PinName)pConfig->resetPin,
+ (PinName)pConfig->csPin,
(PinName)pConfig->alertErrorPin,
(PinName)pConfig->datareadyPin);
if (!pCtx) {
--- a/src/mbed/admw_log.cpp Wed Oct 23 16:18:50 2019 +0000 +++ b/src/mbed/admw_log.cpp Fri Oct 25 05:08:19 2019 +0000 @@ -1,5 +1,5 @@ /****************************************************************************** -Copyright 2017 (c) Analog Devices, Inc. +Copyright 2019 (c) Analog Devices, Inc. All rights reserved.
--- a/src/mbed/admw_spi.cpp Wed Oct 23 16:18:50 2019 +0000
+++ b/src/mbed/admw_spi.cpp Fri Oct 25 05:08:19 2019 +0000
@@ -1,5 +1,5 @@
/******************************************************************************
-Copyright 2017 (c) Analog Devices, Inc.
+Copyright 2019 (c) Analog Devices, Inc.
All rights reserved.
@@ -77,25 +77,22 @@
ADMW_LOG_ERROR("Failed to allocate memory for SPI device");
return ADMW_NO_MEM;
}
-
+
pCtx->_spi = new SPI((PinName)pConfig->mosiPin,
- (PinName)pConfig->misoPin,
- (PinName)pConfig->sckPin);
+ (PinName)pConfig->misoPin,
+ (PinName)pConfig->sckPin);
pCtx->_cs = new DigitalOut((PinName)pConfig->csPin, 1);
-
+
pCtx->_spi->format(ADMW_SPI_FRAME_SIZE, ADMW_SPI_MODE);
pCtx->_spi->frequency(pConfig->maxSpeedHz);
-
+
pCtx->_wakeup = new DigitalOut((PinName)pConfig->wakeupPin, 1);
-
+
*phDevice = (ADMW_SPI_HANDLE)pCtx;
-
+
return ADMW_SUCCESS;
}
-/*
- * Execute a bi-directional data transfer on the SPI interface
- */
ADMW_RESULT
admw_SpiReceive(
ADMW_SPI_HANDLE hDevice,
@@ -105,35 +102,33 @@
bool bCsHold)
{
SpiContext_t *pCtx = (SpiContext_t*)hDevice;
-
+
pCtx->_spi->format(ADMW_SPI_FRAME_SIZE, 1);
-
+
int rc = 0;
-
- *(pCtx->_wakeup) = 0;
-
- wait_us(60);
-
+
*(pCtx->_cs) = 0;
-
+
rc = pCtx->_spi->write((char*)(pTxData), pTxData ? nLength : 0,
- (char*)(pRxData), pRxData ? nLength : 0);
-
+ (char*)(pRxData), pRxData ? nLength : 0);
+
if ((rc < 0) || !bCsHold)
*(pCtx->_cs) = 1;
-
- *(pCtx->_wakeup) = 1;
-
- if (rc < 0) {
+
+ if (rc < 0)
+ {
ADMW_LOG_ERROR("Failed to complete SPI transfer");
return ADMW_FAILURE;
}
-
+
pCtx->_spi->format(ADMW_SPI_FRAME_SIZE, ADMW_SPI_MODE);
+
+ return ADMW_SUCCESS;
+}
- return ADMW_SUCCESS;
-
-}
+/*
+ * Execute a bi-directional data transfer on the SPI interface
+ */
ADMW_RESULT
admw_SpiTransfer(
ADMW_SPI_HANDLE hDevice,
@@ -143,28 +138,23 @@
bool bCsHold)
{
int rc = 0;
-
+
SpiContext_t *pCtx = (SpiContext_t*)hDevice;
-
- *(pCtx->_wakeup) = 0;
-
- wait_us(60);
-
+
*(pCtx->_cs) = 0;
-
+
rc = pCtx->_spi->write((char*)(pTxData), pTxData ? nLength : 0,
- (char*)(pRxData), pRxData ? nLength : 0);
-
+ (char*)(pRxData), pRxData ? nLength : 0);
+
if ((rc < 0) || !bCsHold)
*(pCtx->_cs) = 1;
-
- *(pCtx->_wakeup) = 1;
-
- if (rc < 0) {
+
+ if (rc < 0)
+ {
ADMW_LOG_ERROR("Failed to complete SPI transfer");
return ADMW_FAILURE;
}
-
+
return ADMW_SUCCESS;
}
@@ -179,7 +169,7 @@
delete pCtx->_spi;
delete pCtx->_cs;
delete pCtx->_wakeup;
-
+
free(pCtx);
}
--- a/src/mbed/admw_time.cpp Wed Oct 23 16:18:50 2019 +0000 +++ b/src/mbed/admw_time.cpp Fri Oct 25 05:08:19 2019 +0000 @@ -1,5 +1,5 @@ /****************************************************************************** -Copyright 2017 (c) Analog Devices, Inc. +Copyright 2019 (c) Analog Devices, Inc. All rights reserved.