Vybhav Kadaba
Mbed FW update
inc/admw1001/ADMW1001_REGISTERS_typedefs.h
- Committer:
- Vkadaba
- Date:
- 2020-03-31
- Revision:
- 61:0f16a2e3b58b
- Parent:
- 58:aa9cd5072f66
File content as of revision 61:0f16a2e3b58b:
/* ================================================================================
Created by :
Created on : 2020 Mar 12, 16:15 GMT Standard Time
Project : ADMW1001_REGISTERS
File : ADMW1001_REGISTERS_typedefs.h
Description : C Register Structures
!! ADI Confidential !!
INTERNAL USE ONLY
Copyright (c) 2020 Analog Devices, Inc. All Rights Reserved.
This software is proprietary and confidential to Analog Devices, Inc. and
its licensors.
This file was auto-generated. Do not make local changes to this file.
Auto generation script information:
Script: C:\Program Files (x86)\Yoda-19.05.01\generators\inc\genHeaders
Last modified: 26-SEP-2017
================================================================================ */
#ifndef _ADMW1001_REGISTERS_TYPEDEFS_H
#define _ADMW1001_REGISTERS_TYPEDEFS_H
/* pickup integer types */
#if defined(_LANGUAGE_C) || (defined(__GNUC__) && !defined(__ASSEMBLER__))
#include <stdint.h>
#endif /* _LANGUAGE_C */
#if defined ( __CC_ARM )
#pragma push
#pragma anon_unions
#endif
/** @defgroup Interface_Config_A Interface Configuration A (Interface_Config_A) Register
* Interface Configuration A (Interface_Config_A) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_SPI_Interface_Config_A_Addr_Ascension
*! \brief Determines Sequential Addressing Behavior (Addr_Ascension) Enumerations
* ========================================================================= */
typedef enum
{
SPI_INTERFACE_CONFIG_A_DESCEND = 0, /**< Address accessed is decremented by one for each data byte when streaming */
SPI_INTERFACE_CONFIG_A_ASCEND = 1 /**< Address accessed is incremented by one for each data byte when streaming */
} ADMW_SPI_Interface_Config_A_Addr_Ascension;
/* ==========================================================================
*! \struct ADMW_SPI_Interface_Config_A_Struct
*! \brief Interface Configuration A Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Interface_Config_A_t {
union {
struct {
uint8_t SW_ResetX : 1; /**< Second of Two of the SW_RESET Bits. */
uint8_t reserved1 : 3;
uint8_t SDO_Enable : 1; /**< Serial Data Output Pin Enable */
uint8_t Addr_Ascension : 1; /**< Determines Sequential Addressing Behavior */
uint8_t reserved6 : 1;
uint8_t SW_Reset : 1; /**< First of Two of the SW_RESET Bits. */
};
uint8_t VALUE8;
};
} ADMW_SPI_Interface_Config_A_t;
/*@}*/
/** @defgroup Chip_Type Chip Type (Chip_Type) Register
* Chip Type (Chip_Type) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_SPI_Chip_Type_Struct
*! \brief Chip Type Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Chip_Type_t {
union {
struct {
uint8_t Chip_Type : 4; /**< Precision ADC */
uint8_t reserved4 : 4;
};
uint8_t VALUE8;
};
} ADMW_SPI_Chip_Type_t;
/*@}*/
/** @defgroup Product_ID_L Product ID Low (Product_ID_L) Register
* Product ID Low (Product_ID_L) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_SPI_Product_ID_L_Struct
*! \brief Product ID Low Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Product_ID_L_t {
union {
struct {
uint8_t Product_ID : 8; /**< Product_ID[7:0] The Device Chip Type and Family */
};
uint8_t VALUE8;
};
} ADMW_SPI_Product_ID_L_t;
/*@}*/
/** @defgroup Product_ID_H Product ID High (Product_ID_H) Register
* Product ID High (Product_ID_H) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_SPI_Product_ID_H_Struct
*! \brief Product ID High Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Product_ID_H_t {
union {
struct {
uint8_t Product_ID : 8; /**< Product_ID[15:8] The Device Chip Type and Family */
};
uint8_t VALUE8;
};
} ADMW_SPI_Product_ID_H_t;
/*@}*/
/** @defgroup Scratch_Pad Scratch Pad (Scratch_Pad) Register
* Scratch Pad (Scratch_Pad) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_SPI_Scratch_Pad_Struct
*! \brief Scratch Pad Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Scratch_Pad_t {
union {
struct {
uint8_t Scratch_Value : 8; /**< Software Scratchpad */
};
uint8_t VALUE8;
};
} ADMW_SPI_Scratch_Pad_t;
/*@}*/
/** @defgroup SPI_Revision SPI Revision (SPI_Revision) Register
* SPI Revision (SPI_Revision) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_SPI_SPI_Revision_Version
*! \brief SPI Version (Version) Enumerations
* ========================================================================= */
typedef enum
{
SPI_SPI_REVISION_REV1_0 = 2 /**< Revision 1.0 */
} ADMW_SPI_SPI_Revision_Version;
/* =========================================================================
*! \enum ADMW_SPI_SPI_Revision_SPI_Type
*! \brief Always Reads as 0x2 (SPI_Type) Enumerations
* ========================================================================= */
typedef enum
{
SPI_SPI_REVISION_ADI_SPI = 0, /**< ADI_SPI */
SPI_SPI_REVISION_LPT_SPI = 2 /**< LPT_SPI */
} ADMW_SPI_SPI_Revision_SPI_Type;
/* ==========================================================================
*! \struct ADMW_SPI_SPI_Revision_Struct
*! \brief SPI Revision Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_SPI_Revision_t {
union {
struct {
uint8_t Version : 6; /**< SPI Version */
uint8_t SPI_Type : 2; /**< Always Reads as 0x2 */
};
uint8_t VALUE8;
};
} ADMW_SPI_SPI_Revision_t;
/*@}*/
/** @defgroup Vendor_L Vendor ID Low (Vendor_L) Register
* Vendor ID Low (Vendor_L) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_SPI_Vendor_L_Struct
*! \brief Vendor ID Low Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Vendor_L_t {
union {
struct {
uint8_t VID : 8; /**< VID[7:0] Analog Devices Vendor ID */
};
uint8_t VALUE8;
};
} ADMW_SPI_Vendor_L_t;
/*@}*/
/** @defgroup Vendor_H Vendor ID High (Vendor_H) Register
* Vendor ID High (Vendor_H) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_SPI_Vendor_H_Struct
*! \brief Vendor ID High Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Vendor_H_t {
union {
struct {
uint8_t VID : 8; /**< VID[15:8] Analog Devices Vendor ID */
};
uint8_t VALUE8;
};
} ADMW_SPI_Vendor_H_t;
/*@}*/
/** @defgroup Stream_Mode Stream Mode (Stream_Mode) Register
* Stream Mode (Stream_Mode) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_SPI_Stream_Mode_Struct
*! \brief Stream Mode Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Stream_Mode_t {
union {
struct {
uint8_t Loop_Count : 8; /**< Set the Data Byte Count Before Looping to Start Address */
};
uint8_t VALUE8;
};
} ADMW_SPI_Stream_Mode_t;
/*@}*/
/** @defgroup Interface_Status_A Interface Status A (Interface_Status_A) Register
* Interface Status A (Interface_Status_A) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_SPI_Interface_Status_A_Struct
*! \brief Interface Status A Register bit field structure
* ========================================================================== */
typedef struct _ADMW_SPI_Interface_Status_A_t {
union {
struct {
uint8_t Address_Invalid_Error : 1; /**< Attempt to Read/Write Nonexistent Register Address */
uint8_t Register_Partial_Access_Error : 1; /**< Set When Fewer Than Expected Number of Bytes Read/Written */
uint8_t Wr_To_Rd_Only_Reg_Error : 1; /**< Write to Read Only Register Attempted */
uint8_t CRC_Error : 1; /**< Invalid/No CRC Received */
uint8_t Clock_Count_Error : 1; /**< Incorrect Number of Clocks Detected in a Transaction */
uint8_t reserved5 : 2;
uint8_t Not_Ready_Error : 1; /**< Device Not Ready for Transaction */
};
uint8_t VALUE8;
};
} ADMW_SPI_Interface_Status_A_t;
/*@}*/
/** @defgroup Command Special Command Register (Command) Register
* Special Command Register (Command) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Command_Special_Command
*! \brief Special Command (Special_Command) Enumerations
* ========================================================================= */
typedef enum
{
CORE_COMMAND_NOP = 0, /**< No command */
CORE_COMMAND_CONVERT = 1, /**< Start ADC conversions */
CORE_COMMAND_CONVERT_WITH_RAW = 2, /**< Start conversions with added raw ADC data */
CORE_COMMAND_LATCH_CONFIG = 7, /**< Latch configuration. */
CORE_COMMAND_LOAD_LUT = 8, /**< Load LUT from flash */
CORE_COMMAND_SAVE_LUT = 9, /**< Save LUT to flash */
CORE_COMMAND_LOAD_CONFIG_1 = 24, /**< Load registers with configuration from flash */
CORE_COMMAND_SAVE_CONFIG_1 = 25 /**< Store current registers to flash configuration */
} ADMW_CORE_Command_Special_Command;
/* ==========================================================================
*! \struct ADMW_CORE_Command_Struct
*! \brief Special Command Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Command_t {
union {
struct {
uint8_t Special_Command : 8; /**< Special Command */
};
uint8_t VALUE8;
};
} ADMW_CORE_Command_t;
/*@}*/
/** @defgroup Mode Operating Mode and DRDY Control (Mode) Register
* Operating Mode and DRDY Control (Mode) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Mode_Conversion_Mode
*! \brief Conversion Mode (Conversion_Mode) Enumerations
* ========================================================================= */
typedef enum
{
CORE_MODE_SINGLECYCLE = 0, /**< Single cycle conversion mode. A cycle is completed every time a convert command is issued */
CORE_MODE_RESERVED = 1, /**< Reserved for future use */
CORE_MODE_CONTINUOUS = 2 /**< Continuous conversion mode. A cycle is started repeatedly at time specified in cycle time */
} ADMW_CORE_Mode_Conversion_Mode;
/* =========================================================================
*! \enum ADMW_CORE_Mode_Drdy_Mode
*! \brief Indicates Behavior of DRDY Pin (Drdy_Mode) Enumerations
* ========================================================================= */
typedef enum
{
CORE_MODE_DRDY_PER_CONVERSION = 0, /**< Data ready per conversion */
CORE_MODE_DRDY_PER_CYCLE = 1, /**< Data ready per cycle */
CORE_MODE_DRDY_PER_FIFO_FILL = 2 /**< Data ready per FIFO fill */
} ADMW_CORE_Mode_Drdy_Mode;
/* ==========================================================================
*! \struct ADMW_CORE_Mode_Struct
*! \brief Operating Mode and DRDY Control Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Mode_t {
union {
struct {
uint8_t Conversion_Mode : 2; /**< Conversion Mode */
uint8_t Drdy_Mode : 2; /**< Indicates Behavior of DRDY Pin */
uint8_t reserved4 : 4;
};
uint8_t VALUE8;
};
} ADMW_CORE_Mode_t;
/*@}*/
/** @defgroup Power_Config Power Configuration (Power_Config) Register
* Power Configuration (Power_Config) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Power_Config_Power_Mode_MCU
*! \brief MCU Power Mode (Power_Mode_MCU) Enumerations
* ========================================================================= */
typedef enum
{
CORE_POWER_CONFIG_ACTIVE_MODE = 0, /**< ADMW1001 is fully power up and ready to convert */
CORE_POWER_CONFIG_HIBERNATION = 1 /**< Lowest power mode. wakeup pin required to enter active mode. SPI powered down */
} ADMW_CORE_Power_Config_Power_Mode_MCU;
/* ==========================================================================
*! \struct ADMW_CORE_Power_Config_Struct
*! \brief Power Configuration Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Power_Config_t {
union {
struct {
uint8_t Power_Mode_MCU : 1; /**< MCU Power Mode */
uint8_t reserved1 : 7;
};
uint8_t VALUE8;
};
} ADMW_CORE_Power_Config_t;
/*@}*/
/** @defgroup Cycle_Control Measurement Cycle (Cycle_Control) Register
* Measurement Cycle (Cycle_Control) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Cycle_Control_GND_SW_CTRL
*! \brief Ground Switch Cycle Control (GND_SW_CTRL) Enumerations
* ========================================================================= */
typedef enum
{
CORE_CYCLE_CONTROL_OPEN_SW = 0, /**< Ground Switch Opens outside of measurement cycle to conserve power */
CORE_CYCLE_CONTROL_CLOSE_SW = 1 /**< Ground Switch Closed */
} ADMW_CORE_Cycle_Control_GND_SW_CTRL;
/* =========================================================================
*! \enum ADMW_CORE_Cycle_Control_Vbias
*! \brief Voltage Bias Global Enable (Vbias) Enumerations
* ========================================================================= */
typedef enum
{
CORE_CYCLE_CONTROL_VBIAS_DISABLE = 0, /**< Vbias disabled */
CORE_CYCLE_CONTROL_VBIAS_ENABLE = 1 /**< Enable Vbias output for the duration of a cycle */
} ADMW_CORE_Cycle_Control_Vbias;
/* =========================================================================
*! \enum ADMW_CORE_Cycle_Control_Cycle_Time_Units
*! \brief Units for Cycle Time (Cycle_Time_Units) Enumerations
* ========================================================================= */
typedef enum
{
CORE_CYCLE_CONTROL_MILLISECONDS = 0, /**< Milli-seconds */
CORE_CYCLE_CONTROL_SECONDS = 1 /**< Seconds */
} ADMW_CORE_Cycle_Control_Cycle_Time_Units;
/* =========================================================================
*! \enum ADMW_CORE_Cycle_Control_PST_MEAS_EXC_CTRL
*! \brief Disable Current Sources After Measurement Completes (PST_MEAS_EXC_CTRL) Enumerations
* ========================================================================= */
typedef enum
{
CORE_CYCLE_CONTROL_POWERCYCLE = 0, /**< */
CORE_CYCLE_CONTROL_ALWAYSON = 1 /**< */
} ADMW_CORE_Cycle_Control_PST_MEAS_EXC_CTRL;
/* ==========================================================================
*! \struct ADMW_CORE_Cycle_Control_Struct
*! \brief Measurement Cycle Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Cycle_Control_t {
union {
struct {
uint16_t Cycle_Time : 12; /**< Time Between Measurement Cycles */
uint16_t GND_SW_CTRL : 1; /**< Ground Switch Cycle Control */
uint16_t Vbias : 1; /**< Voltage Bias Global Enable */
uint16_t Cycle_Time_Units : 1; /**< Units for Cycle Time */
uint16_t PST_MEAS_EXC_CTRL : 1; /**< Disable Current Sources After Measurement Completes */
};
uint16_t VALUE16;
};
} ADMW_CORE_Cycle_Control_t;
/*@}*/
/** @defgroup Fifo_Num_Cycles Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register
* Number of Measurement Cycles to Store in FIFO (Fifo_Num_Cycles) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Fifo_Num_Cycles_Struct
*! \brief Number of Measurement Cycles to Store in FIFO Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Fifo_Num_Cycles_t {
union {
struct {
uint8_t Fifo_Num_Cycles : 8; /**< Number of Cycles to Fill the FIFO */
};
uint8_t VALUE8;
};
} ADMW_CORE_Fifo_Num_Cycles_t;
/*@}*/
/** @defgroup Status General Status (Status) Register
* General Status (Status) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Status_Struct
*! \brief General Status Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Status_t {
union {
struct {
uint8_t Configuration_Error : 1; /**< Indicates Error with Programmed Configuration */
uint8_t Alert_Active : 1; /**< Indicates One or More Sensor Alerts Active */
uint8_t Error : 1; /**< Indicates an Error */
uint8_t Drdy : 1; /**< Indicates New Sensor Result Available to Read */
uint8_t Cmd_Running : 1; /**< Indicates Special Command Active, Active Low */
uint8_t FIFO_Error : 1; /**< Indicates Error with FIFO */
uint8_t Diag_Checksum_Error : 1; /**< Indicates Error on Internal Checksum Calculations */
uint8_t LUT_Error : 1; /**< Indicates Error with One or More Lookup Tables */
};
uint8_t VALUE8;
};
} ADMW_CORE_Status_t;
/*@}*/
/** @defgroup Channel_Alert_Status Alert Status Summary (Channel_Alert_Status) Register
* Alert Status Summary (Channel_Alert_Status) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Channel_Alert_Status_Struct
*! \brief Alert Status Summary Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Channel_Alert_Status_t {
union {
struct {
uint16_t Alert_Ch0 : 1; /**< Indicates Channel 0 Alert Active */
uint16_t Alert_Ch1 : 1; /**< Indicates Channel 1 Alert Active */
uint16_t Alert_Ch2 : 1; /**< Indicates Channel 2 Alert Active */
uint16_t Alert_Ch3 : 1; /**< Indicates Channel 3 Alert Active */
uint16_t Alert_Ch4 : 1; /**< Indicates Channel 4 Alert Active */
uint16_t Alert_Ch5 : 1; /**< Indicates Channel 5Alert Active */
uint16_t Alert_Ch6 : 1; /**< Indicates Channel 6 Alert Active */
uint16_t Alert_Ch7 : 1; /**< Indicates Channel 7 Alert Active */
uint16_t Alert_Ch8 : 1; /**< Indicates Channel 8 Alert Active */
uint16_t Alert_Ch9 : 1; /**< Indicates Channel 9 Alert Active */
uint16_t Alert_Ch10 : 1; /**< Indicates Channel 10 Alert Active */
uint16_t Alert_Ch11 : 1; /**< Indicates Channel 11 Alert Active */
uint16_t Alert_Ch12 : 1; /**< Indicates Channel 12 Alert Active */
uint16_t reserved13 : 3;
};
uint16_t VALUE16;
};
} ADMW_CORE_Channel_Alert_Status_t;
/*@}*/
/** @defgroup Alert_Detail_Ch Detailed Channel Error Information (Alert_Detail_Ch) Register
* Detailed Channel Error Information (Alert_Detail_Ch) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Alert_Detail_Ch_Struct
*! \brief Detailed Channel Error Information Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Alert_Detail_Ch_t {
union {
struct {
uint16_t Result_Valid : 1; /**< Set If a Result is Valid */
uint16_t ADC_Near_Overrange : 1; /**< Indicates If the ADC is Near Overrange */
uint16_t Sensor_UnderRange : 1; /**< Indicates If the Sensor is Underrange */
uint16_t Sensor_OverRange : 1; /**< Indicates If the Sensor is Overrange */
uint16_t CJ_Soft_Fault : 1; /**< Cold Junction Soft Fault */
uint16_t CJ_Hard_Fault : 1; /**< Cold Junction Hard Fault */
uint16_t ADC_Input_OverRange : 1; /**< Indicates the ADC Input is Overrange */
uint16_t Sensor_HardFault : 1; /**< Indicates Sensor Hard Fault */
uint16_t Threshold_Exceeded : 1; /**< Channel Threshold Limits Exceeded */
uint16_t reserved9 : 7;
};
uint16_t VALUE16;
};
} ADMW_CORE_Alert_Detail_Ch_t;
/*@}*/
/** @defgroup Error_Code Code Indicating Source of Error (Error_Code) Register
* Code Indicating Source of Error (Error_Code) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Error_Code_Struct
*! \brief Code Indicating Source of Error Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Error_Code_t {
union {
struct {
uint16_t Error_Code : 16; /**< Code Indicating Type of Error */
};
uint16_t VALUE16;
};
} ADMW_CORE_Error_Code_t;
/*@}*/
/** @defgroup External_Reference_Resistor External Reference Resistor Value (External_Reference_Resistor) Register
* External Reference Resistor Value (External_Reference_Resistor) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_External_Reference_Resistor_Struct
*! \brief External Reference Resistor Value Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_External_Reference_Resistor_t {
union {
struct {
float Ext_Refin1_Value; /**< External Reference Resistor Value */
};
float VALUE32;
};
} ADMW_CORE_External_Reference_Resistor_t;
/*@}*/
/** @defgroup External_Voltage_Reference External Reference Information (External_Voltage_Reference) Register
* External Reference Information (External_Voltage_Reference) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_External_Voltage_Reference_Struct
*! \brief External Reference Information Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_External_Voltage_Reference_t {
union {
struct {
float Ext_Refin2_Value; /**< Reference Input Value */
};
float VALUE32;
};
} ADMW_CORE_External_Voltage_Reference_t;
/*@}*/
/** @defgroup AVDD_Voltage AVDD Voltage (AVDD_Voltage) Register
* AVDD Voltage (AVDD_Voltage) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_AVDD_Voltage_Struct
*! \brief AVDD Voltage Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_AVDD_Voltage_t {
union {
struct {
float Avdd_Voltage; /**< AVDD Voltage */
};
float VALUE32;
};
} ADMW_CORE_AVDD_Voltage_t;
/*@}*/
/** @defgroup Diagnostics_Control Diagnostic Control (Diagnostics_Control) Register
* Diagnostic Control (Diagnostics_Control) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Diagnostics_Control_Struct
*! \brief Diagnostic Control Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Diagnostics_Control_t {
union {
struct {
uint8_t Diag_Meas_En : 1; /**< Diagnostics Measure Enable */
uint8_t Diag_OSD_Freq : 7; /**< Diagnostics Open Sensor Detect Frequency */
};
uint8_t VALUE8;
};
} ADMW_CORE_Diagnostics_Control_t;
/*@}*/
/** @defgroup EXT_VBUFF External Reference Buffer (EXT_VBUFF) Register
* External Reference Buffer (EXT_VBUFF) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_EXT_VBUFF_EXT_VBUFF
*! \brief This field is used to configure the reference buffers (EXT_VBUFF) Enumerations
* ========================================================================= */
typedef enum
{
CORE_EXT_VBUFF_BOTH_INACTIVE_MODE = 0, /**< Both Reference Buffers Disabled */
CORE_EXT_VBUFF_BOTH_ACTIVE_MODE = 1, /**< Both Reference Buffers Enabled */
CORE_EXT_VBUFF_ONLY_VPOS_MODE = 2 /**< VREF+ Enabled Only */
} ADMW_CORE_EXT_VBUFF_EXT_VBUFF;
/* ==========================================================================
*! \struct ADMW_CORE_EXT_VBUFF_Struct
*! \brief External Reference Buffer Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_EXT_VBUFF_t {
union {
struct {
uint8_t EXT_VBUFF : 2; /**< This field is used to configure the reference buffers */
uint8_t reserved2 : 6;
};
uint8_t VALUE8;
};
} ADMW_CORE_EXT_VBUFF_t;
/*@}*/
/** @defgroup Data_FIFO FIFO Buffer of Sensor Results (Data_FIFO) Register
* FIFO Buffer of Sensor Results (Data_FIFO) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Data_FIFO_Struct
*! \brief FIFO Buffer of Sensor Results Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Data_FIFO_t {
union {
struct {
uint8_t Data_Fifo : 8; /**< FIFO Buffer of Sensor Results */
};
uint8_t VALUE8;
};
} ADMW_CORE_Data_FIFO_t;
/*@}*/
/** @defgroup Debug_Code Additional Information on Source of Alert or Errors (Debug_Code) Register
* Additional Information on Source of Alert or Errors (Debug_Code) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Debug_Code_Struct
*! \brief Additional Information on Source of Alert or Errors Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Debug_Code_t {
union {
struct {
uint32_t Debug_Code : 32; /**< Additional Information on Source of Alert or Errors */
};
uint32_t VALUE32;
};
} ADMW_CORE_Debug_Code_t;
/*@}*/
/** @defgroup Test_Reg_Access Allows Access to Test (Hidden) Registers and Features (Test_Reg_Access) Register
* Allows Access to Test (Hidden) Registers and Features (Test_Reg_Access) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Test_Reg_Access_Struct
*! \brief Allows Access to Test (Hidden) Registers and Features Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Test_Reg_Access_t {
union {
struct {
uint16_t Test_Access : 16; /**< Test Register Access. Specific Write Sequence Required */
};
uint16_t VALUE16;
};
} ADMW_CORE_Test_Reg_Access_t;
/*@}*/
/** @defgroup LUT_Select LUT Read/Write Strobe (LUT_Select) Register
* LUT Read/Write Strobe (LUT_Select) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_LUT_Select_LUT_RW
*! \brief Read or Write LUT Data (LUT_RW) Enumerations
* ========================================================================= */
typedef enum
{
CORE_LUT_SELECT_LUT_READ = 0, /**< Read addressed LUT data */
CORE_LUT_SELECT_LUT_WRITE = 1 /**< Write addressed LUT data */
} ADMW_CORE_LUT_Select_LUT_RW;
/* ==========================================================================
*! \struct ADMW_CORE_LUT_Select_Struct
*! \brief LUT Read/Write Strobe Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_LUT_Select_t {
union {
struct {
uint8_t reserved0 : 7;
uint8_t LUT_RW : 1; /**< Read or Write LUT Data */
};
uint8_t VALUE8;
};
} ADMW_CORE_LUT_Select_t;
/*@}*/
/** @defgroup LUT_Offset Offset into Selected LUT (LUT_Offset) Register
* Offset into Selected LUT (LUT_Offset) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_LUT_Offset_Struct
*! \brief Offset into Selected LUT Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_LUT_Offset_t {
union {
struct {
uint16_t LUT_Offset : 11; /**< Offset into the Lookup Table */
uint16_t reserved11 : 5;
};
uint16_t VALUE16;
};
} ADMW_CORE_LUT_Offset_t;
/*@}*/
/** @defgroup LUT_Data Data to Read/Write from Addressed LUT Entry (LUT_Data) Register
* Data to Read/Write from Addressed LUT Entry (LUT_Data) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_LUT_Data_Struct
*! \brief Data to Read/Write from Addressed LUT Entry Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_LUT_Data_t {
union {
struct {
uint8_t LUT_Data : 8; /**< Data Byte to Write to and Read from the Lookup Table */
};
uint8_t VALUE8;
};
} ADMW_CORE_LUT_Data_t;
/*@}*/
/** @defgroup Revision Hardware, Firmware Revision (Revision) Register
* Hardware, Firmware Revision (Revision) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Revision_Struct
*! \brief Hardware, Firmware Revision Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Revision_t {
union {
struct {
uint32_t Rev_Patch : 16; /**< Patch Revision Information */
uint32_t Rev_Minor : 8; /**< Minor Revision Information */
uint32_t Rev_Major : 8; /**< Major Revision Information */
};
uint32_t VALUE32;
};
} ADMW_CORE_Revision_t;
/*@}*/
/** @defgroup Channel_Count Number of Channel Occurrences per Measurement Cycle (Channel_Count) Register
* Number of Channel Occurrences per Measurement Cycle (Channel_Count) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Channel_Count_Struct
*! \brief Number of Channel Occurrences per Measurement Cycle Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Channel_Count_t {
union {
struct {
uint8_t Channel_Count : 7; /**< How Many Times Channel Appears in One Cycle */
uint8_t Channel_Enable : 1; /**< Enable Channel in Measurement Cycle */
};
uint8_t VALUE8;
};
} ADMW_CORE_Channel_Count_t;
/*@}*/
/** @defgroup Channel_Options Position of Channel Within Sequence (Channel_Options) Register
* Position of Channel Within Sequence (Channel_Options) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Channel_Options_Struct
*! \brief Position of Channel Within Sequence Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Channel_Options_t {
union {
struct {
uint8_t Channel_Priority : 4; /**< Indicates Priority or Position of This Channel in Sequence */
uint8_t reserved4 : 4;
};
uint8_t VALUE8;
};
} ADMW_CORE_Channel_Options_t;
/*@}*/
/** @defgroup Sensor_Type Sensor Select (Sensor_Type) Register
* Sensor Select (Sensor_Type) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Sensor_Type_Sensor_Type
*! \brief Sensor Type (Sensor_Type) Enumerations
* ========================================================================= */
typedef enum
{
CORE_SENSOR_TYPE_THERMOCOUPLE_T = 0, /**< Thermocouple T-Type sensor */
CORE_SENSOR_TYPE_THERMOCOUPLE_J = 1, /**< Thermocouple J-Type Sensor */
CORE_SENSOR_TYPE_THERMOCOUPLE_K = 2, /**< Thermocouple K-Type Sensor */
CORE_SENSOR_TYPE_THERMOCOUPLE_E = 3, /**< Thermocouple E-Type Sensor */
CORE_SENSOR_TYPE_THERMOCOUPLE_N = 4, /**< Thermocouple N-Type Sensor */
CORE_SENSOR_TYPE_THERMOCOUPLE_R = 5, /**< Thermocouple R-Type Sensor */
CORE_SENSOR_TYPE_THERMOCOUPLE_S = 6, /**< Thermocouple S-Type Sensor */
CORE_SENSOR_TYPE_THERMOCOUPLE_B = 7, /**< Thermocouple B-Type Sensor */
CORE_SENSOR_TYPE_THERMOCOUPLE_CUSTOM = 8, /**< Thermocouple CUSTOM-Type Sensor */
CORE_SENSOR_TYPE_RTD_2W_PT100 = 32, /**< RTD 2 wire PT100 sensor */
CORE_SENSOR_TYPE_RTD_2W_PT1000 = 33, /**< RTD 2 wire PT1000 sensor */
CORE_SENSOR_TYPE_RTD_2W_PT10 = 34, /**< RTD 2 wire PT10 sensor */
CORE_SENSOR_TYPE_RTD_2W_PT50 = 35, /**< RTD 2 wire PT50 sensor */
CORE_SENSOR_TYPE_RTD_2W_PT200 = 36, /**< RTD 2 wire PT200 sensor */
CORE_SENSOR_TYPE_RTD_2W_PT500 = 37, /**< RTD 2 wire PT500 sensor */
CORE_SENSOR_TYPE_RTD_2W_PT1000_0P00375 = 38, /**< RTD 2 wire PT1000 sensor */
CORE_SENSOR_TYPE_RTD_2W_NI120 = 39, /**< RTD 2 wire PT1000 sensor */
CORE_SENSOR_TYPE_RTD_2W_CUSTOM = 40, /**< RTD 2 wire Custom sensor */
CORE_SENSOR_TYPE_RTD_3W_PT100 = 64, /**< RTD 3 wire PT100 sensor */
CORE_SENSOR_TYPE_RTD_3W_PT1000 = 65, /**< RTD 3 wire PT1000 sensor */
CORE_SENSOR_TYPE_RTD_3W_PT10 = 66, /**< RTD 3 wire PT10 sensor */
CORE_SENSOR_TYPE_RTD_3W_PT50 = 67, /**< RTD 3 wire PT50 sensor */
CORE_SENSOR_TYPE_RTD_3W_PT200 = 68, /**< RTD 3 wire PT200 sensor */
CORE_SENSOR_TYPE_RTD_3W_PT500 = 69, /**< RTD 3 wire PT500 sensor */
CORE_SENSOR_TYPE_RTD_3W_PT1000_0P00375 = 70, /**< RTD 3 wire PT1000 sensor */
CORE_SENSOR_TYPE_RTD_3W_NI120 = 71, /**< RTD 3 wire NI120 sensor */
CORE_SENSOR_TYPE_RTD_3W_CUSTOM = 72, /**< RTD 3 wire Custom sensor */
CORE_SENSOR_TYPE_RTD_4W_PT100 = 96, /**< RTD 4 wire PT100 sensor */
CORE_SENSOR_TYPE_RTD_4W_PT1000 = 97, /**< RTD 4 wire PT1000 sensor */
CORE_SENSOR_TYPE_RTD_4W_PT10 = 98, /**< RTD 4 wire PT10 sensor */
CORE_SENSOR_TYPE_RTD_4W_PT50 = 99, /**< RTD 4 wire PT50 sensor */
CORE_SENSOR_TYPE_RTD_4W_PT200 = 100, /**< RTD 4 wire PT200 sensor */
CORE_SENSOR_TYPE_RTD_4W_PT500 = 101, /**< RTD 4 wire PT500 sensor */
CORE_SENSOR_TYPE_RTD_4W_PT1000_0P00375 = 102, /**< RTD 4 wire PT1000 0.00375 sensor */
CORE_SENSOR_TYPE_RTD_4W_NI120 = 103, /**< RTD 4 wire NI120 */
CORE_SENSOR_TYPE_RTD_4W_CUSTOM = 104, /**< RTD 4 wire Custom sensor */
CORE_SENSOR_TYPE_THERMISTOR_44004_44033_2P252K_AT_25C = 128, /**< THERMISTOR_44004_44033_2P252K_AT_25C */
CORE_SENSOR_TYPE_THERMISTOR_44005_44030_3K_AT_25C = 129, /**< THERMISTOR_44005_44030_3K_AT_25C */
CORE_SENSOR_TYPE_THERMISTOR_44007_44034_5K_AT_25C = 130, /**< THERMISTOR_44007_44034_5K_AT_25C */
CORE_SENSOR_TYPE_THERMISTOR_44006_44031_10K_AT_25C = 131, /**< THERMISTOR_44006_44031_10K_AT_25C */
CORE_SENSOR_TYPE_THERMISTOR_44008_44032_30K_AT_25C = 132, /**< THERMISTOR_44008_44032_30K_AT_25C */
CORE_SENSOR_TYPE_THERMISTOR_YSI_400 = 133, /**< THERMISTOR_YSI_400 */
CORE_SENSOR_TYPE_THERMISTOR_SPECTRUM_1003K_1K = 134, /**< THERMISTOR_SPECTRUM_1003K_1K */
CORE_SENSOR_TYPE_THERMISTOR_CUSTOM_STEINHART_HART = 135, /**< THERMISTOR_CUSTOM_STEINHART_HART */
CORE_SENSOR_TYPE_THERMISTOR_CUSTOM_TABLE = 136, /**< THERMISTOR_CUSTOM_TABLE */
CORE_SENSOR_TYPE_BRIDGE_4WIRE = 168, /**< Bridge 4 wire sensor */
CORE_SENSOR_TYPE_BRIDGE_6WIRE = 200, /**< Bridge 6 wire sensor */
CORE_SENSOR_TYPE_DIODE = 224, /**< DIODE Temperature Sensor */
CORE_SENSOR_TYPE_SINGLE_ENDED_ABSOLUTE = 576, /**< Voltage Input Single Ended on V+ */
CORE_SENSOR_TYPE_DIFFERENTIAL_ABSOLUTE = 640, /**< Voltage Input Differential Ended on V+ and V- */
CORE_SENSOR_TYPE_SINGLE_ENDED_RATIO = 656, /**< Ratiometeric Output, Voltage_IN/Voltage_Reference */
CORE_SENSOR_TYPE_DIFFERENTIAL_RATIO = 672, /**< Ratiometeric Output, Voltage_IN/Voltage_Reference */
CORE_SENSOR_TYPE_I2C_HUMIDITY = 2112, /**< I2C humidity sensor B */
CORE_SENSOR_TYPE_I2C_TEMPERATURE_ADT742X = 2218 /**< ADI Precision I2C Digital Temperature Sensor */
} ADMW_CORE_Sensor_Type_Sensor_Type;
/* ==========================================================================
*! \struct ADMW_CORE_Sensor_Type_Struct
*! \brief Sensor Select Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Sensor_Type_t {
union {
struct {
uint16_t Sensor_Type : 12; /**< Sensor Type */
uint16_t reserved12 : 4;
};
uint16_t VALUE16;
};
} ADMW_CORE_Sensor_Type_t;
/*@}*/
/** @defgroup Sensor_Details Sensor Details (Sensor_Details) Register
* Sensor Details (Sensor_Details) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Sensor_Details_Measurement_Units
*! \brief Units of Sensor Measurement (Measurement_Units) Enumerations
* ========================================================================= */
typedef enum
{
CORE_SENSOR_DETAILS_UNITS_UNSPECIFIED = 0, /**< Not Specified */
CORE_SENSOR_DETAILS_UNITS_RESERVED = 1, /**< Reserved */
CORE_SENSOR_DETAILS_UNITS_DEGC = 2, /**< Degrees C */
CORE_SENSOR_DETAILS_UNITS_DEGF = 3 /**< Degrees F */
} ADMW_CORE_Sensor_Details_Measurement_Units;
/* =========================================================================
*! \enum ADMW_CORE_Sensor_Details_LUT_Select
*! \brief Lookup Table Select (LUT_Select) Enumerations
* ========================================================================= */
typedef enum
{
CORE_SENSOR_DETAILS_LUT_DEFAULT = 0, /**< Default lookup table for selected sensor type */
CORE_SENSOR_DETAILS_LUT_CUSTOM = 1, /**< User defined custom lookup table. */
CORE_SENSOR_DETAILS_LUT_RESERVED = 2 /**< Reserved */
} ADMW_CORE_Sensor_Details_LUT_Select;
/* =========================================================================
*! \enum ADMW_CORE_Sensor_Details_Reference_Select
*! \brief Reference Selection (Reference_Select) Enumerations
* ========================================================================= */
typedef enum
{
CORE_SENSOR_DETAILS_REF_VINT = 0, /**< Internal voltage reference (1.2V) */
CORE_SENSOR_DETAILS_REF_VEXT1 = 1, /**< External voltage reference applied to VERF+ and VREF- */
CORE_SENSOR_DETAILS_REF_AVDD = 3 /**< AVDD supply internally used as reference */
} ADMW_CORE_Sensor_Details_Reference_Select;
/* =========================================================================
*! \enum ADMW_CORE_Sensor_Details_PGA_Gain
*! \brief PGA Gain (PGA_Gain) Enumerations
* ========================================================================= */
typedef enum
{
CORE_SENSOR_DETAILS_PGA_GAIN_1 = 0, /**< Gain of 1 */
CORE_SENSOR_DETAILS_PGA_GAIN_2 = 1, /**< Gain of 2 */
CORE_SENSOR_DETAILS_PGA_GAIN_4 = 2, /**< Gain of 4 */
CORE_SENSOR_DETAILS_PGA_GAIN_8 = 3, /**< Gain of 8 */
CORE_SENSOR_DETAILS_PGA_GAIN_16 = 4, /**< Gain of 16 */
CORE_SENSOR_DETAILS_PGA_GAIN_32 = 5, /**< Gain of 32 */
CORE_SENSOR_DETAILS_PGA_GAIN_64 = 6, /**< Gain of 64 */
CORE_SENSOR_DETAILS_PGA_GAIN_128 = 7 /**< Gain of 128 */
} ADMW_CORE_Sensor_Details_PGA_Gain;
/* =========================================================================
*! \enum ADMW_CORE_Sensor_Details_RTD_Curve
*! \brief Select RTD Curve for Linearization (RTD_Curve) Enumerations
* ========================================================================= */
typedef enum
{
CORE_SENSOR_DETAILS_EUROPEAN_CURVE = 0, /**< European curve */
CORE_SENSOR_DETAILS_AMERICAN_CURVE = 1, /**< American curve */
CORE_SENSOR_DETAILS_JAPANESE_CURVE = 2, /**< Japanese curve */
CORE_SENSOR_DETAILS_ITS90_CURVE = 3 /**< ITS-90 curve */
} ADMW_CORE_Sensor_Details_RTD_Curve;
/* ==========================================================================
*! \struct ADMW_CORE_Sensor_Details_Struct
*! \brief Sensor Details Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Sensor_Details_t {
union {
struct {
uint32_t Measurement_Units : 4; /**< Units of Sensor Measurement */
uint32_t Compensation_Channel : 4; /**< Indicates Which Channel Used to Compensate the Sensor Result */
uint32_t reserved8 : 7;
uint32_t LUT_Select : 2; /**< Lookup Table Select */
uint32_t Do_Not_Publish : 1; /**< Do Not Publish Channel Result */
uint32_t reserved18 : 2;
uint32_t Reference_Select : 4; /**< Reference Selection */
uint32_t PGA_Gain : 3; /**< PGA Gain */
uint32_t RTD_Curve : 2; /**< Select RTD Curve for Linearization */
uint32_t reserved29 : 2;
uint32_t Compensation_Disable : 1; /**< This Bit Indicates Compensation Data Must Not Be Used */
};
uint32_t VALUE32;
};
} ADMW_CORE_Sensor_Details_t;
/*@}*/
/** @defgroup Channel_Excitation Excitation Current (Channel_Excitation) Register
* Excitation Current (Channel_Excitation) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Channel_Excitation_IOUT_Excitation_Current
*! \brief Current Source Value (IOUT_Excitation_Current) Enumerations
* ========================================================================= */
typedef enum
{
CORE_CHANNEL_EXCITATION_NONE = 0, /**< Excitation Current Disabled */
CORE_CHANNEL_EXCITATION_RESERVED = 1, /**< Reserved */
CORE_CHANNEL_EXCITATION_IEXC_10UA = 2, /**< 10 \mu;A */
CORE_CHANNEL_EXCITATION_RESERVED2 = 3, /**< Reserved */
CORE_CHANNEL_EXCITATION_IEXC_50UA = 4, /**< 50 \mu;A */
CORE_CHANNEL_EXCITATION_IEXC_100UA = 5, /**< 100 \mu;A */
CORE_CHANNEL_EXCITATION_IEXC_250UA = 6, /**< 250 \mu;A */
CORE_CHANNEL_EXCITATION_IEXC_500UA = 7, /**< 500 \mu;A */
CORE_CHANNEL_EXCITATION_IEXC_1000UA = 8, /**< 1000 \mu;A */
CORE_CHANNEL_EXCITATION_EXTERNAL = 15 /**< External current sourced */
} ADMW_CORE_Channel_Excitation_IOUT_Excitation_Current;
/* =========================================================================
*! \enum ADMW_CORE_Channel_Excitation_IOUT_Diode_Ratio
*! \brief Modify Current Ratios Used for Diode Sensor (IOUT_Diode_Ratio) Enumerations
* ========================================================================= */
typedef enum
{
CORE_CHANNEL_EXCITATION_DIODE_2PT_10UA_100UA = 0, /**< 2 Current measurement 10uA 100uA */
CORE_CHANNEL_EXCITATION_DIODE_2PT_20UA_160UA = 1, /**< 2 Current measurement 20uA 160uA */
CORE_CHANNEL_EXCITATION_DIODE_2PT_50UA_300UA = 2, /**< 2 Current measurement 50uA 300uA */
CORE_CHANNEL_EXCITATION_DIODE_2PT_100UA_600UA = 3, /**< 2 Current measurement 100uA 600uA */
CORE_CHANNEL_EXCITATION_DIODE_3PT_10UA_50UA_100UA = 4, /**< 3 current measuremet 10uA 50uA 100uA */
CORE_CHANNEL_EXCITATION_DIODE_3PT_20UA_100UA_160UA = 5, /**< 3 current measuremet 20uA 100uA 160uA */
CORE_CHANNEL_EXCITATION_DIODE_3PT_50UA_150UA_300UA = 6, /**< 3 current measuremet 50uA 150uA 300uA */
CORE_CHANNEL_EXCITATION_DIODE_3PT_100UA_300UA_600UA = 7 /**< 3 current measuremet 100uA 300uA 600uA */
} ADMW_CORE_Channel_Excitation_IOUT_Diode_Ratio;
/* ==========================================================================
*! \struct ADMW_CORE_Channel_Excitation_Struct
*! \brief Excitation Current Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Channel_Excitation_t {
union {
struct {
uint16_t IOUT_Excitation_Current : 4; /**< Current Source Value */
uint16_t reserved4 : 2;
uint16_t IOUT_Diode_Ratio : 3; /**< Modify Current Ratios Used for Diode Sensor */
uint16_t reserved9 : 7;
};
uint16_t VALUE16;
};
} ADMW_CORE_Channel_Excitation_t;
/*@}*/
/** @defgroup Settling_Time Settling Time (Settling_Time) Register
* Settling Time (Settling_Time) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Settling_Time_Struct
*! \brief Settling Time Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Settling_Time_t {
union {
struct {
uint16_t Settling_Time : 8; /**< Additional Settling Time in Milliseconds. Max 255ms */
uint16_t reserved8 : 8;
};
uint16_t VALUE16;
};
} ADMW_CORE_Settling_Time_t;
/*@}*/
/** @defgroup Measurement_Setup ADC Measurement Setup (Measurement_Setup) Register
* ADC Measurement Setup (Measurement_Setup) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Measurement_Setup_NOTCH_EN_2
*! \brief Enable Notch 2 Filter Mode (NOTCH_EN_2) Enumerations
* ========================================================================= */
typedef enum
{
CORE_MEASUREMENT_SETUP_NOTCH_DIS = 0, /**< Disable notch filter */
CORE_MEASUREMENT_SETUP_NOTCH_EN = 1 /**< Enable notch 2 filter option. */
} ADMW_CORE_Measurement_Setup_NOTCH_EN_2;
/* =========================================================================
*! \enum ADMW_CORE_Measurement_Setup_Chop_Mode
*! \brief Enabled and Disable Chop Mode (Chop_Mode) Enumerations
* ========================================================================= */
typedef enum
{
CORE_MEASUREMENT_SETUP_DISABLE_CHOP = 0, /**< ADC front end chopping disabled */
CORE_MEASUREMENT_SETUP_ENABLE_CHOP = 1 /**< ADC front end chopping enabled */
} ADMW_CORE_Measurement_Setup_Chop_Mode;
/* =========================================================================
*! \enum ADMW_CORE_Measurement_Setup_ADC_Filter_Type
*! \brief ADC Digital Filter Type (ADC_Filter_Type) Enumerations
* ========================================================================= */
typedef enum
{
CORE_MEASUREMENT_SETUP_ENABLE_SINC4 = 0, /**< Enabled SINC4 filter */
CORE_MEASUREMENT_SETUP_ENABLE_SINC3 = 1 /**< Enabled SINC3 filter */
} ADMW_CORE_Measurement_Setup_ADC_Filter_Type;
/* =========================================================================
*! \enum ADMW_CORE_Measurement_Setup_Buffer_Bypass
*! \brief Disable Buffers (Buffer_Bypass) Enumerations
* ========================================================================= */
typedef enum
{
CORE_MEASUREMENT_SETUP_BUFFERS_ENABLED = 0, /**< Input buffers enabled */
CORE_MEASUREMENT_SETUP_BUFFERS_DISABLED = 1 /**< Input buffers disabled */
} ADMW_CORE_Measurement_Setup_Buffer_Bypass;
/* ==========================================================================
*! \struct ADMW_CORE_Measurement_Setup_Struct
*! \brief ADC Measurement Setup Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Measurement_Setup_t {
union {
struct {
uint32_t ADC_SF : 7; /**< ADC Digital Filter Speed */
uint32_t reserved7 : 1;
uint32_t NOTCH_EN_2 : 1; /**< Enable Notch 2 Filter Mode */
uint32_t reserved9 : 1;
uint32_t Chop_Mode : 1; /**< Enabled and Disable Chop Mode */
uint32_t reserved11 : 1;
uint32_t ADC_Filter_Type : 1; /**< ADC Digital Filter Type */
uint32_t reserved13 : 2;
uint32_t Buffer_Bypass : 1; /**< Disable Buffers */
uint32_t reserved16 : 16;
};
uint32_t VALUE32;
};
} ADMW_CORE_Measurement_Setup_t;
/*@}*/
/** @defgroup Ideality_Factor Diode Ideality Factor Register (Ideality_Factor) Register
* Diode Ideality Factor Register (Ideality_Factor) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Ideality_Factor_Struct
*! \brief Diode Ideality Factor Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Ideality_Factor_t {
union {
struct {
float32_t Ideality_Factor; /**< Diode Ideality Factor, Default 1.003. */
};
float32_t VALUE32;
};
} ADMW_CORE_Ideality_Factor_t;
/*@}*/
/** @defgroup High_Threshold_Limit High Threshold (High_Threshold_Limit) Register
* High Threshold (High_Threshold_Limit) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_High_Threshold_Limit_Struct
*! \brief High Threshold Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_High_Threshold_Limit_t {
union {
struct {
float High_Threshold; /**< Upper Limit for Sensor Alert Comparison */
};
float VALUE32;
};
} ADMW_CORE_High_Threshold_Limit_t;
/*@}*/
/** @defgroup Low_Threshold_Limit Low Threshold (Low_Threshold_Limit) Register
* Low Threshold (Low_Threshold_Limit) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Low_Threshold_Limit_Struct
*! \brief Low Threshold Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Low_Threshold_Limit_t {
union {
struct {
float Low_Threshold; /**< Lower Limit for Sensor Alert Comparison */
};
float VALUE32;
};
} ADMW_CORE_Low_Threshold_Limit_t;
/*@}*/
/** @defgroup Sensor_Offset Sensor Offset Adjustment (Sensor_Offset) Register
* Sensor Offset Adjustment (Sensor_Offset) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Sensor_Offset_Struct
*! \brief Sensor Offset Adjustment Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Sensor_Offset_t {
union {
struct {
float Sensor_Offset; /**< Sensor Offset Adjustment */
};
float VALUE32;
};
} ADMW_CORE_Sensor_Offset_t;
/*@}*/
/** @defgroup Sensor_Gain Sensor Gain Adjustment (Sensor_Gain) Register
* Sensor Gain Adjustment (Sensor_Gain) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Sensor_Gain_Struct
*! \brief Sensor Gain Adjustment Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Sensor_Gain_t {
union {
struct {
float Sensor_Gain; /**< Sensor Gain Adjustment */
};
float VALUE32;
};
} ADMW_CORE_Sensor_Gain_t;
/*@}*/
/** @defgroup Channel_Skip Indicates If Channel Will Skip Some Measurement Cycles (Channel_Skip) Register
* Indicates If Channel Will Skip Some Measurement Cycles (Channel_Skip) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Channel_Skip_Struct
*! \brief Indicates If Channel Will Skip Some Measurement Cycles Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Channel_Skip_t {
union {
struct {
uint16_t Channel_Skip : 8; /**< Indicates If Channel Will Skip Some Measurement Cycles */
uint16_t reserved8 : 8;
};
uint16_t VALUE16;
};
} ADMW_CORE_Channel_Skip_t;
/*@}*/
/** @defgroup Sensor_Parameter Sensor Parameter Adjustment (Sensor_Parameter) Register
* Sensor Parameter Adjustment (Sensor_Parameter) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Sensor_Parameter_Struct
*! \brief Sensor Parameter Adjustment Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Sensor_Parameter_t {
union {
struct {
float Sensor_Parameter; /**< Sensor Parameter Adjustment */
};
float VALUE32;
};
} ADMW_CORE_Sensor_Parameter_t;
/*@}*/
/** @defgroup Digital_Sensor_Config Digital Sensor Data Coding (Digital_Sensor_Config) Register
* Digital Sensor Data Coding (Digital_Sensor_Config) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Digital_Sensor_Config_Digital_Sensor_Coding
*! \brief Data Encoding of Sensor Result (Digital_Sensor_Coding) Enumerations
* ========================================================================= */
typedef enum
{
CORE_DIGITAL_SENSOR_CONFIG_CODING_NONE = 0, /**< None/Invalid */
CORE_DIGITAL_SENSOR_CONFIG_CODING_UNIPOLAR = 1, /**< Unipolar */
CORE_DIGITAL_SENSOR_CONFIG_CODING_TWOS_COMPL = 2, /**< Twos complement */
CORE_DIGITAL_SENSOR_CONFIG_CODING_OFFSET_BINARY = 3 /**< Offset binary */
} ADMW_CORE_Digital_Sensor_Config_Digital_Sensor_Coding;
/* ==========================================================================
*! \struct ADMW_CORE_Digital_Sensor_Config_Struct
*! \brief Digital Sensor Data Coding Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Digital_Sensor_Config_t {
union {
struct {
uint16_t Digital_Sensor_Coding : 2; /**< Data Encoding of Sensor Result */
uint16_t Digital_Sensor_Little_Endian : 1; /**< Data Endianness of Sensor Result */
uint16_t Digital_Sensor_Left_Aligned : 1; /**< Data Alignment Within the Data Frame */
uint16_t Digital_Sensor_Bit_Offset : 4; /**< Data Bit Offset, Relative to Alignment */
uint16_t Digital_Sensor_Read_Bytes : 3; /**< Number of Bytes to Read from the Sensor */
uint16_t Digital_Sensor_Data_Bits : 5; /**< Number of Relevant Data Bits */
};
uint16_t VALUE16;
};
} ADMW_CORE_Digital_Sensor_Config_t;
/*@}*/
/** @defgroup Digital_Sensor_Address Sensor Address (Digital_Sensor_Address) Register
* Sensor Address (Digital_Sensor_Address) Register.
* @{
*/
/* ==========================================================================
*! \struct ADMW_CORE_Digital_Sensor_Address_Struct
*! \brief Sensor Address Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Digital_Sensor_Address_t {
union {
struct {
uint8_t Digital_Sensor_Address : 8; /**< I2C Address or Write Address Command for SPI Sensor */
};
uint8_t VALUE8;
};
} ADMW_CORE_Digital_Sensor_Address_t;
/*@}*/
/** @defgroup Digital_Sensor_Comms Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register
* Digital Sensor Communication Clock Configuration (Digital_Sensor_Comms) Register.
* @{
*/
/* =========================================================================
*! \enum ADMW_CORE_Digital_Sensor_Comms_SPI_Clock
*! \brief Controls Clock Frequency for SPI Sensors (SPI_Clock) Enumerations
* ========================================================================= */
typedef enum
{
CORE_DIGITAL_SENSOR_COMMS_SPI_8MHZ = 0, /**< 8MHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_4MHZ = 1, /**< 4MHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_2MHZ = 2, /**< 2MHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_1MHZ = 3, /**< 1MHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_500KHZ = 4, /**< 500kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_250KHZ = 5, /**< 250kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_125KHZ = 6, /**< 125kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_62P5KHZ = 7, /**< 62.5kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_31P3KHZ = 8, /**< 31.25kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_15P6KHZ = 9, /**< 15.625kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_7P8KHZ = 10, /**< 7.8kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_3P9KHZ = 11, /**< 3.9kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_1P9KHZ = 12, /**< 1.95kHz */
CORE_DIGITAL_SENSOR_COMMS_SPI_977HZ = 13, /**< 977Hz */
CORE_DIGITAL_SENSOR_COMMS_SPI_488HZ = 14, /**< 488Hz */
CORE_DIGITAL_SENSOR_COMMS_SPI_244HZ = 15 /**< 244Hz */
} ADMW_CORE_Digital_Sensor_Comms_SPI_Clock;
/* =========================================================================
*! \enum ADMW_CORE_Digital_Sensor_Comms_I2C_Clock
*! \brief Controls SCLK Frequency for I2C Sensors (I2C_Clock) Enumerations
* ========================================================================= */
typedef enum
{
CORE_DIGITAL_SENSOR_COMMS_I2C_100K = 0, /**< 100kHz SCL */
CORE_DIGITAL_SENSOR_COMMS_I2C_400K = 1, /**< 400kHz SCL */
CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED1 = 2, /**< Reserved */
CORE_DIGITAL_SENSOR_COMMS_I2C_RESERVED2 = 3 /**< Reserved */
} ADMW_CORE_Digital_Sensor_Comms_I2C_Clock;
/* =========================================================================
*! \enum ADMW_CORE_Digital_Sensor_Comms_SPI_Mode
*! \brief Configuration for Sensor SPI Protocol (SPI_Mode) Enumerations
* ========================================================================= */
typedef enum
{
CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_0 = 0, /**< Clock polarity = 0 Clock phase = 0 */
CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_1 = 1, /**< Clock polarity = 0 Clock phase = 1 */
CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_2 = 2, /**< Clock polarity = 1 Clock phase = 0 */
CORE_DIGITAL_SENSOR_COMMS_SPI_MODE_3 = 3 /**< Clock polarity = 1 Clock phase = 1 */
} ADMW_CORE_Digital_Sensor_Comms_SPI_Mode;
/* ==========================================================================
*! \struct ADMW_CORE_Digital_Sensor_Comms_Struct
*! \brief Digital Sensor Communication Clock Configuration Register bit field structure
* ========================================================================== */
typedef struct _ADMW_CORE_Digital_Sensor_Comms_t {
union {
struct {
uint16_t reserved0 : 1;
uint16_t SPI_Clock : 4; /**< Controls Clock Frequency for SPI Sensors */
uint16_t I2C_Clock : 2; /**< Controls SCLK Frequency for I2C Sensors */
uint16_t reserved7 : 3;
uint16_t SPI_Mode : 2; /**< Configuration for Sensor SPI Protocol */
uint16_t reserved12 : 4;
};
uint16_t VALUE16;
};
} ADMW_CORE_Digital_Sensor_Comms_t;
/*@}*/
#if defined (__CC_ARM)
#pragma pop
#endif
#endif