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targets/hal/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/spi_api.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "spi_api.h"
<> 144:ef7eb2e8f9f7 17
<> 144:ef7eb2e8f9f7 18 #include <math.h>
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 21 #include "pinmap.h"
<> 144:ef7eb2e8f9f7 22
<> 144:ef7eb2e8f9f7 23 static const PinMap PinMap_SPI_SCLK[] = {
<> 144:ef7eb2e8f9f7 24 {PTB0, SPI_0, 3},
<> 144:ef7eb2e8f9f7 25 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 26 };
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 static const PinMap PinMap_SPI_MOSI[] = {
<> 144:ef7eb2e8f9f7 29 {PTA7, SPI_0, 3},
<> 144:ef7eb2e8f9f7 30 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 31 };
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 static const PinMap PinMap_SPI_MISO[] = {
<> 144:ef7eb2e8f9f7 34 {PTA6, SPI_0, 3},
<> 144:ef7eb2e8f9f7 35 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 36 };
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 static const PinMap PinMap_SPI_SSEL[] = {
<> 144:ef7eb2e8f9f7 39 {PTA5, SPI_0, 3},
<> 144:ef7eb2e8f9f7 40 {NC , NC , 0}
<> 144:ef7eb2e8f9f7 41 };
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
<> 144:ef7eb2e8f9f7 44 // determine the SPI to use
<> 144:ef7eb2e8f9f7 45 SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 46 SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 47 SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 48 SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 49 SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
<> 144:ef7eb2e8f9f7 50 SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 obj->spi = (SPI_Type*)pinmap_merge(spi_data, spi_cntl);
<> 144:ef7eb2e8f9f7 53 MBED_ASSERT((int)obj->spi != NC);
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 // enable power and clocking
<> 144:ef7eb2e8f9f7 56 switch ((int)obj->spi) {
<> 144:ef7eb2e8f9f7 57 case SPI_0:
<> 144:ef7eb2e8f9f7 58 SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK);
<> 144:ef7eb2e8f9f7 59 SIM->SCGC4 |= SIM_SCGC4_SPI0_MASK;
<> 144:ef7eb2e8f9f7 60 break;
<> 144:ef7eb2e8f9f7 61 }
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 // enable SPI
<> 144:ef7eb2e8f9f7 64 obj->spi->C1 |= SPI_C1_SPE_MASK;
<> 144:ef7eb2e8f9f7 65
<> 144:ef7eb2e8f9f7 66 // pin out the spi pins
<> 144:ef7eb2e8f9f7 67 pinmap_pinout(mosi, PinMap_SPI_MOSI);
<> 144:ef7eb2e8f9f7 68 pinmap_pinout(miso, PinMap_SPI_MISO);
<> 144:ef7eb2e8f9f7 69 pinmap_pinout(sclk, PinMap_SPI_SCLK);
<> 144:ef7eb2e8f9f7 70 if (ssel != NC) {
<> 144:ef7eb2e8f9f7 71 pinmap_pinout(ssel, PinMap_SPI_SSEL);
<> 144:ef7eb2e8f9f7 72 }
<> 144:ef7eb2e8f9f7 73 }
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 void spi_free(spi_t *obj) {
<> 144:ef7eb2e8f9f7 76 // [TODO]
<> 144:ef7eb2e8f9f7 77 }
<> 144:ef7eb2e8f9f7 78 void spi_format(spi_t *obj, int bits, int mode, int slave) {
<> 144:ef7eb2e8f9f7 79 MBED_ASSERT(bits == 8);
<> 144:ef7eb2e8f9f7 80 MBED_ASSERT((mode >= 0) && (mode <= 3));
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 uint8_t polarity = (mode & 0x2) ? 1 : 0;
<> 144:ef7eb2e8f9f7 83 uint8_t phase = (mode & 0x1) ? 1 : 0;
<> 144:ef7eb2e8f9f7 84 uint8_t c1_data = ((!slave) << 4) | (polarity << 3) | (phase << 2);
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 // clear MSTR, CPOL and CPHA bits
<> 144:ef7eb2e8f9f7 87 obj->spi->C1 &= ~(0x7 << 2);
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 // write new value
<> 144:ef7eb2e8f9f7 90 obj->spi->C1 |= c1_data;
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 void spi_frequency(spi_t *obj, int hz) {
<> 144:ef7eb2e8f9f7 94 uint32_t error = 0;
<> 144:ef7eb2e8f9f7 95 uint32_t p_error = 0xffffffff;
<> 144:ef7eb2e8f9f7 96 uint32_t ref = 0;
<> 144:ef7eb2e8f9f7 97 uint8_t spr = 0;
<> 144:ef7eb2e8f9f7 98 uint8_t ref_spr = 0;
<> 144:ef7eb2e8f9f7 99 uint8_t ref_prescaler = 0;
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 // bus clk
<> 144:ef7eb2e8f9f7 102 uint32_t PCLK = SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
<> 144:ef7eb2e8f9f7 103 uint8_t prescaler = 1;
<> 144:ef7eb2e8f9f7 104 uint8_t divisor = 2;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 for (prescaler = 1; prescaler <= 8; prescaler++) {
<> 144:ef7eb2e8f9f7 107 divisor = 2;
<> 144:ef7eb2e8f9f7 108 for (spr = 0; spr <= 8; spr++) {
<> 144:ef7eb2e8f9f7 109 ref = PCLK / (prescaler*divisor);
<> 144:ef7eb2e8f9f7 110 if (ref > (uint32_t)hz)
<> 144:ef7eb2e8f9f7 111 continue;
<> 144:ef7eb2e8f9f7 112 error = hz - ref;
<> 144:ef7eb2e8f9f7 113 if (error < p_error) {
<> 144:ef7eb2e8f9f7 114 ref_spr = spr;
<> 144:ef7eb2e8f9f7 115 ref_prescaler = prescaler - 1;
<> 144:ef7eb2e8f9f7 116 p_error = error;
<> 144:ef7eb2e8f9f7 117 }
<> 144:ef7eb2e8f9f7 118 divisor *= 2;
<> 144:ef7eb2e8f9f7 119 }
<> 144:ef7eb2e8f9f7 120 }
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 // set SPPR and SPR
<> 144:ef7eb2e8f9f7 123 obj->spi->BR = ((ref_prescaler & 0x7) << 4) | (ref_spr & 0xf);
<> 144:ef7eb2e8f9f7 124 }
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 static inline int spi_writeable(spi_t * obj) {
<> 144:ef7eb2e8f9f7 127 return (obj->spi->S & SPI_S_SPTEF_MASK) ? 1 : 0;
<> 144:ef7eb2e8f9f7 128 }
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 static inline int spi_readable(spi_t * obj) {
<> 144:ef7eb2e8f9f7 131 return (obj->spi->S & SPI_S_SPRF_MASK) ? 1 : 0;
<> 144:ef7eb2e8f9f7 132 }
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 int spi_master_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 135 // wait tx buffer empty
<> 144:ef7eb2e8f9f7 136 while(!spi_writeable(obj));
<> 144:ef7eb2e8f9f7 137 obj->spi->D = (value & 0xff);
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 // wait rx buffer full
<> 144:ef7eb2e8f9f7 140 while (!spi_readable(obj));
<> 144:ef7eb2e8f9f7 141 return obj->spi->D & 0xff;
<> 144:ef7eb2e8f9f7 142 }
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 int spi_slave_receive(spi_t *obj) {
<> 144:ef7eb2e8f9f7 145 return spi_readable(obj);
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 int spi_slave_read(spi_t *obj) {
<> 144:ef7eb2e8f9f7 149 return obj->spi->D;
<> 144:ef7eb2e8f9f7 150 }
<> 144:ef7eb2e8f9f7 151
<> 144:ef7eb2e8f9f7 152 void spi_slave_write(spi_t *obj, int value) {
<> 144:ef7eb2e8f9f7 153 while (!spi_writeable(obj));
<> 144:ef7eb2e8f9f7 154 obj->spi->D = value;
<> 144:ef7eb2e8f9f7 155 }