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targets/TARGET_NUVOTON/TARGET_NUC472/device/NUC472_442.h@181:96ed750bd169, 2018-01-17 (annotated)

Committer:
Anna Bridge
Date:
Wed Jan 17 15:23:54 2018 +0000
Revision:
181:96ed750bd169
Parent:
178:79309dc6340a 
mbed-dev libray. Release version 158

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file NUC472_442.h
<> 144:ef7eb2e8f9f7 3 * @version V1.00
<> 144:ef7eb2e8f9f7 4 * $Revision: 156 $
<> 144:ef7eb2e8f9f7 5 * $Date: 14/10/08 9:26a $
<> 144:ef7eb2e8f9f7 6 * @brief NUC472/NUC442 peripheral access layer header file.
<> 144:ef7eb2e8f9f7 7 * This file contains all the peripheral register's definitions,
<> 144:ef7eb2e8f9f7 8 * bits definitions and memory mapping for NuMicro NUC472/NUC442 MCU.
<> 144:ef7eb2e8f9f7 9 * @note
<> 144:ef7eb2e8f9f7 10 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
<> 144:ef7eb2e8f9f7 11 *****************************************************************************/
<> 144:ef7eb2e8f9f7 12 /**
<> 144:ef7eb2e8f9f7 13 \mainpage NuMicro NUC472/NUC442 MCU Driver Reference Guide
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * <b>Introduction</b>
<> 144:ef7eb2e8f9f7 16 *
<> 144:ef7eb2e8f9f7 17 * This user manual describes the usage of NUC472/NUC442 MCU device driver
<> 144:ef7eb2e8f9f7 18 *
<> 144:ef7eb2e8f9f7 19 * <b>Disclaimer</b>
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * The Software is furnished "AS IS", without warranty as to performance or results, and
<> 144:ef7eb2e8f9f7 22 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
<> 144:ef7eb2e8f9f7 23 * warranties, express, implied or otherwise, with regard to the Software, its use, or
<> 144:ef7eb2e8f9f7 24 * operation, including without limitation any and all warranties of merchantability, fitness
<> 144:ef7eb2e8f9f7 25 * for a particular purpose, and non-infringement of intellectual property rights.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * <b>Important Notice</b>
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * Nuvoton Products are neither intended nor warranted for usage in systems or equipment,
<> 144:ef7eb2e8f9f7 30 * any malfunction or failure of which may cause loss of human life, bodily injury or severe
<> 144:ef7eb2e8f9f7 31 * property damage. Such applications are deemed, "Insecure Usage".
<> 144:ef7eb2e8f9f7 32 *
<> 144:ef7eb2e8f9f7 33 * Insecure usage includes, but is not limited to: equipment for surgical implementation,
<> 144:ef7eb2e8f9f7 34 * atomic energy control instruments, airplane or spaceship instruments, the control or
<> 144:ef7eb2e8f9f7 35 * operation of dynamic, brake or safety systems designed for vehicular use, traffic signal
<> 144:ef7eb2e8f9f7 36 * instruments, all types of safety devices, and other applications intended to support or
<> 144:ef7eb2e8f9f7 37 * sustain life.
<> 144:ef7eb2e8f9f7 38 *
<> 144:ef7eb2e8f9f7 39 * All Insecure Usage shall be made at customer's risk, and in the event that third parties
<> 144:ef7eb2e8f9f7 40 * lay claims to Nuvoton as a result of customer's Insecure Usage, customer shall indemnify
<> 144:ef7eb2e8f9f7 41 * the damages and liabilities thus incurred by Nuvoton.
<> 144:ef7eb2e8f9f7 42 *
<> 144:ef7eb2e8f9f7 43 * Please note that all data and specifications are subject to change without notice. All the
<> 144:ef7eb2e8f9f7 44 * trademarks of products and companies mentioned in this document belong to their respective
<> 144:ef7eb2e8f9f7 45 * owners.
<> 144:ef7eb2e8f9f7 46 *
<> 144:ef7eb2e8f9f7 47 * <b>Copyright Notice</b>
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 * Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
<> 144:ef7eb2e8f9f7 50 */
<> 144:ef7eb2e8f9f7 51 /**
<> 144:ef7eb2e8f9f7 52 * \page pg1 NuMicro NUC472/NUC442 BSP Directory Structure
<> 144:ef7eb2e8f9f7 53 * Please refer to Readme.pdf under BSP root directory for the BSP directory structure
<> 144:ef7eb2e8f9f7 54 *
<> 144:ef7eb2e8f9f7 55 * \page pg2 Revision History
<> 144:ef7eb2e8f9f7 56 *
<> 144:ef7eb2e8f9f7 57 * <b>Revision 3.01.001</b>
<> 144:ef7eb2e8f9f7 58 * \li Removed NVIC_EnableIRQ() function call in I2S_Open() and SD_Open().
<> 144:ef7eb2e8f9f7 59 * \li Removed PI definition and add GPI definition.
<> 144:ef7eb2e8f9f7 60 * \li Removed uCOS-II and uCOS-III samples.
<> 144:ef7eb2e8f9f7 61 * \li Renamed CAN_NOTMAL_MODE to CAN_NORMAL_MODE.
<> 144:ef7eb2e8f9f7 62 * \li Renamed UBSD_*() macros to USBD_*().
<> 144:ef7eb2e8f9f7 63 * \li Renamed USBH registers and related bit name.
<> 144:ef7eb2e8f9f7 64 * \li Renamed PD13MFP_SC3_SS0 to PD13MFP_SPI1_SS0.
<> 144:ef7eb2e8f9f7 65 * \li Replaced the USBH_ProcessHubEvents() and usb_hub_events() return type from void to int.
<> 144:ef7eb2e8f9f7 66 * \li Updated original USBH HID library with Nuvoton HID library with less footprint.
<> 144:ef7eb2e8f9f7 67 * \li Updated bit filed definition of register VREFCTL.
<> 144:ef7eb2e8f9f7 68 * \li Enable branch buffer starting from version E MCU.
<> 144:ef7eb2e8f9f7 69 * \li Added RTX support.
<> 144:ef7eb2e8f9f7 70 * \li Added EADC driver.
<> 144:ef7eb2e8f9f7 71 * \li Added Cortex-M4 BitBand and MPU sample codes.
<> 144:ef7eb2e8f9f7 72 * \li Added ADC_PDMA, EADC_ADINT_Trigger, EADC_Compare, EADC_STADC_Trigger, EADC_SWTRG_Trigger, EADC_Timer_Trigger, I2S_NAU8822_PDMA, ISP_Updater,
<> 144:ef7eb2e8f9f7 73 * USBD_Bulk, USBD_HID_Mouse_Vendor, USBD_HID_MouseKeyboard, USBD_HID_Transfer, USBD_VCOM_SerialEmulator, USBD_VENDOR_LBK, USBH_VENDOR_LBK samples.
<> 144:ef7eb2e8f9f7 74 *
<> 144:ef7eb2e8f9f7 75 * <b>Revision 3.01.000</b>
<> 144:ef7eb2e8f9f7 76 * \li Rename registers and bit fields.
<> 144:ef7eb2e8f9f7 77 * \li Added Analog comparator (ACMP) driver
<> 144:ef7eb2e8f9f7 78 * \li Added I2S, ACMP ,and USBD sample codes
<> 144:ef7eb2e8f9f7 79 * \li Minor bug fix.
<> 144:ef7eb2e8f9f7 80 *
<> 144:ef7eb2e8f9f7 81 * <b>Revision 3.00.001</b>
<> 144:ef7eb2e8f9f7 82 * \li Improved PWM driver performance.
<> 144:ef7eb2e8f9f7 83 * \li Renamed EPWM register PWM0/2/4 to PWM_CH0/2/4.
<> 144:ef7eb2e8f9f7 84 * \li Updated IAR project files to support Nu-Link IAR driver v6287 or above.
<> 144:ef7eb2e8f9f7 85 * \li Removed learning board sample code directory NUC472-LB.
<> 144:ef7eb2e8f9f7 86 * \li Added wave player and hard fault sample.
<> 144:ef7eb2e8f9f7 87 * \li Minor bug fix.
<> 144:ef7eb2e8f9f7 88 *
<> 144:ef7eb2e8f9f7 89 * <b>Revision 3.00.000</b>
<> 144:ef7eb2e8f9f7 90 * \li Moved Smartcard library one directory level up to "Library\SmartcardLib\".
<> 144:ef7eb2e8f9f7 91 * \li Added OTG dual role sample code and Learning Board G-sensor sample code.
<> 144:ef7eb2e8f9f7 92 * \li Added FreeRTOS LwIP IAR project file.
<> 144:ef7eb2e8f9f7 93 * \li Renamed RTC_GetDatAndTime() to RTC_GetDateAndTime().
<> 144:ef7eb2e8f9f7 94 * \li Changed Major number from 1 to 3.
<> 144:ef7eb2e8f9f7 95 * \li Minor bug fix.
<> 144:ef7eb2e8f9f7 96 *
<> 144:ef7eb2e8f9f7 97 * <b>Revision 1.00.000</b>
<> 144:ef7eb2e8f9f7 98 * \li Added CAN, SD, SC, SCUART driver and samples.
<> 144:ef7eb2e8f9f7 99 * \li Added smartcard 7816-3 library.
<> 144:ef7eb2e8f9f7 100 * \li Added NUC472 Tiny Board sample.
<> 144:ef7eb2e8f9f7 101 * \li Renamed I2C_GetClockBusFreq() to I2C_GetBusClockFreq().
<> 144:ef7eb2e8f9f7 102 * \li Renamed I2C_SetClockBusFreq() to I2C_SetBusClockFreq().
<> 144:ef7eb2e8f9f7 103 * \li Renamed I2C_SetSlaveMask() to I2C_SetSlaveAddrMask().
<> 144:ef7eb2e8f9f7 104 * \li Minor bug fix.
<> 144:ef7eb2e8f9f7 105 *
<> 144:ef7eb2e8f9f7 106 * <b>Revision 0.10.000</b>
<> 144:ef7eb2e8f9f7 107 * \li Added I2S, PDMA driver.
<> 144:ef7eb2e8f9f7 108 * \li Added Learning Board and Standard Driver samples.
<> 144:ef7eb2e8f9f7 109 * \li Added FreeRTOS lwIP sample.
<> 144:ef7eb2e8f9f7 110 *
<> 144:ef7eb2e8f9f7 111 * <b>Revision 0.09.000</b>
<> 144:ef7eb2e8f9f7 112 * \li Added CAP, EBI, I2C, PWM, SPI, USBD, USBH drivers and samples.
<> 144:ef7eb2e8f9f7 113 * \li Added uCOS-II and uCOS-III samples.
<> 144:ef7eb2e8f9f7 114 * \li Added FreeRTOS source code and sample.
<> 144:ef7eb2e8f9f7 115 *
<> 144:ef7eb2e8f9f7 116 * <b>Revision 0.08.000</b>
<> 144:ef7eb2e8f9f7 117 * \li Preliminary release.
<> 144:ef7eb2e8f9f7 118 */
<> 144:ef7eb2e8f9f7 119 #ifndef __NUC472_442_H__
<> 144:ef7eb2e8f9f7 120 #define __NUC472_442_H__
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 123 extern "C" {
<> 144:ef7eb2e8f9f7 124 #endif
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /******************************************************************************/
<> 144:ef7eb2e8f9f7 127 /* Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 128 /******************************************************************************/
<> 144:ef7eb2e8f9f7 129 /** @addtogroup NUC472_442_CMSIS NUC472/NUC442 Device CMSIS Definitions
<> 144:ef7eb2e8f9f7 130 Configuration of the Cortex-M4 Processor and Core Peripherals
<> 144:ef7eb2e8f9f7 131 @{
<> 144:ef7eb2e8f9f7 132 */
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @details Interrupt Number Definition.
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137 typedef enum IRQn {
<> 144:ef7eb2e8f9f7 138 /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/
<> 144:ef7eb2e8f9f7 139 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
<> 144:ef7eb2e8f9f7 140 MemoryManagement_IRQn = -12, /*!< 4 Memory Management Interrupt */
<> 144:ef7eb2e8f9f7 141 BusFault_IRQn = -11, /*!< 5 Bus Fault Interrupt */
<> 144:ef7eb2e8f9f7 142 UsageFault_IRQn = -10, /*!< 6 Usage Fault Interrupt */
<> 144:ef7eb2e8f9f7 143 SVCall_IRQn = -5, /*!< 11 SV Call Interrupt */
<> 144:ef7eb2e8f9f7 144 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor Interrupt */
<> 144:ef7eb2e8f9f7 145 PendSV_IRQn = -2, /*!< 14 Pend SV Interrupt */
<> 144:ef7eb2e8f9f7 146 SysTick_IRQn = -1, /*!< 15 System Tick Interrupt */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /****** NUC472/NUC442 Specific Interrupt Numbers ********************************************************/
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 BOD_IRQn = 0, /*!< Brown Out detection Interrupt */
<> 144:ef7eb2e8f9f7 151 IRC_IRQn = 1, /*!< Internal RC Interrupt */
<> 144:ef7eb2e8f9f7 152 PWRWU_IRQn = 2, /*!< Power Down Wake Up Interrupt */
<> 144:ef7eb2e8f9f7 153 SRAMF_IRQn = 3, /*!< SRAM Parity Check Failed Interrupt */
<> 144:ef7eb2e8f9f7 154 CLKF_IRQn = 4, /*!< Clock Detection Failed Interrupt */
<> 144:ef7eb2e8f9f7 155 RTC_IRQn = 6, /*!< Real Time Clock Interrupt */
<> 144:ef7eb2e8f9f7 156 TAMPER_IRQn = 7, /*!< Tamper detection Interrupt */
<> 144:ef7eb2e8f9f7 157 EINT0_IRQn = 8, /*!< External Input 0 Interrupt */
<> 144:ef7eb2e8f9f7 158 EINT1_IRQn = 9, /*!< External Input 1 Interrupt */
<> 144:ef7eb2e8f9f7 159 EINT2_IRQn = 10, /*!< External Input 2 Interrupt */
<> 144:ef7eb2e8f9f7 160 EINT3_IRQn = 11, /*!< External Input 3 Interrupt */
<> 144:ef7eb2e8f9f7 161 EINT4_IRQn = 12, /*!< External Input 4 Interrupt */
<> 144:ef7eb2e8f9f7 162 EINT5_IRQn = 13, /*!< External Input 5 Interrupt */
<> 144:ef7eb2e8f9f7 163 EINT6_IRQn = 14, /*!< External Input 6 Interrupt */
<> 144:ef7eb2e8f9f7 164 EINT7_IRQn = 15, /*!< External Input 7 Interrupt */
<> 144:ef7eb2e8f9f7 165 GPA_IRQn = 16, /*!< GPIO Port A Interrupt */
<> 144:ef7eb2e8f9f7 166 GPB_IRQn = 17, /*!< GPIO Port B Interrupt */
<> 144:ef7eb2e8f9f7 167 GPC_IRQn = 18, /*!< GPIO Port C Interrupt */
<> 144:ef7eb2e8f9f7 168 GPD_IRQn = 19, /*!< GPIO Port D Interrupt */
<> 144:ef7eb2e8f9f7 169 GPE_IRQn = 20, /*!< GPIO Port E Interrupt */
<> 144:ef7eb2e8f9f7 170 GPF_IRQn = 21, /*!< GPIO Port F Interrupt */
<> 144:ef7eb2e8f9f7 171 GPG_IRQn = 22, /*!< GPIO Port G Interrupt */
<> 144:ef7eb2e8f9f7 172 GPH_IRQn = 23, /*!< GPIO Port H Interrupt */
<> 144:ef7eb2e8f9f7 173 GPI_IRQn = 24, /*!< GPIO Port I Interrupt */
<> 144:ef7eb2e8f9f7 174 TMR0_IRQn = 32, /*!< Timer 0 Interrupt */
<> 144:ef7eb2e8f9f7 175 TMR1_IRQn = 33, /*!< Timer 1 Interrupt */
<> 144:ef7eb2e8f9f7 176 TMR2_IRQn = 34, /*!< Timer 2 Interrupt */
<> 144:ef7eb2e8f9f7 177 TMR3_IRQn = 35, /*!< Timer 3 Interrupt */
<> 144:ef7eb2e8f9f7 178 PDMA_IRQn = 40, /*!< Peripheral DMA Interrupt */
<> 144:ef7eb2e8f9f7 179 ADC_IRQn = 42, /*!< ADC Interrupt */
<> 144:ef7eb2e8f9f7 180 WDT_IRQn = 46, /*!< Watch Dog Timer Interrupt */
<> 144:ef7eb2e8f9f7 181 WWDT_IRQn = 47, /*!< Window Watch Dog Timer Interrupt */
<> 144:ef7eb2e8f9f7 182 EADC0_IRQn = 48, /*!< Enhanced ADC 0 Interrupt */
<> 144:ef7eb2e8f9f7 183 EADC1_IRQn = 49, /*!< Enhanced ADC 1 Interrupt */
<> 144:ef7eb2e8f9f7 184 EADC2_IRQn = 50, /*!< Enhanced ADC 2 Interrupt */
<> 144:ef7eb2e8f9f7 185 EADC3_IRQn = 51, /*!< Enhanced ADC 3 Interrupt */
<> 144:ef7eb2e8f9f7 186 ACMP_IRQn = 56, /*!< Analog Comparator Interrupt */
<> 144:ef7eb2e8f9f7 187 OPA0_IRQn = 60, /*!< OPA 0 Interrupt */
<> 144:ef7eb2e8f9f7 188 OPA1_IRQn = 61, /*!< OPA 1 Interrupt */
<> 144:ef7eb2e8f9f7 189 ICAP0_IRQn = 62, /*!< Input Capture 0 Interrupt */
<> 144:ef7eb2e8f9f7 190 ICAP1_IRQn = 63, /*!< Input Capture 1 Interrupt */
<> 144:ef7eb2e8f9f7 191 PWM0CH0_IRQn = 64, /*!< PWM 0 Channel 0 Interrupt */
<> 144:ef7eb2e8f9f7 192 PWM0CH1_IRQn = 65, /*!< PWM 0 Channel 1 Interrupt */
<> 144:ef7eb2e8f9f7 193 PWM0CH2_IRQn = 66, /*!< PWM 0 Channel 2 Interrupt */
<> 144:ef7eb2e8f9f7 194 PWM0CH3_IRQn = 67, /*!< PWM 0 Channel 3 Interrupt */
<> 144:ef7eb2e8f9f7 195 PWM0CH4_IRQn = 68, /*!< PWM 0 Channel 4 Interrupt */
<> 144:ef7eb2e8f9f7 196 PWM0CH5_IRQn = 69, /*!< PWM 0 Channel 5 Interrupt */
<> 144:ef7eb2e8f9f7 197 PWM0_BRK_IRQn = 70, /*!< PWM 0 Break Interrupt */
<> 144:ef7eb2e8f9f7 198 QEI0_IRQn = 71, /*!< QEI 0 Interrupt */
<> 144:ef7eb2e8f9f7 199 PWM1CH0_IRQn = 72, /*!< PWM 1 Channel 0 Interrupt */
<> 144:ef7eb2e8f9f7 200 PWM1CH1_IRQn = 73, /*!< PWM 1 Channel 1 Interrupt */
<> 144:ef7eb2e8f9f7 201 PWM1CH2_IRQn = 74, /*!< PWM 1 Channel 2 Interrupt */
<> 144:ef7eb2e8f9f7 202 PWM1CH3_IRQn = 75, /*!< PWM 1 Channel 3 Interrupt */
<> 144:ef7eb2e8f9f7 203 PWM1CH4_IRQn = 76, /*!< PWM 1 Channel 4 Interrupt */
<> 144:ef7eb2e8f9f7 204 PWM1CH5_IRQn = 77, /*!< PWM 1 Channel 5 Interrupt */
<> 144:ef7eb2e8f9f7 205 PWM1_BRK_IRQn = 78, /*!< PWM 1 Break Interrupt */
<> 144:ef7eb2e8f9f7 206 QEI1_IRQn = 79, /*!< QEI 1 Interrupt */
<> 144:ef7eb2e8f9f7 207 EPWM0_IRQn = 80, /*!< Enhanced PWM 0 Interrupt */
<> 144:ef7eb2e8f9f7 208 EPWM0BRK_IRQn = 81, /*!< Enhanced PWM 0 Break Interrupt */
<> 144:ef7eb2e8f9f7 209 EPWM1_IRQn = 82, /*!< Enhanced PWM 1 Interrupt */
<> 144:ef7eb2e8f9f7 210 EPWM1BRK_IRQn = 83, /*!< Enhanced PWM 1 Break Interrupt */
<> 144:ef7eb2e8f9f7 211 USBD_IRQn = 88, /*!< USB FS Device Interrupt */
<> 144:ef7eb2e8f9f7 212 USBH_IRQn = 89, /*!< USB FS Host Interrupt */
<> 144:ef7eb2e8f9f7 213 USB_OTG_IRQn = 90, /*!< USB OTG Interrupt */
<> 144:ef7eb2e8f9f7 214 EMAC_TX_IRQn = 92, /*!< Ethernet MAC TX Interrupt */
<> 144:ef7eb2e8f9f7 215 EMAC_RX_IRQn = 93, /*!< Ethernet MAC RX Interrupt */
<> 144:ef7eb2e8f9f7 216 SPI0_IRQn = 96, /*!< SPI 0 Interrupt */
<> 144:ef7eb2e8f9f7 217 SPI1_IRQn = 97, /*!< SPI 1 Interrupt */
<> 144:ef7eb2e8f9f7 218 SPI2_IRQn = 98, /*!< SPI 2 Interrupt */
<> 144:ef7eb2e8f9f7 219 SPI3_IRQn = 99, /*!< SPI 3 Interrupt */
<> 144:ef7eb2e8f9f7 220 UART0_IRQn = 104, /*!< UART 0 Interrupt */
<> 144:ef7eb2e8f9f7 221 UART1_IRQn = 105, /*!< UART 1 Interrupt */
<> 144:ef7eb2e8f9f7 222 UART2_IRQn = 106, /*!< UART 2 Interrupt */
<> 144:ef7eb2e8f9f7 223 UART3_IRQn = 107, /*!< UART 3 Interrupt */
<> 144:ef7eb2e8f9f7 224 UART4_IRQn = 108, /*!< UART 4 Interrupt */
<> 144:ef7eb2e8f9f7 225 UART5_IRQn = 109, /*!< UART 5 Interrupt */
<> 144:ef7eb2e8f9f7 226 I2C0_IRQn = 112, /*!< I2C 0 Interrupt */
<> 144:ef7eb2e8f9f7 227 I2C1_IRQn = 113, /*!< I2C 1 Interrupt */
<> 144:ef7eb2e8f9f7 228 I2C2_IRQn = 114, /*!< I2C 2 Interrupt */
<> 144:ef7eb2e8f9f7 229 I2C3_IRQn = 115, /*!< I2C 3 Interrupt */
<> 144:ef7eb2e8f9f7 230 I2C4_IRQn = 116, /*!< I2C 4 Interrupt */
<> 144:ef7eb2e8f9f7 231 SC0_IRQn = 120, /*!< Smart Card 0 Interrupt */
<> 144:ef7eb2e8f9f7 232 SC1_IRQn = 121, /*!< Smart Card 1 Interrupt */
<> 144:ef7eb2e8f9f7 233 SC2_IRQn = 122, /*!< Smart Card 2 Interrupt */
<> 144:ef7eb2e8f9f7 234 SC3_IRQn = 123, /*!< Smart Card 3 Interrupt */
<> 144:ef7eb2e8f9f7 235 SC4_IRQn = 124, /*!< Smart Card 4 Interrupt */
<> 144:ef7eb2e8f9f7 236 SC5_IRQn = 125, /*!< Smart Card 5 Interrupt */
<> 144:ef7eb2e8f9f7 237 CAN0_IRQn = 128, /*!< CAN 0 Interrupt */
<> 144:ef7eb2e8f9f7 238 CAN1_IRQn = 129, /*!< CAN 1 Interrupt */
<> 144:ef7eb2e8f9f7 239 I2S0_IRQn = 132, /*!< I2S 0 Interrupt */
<> 144:ef7eb2e8f9f7 240 I2S1_IRQn = 133, /*!< I2S 1 Interrupt */
<> 144:ef7eb2e8f9f7 241 SD_IRQn = 136, /*!< SD Host Interrupt */
<> 144:ef7eb2e8f9f7 242 PS2D_IRQn = 138, /*!< PS/2 device Interrupt */
<> 144:ef7eb2e8f9f7 243 CAP_IRQn = 139, /*!< VCAP Interrupt */
<> 144:ef7eb2e8f9f7 244 CRPT_IRQn = 140, /*!< Cryptographic Accelerator Interrupt */
<> 144:ef7eb2e8f9f7 245 CRC_IRQn = 141, /*!< CRC Interrupt */
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247 IRQn_Type;
<> 144:ef7eb2e8f9f7 248
<> 144:ef7eb2e8f9f7 249
<> 144:ef7eb2e8f9f7 250 /*
<> 144:ef7eb2e8f9f7 251 * ==========================================================================
<> 144:ef7eb2e8f9f7 252 * ----------- Processor and Core Peripheral Section ------------------------
<> 144:ef7eb2e8f9f7 253 * ==========================================================================
<> 144:ef7eb2e8f9f7 254 */
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /* Configuration of the Cortex-M# Processor and Core Peripherals */
<> 144:ef7eb2e8f9f7 257 #define __CM4_REV 0x0201 /*!< Core Revision r2p1 */
<> 144:ef7eb2e8f9f7 258 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 259 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 260 #define __MPU_PRESENT 1 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 261 #define __FPU_PRESENT 1 /*!< FPU present or not */
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /*@}*/ /* end of group NUC472_442_CMSIS */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265
<> 144:ef7eb2e8f9f7 266 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
<> 144:ef7eb2e8f9f7 267 #include "system_NUC472_442.h" /* NUC472/NUC442 System include file */
<> 144:ef7eb2e8f9f7 268 #include <stdint.h>
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /******************************************************************************/
<> 144:ef7eb2e8f9f7 271 /* Device Specific Peripheral registers structures */
<> 144:ef7eb2e8f9f7 272 /******************************************************************************/
<> 144:ef7eb2e8f9f7 273 /** @addtogroup NUC472_442_Peripherals NUC472/NUC442 Control Register
<> 144:ef7eb2e8f9f7 274 NUC472/NUC442 Device Specific Peripheral registers structures
<> 144:ef7eb2e8f9f7 275 @{
<> 144:ef7eb2e8f9f7 276 */
<> 144:ef7eb2e8f9f7 277
<> 144:ef7eb2e8f9f7 278 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 279 #pragma anon_unions
<> 144:ef7eb2e8f9f7 280 #endif
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /*---------------------- Analog Comparator Controller -------------------------*/
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 @addtogroup ACMP Analog Comparator Controller(ACMP)
<> 144:ef7eb2e8f9f7 286 Memory Mapped Structure for ACMP Controller
<> 144:ef7eb2e8f9f7 287 @{ */
<> 144:ef7eb2e8f9f7 288
<> 144:ef7eb2e8f9f7 289 typedef struct {
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /**
<> 144:ef7eb2e8f9f7 293 * CTL0, CTL1, CTL2
<> 144:ef7eb2e8f9f7 294 * ===================================================================================================
<> 144:ef7eb2e8f9f7 295 * Offset: 0x00~0x08 Analog Comparator 0/1/2 Control Register
<> 144:ef7eb2e8f9f7 296 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 297 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 298 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 299 * |[0] |ACMPEN |Comparator 0 Enable Control
<> 144:ef7eb2e8f9f7 300 * | | |0 = Comparator 0 Disabled.
<> 144:ef7eb2e8f9f7 301 * | | |1 = Comparator 0 Enabled.
<> 144:ef7eb2e8f9f7 302 * | | |Note: The comparator output needs to wait 2 us stable time after ACMPEN is set.
<> 144:ef7eb2e8f9f7 303 * |[1] |ACMPIE |Comparator 0 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 304 * | | |0 = Comparator 0 interrupt Disabled.
<> 144:ef7eb2e8f9f7 305 * | | |1 = Comparator 0 interrupt Enabled.
<> 144:ef7eb2e8f9f7 306 * |[2] |HYSEN |Comparator 0 Hysteresis Enable Control
<> 144:ef7eb2e8f9f7 307 * | | |0 = Comparator 0 hysteresis Disabled (Default).
<> 144:ef7eb2e8f9f7 308 * | | |1 = Comparator 0 hysteresis Enabled (typical range is 20 mV).
<> 144:ef7eb2e8f9f7 309 * |[3] |ACMPOINV |Comparator 0 Output Inverse
<> 144:ef7eb2e8f9f7 310 * | | |0 = Comparator 0 output inverse Disabled.
<> 144:ef7eb2e8f9f7 311 * | | |1 = Comparator 0 output inverse Enabled.
<> 144:ef7eb2e8f9f7 312 * |[4] |NEGSEL |Comparator 0 Negative Input Selection
<> 144:ef7eb2e8f9f7 313 * | | |0 = The source of comparator 0 negative input is from ACMP0_N pin.
<> 144:ef7eb2e8f9f7 314 * | | |1 = The internal comparator reference voltage (Band-gap voltage or CRV) is selected as the source of comparator 0 negative input.
<> 144:ef7eb2e8f9f7 315 * |[5:7] |POSSEL |Comparator 0 Positive Input Selection
<> 144:ef7eb2e8f9f7 316 * | | |000= Input from ACMP0_P0.
<> 144:ef7eb2e8f9f7 317 * | | |001= Input from ACMP0_P1.
<> 144:ef7eb2e8f9f7 318 * | | |010= Input from ACMP0_P2.
<> 144:ef7eb2e8f9f7 319 * | | |011= Input from ACMP0_P3.
<> 144:ef7eb2e8f9f7 320 * | | |100= Input from OPA0.
<> 144:ef7eb2e8f9f7 321 * | | |The other options are reserved.
<> 144:ef7eb2e8f9f7 322 */
<> 144:ef7eb2e8f9f7 323 __IO uint32_t CTL[3];
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /**
<> 144:ef7eb2e8f9f7 326 * STATUS
<> 144:ef7eb2e8f9f7 327 * ===================================================================================================
<> 144:ef7eb2e8f9f7 328 * Offset: 0x0C Analog Comparator Status Register
<> 144:ef7eb2e8f9f7 329 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 330 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 331 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 332 * |[0] |ACMPIF0 |Comparator 0 Flag
<> 144:ef7eb2e8f9f7 333 * | | |This bit is set by hardware whenever the comparator 0 output changes state.
<> 144:ef7eb2e8f9f7 334 * | | |This will cause an interrupt if ACMP_CTL0[1] is set to 1.
<> 144:ef7eb2e8f9f7 335 * | | |Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 336 * |[1] |ACMPIF1 |Comparator 1 Flag
<> 144:ef7eb2e8f9f7 337 * | | |This bit is set by hardware whenever the comparator 1 output changes state.
<> 144:ef7eb2e8f9f7 338 * | | |This will cause an interrupt if ACMP_CTL1[1] is set to 1.
<> 144:ef7eb2e8f9f7 339 * | | |Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 340 * |[2] |ACMPIF2 |Comparator 2 Flag
<> 144:ef7eb2e8f9f7 341 * | | |This bit is set by hardware whenever the comparator 2 output changes state.
<> 144:ef7eb2e8f9f7 342 * | | |This will cause an interrupt if ACMP_CTL2[1] is set to 1.
<> 144:ef7eb2e8f9f7 343 * | | |Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 344 * |[3] |ACMPO0 |Comparator 0 Output
<> 144:ef7eb2e8f9f7 345 * | | |Synchronized to the APB clock to allow reading by software.
<> 144:ef7eb2e8f9f7 346 * | | |Cleared when the comparator 0 is disabled (ACMP_CTL0[0] = 0).
<> 144:ef7eb2e8f9f7 347 * |[4] |ACMPO1 |Comparator 1 Output
<> 144:ef7eb2e8f9f7 348 * | | |Synchronized to the APB clock to allow reading by software.
<> 144:ef7eb2e8f9f7 349 * | | |Cleared when the comparator 1 is disabled (ACMP_CTL1[0] = 0).
<> 144:ef7eb2e8f9f7 350 * |[5] |ACMPO2 |Comparator 2 Output
<> 144:ef7eb2e8f9f7 351 * | | |Synchronized to the APB clock to allow reading by software.
<> 144:ef7eb2e8f9f7 352 * | | |Cleared when the comparator 2 is disabled (ACMP_CTL2[0] = 0).
<> 144:ef7eb2e8f9f7 353 */
<> 144:ef7eb2e8f9f7 354 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /**
<> 144:ef7eb2e8f9f7 357 * VREF
<> 144:ef7eb2e8f9f7 358 * ===================================================================================================
<> 144:ef7eb2e8f9f7 359 * Offset: 0x10 Analog Comparator Reference Voltage Control Register
<> 144:ef7eb2e8f9f7 360 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 361 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 362 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 363 * |[0:3] |CRVCTL |Comparator Reference Voltage Setting
<> 144:ef7eb2e8f9f7 364 * | | |CRV = CRV source voltage * (1/6+VREF[3:0]/24).
<> 144:ef7eb2e8f9f7 365 * |[6] |CRVSSEL |CRV Source Voltage Selection
<> 144:ef7eb2e8f9f7 366 * | | |0 = VDDA is selected as CRV source voltage.
<> 144:ef7eb2e8f9f7 367 * | | |1 = Internal reference voltage is selected as CRV source voltage.
<> 144:ef7eb2e8f9f7 368 * |[7] |IREFSEL |Internal Reference Selection
<> 144:ef7eb2e8f9f7 369 * | | |0 = Band-gap voltage is selected as internal reference.
<> 144:ef7eb2e8f9f7 370 * | | |1 = CRV is selected as internal reference.
<> 144:ef7eb2e8f9f7 371 */
<> 144:ef7eb2e8f9f7 372 __IO uint32_t VREF;
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 } ACMP_T;
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /**
<> 144:ef7eb2e8f9f7 377 @addtogroup ACMP_CONST ACMP Bit Field Definition
<> 144:ef7eb2e8f9f7 378 Constant Definitions for ACMP Controller
<> 144:ef7eb2e8f9f7 379 @{ */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 #define ACMP_CTL_ACMPEN_Pos (0) /*!< ACMP CTL: ACMPEN Position */
<> 144:ef7eb2e8f9f7 382 #define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) /*!< ACMP CTL: ACMPEN Mask */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 #define ACMP_CTL_ACMPIE_Pos (1) /*!< ACMP CTL: ACMPIE Position */
<> 144:ef7eb2e8f9f7 385 #define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) /*!< ACMP CTL: ACMPIE Mask */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 #define ACMP_CTL_HYSEN_Pos (2) /*!< ACMP CTL: HYSEN Position */
<> 144:ef7eb2e8f9f7 388 #define ACMP_CTL_HYSEN_Msk (0x1ul << ACMP_CTL_HYSEN_Pos) /*!< ACMP CTL: HYSEN Mask */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 #define ACMP_CTL_ACMPOINV_Pos (3) /*!< ACMP CTL: ACMPOINV Position */
<> 144:ef7eb2e8f9f7 391 #define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) /*!< ACMP CTL: ACMPOINV Mask */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 #define ACMP_CTL_NEGSEL_Pos (4) /*!< ACMP CTL: NEGSEL Position */
<> 144:ef7eb2e8f9f7 394 #define ACMP_CTL_NEGSEL_Msk (0x1ul << ACMP_CTL_NEGSEL_Pos) /*!< ACMP CTL: NEGSEL Mask */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 #define ACMP_CTL_POSSEL_Pos (5) /*!< ACMP CTL: POSSEL Position */
<> 144:ef7eb2e8f9f7 397 #define ACMP_CTL_POSSEL_Msk (0x7ul << ACMP_CTL_POSSEL_Pos) /*!< ACMP CTL: POSSEL Mask */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 #define ACMP_STATUS_ACMPIF0_Pos (0) /*!< ACMP STATUS: ACMPIF0 Position */
<> 144:ef7eb2e8f9f7 400 #define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) /*!< ACMP STATUS: ACMPIF0 Mask */
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 #define ACMP_STATUS_ACMPIF1_Pos (1) /*!< ACMP STATUS: ACMPIF1 Position */
<> 144:ef7eb2e8f9f7 403 #define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) /*!< ACMP STATUS: ACMPIF1 Mask */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 #define ACMP_STATUS_ACMPIF2_Pos (2) /*!< ACMP STATUS: ACMPIF2 Position */
<> 144:ef7eb2e8f9f7 406 #define ACMP_STATUS_ACMPIF2_Msk (0x1ul << ACMP_STATUS_ACMPIF2_Pos) /*!< ACMP STATUS: ACMPIF2 Mask */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 #define ACMP_STATUS_ACMPO0_Pos (3) /*!< ACMP STATUS: ACMPO0 Position */
<> 144:ef7eb2e8f9f7 409 #define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) /*!< ACMP STATUS: ACMPO0 Mask */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 #define ACMP_STATUS_ACMPO1_Pos (4) /*!< ACMP STATUS: ACMPO1 Position */
<> 144:ef7eb2e8f9f7 412 #define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) /*!< ACMP STATUS: ACMPO1 Mask */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 #define ACMP_STATUS_ACMPO2_Pos (5) /*!< ACMP STATUS: ACMPO2 Position */
<> 144:ef7eb2e8f9f7 415 #define ACMP_STATUS_ACMPO2_Msk (0x1ul << ACMP_STATUS_ACMPO2_Pos) /*!< ACMP STATUS: ACMPO2 Mask */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 #define ACMP_VREF_CRVCTL_Pos (0) /*!< ACMP VREF: CRVCTL Position */
<> 144:ef7eb2e8f9f7 418 #define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) /*!< ACMP VREF: CRVCTL Mask */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 #define ACMP_VREF_CRVSSEL_Pos (6) /*!< ACMP VREF: CRVSSEL Position */
<> 144:ef7eb2e8f9f7 421 #define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) /*!< ACMP VREF: CRVSSEL Mask */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 #define ACMP_VREF_IREFSEL_Pos (7) /*!< ACMP VREF: IREFSEL Position */
<> 144:ef7eb2e8f9f7 424 #define ACMP_VREF_IREFSEL_Msk (0x1ul << ACMP_VREF_IREFSEL_Pos) /*!< ACMP VREF: IREFSEL Mask */
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 /**@}*/ /* ACMP_CONST */
<> 144:ef7eb2e8f9f7 427 /**@}*/ /* end of ACMP register group */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 /*---------------------- Analog to Digital Converter -------------------------*/
<> 144:ef7eb2e8f9f7 431 /**
<> 144:ef7eb2e8f9f7 432 @addtogroup ADC Analog to Digital Converter(ADC)
<> 144:ef7eb2e8f9f7 433 Memory Mapped Structure for ADC Controller
<> 144:ef7eb2e8f9f7 434 @{ */
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 typedef struct {
<> 144:ef7eb2e8f9f7 437
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /**
<> 144:ef7eb2e8f9f7 440 * DAT
<> 144:ef7eb2e8f9f7 441 * ===================================================================================================
<> 144:ef7eb2e8f9f7 442 * Offset: 0x00~0x34 ADC Data Register 0~13
<> 144:ef7eb2e8f9f7 443 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 444 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 445 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 446 * |[0:15] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 447 * | | |This field contains conversion result of ADC.
<> 144:ef7eb2e8f9f7 448 * | | |When DMOF (ADC_CTL[31]) bit is set to 0, 12-bit ADC conversion result with unsigned format will be filled in RESULT[11:0] and zero will be filled in RESULT[15:12].
<> 144:ef7eb2e8f9f7 449 * | | |When DMOF (ADC_CTL[31]) bit set to 1, 12-bit ADC conversion result with 2'complement format will be filled in RESULT[11:0] and signed bits to will be filled in RESULT[15:12].
<> 144:ef7eb2e8f9f7 450 * |[16] |OV |Overrun Flag (Read Only)
<> 144:ef7eb2e8f9f7 451 * | | |0 = Data in RESULT (ADC_DATx[15:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 452 * | | |1 = Data in RESULT (ADC_DATx[15:0]) is overwrite.
<> 144:ef7eb2e8f9f7 453 * | | |If converted data in RESULT[15:0] has not been read before new conversion result is loaded to this register, OV is set to 1 and previous conversion result is gone.
<> 144:ef7eb2e8f9f7 454 * | | |It is cleared by hardware after ADC_DAT register is read.
<> 144:ef7eb2e8f9f7 455 * |[17] |VALID |Valid Flag (Read Only)
<> 144:ef7eb2e8f9f7 456 * | | |0 = Data in RESULT (ADC_DATx[15:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 457 * | | |1 = Data in RESULT (ADC_DATx[15:0]) bits is valid.
<> 144:ef7eb2e8f9f7 458 * | | |This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADC_DAT register is read.
<> 144:ef7eb2e8f9f7 459 */
<> 144:ef7eb2e8f9f7 460 __I uint32_t DAT[14];
<> 144:ef7eb2e8f9f7 461
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 uint32_t RESERVE0[2];
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 /**
<> 144:ef7eb2e8f9f7 467 * CTL
<> 144:ef7eb2e8f9f7 468 * ===================================================================================================
<> 144:ef7eb2e8f9f7 469 * Offset: 0x40 ADC Control Register
<> 144:ef7eb2e8f9f7 470 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 471 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 472 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 473 * |[0] |ADCEN |ADC Enable Control
<> 144:ef7eb2e8f9f7 474 * | | |0 = ADC analog circuit Disabled.
<> 144:ef7eb2e8f9f7 475 * | | |1 = ADC analog circuit Enabled.
<> 144:ef7eb2e8f9f7 476 * | | |Before disabling ADC clock, this bit should be cleared to 0 by software.
<> 144:ef7eb2e8f9f7 477 * |[1] |ADCIEN |ADC Interrupt Enable Control
<> 144:ef7eb2e8f9f7 478 * | | |0 = ADC interrupt function Disabled.
<> 144:ef7eb2e8f9f7 479 * | | |1 = ADC interrupt function Enabled.
<> 144:ef7eb2e8f9f7 480 * | | |A/D conversion end interrupt request is generated if ADCIEN (ADC_CTL[1]) bit is set to 1.
<> 144:ef7eb2e8f9f7 481 * |[2:3] |OPMODE |ADC Operation Mode
<> 144:ef7eb2e8f9f7 482 * | | |00 = Single conversion.
<> 144:ef7eb2e8f9f7 483 * | | |01 = Reserved.
<> 144:ef7eb2e8f9f7 484 * | | |10 = Single-cycle scan.
<> 144:ef7eb2e8f9f7 485 * | | |11 = Continuous scan.
<> 144:ef7eb2e8f9f7 486 * | | |When changing the operation mode, software should disable SWTRG (ADC_CTL[11]) bit firstly.
<> 144:ef7eb2e8f9f7 487 * |[4:5] |HWTRGSEL |External Hardware Trigger Source
<> 144:ef7eb2e8f9f7 488 * | | |00 = A/D conversion is started by external pin (STADC).
<> 144:ef7eb2e8f9f7 489 * | | |01 = Reserved.
<> 144:ef7eb2e8f9f7 490 * | | |10 = Reserved.
<> 144:ef7eb2e8f9f7 491 * | | |11 = PWM0 or PWM1 trigger condition is matched.
<> 144:ef7eb2e8f9f7 492 * | | |Software should disable HWTRGCOND (ADC_CTL[8]) and SWTRG (ADC_CTL[11]) before changing HWTRGSEL (ADC_CTL[5:4]).
<> 144:ef7eb2e8f9f7 493 * | | |In hardware trigger mode, the SWTRG (ADC_CTL[11]) bit is set by hardware trigger source.
<> 144:ef7eb2e8f9f7 494 * |[6:7] |HWTRGCOND |External Pin Trigger Conditions
<> 144:ef7eb2e8f9f7 495 * | | |These two bits decide external pin (STADC) trigger event.
<> 144:ef7eb2e8f9f7 496 * | | |The signal must be kept at stable state at least 8 system clocks for level trigger and 4 system clocks at high and low state for edge trigger.
<> 144:ef7eb2e8f9f7 497 * | | |00 = Low level.
<> 144:ef7eb2e8f9f7 498 * | | |01 = High level.
<> 144:ef7eb2e8f9f7 499 * | | |10 = Falling edge.
<> 144:ef7eb2e8f9f7 500 * | | |11 = Rising edge.
<> 144:ef7eb2e8f9f7 501 * |[8] |HWTRGEN |External Hardware Trigger Enable Control
<> 144:ef7eb2e8f9f7 502 * | | |Enable or disable hardware triggering of A/D conversion.
<> 144:ef7eb2e8f9f7 503 * | | |The hardware trigger source include external pin (STADC) or PWM trigger which is controlled by HWTRGSEL (ADC_CTL[5:4]) register.
<> 144:ef7eb2e8f9f7 504 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 505 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 506 * | | |ADC hardware trigger function is only supported in single-cycle scan mode.
<> 144:ef7eb2e8f9f7 507 * |[9] |PDMAEN |PDMA Transfer Enable Control
<> 144:ef7eb2e8f9f7 508 * | | |0 = PDMA data transfer Disabled.
<> 144:ef7eb2e8f9f7 509 * | | |1 = PDMA data transfer in ADC_DATx Enabled.
<> 144:ef7eb2e8f9f7 510 * | | |When A/D conversion is completed, the converted data is loaded into ADC_DATx, software can enable this bit to generate a PDMA data transfer request.
<> 144:ef7eb2e8f9f7 511 * | | |When PDMAEN (ADC_CTL[9]) is set to 1, software must set ADCIEN (ADC_CTL[1]) bit to 0 to disable interrupt.
<> 144:ef7eb2e8f9f7 512 * |[10] |DIFFEN |Differential Input Mode Enable Control
<> 144:ef7eb2e8f9f7 513 * | | |0 = Single-end analog input mode.
<> 144:ef7eb2e8f9f7 514 * | | |1 = Differential analog input mode.
<> 144:ef7eb2e8f9f7 515 * | | |The A/D analog input ADC0_CH0/ADC0_CH1 consists of a differential pair.
<> 144:ef7eb2e8f9f7 516 * | | |So as ADC0_CH2/ADC0_CH3, ADC0_CH4/ADC0_CH5, ADC0_CH6/ADC0_CH7, ADC0_CH8/ADC0_CH9 and ADC0_CH10/ADC0_CH11.
<> 144:ef7eb2e8f9f7 517 * | | |The even channel defines as plus analog input voltage (Vplus) and the odd channel defines as minus analog input voltage (Vminus).
<> 144:ef7eb2e8f9f7 518 * | | |Differential input voltage (Vdiff) = Vplus - Vminus, where Vplus
<> 144:ef7eb2e8f9f7 519 * | | |is the analog input; Vminus is the inverted analog input.
<> 144:ef7eb2e8f9f7 520 * | | |In differential input mode, only the even number of the two corresponding channels needs to be enabled in ADCHER (ADC_CHEN[11:0]).
<> 144:ef7eb2e8f9f7 521 * | | |The conversion result will be placed to the corresponding data register of the enabled channel.
<> 144:ef7eb2e8f9f7 522 * |[11] |SWTRG |A/D Conversion Start
<> 144:ef7eb2e8f9f7 523 * | | |0 = Conversion stopped and A/D converter enter idle state.
<> 144:ef7eb2e8f9f7 524 * | | |1 = Conversion start.
<> 144:ef7eb2e8f9f7 525 * | | |The SWTRG (ADC_CTL[11]) bit can be set to 1 from two sources: software and hardware trigger.
<> 144:ef7eb2e8f9f7 526 * | | |The SWTRG (ADC_CTL[11]) bit will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode.
<> 144:ef7eb2e8f9f7 527 * | | |In continuous scan mode, A/D conversion is continuously performed until software write 0 to this bit or chip reset.
<> 144:ef7eb2e8f9f7 528 * |[16:23] |PWMTRGDLY |PWM Trigger Delay Time
<> 144:ef7eb2e8f9f7 529 * | | |Setting this field will delay ADC start conversion time after PWM trigger comes.
<> 144:ef7eb2e8f9f7 530 * | | |PWM trigger delay time is 4 * system clock * PWMTRGDLY (ADC_CTL[23:16])
<> 144:ef7eb2e8f9f7 531 * |[31] |DMOF |ADC Differential Input Mode Output Format
<> 144:ef7eb2e8f9f7 532 * | | |0 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with unsigned format.
<> 144:ef7eb2e8f9f7 533 * | | |1 = A/D conversion result will be filled in RESULT (ADC_DATx[15:0]) registers with 2'complement format.
<> 144:ef7eb2e8f9f7 534 */
<> 144:ef7eb2e8f9f7 535 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /**
<> 144:ef7eb2e8f9f7 538 * CHEN
<> 144:ef7eb2e8f9f7 539 * ===================================================================================================
<> 144:ef7eb2e8f9f7 540 * Offset: 0x44 ADC Channel Enable Control Register
<> 144:ef7eb2e8f9f7 541 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 542 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 543 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 544 * |[0:11] |CHEN |Analog Input Channel Enable Control
<> 144:ef7eb2e8f9f7 545 * | | |Set CHEN (ADC_CHEN[11:0]) to enable the corresponding analog input channel (ADC0_CH1 ~ ADC0_CH11).
<> 144:ef7eb2e8f9f7 546 * | | |If DIFFEN bit is set to 1, only the even number channels need to be enabled.
<> 144:ef7eb2e8f9f7 547 * | | |0 = ADC input channel Disabled.
<> 144:ef7eb2e8f9f7 548 * | | |1 = ADC input channel Enabled.
<> 144:ef7eb2e8f9f7 549 * |[16] |ADTSEN |Internal Temperature Sensor Selection
<> 144:ef7eb2e8f9f7 550 * | | |0 = Internal temperature sensor is not selected to be the analog input source of ADC.
<> 144:ef7eb2e8f9f7 551 * | | |1 = Internal temperature sensor is selected to be the analog input source of ADC.
<> 144:ef7eb2e8f9f7 552 * | | |ADC can only work at Single mode when software selects the temperature sensor voltage as the analog input source of ADC
<> 144:ef7eb2e8f9f7 553 * |[17] |ADBGEN |Internal Band-Gap Selection
<> 144:ef7eb2e8f9f7 554 * | | |0 = Internal band-gap is not selected to be the analog input source of ADC.
<> 144:ef7eb2e8f9f7 555 * | | |1 = Internal band-gap is selected to be the analog input source of ADC.
<> 144:ef7eb2e8f9f7 556 * | | |ADC can only work at Single mode when software selects the band-gap voltage as the analog input source of ADC
<> 144:ef7eb2e8f9f7 557 */
<> 144:ef7eb2e8f9f7 558 __IO uint32_t CHEN;
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 /**
<> 144:ef7eb2e8f9f7 561 * CMP
<> 144:ef7eb2e8f9f7 562 * ===================================================================================================
<> 144:ef7eb2e8f9f7 563 * Offset: 0x48 ADC Compare Register 0/1
<> 144:ef7eb2e8f9f7 564 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 565 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 566 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 567 * |[0] |ADCMPEN |Compare Enable Control
<> 144:ef7eb2e8f9f7 568 * | | |0 = Compare function Disabled.
<> 144:ef7eb2e8f9f7 569 * | | |1 = Compare function Enabled.
<> 144:ef7eb2e8f9f7 570 * | | |Set this bit to 1 to enable ADC controller to compare CMPDAT (ADC_CMPx[27:16]) with the conversion result of the channel specified by CMPCH (ADC_CMPx[6:3]) when the conversion data of the specified channel is loaded into ADC_DATx register.
<> 144:ef7eb2e8f9f7 571 * |[1] |ADCMPIE |Compare Interrupt Enable Control
<> 144:ef7eb2e8f9f7 572 * | | |0 = Compare function interrupt Disabled.
<> 144:ef7eb2e8f9f7 573 * | | |1 = Compare function interrupt Enabled.
<> 144:ef7eb2e8f9f7 574 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (ADC_CMPx[2]) and CMPMCNT(ADC_CMPx[11:8]), ADCMPFx (ADC_STATUS0[2:1]) bit will be asserted, in the meanwhile, if ADCMPIE (ADC_CMPx[1])is set to 1, a compare interrupt request is generated.
<> 144:ef7eb2e8f9f7 575 * |[2] |CMPCOND |Compare Condition
<> 144:ef7eb2e8f9f7 576 * | | |0 = Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one.
<> 144:ef7eb2e8f9f7 577 * | | |1 = Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (ADC_CMPx[27:16]), the internal match counter will increase one.
<> 144:ef7eb2e8f9f7 578 * | | |Note: When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
<> 144:ef7eb2e8f9f7 579 * |[3:6] |CMPCH |Compare Channel Selection
<> 144:ef7eb2e8f9f7 580 * | | |0000 = Channel 0 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 581 * | | |0001 = Channel 1 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 582 * | | |0010 = Channel 2 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 583 * | | |0011 = Channel 3 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 584 * | | |0100 = Channel 4 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 585 * | | |0101 = Channel 5 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 586 * | | |0110 = Channel 6 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 587 * | | |0111 = Channel 7 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 588 * | | |1000 = Channel 8 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 589 * | | |1001 = Channel 9 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 590 * | | |1010 = Channel 10 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 591 * | | |1011 = Channel 11 conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 592 * | | |1100 = band-gap voltage result is selected to be compared.
<> 144:ef7eb2e8f9f7 593 * | | |1101 = temperature sensor conversion result is selected to be compared.
<> 144:ef7eb2e8f9f7 594 * | | |Others = reserved.
<> 144:ef7eb2e8f9f7 595 * |[8:11] |CMPMCNT |Compare Match Count
<> 144:ef7eb2e8f9f7 596 * | | |When the specified ADC channel analog conversion result matches the compare condition defined by CMPCOND (ADC_CMPx[2]), the internal match counter will increase 1.
<> 144:ef7eb2e8f9f7 597 * | | |When the internal counter reaches the value to CMPMCNT (ADC_CMPx[11:8]) + 1, the ADCMPFx (ADC_STATUS0[2:1]) bit will be set.
<> 144:ef7eb2e8f9f7 598 * |[16:27] |CMPDAT |Compared Data
<> 144:ef7eb2e8f9f7 599 * | | |When DMOF (ADC_CTL[31]) bit is set to 0, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with unsigned format.
<> 144:ef7eb2e8f9f7 600 * | | |CMPDAT (ADC_CTL[27:16]) should be filled in unsigned format.
<> 144:ef7eb2e8f9f7 601 * | | |When DMOF (ADC_CTL[31]) bit is set to 1, ADC comparator compares CMPDAT (ADC_CTL[27:16]) with conversion result with 2'complement format.
<> 144:ef7eb2e8f9f7 602 * | | |CMPDAT (ADC_CTL[27:16]) should be filled in 2'complement format.
<> 144:ef7eb2e8f9f7 603 */
<> 144:ef7eb2e8f9f7 604 __IO uint32_t CMP[2];
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /**
<> 144:ef7eb2e8f9f7 607 * STATUS0
<> 144:ef7eb2e8f9f7 608 * ===================================================================================================
<> 144:ef7eb2e8f9f7 609 * Offset: 0x50 ADC Status Register 0
<> 144:ef7eb2e8f9f7 610 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 611 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 612 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 613 * |[0] |ADIF |ADC Interrupt Flag
<> 144:ef7eb2e8f9f7 614 * | | |A status flag that indicates the end of A/D conversion.
<> 144:ef7eb2e8f9f7 615 * | | |ADIF (ADC_STATUS0[0]) is set to 1 at these two conditions:
<> 144:ef7eb2e8f9f7 616 * | | |1. When A/D conversion ends in Single mode
<> 144:ef7eb2e8f9f7 617 * | | |2. When A/D conversion ends on all specified channels in Scan mode
<> 144:ef7eb2e8f9f7 618 * | | |Note: This flag can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 619 * |[1] |ADCMPF0 |Compare Flag
<> 144:ef7eb2e8f9f7 620 * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1.
<> 144:ef7eb2e8f9f7 621 * | | |And it is cleared by writing 1 to self.
<> 144:ef7eb2e8f9f7 622 * | | |0 = Conversion result in ADC_DATx does not meet ADCMPR0 setting.
<> 144:ef7eb2e8f9f7 623 * | | |1 = Conversion result in ADC_DATx meets ADCMPR0 setting.
<> 144:ef7eb2e8f9f7 624 * |[2] |ADCMPF1 |Compare Flag
<> 144:ef7eb2e8f9f7 625 * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1.
<> 144:ef7eb2e8f9f7 626 * | | |And it is cleared by writing 1 to self.
<> 144:ef7eb2e8f9f7 627 * | | |0 = Conversion result in ADC_DATx does not meet ADCMPR1 setting.
<> 144:ef7eb2e8f9f7 628 * | | |1 = Conversion result in ADC_DATx meets ADCMPR1 setting.
<> 144:ef7eb2e8f9f7 629 * |[3] |BUSY |BUSY/IDLE (Read Only)
<> 144:ef7eb2e8f9f7 630 * | | |0 = ADC is in idle state.
<> 144:ef7eb2e8f9f7 631 * | | |1 = ADC is doing conversion.
<> 144:ef7eb2e8f9f7 632 * | | |This bit is mirror of as SWTRG (ADC_CTL[11]) bit.
<> 144:ef7eb2e8f9f7 633 * |[4:7] |CHANNEL |Current Conversion Channel (Read Only)
<> 144:ef7eb2e8f9f7 634 * | | |This field reflects the current conversion channel when BUSY (ADC_STATUS0[3]) = 1.
<> 144:ef7eb2e8f9f7 635 * | | |When BUSY (ADC_STATUS0[3]) = 0, it shows the number of the next converted channel.
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 __IO uint32_t STATUS0;
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 /**
<> 144:ef7eb2e8f9f7 640 * STATUS1
<> 144:ef7eb2e8f9f7 641 * ===================================================================================================
<> 144:ef7eb2e8f9f7 642 * Offset: 0x54 ADC Status Register 1
<> 144:ef7eb2e8f9f7 643 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 644 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 645 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 646 * |[0:13] |VALID |Data Valid Flag (Read Only)
<> 144:ef7eb2e8f9f7 647 * | | |It is a mirror of VALID (ADC_DATx[17]) bit.
<> 144:ef7eb2e8f9f7 648 * |[16:29] |OV |Overrun Flag (Read Only)
<> 144:ef7eb2e8f9f7 649 * | | |It is a mirror to OV (ADC_DATx[16]) bit.
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651 __I uint32_t STATUS1;
<> 144:ef7eb2e8f9f7 652 uint32_t RESERVE1[2];
<> 144:ef7eb2e8f9f7 653
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /**
<> 144:ef7eb2e8f9f7 656 * CURDAT
<> 144:ef7eb2e8f9f7 657 * ===================================================================================================
<> 144:ef7eb2e8f9f7 658 * Offset: 0x60 ADC PDMA Current Transfer Data Register
<> 144:ef7eb2e8f9f7 659 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 660 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 661 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 662 * |[0:17] |CURDAT |ADC PDMA Current Transfer Data Bit (Read Only)
<> 144:ef7eb2e8f9f7 663 * | | |When PDMA transferring, read this register can monitor current PDMA transfer data.
<> 144:ef7eb2e8f9f7 664 */
<> 144:ef7eb2e8f9f7 665 __I uint32_t CURDAT;
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 } ADC_T;
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /**
<> 144:ef7eb2e8f9f7 670 @addtogroup ADC_CONST ADC Bit Field Definition
<> 144:ef7eb2e8f9f7 671 Constant Definitions for ADC Controller
<> 144:ef7eb2e8f9f7 672 @{ */
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 #define ADC_DAT0_RESULT_Pos (0) /*!< ADC DAT0: RESULT Position */
<> 144:ef7eb2e8f9f7 675 #define ADC_DAT0_RESULT_Msk (0xfffful << ADC_DAT0_RESULT_Pos) /*!< ADC DAT0: RESULT Mask */
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677 #define ADC_DAT0_OV_Pos (16) /*!< ADC DAT0: OV Position */
<> 144:ef7eb2e8f9f7 678 #define ADC_DAT0_OV_Msk (0x1ul << ADC_DAT0_OV_Pos) /*!< ADC DAT0: OV Mask */
<> 144:ef7eb2e8f9f7 679
<> 144:ef7eb2e8f9f7 680 #define ADC_DAT0_VALID_Pos (17) /*!< ADC DAT0: VALID Position */
<> 144:ef7eb2e8f9f7 681 #define ADC_DAT0_VALID_Msk (0x1ul << ADC_DAT0_VALID_Pos) /*!< ADC DAT0: VALID Mask */
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 #define ADC_DAT1_RESULT_Pos (0) /*!< ADC DAT1: RESULT Position */
<> 144:ef7eb2e8f9f7 684 #define ADC_DAT1_RESULT_Msk (0xfffful << ADC_DAT1_RESULT_Pos) /*!< ADC DAT1: RESULT Mask */
<> 144:ef7eb2e8f9f7 685
<> 144:ef7eb2e8f9f7 686 #define ADC_DAT1_OV_Pos (16) /*!< ADC DAT1: OV Position */
<> 144:ef7eb2e8f9f7 687 #define ADC_DAT1_OV_Msk (0x1ul << ADC_DAT1_OV_Pos) /*!< ADC DAT1: OV Mask */
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689 #define ADC_DAT1_VALID_Pos (17) /*!< ADC DAT1: VALID Position */
<> 144:ef7eb2e8f9f7 690 #define ADC_DAT1_VALID_Msk (0x1ul << ADC_DAT1_VALID_Pos) /*!< ADC DAT1: VALID Mask */
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 #define ADC_DAT2_RESULT_Pos (0) /*!< ADC DAT2: RESULT Position */
<> 144:ef7eb2e8f9f7 693 #define ADC_DAT2_RESULT_Msk (0xfffful << ADC_DAT2_RESULT_Pos) /*!< ADC DAT2: RESULT Mask */
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 #define ADC_DAT2_OV_Pos (16) /*!< ADC DAT2: OV Position */
<> 144:ef7eb2e8f9f7 696 #define ADC_DAT2_OV_Msk (0x1ul << ADC_DAT2_OV_Pos) /*!< ADC DAT2: OV Mask */
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 #define ADC_DAT2_VALID_Pos (17) /*!< ADC DAT2: VALID Position */
<> 144:ef7eb2e8f9f7 699 #define ADC_DAT2_VALID_Msk (0x1ul << ADC_DAT2_VALID_Pos) /*!< ADC DAT2: VALID Mask */
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 #define ADC_DAT3_RESULT_Pos (0) /*!< ADC DAT3: RESULT Position */
<> 144:ef7eb2e8f9f7 702 #define ADC_DAT3_RESULT_Msk (0xfffful << ADC_DAT3_RESULT_Pos) /*!< ADC DAT3: RESULT Mask */
<> 144:ef7eb2e8f9f7 703
<> 144:ef7eb2e8f9f7 704 #define ADC_DAT3_OV_Pos (16) /*!< ADC DAT3: OV Position */
<> 144:ef7eb2e8f9f7 705 #define ADC_DAT3_OV_Msk (0x1ul << ADC_DAT3_OV_Pos) /*!< ADC DAT3: OV Mask */
<> 144:ef7eb2e8f9f7 706
<> 144:ef7eb2e8f9f7 707 #define ADC_DAT3_VALID_Pos (17) /*!< ADC DAT3: VALID Position */
<> 144:ef7eb2e8f9f7 708 #define ADC_DAT3_VALID_Msk (0x1ul << ADC_DAT3_VALID_Pos) /*!< ADC DAT3: VALID Mask */
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 #define ADC_DAT4_RESULT_Pos (0) /*!< ADC DAT4: RESULT Position */
<> 144:ef7eb2e8f9f7 711 #define ADC_DAT4_RESULT_Msk (0xfffful << ADC_DAT4_RESULT_Pos) /*!< ADC DAT4: RESULT Mask */
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 #define ADC_DAT4_OV_Pos (16) /*!< ADC DAT4: OV Position */
<> 144:ef7eb2e8f9f7 714 #define ADC_DAT4_OV_Msk (0x1ul << ADC_DAT4_OV_Pos) /*!< ADC DAT4: OV Mask */
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 #define ADC_DAT4_VALID_Pos (17) /*!< ADC DAT4: VALID Position */
<> 144:ef7eb2e8f9f7 717 #define ADC_DAT4_VALID_Msk (0x1ul << ADC_DAT4_VALID_Pos) /*!< ADC DAT4: VALID Mask */
<> 144:ef7eb2e8f9f7 718
<> 144:ef7eb2e8f9f7 719 #define ADC_DAT5_RESULT_Pos (0) /*!< ADC DAT5: RESULT Position */
<> 144:ef7eb2e8f9f7 720 #define ADC_DAT5_RESULT_Msk (0xfffful << ADC_DAT5_RESULT_Pos) /*!< ADC DAT5: RESULT Mask */
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 #define ADC_DAT5_OV_Pos (16) /*!< ADC DAT5: OV Position */
<> 144:ef7eb2e8f9f7 723 #define ADC_DAT5_OV_Msk (0x1ul << ADC_DAT5_OV_Pos) /*!< ADC DAT5: OV Mask */
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 #define ADC_DAT5_VALID_Pos (17) /*!< ADC DAT5: VALID Position */
<> 144:ef7eb2e8f9f7 726 #define ADC_DAT5_VALID_Msk (0x1ul << ADC_DAT5_VALID_Pos) /*!< ADC DAT5: VALID Mask */
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 #define ADC_DAT6_RESULT_Pos (0) /*!< ADC DAT6: RESULT Position */
<> 144:ef7eb2e8f9f7 729 #define ADC_DAT6_RESULT_Msk (0xfffful << ADC_DAT6_RESULT_Pos) /*!< ADC DAT6: RESULT Mask */
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 #define ADC_DAT6_OV_Pos (16) /*!< ADC DAT6: OV Position */
<> 144:ef7eb2e8f9f7 732 #define ADC_DAT6_OV_Msk (0x1ul << ADC_DAT6_OV_Pos) /*!< ADC DAT6: OV Mask */
<> 144:ef7eb2e8f9f7 733
<> 144:ef7eb2e8f9f7 734 #define ADC_DAT6_VALID_Pos (17) /*!< ADC DAT6: VALID Position */
<> 144:ef7eb2e8f9f7 735 #define ADC_DAT6_VALID_Msk (0x1ul << ADC_DAT6_VALID_Pos) /*!< ADC DAT6: VALID Mask */
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 #define ADC_DAT7_RESULT_Pos (0) /*!< ADC DAT7: RESULT Position */
<> 144:ef7eb2e8f9f7 738 #define ADC_DAT7_RESULT_Msk (0xfffful << ADC_DAT7_RESULT_Pos) /*!< ADC DAT7: RESULT Mask */
<> 144:ef7eb2e8f9f7 739
<> 144:ef7eb2e8f9f7 740 #define ADC_DAT7_OV_Pos (16) /*!< ADC DAT7: OV Position */
<> 144:ef7eb2e8f9f7 741 #define ADC_DAT7_OV_Msk (0x1ul << ADC_DAT7_OV_Pos) /*!< ADC DAT7: OV Mask */
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 #define ADC_DAT7_VALID_Pos (17) /*!< ADC DAT7: VALID Position */
<> 144:ef7eb2e8f9f7 744 #define ADC_DAT7_VALID_Msk (0x1ul << ADC_DAT7_VALID_Pos) /*!< ADC DAT7: VALID Mask */
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 #define ADC_DAT8_RESULT_Pos (0) /*!< ADC DAT8: RESULT Position */
<> 144:ef7eb2e8f9f7 747 #define ADC_DAT8_RESULT_Msk (0xfffful << ADC_DAT8_RESULT_Pos) /*!< ADC DAT8: RESULT Mask */
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 #define ADC_DAT8_OV_Pos (16) /*!< ADC DAT8: OV Position */
<> 144:ef7eb2e8f9f7 750 #define ADC_DAT8_OV_Msk (0x1ul << ADC_DAT8_OV_Pos) /*!< ADC DAT8: OV Mask */
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 #define ADC_DAT8_VALID_Pos (17) /*!< ADC DAT8: VALID Position */
<> 144:ef7eb2e8f9f7 753 #define ADC_DAT8_VALID_Msk (0x1ul << ADC_DAT8_VALID_Pos) /*!< ADC DAT8: VALID Mask */
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 #define ADC_DAT9_RESULT_Pos (0) /*!< ADC DAT9: RESULT Position */
<> 144:ef7eb2e8f9f7 756 #define ADC_DAT9_RESULT_Msk (0xfffful << ADC_DAT9_RESULT_Pos) /*!< ADC DAT9: RESULT Mask */
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 #define ADC_DAT9_OV_Pos (16) /*!< ADC DAT9: OV Position */
<> 144:ef7eb2e8f9f7 759 #define ADC_DAT9_OV_Msk (0x1ul << ADC_DAT9_OV_Pos) /*!< ADC DAT9: OV Mask */
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 #define ADC_DAT9_VALID_Pos (17) /*!< ADC DAT9: VALID Position */
<> 144:ef7eb2e8f9f7 762 #define ADC_DAT9_VALID_Msk (0x1ul << ADC_DAT9_VALID_Pos) /*!< ADC DAT9: VALID Mask */
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 #define ADC_DAT10_RESULT_Pos (0) /*!< ADC DAT10: RESULT Position */
<> 144:ef7eb2e8f9f7 765 #define ADC_DAT10_RESULT_Msk (0xfffful << ADC_DAT10_RESULT_Pos) /*!< ADC DAT10: RESULT Mask */
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 #define ADC_DAT10_OV_Pos (16) /*!< ADC DAT10: OV Position */
<> 144:ef7eb2e8f9f7 768 #define ADC_DAT10_OV_Msk (0x1ul << ADC_DAT10_OV_Pos) /*!< ADC DAT10: OV Mask */
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 #define ADC_DAT10_VALID_Pos (17) /*!< ADC DAT10: VALID Position */
<> 144:ef7eb2e8f9f7 771 #define ADC_DAT10_VALID_Msk (0x1ul << ADC_DAT10_VALID_Pos) /*!< ADC DAT10: VALID Mask */
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 #define ADC_DAT11_RESULT_Pos (0) /*!< ADC DAT11: RESULT Position */
<> 144:ef7eb2e8f9f7 774 #define ADC_DAT11_RESULT_Msk (0xfffful << ADC_DAT11_RESULT_Pos) /*!< ADC DAT11: RESULT Mask */
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 #define ADC_DAT11_OV_Pos (16) /*!< ADC DAT11: OV Position */
<> 144:ef7eb2e8f9f7 777 #define ADC_DAT11_OV_Msk (0x1ul << ADC_DAT11_OV_Pos) /*!< ADC DAT11: OV Mask */
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 #define ADC_DAT11_VALID_Pos (17) /*!< ADC DAT11: VALID Position */
<> 144:ef7eb2e8f9f7 780 #define ADC_DAT11_VALID_Msk (0x1ul << ADC_DAT11_VALID_Pos) /*!< ADC DAT11: VALID Mask */
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 #define ADC_DAT12_RESULT_Pos (0) /*!< ADC DAT12: RESULT Position */
<> 144:ef7eb2e8f9f7 783 #define ADC_DAT12_RESULT_Msk (0xfffful << ADC_DAT12_RESULT_Pos) /*!< ADC DAT12: RESULT Mask */
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 #define ADC_DAT12_OV_Pos (16) /*!< ADC DAT12: OV Position */
<> 144:ef7eb2e8f9f7 786 #define ADC_DAT12_OV_Msk (0x1ul << ADC_DAT12_OV_Pos) /*!< ADC DAT12: OV Mask */
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 #define ADC_DAT12_VALID_Pos (17) /*!< ADC DAT12: VALID Position */
<> 144:ef7eb2e8f9f7 789 #define ADC_DAT12_VALID_Msk (0x1ul << ADC_DAT12_VALID_Pos) /*!< ADC DAT12: VALID Mask */
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 #define ADC_DAT13_RESULT_Pos (0) /*!< ADC DAT13: RESULT Position */
<> 144:ef7eb2e8f9f7 792 #define ADC_DAT13_RESULT_Msk (0xfffful << ADC_DAT13_RESULT_Pos) /*!< ADC DAT13: RESULT Mask */
<> 144:ef7eb2e8f9f7 793
<> 144:ef7eb2e8f9f7 794 #define ADC_DAT13_OV_Pos (16) /*!< ADC DAT13: OV Position */
<> 144:ef7eb2e8f9f7 795 #define ADC_DAT13_OV_Msk (0x1ul << ADC_DAT13_OV_Pos) /*!< ADC DAT13: OV Mask */
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 #define ADC_DAT13_VALID_Pos (17) /*!< ADC DAT13: VALID Position */
<> 144:ef7eb2e8f9f7 798 #define ADC_DAT13_VALID_Msk (0x1ul << ADC_DAT13_VALID_Pos) /*!< ADC DAT13: VALID Mask */
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 #define ADC_CTL_ADCEN_Pos (0) /*!< ADC CTL: ADCEN Position */
<> 144:ef7eb2e8f9f7 801 #define ADC_CTL_ADCEN_Msk (0x1ul << ADC_CTL_ADCEN_Pos) /*!< ADC CTL: ADCEN Mask */
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 #define ADC_CTL_ADCIEN_Pos (1) /*!< ADC CTL: ADCIEN Position */
<> 144:ef7eb2e8f9f7 804 #define ADC_CTL_ADCIEN_Msk (0x1ul << ADC_CTL_ADCIEN_Pos) /*!< ADC CTL: ADCIEN Mask */
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 #define ADC_CTL_OPMODE_Pos (2) /*!< ADC CTL: OPMODE Position */
<> 144:ef7eb2e8f9f7 807 #define ADC_CTL_OPMODE_Msk (0x3ul << ADC_CTL_OPMODE_Pos) /*!< ADC CTL: OPMODE Mask */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 #define ADC_CTL_HWTRGSEL_Pos (4) /*!< ADC CTL: HWTRGSEL Position */
<> 144:ef7eb2e8f9f7 810 #define ADC_CTL_HWTRGSEL_Msk (0x3ul << ADC_CTL_HWTRGSEL_Pos) /*!< ADC CTL: HWTRGSEL Mask */
<> 144:ef7eb2e8f9f7 811
<> 144:ef7eb2e8f9f7 812 #define ADC_CTL_HWTRGCOND_Pos (6) /*!< ADC CTL: HWTRGCOND Position */
<> 144:ef7eb2e8f9f7 813 #define ADC_CTL_HWTRGCOND_Msk (0x3ul << ADC_CTL_HWTRGCOND_Pos) /*!< ADC CTL: HWTRGCOND Mask */
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 #define ADC_CTL_HWTRGEN_Pos (8) /*!< ADC CTL: HWTRGEN Position */
<> 144:ef7eb2e8f9f7 816 #define ADC_CTL_HWTRGEN_Msk (0x1ul << ADC_CTL_HWTRGEN_Pos) /*!< ADC CTL: HWTRGEN Mask */
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 #define ADC_CTL_PDMAEN_Pos (9) /*!< ADC CTL: PDMAEN Position */
<> 144:ef7eb2e8f9f7 819 #define ADC_CTL_PDMAEN_Msk (0x1ul << ADC_CTL_PDMAEN_Pos) /*!< ADC CTL: PDMAEN Mask */
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 #define ADC_CTL_DIFFEN_Pos (10) /*!< ADC CTL: DIFFEN Position */
<> 144:ef7eb2e8f9f7 822 #define ADC_CTL_DIFFEN_Msk (0x1ul << ADC_CTL_DIFFEN_Pos) /*!< ADC CTL: DIFFEN Mask */
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 #define ADC_CTL_SWTRG_Pos (11) /*!< ADC CTL: SWTRG Position */
<> 144:ef7eb2e8f9f7 825 #define ADC_CTL_SWTRG_Msk (0x1ul << ADC_CTL_SWTRG_Pos) /*!< ADC CTL: SWTRG Mask */
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 #define ADC_CTL_PWMTRGDLY_Pos (16) /*!< ADC CTL: PWMTRGDLY Position */
<> 144:ef7eb2e8f9f7 828 #define ADC_CTL_PWMTRGDLY_Msk (0xfful << ADC_CTL_PWMTRGDLY_Pos) /*!< ADC CTL: PWMTRGDLY Mask */
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 #define ADC_CTL_DMOF_Pos (31) /*!< ADC CTL: DMOF Position */
<> 144:ef7eb2e8f9f7 831 #define ADC_CTL_DMOF_Msk (0x1ul << ADC_CTL_DMOF_Pos) /*!< ADC CTL: DMOF Mask */
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 #define ADC_CHEN_CHEN_Pos (0) /*!< ADC CHEN: CHEN Position */
<> 144:ef7eb2e8f9f7 834 #define ADC_CHEN_CHEN_Msk (0xffful << ADC_CHEN_CHEN_Pos) /*!< ADC CHEN: CHEN Mask */
<> 144:ef7eb2e8f9f7 835
<> 144:ef7eb2e8f9f7 836 #define ADC_CHEN_ADTSEN_Pos (16) /*!< ADC CHEN: ADTSEN Position */
<> 144:ef7eb2e8f9f7 837 #define ADC_CHEN_ADTSEN_Msk (0x1ul << ADC_CHEN_ADTSEN_Pos) /*!< ADC CHEN: ADTSEN Mask */
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 #define ADC_CHEN_ADBGEN_Pos (17) /*!< ADC CHEN: ADBGEN Position */
<> 144:ef7eb2e8f9f7 840 #define ADC_CHEN_ADBGEN_Msk (0x1ul << ADC_CHEN_ADBGEN_Pos) /*!< ADC CHEN: ADBGEN Mask */
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 #define ADC_CMP0_ADCMPEN_Pos (0) /*!< ADC CMP0: ADCMPEN Position */
<> 144:ef7eb2e8f9f7 843 #define ADC_CMP0_ADCMPEN_Msk (0x1ul << ADC_CMP0_ADCMPEN_Pos) /*!< ADC CMP0: ADCMPEN Mask */
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 #define ADC_CMP0_ADCMPIE_Pos (1) /*!< ADC CMP0: ADCMPIE Position */
<> 144:ef7eb2e8f9f7 846 #define ADC_CMP0_ADCMPIE_Msk (0x1ul << ADC_CMP0_ADCMPIE_Pos) /*!< ADC CMP0: ADCMPIE Mask */
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 #define ADC_CMP0_CMPCOND_Pos (2) /*!< ADC CMP0: CMPCOND Position */
<> 144:ef7eb2e8f9f7 849 #define ADC_CMP0_CMPCOND_Msk (0x1ul << ADC_CMP0_CMPCOND_Pos) /*!< ADC CMP0: CMPCOND Mask */
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 #define ADC_CMP0_CMPCH_Pos (3) /*!< ADC CMP0: CMPCH Position */
<> 144:ef7eb2e8f9f7 852 #define ADC_CMP0_CMPCH_Msk (0xful << ADC_CMP0_CMPCH_Pos) /*!< ADC CMP0: CMPCH Mask */
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 #define ADC_CMP0_CMPMCNT_Pos (8) /*!< ADC CMP0: CMPMCNT Position */
<> 144:ef7eb2e8f9f7 855 #define ADC_CMP0_CMPMCNT_Msk (0xful << ADC_CMP0_CMPMCNT_Pos) /*!< ADC CMP0: CMPMCNT Mask */
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 #define ADC_CMP0_CMPDAT_Pos (16) /*!< ADC CMP0: CMPDAT Position */
<> 144:ef7eb2e8f9f7 858 #define ADC_CMP0_CMPDAT_Msk (0xffful << ADC_CMP0_CMPDAT_Pos) /*!< ADC CMP0: CMPDAT Mask */
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 #define ADC_CMP1_ADCMPEN_Pos (0) /*!< ADC CMP1: ADCMPEN Position */
<> 144:ef7eb2e8f9f7 861 #define ADC_CMP1_ADCMPEN_Msk (0x1ul << ADC_CMP1_ADCMPEN_Pos) /*!< ADC CMP1: ADCMPEN Mask */
<> 144:ef7eb2e8f9f7 862
<> 144:ef7eb2e8f9f7 863 #define ADC_CMP1_ADCMPIE_Pos (1) /*!< ADC CMP1: ADCMPIE Position */
<> 144:ef7eb2e8f9f7 864 #define ADC_CMP1_ADCMPIE_Msk (0x1ul << ADC_CMP1_ADCMPIE_Pos) /*!< ADC CMP1: ADCMPIE Mask */
<> 144:ef7eb2e8f9f7 865
<> 144:ef7eb2e8f9f7 866 #define ADC_CMP1_CMPCOND_Pos (2) /*!< ADC CMP1: CMPCOND Position */
<> 144:ef7eb2e8f9f7 867 #define ADC_CMP1_CMPCOND_Msk (0x1ul << ADC_CMP1_CMPCOND_Pos) /*!< ADC CMP1: CMPCOND Mask */
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 #define ADC_CMP1_CMPCH_Pos (3) /*!< ADC CMP1: CMPCH Position */
<> 144:ef7eb2e8f9f7 870 #define ADC_CMP1_CMPCH_Msk (0xful << ADC_CMP1_CMPCH_Pos) /*!< ADC CMP1: CMPCH Mask */
<> 144:ef7eb2e8f9f7 871
<> 144:ef7eb2e8f9f7 872 #define ADC_CMP1_CMPMCNT_Pos (8) /*!< ADC CMP1: CMPMCNT Position */
<> 144:ef7eb2e8f9f7 873 #define ADC_CMP1_CMPMCNT_Msk (0xful << ADC_CMP1_CMPMCNT_Pos) /*!< ADC CMP1: CMPMCNT Mask */
<> 144:ef7eb2e8f9f7 874
<> 144:ef7eb2e8f9f7 875 #define ADC_CMP1_CMPDAT_Pos (16) /*!< ADC CMP1: CMPDAT Position */
<> 144:ef7eb2e8f9f7 876 #define ADC_CMP1_CMPDAT_Msk (0xffful << ADC_CMP1_CMPDAT_Pos) /*!< ADC CMP1: CMPDAT Mask */
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 #define ADC_STATUS0_ADIF_Pos (0) /*!< ADC STATUS0: ADIF Position */
<> 144:ef7eb2e8f9f7 879 #define ADC_STATUS0_ADIF_Msk (0x1ul << ADC_STATUS0_ADIF_Pos) /*!< ADC STATUS0: ADIF Mask */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 #define ADC_STATUS0_ADCMPF0_Pos (1) /*!< ADC STATUS0: ADCMPF0 Position */
<> 144:ef7eb2e8f9f7 882 #define ADC_STATUS0_ADCMPF0_Msk (0x1ul << ADC_STATUS0_ADCMPF0_Pos) /*!< ADC STATUS0: ADCMPF0 Mask */
<> 144:ef7eb2e8f9f7 883
<> 144:ef7eb2e8f9f7 884 #define ADC_STATUS0_ADCMPF1_Pos (2) /*!< ADC STATUS0: ADCMPF1 Position */
<> 144:ef7eb2e8f9f7 885 #define ADC_STATUS0_ADCMPF1_Msk (0x1ul << ADC_STATUS0_ADCMPF1_Pos) /*!< ADC STATUS0: ADCMPF1 Mask */
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 #define ADC_STATUS0_BUSY_Pos (3) /*!< ADC STATUS0: BUSY Position */
<> 144:ef7eb2e8f9f7 888 #define ADC_STATUS0_BUSY_Msk (0x1ul << ADC_STATUS0_BUSY_Pos) /*!< ADC STATUS0: BUSY Mask */
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 #define ADC_STATUS0_CHANNEL_Pos (4) /*!< ADC STATUS0: CHANNEL Position */
<> 144:ef7eb2e8f9f7 891 #define ADC_STATUS0_CHANNEL_Msk (0xful << ADC_STATUS0_CHANNEL_Pos) /*!< ADC STATUS0: CHANNEL Mask */
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 #define ADC_STATUS1_VALID_Pos (0) /*!< ADC STATUS1: VALID Position */
<> 144:ef7eb2e8f9f7 894 #define ADC_STATUS1_VALID_Msk (0x3ffful << ADC_STATUS1_VALID_Pos) /*!< ADC STATUS1: VALID Mask */
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 #define ADC_STATUS1_OV_Pos (16) /*!< ADC STATUS1: OV Position */
<> 144:ef7eb2e8f9f7 897 #define ADC_STATUS1_OV_Msk (0x3ffful << ADC_STATUS1_OV_Pos) /*!< ADC STATUS1: OV Mask */
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 #define ADC_CURDAT_CURDAT_Pos (0) /*!< ADC CURDAT: CURDAT Position */
<> 144:ef7eb2e8f9f7 900 #define ADC_CURDAT_CURDAT_Msk (0x3fffful << ADC_CURDAT_CURDAT_Pos) /*!< ADC CURDAT: CURDAT Mask */
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 /**@}*/ /* ADC_CONST */
<> 144:ef7eb2e8f9f7 903 /**@}*/ /* end of ADC register group */
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /*---------------------- Controller Area Network Controller -------------------------*/
<> 144:ef7eb2e8f9f7 907 /**
<> 144:ef7eb2e8f9f7 908 @addtogroup CAN Controller Area Network Controller(CAN)
<> 144:ef7eb2e8f9f7 909 Memory Mapped Structure for CAN Controller
<> 144:ef7eb2e8f9f7 910 @{ */
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 typedef struct {
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /**
<> 144:ef7eb2e8f9f7 915 * CAN_IFn_CREQ
<> 144:ef7eb2e8f9f7 916 * ===================================================================================================
<> 144:ef7eb2e8f9f7 917 * Offset: 0x20, 0x80 IFn (Register Map Note 2) Command Request Registers
<> 144:ef7eb2e8f9f7 918 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 919 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 920 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 921 * |[0:5] |MessageNumber|Message Number
<> 144:ef7eb2e8f9f7 922 * | | |0x01-0x20: Valid Message Number, the Message Object in the Message
<> 144:ef7eb2e8f9f7 923 * | | |RAM is selected for data transfer.
<> 144:ef7eb2e8f9f7 924 * | | |0x00: Not a valid Message Number, interpreted as 0x20.
<> 144:ef7eb2e8f9f7 925 * | | |0x21-0x3F: Not a valid Message Number, interpreted as 0x01-0x1F.
<> 144:ef7eb2e8f9f7 926 * |[15] |Busy |Busy Flag
<> 144:ef7eb2e8f9f7 927 * | | |0 = Read/write action has finished.
<> 144:ef7eb2e8f9f7 928 * | | |1 = Writing to the IFn Command Request Register is in progress.
<> 144:ef7eb2e8f9f7 929 * | | |This bit can only be read by the software.
<> 144:ef7eb2e8f9f7 930 */
<> 144:ef7eb2e8f9f7 931 __IO uint32_t CREQ;
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /**
<> 144:ef7eb2e8f9f7 934 * CAN_IFn_CMASK
<> 144:ef7eb2e8f9f7 935 * ===================================================================================================
<> 144:ef7eb2e8f9f7 936 * Offset: 0x24, 0x84 IFn Command Mask Register
<> 144:ef7eb2e8f9f7 937 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 938 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 939 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 940 * |[0] |DAT_B |Access Data Bytes [7:4]
<> 144:ef7eb2e8f9f7 941 * | | |Write Operation:
<> 144:ef7eb2e8f9f7 942 * | | |0 = Data Bytes [7:4] unchanged.
<> 144:ef7eb2e8f9f7 943 * | | |1 = Transfer Data Bytes [7:4] to Message Object.
<> 144:ef7eb2e8f9f7 944 * | | |Read Operation:
<> 144:ef7eb2e8f9f7 945 * | | |0 = Data Bytes [7:4] unchanged.
<> 144:ef7eb2e8f9f7 946 * | | |1 = Transfer Data Bytes [7:4] to IFn Message Buffer Register.
<> 144:ef7eb2e8f9f7 947 * |[1] |DAT_A |Access Data Bytes [3:0]
<> 144:ef7eb2e8f9f7 948 * | | |Write Operation:
<> 144:ef7eb2e8f9f7 949 * | | |0 = Data Bytes [3:0] unchanged.
<> 144:ef7eb2e8f9f7 950 * | | |1 = Transfer Data Bytes [3:0] to Message Object.
<> 144:ef7eb2e8f9f7 951 * | | |Read Operation:
<> 144:ef7eb2e8f9f7 952 * | | |0 = Data Bytes [3:0] unchanged.
<> 144:ef7eb2e8f9f7 953 * | | |1 = Transfer Data Bytes [3:0] to IFn Message Buffer Register.
<> 144:ef7eb2e8f9f7 954 * |[2] |TxRqst_NewDat|Access Transmission Request Bit When Write Operation
<> 144:ef7eb2e8f9f7 955 * | | |0 = TxRqst bit unchanged.
<> 144:ef7eb2e8f9f7 956 * | | |1 = Set TxRqst bit.
<> 144:ef7eb2e8f9f7 957 * | | |Note: If a transmission is requested by programming bit TxRqst/NewDat in the IFn Command Mask Register, bit TxRqst in the IFn Message Control Register will be ignored.
<> 144:ef7eb2e8f9f7 958 * | | |Access New Data Bit when Read Operation.
<> 144:ef7eb2e8f9f7 959 * | | |0 = NewDat bit remains unchanged.
<> 144:ef7eb2e8f9f7 960 * | | |1 = Clear NewDat bit in the Message Object.
<> 144:ef7eb2e8f9f7 961 * | | |Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat.
<> 144:ef7eb2e8f9f7 962 * | | |The values of these bits transferred to the IFn Message Control Register always reflect the status before resetting these bits.
<> 144:ef7eb2e8f9f7 963 * |[3] |ClrIntPnd |Clear Interrupt Pending Bit
<> 144:ef7eb2e8f9f7 964 * | | |Write Operation:
<> 144:ef7eb2e8f9f7 965 * | | |When writing to a Message Object, this bit is ignored.
<> 144:ef7eb2e8f9f7 966 * | | |Read Operation:
<> 144:ef7eb2e8f9f7 967 * | | |0 = IntPnd bit (CAN_IFn_MCON[13]) remains unchanged.
<> 144:ef7eb2e8f9f7 968 * | | |1 = Clear IntPnd bit in the Message Object.
<> 144:ef7eb2e8f9f7 969 * |[4] |Control |Control Access Control Bits
<> 144:ef7eb2e8f9f7 970 * | | |Write Operation:
<> 144:ef7eb2e8f9f7 971 * | | |0 = Control Bits unchanged.
<> 144:ef7eb2e8f9f7 972 * | | |1 = Transfer Control Bits to Message Object.
<> 144:ef7eb2e8f9f7 973 * | | |Read Operation:
<> 144:ef7eb2e8f9f7 974 * | | |0 = Control Bits unchanged.
<> 144:ef7eb2e8f9f7 975 * | | |1 = Transfer Control Bits to IFn Message Buffer Register.
<> 144:ef7eb2e8f9f7 976 * |[5] |Arb |Access Arbitration Bits
<> 144:ef7eb2e8f9f7 977 * | | |Write Operation:
<> 144:ef7eb2e8f9f7 978 * | | |0 = Arbitration bits unchanged.
<> 144:ef7eb2e8f9f7 979 * | | |1 = Transfer Identifier + Dir (CAN_IFn_ARB2[13]) + Xtd (CAN_IFn_ARB2[14]) + MsgVal (CAN_IFn_APB2[15]) to Message Object.
<> 144:ef7eb2e8f9f7 980 * | | |Read Operation:
<> 144:ef7eb2e8f9f7 981 * | | |0 = Arbitration bits unchanged.
<> 144:ef7eb2e8f9f7 982 * | | |1 = Transfer Identifier + Dir + Xtd + MsgVal to IFn Message Buffer Register.
<> 144:ef7eb2e8f9f7 983 * |[6] |Mask |Access Mask Bits
<> 144:ef7eb2e8f9f7 984 * | | |Write Operation:
<> 144:ef7eb2e8f9f7 985 * | | |0 = Mask bits unchanged.
<> 144:ef7eb2e8f9f7 986 * | | |1 = Transfer Identifier Mask + MDir + MXtd to Message Object.
<> 144:ef7eb2e8f9f7 987 * | | |Read Operation:
<> 144:ef7eb2e8f9f7 988 * | | |0 = Mask bits unchanged.
<> 144:ef7eb2e8f9f7 989 * | | |1 = Transfer Identifier Mask + MDir + MXtd to IFn Message Buffer Register.
<> 144:ef7eb2e8f9f7 990 * |[7] |WR_RD |Write / Read Mode
<> 144:ef7eb2e8f9f7 991 * | | |0 = Read: Transfer data from the Message Object addressed by the Command Request Register into the selected Message Buffer Registers.
<> 144:ef7eb2e8f9f7 992 * | | |1 = Write: Transfer data from the selected Message Buffer Registers to the Message Object addressed by the Command Request Register.
<> 144:ef7eb2e8f9f7 993 */
<> 144:ef7eb2e8f9f7 994 __IO uint32_t CMASK;
<> 144:ef7eb2e8f9f7 995
<> 144:ef7eb2e8f9f7 996 /**
<> 144:ef7eb2e8f9f7 997 * CAN_IFn_MASK1
<> 144:ef7eb2e8f9f7 998 * ===================================================================================================
<> 144:ef7eb2e8f9f7 999 * Offset: 0x28, 0x88 IFn Mask 1 Register
<> 144:ef7eb2e8f9f7 1000 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1001 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1002 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1003 * |[0:15] |Msk150 |Identifier Mask 15-0
<> 144:ef7eb2e8f9f7 1004 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
<> 144:ef7eb2e8f9f7 1005 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
<> 144:ef7eb2e8f9f7 1006 */
<> 144:ef7eb2e8f9f7 1007 __IO uint32_t MASK1;
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /**
<> 144:ef7eb2e8f9f7 1010 * CAN_IFn_MASK2
<> 144:ef7eb2e8f9f7 1011 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1012 * Offset: 0x2C, 0x8C IFn Mask 2 Register
<> 144:ef7eb2e8f9f7 1013 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1014 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1015 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1016 * |[0:12] |Msk2816 |Identifier Mask 28-16
<> 144:ef7eb2e8f9f7 1017 * | | |0 = The corresponding bit in the identifier of the message object cannot inhibit the match in the acceptance filtering.
<> 144:ef7eb2e8f9f7 1018 * | | |1 = The corresponding identifier bit is used for acceptance filtering.
<> 144:ef7eb2e8f9f7 1019 * |[14] |MDir |Mask Message Direction
<> 144:ef7eb2e8f9f7 1020 * | | |0 = The message direction bit (Dir (CAN_IFn_ARB2[13])) has no effect on the acceptance filtering.
<> 144:ef7eb2e8f9f7 1021 * | | |1 = The message direction bit (Dir) is used for acceptance filtering.
<> 144:ef7eb2e8f9f7 1022 * |[15] |MXtd |Mask Extended Identifier
<> 144:ef7eb2e8f9f7 1023 * | | |0 = The extended identifier bit (IDE) has no effect on the acceptance filtering.
<> 144:ef7eb2e8f9f7 1024 * | | |1 = The extended identifier bit (IDE) is used for acceptance filtering.
<> 144:ef7eb2e8f9f7 1025 * | | |Note: When 11-bit ("standard") Identifiers are used for a Message Object, the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2]).
<> 144:ef7eb2e8f9f7 1026 * | | |For acceptance filtering, only these bits together with mask bits Msk28 to Msk18 (CAN_IFn_MASK2[12:2]) are considered.
<> 144:ef7eb2e8f9f7 1027 */
<> 144:ef7eb2e8f9f7 1028 __IO uint32_t MASK2;
<> 144:ef7eb2e8f9f7 1029
<> 144:ef7eb2e8f9f7 1030 /**
<> 144:ef7eb2e8f9f7 1031 * CAN_IFn_ARB1
<> 144:ef7eb2e8f9f7 1032 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1033 * Offset: 0x30, 0x90 IFn Arbitration 1 Register
<> 144:ef7eb2e8f9f7 1034 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1035 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1036 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1037 * |[0:15] |ID150 |Message Identifier 15-0
<> 144:ef7eb2e8f9f7 1038 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
<> 144:ef7eb2e8f9f7 1039 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
<> 144:ef7eb2e8f9f7 1040 */
<> 144:ef7eb2e8f9f7 1041 __IO uint32_t ARB1;
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 /**
<> 144:ef7eb2e8f9f7 1044 * CAN_IFn_ARB2
<> 144:ef7eb2e8f9f7 1045 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1046 * Offset: 0x34, 0x94 IFn Arbitration 2 Register
<> 144:ef7eb2e8f9f7 1047 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1048 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1049 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1050 * |[0:12] |ID2816 |Message Identifier 28-16
<> 144:ef7eb2e8f9f7 1051 * | | |ID28 - ID0, 29-bit Identifier ("Extended Frame").
<> 144:ef7eb2e8f9f7 1052 * | | |ID28 - ID18, 11-bit Identifier ("Standard Frame")
<> 144:ef7eb2e8f9f7 1053 * |[13] |Dir |Message Direction
<> 144:ef7eb2e8f9f7 1054 * | | |0 = Direction is receive.
<> 144:ef7eb2e8f9f7 1055 * | | |On TxRqst, a Remote Frame with the identifier of this Message Object is transmitted.
<> 144:ef7eb2e8f9f7 1056 * | | |On reception of a Data Frame with matching identifier, that message is stored in this Message Object.
<> 144:ef7eb2e8f9f7 1057 * | | |1 = Direction is transmit.
<> 144:ef7eb2e8f9f7 1058 * | | |On TxRqst, the respective Message Object is transmitted as a Data Frame.
<> 144:ef7eb2e8f9f7 1059 * | | |On reception of a Remote Frame with matching identifier, the TxRqst bit (CAN_IFn_CMASK[2]) of this Message Object is set (if RmtEn (CAN_IFn_MCON[9]) = one).
<> 144:ef7eb2e8f9f7 1060 * |[14] |Xtd |Extended Identifier
<> 144:ef7eb2e8f9f7 1061 * | | |0 = The 11-bit ("standard") Identifier will be used for this Message Object.
<> 144:ef7eb2e8f9f7 1062 * | | |1 = The 29-bit ("extended") Identifier will be used for this Message Object.
<> 144:ef7eb2e8f9f7 1063 * |[15] |MsgVal |Message Valid
<> 144:ef7eb2e8f9f7 1064 * | | |0 = The Message Object is ignored by the Message Handler.
<> 144:ef7eb2e8f9f7 1065 * | | |1 = The Message Object is configured and should be considered by the Message Handler.
<> 144:ef7eb2e8f9f7 1066 * | | |Note: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0]).
<> 144:ef7eb2e8f9f7 1067 * | | |This bit must also be reset before the identifier Id28-0 (CAN_IFn_ARB1/2), the control bits Xtd (CAN_IFn_ARB2[14]), Dir (CAN_IFn_APB2[13]), or the Data Length Code DLC3-0 (CAN_IFn_MCON[3:0]) are modified, or if the Messages Object is no longer required.
<> 144:ef7eb2e8f9f7 1068 */
<> 144:ef7eb2e8f9f7 1069 __IO uint32_t ARB2;
<> 144:ef7eb2e8f9f7 1070
<> 144:ef7eb2e8f9f7 1071 /**
<> 144:ef7eb2e8f9f7 1072 * CAN_IFn_MCON
<> 144:ef7eb2e8f9f7 1073 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1074 * Offset: 0x38, 0x98 IFn Message Control Register
<> 144:ef7eb2e8f9f7 1075 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1076 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1077 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1078 * |[0:3] |DLC |Data Length Code
<> 144:ef7eb2e8f9f7 1079 * | | |0-8: Data Frame has 0-8 data bytes.
<> 144:ef7eb2e8f9f7 1080 * | | |9-15: Data Frame has 8 data bytes
<> 144:ef7eb2e8f9f7 1081 * | | |Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes.
<> 144:ef7eb2e8f9f7 1082 * | | |When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.
<> 144:ef7eb2e8f9f7 1083 * | | |Data 0: 1st data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1084 * | | |Data 1: 2nd data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1085 * | | |Data 2: 3rd data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1086 * | | |Data 3: 4th data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1087 * | | |Data 4: 5th data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1088 * | | |Data 5: 6th data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1089 * | | |Data 6: 7th data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1090 * | | |Data 7 : 8th data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1091 * | | |Note: The Data 0 Byte is the first data byte shifted into the shift register of the CAN Core during a reception while the Data 7 byte is the last.
<> 144:ef7eb2e8f9f7 1092 * | | |When the Message Handler stores a Data Frame, it will write all the eight data bytes into a Message Object.
<> 144:ef7eb2e8f9f7 1093 * | | |If the Data Length Code is less than 8, the remaining bytes of the Message Object will be overwritten by unspecified values.
<> 144:ef7eb2e8f9f7 1094 * |[7] |EoB |End Of Buffer
<> 144:ef7eb2e8f9f7 1095 * | | |0 = Message Object belongs to a FIFO Buffer and is not the last Message Object of that FIFO Buffer.
<> 144:ef7eb2e8f9f7 1096 * | | |1 = Single Message Object or last Message Object of a FIFO Buffer.
<> 144:ef7eb2e8f9f7 1097 * | | |Note: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer.
<> 144:ef7eb2e8f9f7 1098 * | | |For single Message Objects (not belonging to a FIFO Buffer), this bit must always be set to one.
<> 144:ef7eb2e8f9f7 1099 * |[8] |TxRqst |Transmit Request
<> 144:ef7eb2e8f9f7 1100 * | | |0 = This Message Object is not waiting for transmission.
<> 144:ef7eb2e8f9f7 1101 * | | |1 = The transmission of this Message Object is requested and is not yet done.
<> 144:ef7eb2e8f9f7 1102 * |[9] |RmtEn |Remote Enable Control
<> 144:ef7eb2e8f9f7 1103 * | | |0 = At the reception of a Remote Frame, TxRqst (CAN_IFn_MCON[8]) is left unchanged.
<> 144:ef7eb2e8f9f7 1104 * | | |1 = At the reception of a Remote Frame, TxRqst is set.
<> 144:ef7eb2e8f9f7 1105 * |[10] |RxIE |Receive Interrupt Enable Control
<> 144:ef7eb2e8f9f7 1106 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after a successful reception of a frame.
<> 144:ef7eb2e8f9f7 1107 * | | |1 = IntPnd will be set after a successful reception of a frame.
<> 144:ef7eb2e8f9f7 1108 * |[11] |TxIE |Transmit Interrupt Enable Control
<> 144:ef7eb2e8f9f7 1109 * | | |0 = IntPnd (CAN_IFn_MCON[13]) will be left unchanged after the successful transmission of a frame.
<> 144:ef7eb2e8f9f7 1110 * | | |1 = IntPnd will be set after a successful transmission of a frame.
<> 144:ef7eb2e8f9f7 1111 * |[12] |UMask |Use Acceptance Mask
<> 144:ef7eb2e8f9f7 1112 * | | |0 = Mask ignored.
<> 144:ef7eb2e8f9f7 1113 * | | |1 = Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering.
<> 144:ef7eb2e8f9f7 1114 * | | |Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_APB2[15]) is set to one.
<> 144:ef7eb2e8f9f7 1115 * |[13] |IntPnd |Interrupt Pending
<> 144:ef7eb2e8f9f7 1116 * | | |0 = This message object is not the source of an interrupt.
<> 144:ef7eb2e8f9f7 1117 * | | |1 = This message object is the source of an interrupt.
<> 144:ef7eb2e8f9f7 1118 * | | |The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
<> 144:ef7eb2e8f9f7 1119 * |[14] |MsgLst |Message Lost (only valid for Message Objects with direction = receive).
<> 144:ef7eb2e8f9f7 1120 * | | |0 = No message lost since last time this bit was reset by the CPU.
<> 144:ef7eb2e8f9f7 1121 * | | |1 = The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
<> 144:ef7eb2e8f9f7 1122 * |[15] |NewDat |New Data
<> 144:ef7eb2e8f9f7 1123 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the application software.
<> 144:ef7eb2e8f9f7 1124 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
<> 144:ef7eb2e8f9f7 1125 */
<> 144:ef7eb2e8f9f7 1126 __IO uint32_t MCON;
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /**
<> 144:ef7eb2e8f9f7 1129 * CAN_IFn_DAT_A1
<> 144:ef7eb2e8f9f7 1130 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1131 * Offset: 0x3C, 0x9C IFn Data A1 Register (Register Map Note 3)
<> 144:ef7eb2e8f9f7 1132 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1133 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1134 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1135 * |[0:7] |Data0 |Data Byte 0
<> 144:ef7eb2e8f9f7 1136 * | | |1st data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1137 * |[8:15] |Data1 |Data Byte 1
<> 144:ef7eb2e8f9f7 1138 * | | |2nd data byte of a CAN Data Frame
<> 144:ef7eb2e8f9f7 1139 */
<> 144:ef7eb2e8f9f7 1140 __IO uint32_t DAT_A1;
<> 144:ef7eb2e8f9f7 1141
<> 144:ef7eb2e8f9f7 1142 /**
<> 144:ef7eb2e8f9f7 1143 * CAN_IFn_DAT_A2
<> 144:ef7eb2e8f9f7 1144 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1145 * Offset: 0x40, 0xA0 IFn Data A2 Register (Register Map Note 3)
<> 144:ef7eb2e8f9f7 1146 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1147 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1148 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1149 * |[0:7] |Data2 |Data Byte 2
<> 144:ef7eb2e8f9f7 1150 * | | |3rd data byte of CAN Data Frame
<> 144:ef7eb2e8f9f7 1151 * |[8:15] |Data3 |Data Byte 3
<> 144:ef7eb2e8f9f7 1152 * | | |4th data byte of CAN Data Frame
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154 __IO uint32_t DAT_A2;
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /**
<> 144:ef7eb2e8f9f7 1157 * CAN_IFn_DAT_B1
<> 144:ef7eb2e8f9f7 1158 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1159 * Offset: 0x44, 0xA4 IFn Data B1 Register (Register Map Note 3)
<> 144:ef7eb2e8f9f7 1160 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1161 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1162 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1163 * |[0:7] |Data4 |Data Byte 4
<> 144:ef7eb2e8f9f7 1164 * | | |5th data byte of CAN Data Frame
<> 144:ef7eb2e8f9f7 1165 * |[8:15] |Data5 |Data Byte 5
<> 144:ef7eb2e8f9f7 1166 * | | |6th data byte of CAN Data Frame
<> 144:ef7eb2e8f9f7 1167 */
<> 144:ef7eb2e8f9f7 1168 __IO uint32_t DAT_B1;
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /**
<> 144:ef7eb2e8f9f7 1171 * CAN_IFn_DAT_B2
<> 144:ef7eb2e8f9f7 1172 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1173 * Offset: 0x48, 0xA8 IFn Data B2 Register (Register Map Note 3)
<> 144:ef7eb2e8f9f7 1174 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1175 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1176 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1177 * |[0:7] |Data6 |Data Byte 6
<> 144:ef7eb2e8f9f7 1178 * | | |7th data byte of CAN Data Frame.
<> 144:ef7eb2e8f9f7 1179 * |[8:15] |Data7 |Data Byte 7
<> 144:ef7eb2e8f9f7 1180 * | | |8th data byte of CAN Data Frame.
<> 144:ef7eb2e8f9f7 1181 */
<> 144:ef7eb2e8f9f7 1182 __IO uint32_t DAT_B2;
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 __I uint32_t RESERVE0[13];
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 } CAN_IF_T;
<> 144:ef7eb2e8f9f7 1187
<> 144:ef7eb2e8f9f7 1188 typedef struct {
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /**
<> 144:ef7eb2e8f9f7 1191 * CAN_CON
<> 144:ef7eb2e8f9f7 1192 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1193 * Offset: 0x00 Control Register
<> 144:ef7eb2e8f9f7 1194 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1195 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1196 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1197 * |[0] |Init |Init Initialization
<> 144:ef7eb2e8f9f7 1198 * | | |0 = Normal Operation.
<> 144:ef7eb2e8f9f7 1199 * | | |1 = Initialization is started.
<> 144:ef7eb2e8f9f7 1200 * |[1] |IE |Module Interrupt Enable Control
<> 144:ef7eb2e8f9f7 1201 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 1202 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 1203 * |[2] |SIE |Status Change Interrupt Enable Control
<> 144:ef7eb2e8f9f7 1204 * | | |0 = Disabled - No Status Change Interrupt will be generated.
<> 144:ef7eb2e8f9f7 1205 * | | |1 = Enabled - An interrupt will be generated when a message transfer is successfully completed or a CAN bus error is detected.
<> 144:ef7eb2e8f9f7 1206 * |[3] |EIE |Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 1207 * | | |0 = Disabled - No Error Status Interrupt will be generated.
<> 144:ef7eb2e8f9f7 1208 * | | |1 = Enabled - A change in the bits BOff (CAN_STATUS[7]) or EWarn (CAN_STATUS[6]) in the Status Register will generate an interrupt.
<> 144:ef7eb2e8f9f7 1209 * |[5] |DAR |Automatic Re-Transmission Disable Control
<> 144:ef7eb2e8f9f7 1210 * | | |0 = Automatic Retransmission of disturbed messages enabled.
<> 144:ef7eb2e8f9f7 1211 * | | |1 = Automatic Retransmission disabled.
<> 144:ef7eb2e8f9f7 1212 * |[6] |CCE |Configuration Change Enable Control
<> 144:ef7eb2e8f9f7 1213 * | | |0 = No write access to the Bit Timing Register.
<> 144:ef7eb2e8f9f7 1214 * | | |1 = Write access to the Bit Timing Register (CAN_BTIME) allowed. (while Init bit (CAN_CON[0]) = 1).
<> 144:ef7eb2e8f9f7 1215 * |[7] |Test |Test Mode Enable Control
<> 144:ef7eb2e8f9f7 1216 * | | |0 = Normal Operation.
<> 144:ef7eb2e8f9f7 1217 * | | |1 = Test Mode.
<> 144:ef7eb2e8f9f7 1218 */
<> 144:ef7eb2e8f9f7 1219 __IO uint32_t CON;
<> 144:ef7eb2e8f9f7 1220
<> 144:ef7eb2e8f9f7 1221 /**
<> 144:ef7eb2e8f9f7 1222 * CAN_STATUS
<> 144:ef7eb2e8f9f7 1223 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1224 * Offset: 0x04 Status Register
<> 144:ef7eb2e8f9f7 1225 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1226 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1227 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1228 * |[0:2] |LEC |Last Error Code (Type Of The Last Error To Occur On The CAN Bus)
<> 144:ef7eb2e8f9f7 1229 * | | |The LEC field holds a code, which indicates the type of the last error to occur on the CAN bus.
<> 144:ef7eb2e8f9f7 1230 * | | |This field will be cleared to '0' when a message has been transferred (reception or transmission) without error.
<> 144:ef7eb2e8f9f7 1231 * | | |The unused code '7' may be written by the CPU to check for updates.
<> 144:ef7eb2e8f9f7 1232 * | | |The following table describes the error code.
<> 144:ef7eb2e8f9f7 1233 * |[3] |TxOK |Transmitted A Message Successfully
<> 144:ef7eb2e8f9f7 1234 * | | |0 = Since this bit was reset by the CPU, no message has been successfully transmitted.
<> 144:ef7eb2e8f9f7 1235 * | | |This bit is never reset by the CAN Core.
<> 144:ef7eb2e8f9f7 1236 * | | |1 = Since this bit was last reset by the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted.
<> 144:ef7eb2e8f9f7 1237 * |[4] |RxOK |Received A Message Successfully
<> 144:ef7eb2e8f9f7 1238 * | | |0 = No message has been successfully received since this bit was last reset by the CPU.
<> 144:ef7eb2e8f9f7 1239 * | | |This bit is never reset by the CAN Core.
<> 144:ef7eb2e8f9f7 1240 * | | |1 = A message has been successfully received since this bit was last reset by the CPU (independent of the result of acceptance filtering).
<> 144:ef7eb2e8f9f7 1241 * |[5] |EPass |Error Passive (Read Only)
<> 144:ef7eb2e8f9f7 1242 * | | |0 = The CAN Core is error active.
<> 144:ef7eb2e8f9f7 1243 * | | |1 = The CAN Core is in the error passive state as defined in the CAN Specification.
<> 144:ef7eb2e8f9f7 1244 * |[6] |EWarn |Error Warning Status (Read Only)
<> 144:ef7eb2e8f9f7 1245 * | | |0 = Both error counters are below the error warning limit of 96.
<> 144:ef7eb2e8f9f7 1246 * | | |1 = At least one of the error counters in the EML has reached the error warning limit of 96.
<> 144:ef7eb2e8f9f7 1247 * |[7] |BOff |Bus-Off Status (Read Only)
<> 144:ef7eb2e8f9f7 1248 * | | |0 = The CAN module is not in bus-off state.
<> 144:ef7eb2e8f9f7 1249 * | | |1 = The CAN module is in bus-off state.
<> 144:ef7eb2e8f9f7 1250 */
<> 144:ef7eb2e8f9f7 1251 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 1252
<> 144:ef7eb2e8f9f7 1253 /**
<> 144:ef7eb2e8f9f7 1254 * CAN_ERR
<> 144:ef7eb2e8f9f7 1255 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1256 * Offset: 0x08 Error Counter Register
<> 144:ef7eb2e8f9f7 1257 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1258 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1259 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1260 * |[0:7] |TEC |Transmit Error Counter
<> 144:ef7eb2e8f9f7 1261 * | | |Actual state of the Transmit Error Counter. Values between 0 and 255.
<> 144:ef7eb2e8f9f7 1262 * |[8:14] |REC |Receive Error Counter
<> 144:ef7eb2e8f9f7 1263 * | | |Actual state of the Receive Error Counter. Values between 0 and 127.
<> 144:ef7eb2e8f9f7 1264 * |[15] |RP |Receive Error Passive
<> 144:ef7eb2e8f9f7 1265 * | | |0 = The Receive Error Counter is below the error passive level.
<> 144:ef7eb2e8f9f7 1266 * | | |1 = The Receive Error Counter has reached the error passive level as defined in the CAN Specification.
<> 144:ef7eb2e8f9f7 1267 */
<> 144:ef7eb2e8f9f7 1268 __IO uint32_t ERR;
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /**
<> 144:ef7eb2e8f9f7 1271 * CAN_BTIME
<> 144:ef7eb2e8f9f7 1272 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1273 * Offset: 0x0C Bit Timing Register
<> 144:ef7eb2e8f9f7 1274 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1275 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1276 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1277 * |[0:5] |BRP |Baud Rate Prescaler
<> 144:ef7eb2e8f9f7 1278 * | | |0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta.
<> 144:ef7eb2e8f9f7 1279 * | | |The bit time is built up from a multiple of this quanta.
<> 144:ef7eb2e8f9f7 1280 * | | |Valid values for the Baud Rate Prescaler are [ 0 ... 63 ].
<> 144:ef7eb2e8f9f7 1281 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
<> 144:ef7eb2e8f9f7 1282 * |[6:7] |SJW |(Re)Synchronization Jump Width
<> 144:ef7eb2e8f9f7 1283 * | | |0x0-0x3: Valid programmed values are [0 ... 3].
<> 144:ef7eb2e8f9f7 1284 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
<> 144:ef7eb2e8f9f7 1285 * |[8:11] |TSeg1 |Time Segment Before The Sample Point Minus Sync_Seg
<> 144:ef7eb2e8f9f7 1286 * | | |0x01-0x0F: valid values for TSeg1 are [1 ... 15].
<> 144:ef7eb2e8f9f7 1287 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed is used.
<> 144:ef7eb2e8f9f7 1288 * |[12:14] |TSeg2 |Time Segment After Sample Point
<> 144:ef7eb2e8f9f7 1289 * | | |0x0-0x7: Valid values for TSeg2 are [0 ... 7].
<> 144:ef7eb2e8f9f7 1290 * | | |The actual interpretation by the hardware of this value is such that one more than the value programmed here is used.
<> 144:ef7eb2e8f9f7 1291 */
<> 144:ef7eb2e8f9f7 1292 __IO uint32_t BTIME;
<> 144:ef7eb2e8f9f7 1293
<> 144:ef7eb2e8f9f7 1294 /**
<> 144:ef7eb2e8f9f7 1295 * CAN_IIDR
<> 144:ef7eb2e8f9f7 1296 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1297 * Offset: 0x10 Interrupt Identifier Register
<> 144:ef7eb2e8f9f7 1298 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1299 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1300 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1301 * |[0:15] |IntId |Interrupt Identifier (Indicates The Source Of The Interrupt)
<> 144:ef7eb2e8f9f7 1302 * | | |If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt with the highest priority, disregarding their chronological order.
<> 144:ef7eb2e8f9f7 1303 * | | |An interrupt remains pending until the application software has cleared it.
<> 144:ef7eb2e8f9f7 1304 * | | |If IntId is different from 0x0000 and IE (CAN_IFn_MCON[1]) is set, the IRQ interrupt signal to the EIC is active.
<> 144:ef7eb2e8f9f7 1305 * | | |The interrupt remains active until IntId is back to value 0x0000 (the cause of the interrupt is reset) or until IE is reset.
<> 144:ef7eb2e8f9f7 1306 * | | |The Status Interrupt has the highest priority.
<> 144:ef7eb2e8f9f7 1307 * | | |Among the message interrupts, the Message Object' s interrupt priority decreases with increasing message number.
<> 144:ef7eb2e8f9f7 1308 * | | |A message interrupt is cleared by clearing the Message Object's IntPnd bit (CAN_IFn_MCON[13]).
<> 144:ef7eb2e8f9f7 1309 * | | |The Status Interrupt is cleared by reading the Status Register.
<> 144:ef7eb2e8f9f7 1310 */
<> 144:ef7eb2e8f9f7 1311 __IO uint32_t IIDR;
<> 144:ef7eb2e8f9f7 1312
<> 144:ef7eb2e8f9f7 1313 /**
<> 144:ef7eb2e8f9f7 1314 * CAN_TEST
<> 144:ef7eb2e8f9f7 1315 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1316 * Offset: 0x14 Test Register (Register Map Note 1)
<> 144:ef7eb2e8f9f7 1317 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1318 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1319 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1320 * |[0:1] |Res |Reserved
<> 144:ef7eb2e8f9f7 1321 * | | |There are reserved bits.
<> 144:ef7eb2e8f9f7 1322 * | | |These bits are always read as '0' and must always be written with '0'.
<> 144:ef7eb2e8f9f7 1323 * |[2] |Basic |Basic Mode
<> 144:ef7eb2e8f9f7 1324 * | | |0 = Basic Mode disabled.
<> 144:ef7eb2e8f9f7 1325 * | | |1= IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer.
<> 144:ef7eb2e8f9f7 1326 * |[3] |Silent |Silent Mode
<> 144:ef7eb2e8f9f7 1327 * | | |0 = Normal operation.
<> 144:ef7eb2e8f9f7 1328 * | | |1 = The module is in Silent Mode.
<> 144:ef7eb2e8f9f7 1329 * |[4] |LBack |Loop Back Mode Enable Control
<> 144:ef7eb2e8f9f7 1330 * | | |0 = Loop Back Mode is disabled.
<> 144:ef7eb2e8f9f7 1331 * | | |1 = Loop Back Mode is enabled.
<> 144:ef7eb2e8f9f7 1332 * |[5:6] |Tx10 |Tx[1:0]: Control Of CAN_TX Pin
<> 144:ef7eb2e8f9f7 1333 * | | |00 = Reset value, CAN_TX pin is controlled by the CAN Core.
<> 144:ef7eb2e8f9f7 1334 * | | |01 = Sample Point can be monitored at CAN_TX pin.
<> 144:ef7eb2e8f9f7 1335 * | | |10 = CAN_TX pin drives a dominant ('0') value.
<> 144:ef7eb2e8f9f7 1336 * | | |11 = CAN_TX pin drives a recessive ('1') value.
<> 144:ef7eb2e8f9f7 1337 * |[7] |Rx |Monitors The Actual Value Of CAN_RX Pin (Read Only)
<> 144:ef7eb2e8f9f7 1338 * | | |0 = The CAN bus is dominant (CAN_RX = '0').
<> 144:ef7eb2e8f9f7 1339 * | | |1 = The CAN bus is recessive (CAN_RX = '1').
<> 144:ef7eb2e8f9f7 1340 */
<> 144:ef7eb2e8f9f7 1341 __IO uint32_t TEST;
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 /**
<> 144:ef7eb2e8f9f7 1344 * CAN_BRPE
<> 144:ef7eb2e8f9f7 1345 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1346 * Offset: 0x18 Baud Rate Prescaler Extension Register
<> 144:ef7eb2e8f9f7 1347 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1348 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1349 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1350 * |[0:3] |BRPE |BRPE: Baud Rate Prescaler Extension
<> 144:ef7eb2e8f9f7 1351 * | | |0x00-0x0F: By programming BRPE, the Baud Rate Prescaler can be extended to values up to 1023.
<> 144:ef7eb2e8f9f7 1352 * | | |The actual interpretation by the hardware is that one more than the value programmed by BRPE (MSBs) and BTIME (LSBs) is used.
<> 144:ef7eb2e8f9f7 1353 */
<> 144:ef7eb2e8f9f7 1354 __IO uint32_t BRPE;
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 __I uint32_t RESERVE0[1];
<> 144:ef7eb2e8f9f7 1357
<> 144:ef7eb2e8f9f7 1358 __IO CAN_IF_T IF[2];
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 __I uint32_t RESERVE1[8];
<> 144:ef7eb2e8f9f7 1361
<> 144:ef7eb2e8f9f7 1362 /**
<> 144:ef7eb2e8f9f7 1363 * CAN_TXREQ1
<> 144:ef7eb2e8f9f7 1364 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1365 * Offset: 0x100 Transmission Request Register 1
<> 144:ef7eb2e8f9f7 1366 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1367 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1368 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1369 * |[0:15] |TxRqst161 |Transmission Request Bits 16-1 (Of All Message Objects)
<> 144:ef7eb2e8f9f7 1370 * | | |0 = This Message Object is not waiting for transmission.
<> 144:ef7eb2e8f9f7 1371 * | | |1 = The transmission of this Message Object is requested and is not yet done.
<> 144:ef7eb2e8f9f7 1372 * | | |These bits are read only.
<> 144:ef7eb2e8f9f7 1373 */
<> 144:ef7eb2e8f9f7 1374 __IO uint32_t TXREQ1;
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 /**
<> 144:ef7eb2e8f9f7 1377 * CAN_TXREQ2
<> 144:ef7eb2e8f9f7 1378 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1379 * Offset: 0x104 Transmission Request Register 2
<> 144:ef7eb2e8f9f7 1380 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1381 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1382 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1383 * |[0:15] |TxRqst3217|Transmission Request Bits 32-17 (Of All Message Objects)
<> 144:ef7eb2e8f9f7 1384 * | | |0 = This Message Object is not waiting for transmission.
<> 144:ef7eb2e8f9f7 1385 * | | |1 = The transmission of this Message Object is requested and is not yet done.
<> 144:ef7eb2e8f9f7 1386 * | | |These bits are read only.
<> 144:ef7eb2e8f9f7 1387 */
<> 144:ef7eb2e8f9f7 1388 __IO uint32_t TXREQ2;
<> 144:ef7eb2e8f9f7 1389
<> 144:ef7eb2e8f9f7 1390 __I uint32_t RESERVE2[6];
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 /**
<> 144:ef7eb2e8f9f7 1393 * CAN_NDAT1
<> 144:ef7eb2e8f9f7 1394 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1395 * Offset: 0x120 New Data Register 1
<> 144:ef7eb2e8f9f7 1396 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1397 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1398 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1399 * |[0:15] |NewData161|New Data Bits 16-1 (Of All Message Objects)
<> 144:ef7eb2e8f9f7 1400 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
<> 144:ef7eb2e8f9f7 1401 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
<> 144:ef7eb2e8f9f7 1402 */
<> 144:ef7eb2e8f9f7 1403 __IO uint32_t NDAT1;
<> 144:ef7eb2e8f9f7 1404
<> 144:ef7eb2e8f9f7 1405 /**
<> 144:ef7eb2e8f9f7 1406 * CAN_NDAT2
<> 144:ef7eb2e8f9f7 1407 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1408 * Offset: 0x124 New Data Register 2
<> 144:ef7eb2e8f9f7 1409 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1410 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1411 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1412 * |[0:15] |NewData3217|New Data Bits 32-17 (Of All Message Objects)
<> 144:ef7eb2e8f9f7 1413 * | | |0 = No new data has been written into the data portion of this Message Object by the Message Handler since the last time this flag was cleared by the application software.
<> 144:ef7eb2e8f9f7 1414 * | | |1 = The Message Handler or the application software has written new data into the data portion of this Message Object.
<> 144:ef7eb2e8f9f7 1415 */
<> 144:ef7eb2e8f9f7 1416 __IO uint32_t NDAT2;
<> 144:ef7eb2e8f9f7 1417
<> 144:ef7eb2e8f9f7 1418 __I uint32_t RESERVE3[6];
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 /**
<> 144:ef7eb2e8f9f7 1421 * CAN_IPND1
<> 144:ef7eb2e8f9f7 1422 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1423 * Offset: 0x140 Interrupt Pending Register 1
<> 144:ef7eb2e8f9f7 1424 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1425 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1426 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1427 * |[0:15] |IntPnd161 |Interrupt Pending Bits 16-1 (Of All Message Objects)
<> 144:ef7eb2e8f9f7 1428 * | | |0 = This message object is not the source of an interrupt.
<> 144:ef7eb2e8f9f7 1429 * | | |1 = This message object is the source of an interrupt.
<> 144:ef7eb2e8f9f7 1430 */
<> 144:ef7eb2e8f9f7 1431 __IO uint32_t IPND1;
<> 144:ef7eb2e8f9f7 1432
<> 144:ef7eb2e8f9f7 1433 /**
<> 144:ef7eb2e8f9f7 1434 * CAN_IPND2
<> 144:ef7eb2e8f9f7 1435 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1436 * Offset: 0x144 Interrupt Pending Register 2
<> 144:ef7eb2e8f9f7 1437 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1438 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1439 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1440 * |[0:15] |IntPnd3217|Interrupt Pending Bits 32-17(Of All Message Objects)
<> 144:ef7eb2e8f9f7 1441 * | | |0 = This message object is not the source of an interrupt.
<> 144:ef7eb2e8f9f7 1442 * | | |1 = This message object is the source of an interrupt.
<> 144:ef7eb2e8f9f7 1443 */
<> 144:ef7eb2e8f9f7 1444 __IO uint32_t IPND2;
<> 144:ef7eb2e8f9f7 1445
<> 144:ef7eb2e8f9f7 1446 __I uint32_t RESERVE4[6];
<> 144:ef7eb2e8f9f7 1447
<> 144:ef7eb2e8f9f7 1448 /**
<> 144:ef7eb2e8f9f7 1449 * CAN_MVLD1
<> 144:ef7eb2e8f9f7 1450 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1451 * Offset: 0x160 Message Valid Register 1
<> 144:ef7eb2e8f9f7 1452 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1453 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1454 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1455 * |[0:15] |MsgVal161 |Message Valid Bits 16-1 (Of All Message Objects) (Read Only)
<> 144:ef7eb2e8f9f7 1456 * | | |0 = This Message Object is ignored by the Message Handler.
<> 144:ef7eb2e8f9f7 1457 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
<> 144:ef7eb2e8f9f7 1458 * | | |Ex.
<> 144:ef7eb2e8f9f7 1459 * | | |CAN_MVLD1[0] means Message object No.1 is valid or not.
<> 144:ef7eb2e8f9f7 1460 * | | |If CAN_MVLD1[0] is set, message object No.1 is configured.
<> 144:ef7eb2e8f9f7 1461 */
<> 144:ef7eb2e8f9f7 1462 __IO uint32_t MVLD1;
<> 144:ef7eb2e8f9f7 1463
<> 144:ef7eb2e8f9f7 1464 /**
<> 144:ef7eb2e8f9f7 1465 * CAN_MVLD2
<> 144:ef7eb2e8f9f7 1466 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1467 * Offset: 0x164 Message Valid Register 2
<> 144:ef7eb2e8f9f7 1468 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1469 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1470 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1471 * |[0:15] |MsgVal3217|Message Valid Bits 32-17 (Of All Message Objects) (Read Only)
<> 144:ef7eb2e8f9f7 1472 * | | |0 = This Message Object is ignored by the Message Handler.
<> 144:ef7eb2e8f9f7 1473 * | | |1 = This Message Object is configured and should be considered by the Message Handler.
<> 144:ef7eb2e8f9f7 1474 * | | |Ex.CAN_MVLD2[15] means Message object No.32 is valid or not.
<> 144:ef7eb2e8f9f7 1475 * | | |If CAN_MVLD2[15] is set, message object No.32 is configured.
<> 144:ef7eb2e8f9f7 1476 */
<> 144:ef7eb2e8f9f7 1477 __IO uint32_t MVLD2;
<> 144:ef7eb2e8f9f7 1478
<> 144:ef7eb2e8f9f7 1479 /**
<> 144:ef7eb2e8f9f7 1480 * CAN_WU_EN
<> 144:ef7eb2e8f9f7 1481 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1482 * Offset: 0x168 Wake-up Enable Register
<> 144:ef7eb2e8f9f7 1483 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1484 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1485 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1486 * |[0] |WAKUP_EN |Wake-Up Enable Control
<> 144:ef7eb2e8f9f7 1487 * | | |0 = The wake-up function Disabled.
<> 144:ef7eb2e8f9f7 1488 * | | |1 = The wake-up function Enabled.
<> 144:ef7eb2e8f9f7 1489 * | | |Note: User can wake-up system when there is a falling edge in the CAN_Rx pin.
<> 144:ef7eb2e8f9f7 1490 */
<> 144:ef7eb2e8f9f7 1491 __IO uint32_t WU_EN;
<> 144:ef7eb2e8f9f7 1492
<> 144:ef7eb2e8f9f7 1493 /**
<> 144:ef7eb2e8f9f7 1494 * CAN_WU_STATUS
<> 144:ef7eb2e8f9f7 1495 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1496 * Offset: 0x16C Wake-up Status Register
<> 144:ef7eb2e8f9f7 1497 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1498 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1499 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1500 * |[0] |WAKUP_STS |Wake-Up Status
<> 144:ef7eb2e8f9f7 1501 * | | |0 = No wake-up event occurred.
<> 144:ef7eb2e8f9f7 1502 * | | |1 = Wake-up event occurred.
<> 144:ef7eb2e8f9f7 1503 * | | |Note: This bit can be cleared by writing '0'.
<> 144:ef7eb2e8f9f7 1504 */
<> 144:ef7eb2e8f9f7 1505 __IO uint32_t WU_STATUS;
<> 144:ef7eb2e8f9f7 1506 } CAN_T;
<> 144:ef7eb2e8f9f7 1507
<> 144:ef7eb2e8f9f7 1508 /**
<> 144:ef7eb2e8f9f7 1509 @addtogroup CAN_CONST CAN Bit Field Definition
<> 144:ef7eb2e8f9f7 1510 Constant Definitions for CAN Controller
<> 144:ef7eb2e8f9f7 1511 @{ */
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 #define CAN_CON_TEST_Pos 7 /*!< CAN CON: TEST Position */
<> 144:ef7eb2e8f9f7 1514 #define CAN_CON_TEST_Msk (1ul << CAN_CON_TEST_Pos) /*!< CAN CON: TEST Mask */
<> 144:ef7eb2e8f9f7 1515
<> 144:ef7eb2e8f9f7 1516 #define CAN_CON_CCE_Pos 6 /*!< CAN CON: CCE Position */
<> 144:ef7eb2e8f9f7 1517 #define CAN_CON_CCE_Msk (1ul << CAN_CON_CCE_Pos) /*!< CAN CON: CCE Mask */
<> 144:ef7eb2e8f9f7 1518
<> 144:ef7eb2e8f9f7 1519 #define CAN_CON_DAR_Pos 5 /*!< CAN CON: DAR Position */
<> 144:ef7eb2e8f9f7 1520 #define CAN_CON_DAR_Msk (1ul << CAN_CON_DAR_Pos) /*!< CAN CON: DAR Mask */
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 #define CAN_CON_EIE_Pos 3 /*!< CAN CON: EIE Position */
<> 144:ef7eb2e8f9f7 1523 #define CAN_CON_EIE_Msk (1ul << CAN_CON_EIE_Pos) /*!< CAN CON: EIE Mask */
<> 144:ef7eb2e8f9f7 1524
<> 144:ef7eb2e8f9f7 1525 #define CAN_CON_SIE_Pos 2 /*!< CAN CON: SIE Position */
<> 144:ef7eb2e8f9f7 1526 #define CAN_CON_SIE_Msk (1ul << CAN_CON_SIE_Pos) /*!< CAN CON: SIE Mask */
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 #define CAN_CON_IE_Pos 1 /*!< CAN CON: IE Position */
<> 144:ef7eb2e8f9f7 1529 #define CAN_CON_IE_Msk (1ul << CAN_CON_IE_Pos) /*!< CAN CON: IE Mask */
<> 144:ef7eb2e8f9f7 1530
<> 144:ef7eb2e8f9f7 1531 #define CAN_CON_INIT_Pos 0 /*!< CAN CON: INIT Position */
<> 144:ef7eb2e8f9f7 1532 #define CAN_CON_INIT_Msk (1ul << CAN_CON_INIT_Pos) /*!< CAN CON: INIT Mask */
<> 144:ef7eb2e8f9f7 1533
<> 144:ef7eb2e8f9f7 1534 #define CAN_STATUS_BOFF_Pos 7 /*!< CAN STATUS: BOFF Position */
<> 144:ef7eb2e8f9f7 1535 #define CAN_STATUS_BOFF_Msk (1ul << CAN_STATUS_BOFF_Pos) /*!< CAN STATUS: BOFF Mask */
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 #define CAN_STATUS_EWARN_Pos 6 /*!< CAN STATUS: EWARN Position */
<> 144:ef7eb2e8f9f7 1538 #define CAN_STATUS_EWARN_Msk (1ul << CAN_STATUS_EWARN_Pos) /*!< CAN STATUS: EWARN Mask */
<> 144:ef7eb2e8f9f7 1539
<> 144:ef7eb2e8f9f7 1540 #define CAN_STATUS_EPASS_Pos 5 /*!< CAN STATUS: EPASS Position */
<> 144:ef7eb2e8f9f7 1541 #define CAN_STATUS_EPASS_Msk (1ul << CAN_STATUS_EPASS_Pos) /*!< CAN STATUS: EPASS Mask */
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 #define CAN_STATUS_RXOK_Pos 4 /*!< CAN STATUS: RXOK Position */
<> 144:ef7eb2e8f9f7 1544 #define CAN_STATUS_RXOK_Msk (1ul << CAN_STATUS_RXOK_Pos) /*!< CAN STATUS: RXOK Mask */
<> 144:ef7eb2e8f9f7 1545
<> 144:ef7eb2e8f9f7 1546 #define CAN_STATUS_TXOK_Pos 3 /*!< CAN STATUS: TXOK Position */
<> 144:ef7eb2e8f9f7 1547 #define CAN_STATUS_TXOK_Msk (1ul << CAN_STATUS_TXOK_Pos) /*!< CAN STATUS: TXOK Mask */
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 #define CAN_STATUS_LEC_Pos 0 /*!< CAN STATUS: LEC Position */
<> 144:ef7eb2e8f9f7 1550 #define CAN_STATUS_LEC_Msk (0x3ul << CAN_STATUS_LEC_Pos) /*!< CAN STATUS: LEC Mask */
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 #define CAN_ERR_RP_Pos 15 /*!< CAN ERR: RP Position */
<> 144:ef7eb2e8f9f7 1553 #define CAN_ERR_RP_Msk (1ul << CAN_ERR_RP_Pos) /*!< CAN ERR: RP Mask */
<> 144:ef7eb2e8f9f7 1554
<> 144:ef7eb2e8f9f7 1555 #define CAN_ERR_REC_Pos 8 /*!< CAN ERR: REC Position */
<> 144:ef7eb2e8f9f7 1556 #define CAN_ERR_REC_Msk (0x7Ful << CAN_ERR_REC_Pos) /*!< CAN ERR: REC Mask */
<> 144:ef7eb2e8f9f7 1557
<> 144:ef7eb2e8f9f7 1558 #define CAN_ERR_TEC_Pos 0 /*!< CAN ERR: TEC Position */
<> 144:ef7eb2e8f9f7 1559 #define CAN_ERR_TEC_Msk (0xFFul << CAN_ERR_TEC_Pos) /*!< CAN ERR: TEC Mask */
<> 144:ef7eb2e8f9f7 1560
<> 144:ef7eb2e8f9f7 1561 #define CAN_BTIME_TSEG2_Pos 12 /*!< CAN BTIME: TSEG2 Position */
<> 144:ef7eb2e8f9f7 1562 #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) /*!< CAN BTIME: TSEG2 Mask */
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 #define CAN_BTIME_TSEG1_Pos 8 /*!< CAN BTIME: TSEG1 Position */
<> 144:ef7eb2e8f9f7 1565 #define CAN_BTIME_TSEG1_Msk (0xFul << CAN_BTIME_TSEG1_Pos) /*!< CAN BTIME: TSEG1 Mask */
<> 144:ef7eb2e8f9f7 1566
<> 144:ef7eb2e8f9f7 1567 #define CAN_BTIME_SJW_Pos 6 /*!< CAN BTIME: SJW Position */
<> 144:ef7eb2e8f9f7 1568 #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) /*!< CAN BTIME: SJW Mask */
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 #define CAN_BTIME_BRP_Pos 0 /*!< CAN BTIME: BRP Position */
<> 144:ef7eb2e8f9f7 1571 #define CAN_BTIME_BRP_Msk (0x3Ful << CAN_BTIME_BRP_Pos) /*!< CAN BTIME: BRP Mask */
<> 144:ef7eb2e8f9f7 1572
<> 144:ef7eb2e8f9f7 1573 #define CAN_IIDR_INTID_Pos 0 /*!< CAN IIDR: INTID Position */
<> 144:ef7eb2e8f9f7 1574 #define CAN_IIDR_INTID_Msk (0xFFFFul << CAN_IIDR_INTID_Pos) /*!< CAN IIDR: INTID Mask */
<> 144:ef7eb2e8f9f7 1575
<> 144:ef7eb2e8f9f7 1576 #define CAN_TEST_RX_Pos 7 /*!< CAN TEST: RX Position */
<> 144:ef7eb2e8f9f7 1577 #define CAN_TEST_RX_Msk (1ul << CAN_TEST_RX_Pos) /*!< CAN TEST: RX Mask */
<> 144:ef7eb2e8f9f7 1578
<> 144:ef7eb2e8f9f7 1579 #define CAN_TEST_TX_Pos 5 /*!< CAN TEST: TX Position */
<> 144:ef7eb2e8f9f7 1580 #define CAN_TEST_TX_Msk (0x3ul << CAN_TEST_TX_Pos) /*!< CAN TEST: TX Mask */
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 #define CAN_TEST_LBACK_Pos 4 /*!< CAN TEST: LBACK Position */
<> 144:ef7eb2e8f9f7 1583 #define CAN_TEST_LBACK_Msk (1ul << CAN_TEST_LBACK_Pos) /*!< CAN TEST: LBACK Mask */
<> 144:ef7eb2e8f9f7 1584
<> 144:ef7eb2e8f9f7 1585 #define CAN_TEST_SILENT_Pos 3 /*!< CAN TEST: Silent Position */
<> 144:ef7eb2e8f9f7 1586 #define CAN_TEST_SILENT_Msk (1ul << CAN_TEST_SILENT_Pos) /*!< CAN TEST: Silent Mask */
<> 144:ef7eb2e8f9f7 1587
<> 144:ef7eb2e8f9f7 1588 #define CAN_TEST_BASIC_Pos 2 /*!< CAN TEST: Basic Position */
<> 144:ef7eb2e8f9f7 1589 #define CAN_TEST_BASIC_Msk (1ul << CAN_TEST_BASIC_Pos) /*!< CAN TEST: Basic Mask */
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 #define CAN_BRPE_BRPE_Pos 0 /*!< CAN BRPE: BRPE Position */
<> 144:ef7eb2e8f9f7 1592 #define CAN_BRPE_BRPE_Msk (0xFul << CAN_BRPE_BRPE_Pos) /*!< CAN BRPE: BRPE Mask */
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 #define CAN_IF_CREQ_BUSY_Pos 15 /*!< CAN IFnCREQ: BUSY Position */
<> 144:ef7eb2e8f9f7 1595 #define CAN_IF_CREQ_BUSY_Msk (1ul << CAN_IF_CREQ_BUSY_Pos) /*!< CAN IFnCREQ: BUSY Mask */
<> 144:ef7eb2e8f9f7 1596
<> 144:ef7eb2e8f9f7 1597 #define CAN_IF_CREQ_MSGNUM_Pos 0 /*!< CAN IFnCREQ: MSGNUM Position */
<> 144:ef7eb2e8f9f7 1598 #define CAN_IF_CREQ_MSGNUM_Msk (0x3Ful << CAN_IF_CREQ_MSGNUM_Pos) /*!< CAN IFnCREQ: MSGNUM Mask */
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 #define CAN_IF_CMASK_WRRD_Pos 7 /*!< CAN IFnCMASK: WRRD Position */
<> 144:ef7eb2e8f9f7 1601 #define CAN_IF_CMASK_WRRD_Msk (1ul << CAN_IF_CMASK_WRRD_Pos) /*!< CAN IFnCMASK: WRRD Mask */
<> 144:ef7eb2e8f9f7 1602
<> 144:ef7eb2e8f9f7 1603 #define CAN_IF_CMASK_MASK_Pos 6 /*!< CAN IFnCMASK: MASK Position */
<> 144:ef7eb2e8f9f7 1604 #define CAN_IF_CMASK_MASK_Msk (1ul << CAN_IF_CMASK_MASK_Pos) /*!< CAN IFnCMASK: MASK Mask */
<> 144:ef7eb2e8f9f7 1605
<> 144:ef7eb2e8f9f7 1606 #define CAN_IF_CMASK_ARB_Pos 5 /*!< CAN IFnCMASK: ARB Position */
<> 144:ef7eb2e8f9f7 1607 #define CAN_IF_CMASK_ARB_Msk (1ul << CAN_IF_CMASK_ARB_Pos) /*!< CAN IFnCMASK: ARB Mask */
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 #define CAN_IF_CMASK_CONTROL_Pos 4 /*!< CAN IFnCMASK: CONTROL Position */
<> 144:ef7eb2e8f9f7 1610 #define CAN_IF_CMASK_CONTROL_Msk (1ul << CAN_IF_CMASK_CONTROL_Pos) /*!< CAN IFnCMASK: CONTROL Mask */
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 #define CAN_IF_CMASK_CLRINTPND_Pos 3 /*!< CAN IFnCMASK: CLRINTPND Position */
<> 144:ef7eb2e8f9f7 1613 #define CAN_IF_CMASK_CLRINTPND_Msk (1ul << CAN_IF_CMASK_CLRINTPND_Pos) /*!< CAN IFnCMASK: CLRINTPND Mask */
<> 144:ef7eb2e8f9f7 1614
<> 144:ef7eb2e8f9f7 1615 #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos 2 /*!< CAN IFnCMASK: TXRQSTNEWDAT Position */
<> 144:ef7eb2e8f9f7 1616 #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) /*!< CAN IFnCMASK: TXRQSTNEWDAT Mask */
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 #define CAN_IF_CMASK_DATAA_Pos 1 /*!< CAN IFnCMASK: DATAA Position */
<> 144:ef7eb2e8f9f7 1619 #define CAN_IF_CMASK_DATAA_Msk (1ul << CAN_IF_CMASK_DATAA_Pos) /*!< CAN IFnCMASK: DATAA Mask */
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 #define CAN_IF_CMASK_DATAB_Pos 0 /*!< CAN IFnCMASK: DATAB Position */
<> 144:ef7eb2e8f9f7 1622 #define CAN_IF_CMASK_DATAB_Msk (1ul << CAN_IF_CMASK_DATAB_Pos) /*!< CAN IFnCMASK: DATAB Mask */
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 #define CAN_IF_MASK1_MSK_Pos 0 /*!< CAN IFnMASK1: MSK Position */
<> 144:ef7eb2e8f9f7 1625 #define CAN_IF_MASK1_MSK_Msk (0xFFul << CAN_IF_MASK1_MSK_Pos) /*!< CAN IFnMASK1: MSK Mask */
<> 144:ef7eb2e8f9f7 1626
<> 144:ef7eb2e8f9f7 1627 #define CAN_IF_MASK2_MXTD_Pos 15 /*!< CAN IFnMASK2: MXTD Position */
<> 144:ef7eb2e8f9f7 1628 #define CAN_IF_MASK2_MXTD_Msk (1ul << CAN_IF_MASK2_MXTD_Pos) /*!< CAN IFnMASK2: MXTD Mask */
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 #define CAN_IF_MASK2_MDIR_Pos 14 /*!< CAN IFnMASK2: MDIR Position */
<> 144:ef7eb2e8f9f7 1631 #define CAN_IF_MASK2_MDIR_Msk (1ul << CAN_IF_MASK2_MDIR_Pos) /*!< CAN IFnMASK2: MDIR Mask */
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 #define CAN_IF_MASK2_MSK_Pos 0 /*!< CAN IFnMASK2: MSK Position */
<> 144:ef7eb2e8f9f7 1634 #define CAN_IF_MASK2_MSK_Msk (0x1FFul << CAN_IF_MASK2_MSK_Pos) /*!< CAN IFnMASK2: MSK Mask */
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 #define CAN_IF_ARB1_ID_Pos 0 /*!< CAN IFnARB1: ID Position */
<> 144:ef7eb2e8f9f7 1637 #define CAN_IF_ARB1_ID_Msk (0xFFFFul << CAN_IF_ARB1_ID_Pos) /*!< CAN IFnARB1: ID Mask */
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 #define CAN_IF_ARB2_MSGVAL_Pos 15 /*!< CAN IFnARB2: MSGVAL Position */
<> 144:ef7eb2e8f9f7 1640 #define CAN_IF_ARB2_MSGVAL_Msk (1ul << CAN_IF_ARB2_MSGVAL_Pos) /*!< CAN IFnARB2: MSGVAL Mask */
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 #define CAN_IF_ARB2_XTD_Pos 14 /*!< CAN IFnARB2: XTD Position */
<> 144:ef7eb2e8f9f7 1643 #define CAN_IF_ARB2_XTD_Msk (1ul << CAN_IF_ARB2_XTD_Pos) /*!< CAN IFnARB2: XTD Mask */
<> 144:ef7eb2e8f9f7 1644
<> 144:ef7eb2e8f9f7 1645 #define CAN_IF_ARB2_DIR_Pos 13 /*!< CAN IFnARB2: DIR Position */
<> 144:ef7eb2e8f9f7 1646 #define CAN_IF_ARB2_DIR_Msk (1ul << CAN_IF_ARB2_DIR_Pos) /*!< CAN IFnARB2: DIR Mask */
<> 144:ef7eb2e8f9f7 1647
<> 144:ef7eb2e8f9f7 1648 #define CAN_IF_ARB2_ID_Pos 0 /*!< CAN IFnARB2: ID Position */
<> 144:ef7eb2e8f9f7 1649 #define CAN_IF_ARB2_ID_Msk (0x1FFFul << CAN_IF_ARB2_ID_Pos) /*!< CAN IFnARB2: ID Mask */
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 #define CAN_IF_MCON_NEWDAT_Pos 15 /*!< CAN IFnMCON: NEWDAT Position */
<> 144:ef7eb2e8f9f7 1652 #define CAN_IF_MCON_NEWDAT_Msk (1ul << CAN_IF_MCON_NEWDAT_Pos) /*!< CAN IFnMCON: NEWDAT Mask */
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 #define CAN_IF_MCON_MSGLST_Pos 14 /*!< CAN IFnMCON: MSGLST Position */
<> 144:ef7eb2e8f9f7 1655 #define CAN_IF_MCON_MSGLST_Msk (1ul << CAN_IF_MCON_MSGLST_Pos) /*!< CAN IFnMCON: MSGLST Mask */
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 #define CAN_IF_MCON_INTPND_Pos 13 /*!< CAN IFnMCON: INTPND Position */
<> 144:ef7eb2e8f9f7 1658 #define CAN_IF_MCON_INTPND_Msk (1ul << CAN_IF_MCON_INTPND_Pos) /*!< CAN IFnMCON: INTPND Mask */
<> 144:ef7eb2e8f9f7 1659
<> 144:ef7eb2e8f9f7 1660 #define CAN_IF_MCON_UMASK_Pos 12 /*!< CAN IFnMCON: UMASK Position */
<> 144:ef7eb2e8f9f7 1661 #define CAN_IF_MCON_UMASK_Msk (1ul << CAN_IF_MCON_UMASK_Pos) /*!< CAN IFnMCON: UMASK Mask */
<> 144:ef7eb2e8f9f7 1662
<> 144:ef7eb2e8f9f7 1663 #define CAN_IF_MCON_TXIE_Pos 11 /*!< CAN IFnMCON: TXIE Position */
<> 144:ef7eb2e8f9f7 1664 #define CAN_IF_MCON_TXIE_Msk (1ul << CAN_IF_MCON_TXIE_Pos) /*!< CAN IFnMCON: TXIE Mask */
<> 144:ef7eb2e8f9f7 1665
<> 144:ef7eb2e8f9f7 1666 #define CAN_IF_MCON_RXIE_Pos 10 /*!< CAN IFnMCON: RXIE Position */
<> 144:ef7eb2e8f9f7 1667 #define CAN_IF_MCON_RXIE_Msk (1ul << CAN_IF_MCON_RXIE_Pos) /*!< CAN IFnMCON: RXIE Mask */
<> 144:ef7eb2e8f9f7 1668
<> 144:ef7eb2e8f9f7 1669 #define CAN_IF_MCON_RMTEN_Pos 9 /*!< CAN IFnMCON: RMTEN Position */
<> 144:ef7eb2e8f9f7 1670 #define CAN_IF_MCON_RMTEN_Msk (1ul << CAN_IF_MCON_RMTEN_Pos) /*!< CAN IFnMCON: RMTEN Mask */
<> 144:ef7eb2e8f9f7 1671
<> 144:ef7eb2e8f9f7 1672 #define CAN_IF_MCON_TXRQST_Pos 8 /*!< CAN IFnMCON: TXRQST Position */
<> 144:ef7eb2e8f9f7 1673 #define CAN_IF_MCON_TXRQST_Msk (1ul << CAN_IF_MCON_TXRQST_Pos) /*!< CAN IFnMCON: TXRQST Mask */
<> 144:ef7eb2e8f9f7 1674
<> 144:ef7eb2e8f9f7 1675 #define CAN_IF_MCON_EOB_Pos 7 /*!< CAN IFnMCON: EOB Position */
<> 144:ef7eb2e8f9f7 1676 #define CAN_IF_MCON_EOB_Msk (1ul << CAN_IF_MCON_EOB_Pos) /*!< CAN IFnMCON: EOB Mask */
<> 144:ef7eb2e8f9f7 1677
<> 144:ef7eb2e8f9f7 1678 #define CAN_IF_MCON_DLC_Pos 0 /*!< CAN IFnMCON: DLC Position */
<> 144:ef7eb2e8f9f7 1679 #define CAN_IF_MCON_DLC_Msk (0xFul << CAN_IF_MCON_DLC_Pos) /*!< CAN IFnMCON: DLC Mask */
<> 144:ef7eb2e8f9f7 1680
<> 144:ef7eb2e8f9f7 1681 #define CAN_IF_DAT_A1_DATA1_Pos 8 /*!< CAN IFnDATAA1: DATA1 Position */
<> 144:ef7eb2e8f9f7 1682 #define CAN_IF_DAT_A1_DATA1_Msk (0xFFul << CAN_IF_DAT_A1_DATA1_Pos) /*!< CAN IFnDATAA1: DATA1 Mask */
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 #define CAN_IF_DAT_A1_DATA0_Pos 0 /*!< CAN IFnDATAA1: DATA0 Position */
<> 144:ef7eb2e8f9f7 1685 #define CAN_IF_DAT_A1_DATA0_Msk (0xFFul << CAN_IF_DAT_A1_DATA0_Pos) /*!< CAN IFnDATAA1: DATA0 Mask */
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 #define CAN_IF_DAT_A2_DATA3_Pos 8 /*!< CAN IFnDATAA1: DATA3 Position */
<> 144:ef7eb2e8f9f7 1688 #define CAN_IF_DAT_A2_DATA3_Msk (0xFFul << CAN_IF_DAT_A2_DATA3_Pos) /*!< CAN IFnDATAA1: DATA3 Mask */
<> 144:ef7eb2e8f9f7 1689
<> 144:ef7eb2e8f9f7 1690 #define CAN_IF_DAT_A2_DATA2_Pos 0 /*!< CAN IFnDATAA1: DATA2 Position */
<> 144:ef7eb2e8f9f7 1691 #define CAN_IF_DAT_A2_DATA2_Msk (0xFFul << CAN_IF_DAT_A2_DATA2_Pos) /*!< CAN IFnDATAA1: DATA2 Mask */
<> 144:ef7eb2e8f9f7 1692
<> 144:ef7eb2e8f9f7 1693 #define CAN_IF_DAT_B1_DATA5_Pos 8 /*!< CAN IFnDATAB1: DATA5 Position */
<> 144:ef7eb2e8f9f7 1694 #define CAN_IF_DAT_B1_DATA5_Msk (0xFFul << CAN_IF_DAT_B1_DATA5_Pos) /*!< CAN IFnDATAB1: DATA5 Mask */
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 #define CAN_IF_DAT_B1_DATA4_Pos 0 /*!< CAN IFnDATAB1: DATA4 Position */
<> 144:ef7eb2e8f9f7 1697 #define CAN_IF_DAT_B1_DATA4_Msk (0xFFul << CAN_IF_DAT_B1_DATA4_Pos) /*!< CAN IFnDATAB1: DATA4 Mask */
<> 144:ef7eb2e8f9f7 1698
<> 144:ef7eb2e8f9f7 1699 #define CAN_IF_DAT_B2_DATA7_Pos 8 /*!< CAN IFnDATAB2: DATA7 Position */
<> 144:ef7eb2e8f9f7 1700 #define CAN_IF_DAT_B2_DATA7_Msk (0xFFul << CAN_IF_DAT_B2_DATA7_Pos) /*!< CAN IFnDATAB2: DATA7 Mask */
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 #define CAN_IF_DAT_B2_DATA6_Pos 0 /*!< CAN IFnDATAB2: DATA6 Position */
<> 144:ef7eb2e8f9f7 1703 #define CAN_IF_DAT_B2_DATA6_Msk (0xFFul << CAN_IF_DAT_B2_DATA6_Pos) /*!< CAN IFnDATAB2: DATA6 Mask */
<> 144:ef7eb2e8f9f7 1704
<> 144:ef7eb2e8f9f7 1705 #define CAN_IF_TXRQST1_TXRQST_Pos 0 /*!< CAN IFnTXRQST1: TXRQST Position */
<> 144:ef7eb2e8f9f7 1706 #define CAN_IF_TXRQST1_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST1_TXRQST_Pos) /*!< CAN IFnTXRQST1: TXRQST Mask */
<> 144:ef7eb2e8f9f7 1707
<> 144:ef7eb2e8f9f7 1708 #define CAN_IF_TXRQST2_TXRQST_Pos 0 /*!< CAN IFnTXRQST2: TXRQST Position */
<> 144:ef7eb2e8f9f7 1709 #define CAN_IF_TXRQST2_TXRQST_Msk (0xFFFFul << CAN_IF_TXRQST2_TXRQST_Pos) /*!< CAN IFnTXRQST2: TXRQST Mask */
<> 144:ef7eb2e8f9f7 1710
<> 144:ef7eb2e8f9f7 1711 #define CAN_IF_NDAT1_NEWDATA_Pos 0 /*!< CAN IFnNDAT1: NEWDATA Position */
<> 144:ef7eb2e8f9f7 1712 #define CAN_IF_NDAT1_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT1_NEWDATA_Pos) /*!< CAN IFnNDAT1: NEWDATA Mask */
<> 144:ef7eb2e8f9f7 1713
<> 144:ef7eb2e8f9f7 1714 #define CAN_IF_NDAT2_NEWDATA_Pos 0 /*!< CAN IFnNDAT2: NEWDATA Position */
<> 144:ef7eb2e8f9f7 1715 #define CAN_IF_NDAT2_NEWDATA_Msk (0xFFFFul << CAN_IF_NDAT2_NEWDATA_Pos) /*!< CAN IFnNDAT2: NEWDATA Mask */
<> 144:ef7eb2e8f9f7 1716
<> 144:ef7eb2e8f9f7 1717 #define CAN_IF_IPND1_INTPND_Pos 0 /*!< CAN IFnIPND1: INTPND Position */
<> 144:ef7eb2e8f9f7 1718 #define CAN_IF_IPND1_INTPND_Msk (0xFFFFul << CAN_IF_IPND1_INTPND_Pos) /*!< CAN IFnIPND1: INTPND Mask */
<> 144:ef7eb2e8f9f7 1719
<> 144:ef7eb2e8f9f7 1720 #define CAN_IF_IPND2_INTPND_Pos 0 /*!< CAN IFnIPND2: INTPND Position */
<> 144:ef7eb2e8f9f7 1721 #define CAN_IF_IPND2_INTPND_Msk (0xFFFFul << CAN_IF_IPND2_INTPND_Pos) /*!< CAN IFnIPND2: INTPND Mask */
<> 144:ef7eb2e8f9f7 1722
<> 144:ef7eb2e8f9f7 1723 #define CAN_IF_MVLD1_MSGVAL_Pos 0 /*!< CAN IFnMVLD1: MSGVAL Position */
<> 144:ef7eb2e8f9f7 1724 #define CAN_IF_MVLD1_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD1_MSGVAL_Pos) /*!< CAN IFnMVLD1: MSGVAL Mask */
<> 144:ef7eb2e8f9f7 1725
<> 144:ef7eb2e8f9f7 1726 #define CAN_IF_MVLD2_MSGVAL_Pos 0 /*!< CAN IFnMVLD2: MSGVAL Position */
<> 144:ef7eb2e8f9f7 1727 #define CAN_IF_MVLD2_MSGVAL_Msk (0xFFFFul << CAN_IF_MVLD2_MSGVAL_Pos) /*!< CAN IFnMVLD2: MSGVAL Mask */
<> 144:ef7eb2e8f9f7 1728
<> 144:ef7eb2e8f9f7 1729 #define CAN_WUEN_WAKUP_EN_Pos 0 /*!< CAN WUEN: WAKUP_EN Position */
<> 144:ef7eb2e8f9f7 1730 #define CAN_WUEN_WAKUP_EN_Msk (1ul << CAN_WUEN_WAKUP_EN_Pos) /*!< CAN WUEN: WAKUP_EN Mask */
<> 144:ef7eb2e8f9f7 1731
<> 144:ef7eb2e8f9f7 1732 #define CAN_WUSTATUS_WAKUP_STS_Pos 0 /*!< CAN WUSTATUS: WAKUP_STS Position */
<> 144:ef7eb2e8f9f7 1733 #define CAN_WUSTATUS_WAKUP_STS_Msk (1ul << CAN_WUSTATUS_WAKUP_STS_Pos) /*!< CAN WUSTATUS: WAKUP_STS Mask */
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 /**@}*/ /* CAN_CONST */
<> 144:ef7eb2e8f9f7 1736 /**@}*/ /* end of CAN register group */
<> 144:ef7eb2e8f9f7 1737
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 /*---------------------- Capture Engine -------------------------*/
<> 144:ef7eb2e8f9f7 1740 /**
<> 144:ef7eb2e8f9f7 1741 @addtogroup CAP Capture Engine(CAP)
<> 144:ef7eb2e8f9f7 1742 Memory Mapped Structure for CAP Controller
<> 144:ef7eb2e8f9f7 1743 @{ */
<> 144:ef7eb2e8f9f7 1744
<> 144:ef7eb2e8f9f7 1745 typedef struct {
<> 144:ef7eb2e8f9f7 1746
<> 144:ef7eb2e8f9f7 1747
<> 144:ef7eb2e8f9f7 1748 /**
<> 144:ef7eb2e8f9f7 1749 * CTL
<> 144:ef7eb2e8f9f7 1750 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1751 * Offset: 0x00 Image Capture Interface Control Register
<> 144:ef7eb2e8f9f7 1752 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1753 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1754 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1755 * |[0] |CAPEN |Image Capture Interface Enable
<> 144:ef7eb2e8f9f7 1756 * | | |0 = Image Capture Interface Disabled.
<> 144:ef7eb2e8f9f7 1757 * | | |1 = Image Capture Interface Enabled.
<> 144:ef7eb2e8f9f7 1758 * |[3] |ADDRSW |Packet Buffer Address Switch
<> 144:ef7eb2e8f9f7 1759 * | | |0 = Packet buffer address switch Disabled.
<> 144:ef7eb2e8f9f7 1760 * | | |1 = Packet buffer address switch Enabled.
<> 144:ef7eb2e8f9f7 1761 * |[5] |PLNEN |Planar Output Enable
<> 144:ef7eb2e8f9f7 1762 * | | |0 = Planar output Disabled.
<> 144:ef7eb2e8f9f7 1763 * | | |1 = Planar output Enabled.
<> 144:ef7eb2e8f9f7 1764 * |[6] |PKTEN |Packet Output Enable
<> 144:ef7eb2e8f9f7 1765 * | | |0 = Packet output Disabled.
<> 144:ef7eb2e8f9f7 1766 * | | |1 = Packet output Enabled.
<> 144:ef7eb2e8f9f7 1767 * |[16] |SHUTTER |Image Capture Interface Automatically Disable The Capture Inteface After A Frame Had Been Captured
<> 144:ef7eb2e8f9f7 1768 * | | |0 = Shutter Disabled.
<> 144:ef7eb2e8f9f7 1769 * | | |1 = Shutter Enabled.
<> 144:ef7eb2e8f9f7 1770 * |[20] |UPDATE |Update Register At New Frame
<> 144:ef7eb2e8f9f7 1771 * | | |0 = Update register at new frame Disabled.
<> 144:ef7eb2e8f9f7 1772 * | | |1 = Update register at new frame Enabled (Auto clear to 0 when register updated).
<> 144:ef7eb2e8f9f7 1773 * |[24] |VPRST |Capture Interface Reset
<> 144:ef7eb2e8f9f7 1774 * | | |0 = Capture interface reset Disabled.
<> 144:ef7eb2e8f9f7 1775 * | | |1 = Capture interface reset Enabled.
<> 144:ef7eb2e8f9f7 1776 */
<> 144:ef7eb2e8f9f7 1777 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 1778
<> 144:ef7eb2e8f9f7 1779 /**
<> 144:ef7eb2e8f9f7 1780 * PAR
<> 144:ef7eb2e8f9f7 1781 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1782 * Offset: 0x04 Image Capture Interface Parameter Register
<> 144:ef7eb2e8f9f7 1783 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1784 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1785 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1786 * |[0] |INFMT |Sensor Input Data Format
<> 144:ef7eb2e8f9f7 1787 * | | |0 = YCbCr422.
<> 144:ef7eb2e8f9f7 1788 * | | |1 = RGB565.
<> 144:ef7eb2e8f9f7 1789 * |[1] |SENTYPE |Sensor Input Type
<> 144:ef7eb2e8f9f7 1790 * | | |0 = CCIR601.
<> 144:ef7eb2e8f9f7 1791 * | | |1 = CCIR656, VSync & Hsync embedded in the data signal.
<> 144:ef7eb2e8f9f7 1792 * |[2:3] |INDATORD |Sensor Input Data Order
<> 144:ef7eb2e8f9f7 1793 * | | |If INFMT = 0 (YCbCr),.
<> 144:ef7eb2e8f9f7 1794 * | | | Byte 0 1 2 3
<> 144:ef7eb2e8f9f7 1795 * | | |00 = Y0 U0 Y1 V0.
<> 144:ef7eb2e8f9f7 1796 * | | |01 = Y0 V0 Y1 U0.
<> 144:ef7eb2e8f9f7 1797 * | | |10 = U0 Y0 V0 Y1.
<> 144:ef7eb2e8f9f7 1798 * | | |11 = V0 Y0 U0 Y1.
<> 144:ef7eb2e8f9f7 1799 * | | |If INFMT = 1 (RGB565),.
<> 144:ef7eb2e8f9f7 1800 * | | |00
<> 144:ef7eb2e8f9f7 1801 * | | |Byte 0
<> 144:ef7eb2e8f9f7 1802 * | | |R[4:0] G[5:3]
<> 144:ef7eb2e8f9f7 1803 * | | |Byte 1
<> 144:ef7eb2e8f9f7 1804 * | | |G[2:0] B[4:0]
<> 144:ef7eb2e8f9f7 1805 * | | |01
<> 144:ef7eb2e8f9f7 1806 * | | |Byte 0
<> 144:ef7eb2e8f9f7 1807 * | | |B[4:0] G[5:3]
<> 144:ef7eb2e8f9f7 1808 * | | |Byte 1
<> 144:ef7eb2e8f9f7 1809 * | | |G[2:0] R[4:0]
<> 144:ef7eb2e8f9f7 1810 * | | |10
<> 144:ef7eb2e8f9f7 1811 * | | |Byte 0
<> 144:ef7eb2e8f9f7 1812 * | | |G[2:0] B[4:0]
<> 144:ef7eb2e8f9f7 1813 * | | |Byte 1
<> 144:ef7eb2e8f9f7 1814 * | | |R[4:0] G[5:3]
<> 144:ef7eb2e8f9f7 1815 * | | |11
<> 144:ef7eb2e8f9f7 1816 * | | |Byte 0
<> 144:ef7eb2e8f9f7 1817 * | | |G[2:0] R[4:0]
<> 144:ef7eb2e8f9f7 1818 * | | |Byte 1
<> 144:ef7eb2e8f9f7 1819 * | | |R[4:0] G[5:3]
<> 144:ef7eb2e8f9f7 1820 * |[4:5] |OUTFMT |Image Data Format Output To System Memory
<> 144:ef7eb2e8f9f7 1821 * | | |00 = YCbCr422.
<> 144:ef7eb2e8f9f7 1822 * | | |01 = Only output Y.
<> 144:ef7eb2e8f9f7 1823 * | | |10 = RGB555.
<> 144:ef7eb2e8f9f7 1824 * | | |11 = RGB565.
<> 144:ef7eb2e8f9f7 1825 * |[6] |RANGE |Scale Input YUV CCIR601 Color Range To Full Range
<> 144:ef7eb2e8f9f7 1826 * | | |0 = default.
<> 144:ef7eb2e8f9f7 1827 * | | |1 = Scale to full range.
<> 144:ef7eb2e8f9f7 1828 * |[7] |PLNFMT |Planar Output YUV Format
<> 144:ef7eb2e8f9f7 1829 * | | |0 = YUV422.
<> 144:ef7eb2e8f9f7 1830 * | | |1 = YUV420.
<> 144:ef7eb2e8f9f7 1831 * |[8] |PCLKP |Sensor Pixel Clock Polarity
<> 144:ef7eb2e8f9f7 1832 * | | |0 = Input video data and signals are latched by falling edge of Pixel Clock.
<> 144:ef7eb2e8f9f7 1833 * | | |1 = Input video data and signals are latched by rising edge of Pixel Clock.
<> 144:ef7eb2e8f9f7 1834 * |[9] |HSP |Sensor Hsync Polarity
<> 144:ef7eb2e8f9f7 1835 * | | |0 = Sync Low.
<> 144:ef7eb2e8f9f7 1836 * | | |1 = Sync High.
<> 144:ef7eb2e8f9f7 1837 * |[10] |VSP |Sensor Vsync Polarity
<> 144:ef7eb2e8f9f7 1838 * | | |0 = Sync Low.
<> 144:ef7eb2e8f9f7 1839 * | | |1 = Sync High.
<> 144:ef7eb2e8f9f7 1840 * |[11:12] |COLORCTL |Special COLORCTL Processing
<> 144:ef7eb2e8f9f7 1841 * | | |00 = Normal Color.
<> 144:ef7eb2e8f9f7 1842 * | | |01 = Sepia effect, corresponding U,V component value is set at register CAP_SEPIA.
<> 144:ef7eb2e8f9f7 1843 * | | |10 = Negative picture.
<> 144:ef7eb2e8f9f7 1844 * | | |11 = Posterize image, the Y, U, V components posterizing factor are set at register CAP_POSTERIZE.
<> 144:ef7eb2e8f9f7 1845 * |[18] |FBB |Field By Blank
<> 144:ef7eb2e8f9f7 1846 * | | |Hardware will tag field0 or field1 by vertical blanking instead of FIELD flag in ccir-656 mode.
<> 144:ef7eb2e8f9f7 1847 * | | |0 = Field by blank Disabled.
<> 144:ef7eb2e8f9f7 1848 * | | |1 = Field by blank Enabled.
<> 144:ef7eb2e8f9f7 1849 */
<> 144:ef7eb2e8f9f7 1850 __IO uint32_t PAR;
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 /**
<> 144:ef7eb2e8f9f7 1853 * INT
<> 144:ef7eb2e8f9f7 1854 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1855 * Offset: 0x08 Image Capture Interface Interrupt Register
<> 144:ef7eb2e8f9f7 1856 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1857 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1858 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1859 * |[0] |VINTF |Video Frame End Interrupt
<> 144:ef7eb2e8f9f7 1860 * | | |If this bit shows 1, receiving a frame completed.
<> 144:ef7eb2e8f9f7 1861 * | | |Write 1 to clear it.
<> 144:ef7eb2e8f9f7 1862 * |[1] |MEINTF |Bus Master Transfer Error Interrupt
<> 144:ef7eb2e8f9f7 1863 * | | |If this bit shows 1, Transfer Error occurred. Write 1 to clear it.
<> 144:ef7eb2e8f9f7 1864 * |[3] |ADDRMINTF |Memory Address Match Interrupt
<> 144:ef7eb2e8f9f7 1865 * | | |If this bit shows 1, Memory Address Match Interrupt occurred.
<> 144:ef7eb2e8f9f7 1866 * | | |Write 1 to clear it.
<> 144:ef7eb2e8f9f7 1867 * |[4] |MDINTF |Motion Detection Output Finish Interrupt
<> 144:ef7eb2e8f9f7 1868 * | | |If this bit shows 1, Motion Detection Output Finish Interrupt occurred.
<> 144:ef7eb2e8f9f7 1869 * | | |Write 1 to clear it.
<> 144:ef7eb2e8f9f7 1870 * |[16] |VIEN |Video Frame End Interrupt Enable
<> 144:ef7eb2e8f9f7 1871 * | | |0 = Video frame end interrupt Disabled.
<> 144:ef7eb2e8f9f7 1872 * | | |1 = Video frame end interrupt Enabled.
<> 144:ef7eb2e8f9f7 1873 * |[17] |MEIEN |System Memory Error Interrupt Enable
<> 144:ef7eb2e8f9f7 1874 * | | |0 = System memory error interrupt Disabled.
<> 144:ef7eb2e8f9f7 1875 * | | |1 = System memory error interrupt Enabled.
<> 144:ef7eb2e8f9f7 1876 * |[19] |ADDRMIEN |Address Match Interrupt Enable
<> 144:ef7eb2e8f9f7 1877 * | | |0 = Address match interrupt Disabled.
<> 144:ef7eb2e8f9f7 1878 * | | |1 = Address match interrupt Enabled.
<> 144:ef7eb2e8f9f7 1879 * |[20] |MDIEN |Motion Detection Output Finish Interrupt Enable
<> 144:ef7eb2e8f9f7 1880 * | | |0 = CAP_MD finish interrupt Disabled.
<> 144:ef7eb2e8f9f7 1881 * | | |1 = CAP_MD finish interrupt Enabled.
<> 144:ef7eb2e8f9f7 1882 */
<> 144:ef7eb2e8f9f7 1883 __IO uint32_t INT;
<> 144:ef7eb2e8f9f7 1884
<> 144:ef7eb2e8f9f7 1885 /**
<> 144:ef7eb2e8f9f7 1886 * POSTERIZE
<> 144:ef7eb2e8f9f7 1887 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1888 * Offset: 0x0C YUV Component Posterizing Factor Register
<> 144:ef7eb2e8f9f7 1889 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1890 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1891 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1892 * |[0:7] |VCOMP |V Component Posterizing Factor
<> 144:ef7eb2e8f9f7 1893 * | | |Final_V_Out = Original_V[7:0] & V_Posterizing_Factor.
<> 144:ef7eb2e8f9f7 1894 * |[8:15] |UCOMP |U Component Posterizing Factor
<> 144:ef7eb2e8f9f7 1895 * | | |Final_U_Out = Original_U[7:0] & U_Posterizing_Factor.
<> 144:ef7eb2e8f9f7 1896 * |[16:23] |YCOMP |Y Component Posterizing Factor
<> 144:ef7eb2e8f9f7 1897 * | | |Final_Y_Out = Original_Y[7:0] & Y_Posterizing_Factor.
<> 144:ef7eb2e8f9f7 1898 */
<> 144:ef7eb2e8f9f7 1899 __IO uint32_t POSTERIZE;
<> 144:ef7eb2e8f9f7 1900
<> 144:ef7eb2e8f9f7 1901 /**
<> 144:ef7eb2e8f9f7 1902 * MD
<> 144:ef7eb2e8f9f7 1903 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1904 * Offset: 0x10 Motion Detection Register
<> 144:ef7eb2e8f9f7 1905 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1906 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1907 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1908 * |[0] |MDEN |Motion Detection Enable
<> 144:ef7eb2e8f9f7 1909 * | | |0 = CAP_MD Disabled.
<> 144:ef7eb2e8f9f7 1910 * | | |1 = CAP_MD Enabled.
<> 144:ef7eb2e8f9f7 1911 * |[8] |MDBS |Motion Detection Block Size
<> 144:ef7eb2e8f9f7 1912 * | | |0 = 16x16.
<> 144:ef7eb2e8f9f7 1913 * | | |1 = 8x8.
<> 144:ef7eb2e8f9f7 1914 * |[9] |MDSM |Motion Detection Save Mode
<> 144:ef7eb2e8f9f7 1915 * | | |0 = 1 bit DIFF + 7 bit Y Differential.
<> 144:ef7eb2e8f9f7 1916 * | | |1 = 1 bit DIFF only.
<> 144:ef7eb2e8f9f7 1917 * |[10:11] |MDDF |Motion Detection Detect Frequency
<> 144:ef7eb2e8f9f7 1918 * | | |00 = Each frame.
<> 144:ef7eb2e8f9f7 1919 * | | |01 = Every 2 frame.
<> 144:ef7eb2e8f9f7 1920 * | | |10 = Every 3 frame.
<> 144:ef7eb2e8f9f7 1921 * | | |11 = Every 4 frame.
<> 144:ef7eb2e8f9f7 1922 * |[16:20] |MDTHR |Motion Detection Differential Threshold
<> 144:ef7eb2e8f9f7 1923 */
<> 144:ef7eb2e8f9f7 1924 __IO uint32_t MD;
<> 144:ef7eb2e8f9f7 1925
<> 144:ef7eb2e8f9f7 1926 /**
<> 144:ef7eb2e8f9f7 1927 * MDADDR
<> 144:ef7eb2e8f9f7 1928 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1929 * Offset: 0x14 Motion Detection Output Address Register
<> 144:ef7eb2e8f9f7 1930 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1931 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1932 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1933 * |[0:31] |MDADDR |Motion Detection Output Address Register (Word Alignment)
<> 144:ef7eb2e8f9f7 1934 */
<> 144:ef7eb2e8f9f7 1935 __IO uint32_t MDADDR;
<> 144:ef7eb2e8f9f7 1936
<> 144:ef7eb2e8f9f7 1937 /**
<> 144:ef7eb2e8f9f7 1938 * MDYADDR
<> 144:ef7eb2e8f9f7 1939 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1940 * Offset: 0x18 Motion Detection Temp Y Output Address Register
<> 144:ef7eb2e8f9f7 1941 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1942 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1943 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1944 * |[0:31] |MDYADDR |Motion Detection Temp Y Output Address Register (Word Alignment)
<> 144:ef7eb2e8f9f7 1945 */
<> 144:ef7eb2e8f9f7 1946 __IO uint32_t MDYADDR;
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /**
<> 144:ef7eb2e8f9f7 1949 * SEPIA
<> 144:ef7eb2e8f9f7 1950 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1951 * Offset: 0x1C Sepia Effect Control Register
<> 144:ef7eb2e8f9f7 1952 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1953 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1954 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1955 * |[0:7] |VCOMP |Define the constant V component while Sepia color effect is turned on.
<> 144:ef7eb2e8f9f7 1956 * |[8:15] |UCOMP |Define the constant U component while Sepia color effect is turned on.
<> 144:ef7eb2e8f9f7 1957 */
<> 144:ef7eb2e8f9f7 1958 __IO uint32_t SEPIA;
<> 144:ef7eb2e8f9f7 1959
<> 144:ef7eb2e8f9f7 1960 /**
<> 144:ef7eb2e8f9f7 1961 * CWSP
<> 144:ef7eb2e8f9f7 1962 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1963 * Offset: 0x20 Cropping Window Starting Address Register
<> 144:ef7eb2e8f9f7 1964 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1965 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1966 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1967 * |[0:11] |CWSADDRH |Cropping Window Horizontal Starting Address
<> 144:ef7eb2e8f9f7 1968 * |[16:26] |CWSADDRV |Cropping Window Vertical Starting Address
<> 144:ef7eb2e8f9f7 1969 */
<> 144:ef7eb2e8f9f7 1970 __IO uint32_t CWSP;
<> 144:ef7eb2e8f9f7 1971
<> 144:ef7eb2e8f9f7 1972 /**
<> 144:ef7eb2e8f9f7 1973 * CWS
<> 144:ef7eb2e8f9f7 1974 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1975 * Offset: 0x24 Cropping Window Size Register
<> 144:ef7eb2e8f9f7 1976 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1977 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1978 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1979 * |[0:11] |CIWW |Cropping Image Window Width
<> 144:ef7eb2e8f9f7 1980 * |[16:26] |CIWH |Cropping Image Window Height
<> 144:ef7eb2e8f9f7 1981 */
<> 144:ef7eb2e8f9f7 1982 __IO uint32_t CWS;
<> 144:ef7eb2e8f9f7 1983
<> 144:ef7eb2e8f9f7 1984 /**
<> 144:ef7eb2e8f9f7 1985 * PKTSL
<> 144:ef7eb2e8f9f7 1986 * ===================================================================================================
<> 144:ef7eb2e8f9f7 1987 * Offset: 0x28 Packet Scaling Vertical/Horizontal Factor Register (LSB)
<> 144:ef7eb2e8f9f7 1988 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 1989 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 1990 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 1991 * |[0:7] |PKTSHML |Packet Scaling Horizontal Factor M (Lower 8-Bit)
<> 144:ef7eb2e8f9f7 1992 * | | |Specifies the lower 8-bit of denominator part (M) of the horizontal scaling factor.
<> 144:ef7eb2e8f9f7 1993 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHMH) to form a 16-bit denominator (M) of vertical factor.
<> 144:ef7eb2e8f9f7 1994 * | | |The output image width will be equal to the image width * N/M.
<> 144:ef7eb2e8f9f7 1995 * | | |Note: The value of N must be equal to or less than M.
<> 144:ef7eb2e8f9f7 1996 * |[8:15] |PKTSHNL |Packet Scaling Horizontal Factor N (Lower 8-Bit)
<> 144:ef7eb2e8f9f7 1997 * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
<> 144:ef7eb2e8f9f7 1998 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSHNH) to form a 16-bit numerator of horizontal factor.
<> 144:ef7eb2e8f9f7 1999 * |[16:23] |PKTSVML |Packet Scaling Vertical Factor M (Lower 8-Bit)
<> 144:ef7eb2e8f9f7 2000 * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
<> 144:ef7eb2e8f9f7 2001 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVMH) to form a 16-bit denominator (M) of vertical factor.
<> 144:ef7eb2e8f9f7 2002 * | | |The output image width will be equal to the image height * N/M.
<> 144:ef7eb2e8f9f7 2003 * | | |Note: The value of N must be equal to or less than M.
<> 144:ef7eb2e8f9f7 2004 * |[24:31] |PKTSVNL |Packet Scaling Vertical Factor N (Lower 8-Bit)
<> 144:ef7eb2e8f9f7 2005 * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
<> 144:ef7eb2e8f9f7 2006 * | | |The lower 8-bit will be cascaded with higher 8-bit (PKDSVNH) to form a 16-bit numerator of vertical factor
<> 144:ef7eb2e8f9f7 2007 */
<> 144:ef7eb2e8f9f7 2008 __IO uint32_t PKTSL;
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /**
<> 144:ef7eb2e8f9f7 2011 * PLNSL
<> 144:ef7eb2e8f9f7 2012 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2013 * Offset: 0x2C Planar Scaling Vertical/Horizontal Factor Register (LSB)
<> 144:ef7eb2e8f9f7 2014 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2015 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2016 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2017 * |[0:7] |PLNSHML |Planar Scaling Horizontal Factor M (Lower 8-Bit)
<> 144:ef7eb2e8f9f7 2018 * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
<> 144:ef7eb2e8f9f7 2019 * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHMH) to form a 16-bit denominator (M) of vertical factor.
<> 144:ef7eb2e8f9f7 2020 * | | |The output image width will be equal to the image width * N/M.
<> 144:ef7eb2e8f9f7 2021 * | | |Note: The value of N must be equal to or less than M.
<> 144:ef7eb2e8f9f7 2022 * |[8:15] |PLNSHNL |Planar Scaling Horizontal Factor N (Lower 8-Bit)
<> 144:ef7eb2e8f9f7 2023 * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
<> 144:ef7eb2e8f9f7 2024 * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSHNH) to form a 16-bit numerator of horizontal factor.
<> 144:ef7eb2e8f9f7 2025 * |[16:23] |PLNSVML |Planar Scaling Vertical Factor M (Lower 8-Bit)
<> 144:ef7eb2e8f9f7 2026 * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
<> 144:ef7eb2e8f9f7 2027 * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVMH) to form a 16-bit denominator (M) of vertical factor.
<> 144:ef7eb2e8f9f7 2028 * | | |The output image width will be equal to the image height * N/M.
<> 144:ef7eb2e8f9f7 2029 * | | |Note: The value of N must be equal to or less than M.
<> 144:ef7eb2e8f9f7 2030 * |[24:31] |PLNSVNL |Planar Scaling Vertical Factor N (Lower 8-Bit)
<> 144:ef7eb2e8f9f7 2031 * | | |Specify the lower 8-bit of numerator part (N) of the vertical scaling factor.
<> 144:ef7eb2e8f9f7 2032 * | | |The lower 8-bit will be cascaded with higher 8-bit (PNDSVNH) to form a 16-bit numerator of vertical factor.
<> 144:ef7eb2e8f9f7 2033 */
<> 144:ef7eb2e8f9f7 2034 __IO uint32_t PLNSL;
<> 144:ef7eb2e8f9f7 2035
<> 144:ef7eb2e8f9f7 2036 /**
<> 144:ef7eb2e8f9f7 2037 * FRCTL
<> 144:ef7eb2e8f9f7 2038 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2039 * Offset: 0x30 Scaling Frame Rate Factor Register
<> 144:ef7eb2e8f9f7 2040 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2041 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2042 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2043 * |[0:5] |FRM |Scaling Frame Rate Factor M
<> 144:ef7eb2e8f9f7 2044 * | | |Specify the denominator part (M) of the frame rate scaling factor.
<> 144:ef7eb2e8f9f7 2045 * | | |The output image frame rate will be equal to input image frame rate * (N/M).
<> 144:ef7eb2e8f9f7 2046 * | | |Note: The value of N must be equal to or less than M.
<> 144:ef7eb2e8f9f7 2047 * |[8:13] |FRN |Scaling Frame Rate Factor N
<> 144:ef7eb2e8f9f7 2048 * | | |Specify the denominator part (N) of the frame rate scaling factor.
<> 144:ef7eb2e8f9f7 2049 */
<> 144:ef7eb2e8f9f7 2050 __IO uint32_t FRCTL;
<> 144:ef7eb2e8f9f7 2051
<> 144:ef7eb2e8f9f7 2052 /**
<> 144:ef7eb2e8f9f7 2053 * STRIDE
<> 144:ef7eb2e8f9f7 2054 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2055 * Offset: 0x34 Frame Output Pixel Stride Width Register
<> 144:ef7eb2e8f9f7 2056 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2057 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2058 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2059 * |[0:13] |PKTSTRIDE |Packet Frame Output Pixel Stride Width
<> 144:ef7eb2e8f9f7 2060 * | | |The output pixel stride size of packet pipe.
<> 144:ef7eb2e8f9f7 2061 * |[16:29] |PLNSTRIDE |Planar Frame Output Pixel Stride Width
<> 144:ef7eb2e8f9f7 2062 * | | |The output pixel stride size of planar pipe.
<> 144:ef7eb2e8f9f7 2063 */
<> 144:ef7eb2e8f9f7 2064 __IO uint32_t STRIDE;
<> 144:ef7eb2e8f9f7 2065 uint32_t RESERVE0[1];
<> 144:ef7eb2e8f9f7 2066
<> 144:ef7eb2e8f9f7 2067
<> 144:ef7eb2e8f9f7 2068 /**
<> 144:ef7eb2e8f9f7 2069 * FIFOTH
<> 144:ef7eb2e8f9f7 2070 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2071 * Offset: 0x3C FIFO Threshold Register
<> 144:ef7eb2e8f9f7 2072 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2073 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2074 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2075 * |[0:3] |PLNVFTH |Planar V FIFO Threshold
<> 144:ef7eb2e8f9f7 2076 * |[8:11] |PLNUFTH |Planar U FIFO Threshold
<> 144:ef7eb2e8f9f7 2077 * |[16:20] |PLNYFTH |Planar Y FIFO Threshold
<> 144:ef7eb2e8f9f7 2078 * |[24:28] |PKTFTH |Packet FIFO Threshold
<> 144:ef7eb2e8f9f7 2079 * |[31] |OVF |FIFO Overflow Flag
<> 144:ef7eb2e8f9f7 2080 */
<> 144:ef7eb2e8f9f7 2081 __IO uint32_t FIFOTH;
<> 144:ef7eb2e8f9f7 2082
<> 144:ef7eb2e8f9f7 2083 /**
<> 144:ef7eb2e8f9f7 2084 * CMPADDR
<> 144:ef7eb2e8f9f7 2085 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2086 * Offset: 0x40 Compare Memory Base Address Register
<> 144:ef7eb2e8f9f7 2087 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2088 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2089 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2090 * |[0:31] |CMPADDR |Compare Memory Base Address
<> 144:ef7eb2e8f9f7 2091 * | | |Word aligns address; ignore the bits [1:0].
<> 144:ef7eb2e8f9f7 2092 */
<> 144:ef7eb2e8f9f7 2093 __IO uint32_t CMPADDR;
<> 144:ef7eb2e8f9f7 2094 uint32_t RESERVE1[1];
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096
<> 144:ef7eb2e8f9f7 2097 /**
<> 144:ef7eb2e8f9f7 2098 * PKTSM
<> 144:ef7eb2e8f9f7 2099 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2100 * Offset: 0x48 Packet Scaling Vertical/Horizontal Factor Register (MSB)
<> 144:ef7eb2e8f9f7 2101 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2102 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2103 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2104 * |[0:7] |PKTSHMH |Packet Scaling Horizontal Factor M (Higher 8-Bit)
<> 144:ef7eb2e8f9f7 2105 * | | |Specify the lower 8-bit of denominator part (M) of the horizontal scaling factor.
<> 144:ef7eb2e8f9f7 2106 * | | |Please refer to the register CAP_PKTSL?for the detailed operation.
<> 144:ef7eb2e8f9f7 2107 * |[8:15] |PKTSHNH |Packet Scaling Horizontal Factor N (Higher 8-Bit)
<> 144:ef7eb2e8f9f7 2108 * | | |Specify the lower 8-bit of numerator part (N) of the horizontal scaling factor.
<> 144:ef7eb2e8f9f7 2109 * | | |Please refer to the register CAP_PKTSL for the detailed operation.
<> 144:ef7eb2e8f9f7 2110 * |[16:23] |PKTSVMH |Packet Scaling Vertical Factor M (Higher 8-Bit)
<> 144:ef7eb2e8f9f7 2111 * | | |Specify the lower 8-bit of denominator part (M) of the vertical scaling factor.
<> 144:ef7eb2e8f9f7 2112 * | | |Please refer to the register CAP_PKTSL to check the cooperation between these two registers.
<> 144:ef7eb2e8f9f7 2113 * |[24:31] |PKTSVNH |Packet Scaling Vertical Factor N (Higher 8-Bit)
<> 144:ef7eb2e8f9f7 2114 * | | |Specify the higher 8-bit of numerator part (N) of the vertical scaling factor.
<> 144:ef7eb2e8f9f7 2115 * | | |Please refer to the register CAP_PKTSL?to check the cooperation between these two registers.
<> 144:ef7eb2e8f9f7 2116 */
<> 144:ef7eb2e8f9f7 2117 __IO uint32_t PKTSM;
<> 144:ef7eb2e8f9f7 2118
<> 144:ef7eb2e8f9f7 2119 /**
<> 144:ef7eb2e8f9f7 2120 * PLNSM
<> 144:ef7eb2e8f9f7 2121 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2122 * Offset: 0x4C Planar Scaling Vertical/Horizontal Factor Register (MSB)
<> 144:ef7eb2e8f9f7 2123 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2124 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2125 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2126 * |[0:7] |PLNSHMH |Planar Scaling Horizontal Factor M (Higher 8-Bit)
<> 144:ef7eb2e8f9f7 2127 * | | |Specifies the higher 8-bit of denominator part (M) of the horizontal scaling factor
<> 144:ef7eb2e8f9f7 2128 * | | |For detailed programming, please refer to the register “CAP_PLNSL?
<> 144:ef7eb2e8f9f7 2129 * |[8:15] |PLNSHNH |Planar Scaling Horizontal Factor N (Higher 8-Bit)
<> 144:ef7eb2e8f9f7 2130 * | | |Specifies the higher 8-bit of numerator part (N) of the horizontal scaling factor.
<> 144:ef7eb2e8f9f7 2131 * | | |For detailed programming, please refer to the register “CAP_PLNSL?
<> 144:ef7eb2e8f9f7 2132 * |[16:23] |PLNSVMH |Planar Scaling Vertical Factor M (Higher 8-Bit)
<> 144:ef7eb2e8f9f7 2133 * | | |Specifies the lower 8-bit of denominator part (M) of the vertical scaling factor.
<> 144:ef7eb2e8f9f7 2134 * | | |For detailed programming, please refer to the register “CAP_PLNSL?
<> 144:ef7eb2e8f9f7 2135 * |[24:31] |PLNSVNH |Planar Scaling Vertical Factor N (Higher 8-Bit)
<> 144:ef7eb2e8f9f7 2136 * | | |Specifies the higher 8-bit of numerator part (N) of the vertical scaling factor.
<> 144:ef7eb2e8f9f7 2137 * | | |For detailed programming, please refer to the register “CAP_PLNSL?
<> 144:ef7eb2e8f9f7 2138 */
<> 144:ef7eb2e8f9f7 2139 __IO uint32_t PLNSM;
<> 144:ef7eb2e8f9f7 2140
<> 144:ef7eb2e8f9f7 2141 /**
<> 144:ef7eb2e8f9f7 2142 * CURADDRP
<> 144:ef7eb2e8f9f7 2143 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2144 * Offset: 0x50 Current Packet System Memory Address Register
<> 144:ef7eb2e8f9f7 2145 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2146 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2147 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2148 * |[0:31] |CURADDR |Current Packet Output Memory Address
<> 144:ef7eb2e8f9f7 2149 */
<> 144:ef7eb2e8f9f7 2150 __I uint32_t CURADDRP;
<> 144:ef7eb2e8f9f7 2151
<> 144:ef7eb2e8f9f7 2152 /**
<> 144:ef7eb2e8f9f7 2153 * CURADDRY
<> 144:ef7eb2e8f9f7 2154 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2155 * Offset: 0x54 Current Planar Y System Memory Address Register
<> 144:ef7eb2e8f9f7 2156 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2157 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2158 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2159 * |[0:31] |CURADDR |Current Planar Y Output Memory Address
<> 144:ef7eb2e8f9f7 2160 */
<> 144:ef7eb2e8f9f7 2161 __I uint32_t CURADDRY;
<> 144:ef7eb2e8f9f7 2162
<> 144:ef7eb2e8f9f7 2163 /**
<> 144:ef7eb2e8f9f7 2164 * CURADDRU
<> 144:ef7eb2e8f9f7 2165 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2166 * Offset: 0x58 Current Planar U System Memory Address Register
<> 144:ef7eb2e8f9f7 2167 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2168 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2169 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2170 * |[0:31] |CURADDR |Current Planar U Output Memory Address
<> 144:ef7eb2e8f9f7 2171 */
<> 144:ef7eb2e8f9f7 2172 __I uint32_t CURADDRU;
<> 144:ef7eb2e8f9f7 2173
<> 144:ef7eb2e8f9f7 2174 /**
<> 144:ef7eb2e8f9f7 2175 * CURVADDR
<> 144:ef7eb2e8f9f7 2176 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2177 * Offset: 0x5C Current Planar V System Memory Address Register
<> 144:ef7eb2e8f9f7 2178 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2179 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2180 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2181 * |[0:31] |CURADDR |Current Planar V Output Memory Address
<> 144:ef7eb2e8f9f7 2182 */
<> 144:ef7eb2e8f9f7 2183 __I uint32_t CURVADDR;
<> 144:ef7eb2e8f9f7 2184
<> 144:ef7eb2e8f9f7 2185 /**
<> 144:ef7eb2e8f9f7 2186 * PKTBA0
<> 144:ef7eb2e8f9f7 2187 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2188 * Offset: 0x60 System Memory Packet Base Address 0 Register
<> 144:ef7eb2e8f9f7 2189 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2190 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2191 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2192 * |[0:31] |BASEADDR |System Memory Packet Base Address 0
<> 144:ef7eb2e8f9f7 2193 * | | |Word aligns address; ignore the bits [1:0].
<> 144:ef7eb2e8f9f7 2194 */
<> 144:ef7eb2e8f9f7 2195 __IO uint32_t PKTBA0;
<> 144:ef7eb2e8f9f7 2196
<> 144:ef7eb2e8f9f7 2197 /**
<> 144:ef7eb2e8f9f7 2198 * PKTBA1
<> 144:ef7eb2e8f9f7 2199 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2200 * Offset: 0x64 System Memory Packet Base Address 1 Register
<> 144:ef7eb2e8f9f7 2201 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2202 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2203 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2204 * |[0:31] |BASEADDR |System Memory Packet Base Address 1
<> 144:ef7eb2e8f9f7 2205 * | | |Word aligns address; ignore the bits [1:0].
<> 144:ef7eb2e8f9f7 2206 */
<> 144:ef7eb2e8f9f7 2207 __IO uint32_t PKTBA1;
<> 144:ef7eb2e8f9f7 2208 uint32_t RESERVE2[6];
<> 144:ef7eb2e8f9f7 2209
<> 144:ef7eb2e8f9f7 2210
<> 144:ef7eb2e8f9f7 2211 /**
<> 144:ef7eb2e8f9f7 2212 * YBA
<> 144:ef7eb2e8f9f7 2213 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2214 * Offset: 0x80 System Memory Planar Y Base Address Register
<> 144:ef7eb2e8f9f7 2215 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2216 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2217 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2218 * |[0:31] |BASEADDR |System Memory Planar Y Base Address
<> 144:ef7eb2e8f9f7 2219 * | | |Word aligns address; ignore the bits [1:0].
<> 144:ef7eb2e8f9f7 2220 */
<> 144:ef7eb2e8f9f7 2221 __IO uint32_t YBA;
<> 144:ef7eb2e8f9f7 2222
<> 144:ef7eb2e8f9f7 2223 /**
<> 144:ef7eb2e8f9f7 2224 * UBA
<> 144:ef7eb2e8f9f7 2225 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2226 * Offset: 0x84 System Memory Planar U Base Address Register
<> 144:ef7eb2e8f9f7 2227 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2228 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2229 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2230 * |[0:31] |BASEADDR |System Memory Planar U Base Address
<> 144:ef7eb2e8f9f7 2231 * | | |Word aligns address; ignore the bits [1:0].
<> 144:ef7eb2e8f9f7 2232 */
<> 144:ef7eb2e8f9f7 2233 __IO uint32_t UBA;
<> 144:ef7eb2e8f9f7 2234
<> 144:ef7eb2e8f9f7 2235 /**
<> 144:ef7eb2e8f9f7 2236 * VBA
<> 144:ef7eb2e8f9f7 2237 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2238 * Offset: 0x88 System Memory Planar V Base Address Register
<> 144:ef7eb2e8f9f7 2239 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2240 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2241 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2242 * |[0:31] |BASEADDR |System Memory Planar V Base Address
<> 144:ef7eb2e8f9f7 2243 * | | |Word aligns address; ignore the bits [1:0].
<> 144:ef7eb2e8f9f7 2244 */
<> 144:ef7eb2e8f9f7 2245 __IO uint32_t VBA;
<> 144:ef7eb2e8f9f7 2246
<> 144:ef7eb2e8f9f7 2247 } CAP_T;
<> 144:ef7eb2e8f9f7 2248
<> 144:ef7eb2e8f9f7 2249 /**
<> 144:ef7eb2e8f9f7 2250 @addtogroup CAP_CONST CAP Bit Field Definition
<> 144:ef7eb2e8f9f7 2251 Constant Definitions for CAP Controller
<> 144:ef7eb2e8f9f7 2252 @{ */
<> 144:ef7eb2e8f9f7 2253
<> 144:ef7eb2e8f9f7 2254 #define CAP_CTL_CAPEN_Pos (0) /*!< CAP CTL: CAPEN Position */
<> 144:ef7eb2e8f9f7 2255 #define CAP_CTL_CAPEN_Msk (0x1ul << CAP_CTL_CAPEN_Pos) /*!< CAP CTL: CAPEN Mask */
<> 144:ef7eb2e8f9f7 2256
<> 144:ef7eb2e8f9f7 2257 #define CAP_CTL_ADDRSW_Pos (3) /*!< CAP CTL: ADDRSW Position */
<> 144:ef7eb2e8f9f7 2258 #define CAP_CTL_ADDRSW_Msk (0x1ul << CAP_CTL_ADDRSW_Pos) /*!< CAP CTL: ADDRSW Mask */
<> 144:ef7eb2e8f9f7 2259
<> 144:ef7eb2e8f9f7 2260 #define CAP_CTL_PLNEN_Pos (5) /*!< CAP CTL: PLNEN Position */
<> 144:ef7eb2e8f9f7 2261 #define CAP_CTL_PLNEN_Msk (0x1ul << CAP_CTL_PLNEN_Pos) /*!< CAP CTL: PLNEN Mask */
<> 144:ef7eb2e8f9f7 2262
<> 144:ef7eb2e8f9f7 2263 #define CAP_CTL_PKTEN_Pos (6) /*!< CAP CTL: PKTEN Position */
<> 144:ef7eb2e8f9f7 2264 #define CAP_CTL_PKTEN_Msk (0x1ul << CAP_CTL_PKTEN_Pos) /*!< CAP CTL: PKTEN Mask */
<> 144:ef7eb2e8f9f7 2265
<> 144:ef7eb2e8f9f7 2266 #define CAP_CTL_SHUTTER_Pos (16) /*!< CAP CTL: SHUTTER Position */
<> 144:ef7eb2e8f9f7 2267 #define CAP_CTL_SHUTTER_Msk (0x1ul << CAP_CTL_SHUTTER_Pos) /*!< CAP CTL: SHUTTER Mask */
<> 144:ef7eb2e8f9f7 2268
<> 144:ef7eb2e8f9f7 2269 #define CAP_CTL_UPDATE_Pos (20) /*!< CAP CTL: UPDATE Position */
<> 144:ef7eb2e8f9f7 2270 #define CAP_CTL_UPDATE_Msk (0x1ul << CAP_CTL_UPDATE_Pos) /*!< CAP CTL: UPDATE Mask */
<> 144:ef7eb2e8f9f7 2271
<> 144:ef7eb2e8f9f7 2272 #define CAP_CTL_VPRST_Pos (24) /*!< CAP CTL: VPRST Position */
<> 144:ef7eb2e8f9f7 2273 #define CAP_CTL_VPRST_Msk (0x1ul << CAP_CTL_VPRST_Pos) /*!< CAP CTL: VPRST Mask */
<> 144:ef7eb2e8f9f7 2274
<> 144:ef7eb2e8f9f7 2275 #define CAP_PAR_INFMT_Pos (0) /*!< CAP PAR: INFMT Position */
<> 144:ef7eb2e8f9f7 2276 #define CAP_PAR_INFMT_Msk (0x1ul << CAP_PAR_INFMT_Pos) /*!< CAP PAR: INFMT Mask */
<> 144:ef7eb2e8f9f7 2277
<> 144:ef7eb2e8f9f7 2278 #define CAP_PAR_SENTYPE_Pos (1) /*!< CAP PAR: SENTYPE Position */
<> 144:ef7eb2e8f9f7 2279 #define CAP_PAR_SENTYPE_Msk (0x1ul << CAP_PAR_SENTYPE_Pos) /*!< CAP PAR: SENTYPE Mask */
<> 144:ef7eb2e8f9f7 2280
<> 144:ef7eb2e8f9f7 2281 #define CAP_PAR_INDATORD_Pos (2) /*!< CAP PAR: INDATORD Position */
<> 144:ef7eb2e8f9f7 2282 #define CAP_PAR_INDATORD_Msk (0x3ul << CAP_PAR_INDATORD_Pos) /*!< CAP PAR: INDATORD Mask */
<> 144:ef7eb2e8f9f7 2283
<> 144:ef7eb2e8f9f7 2284 #define CAP_PAR_OUTFMT_Pos (4) /*!< CAP PAR: OUTFMT Position */
<> 144:ef7eb2e8f9f7 2285 #define CAP_PAR_OUTFMT_Msk (0x3ul << CAP_PAR_OUTFMT_Pos) /*!< CAP PAR: OUTFMT Mask */
<> 144:ef7eb2e8f9f7 2286
<> 144:ef7eb2e8f9f7 2287 #define CAP_PAR_RANGE_Pos (6) /*!< CAP PAR: RANGE Position */
<> 144:ef7eb2e8f9f7 2288 #define CAP_PAR_RANGE_Msk (0x1ul << CAP_PAR_RANGE_Pos) /*!< CAP PAR: RANGE Mask */
<> 144:ef7eb2e8f9f7 2289
<> 144:ef7eb2e8f9f7 2290 #define CAP_PAR_PLNFMT_Pos (7) /*!< CAP PAR: PLNFMT Position */
<> 144:ef7eb2e8f9f7 2291 #define CAP_PAR_PLNFMT_Msk (0x1ul << CAP_PAR_PLNFMT_Pos) /*!< CAP PAR: PLNFMT Mask */
<> 144:ef7eb2e8f9f7 2292
<> 144:ef7eb2e8f9f7 2293 #define CAP_PAR_PCLKP_Pos (8) /*!< CAP PAR: PCLKP Position */
<> 144:ef7eb2e8f9f7 2294 #define CAP_PAR_PCLKP_Msk (0x1ul << CAP_PAR_PCLKP_Pos) /*!< CAP PAR: PCLKP Mask */
<> 144:ef7eb2e8f9f7 2295
<> 144:ef7eb2e8f9f7 2296 #define CAP_PAR_HSP_Pos (9) /*!< CAP PAR: HSP Position */
<> 144:ef7eb2e8f9f7 2297 #define CAP_PAR_HSP_Msk (0x1ul << CAP_PAR_HSP_Pos) /*!< CAP PAR: HSP Mask */
<> 144:ef7eb2e8f9f7 2298
<> 144:ef7eb2e8f9f7 2299 #define CAP_PAR_VSP_Pos (10) /*!< CAP PAR: VSP Position */
<> 144:ef7eb2e8f9f7 2300 #define CAP_PAR_VSP_Msk (0x1ul << CAP_PAR_VSP_Pos) /*!< CAP PAR: VSP Mask */
<> 144:ef7eb2e8f9f7 2301
<> 144:ef7eb2e8f9f7 2302 #define CAP_PAR_COLORCTL_Pos (11) /*!< CAP PAR: COLORCTL Position */
<> 144:ef7eb2e8f9f7 2303 #define CAP_PAR_COLORCTL_Msk (0x3ul << CAP_PAR_COLORCTL_Pos) /*!< CAP PAR: COLORCTL Mask */
<> 144:ef7eb2e8f9f7 2304
<> 144:ef7eb2e8f9f7 2305 #define CAP_PAR_FBB_Pos (18) /*!< CAP PAR: FBB Position */
<> 144:ef7eb2e8f9f7 2306 #define CAP_PAR_FBB_Msk (0x1ul << CAP_PAR_FBB_Pos) /*!< CAP PAR: FBB Mask */
<> 144:ef7eb2e8f9f7 2307
<> 144:ef7eb2e8f9f7 2308 #define CAP_INT_VINTF_Pos (0) /*!< CAP INT: VINTF Position */
<> 144:ef7eb2e8f9f7 2309 #define CAP_INT_VINTF_Msk (0x1ul << CAP_INT_VINTF_Pos) /*!< CAP INT: VINTF Mask */
<> 144:ef7eb2e8f9f7 2310
<> 144:ef7eb2e8f9f7 2311 #define CAP_INT_MEINTF_Pos (1) /*!< CAP INT: MEINTF Position */
<> 144:ef7eb2e8f9f7 2312 #define CAP_INT_MEINTF_Msk (0x1ul << CAP_INT_MEINTF_Pos) /*!< CAP INT: MEINTF Mask */
<> 144:ef7eb2e8f9f7 2313
<> 144:ef7eb2e8f9f7 2314 #define CAP_INT_ADDRMINTF_Pos (3) /*!< CAP INT: ADDRMINTF Position */
<> 144:ef7eb2e8f9f7 2315 #define CAP_INT_ADDRMINTF_Msk (0x1ul << CAP_INT_ADDRMINTF_Pos) /*!< CAP INT: ADDRMINTF Mask */
<> 144:ef7eb2e8f9f7 2316
<> 144:ef7eb2e8f9f7 2317 #define CAP_INT_MDINTF_Pos (4) /*!< CAP INT: MDINTF Position */
<> 144:ef7eb2e8f9f7 2318 #define CAP_INT_MDINTF_Msk (0x1ul << CAP_INT_MDINTF_Pos) /*!< CAP INT: MDINTF Mask */
<> 144:ef7eb2e8f9f7 2319
<> 144:ef7eb2e8f9f7 2320 #define CAP_INT_VIEN_Pos (16) /*!< CAP INT: VIEN Position */
<> 144:ef7eb2e8f9f7 2321 #define CAP_INT_VIEN_Msk (0x1ul << CAP_INT_VIEN_Pos) /*!< CAP INT: VIEN Mask */
<> 144:ef7eb2e8f9f7 2322
<> 144:ef7eb2e8f9f7 2323 #define CAP_INT_MEIEN_Pos (17) /*!< CAP INT: MEIEN Position */
<> 144:ef7eb2e8f9f7 2324 #define CAP_INT_MEIEN_Msk (0x1ul << CAP_INT_MEIEN_Pos) /*!< CAP INT: MEIEN Mask */
<> 144:ef7eb2e8f9f7 2325
<> 144:ef7eb2e8f9f7 2326 #define CAP_INT_ADDRMIEN_Pos (19) /*!< CAP INT: ADDRMIEN Position */
<> 144:ef7eb2e8f9f7 2327 #define CAP_INT_ADDRMIEN_Msk (0x1ul << CAP_INT_ADDRMIEN_Pos) /*!< CAP INT: ADDRMIEN Mask */
<> 144:ef7eb2e8f9f7 2328
<> 144:ef7eb2e8f9f7 2329 #define CAP_INT_MDIEN_Pos (20) /*!< CAP INT: MDIEN Position */
<> 144:ef7eb2e8f9f7 2330 #define CAP_INT_MDIEN_Msk (0x1ul << CAP_INT_MDIEN_Pos) /*!< CAP INT: MDIEN Mask */
<> 144:ef7eb2e8f9f7 2331
<> 144:ef7eb2e8f9f7 2332 #define CAP_POSTERIZE_VCOMP_Pos (0) /*!< CAP POSTERIZE: VCOMP Position */
<> 144:ef7eb2e8f9f7 2333 #define CAP_POSTERIZE_VCOMP_Msk (0xfful << CAP_POSTERIZE_VCOMP_Pos) /*!< CAP POSTERIZE: VCOMP Mask */
<> 144:ef7eb2e8f9f7 2334
<> 144:ef7eb2e8f9f7 2335 #define CAP_POSTERIZE_UCOMP_Pos (8) /*!< CAP POSTERIZE: UCOMP Position */
<> 144:ef7eb2e8f9f7 2336 #define CAP_POSTERIZE_UCOMP_Msk (0xfful << CAP_POSTERIZE_UCOMP_Pos) /*!< CAP POSTERIZE: UCOMP Mask */
<> 144:ef7eb2e8f9f7 2337
<> 144:ef7eb2e8f9f7 2338 #define CAP_POSTERIZE_YCOMP_Pos (16) /*!< CAP POSTERIZE: YCOMP Position */
<> 144:ef7eb2e8f9f7 2339 #define CAP_POSTERIZE_YCOMP_Msk (0xfful << CAP_POSTERIZE_YCOMP_Pos) /*!< CAP POSTERIZE: YCOMP Mask */
<> 144:ef7eb2e8f9f7 2340
<> 144:ef7eb2e8f9f7 2341 #define CAP_MD_MDEN_Pos (0) /*!< CAP MD: MDEN Position */
<> 144:ef7eb2e8f9f7 2342 #define CAP_MD_MDEN_Msk (0x1ul << CAP_MD_MDEN_Pos) /*!< CAP MD: MDEN Mask */
<> 144:ef7eb2e8f9f7 2343
<> 144:ef7eb2e8f9f7 2344 #define CAP_MD_MDBS_Pos (8) /*!< CAP MD: MDBS Position */
<> 144:ef7eb2e8f9f7 2345 #define CAP_MD_MDBS_Msk (0x1ul << CAP_MD_MDBS_Pos) /*!< CAP MD: MDBS Mask */
<> 144:ef7eb2e8f9f7 2346
<> 144:ef7eb2e8f9f7 2347 #define CAP_MD_MDSM_Pos (9) /*!< CAP MD: MDSM Position */
<> 144:ef7eb2e8f9f7 2348 #define CAP_MD_MDSM_Msk (0x1ul << CAP_MD_MDSM_Pos) /*!< CAP MD: MDSM Mask */
<> 144:ef7eb2e8f9f7 2349
<> 144:ef7eb2e8f9f7 2350 #define CAP_MD_MDDF_Pos (10) /*!< CAP MD: MDDF Position */
<> 144:ef7eb2e8f9f7 2351 #define CAP_MD_MDDF_Msk (0x3ul << CAP_MD_MDDF_Pos) /*!< CAP MD: MDDF Mask */
<> 144:ef7eb2e8f9f7 2352
<> 144:ef7eb2e8f9f7 2353 #define CAP_MD_MDTHR_Pos (16) /*!< CAP MD: MDTHR Position */
<> 144:ef7eb2e8f9f7 2354 #define CAP_MD_MDTHR_Msk (0x1ful << CAP_MD_MDTHR_Pos) /*!< CAP MD: MDTHR Mask */
<> 144:ef7eb2e8f9f7 2355
<> 144:ef7eb2e8f9f7 2356 #define CAP_MDADDR_MDADDR_Pos (0) /*!< CAP MDADDR: MDADDR Position */
<> 144:ef7eb2e8f9f7 2357 #define CAP_MDADDR_MDADDR_Msk (0xfffffffful << CAP_MDADDR_MDADDR_Pos) /*!< CAP MDADDR: MDADDR Mask */
<> 144:ef7eb2e8f9f7 2358
<> 144:ef7eb2e8f9f7 2359 #define CAP_MDYADDR_MDYADDR_Pos (0) /*!< CAP MDYADDR: MDYADDR Position */
<> 144:ef7eb2e8f9f7 2360 #define CAP_MDYADDR_MDYADDR_Msk (0xfffffffful << CAP_MDYADDR_MDYADDR_Pos) /*!< CAP MDYADDR: MDYADDR Mask */
<> 144:ef7eb2e8f9f7 2361
<> 144:ef7eb2e8f9f7 2362 #define CAP_SEPIA_VCOMP_Pos (0) /*!< CAP SEPIA: VCOMP Position */
<> 144:ef7eb2e8f9f7 2363 #define CAP_SEPIA_VCOMP_Msk (0xfful << CAP_SEPIA_VCOMP_Pos) /*!< CAP SEPIA: VCOMP Mask */
<> 144:ef7eb2e8f9f7 2364
<> 144:ef7eb2e8f9f7 2365 #define CAP_SEPIA_UCOMP_Pos (8) /*!< CAP SEPIA: UCOMP Position */
<> 144:ef7eb2e8f9f7 2366 #define CAP_SEPIA_UCOMP_Msk (0xfful << CAP_SEPIA_UCOMP_Pos) /*!< CAP SEPIA: UCOMP Mask */
<> 144:ef7eb2e8f9f7 2367
<> 144:ef7eb2e8f9f7 2368 #define CAP_CWSP_CWSADDRH_Pos (0) /*!< CAP CWSP: CWSADDRH Position */
<> 144:ef7eb2e8f9f7 2369 #define CAP_CWSP_CWSADDRH_Msk (0xffful << CAP_CWSP_CWSADDRH_Pos) /*!< CAP CWSP: CWSADDRH Mask */
<> 144:ef7eb2e8f9f7 2370
<> 144:ef7eb2e8f9f7 2371 #define CAP_CWSP_CWSADDRV_Pos (16) /*!< CAP CWSP: CWSADDRV Position */
<> 144:ef7eb2e8f9f7 2372 #define CAP_CWSP_CWSADDRV_Msk (0x7fful << CAP_CWSP_CWSADDRV_Pos) /*!< CAP CWSP: CWSADDRV Mask */
<> 144:ef7eb2e8f9f7 2373
<> 144:ef7eb2e8f9f7 2374 #define CAP_CWS_CWW_Pos (0) /*!< CAP CWS: CWW Position */
<> 144:ef7eb2e8f9f7 2375 #define CAP_CWS_CWW_Msk (0xffful << CAP_CWS_CWW_Pos) /*!< CAP CWS: CWW Mask */
<> 144:ef7eb2e8f9f7 2376
<> 144:ef7eb2e8f9f7 2377 #define CAP_CWS_CWH_Pos (16) /*!< CAP CWS: CIWH Position */
<> 144:ef7eb2e8f9f7 2378 #define CAP_CWS_CWH_Msk (0x7fful << CAP_CWS_CWH_Pos) /*!< CAP CWS: CIWH Mask */
<> 144:ef7eb2e8f9f7 2379
<> 144:ef7eb2e8f9f7 2380 #define CAP_PKTSL_PKTSHML_Pos (0) /*!< CAP PKTSL: PKTSHML Position */
<> 144:ef7eb2e8f9f7 2381 #define CAP_PKTSL_PKTSHML_Msk (0xfful << CAP_PKTSL_PKTSHML_Pos) /*!< CAP PKTSL: PKTSHML Mask */
<> 144:ef7eb2e8f9f7 2382
<> 144:ef7eb2e8f9f7 2383 #define CAP_PKTSL_PKTSHNL_Pos (8) /*!< CAP PKTSL: PKTSHNL Position */
<> 144:ef7eb2e8f9f7 2384 #define CAP_PKTSL_PKTSHNL_Msk (0xfful << CAP_PKTSL_PKTSHNL_Pos) /*!< CAP PKTSL: PKTSHNL Mask */
<> 144:ef7eb2e8f9f7 2385
<> 144:ef7eb2e8f9f7 2386 #define CAP_PKTSL_PKTSVML_Pos (16) /*!< CAP PKTSL: PKTSVML Position */
<> 144:ef7eb2e8f9f7 2387 #define CAP_PKTSL_PKTSVML_Msk (0xfful << CAP_PKTSL_PKTSVML_Pos) /*!< CAP PKTSL: PKTSVML Mask */
<> 144:ef7eb2e8f9f7 2388
<> 144:ef7eb2e8f9f7 2389 #define CAP_PKTSL_PKTSVNL_Pos (24) /*!< CAP PKTSL: PKTSVNL Position */
<> 144:ef7eb2e8f9f7 2390 #define CAP_PKTSL_PKTSVNL_Msk (0xfful << CAP_PKTSL_PKTSVNL_Pos) /*!< CAP PKTSL: PKTSVNL Mask */
<> 144:ef7eb2e8f9f7 2391
<> 144:ef7eb2e8f9f7 2392 #define CAP_PLNSL_PLNSHML_Pos (0) /*!< CAP PLNSL: PLNSHML Position */
<> 144:ef7eb2e8f9f7 2393 #define CAP_PLNSL_PLNSHML_Msk (0xfful << CAP_PLNSL_PLNSHML_Pos) /*!< CAP PLNSL: PLNSHML Mask */
<> 144:ef7eb2e8f9f7 2394
<> 144:ef7eb2e8f9f7 2395 #define CAP_PLNSL_PLNSHNL_Pos (8) /*!< CAP PLNSL: PLNSHNL Position */
<> 144:ef7eb2e8f9f7 2396 #define CAP_PLNSL_PLNSHNL_Msk (0xfful << CAP_PLNSL_PLNSHNL_Pos) /*!< CAP PLNSL: PLNSHNL Mask */
<> 144:ef7eb2e8f9f7 2397
<> 144:ef7eb2e8f9f7 2398 #define CAP_PLNSL_PLNSVML_Pos (16) /*!< CAP PLNSL: PLNSVML Position */
<> 144:ef7eb2e8f9f7 2399 #define CAP_PLNSL_PLNSVML_Msk (0xfful << CAP_PLNSL_PLNSVML_Pos) /*!< CAP PLNSL: PLNSVML Mask */
<> 144:ef7eb2e8f9f7 2400
<> 144:ef7eb2e8f9f7 2401 #define CAP_PLNSL_PLNSVNL_Pos (24) /*!< CAP PLNSL: PLNSVNL Position */
<> 144:ef7eb2e8f9f7 2402 #define CAP_PLNSL_PLNSVNL_Msk (0xfful << CAP_PLNSL_PLNSVNL_Pos) /*!< CAP PLNSL: PLNSVNL Mask */
<> 144:ef7eb2e8f9f7 2403
<> 144:ef7eb2e8f9f7 2404 #define CAP_FRCTL_FRM_Pos (0) /*!< CAP FRCTL: FRM Position */
<> 144:ef7eb2e8f9f7 2405 #define CAP_FRCTL_FRM_Msk (0x3ful << CAP_FRCTL_FRM_Pos) /*!< CAP FRCTL: FRM Mask */
<> 144:ef7eb2e8f9f7 2406
<> 144:ef7eb2e8f9f7 2407 #define CAP_FRCTL_FRN_Pos (8) /*!< CAP FRCTL: FRN Position */
<> 144:ef7eb2e8f9f7 2408 #define CAP_FRCTL_FRN_Msk (0x3ful << CAP_FRCTL_FRN_Pos) /*!< CAP FRCTL: FRN Mask */
<> 144:ef7eb2e8f9f7 2409
<> 144:ef7eb2e8f9f7 2410 #define CAP_STRIDE_PKTSTRIDE_Pos (0) /*!< CAP STRIDE: PKTSTRIDE Position */
<> 144:ef7eb2e8f9f7 2411 #define CAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CAP_STRIDE_PKTSTRIDE_Pos) /*!< CAP STRIDE: PKTSTRIDE Mask */
<> 144:ef7eb2e8f9f7 2412
<> 144:ef7eb2e8f9f7 2413 #define CAP_STRIDE_PLNSTRIDE_Pos (16) /*!< CAP STRIDE: PLNSTRIDE Position */
<> 144:ef7eb2e8f9f7 2414 #define CAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CAP_STRIDE_PLNSTRIDE_Pos) /*!< CAP STRIDE: PLNSTRIDE Mask */
<> 144:ef7eb2e8f9f7 2415
<> 144:ef7eb2e8f9f7 2416 #define CAP_FIFOTH_PLNVFTH_Pos (0) /*!< CAP FIFOTH: PLNVFTH Position */
<> 144:ef7eb2e8f9f7 2417 #define CAP_FIFOTH_PLNVFTH_Msk (0xful << CAP_FIFOTH_PLNVFTH_Pos) /*!< CAP FIFOTH: PLNVFTH Mask */
<> 144:ef7eb2e8f9f7 2418
<> 144:ef7eb2e8f9f7 2419 #define CAP_FIFOTH_PLNUFTH_Pos (8) /*!< CAP FIFOTH: PLNUFTH Position */
<> 144:ef7eb2e8f9f7 2420 #define CAP_FIFOTH_PLNUFTH_Msk (0xful << CAP_FIFOTH_PLNUFTH_Pos) /*!< CAP FIFOTH: PLNUFTH Mask */
<> 144:ef7eb2e8f9f7 2421
<> 144:ef7eb2e8f9f7 2422 #define CAP_FIFOTH_PLNYFTH_Pos (16) /*!< CAP FIFOTH: PLNYFTH Position */
<> 144:ef7eb2e8f9f7 2423 #define CAP_FIFOTH_PLNYFTH_Msk (0x1ful << CAP_FIFOTH_PLNYFTH_Pos) /*!< CAP FIFOTH: PLNYFTH Mask */
<> 144:ef7eb2e8f9f7 2424
<> 144:ef7eb2e8f9f7 2425 #define CAP_FIFOTH_PKTFTH_Pos (24) /*!< CAP FIFOTH: PKTFTH Position */
<> 144:ef7eb2e8f9f7 2426 #define CAP_FIFOTH_PKTFTH_Msk (0x1ful << CAP_FIFOTH_PKTFTH_Pos) /*!< CAP FIFOTH: PKTFTH Mask */
<> 144:ef7eb2e8f9f7 2427
<> 144:ef7eb2e8f9f7 2428 #define CAP_FIFOTH_OVF_Pos (31) /*!< CAP FIFOTH: OVF Position */
<> 144:ef7eb2e8f9f7 2429 #define CAP_FIFOTH_OVF_Msk (0x1ul << CAP_FIFOTH_OVF_Pos) /*!< CAP FIFOTH: OVF Mask */
<> 144:ef7eb2e8f9f7 2430
<> 144:ef7eb2e8f9f7 2431 #define CAP_CMPADDR_CMPADDR_Pos (0) /*!< CAP CMPADDR: CMPADDR Position */
<> 144:ef7eb2e8f9f7 2432 #define CAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CAP_CMPADDR_CMPADDR_Pos) /*!< CAP CMPADDR: CMPADDR Mask */
<> 144:ef7eb2e8f9f7 2433
<> 144:ef7eb2e8f9f7 2434 #define CAP_PKTSM_PKTSHMH_Pos (0) /*!< CAP PKTSM: PKTSHMH Position */
<> 144:ef7eb2e8f9f7 2435 #define CAP_PKTSM_PKTSHMH_Msk (0xfful << CAP_PKTSM_PKTSHMH_Pos) /*!< CAP PKTSM: PKTSHMH Mask */
<> 144:ef7eb2e8f9f7 2436
<> 144:ef7eb2e8f9f7 2437 #define CAP_PKTSM_PKTSHNH_Pos (8) /*!< CAP PKTSM: PKTSHNH Position */
<> 144:ef7eb2e8f9f7 2438 #define CAP_PKTSM_PKTSHNH_Msk (0xfful << CAP_PKTSM_PKTSHNH_Pos) /*!< CAP PKTSM: PKTSHNH Mask */
<> 144:ef7eb2e8f9f7 2439
<> 144:ef7eb2e8f9f7 2440 #define CAP_PKTSM_PKTSVMH_Pos (16) /*!< CAP PKTSM: PKTSVMH Position */
<> 144:ef7eb2e8f9f7 2441 #define CAP_PKTSM_PKTSVMH_Msk (0xfful << CAP_PKTSM_PKTSVMH_Pos) /*!< CAP PKTSM: PKTSVMH Mask */
<> 144:ef7eb2e8f9f7 2442
<> 144:ef7eb2e8f9f7 2443 #define CAP_PKTSM_PKTSVNH_Pos (24) /*!< CAP PKTSM: PKTSVNH Position */
<> 144:ef7eb2e8f9f7 2444 #define CAP_PKTSM_PKTSVNH_Msk (0xfful << CAP_PKTSM_PKTSVNH_Pos) /*!< CAP PKTSM: PKTSVNH Mask */
<> 144:ef7eb2e8f9f7 2445
<> 144:ef7eb2e8f9f7 2446 #define CAP_PLNSM_PLNSHMH_Pos (0) /*!< CAP PLNSM: PLNSHMH Position */
<> 144:ef7eb2e8f9f7 2447 #define CAP_PLNSM_PLNSHMH_Msk (0xfful << CAP_PLNSM_PLNSHMH_Pos) /*!< CAP PLNSM: PLNSHMH Mask */
<> 144:ef7eb2e8f9f7 2448
<> 144:ef7eb2e8f9f7 2449 #define CAP_PLNSM_PLNSHNH_Pos (8) /*!< CAP PLNSM: PLNSHNH Position */
<> 144:ef7eb2e8f9f7 2450 #define CAP_PLNSM_PLNSHNH_Msk (0xfful << CAP_PLNSM_PLNSHNH_Pos) /*!< CAP PLNSM: PLNSHNH Mask */
<> 144:ef7eb2e8f9f7 2451
<> 144:ef7eb2e8f9f7 2452 #define CAP_PLNSM_PLNSVMH_Pos (16) /*!< CAP PLNSM: PLNSVMH Position */
<> 144:ef7eb2e8f9f7 2453 #define CAP_PLNSM_PLNSVMH_Msk (0xfful << CAP_PLNSM_PLNSVMH_Pos) /*!< CAP PLNSM: PLNSVMH Mask */
<> 144:ef7eb2e8f9f7 2454
<> 144:ef7eb2e8f9f7 2455 #define CAP_PLNSM_PLNSVNH_Pos (24) /*!< CAP PLNSM: PLNSVNH Position */
<> 144:ef7eb2e8f9f7 2456 #define CAP_PLNSM_PLNSVNH_Msk (0xfful << CAP_PLNSM_PLNSVNH_Pos) /*!< CAP PLNSM: PLNSVNH Mask */
<> 144:ef7eb2e8f9f7 2457
<> 144:ef7eb2e8f9f7 2458 #define CAP_CURADDRP_CURADDR_Pos (0) /*!< CAP CURADDRP: CURADDR Position */
<> 144:ef7eb2e8f9f7 2459 #define CAP_CURADDRP_CURADDR_Msk (0xfffffffful << CAP_CURADDRP_CURADDR_Pos) /*!< CAP CURADDRP: CURADDR Mask */
<> 144:ef7eb2e8f9f7 2460
<> 144:ef7eb2e8f9f7 2461 #define CAP_CURADDRY_CURADDR_Pos (0) /*!< CAP CURADDRY: CURADDR Position */
<> 144:ef7eb2e8f9f7 2462 #define CAP_CURADDRY_CURADDR_Msk (0xfffffffful << CAP_CURADDRY_CURADDR_Pos) /*!< CAP CURADDRY: CURADDR Mask */
<> 144:ef7eb2e8f9f7 2463
<> 144:ef7eb2e8f9f7 2464 #define CAP_CURADDRU_CURADDR_Pos (0) /*!< CAP CURADDRU: CURADDR Position */
<> 144:ef7eb2e8f9f7 2465 #define CAP_CURADDRU_CURADDR_Msk (0xfffffffful << CAP_CURADDRU_CURADDR_Pos) /*!< CAP CURADDRU: CURADDR Mask */
<> 144:ef7eb2e8f9f7 2466
<> 144:ef7eb2e8f9f7 2467 #define CAP_CURVADDR_CURADDR_Pos (0) /*!< CAP CURVADDR: CURADDR Position */
<> 144:ef7eb2e8f9f7 2468 #define CAP_CURVADDR_CURADDR_Msk (0xfffffffful << CAP_CURVADDR_CURADDR_Pos) /*!< CAP CURVADDR: CURADDR Mask */
<> 144:ef7eb2e8f9f7 2469
<> 144:ef7eb2e8f9f7 2470 #define CAP_PKTBA0_BASEADDR_Pos (0) /*!< CAP PKTBA0: BASEADDR Position */
<> 144:ef7eb2e8f9f7 2471 #define CAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CAP_PKTBA0_BASEADDR_Pos) /*!< CAP PKTBA0: BASEADDR Mask */
<> 144:ef7eb2e8f9f7 2472
<> 144:ef7eb2e8f9f7 2473 #define CAP_PKTBA1_BASEADDR_Pos (0) /*!< CAP PKTBA1: BASEADDR Position */
<> 144:ef7eb2e8f9f7 2474 #define CAP_PKTBA1_BASEADDR_Msk (0xfffffffful << CAP_PKTBA1_BASEADDR_Pos) /*!< CAP PKTBA1: BASEADDR Mask */
<> 144:ef7eb2e8f9f7 2475
<> 144:ef7eb2e8f9f7 2476 #define CAP_YBA_BASEADDR_Pos (0) /*!< CAP YBA: BASEADDR Position */
<> 144:ef7eb2e8f9f7 2477 #define CAP_YBA_BASEADDR_Msk (0xfffffffful << CAP_YBA_BASEADDR_Pos) /*!< CAP YBA: BASEADDR Mask */
<> 144:ef7eb2e8f9f7 2478
<> 144:ef7eb2e8f9f7 2479 #define CAP_UBA_BASEADDR_Pos (0) /*!< CAP UBA: BASEADDR Position */
<> 144:ef7eb2e8f9f7 2480 #define CAP_UBA_BASEADDR_Msk (0xfffffffful << CAP_UBA_BASEADDR_Pos) /*!< CAP UBA: BASEADDR Mask */
<> 144:ef7eb2e8f9f7 2481
<> 144:ef7eb2e8f9f7 2482 #define CAP_VBA_BASEADDR_Pos (0) /*!< CAP VBA: BASEADDR Position */
<> 144:ef7eb2e8f9f7 2483 #define CAP_VBA_BASEADDR_Msk (0xfffffffful << CAP_VBA_BASEADDR_Pos) /*!< CAP VBA: BASEADDR Mask */
<> 144:ef7eb2e8f9f7 2484
<> 144:ef7eb2e8f9f7 2485 /**@}*/ /* CAP_CONST */
<> 144:ef7eb2e8f9f7 2486 /**@}*/ /* end of CAP register group */
<> 144:ef7eb2e8f9f7 2487
<> 144:ef7eb2e8f9f7 2488
<> 144:ef7eb2e8f9f7 2489 /*---------------------- Enhanced Input Capture Timer -------------------------*/
<> 144:ef7eb2e8f9f7 2490 /**
<> 144:ef7eb2e8f9f7 2491 @addtogroup ECAP Enhanced Input Capture Timer(ECAP)
<> 144:ef7eb2e8f9f7 2492 Memory Mapped Structure for ECAP Controller
<> 144:ef7eb2e8f9f7 2493 @{ */
<> 144:ef7eb2e8f9f7 2494
<> 144:ef7eb2e8f9f7 2495 typedef struct {
<> 144:ef7eb2e8f9f7 2496
<> 144:ef7eb2e8f9f7 2497
<> 144:ef7eb2e8f9f7 2498 /**
<> 144:ef7eb2e8f9f7 2499 * CNT
<> 144:ef7eb2e8f9f7 2500 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2501 * Offset: 0x00 Input Capture Counter (24-bit up counter)
<> 144:ef7eb2e8f9f7 2502 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2503 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2504 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2505 * |[0:23] |VAL |Input Capture Timer/Counter
<> 144:ef7eb2e8f9f7 2506 * | | |The input Capture Timer/Counter is a 24-bit up-counting counter.
<> 144:ef7eb2e8f9f7 2507 * | | |The clock source for the counter is from the clock divider output which the CAP_CLK is software optionally divided by 1,4,16 or 32.
<> 144:ef7eb2e8f9f7 2508 */
<> 144:ef7eb2e8f9f7 2509 __IO uint32_t CNT;
<> 144:ef7eb2e8f9f7 2510
<> 144:ef7eb2e8f9f7 2511 /**
<> 144:ef7eb2e8f9f7 2512 * HOLD0
<> 144:ef7eb2e8f9f7 2513 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2514 * Offset: 0x04 Input Capture Counter Hold Register 0
<> 144:ef7eb2e8f9f7 2515 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2516 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2517 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2518 * |[0:23] |VAL |Input Capture Counter Hold Register
<> 144:ef7eb2e8f9f7 2519 * | | |When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
<> 144:ef7eb2e8f9f7 2520 * | | |Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
<> 144:ef7eb2e8f9f7 2521 */
<> 144:ef7eb2e8f9f7 2522 __IO uint32_t HOLD0;
<> 144:ef7eb2e8f9f7 2523
<> 144:ef7eb2e8f9f7 2524 /**
<> 144:ef7eb2e8f9f7 2525 * HOLD1
<> 144:ef7eb2e8f9f7 2526 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2527 * Offset: 0x08 Input Capture Counter Hold Register 1
<> 144:ef7eb2e8f9f7 2528 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2529 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2530 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2531 * |[0:23] |VAL |Input Capture Counter Hold Register
<> 144:ef7eb2e8f9f7 2532 * | | |When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
<> 144:ef7eb2e8f9f7 2533 * | | |Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
<> 144:ef7eb2e8f9f7 2534 */
<> 144:ef7eb2e8f9f7 2535 __IO uint32_t HOLD1;
<> 144:ef7eb2e8f9f7 2536
<> 144:ef7eb2e8f9f7 2537 /**
<> 144:ef7eb2e8f9f7 2538 * HOLD2
<> 144:ef7eb2e8f9f7 2539 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2540 * Offset: 0x0C Input Capture Counter Hold Register 2
<> 144:ef7eb2e8f9f7 2541 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2542 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2543 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2544 * |[0:23] |VAL |Input Capture Counter Hold Register
<> 144:ef7eb2e8f9f7 2545 * | | |When an active input capture channel detects a valid edge signal change, the ECAP_CNT value is latched into the corresponding holding register.
<> 144:ef7eb2e8f9f7 2546 * | | |Each input channel has itself holding register named by ECAP_HOLDx where x is from 0 to 2 to indicate inputs from IC0 to IC2, respectively.
<> 144:ef7eb2e8f9f7 2547 */
<> 144:ef7eb2e8f9f7 2548 __IO uint32_t HOLD2;
<> 144:ef7eb2e8f9f7 2549
<> 144:ef7eb2e8f9f7 2550 /**
<> 144:ef7eb2e8f9f7 2551 * CNTCMP
<> 144:ef7eb2e8f9f7 2552 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2553 * Offset: 0x10 Input Capture Counter Compare Register
<> 144:ef7eb2e8f9f7 2554 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2555 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2556 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2557 * |[0:23] |VAL |Input Capture Counter Compare Register
<> 144:ef7eb2e8f9f7 2558 * | | |If the compare function is enabled (CMPEN = 1), the compare register is loaded with the value that the compare function compares the capture counter (ECAP_CNT) with.
<> 144:ef7eb2e8f9f7 2559 * | | |If the reload control is enabled (RLDEN = 1), an overflow event or capture events will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.
<> 144:ef7eb2e8f9f7 2560 */
<> 144:ef7eb2e8f9f7 2561 __IO uint32_t CNTCMP;
<> 144:ef7eb2e8f9f7 2562
<> 144:ef7eb2e8f9f7 2563 /**
<> 144:ef7eb2e8f9f7 2564 * CTL0
<> 144:ef7eb2e8f9f7 2565 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2566 * Offset: 0x14 Input Capture Control Register 0
<> 144:ef7eb2e8f9f7 2567 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2568 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2569 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2570 * |[0:1] |NFDIS |Noise Filter Clock Pre-Divide Selection
<> 144:ef7eb2e8f9f7 2571 * | | |To determine the sampling frequency of the Noise Filter clock
<> 144:ef7eb2e8f9f7 2572 * | | |00 = CAP_CLK.
<> 144:ef7eb2e8f9f7 2573 * | | |01 = CAP_CLK/2.
<> 144:ef7eb2e8f9f7 2574 * | | |10 = CAP_CLK/4.
<> 144:ef7eb2e8f9f7 2575 * | | |11 = CAP_CLK/16.
<> 144:ef7eb2e8f9f7 2576 * |[3] |CAPNF_DIS |Input Capture Noise Filter Disable Control
<> 144:ef7eb2e8f9f7 2577 * | | |0 = Noise filter of Input Capture Enabled.
<> 144:ef7eb2e8f9f7 2578 * | | |1 = Noise filter of Input Capture Disabled.
<> 144:ef7eb2e8f9f7 2579 * |[4] |CAPEN0 |Port Pin IC0 Input To Input Capture Unit Enable Control
<> 144:ef7eb2e8f9f7 2580 * | | |0 = IC0 input to Input Capture Unit Disabled.
<> 144:ef7eb2e8f9f7 2581 * | | |1 = IC0 input to Input Capture Unit Enabled.
<> 144:ef7eb2e8f9f7 2582 * |[5] |CAPEN1 |Port Pin IC1 Input To Input Capture Unit Enable Control
<> 144:ef7eb2e8f9f7 2583 * | | |0 = IC1 input to Input Capture Unit Disabled.
<> 144:ef7eb2e8f9f7 2584 * | | |1 = IC1 input to Input Capture Unit Enabled.
<> 144:ef7eb2e8f9f7 2585 * |[6] |CAPEN2 |Port Pin IC2 Input To Input Capture Unit Enable Control
<> 144:ef7eb2e8f9f7 2586 * | | |0 = IC2 input to Input Capture Unit Disabled.
<> 144:ef7eb2e8f9f7 2587 * | | |1 = IC2 input to Input Capture Unit Enabled.
<> 144:ef7eb2e8f9f7 2588 * |[8:9] |CAPSEL0 |CAP0 Input Source Selection
<> 144:ef7eb2e8f9f7 2589 * | | |00 = CAP0 input is from port pin IC0.
<> 144:ef7eb2e8f9f7 2590 * | | |01 = CAP0 input is from signal CPO0 (Analog comparator 0 output).
<> 144:ef7eb2e8f9f7 2591 * | | |10 = CAP0 input is from signal CHA of QEI controller unit x.
<> 144:ef7eb2e8f9f7 2592 * | | |11 = CAP0 input is from signal OPDO0 (OP0 digital output).
<> 144:ef7eb2e8f9f7 2593 * | | |Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
<> 144:ef7eb2e8f9f7 2594 * |[10:11] |CAPSEL1 |CAP1 Input Source Selection
<> 144:ef7eb2e8f9f7 2595 * | | |00 = CAP1 input is from port pin IC1.
<> 144:ef7eb2e8f9f7 2596 * | | |01 = CAP1 input is from signal CPO1 (Analog comparator 1 output).
<> 144:ef7eb2e8f9f7 2597 * | | |10 = CAP1 input is from signal CHB of QEI controller unit x.
<> 144:ef7eb2e8f9f7 2598 * | | |11 = CAP1 input is from signal OPDO1 (OP1 digital output).
<> 144:ef7eb2e8f9f7 2599 * | | |Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
<> 144:ef7eb2e8f9f7 2600 * |[12:13] |CAPSEL2 |CAP2 Input Source Selection
<> 144:ef7eb2e8f9f7 2601 * | | |00 = CAP2 input is from port pin IC2.
<> 144:ef7eb2e8f9f7 2602 * | | |01 = CAP2 input is from signal CPO2 (Analog comparator 2 output).
<> 144:ef7eb2e8f9f7 2603 * | | |10 = CAP2 input is from signal CHX of QEI controller unit x.
<> 144:ef7eb2e8f9f7 2604 * | | |11 = CAP2 input is from signal ADCMPOx (ADC compare output x).
<> 144:ef7eb2e8f9f7 2605 * | | |Note: Input capture unit n matches QEI or comparator unit x, where x = 0~1.
<> 144:ef7eb2e8f9f7 2606 * |[16] |CAPIEN0 |Input Capture Channel 0 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 2607 * | | |0 = The flag CAPF0 can trigger Input Capture interrupt Disabled.
<> 144:ef7eb2e8f9f7 2608 * | | |1 = The flag CAPF0 can trigger Input Capture interrupt Enabled.
<> 144:ef7eb2e8f9f7 2609 * |[17] |CAPIEN1 |Input Capture Channel 1 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 2610 * | | |0 = The flag CAPF1 can trigger Input Capture interrupt Disabled.
<> 144:ef7eb2e8f9f7 2611 * | | |1 = The flag CAPF1 can trigger Input Capture interrupt Enabled.
<> 144:ef7eb2e8f9f7 2612 * |[18] |CAPIEN2 |Input Capture Channel 2 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 2613 * | | |0 = The flag CAPF2 can trigger Input Capture interrupt Disabled.
<> 144:ef7eb2e8f9f7 2614 * | | |1 = The flag CAPF2 can trigger Input Capture interrupt Enabled.
<> 144:ef7eb2e8f9f7 2615 * |[20] |OVIEN |OVF Trigger Input Capture Interrupt Enable Control
<> 144:ef7eb2e8f9f7 2616 * | | |0 = The flag OVUNF can trigger Input Capture interrupt Disabled.
<> 144:ef7eb2e8f9f7 2617 * | | |1 = The flag OVUNF can trigger Input Capture interrupt Enabled.
<> 144:ef7eb2e8f9f7 2618 * |[21] |CMPIEN |CMPF Trigger Input Capture Interrupt Enable Control
<> 144:ef7eb2e8f9f7 2619 * | | |0 = The flag CMPF can trigger Input Capture interrupt Disabled.
<> 144:ef7eb2e8f9f7 2620 * | | |1 = The flag CMPF can trigger Input Capture interrupt Enabled.
<> 144:ef7eb2e8f9f7 2621 * |[24] |CNTEN |Input Capture Counter Start
<> 144:ef7eb2e8f9f7 2622 * | | |Setting this bit to 1, the capture counter (ECAP_CNT) starts up-counting synchronously with capture clock input (CAP_CLK).
<> 144:ef7eb2e8f9f7 2623 * | | |0 = ECAP_CNT stop counting.
<> 144:ef7eb2e8f9f7 2624 * | | |1 = ECAP_CNT starts up-counting.
<> 144:ef7eb2e8f9f7 2625 * |[25] |CMPCLR |Input Capture Counter Cleared By Compare-Match Control
<> 144:ef7eb2e8f9f7 2626 * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to 0 when the compare-match event (CAMCMPF = 1) occurs.
<> 144:ef7eb2e8f9f7 2627 * | | |0 = Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Disabled.
<> 144:ef7eb2e8f9f7 2628 * | | |1 = Compare-match event (CAMCMPF) can clear capture counter (ECAP_CNT) Enabled.
<> 144:ef7eb2e8f9f7 2629 * |[26] |CPTCLR |Input Capture Counter Cleared By Capture Events Control
<> 144:ef7eb2e8f9f7 2630 * | | |If this bit is set to 1, the capture counter (ECAP_CNT) will be cleared to zero when any one of capture events (CAPF0~3) occurs.
<> 144:ef7eb2e8f9f7 2631 * | | |0 = Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Disabled.
<> 144:ef7eb2e8f9f7 2632 * | | |1 = Capture events (CAPF0~3) can clear capture counter (ECAP_CNT) Enabled.
<> 144:ef7eb2e8f9f7 2633 * |[27] |RLDEN |Reload Function Enable Control
<> 144:ef7eb2e8f9f7 2634 * | | |Setting this bit to enable the reload function.
<> 144:ef7eb2e8f9f7 2635 * | | |If the reload control is enabled, an overflow event (OVF) or capture events (CAPFx) will trigger the hardware to reload ECAP_CNTCMP into ECAP_CNT.
<> 144:ef7eb2e8f9f7 2636 * | | |0 = The reload function Disabled.
<> 144:ef7eb2e8f9f7 2637 * | | |1 = The reload function Enabled.
<> 144:ef7eb2e8f9f7 2638 * |[28] |CMPEN |Compare Function Enable Control
<> 144:ef7eb2e8f9f7 2639 * | | |The compare function in input capture timer/counter is to compare the dynamic counting ECAP_CNT with the compare register ECAP_CNTCMP, if ECAP_CNT value reaches ECAP_CNTCMP, the flag CMPF will be set.
<> 144:ef7eb2e8f9f7 2640 * | | |0 = The compare function Disabled.
<> 144:ef7eb2e8f9f7 2641 * | | |1 = The compare function Enabled.
<> 144:ef7eb2e8f9f7 2642 * |[29] |CAPEN |Input Capture Timer/Counter Enable Control
<> 144:ef7eb2e8f9f7 2643 * | | |0 = Input Capture function Disabled.
<> 144:ef7eb2e8f9f7 2644 * | | |1 = Input Capture function Enabled.
<> 144:ef7eb2e8f9f7 2645 */
<> 144:ef7eb2e8f9f7 2646 __IO uint32_t CTL0;
<> 144:ef7eb2e8f9f7 2647
<> 144:ef7eb2e8f9f7 2648 /**
<> 144:ef7eb2e8f9f7 2649 * CTL1
<> 144:ef7eb2e8f9f7 2650 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2651 * Offset: 0x18 Input Capture Control Register 1
<> 144:ef7eb2e8f9f7 2652 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2653 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2654 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2655 * |[0:1] |EDGESEL0 |Channel 0 Captured Edge Selection
<> 144:ef7eb2e8f9f7 2656 * | | |Input capture can detect falling edge change only, rising edge change only or one of both edge change
<> 144:ef7eb2e8f9f7 2657 * | | |00 = Detect rising edge.
<> 144:ef7eb2e8f9f7 2658 * | | |01 = Detect falling edge.
<> 144:ef7eb2e8f9f7 2659 * | | |1x = Detect either rising or falling edge.
<> 144:ef7eb2e8f9f7 2660 * |[2:3] |EDGESEL1 |Channel 1 Captured Edge Selection
<> 144:ef7eb2e8f9f7 2661 * | | |Input capture can detect falling edge change only, rising edge change only or one of both edge change
<> 144:ef7eb2e8f9f7 2662 * | | |00 = Detect rising edge.
<> 144:ef7eb2e8f9f7 2663 * | | |01 = Detect falling edge.
<> 144:ef7eb2e8f9f7 2664 * | | |1x = Detect either rising or falling edge.
<> 144:ef7eb2e8f9f7 2665 * |[4:5] |EDGESEL2 |Channel 2 Captured Edge Selection
<> 144:ef7eb2e8f9f7 2666 * | | |Input capture can detect falling edge change or rising edge change only, or one of both edge changes.
<> 144:ef7eb2e8f9f7 2667 * | | |00 = Detect rising edge.
<> 144:ef7eb2e8f9f7 2668 * | | |01 = Detect falling edge.
<> 144:ef7eb2e8f9f7 2669 * | | |1x = Detect either rising or falling edge.
<> 144:ef7eb2e8f9f7 2670 * |[8:10] |RLDSEL |ECAP_CNT Reload Trigger Source Selection
<> 144:ef7eb2e8f9f7 2671 * | | |If the reload function is enabled RLDEN (ECAP_CTL0[27]) = 1, when a reload trigger event comes, the ECAP_CNT is reloaded with ECAP_CNTCMP.
<> 144:ef7eb2e8f9f7 2672 * | | |RLDSEL[2:0] determines the ECAP_CNT reload trigger source
<> 144:ef7eb2e8f9f7 2673 * | | |000 = CAPF0.
<> 144:ef7eb2e8f9f7 2674 * | | |001 = CAPF1.
<> 144:ef7eb2e8f9f7 2675 * | | |010 = CAPF2.
<> 144:ef7eb2e8f9f7 2676 * | | |100 = OVF.
<> 144:ef7eb2e8f9f7 2677 * | | |Others = Reserved.
<> 144:ef7eb2e8f9f7 2678 * |[12:14] |CLKSEL |Capture Timer Clock Divide Selection
<> 144:ef7eb2e8f9f7 2679 * | | |The capture timer clock has a pre-divider with four divided options controlled by CLKSEL[1:0].
<> 144:ef7eb2e8f9f7 2680 * | | |000 = CAP_CLK/1.
<> 144:ef7eb2e8f9f7 2681 * | | |001 = CAP_CLK/4.
<> 144:ef7eb2e8f9f7 2682 * | | |010 = CAP_CLK/16.
<> 144:ef7eb2e8f9f7 2683 * | | |011 = CAP_CLK/32.
<> 144:ef7eb2e8f9f7 2684 * | | |100 = CAP_CLK/64.
<> 144:ef7eb2e8f9f7 2685 * | | |101 = CAP_CLK/96.
<> 144:ef7eb2e8f9f7 2686 * | | |110 = CAP_CLK/112.
<> 144:ef7eb2e8f9f7 2687 * | | |111 = CAP_CLK/128.
<> 144:ef7eb2e8f9f7 2688 * |[16:17] |SRCSEL |Capture Timer/Counter Clock Source Selection
<> 144:ef7eb2e8f9f7 2689 * | | |Select the capture timer/counter clock source.
<> 144:ef7eb2e8f9f7 2690 * | | |00 = CAP_CLK (default).
<> 144:ef7eb2e8f9f7 2691 * | | |01 = CAP0.
<> 144:ef7eb2e8f9f7 2692 * | | |10 = CAP1.
<> 144:ef7eb2e8f9f7 2693 * | | |11 = CAP2.
<> 144:ef7eb2e8f9f7 2694 */
<> 144:ef7eb2e8f9f7 2695 __IO uint32_t CTL1;
<> 144:ef7eb2e8f9f7 2696
<> 144:ef7eb2e8f9f7 2697 /**
<> 144:ef7eb2e8f9f7 2698 * STATUS
<> 144:ef7eb2e8f9f7 2699 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2700 * Offset: 0x1C Input Capture Status Register
<> 144:ef7eb2e8f9f7 2701 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2702 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2703 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2704 * |[0] |CAPF0 |Input Capture Channel 0 Captured Flag
<> 144:ef7eb2e8f9f7 2705 * | | |When the input capture channel 0 detects a valid edge change at CAP0 input, it will set flag CAPF0 to high.
<> 144:ef7eb2e8f9f7 2706 * | | |0 = No valid edge change is detected at CAP0 input.
<> 144:ef7eb2e8f9f7 2707 * | | |1 = A valid edge change is detected at CAP0 input.
<> 144:ef7eb2e8f9f7 2708 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 2709 * |[1] |CAPF1 |Input Capture Channel 1 Captured Flag
<> 144:ef7eb2e8f9f7 2710 * | | |When the input capture channel 1 detects a valid edge change at CAP1 input, it will set flag CAPF1 to high.
<> 144:ef7eb2e8f9f7 2711 * | | |0 = No valid edge change is detected at CAP1 input.
<> 144:ef7eb2e8f9f7 2712 * | | |1 = A valid edge change is detected at CAP1 input.
<> 144:ef7eb2e8f9f7 2713 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 2714 * |[2] |CAPF2 |Input Capture Channel 2 Captured Flag
<> 144:ef7eb2e8f9f7 2715 * | | |When the input capture channel 2 detects a valid edge change at CAP2 input, it will set flag CAPF2 to high.
<> 144:ef7eb2e8f9f7 2716 * | | |0 = No valid edge change is detected at CAP2 input.
<> 144:ef7eb2e8f9f7 2717 * | | |1 = A valid edge change is detected at CAP2 input.
<> 144:ef7eb2e8f9f7 2718 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 2719 * |[4] |CMPF |Input Capture Compare-Match Flag
<> 144:ef7eb2e8f9f7 2720 * | | |If the input capture compare function is enabled, the flag is set by hardware while capture counter (ECAP_CNT) up counts and reach to the ECAP_CNTCMP value.
<> 144:ef7eb2e8f9f7 2721 * | | |0 = ECAP_CNT does not match with ECAP_CNTCMP value.
<> 144:ef7eb2e8f9f7 2722 * | | |1 = ECAP_CNT counts to the same as ECAP_CNTCMP value.
<> 144:ef7eb2e8f9f7 2723 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 2724 * |[5] |OVF |Input Capture Counter Overflow Flag
<> 144:ef7eb2e8f9f7 2725 * | | |Flag is set by hardware when input capture up counter (ECAP_CNT) overflows from 0x00FF_FFFF to zero.
<> 144:ef7eb2e8f9f7 2726 * | | |0 = No overflow occurs in ECAP_CNT.
<> 144:ef7eb2e8f9f7 2727 * | | |1 = ECAP_CNT overflows.
<> 144:ef7eb2e8f9f7 2728 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 2729 */
<> 144:ef7eb2e8f9f7 2730 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 2731
<> 144:ef7eb2e8f9f7 2732 } ECAP_T;
<> 144:ef7eb2e8f9f7 2733
<> 144:ef7eb2e8f9f7 2734 /**
<> 144:ef7eb2e8f9f7 2735 @addtogroup ECAP_CONST ECAP Bit Field Definition
<> 144:ef7eb2e8f9f7 2736 Constant Definitions for ECAP Controller
<> 144:ef7eb2e8f9f7 2737 @{ */
<> 144:ef7eb2e8f9f7 2738
<> 144:ef7eb2e8f9f7 2739 #define ECAP_CNT_VAL_Pos (0) /*!< ECAP CNT: VAL Position */
<> 144:ef7eb2e8f9f7 2740 #define ECAP_CNT_VAL_Msk (0xfffffful << ECAP_CNT_VAL_Pos) /*!< ECAP CNT: VAL Mask */
<> 144:ef7eb2e8f9f7 2741
<> 144:ef7eb2e8f9f7 2742 #define ECAP_HOLD0_VAL_Pos (0) /*!< ECAP HOLD0: VAL Position */
<> 144:ef7eb2e8f9f7 2743 #define ECAP_HOLD0_VAL_Msk (0xfffffful << ECAP_HOLD0_VAL_Pos) /*!< ECAP HOLD0: VAL Mask */
<> 144:ef7eb2e8f9f7 2744
<> 144:ef7eb2e8f9f7 2745 #define ECAP_HOLD1_VAL_Pos (0) /*!< ECAP HOLD1: VAL Position */
<> 144:ef7eb2e8f9f7 2746 #define ECAP_HOLD1_VAL_Msk (0xfffffful << ECAP_HOLD1_VAL_Pos) /*!< ECAP HOLD1: VAL Mask */
<> 144:ef7eb2e8f9f7 2747
<> 144:ef7eb2e8f9f7 2748 #define ECAP_HOLD2_VAL_Pos (0) /*!< ECAP HOLD2: VAL Position */
<> 144:ef7eb2e8f9f7 2749 #define ECAP_HOLD2_VAL_Msk (0xfffffful << ECAP_HOLD2_VAL_Pos) /*!< ECAP HOLD2: VAL Mask */
<> 144:ef7eb2e8f9f7 2750
<> 144:ef7eb2e8f9f7 2751 #define ECAP_CNTCMP_VAL_Pos (0) /*!< ECAP CNTCMP: VAL Position */
<> 144:ef7eb2e8f9f7 2752 #define ECAP_CNTCMP_VAL_Msk (0xfffffful << ECAP_CNTCMP_VAL_Pos) /*!< ECAP CNTCMP: VAL Mask */
<> 144:ef7eb2e8f9f7 2753
<> 144:ef7eb2e8f9f7 2754 #define ECAP_CTL0_NFDIS_Pos (0) /*!< ECAP CTL0: NFDIS Position */
<> 144:ef7eb2e8f9f7 2755 #define ECAP_CTL0_NFDIS_Msk (0x3ul << ECAP_CTL0_NFDIS_Pos) /*!< ECAP CTL0: NFDIS Mask */
<> 144:ef7eb2e8f9f7 2756
<> 144:ef7eb2e8f9f7 2757 #define ECAP_CTL0_CAPNF_DIS_Pos (3) /*!< ECAP CTL0: CAPNF_DIS Position */
<> 144:ef7eb2e8f9f7 2758 #define ECAP_CTL0_CAPNF_DIS_Msk (0x1ul << ECAP_CTL0_CAPNF_DIS_Pos) /*!< ECAP CTL0: CAPNF_DIS Mask */
<> 144:ef7eb2e8f9f7 2759
<> 144:ef7eb2e8f9f7 2760 #define ECAP_CTL0_CAPEN0_Pos (4) /*!< ECAP CTL0: CAPEN0 Position */
<> 144:ef7eb2e8f9f7 2761 #define ECAP_CTL0_CAPEN0_Msk (0x1ul << ECAP_CTL0_CAPEN0_Pos) /*!< ECAP CTL0: CAPEN0 Mask */
<> 144:ef7eb2e8f9f7 2762
<> 144:ef7eb2e8f9f7 2763 #define ECAP_CTL0_CAPEN1_Pos (5) /*!< ECAP CTL0: CAPEN1 Position */
<> 144:ef7eb2e8f9f7 2764 #define ECAP_CTL0_CAPEN1_Msk (0x1ul << ECAP_CTL0_CAPEN1_Pos) /*!< ECAP CTL0: CAPEN1 Mask */
<> 144:ef7eb2e8f9f7 2765
<> 144:ef7eb2e8f9f7 2766 #define ECAP_CTL0_CAPEN2_Pos (6) /*!< ECAP CTL0: CAPEN2 Position */
<> 144:ef7eb2e8f9f7 2767 #define ECAP_CTL0_CAPEN2_Msk (0x1ul << ECAP_CTL0_CAPEN2_Pos) /*!< ECAP CTL0: CAPEN2 Mask */
<> 144:ef7eb2e8f9f7 2768
<> 144:ef7eb2e8f9f7 2769 #define ECAP_CTL0_CAPSEL0_Pos (8) /*!< ECAP CTL0: CAPSEL0 Position */
<> 144:ef7eb2e8f9f7 2770 #define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) /*!< ECAP CTL0: CAPSEL0 Mask */
<> 144:ef7eb2e8f9f7 2771
<> 144:ef7eb2e8f9f7 2772 #define ECAP_CTL0_CAPSEL1_Pos (10) /*!< ECAP CTL0: CAPSEL1 Position */
<> 144:ef7eb2e8f9f7 2773 #define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) /*!< ECAP CTL0: CAPSEL1 Mask */
<> 144:ef7eb2e8f9f7 2774
<> 144:ef7eb2e8f9f7 2775 #define ECAP_CTL0_CAPSEL2_Pos (12) /*!< ECAP CTL0: CAPSEL2 Position */
<> 144:ef7eb2e8f9f7 2776 #define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) /*!< ECAP CTL0: CAPSEL2 Mask */
<> 144:ef7eb2e8f9f7 2777
<> 144:ef7eb2e8f9f7 2778 #define ECAP_CTL0_CAPIEN0_Pos (16) /*!< ECAP CTL0: CAPIEN0 Position */
<> 144:ef7eb2e8f9f7 2779 #define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) /*!< ECAP CTL0: CAPIEN0 Mask */
<> 144:ef7eb2e8f9f7 2780
<> 144:ef7eb2e8f9f7 2781 #define ECAP_CTL0_CAPIEN1_Pos (17) /*!< ECAP CTL0: CAPIEN1 Position */
<> 144:ef7eb2e8f9f7 2782 #define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) /*!< ECAP CTL0: CAPIEN1 Mask */
<> 144:ef7eb2e8f9f7 2783
<> 144:ef7eb2e8f9f7 2784 #define ECAP_CTL0_CAPIEN2_Pos (18) /*!< ECAP CTL0: CAPIEN2 Position */
<> 144:ef7eb2e8f9f7 2785 #define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) /*!< ECAP CTL0: CAPIEN2 Mask */
<> 144:ef7eb2e8f9f7 2786
<> 144:ef7eb2e8f9f7 2787 #define ECAP_CTL0_OVIEN_Pos (20) /*!< ECAP CTL0: OVIEN Position */
<> 144:ef7eb2e8f9f7 2788 #define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) /*!< ECAP CTL0: OVIEN Mask */
<> 144:ef7eb2e8f9f7 2789
<> 144:ef7eb2e8f9f7 2790 #define ECAP_CTL0_CMPIEN_Pos (21) /*!< ECAP CTL0: CMPIEN Position */
<> 144:ef7eb2e8f9f7 2791 #define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) /*!< ECAP CTL0: CMPIEN Mask */
<> 144:ef7eb2e8f9f7 2792
<> 144:ef7eb2e8f9f7 2793 #define ECAP_CTL0_CNTEN_Pos (24) /*!< ECAP CTL0: CNTEN Position */
<> 144:ef7eb2e8f9f7 2794 #define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) /*!< ECAP CTL0: CNTEN Mask */
<> 144:ef7eb2e8f9f7 2795
<> 144:ef7eb2e8f9f7 2796 #define ECAP_CTL0_CMPCLR_Pos (25) /*!< ECAP CTL0: CMPCLR Position */
<> 144:ef7eb2e8f9f7 2797 #define ECAP_CTL0_CMPCLR_Msk (0x1ul << ECAP_CTL0_CMPCLR_Pos) /*!< ECAP CTL0: CMPCLR Mask */
<> 144:ef7eb2e8f9f7 2798
<> 144:ef7eb2e8f9f7 2799 #define ECAP_CTL0_CPTCLR_Pos (26) /*!< ECAP CTL0: CPTCLR Position */
<> 144:ef7eb2e8f9f7 2800 #define ECAP_CTL0_CPTCLR_Msk (0x1ul << ECAP_CTL0_CPTCLR_Pos) /*!< ECAP CTL0: CPTCLR Mask */
<> 144:ef7eb2e8f9f7 2801
<> 144:ef7eb2e8f9f7 2802 #define ECAP_CTL0_RLDEN_Pos (27) /*!< ECAP CTL0: RLDEN Position */
<> 144:ef7eb2e8f9f7 2803 #define ECAP_CTL0_RLDEN_Msk (0x1ul << ECAP_CTL0_RLDEN_Pos) /*!< ECAP CTL0: RLDEN Mask */
<> 144:ef7eb2e8f9f7 2804
<> 144:ef7eb2e8f9f7 2805 #define ECAP_CTL0_CMPEN_Pos (28) /*!< ECAP CTL0: CMPEN Position */
<> 144:ef7eb2e8f9f7 2806 #define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) /*!< ECAP CTL0: CMPEN Mask */
<> 144:ef7eb2e8f9f7 2807
<> 144:ef7eb2e8f9f7 2808 #define ECAP_CTL0_CAPEN_Pos (29) /*!< ECAP CTL0: CAPEN Position */
<> 144:ef7eb2e8f9f7 2809 #define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) /*!< ECAP CTL0: CAPEN Mask */
<> 144:ef7eb2e8f9f7 2810
<> 144:ef7eb2e8f9f7 2811 #define ECAP_CTL1_EDGESEL0_Pos (0) /*!< ECAP CTL1: EDGESEL0 Position */
<> 144:ef7eb2e8f9f7 2812 #define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) /*!< ECAP CTL1: EDGESEL0 Mask */
<> 144:ef7eb2e8f9f7 2813
<> 144:ef7eb2e8f9f7 2814 #define ECAP_CTL1_EDGESEL1_Pos (2) /*!< ECAP CTL1: EDGESEL1 Position */
<> 144:ef7eb2e8f9f7 2815 #define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) /*!< ECAP CTL1: EDGESEL1 Mask */
<> 144:ef7eb2e8f9f7 2816
<> 144:ef7eb2e8f9f7 2817 #define ECAP_CTL1_EDGESEL2_Pos (4) /*!< ECAP CTL1: EDGESEL2 Position */
<> 144:ef7eb2e8f9f7 2818 #define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) /*!< ECAP CTL1: EDGESEL2 Mask */
<> 144:ef7eb2e8f9f7 2819
<> 144:ef7eb2e8f9f7 2820 #define ECAP_CTL1_RLDSEL_Pos (8) /*!< ECAP CTL1: RLDSEL Position */
<> 144:ef7eb2e8f9f7 2821 #define ECAP_CTL1_RLDSEL_Msk (0x7ul << ECAP_CTL1_RLDSEL_Pos) /*!< ECAP CTL1: RLDSEL Mask */
<> 144:ef7eb2e8f9f7 2822
<> 144:ef7eb2e8f9f7 2823 #define ECAP_CTL1_CLKSEL_Pos (12) /*!< ECAP CTL1: CLKSEL Position */
<> 144:ef7eb2e8f9f7 2824 #define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) /*!< ECAP CTL1: CLKSEL Mask */
<> 144:ef7eb2e8f9f7 2825
<> 144:ef7eb2e8f9f7 2826 #define ECAP_CTL1_SRCSEL_Pos (16) /*!< ECAP CTL1: SRCSEL Position */
<> 144:ef7eb2e8f9f7 2827 #define ECAP_CTL1_SRCSEL_Msk (0x3ul << ECAP_CTL1_SRCSEL_Pos) /*!< ECAP CTL1: SRCSEL Mask */
<> 144:ef7eb2e8f9f7 2828
<> 144:ef7eb2e8f9f7 2829 #define ECAP_STATUS_CAPF0_Pos (0) /*!< ECAP STATUS: CAPF0 Position */
<> 144:ef7eb2e8f9f7 2830 #define ECAP_STATUS_CAPF0_Msk (0x1ul << ECAP_STATUS_CAPF0_Pos) /*!< ECAP STATUS: CAPF0 Mask */
<> 144:ef7eb2e8f9f7 2831
<> 144:ef7eb2e8f9f7 2832 #define ECAP_STATUS_CAPF1_Pos (1) /*!< ECAP STATUS: CAPF1 Position */
<> 144:ef7eb2e8f9f7 2833 #define ECAP_STATUS_CAPF1_Msk (0x1ul << ECAP_STATUS_CAPF1_Pos) /*!< ECAP STATUS: CAPF1 Mask */
<> 144:ef7eb2e8f9f7 2834
<> 144:ef7eb2e8f9f7 2835 #define ECAP_STATUS_CAPF2_Pos (2) /*!< ECAP STATUS: CAPF2 Position */
<> 144:ef7eb2e8f9f7 2836 #define ECAP_STATUS_CAPF2_Msk (0x1ul << ECAP_STATUS_CAPF2_Pos) /*!< ECAP STATUS: CAPF2 Mask */
<> 144:ef7eb2e8f9f7 2837
<> 144:ef7eb2e8f9f7 2838 #define ECAP_STATUS_CMPF_Pos (4) /*!< ECAP STATUS: CMPF Position */
<> 144:ef7eb2e8f9f7 2839 #define ECAP_STATUS_CMPF_Msk (0x1ul << ECAP_STATUS_CMPF_Pos) /*!< ECAP STATUS: CMPF Mask */
<> 144:ef7eb2e8f9f7 2840
<> 144:ef7eb2e8f9f7 2841 #define ECAP_STATUS_OVF_Pos (5) /*!< ECAP STATUS: OVF Position */
<> 144:ef7eb2e8f9f7 2842 #define ECAP_STATUS_OVF_Msk (0x1ul << ECAP_STATUS_OVF_Pos) /*!< ECAP STATUS: OVF Mask */
<> 144:ef7eb2e8f9f7 2843
<> 144:ef7eb2e8f9f7 2844 /**@}*/ /* ECAP_CONST */
<> 144:ef7eb2e8f9f7 2845 /**@}*/ /* end of ECAP register group */
<> 144:ef7eb2e8f9f7 2846
<> 144:ef7eb2e8f9f7 2847
<> 144:ef7eb2e8f9f7 2848 /*---------------------- System Clock Controller -------------------------*/
<> 144:ef7eb2e8f9f7 2849 /**
<> 144:ef7eb2e8f9f7 2850 @addtogroup CLK System Clock Controller(CLK)
<> 144:ef7eb2e8f9f7 2851 Memory Mapped Structure for CLK Controller
<> 144:ef7eb2e8f9f7 2852 @{ */
<> 144:ef7eb2e8f9f7 2853
<> 144:ef7eb2e8f9f7 2854 typedef struct {
<> 144:ef7eb2e8f9f7 2855
<> 144:ef7eb2e8f9f7 2856
<> 144:ef7eb2e8f9f7 2857 /**
<> 144:ef7eb2e8f9f7 2858 * PWRCTL
<> 144:ef7eb2e8f9f7 2859 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2860 * Offset: 0x00 System Power-down Control Register
<> 144:ef7eb2e8f9f7 2861 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2862 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2863 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2864 * |[0] |HXTEN |4~24 MHz External High-Speed Crystal Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 2865 * | | |The bit default value is set by flash controller user configuration register config0 [26:24].
<> 144:ef7eb2e8f9f7 2866 * | | |When the default clock source is from 4~24 MHz external high-speed crystal, this bit is set to 1 automatically
<> 144:ef7eb2e8f9f7 2867 * | | |0 = HXT Disabled.
<> 144:ef7eb2e8f9f7 2868 * | | |1 = HXT Enabled.
<> 144:ef7eb2e8f9f7 2869 * |[1] |LXTEN |LXT Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 2870 * | | |0 = LXT Disabled.
<> 144:ef7eb2e8f9f7 2871 * | | |1 = LXT (Normal operation) Enabled.
<> 144:ef7eb2e8f9f7 2872 * |[2] |HIRCEN |HIRC Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 2873 * | | |0 = HIRC Disabled.
<> 144:ef7eb2e8f9f7 2874 * | | |1 = HIRC Enabled.
<> 144:ef7eb2e8f9f7 2875 * |[3] |LIRCEN |10 KHz Internal Low-Speed Oscillator Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 2876 * | | |0 = LIRC Disabled.
<> 144:ef7eb2e8f9f7 2877 * | | |1 = LIRC Enabled (default 1).
<> 144:ef7eb2e8f9f7 2878 * |[4] |PDWKDLY |Wake-Up Delay Counter Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 2879 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
<> 144:ef7eb2e8f9f7 2880 * | | |The delayed clock cycle is 4096 clock cycles when chip work at HXT, and 256 clock cycles when chip works at HIRC.
<> 144:ef7eb2e8f9f7 2881 * | | |0 = Clock cycles delay Disabled.
<> 144:ef7eb2e8f9f7 2882 * | | |1 = Clock cycles delay Enabled.
<> 144:ef7eb2e8f9f7 2883 * |[5] |PDWKIEN |Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 2884 * | | |0 = Power-down Mode Wake-up Interrupt Disabled.
<> 144:ef7eb2e8f9f7 2885 * | | |1 = Power-down Mode Wake-up Interrupt Enabled.
<> 144:ef7eb2e8f9f7 2886 * | | |Note: The interrupt will occur when both PDWKIF and PDWKIEN are high.
<> 144:ef7eb2e8f9f7 2887 * |[6] |PDWKIF |Power-Down Mode Wake-Up Interrupt Status
<> 144:ef7eb2e8f9f7 2888 * | | |Set by "power-down wake-up event", it indicates that resume from Power-down mode"
<> 144:ef7eb2e8f9f7 2889 * | | |The flag is set if the GPIO, USB, UART, WDT, CAN, ACMP, BOD, RTC or SDHOST wake-up occurred
<> 144:ef7eb2e8f9f7 2890 * | | |Note1: Write 1 to clear the bit to 0.
<> 144:ef7eb2e8f9f7 2891 * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
<> 144:ef7eb2e8f9f7 2892 * |[7] |PDEN |System Power-Down Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 2893 * | | |When this bit is set to 1, Power-down mode is enabled and chip power-down behavior will depend on the PDEN bit.
<> 144:ef7eb2e8f9f7 2894 * | | |(a) If the PDEN is 0, then the chip enters Power-down mode immediately after
<> 144:ef7eb2e8f9f7 2895 * | | |the PWR_DOWN_EN bit set. ( default)
<> 144:ef7eb2e8f9f7 2896 * | | |(b) if the PDEN is 1, then the chip keeps active till the CPU sleep mode is also
<> 144:ef7eb2e8f9f7 2897 * | | |active and then the chip enters Power-down mode
<> 144:ef7eb2e8f9f7 2898 * | | |When chip wakes up from Power-down mode, this bit is auto cleared. Users need to set
<> 144:ef7eb2e8f9f7 2899 * | | |this bit again for next power-down.
<> 144:ef7eb2e8f9f7 2900 * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but the LXT and
<> 144:ef7eb2e8f9f7 2901 * | | |LIRC are not controlled by Power-down mode.
<> 144:ef7eb2e8f9f7 2902 * | | |In Power-down mode, the PLL and system clock are disabled, and ignored the clock
<> 144:ef7eb2e8f9f7 2903 * | | |source selection. The clocks of peripheral are not controlled by Power-down mode, if the
<> 144:ef7eb2e8f9f7 2904 * | | |peripheral clock source is from LXT or the LIRC.
<> 144:ef7eb2e8f9f7 2905 * | | |0 = Chip operating normally or chip in idle mode by WFI command.
<> 144:ef7eb2e8f9f7 2906 * | | |1 = Chip enters Power-down mode instant or waits CPU sleep command WFI.
<> 144:ef7eb2e8f9f7 2907 * |[8] |PDWTCPU |This Bit Control The Power-Down Entry Condition (Write Protect)
<> 144:ef7eb2e8f9f7 2908 * | | |0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1.
<> 144:ef7eb2e8f9f7 2909 * | | |1 = Chip enters Power-down mode when the both PDEN and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction.
<> 144:ef7eb2e8f9f7 2910 * |[9] |DBPDEN |Chip Entering Power-Down Even ICE Connected
<> 144:ef7eb2e8f9f7 2911 * | | |0 = Chip enters power-down disabled in Debug mode.
<> 144:ef7eb2e8f9f7 2912 * | | |1 = Chip enters power-down enabled in Debug mode.
<> 144:ef7eb2e8f9f7 2913 */
<> 144:ef7eb2e8f9f7 2914 __IO uint32_t PWRCTL;
<> 144:ef7eb2e8f9f7 2915
<> 144:ef7eb2e8f9f7 2916 /**
<> 144:ef7eb2e8f9f7 2917 * AHBCLK
<> 144:ef7eb2e8f9f7 2918 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2919 * Offset: 0x04 AHB Devices Clock Enable Control Register
<> 144:ef7eb2e8f9f7 2920 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2921 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2922 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2923 * |[1] |PDMACKEN |PDMA Controller Clock Enable Control
<> 144:ef7eb2e8f9f7 2924 * | | |0 = PDMA engine clock Disabled.
<> 144:ef7eb2e8f9f7 2925 * | | |1 = PDMA engine clock Enabled.
<> 144:ef7eb2e8f9f7 2926 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Control
<> 144:ef7eb2e8f9f7 2927 * | | |0 = Flash ISP engine clock Disabled.
<> 144:ef7eb2e8f9f7 2928 * | | |1 = Flash ISP engine clock Enabled.
<> 144:ef7eb2e8f9f7 2929 * |[3] |EBICKEN |EBI Controller Clock Enable Control
<> 144:ef7eb2e8f9f7 2930 * | | |0 = EBI engine clock Disabled.
<> 144:ef7eb2e8f9f7 2931 * | | |1 = EBI engine clock Enabled.
<> 144:ef7eb2e8f9f7 2932 * |[4] |USBHCKEN |USB HOST Controller Clock Enable Control
<> 144:ef7eb2e8f9f7 2933 * | | |0 = USB HOST engine clock Disabled.
<> 144:ef7eb2e8f9f7 2934 * | | |1 = USB HOST engine clock Enabled.
<> 144:ef7eb2e8f9f7 2935 * |[5] |EMACCKEN |Ethernet Controller Clock Enable Control (NUC472 Only)
<> 144:ef7eb2e8f9f7 2936 * | | |0 = Ethernet Controller engine clock Disabled.
<> 144:ef7eb2e8f9f7 2937 * | | |1 = Ethernet Controller engine clock Enabled.
<> 144:ef7eb2e8f9f7 2938 * |[6] |SDHCKEN |SDHOST Controller Clock Enable Control
<> 144:ef7eb2e8f9f7 2939 * | | |0 = SDHOST engine clock Disabled.
<> 144:ef7eb2e8f9f7 2940 * | | |1 = SDHOST engine clock Enabled.
<> 144:ef7eb2e8f9f7 2941 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Control
<> 144:ef7eb2e8f9f7 2942 * | | |0 = CRC engine clock Disabled.
<> 144:ef7eb2e8f9f7 2943 * | | |1 = CRC engine clock Enabled.
<> 144:ef7eb2e8f9f7 2944 * |[8] |CAPCKEN |Image Capture Interface Controller Clock Enable Control
<> 144:ef7eb2e8f9f7 2945 * | | |0 = CAP controller's clock Disabled.
<> 144:ef7eb2e8f9f7 2946 * | | |1 = CAP controller's clock Enabled.
<> 144:ef7eb2e8f9f7 2947 * |[9] |SENCKEN |Sensor Clock Enable Control
<> 144:ef7eb2e8f9f7 2948 * | | |0 = Sensor clock Disabled.
<> 144:ef7eb2e8f9f7 2949 * | | |1 = Sensor clock Enabled.
<> 144:ef7eb2e8f9f7 2950 * |[10] |USBDCKEN |USB 2.0 Device Clock Enable Control
<> 144:ef7eb2e8f9f7 2951 * | | |0 = USB device controller's clock Disabled.
<> 144:ef7eb2e8f9f7 2952 * | | |1 = USB device controller's clock Enabled.
<> 144:ef7eb2e8f9f7 2953 * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Control
<> 144:ef7eb2e8f9f7 2954 * | | |0 = Cryptographic Accelerator clock Disabled.
<> 144:ef7eb2e8f9f7 2955 * | | |1 = Cryptographic Accelerator clock Enabled.
<> 144:ef7eb2e8f9f7 2956 */
<> 144:ef7eb2e8f9f7 2957 __IO uint32_t AHBCLK;
<> 144:ef7eb2e8f9f7 2958
<> 144:ef7eb2e8f9f7 2959 /**
<> 144:ef7eb2e8f9f7 2960 * APBCLK0
<> 144:ef7eb2e8f9f7 2961 * ===================================================================================================
<> 144:ef7eb2e8f9f7 2962 * Offset: 0x08 APB Devices Clock Enable Control Register 0
<> 144:ef7eb2e8f9f7 2963 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 2964 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 2965 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 2966 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 2967 * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 2968 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 2969 * | | |0 = Watchdog Timer Clock Disabled.
<> 144:ef7eb2e8f9f7 2970 * | | |1 = Watchdog Timer Clock Enabled.
<> 144:ef7eb2e8f9f7 2971 * |[1] |RTCCKEN |Real-Time-Clock APB Interface Clock Enable Control
<> 144:ef7eb2e8f9f7 2972 * | | |This bit is used to control the RTC APB clock only, The RTC engine clock source is from the 32.768 kHz external low-speed crystal.
<> 144:ef7eb2e8f9f7 2973 * | | |0 = RTC Clock Disabled.
<> 144:ef7eb2e8f9f7 2974 * | | |1 = RTC Clock Enabled.
<> 144:ef7eb2e8f9f7 2975 * |[2] |TMR0CKEN |Timer0 Clock Enable Control
<> 144:ef7eb2e8f9f7 2976 * | | |0 = Timer0 Clock Disabled.
<> 144:ef7eb2e8f9f7 2977 * | | |1 = Timer0 Clock Enabled.
<> 144:ef7eb2e8f9f7 2978 * |[3] |TMR1CKEN |Timer1 Clock Enable Control
<> 144:ef7eb2e8f9f7 2979 * | | |0 = Timer1 Clock Disabled.
<> 144:ef7eb2e8f9f7 2980 * | | |1 = Timer1 Clock Enabled.
<> 144:ef7eb2e8f9f7 2981 * |[4] |TMR2CKEN |Timer2 Clock Enable Control
<> 144:ef7eb2e8f9f7 2982 * | | |0 = Timer2 Clock Disabled.
<> 144:ef7eb2e8f9f7 2983 * | | |1 = Timer2 Clock Enabled.
<> 144:ef7eb2e8f9f7 2984 * |[5] |TMR3CKEN |Timer3 Clock Enable Control
<> 144:ef7eb2e8f9f7 2985 * | | |0 = Timer3 Clock Disabled.
<> 144:ef7eb2e8f9f7 2986 * | | |1 = Timer3 Clock Enabled.
<> 144:ef7eb2e8f9f7 2987 * |[6] |CLKOCKEN |Clock Output Enable Control
<> 144:ef7eb2e8f9f7 2988 * | | |0 = Clock Output Disabled.
<> 144:ef7eb2e8f9f7 2989 * | | |1 = Clock Output Enabled.
<> 144:ef7eb2e8f9f7 2990 * |[7] |ACMPCKEN |Analog Comparator Clock Enable Control
<> 144:ef7eb2e8f9f7 2991 * | | |0 = Analog Comparator Clock Disabled.
<> 144:ef7eb2e8f9f7 2992 * | | |1 = Analog Comparator Clock Enabled.
<> 144:ef7eb2e8f9f7 2993 * |[8] |I2C0CKEN |I2C0 Clock Enable Control
<> 144:ef7eb2e8f9f7 2994 * | | |0 = I2C0 Clock Disabled.
<> 144:ef7eb2e8f9f7 2995 * | | |1 = I2C0 Clock Enabled.
<> 144:ef7eb2e8f9f7 2996 * |[9] |I2C1CKEN |I2C1 Clock Enable Control
<> 144:ef7eb2e8f9f7 2997 * | | |0 = I2C1 Clock Disabled.
<> 144:ef7eb2e8f9f7 2998 * | | |1 = I2C1 Clock Enabled.
<> 144:ef7eb2e8f9f7 2999 * |[10] |I2C2CKEN |I2C2 Clock Enable Control
<> 144:ef7eb2e8f9f7 3000 * | | |0 = I2C2 Clock Disabled.
<> 144:ef7eb2e8f9f7 3001 * | | |1 = I2C2 Clock Enabled.
<> 144:ef7eb2e8f9f7 3002 * |[11] |I2C3CKEN |I2C3 Clock Enable Control
<> 144:ef7eb2e8f9f7 3003 * | | |0 = I2C3 Clock Disabled.
<> 144:ef7eb2e8f9f7 3004 * | | |1 = I2C3 Clock Enabled.
<> 144:ef7eb2e8f9f7 3005 * |[12] |SPI0CKEN |SPI0 Clock Enable Control
<> 144:ef7eb2e8f9f7 3006 * | | |0 = SPI0 Clock Disabled.
<> 144:ef7eb2e8f9f7 3007 * | | |1= SPI0 Clock Enabled.
<> 144:ef7eb2e8f9f7 3008 * |[13] |SPI1CKEN |SPI1 Clock Enable Control
<> 144:ef7eb2e8f9f7 3009 * | | |0 = SPI1 Clock Disabled.
<> 144:ef7eb2e8f9f7 3010 * | | |1 = SPI1 Clock Enabled.
<> 144:ef7eb2e8f9f7 3011 * |[14] |SPI2CKEN |SPI2 Clock Enable Control
<> 144:ef7eb2e8f9f7 3012 * | | |0 = SPI2 Clock Disabled.
<> 144:ef7eb2e8f9f7 3013 * | | |1 = SPI2 Clock Enabled.
<> 144:ef7eb2e8f9f7 3014 * |[15] |SPI3CKEN |SPI3 Clock Enable Control
<> 144:ef7eb2e8f9f7 3015 * | | |0 = SPI3 Clock Disabled.
<> 144:ef7eb2e8f9f7 3016 * | | |1 = SPI3 Clock Enabled.
<> 144:ef7eb2e8f9f7 3017 * |[16] |UART0CKEN |UART0 Clock Enable Control
<> 144:ef7eb2e8f9f7 3018 * | | |0 = UART0 clock Disabled.
<> 144:ef7eb2e8f9f7 3019 * | | |1 = UART0 clock Enabled.
<> 144:ef7eb2e8f9f7 3020 * |[17] |UART1CKEN |UART1 Clock Enable Control
<> 144:ef7eb2e8f9f7 3021 * | | |0 = UART1 clock Disabled.
<> 144:ef7eb2e8f9f7 3022 * | | |1 = UART1 clock Enabled.
<> 144:ef7eb2e8f9f7 3023 * |[18] |UART2CKEN |UART2 Clock Enable Control
<> 144:ef7eb2e8f9f7 3024 * | | |0 = UART2 clock Disabled.
<> 144:ef7eb2e8f9f7 3025 * | | |1 = UART2 clock Enabled.
<> 144:ef7eb2e8f9f7 3026 * |[19] |UART3CKEN |UART3 Clock Enable Control
<> 144:ef7eb2e8f9f7 3027 * | | |0 = UART3 clock Disabled.
<> 144:ef7eb2e8f9f7 3028 * | | |1 = UART3 clock Enabled.
<> 144:ef7eb2e8f9f7 3029 * |[20] |UART4CKEN |UART4 Clock Enable Control
<> 144:ef7eb2e8f9f7 3030 * | | |0 = UART4 clock Disabled.
<> 144:ef7eb2e8f9f7 3031 * | | |1 = UART4 clock Enabled.
<> 144:ef7eb2e8f9f7 3032 * |[21] |UART5CKEN |UART5 Clock Enable Control
<> 144:ef7eb2e8f9f7 3033 * | | |0 = UART5 clock Disabled.
<> 144:ef7eb2e8f9f7 3034 * | | |1 = UART5 clock Enabled.
<> 144:ef7eb2e8f9f7 3035 * |[24] |CAN0CKEN |CAN Bus Controller-0 Clock Enable Control
<> 144:ef7eb2e8f9f7 3036 * | | |0 = CAN0 clock Disabled.
<> 144:ef7eb2e8f9f7 3037 * | | |1 = CAN0 clock Enabled.
<> 144:ef7eb2e8f9f7 3038 * |[25] |CAN1CKEN |CAN Bus Controller-1 Clock Enable Control
<> 144:ef7eb2e8f9f7 3039 * | | |0 = CAN1 clock Disabled.
<> 144:ef7eb2e8f9f7 3040 * | | |1 = CAN1 clock Enabled.
<> 144:ef7eb2e8f9f7 3041 * |[26] |OTGCKEN |USB 2.0 OTG Device Controller Clock Enable Control
<> 144:ef7eb2e8f9f7 3042 * | | |0 = OTG clock Disabled.
<> 144:ef7eb2e8f9f7 3043 * | | |1 = OTG clock Enabled.
<> 144:ef7eb2e8f9f7 3044 * |[28] |ADCCKEN |Analog-Digital-Converter (ADC) Clock Enable Control
<> 144:ef7eb2e8f9f7 3045 * | | |0 = ADC clock Disabled.
<> 144:ef7eb2e8f9f7 3046 * | | |1 = ADC clock Enabled.
<> 144:ef7eb2e8f9f7 3047 * |[29] |I2S0CKEN |I2S0 Clock Enable Control
<> 144:ef7eb2e8f9f7 3048 * | | |0 = I2S Clock Disabled.
<> 144:ef7eb2e8f9f7 3049 * | | |1 = I2S Clock Enabled.
<> 144:ef7eb2e8f9f7 3050 * |[30] |I2S1CKEN |I2S1 Clock Enable Control
<> 144:ef7eb2e8f9f7 3051 * | | |0 = I2S1 Clock Disabled.
<> 144:ef7eb2e8f9f7 3052 * | | |1 = I2S1 Clock Enabled.
<> 144:ef7eb2e8f9f7 3053 * |[31] |PS2CKEN |PS/2 Clock Enable Control
<> 144:ef7eb2e8f9f7 3054 * | | |0 = PS/2 clock Disabled.
<> 144:ef7eb2e8f9f7 3055 * | | |1 = PS/2 clock Enabled.
<> 144:ef7eb2e8f9f7 3056 */
<> 144:ef7eb2e8f9f7 3057 __IO uint32_t APBCLK0;
<> 144:ef7eb2e8f9f7 3058
<> 144:ef7eb2e8f9f7 3059 /**
<> 144:ef7eb2e8f9f7 3060 * APBCLK1
<> 144:ef7eb2e8f9f7 3061 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3062 * Offset: 0x0C APB Devices Clock Enable Control Register 1
<> 144:ef7eb2e8f9f7 3063 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3064 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3065 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3066 * |[0] |SC0CKEN |SC0 Clock Enable Control
<> 144:ef7eb2e8f9f7 3067 * | | |0 = SC0 Clock Disabled.
<> 144:ef7eb2e8f9f7 3068 * | | |1 = SC0 Clock Enabled.
<> 144:ef7eb2e8f9f7 3069 * |[1] |SC1CKEN |SC1 Clock Enable Control
<> 144:ef7eb2e8f9f7 3070 * | | |0 = SC1 Clock Disabled.
<> 144:ef7eb2e8f9f7 3071 * | | |1 = SC1 Clock Enabled.
<> 144:ef7eb2e8f9f7 3072 * |[2] |SC2CKEN |SC2 Clock Enable Control
<> 144:ef7eb2e8f9f7 3073 * | | |0 = SC2 Clock Disabled.
<> 144:ef7eb2e8f9f7 3074 * | | |1 = SC2 Clock Enabled.
<> 144:ef7eb2e8f9f7 3075 * |[3] |SC3CKEN |SC3 Clock Enable Control
<> 144:ef7eb2e8f9f7 3076 * | | |0 = SC3 Clock Disabled.
<> 144:ef7eb2e8f9f7 3077 * | | |1 = SC3 Clock Enabled.
<> 144:ef7eb2e8f9f7 3078 * |[4] |SC4CKEN |SC4 Clock Enable Control
<> 144:ef7eb2e8f9f7 3079 * | | |0 = SC4 Clock Disabled.
<> 144:ef7eb2e8f9f7 3080 * | | |1 = SC4 Clock Enabled.
<> 144:ef7eb2e8f9f7 3081 * |[5] |SC5CKEN |SC5 Clock Enable Control
<> 144:ef7eb2e8f9f7 3082 * | | |0 = SC5 Clock Disabled.
<> 144:ef7eb2e8f9f7 3083 * | | |1 = SC5 Clock Enabled.
<> 144:ef7eb2e8f9f7 3084 * |[8] |I2C4CKEN |I2C4 Clock Enable Control
<> 144:ef7eb2e8f9f7 3085 * | | |0 = I2C4 Clock Disabled.
<> 144:ef7eb2e8f9f7 3086 * | | |1 = I2C4 Clock Enabled.
<> 144:ef7eb2e8f9f7 3087 * |[16] |PWM0CH01CKEN|PWM0_01 Clock Enable Control
<> 144:ef7eb2e8f9f7 3088 * | | |0 = PWM0_01 Clock Disabled.
<> 144:ef7eb2e8f9f7 3089 * | | |1 = PWM0_01 Clock Enabled.
<> 144:ef7eb2e8f9f7 3090 * |[17] |PWM0CH23CKEN|PWM0_23 Clock Enable Control
<> 144:ef7eb2e8f9f7 3091 * | | |0 = PWM0_23 Clock Disabled.
<> 144:ef7eb2e8f9f7 3092 * | | |1 = PWM0_23 Clock Enabled.
<> 144:ef7eb2e8f9f7 3093 * |[18] |PWM0CH45CKEN|PWM0_45 Clock Enable Control
<> 144:ef7eb2e8f9f7 3094 * | | |0 = PWM0_45 Clock Disabled.
<> 144:ef7eb2e8f9f7 3095 * | | |1 = PWM0_45 Clock Enabled.
<> 144:ef7eb2e8f9f7 3096 * |[19] |PWM1CH01CKEN|PWM1_01 Clock Enable Control
<> 144:ef7eb2e8f9f7 3097 * | | |0 = PWM1_01 Clock Disabled.
<> 144:ef7eb2e8f9f7 3098 * | | |1 = PWM1_01 Clock Enabled.
<> 144:ef7eb2e8f9f7 3099 * |[20] |PWM1CH23CKEN|PWM1_23 Clock Enable Control
<> 144:ef7eb2e8f9f7 3100 * | | |0 = PWM1_23 Clock Disabled.
<> 144:ef7eb2e8f9f7 3101 * | | |1 = PWM1_23 Clock Enabled.
<> 144:ef7eb2e8f9f7 3102 * |[21] |PWM1CH45CKEN|PWM1_45 Clock Enable Control
<> 144:ef7eb2e8f9f7 3103 * | | |0 = PWM1_45 Clock Disabled.
<> 144:ef7eb2e8f9f7 3104 * | | |1 = PWM1_45 Clock Enabled.
<> 144:ef7eb2e8f9f7 3105 * |[22] |QEI0CKEN |Quadrature Encoder Interface (QEI0) Clock Enable Control
<> 144:ef7eb2e8f9f7 3106 * | | |0 = QEI0 clock Disabled.
<> 144:ef7eb2e8f9f7 3107 * | | |1 = QEI0 clock Enabled.
<> 144:ef7eb2e8f9f7 3108 * |[23] |QEI1CKEN |Quadrature Encoder Interface (QEI1) Clock Enable Control
<> 144:ef7eb2e8f9f7 3109 * | | |0 = QEI1 clock Disabled.
<> 144:ef7eb2e8f9f7 3110 * | | |1 = QEI1 clock Enabled.
<> 144:ef7eb2e8f9f7 3111 * |[26] |ECAP0CKEN |Enhance CAP (ECAP0) Clock Enable Control
<> 144:ef7eb2e8f9f7 3112 * | | |0 = ECAP0 clock Disabled.
<> 144:ef7eb2e8f9f7 3113 * | | |1 = ECAP0 clock Enabled.
<> 144:ef7eb2e8f9f7 3114 * |[27] |ECAP1CKEN |Enhance CAP (ECAP1) Clock Enable Control
<> 144:ef7eb2e8f9f7 3115 * | | |0 = ECAP1 clock Disabled.
<> 144:ef7eb2e8f9f7 3116 * | | |1 = ECAP1 clock Enabled.
<> 144:ef7eb2e8f9f7 3117 * |[28] |EPWM0CKEN |Enhance PWM0 (EPWM) Clock Enable Control
<> 144:ef7eb2e8f9f7 3118 * | | |0 = EPWM0 clock Disabled.
<> 144:ef7eb2e8f9f7 3119 * | | |1 = EPWM0 clock Enabled.
<> 144:ef7eb2e8f9f7 3120 * |[29] |EPWM1CKEN |Enhance PWM1 (EPWM) Clock Enable Control
<> 144:ef7eb2e8f9f7 3121 * | | |0 = EPWM1 clock Disabled.
<> 144:ef7eb2e8f9f7 3122 * | | |1 = EPWM1 clock Enabled.
<> 144:ef7eb2e8f9f7 3123 * |[30] |OPACKEN |OP Amplifier (OPA) Clock Enable Control
<> 144:ef7eb2e8f9f7 3124 * | | |0 = OPA clock Disabled.
<> 144:ef7eb2e8f9f7 3125 * | | |1 = OPA clock Enabled.
<> 144:ef7eb2e8f9f7 3126 * |[31] |EADCCKEN |Enhance Analog-Digital-Converter (E ADC) Clock Enable Control
<> 144:ef7eb2e8f9f7 3127 * | | |0 = EADC clock Disabled.
<> 144:ef7eb2e8f9f7 3128 * | | |1 = EADC clock Enabled.
<> 144:ef7eb2e8f9f7 3129 */
<> 144:ef7eb2e8f9f7 3130 __IO uint32_t APBCLK1;
<> 144:ef7eb2e8f9f7 3131
<> 144:ef7eb2e8f9f7 3132 /**
<> 144:ef7eb2e8f9f7 3133 * CLKSEL0
<> 144:ef7eb2e8f9f7 3134 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3135 * Offset: 0x10 Clock Source Select Control Register 0
<> 144:ef7eb2e8f9f7 3136 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3137 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3138 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3139 * |[0:2] |HCLKSEL |HCLK Clock Source Selection (Write Protect)
<> 144:ef7eb2e8f9f7 3140 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on
<> 144:ef7eb2e8f9f7 3141 * | | |1.
<> 144:ef7eb2e8f9f7 3142 * | | |The 3-bit default value is reloaded from the value of CFOSC (Config0[26:24]) in user configuration register of Flash controller by any reset.
<> 144:ef7eb2e8f9f7 3143 * | | |Therefore the default value is either 000b or 111b.
<> 144:ef7eb2e8f9f7 3144 * | | |2.
<> 144:ef7eb2e8f9f7 3145 * | | |These bits are protected bit, it means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 3146 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 3147 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3148 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3149 * | | |010 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3150 * | | |011 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3151 * | | |100 = Clock source from PLL2 clock.
<> 144:ef7eb2e8f9f7 3152 * | | |111 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3153 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 3154 * |[3:5] |STCLKSEL |Cortex(TM)-M4 SysTick Clock Source Selection (Write Protect)
<> 144:ef7eb2e8f9f7 3155 * | | |If SYST_CSR[2]=0, SysTick uses listed clock source below.
<> 144:ef7eb2e8f9f7 3156 * | | |These bits are protected bit.
<> 144:ef7eb2e8f9f7 3157 * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 3158 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 3159 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3160 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3161 * | | |010 = Clock source from HXT clock/2.
<> 144:ef7eb2e8f9f7 3162 * | | |011 = Clock source from HCLK/2.
<> 144:ef7eb2e8f9f7 3163 * | | |111 = Clock source from HIRC clock/2.
<> 144:ef7eb2e8f9f7 3164 * |[6] |PCLKSEL |PCLK Clock Source Selection (Write Protect)
<> 144:ef7eb2e8f9f7 3165 * | | |These bits are protected bit.
<> 144:ef7eb2e8f9f7 3166 * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 3167 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 3168 * | | |0 = Clock source from HCLK.
<> 144:ef7eb2e8f9f7 3169 * | | |1 = Clock source from HCLK/2.
<> 144:ef7eb2e8f9f7 3170 * |[8] |USBHSEL |USB Host Clock Source Selection (Write Protect)
<> 144:ef7eb2e8f9f7 3171 * | | |These bits are protected bit.
<> 144:ef7eb2e8f9f7 3172 * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 3173 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 3174 * | | |0 = Clock source from PLL2.
<> 144:ef7eb2e8f9f7 3175 * | | |1 = Clock source from PLL.
<> 144:ef7eb2e8f9f7 3176 * |[16:17] |CAPSEL |Image Capture Interface Clock Source Selection
<> 144:ef7eb2e8f9f7 3177 * | | |These bits are protected bit.
<> 144:ef7eb2e8f9f7 3178 * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 3179 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 3180 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3181 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3182 * | | |10 = Clock source from HCLK.
<> 144:ef7eb2e8f9f7 3183 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3184 * |[20:21] |SDHSEL |SDHOST Engine Clock Source Selection
<> 144:ef7eb2e8f9f7 3185 * | | |These bits are protected bit.
<> 144:ef7eb2e8f9f7 3186 * | | |It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 3187 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 3188 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3189 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3190 * | | |10 = Clock source from HCLK.
<> 144:ef7eb2e8f9f7 3191 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3192 */
<> 144:ef7eb2e8f9f7 3193 __IO uint32_t CLKSEL0;
<> 144:ef7eb2e8f9f7 3194
<> 144:ef7eb2e8f9f7 3195 /**
<> 144:ef7eb2e8f9f7 3196 * CLKSEL1
<> 144:ef7eb2e8f9f7 3197 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3198 * Offset: 0x14 Clock Source Select Control Register 1
<> 144:ef7eb2e8f9f7 3199 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3200 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3201 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3202 * |[0:1] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect)
<> 144:ef7eb2e8f9f7 3203 * | | |These bits are protected bit,and programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 3204 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 3205 * | | |00 = Clock source from 4~24 MHz external high-speed crystal clock.
<> 144:ef7eb2e8f9f7 3206 * | | |01 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3207 * | | |10 = Clock source from HCLK/2048 clock.
<> 144:ef7eb2e8f9f7 3208 * | | |11 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3209 * |[2:3] |EADCSEL |ADC Clock Source Selection
<> 144:ef7eb2e8f9f7 3210 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3211 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3212 * | | |10 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3213 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3214 * |[4] |SPI0SEL |SPI0 Clock Source Selection
<> 144:ef7eb2e8f9f7 3215 * | | |0 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3216 * | | |1 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3217 * |[5] |SPI1SEL |SPI1 Clock Source Selection
<> 144:ef7eb2e8f9f7 3218 * | | |0 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3219 * | | |1 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3220 * |[6] |SPI2SEL |SPI2 Clock Source Selection
<> 144:ef7eb2e8f9f7 3221 * | | |0 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3222 * | | |1 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3223 * |[7] |SPI3SEL |SPI3 Clock Source Selection
<> 144:ef7eb2e8f9f7 3224 * | | |0 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3225 * | | |1 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3226 * |[8:10] |TMR0SEL |TIMER0 Clock Source Selection
<> 144:ef7eb2e8f9f7 3227 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3228 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3229 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3230 * | | |011 = Clock source from external trigger.
<> 144:ef7eb2e8f9f7 3231 * | | |101 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3232 * | | |111 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3233 * | | |Others = reserved.
<> 144:ef7eb2e8f9f7 3234 * |[12:14] |TMR1SEL |TIMER1 Clock Source Selection
<> 144:ef7eb2e8f9f7 3235 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3236 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3237 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3238 * | | |011 = Clock source from external trigger.
<> 144:ef7eb2e8f9f7 3239 * | | |101 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3240 * | | |111 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3241 * | | |Others = reserved.
<> 144:ef7eb2e8f9f7 3242 * |[16:18] |TMR2SEL |TIMER2 Clock Source Selection
<> 144:ef7eb2e8f9f7 3243 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3244 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3245 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3246 * | | |011 = Clock source from external trigger.
<> 144:ef7eb2e8f9f7 3247 * | | |101 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3248 * | | |111 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3249 * | | |Others = reserved.
<> 144:ef7eb2e8f9f7 3250 * |[20:22] |TMR3SEL |TIMER3 Clock Source Selection
<> 144:ef7eb2e8f9f7 3251 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3252 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3253 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3254 * | | |011 = Clock source from external trigger.
<> 144:ef7eb2e8f9f7 3255 * | | |101 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3256 * | | |111 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3257 * | | |Others = reserved.
<> 144:ef7eb2e8f9f7 3258 * |[24:25] |UARTSEL |UART Clock Source Selection
<> 144:ef7eb2e8f9f7 3259 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3260 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3261 * | | |10/11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3262 * |[28:29] |CLKOSEL |Clock Divider Clock Source Selection
<> 144:ef7eb2e8f9f7 3263 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3264 * | | |01 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3265 * | | |10 = Clock source from HCLK.
<> 144:ef7eb2e8f9f7 3266 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3267 * |[30:31] |WWDTSEL |Window Watchdog Timer Clock Source Selection
<> 144:ef7eb2e8f9f7 3268 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 3269 * | | |01 = Reserved.
<> 144:ef7eb2e8f9f7 3270 * | | |10 = Clock source from HCLK/2048 clock.
<> 144:ef7eb2e8f9f7 3271 * | | |11 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3272 */
<> 144:ef7eb2e8f9f7 3273 __IO uint32_t CLKSEL1;
<> 144:ef7eb2e8f9f7 3274
<> 144:ef7eb2e8f9f7 3275 /**
<> 144:ef7eb2e8f9f7 3276 * CLKSEL2
<> 144:ef7eb2e8f9f7 3277 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3278 * Offset: 0x18 Clock Source Select Control Register 2
<> 144:ef7eb2e8f9f7 3279 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3280 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3281 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3282 * |[0:2] |PWM0CH01SEL|PWM0_0 And PWM0_1 Clock Source Selection
<> 144:ef7eb2e8f9f7 3283 * | | |PWM0_0 and PWM0_1 uses the same Engine clock source, both of them use the same prescaler.
<> 144:ef7eb2e8f9f7 3284 * | | |The Engine clock source of PWM0_0 and PWM0_1 is defined by PWM0CH01SEL[2:0].
<> 144:ef7eb2e8f9f7 3285 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3286 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3287 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3288 * | | |011 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3289 * | | |100 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3290 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 3291 * |[4:6] |PPWM0CH23SEL|PWM0_2 And PWM0_3 Clock Source Selection
<> 144:ef7eb2e8f9f7 3292 * | | |PWM0_2 and PWM0_3 uses the same Engine clock source, both of them use the same prescaler.
<> 144:ef7eb2e8f9f7 3293 * | | |The Engine clock source of PWM0_2 and PWM0_3 is defined by PPWM0CH23SEL[2:0].
<> 144:ef7eb2e8f9f7 3294 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3295 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3296 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3297 * | | |011 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3298 * | | |100 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3299 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 3300 * |[8:10] |PWM0CH45SEL|PWM0_4 And PWM0_5 Clock Source Selection
<> 144:ef7eb2e8f9f7 3301 * | | |PWM0_4 and PWM0_5 used the same Engine clock source; both of them use the same prescaler.
<> 144:ef7eb2e8f9f7 3302 * | | |The Engine clock source of PWM0_4 and PWM0_5 is defined by PWM0CH45SEL[2:0].
<> 144:ef7eb2e8f9f7 3303 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3304 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3305 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3306 * | | |011 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3307 * | | |100 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3308 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 3309 * |[12:14] |PWM1CH01SEL|PWM1_0 And PWM1_1 Clock Source Selection
<> 144:ef7eb2e8f9f7 3310 * | | |PWM1_0 and PWM1_1 uses the same Engine clock source, both of them use the same prescaler.
<> 144:ef7eb2e8f9f7 3311 * | | |The Engine clock source of PWM1_0 and PWM1_1 is defined by PWM1CH01SEL[2:0].
<> 144:ef7eb2e8f9f7 3312 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3313 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3314 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3315 * | | |011 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3316 * | | |100 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3317 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 3318 * |[16:18] |PWM1CH23SEL|PWM1_2 And PWM1_3 Clock Source Selection
<> 144:ef7eb2e8f9f7 3319 * | | |PWM1_2 and PWM1_3 uses the same Engine clock source, both of them use the same prescaler.
<> 144:ef7eb2e8f9f7 3320 * | | |The Engine clock source of PWM1_2 and PWM1_3 is defined by PWM1CH23SEL[2:0].
<> 144:ef7eb2e8f9f7 3321 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3322 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3323 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3324 * | | |011 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3325 * | | |100= Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3326 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 3327 * |[20:22] |PWM1CH45SEL|PWM1_4 And PWM1_5 Clock Source Selection
<> 144:ef7eb2e8f9f7 3328 * | | |PWM1_4 and PWM1_5 used the same Engine clock source; both of them use the same prescaler.
<> 144:ef7eb2e8f9f7 3329 * | | |The Engine clock source of PWM1_4 and PWM1_5 is defined by PWM1CH45SEL[2:0].
<> 144:ef7eb2e8f9f7 3330 * | | |000 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3331 * | | |001 = Clock source from LXT clock.
<> 144:ef7eb2e8f9f7 3332 * | | |010 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3333 * | | |011 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3334 * | | |100 = Clock source from LIRC clock.
<> 144:ef7eb2e8f9f7 3335 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 3336 */
<> 144:ef7eb2e8f9f7 3337 __IO uint32_t CLKSEL2;
<> 144:ef7eb2e8f9f7 3338
<> 144:ef7eb2e8f9f7 3339 /**
<> 144:ef7eb2e8f9f7 3340 * CLKSEL3
<> 144:ef7eb2e8f9f7 3341 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3342 * Offset: 0x1C Clock Source Select Control Register 3
<> 144:ef7eb2e8f9f7 3343 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3344 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3345 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3346 * |[0:1] |SC0SEL |SC0 Clock Source Selection
<> 144:ef7eb2e8f9f7 3347 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3348 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3349 * | | |10 = PCLK.
<> 144:ef7eb2e8f9f7 3350 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3351 * |[2:3] |SC1SEL |SC1 Clock Source Selection
<> 144:ef7eb2e8f9f7 3352 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3353 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3354 * | | |10 = PCLK.
<> 144:ef7eb2e8f9f7 3355 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3356 * |[4:5] |SC2SEL |SC2 Clock Source Selection
<> 144:ef7eb2e8f9f7 3357 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3358 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3359 * | | |10 = PCLK.
<> 144:ef7eb2e8f9f7 3360 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3361 * |[6:7] |SC3SEL |SC3 Clock Source Selection
<> 144:ef7eb2e8f9f7 3362 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3363 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3364 * | | |10 = PCLK.
<> 144:ef7eb2e8f9f7 3365 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3366 * |[8:9] |SC4SEL |SC4 Clock Source Selection
<> 144:ef7eb2e8f9f7 3367 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3368 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3369 * | | |10 = PCLK.
<> 144:ef7eb2e8f9f7 3370 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3371 * |[10:11] |SC5SEL |SC5 Clock Source Selection
<> 144:ef7eb2e8f9f7 3372 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3373 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3374 * | | |10 = PCLK.
<> 144:ef7eb2e8f9f7 3375 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3376 * |[16:17] |I2S0SEL |I2S0 Clock Source Selection
<> 144:ef7eb2e8f9f7 3377 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3378 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3379 * | | |10 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3380 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3381 * |[18:19] |I2S1SEL |I2S1 Clock Source Selection
<> 144:ef7eb2e8f9f7 3382 * | | |00 = Clock source from HXT clock.
<> 144:ef7eb2e8f9f7 3383 * | | |01 = Clock source from PLL clock.
<> 144:ef7eb2e8f9f7 3384 * | | |10 = Clock source from PCLK.
<> 144:ef7eb2e8f9f7 3385 * | | |11 = Clock source from HIRC clock.
<> 144:ef7eb2e8f9f7 3386 */
<> 144:ef7eb2e8f9f7 3387 __IO uint32_t CLKSEL3;
<> 144:ef7eb2e8f9f7 3388
<> 144:ef7eb2e8f9f7 3389 /**
<> 144:ef7eb2e8f9f7 3390 * CLKDIV0
<> 144:ef7eb2e8f9f7 3391 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3392 * Offset: 0x20 Clock Divider Number Register 0
<> 144:ef7eb2e8f9f7 3393 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3394 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3395 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3396 * |[0:3] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source
<> 144:ef7eb2e8f9f7 3397 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
<> 144:ef7eb2e8f9f7 3398 * |[4:7] |USBHDIV |USB Host Clock Divide Number From PLL Clock
<> 144:ef7eb2e8f9f7 3399 * | | |USB Host clock frequency = (PLL frequency) / (USBHDIV + 1).
<> 144:ef7eb2e8f9f7 3400 * |[8:11] |UARTDIV |UART Clock Divide Number From UART Clock Source
<> 144:ef7eb2e8f9f7 3401 * | | |UART clock frequency = (UART clock source frequency) / (UARTDIV + 1).
<> 144:ef7eb2e8f9f7 3402 * |[16:23] |ADCDIV |ADC Clock Divide Number From ADC Clock Source
<> 144:ef7eb2e8f9f7 3403 * | | |ADC clock frequency = (ADC clock source frequency) / (ADCDIV + 1).
<> 144:ef7eb2e8f9f7 3404 * |[24:31] |SDHDIV |SDHOST Clock Divide Number From SDHOST Clock Source
<> 144:ef7eb2e8f9f7 3405 * | | |SDHOST clock frequency = (SDHOST clock source frequency) / (SDHDIV + 1).
<> 144:ef7eb2e8f9f7 3406 */
<> 144:ef7eb2e8f9f7 3407 __IO uint32_t CLKDIV0;
<> 144:ef7eb2e8f9f7 3408
<> 144:ef7eb2e8f9f7 3409 /**
<> 144:ef7eb2e8f9f7 3410 * CLKDIV1
<> 144:ef7eb2e8f9f7 3411 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3412 * Offset: 0x24 Clock Divider Number Register 1
<> 144:ef7eb2e8f9f7 3413 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3414 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3415 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3416 * |[0:7] |SC0DIV |SC0 Clock Divide Number From SC0 Clock Source
<> 144:ef7eb2e8f9f7 3417 * | | |SC0 clock frequency = (SC0 clock source frequency ) / (SC0DIV+ 1).
<> 144:ef7eb2e8f9f7 3418 * |[8:15] |SC1DIV |SC1 Clock Divide Number From SC1 Clock Source
<> 144:ef7eb2e8f9f7 3419 * | | |SC1 clock frequency = (SC1 clock source frequency ) / (SC1DIV + 1).
<> 144:ef7eb2e8f9f7 3420 * |[16:23] |SC2DIV |SC2 Clock Divide Number From SC2 Clock Source
<> 144:ef7eb2e8f9f7 3421 * | | |SC2 clock frequency = (SC2 clock source frequency ) / (SC2DIV + 1).
<> 144:ef7eb2e8f9f7 3422 * |[24:31] |SC3DIV |SC3 Clock Divide Number From SC3 Clock Source
<> 144:ef7eb2e8f9f7 3423 * | | |SC3 clock frequency = (SC3 clock source frequency ) / (SC3DIV+ 1).
<> 144:ef7eb2e8f9f7 3424 */
<> 144:ef7eb2e8f9f7 3425 __IO uint32_t CLKDIV1;
<> 144:ef7eb2e8f9f7 3426
<> 144:ef7eb2e8f9f7 3427 /**
<> 144:ef7eb2e8f9f7 3428 * CLKDIV2
<> 144:ef7eb2e8f9f7 3429 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3430 * Offset: 0x28 Clock Divider Number Register 2
<> 144:ef7eb2e8f9f7 3431 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3432 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3433 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3434 * |[0:7] |SC4DIV |SC4 Clock Divide Number From SC4 Clock Source
<> 144:ef7eb2e8f9f7 3435 * | | |SC4 clock frequency = (SC4 clock source frequency ) / (SC4DIV + 1).
<> 144:ef7eb2e8f9f7 3436 * |[8:15] |SC5DIV |SC5 Clock Divide Number From SC5 Clock Source
<> 144:ef7eb2e8f9f7 3437 * | | |SC5 clock frequency = (SC5 clock source frequency ) / (SC5DIV + 1).
<> 144:ef7eb2e8f9f7 3438 */
<> 144:ef7eb2e8f9f7 3439 __IO uint32_t CLKDIV2;
<> 144:ef7eb2e8f9f7 3440
<> 144:ef7eb2e8f9f7 3441 /**
<> 144:ef7eb2e8f9f7 3442 * CLKDIV3
<> 144:ef7eb2e8f9f7 3443 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3444 * Offset: 0x2C Clock Divider Number Register 3
<> 144:ef7eb2e8f9f7 3445 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3446 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3447 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3448 * |[0:7] |CAPDIV |Image Capture Seneor Clock Divide Number From ICAP Clock Source
<> 144:ef7eb2e8f9f7 3449 * | | |Image sensor clock frequency = (ICAP clock source frequency) / (ICAPDIV + 1).
<> 144:ef7eb2e8f9f7 3450 * |[8:15] |VSENSEDIV |Video Pixel Clock Divide Number From ICAP Clock Source
<> 144:ef7eb2e8f9f7 3451 * | | |Video pixel clock frequency = (ICAP clock source frequency) / (VSENSEDIV + 1).
<> 144:ef7eb2e8f9f7 3452 * |[16:23] |EMACDIV |Ethernet Clock Divide Number Form HCLK (NUC472 Only)
<> 144:ef7eb2e8f9f7 3453 * | | |EMAC MDCLK clock frequency = (HCLK) / (EMACDIV + 1).
<> 144:ef7eb2e8f9f7 3454 */
<> 144:ef7eb2e8f9f7 3455 __IO uint32_t CLKDIV3;
<> 144:ef7eb2e8f9f7 3456 uint32_t RESERVE0[4];
<> 144:ef7eb2e8f9f7 3457
<> 144:ef7eb2e8f9f7 3458
<> 144:ef7eb2e8f9f7 3459 /**
<> 144:ef7eb2e8f9f7 3460 * PLLCTL
<> 144:ef7eb2e8f9f7 3461 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3462 * Offset: 0x40 PLL Control Register
<> 144:ef7eb2e8f9f7 3463 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3464 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3465 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3466 * |[0:8] |FBDIV |PLL Feedback Divider Control Pins
<> 144:ef7eb2e8f9f7 3467 * | | |Refer to the formulas below the table.
<> 144:ef7eb2e8f9f7 3468 * |[9:13] |INDIV |PLL Input Divider Control Pins
<> 144:ef7eb2e8f9f7 3469 * | | |Refer to the formulas below the table.
<> 144:ef7eb2e8f9f7 3470 * |[14:15] |OUTDV |PLL Output Divider Control Pins
<> 144:ef7eb2e8f9f7 3471 * | | |Refer to the formulas below the table.
<> 144:ef7eb2e8f9f7 3472 * |[16] |PD |Power-Down Mode
<> 144:ef7eb2e8f9f7 3473 * | | |If set the PWR_DOWN_EN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too.
<> 144:ef7eb2e8f9f7 3474 * | | |0 = PLL is in normal mode.
<> 144:ef7eb2e8f9f7 3475 * | | |1 = PLL is in Power-down mode (default).
<> 144:ef7eb2e8f9f7 3476 * |[17] |BP |PLL Bypass Control
<> 144:ef7eb2e8f9f7 3477 * | | |0 = PLL is in normal mode (default).
<> 144:ef7eb2e8f9f7 3478 * | | |1 = PLL clock output is same as clock input (XTALin).
<> 144:ef7eb2e8f9f7 3479 * |[18] |OE |PLL OE (FOUT Enable) Pin Control
<> 144:ef7eb2e8f9f7 3480 * | | |0 = PLL FOUT Enabled.
<> 144:ef7eb2e8f9f7 3481 * | | |1 = PLL FOUT is fixed low.
<> 144:ef7eb2e8f9f7 3482 * |[19] |PLLSRC |PLL Source Clock Selection
<> 144:ef7eb2e8f9f7 3483 * | | |0 = PLL source clock from HXT.
<> 144:ef7eb2e8f9f7 3484 * | | |1 = PLL source clock from HIRC.
<> 144:ef7eb2e8f9f7 3485 * |[20] |PLLREMAP |PLL Remap Enable Bit
<> 144:ef7eb2e8f9f7 3486 * | | |0 = PLL remap enable.
<> 144:ef7eb2e8f9f7 3487 * | | |1 = PLL remap disable.
<> 144:ef7eb2e8f9f7 3488 */
<> 144:ef7eb2e8f9f7 3489 __IO uint32_t PLLCTL;
<> 144:ef7eb2e8f9f7 3490
<> 144:ef7eb2e8f9f7 3491 /**
<> 144:ef7eb2e8f9f7 3492 * PLL2CTL
<> 144:ef7eb2e8f9f7 3493 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3494 * Offset: 0x44 PLL2 Control Register
<> 144:ef7eb2e8f9f7 3495 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3496 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3497 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3498 * |[0:7] |PLL2DIV |PLL2 Divider Control
<> 144:ef7eb2e8f9f7 3499 * | | |PLL2 clock frequency = (480 MHz) / 2 / (PLL2DIV + 1).
<> 144:ef7eb2e8f9f7 3500 * | | |Note: Max. PLL frequency 240 MHz when XTL12M.
<> 144:ef7eb2e8f9f7 3501 * |[8] |PLL2CKEN |USB OHY 480 MHz Enable Control
<> 144:ef7eb2e8f9f7 3502 * | | |This bit enables USB PHY PLL (480 MHz), and user needs to care extend 12 MHz source.
<> 144:ef7eb2e8f9f7 3503 * | | |0 = USB PHY PLL (480 MHz) Disabled.
<> 144:ef7eb2e8f9f7 3504 * | | |1 = USB PHY PLL (480 MHz) Enabled.
<> 144:ef7eb2e8f9f7 3505 */
<> 144:ef7eb2e8f9f7 3506 __IO uint32_t PLL2CTL;
<> 144:ef7eb2e8f9f7 3507 uint32_t RESERVE1[2];
<> 144:ef7eb2e8f9f7 3508
<> 144:ef7eb2e8f9f7 3509
<> 144:ef7eb2e8f9f7 3510 /**
<> 144:ef7eb2e8f9f7 3511 * STATUS
<> 144:ef7eb2e8f9f7 3512 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3513 * Offset: 0x50 Clock Status Monitor Register
<> 144:ef7eb2e8f9f7 3514 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3515 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3516 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3517 * |[0] |HXTSTB |4~24 MHz External High-Speed Crystal Clock(HXT) Source Stable Flag
<> 144:ef7eb2e8f9f7 3518 * | | |0 = HXT clock is not stable or disabled.
<> 144:ef7eb2e8f9f7 3519 * | | |1 = HXT clock is stable.
<> 144:ef7eb2e8f9f7 3520 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 3521 * |[1] |LXTSTB |32.768 KHz External Low-Speed Crystal Clock(LXT) Source Stable Flag
<> 144:ef7eb2e8f9f7 3522 * | | |0 = LXT clock is not stable or disabled.
<> 144:ef7eb2e8f9f7 3523 * | | |1 = LXT clock is stabled.
<> 144:ef7eb2e8f9f7 3524 * | | |Note: This is read only.
<> 144:ef7eb2e8f9f7 3525 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag
<> 144:ef7eb2e8f9f7 3526 * | | |0 = Internal PLL clock is not stable or disabled.
<> 144:ef7eb2e8f9f7 3527 * | | |1 = Internal PLL clock is stable.
<> 144:ef7eb2e8f9f7 3528 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 3529 * |[3] |LIRCSTB |10 KHz Internal Low-Speed Oscillator Clock (LIRC)Source Stable Flag
<> 144:ef7eb2e8f9f7 3530 * | | |0 = LIRC clock is not stable or disabled.
<> 144:ef7eb2e8f9f7 3531 * | | |1 = LIRC clock is stable.
<> 144:ef7eb2e8f9f7 3532 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 3533 * |[4] |HIRCSTB |22.1184 MHz Internal High-Speed Oscillator Clock (HIRC) Clock Source Stable Flag
<> 144:ef7eb2e8f9f7 3534 * | | |0 = HIRC clock is not stable or disabled.
<> 144:ef7eb2e8f9f7 3535 * | | |1 = HIRC clock is stable.
<> 144:ef7eb2e8f9f7 3536 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 3537 * |[5] |PLL2STB |Internal PLL2 Clock Source Stable Flag
<> 144:ef7eb2e8f9f7 3538 * | | |0 = Internal PLL2 clock is not stable or disabled.
<> 144:ef7eb2e8f9f7 3539 * | | |1 = Internal PLL2 clock is stable.
<> 144:ef7eb2e8f9f7 3540 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 3541 * |[7] |CLKSFAIL |Clock Switching Fail Flag
<> 144:ef7eb2e8f9f7 3542 * | | |0 = Clock switching success.
<> 144:ef7eb2e8f9f7 3543 * | | |1 = Clock switching failure.
<> 144:ef7eb2e8f9f7 3544 * | | |Note1: This bit is updated when software switches system clock source.
<> 144:ef7eb2e8f9f7 3545 * | | |If switch target clock is stable, this bit will be set to 0.
<> 144:ef7eb2e8f9f7 3546 * | | |If switch target clock is not stable, this bit will be set to 1.
<> 144:ef7eb2e8f9f7 3547 * | | |Note2: Write 1 to clear the bit to 0.
<> 144:ef7eb2e8f9f7 3548 */
<> 144:ef7eb2e8f9f7 3549 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 3550 uint32_t RESERVE2[3];
<> 144:ef7eb2e8f9f7 3551
<> 144:ef7eb2e8f9f7 3552
<> 144:ef7eb2e8f9f7 3553 /**
<> 144:ef7eb2e8f9f7 3554 * CLKOCTL
<> 144:ef7eb2e8f9f7 3555 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3556 * Offset: 0x60 Frequency Divider Control Register
<> 144:ef7eb2e8f9f7 3557 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3558 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3559 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3560 * |[0:3] |FSEL |Divider Output Frequency Selection
<> 144:ef7eb2e8f9f7 3561 * | | |The formula of output frequency is:
<> 144:ef7eb2e8f9f7 3562 * | | |Fout = Fin/2(N+1).
<> 144:ef7eb2e8f9f7 3563 * | | |Fin is the input clock frequency.
<> 144:ef7eb2e8f9f7 3564 * | | |Fout is the frequency of divider output clock.
<> 144:ef7eb2e8f9f7 3565 * | | |N is the 4-bit value of FSEL[3:0].
<> 144:ef7eb2e8f9f7 3566 * |[4] |CLKOEN |Clock Output Enable Control
<> 144:ef7eb2e8f9f7 3567 * | | |0 = Clock Output disabled.
<> 144:ef7eb2e8f9f7 3568 * | | |1 = Clock Output enabled.
<> 144:ef7eb2e8f9f7 3569 * |[5] |DIV1EN |Frequency Divider 1 Enable Control
<> 144:ef7eb2e8f9f7 3570 * | | |0 = Divider output frequency is dependent on FSEL value when FDIVEN is enabled.
<> 144:ef7eb2e8f9f7 3571 * | | |1 = Divider output frequency is input clock frequency.
<> 144:ef7eb2e8f9f7 3572 */
<> 144:ef7eb2e8f9f7 3573 __IO uint32_t CLKOCTL;
<> 144:ef7eb2e8f9f7 3574 uint32_t RESERVE3[3];
<> 144:ef7eb2e8f9f7 3575
<> 144:ef7eb2e8f9f7 3576
<> 144:ef7eb2e8f9f7 3577 /**
<> 144:ef7eb2e8f9f7 3578 * CLKDCTL
<> 144:ef7eb2e8f9f7 3579 * ===================================================================================================
<> 144:ef7eb2e8f9f7 3580 * Offset: 0x70 Clock Fail Detector Control Register
<> 144:ef7eb2e8f9f7 3581 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 3582 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 3583 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 3584 * |[0] |SYSFDEN |System Clock Detector Enable Control
<> 144:ef7eb2e8f9f7 3585 * | | |0 = system clock fail interrupt disabled.
<> 144:ef7eb2e8f9f7 3586 * | | |1 = system clock fail interrupt enabled.
<> 144:ef7eb2e8f9f7 3587 * |[1] |SYSFIEN |System Clock Detector Interrupt Enable Control
<> 144:ef7eb2e8f9f7 3588 * | | |0 = system clock fail interrupt disabled.
<> 144:ef7eb2e8f9f7 3589 * | | |1 = system clock fail interrupt enabled.
<> 144:ef7eb2e8f9f7 3590 * |[2] |SYSFIF |System Clock Detect Fail Flag
<> 144:ef7eb2e8f9f7 3591 * | | |0 = System clock normal.
<> 144:ef7eb2e8f9f7 3592 * | | |1 = System clock abnormal (write " 1" to clear).
<> 144:ef7eb2e8f9f7 3593 * |[8] |IRCDEN |Internal RC Clock Detector Enable Control
<> 144:ef7eb2e8f9f7 3594 * | | |0 = IRC clock fail interrupt disabled.
<> 144:ef7eb2e8f9f7 3595 * | | |1 = IRC clock fail interrupt enabled.
<> 144:ef7eb2e8f9f7 3596 * |[9] |IRCFIEN |Internal RC Clock Detector Interrupt Enable Control
<> 144:ef7eb2e8f9f7 3597 * | | |0 = IRC clock fail interrupt disabled.
<> 144:ef7eb2e8f9f7 3598 * | | |1 = IRC clock fail interrupt enabled.
<> 144:ef7eb2e8f9f7 3599 * |[10] |IRCFIF |Internal RC Clock Fail Flag
<> 144:ef7eb2e8f9f7 3600 * | | |0 = IRC clock normal.
<> 144:ef7eb2e8f9f7 3601 * | | |1 = IRC abnormal (write "1" to clear) .
<> 144:ef7eb2e8f9f7 3602 */
<> 144:ef7eb2e8f9f7 3603 __IO uint32_t CLKDCTL;
<> 144:ef7eb2e8f9f7 3604
<> 144:ef7eb2e8f9f7 3605 } CLK_T;
<> 144:ef7eb2e8f9f7 3606
<> 144:ef7eb2e8f9f7 3607 /**
<> 144:ef7eb2e8f9f7 3608 @addtogroup CLK_CONST CLK Bit Field Definition
<> 144:ef7eb2e8f9f7 3609 Constant Definitions for CLK Controller
<> 144:ef7eb2e8f9f7 3610 @{ */
<> 144:ef7eb2e8f9f7 3611
<> 144:ef7eb2e8f9f7 3612 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK PWRCTL: HXTEN Position */
<> 144:ef7eb2e8f9f7 3613 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK PWRCTL: HXTEN Mask */
<> 144:ef7eb2e8f9f7 3614
<> 144:ef7eb2e8f9f7 3615 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK PWRCTL: LXTEN Position */
<> 144:ef7eb2e8f9f7 3616 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK PWRCTL: LXTEN Mask */
<> 144:ef7eb2e8f9f7 3617
<> 144:ef7eb2e8f9f7 3618 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK PWRCTL: HIRCEN Position */
<> 144:ef7eb2e8f9f7 3619 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK PWRCTL: HIRCEN Mask */
<> 144:ef7eb2e8f9f7 3620
<> 144:ef7eb2e8f9f7 3621 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK PWRCTL: LIRCEN Position */
<> 144:ef7eb2e8f9f7 3622 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK PWRCTL: LIRCEN Mask */
<> 144:ef7eb2e8f9f7 3623
<> 144:ef7eb2e8f9f7 3624 #define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK PWRCTL: PDWKDLY Position */
<> 144:ef7eb2e8f9f7 3625 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK PWRCTL: PDWKDLY Mask */
<> 144:ef7eb2e8f9f7 3626
<> 144:ef7eb2e8f9f7 3627 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK PWRCTL: PDWKIEN Position */
<> 144:ef7eb2e8f9f7 3628 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK PWRCTL: PDWKIEN Mask */
<> 144:ef7eb2e8f9f7 3629
<> 144:ef7eb2e8f9f7 3630 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK PWRCTL: PDWKIF Position */
<> 144:ef7eb2e8f9f7 3631 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK PWRCTL: PDWKIF Mask */
<> 144:ef7eb2e8f9f7 3632
<> 144:ef7eb2e8f9f7 3633 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK PWRCTL: PDEN Position */
<> 144:ef7eb2e8f9f7 3634 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK PWRCTL: PDEN Mask */
<> 144:ef7eb2e8f9f7 3635
<> 144:ef7eb2e8f9f7 3636 #define CLK_PWRCTL_PDWTCPU_Pos (8) /*!< CLK PWRCTL: PDWTCPU Position */
<> 144:ef7eb2e8f9f7 3637 #define CLK_PWRCTL_PDWTCPU_Msk (0x1ul << CLK_PWRCTL_PDWTCPU_Pos) /*!< CLK PWRCTL: PDWTCPU Mask */
<> 144:ef7eb2e8f9f7 3638
<> 144:ef7eb2e8f9f7 3639 #define CLK_PWRCTL_DBPDEN_Pos (9) /*!< CLK PWRCTL: DBPDEN Position */
<> 144:ef7eb2e8f9f7 3640 #define CLK_PWRCTL_DBPDEN_Msk (0x1ul << CLK_PWRCTL_DBPDEN_Pos) /*!< CLK PWRCTL: DBPDEN Mask */
<> 144:ef7eb2e8f9f7 3641
<> 144:ef7eb2e8f9f7 3642 #define CLK_AHBCLK_PDMACKEN_Pos (1) /*!< CLK AHBCLK: PDMACKEN Position */
<> 144:ef7eb2e8f9f7 3643 #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) /*!< CLK AHBCLK: PDMACKEN Mask */
<> 144:ef7eb2e8f9f7 3644
<> 144:ef7eb2e8f9f7 3645 #define CLK_AHBCLK_ISPCKEN_Pos (2) /*!< CLK AHBCLK: ISPCKEN Position */
<> 144:ef7eb2e8f9f7 3646 #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) /*!< CLK AHBCLK: ISPCKEN Mask */
<> 144:ef7eb2e8f9f7 3647
<> 144:ef7eb2e8f9f7 3648 #define CLK_AHBCLK_EBICKEN_Pos (3) /*!< CLK AHBCLK: EBICKEN Position */
<> 144:ef7eb2e8f9f7 3649 #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) /*!< CLK AHBCLK: EBICKEN Mask */
<> 144:ef7eb2e8f9f7 3650
<> 144:ef7eb2e8f9f7 3651 #define CLK_AHBCLK_USBHCKEN_Pos (4) /*!< CLK AHBCLK: USBHCKEN Position */
<> 144:ef7eb2e8f9f7 3652 #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) /*!< CLK AHBCLK: USBHCKEN Mask */
<> 144:ef7eb2e8f9f7 3653
<> 144:ef7eb2e8f9f7 3654 #define CLK_AHBCLK_EMACCKEN_Pos (5) /*!< CLK AHBCLK: EMACCKEN Position */
<> 144:ef7eb2e8f9f7 3655 #define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) /*!< CLK AHBCLK: EMACCKEN Mask */
<> 144:ef7eb2e8f9f7 3656
<> 144:ef7eb2e8f9f7 3657 #define CLK_AHBCLK_SDHCKEN_Pos (6) /*!< CLK AHBCLK: SDHCKEN Position */
<> 144:ef7eb2e8f9f7 3658 #define CLK_AHBCLK_SDHCKEN_Msk (0x1ul << CLK_AHBCLK_SDHCKEN_Pos) /*!< CLK AHBCLK: SDHCKEN Mask */
<> 144:ef7eb2e8f9f7 3659
<> 144:ef7eb2e8f9f7 3660 #define CLK_AHBCLK_CRCCKEN_Pos (7) /*!< CLK AHBCLK: CRCCKEN Position */
<> 144:ef7eb2e8f9f7 3661 #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) /*!< CLK AHBCLK: CRCCKEN Mask */
<> 144:ef7eb2e8f9f7 3662
<> 144:ef7eb2e8f9f7 3663 #define CLK_AHBCLK_CAPCKEN_Pos (8) /*!< CLK AHBCLK: CAPCKEN Position */
<> 144:ef7eb2e8f9f7 3664 #define CLK_AHBCLK_CAPCKEN_Msk (0x1ul << CLK_AHBCLK_CAPCKEN_Pos) /*!< CLK AHBCLK: CAPCKEN Mask */
<> 144:ef7eb2e8f9f7 3665
<> 144:ef7eb2e8f9f7 3666 #define CLK_AHBCLK_SENCKEN_Pos (9) /*!< CLK AHBCLK: SENCKEN Position */
<> 144:ef7eb2e8f9f7 3667 #define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) /*!< CLK AHBCLK: SENCKEN Mask */
<> 144:ef7eb2e8f9f7 3668
<> 144:ef7eb2e8f9f7 3669 #define CLK_AHBCLK_USBDCKEN_Pos (10) /*!< CLK AHBCLK: USBDCKEN Position */
<> 144:ef7eb2e8f9f7 3670 #define CLK_AHBCLK_USBDCKEN_Msk (0x1ul << CLK_AHBCLK_USBDCKEN_Pos) /*!< CLK AHBCLK: USBDCKEN Mask */
<> 144:ef7eb2e8f9f7 3671
<> 144:ef7eb2e8f9f7 3672 #define CLK_AHBCLK_CRPTCKEN_Pos (12) /*!< CLK AHBCLK: CRPTCKEN Position */
<> 144:ef7eb2e8f9f7 3673 #define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) /*!< CLK AHBCLK: CRPTCKEN Mask */
<> 144:ef7eb2e8f9f7 3674
<> 144:ef7eb2e8f9f7 3675 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK APBCLK0: WDTCKEN Position */
<> 144:ef7eb2e8f9f7 3676 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK APBCLK0: WDTCKEN Mask */
<> 144:ef7eb2e8f9f7 3677
<> 144:ef7eb2e8f9f7 3678 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK APBCLK0: RTCCKEN Position */
<> 144:ef7eb2e8f9f7 3679 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK APBCLK0: RTCCKEN Mask */
<> 144:ef7eb2e8f9f7 3680
<> 144:ef7eb2e8f9f7 3681 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK APBCLK0: TMR0CKEN Position */
<> 144:ef7eb2e8f9f7 3682 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK APBCLK0: TMR0CKEN Mask */
<> 144:ef7eb2e8f9f7 3683
<> 144:ef7eb2e8f9f7 3684 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK APBCLK0: TMR1CKEN Position */
<> 144:ef7eb2e8f9f7 3685 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK APBCLK0: TMR1CKEN Mask */
<> 144:ef7eb2e8f9f7 3686
<> 144:ef7eb2e8f9f7 3687 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK APBCLK0: TMR2CKEN Position */
<> 144:ef7eb2e8f9f7 3688 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK APBCLK0: TMR2CKEN Mask */
<> 144:ef7eb2e8f9f7 3689
<> 144:ef7eb2e8f9f7 3690 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK APBCLK0: TMR3CKEN Position */
<> 144:ef7eb2e8f9f7 3691 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK APBCLK0: TMR3CKEN Mask */
<> 144:ef7eb2e8f9f7 3692
<> 144:ef7eb2e8f9f7 3693 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK APBCLK0: CLKOCKEN Position */
<> 144:ef7eb2e8f9f7 3694 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK APBCLK0: CLKOCKEN Mask */
<> 144:ef7eb2e8f9f7 3695
<> 144:ef7eb2e8f9f7 3696 #define CLK_APBCLK0_ACMPCKEN_Pos (7) /*!< CLK APBCLK0: ACMPCKEN Position */
<> 144:ef7eb2e8f9f7 3697 #define CLK_APBCLK0_ACMPCKEN_Msk (0x1ul << CLK_APBCLK0_ACMPCKEN_Pos) /*!< CLK APBCLK0: ACMPCKEN Mask */
<> 144:ef7eb2e8f9f7 3698
<> 144:ef7eb2e8f9f7 3699 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK APBCLK0: I2C0CKEN Position */
<> 144:ef7eb2e8f9f7 3700 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK APBCLK0: I2C0CKEN Mask */
<> 144:ef7eb2e8f9f7 3701
<> 144:ef7eb2e8f9f7 3702 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK APBCLK0: I2C1CKEN Position */
<> 144:ef7eb2e8f9f7 3703 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK APBCLK0: I2C1CKEN Mask */
<> 144:ef7eb2e8f9f7 3704
<> 144:ef7eb2e8f9f7 3705 #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK APBCLK0: I2C2CKEN Position */
<> 144:ef7eb2e8f9f7 3706 #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK APBCLK0: I2C2CKEN Mask */
<> 144:ef7eb2e8f9f7 3707
<> 144:ef7eb2e8f9f7 3708 #define CLK_APBCLK0_I2C3CKEN_Pos (11) /*!< CLK APBCLK0: I2C3CKEN Position */
<> 144:ef7eb2e8f9f7 3709 #define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) /*!< CLK APBCLK0: I2C3CKEN Mask */
<> 144:ef7eb2e8f9f7 3710
<> 144:ef7eb2e8f9f7 3711 #define CLK_APBCLK0_SPI0CKEN_Pos (12) /*!< CLK APBCLK0: SPI0CKEN Position */
<> 144:ef7eb2e8f9f7 3712 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK APBCLK0: SPI0CKEN Mask */
<> 144:ef7eb2e8f9f7 3713
<> 144:ef7eb2e8f9f7 3714 #define CLK_APBCLK0_SPI1CKEN_Pos (13) /*!< CLK APBCLK0: SPI1CKEN Position */
<> 144:ef7eb2e8f9f7 3715 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK APBCLK0: SPI1CKEN Mask */
<> 144:ef7eb2e8f9f7 3716
<> 144:ef7eb2e8f9f7 3717 #define CLK_APBCLK0_SPI2CKEN_Pos (14) /*!< CLK APBCLK0: SPI2CKEN Position */
<> 144:ef7eb2e8f9f7 3718 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK APBCLK0: SPI2CKEN Mask */
<> 144:ef7eb2e8f9f7 3719
<> 144:ef7eb2e8f9f7 3720 #define CLK_APBCLK0_SPI3CKEN_Pos (15) /*!< CLK APBCLK0: SPI3CKEN Position */
<> 144:ef7eb2e8f9f7 3721 #define CLK_APBCLK0_SPI3CKEN_Msk (0x1ul << CLK_APBCLK0_SPI3CKEN_Pos) /*!< CLK APBCLK0: SPI3CKEN Mask */
<> 144:ef7eb2e8f9f7 3722
<> 144:ef7eb2e8f9f7 3723 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK APBCLK0: UART0CKEN Position */
<> 144:ef7eb2e8f9f7 3724 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK APBCLK0: UART0CKEN Mask */
<> 144:ef7eb2e8f9f7 3725
<> 144:ef7eb2e8f9f7 3726 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK APBCLK0: UART1CKEN Position */
<> 144:ef7eb2e8f9f7 3727 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK APBCLK0: UART1CKEN Mask */
<> 144:ef7eb2e8f9f7 3728
<> 144:ef7eb2e8f9f7 3729 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK APBCLK0: UART2CKEN Position */
<> 144:ef7eb2e8f9f7 3730 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK APBCLK0: UART2CKEN Mask */
<> 144:ef7eb2e8f9f7 3731
<> 144:ef7eb2e8f9f7 3732 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK APBCLK0: UART3CKEN Position */
<> 144:ef7eb2e8f9f7 3733 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK APBCLK0: UART3CKEN Mask */
<> 144:ef7eb2e8f9f7 3734
<> 144:ef7eb2e8f9f7 3735 #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK APBCLK0: UART4CKEN Position */
<> 144:ef7eb2e8f9f7 3736 #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK APBCLK0: UART4CKEN Mask */
<> 144:ef7eb2e8f9f7 3737
<> 144:ef7eb2e8f9f7 3738 #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK APBCLK0: UART5CKEN Position */
<> 144:ef7eb2e8f9f7 3739 #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK APBCLK0: UART5CKEN Mask */
<> 144:ef7eb2e8f9f7 3740
<> 144:ef7eb2e8f9f7 3741 #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK APBCLK0: CAN0CKEN Position */
<> 144:ef7eb2e8f9f7 3742 #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK APBCLK0: CAN0CKEN Mask */
<> 144:ef7eb2e8f9f7 3743
<> 144:ef7eb2e8f9f7 3744 #define CLK_APBCLK0_CAN1CKEN_Pos (25) /*!< CLK APBCLK0: CAN1CKEN Position */
<> 144:ef7eb2e8f9f7 3745 #define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) /*!< CLK APBCLK0: CAN1CKEN Mask */
<> 144:ef7eb2e8f9f7 3746
<> 144:ef7eb2e8f9f7 3747 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK APBCLK0: OTGCKEN Position */
<> 144:ef7eb2e8f9f7 3748 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK APBCLK0: OTGCKEN Mask */
<> 144:ef7eb2e8f9f7 3749
<> 144:ef7eb2e8f9f7 3750 #define CLK_APBCLK0_ADCCKEN_Pos (28) /*!< CLK APBCLK0: ADCCKEN Position */
<> 144:ef7eb2e8f9f7 3751 #define CLK_APBCLK0_ADCCKEN_Msk (0x1ul << CLK_APBCLK0_ADCCKEN_Pos) /*!< CLK APBCLK0: ADCCKEN Mask */
<> 144:ef7eb2e8f9f7 3752
<> 144:ef7eb2e8f9f7 3753 #define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK APBCLK0: I2S0CKEN Position */
<> 144:ef7eb2e8f9f7 3754 #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK APBCLK0: I2S0CKEN Mask */
<> 144:ef7eb2e8f9f7 3755
<> 144:ef7eb2e8f9f7 3756 #define CLK_APBCLK0_I2S1CKEN_Pos (30) /*!< CLK APBCLK0: I2S1CKEN Position */
<> 144:ef7eb2e8f9f7 3757 #define CLK_APBCLK0_I2S1CKEN_Msk (0x1ul << CLK_APBCLK0_I2S1CKEN_Pos) /*!< CLK APBCLK0: I2S1CKEN Mask */
<> 144:ef7eb2e8f9f7 3758
<> 144:ef7eb2e8f9f7 3759 #define CLK_APBCLK0_PS2CKEN_Pos (31) /*!< CLK APBCLK0: PS2CKEN Position */
<> 144:ef7eb2e8f9f7 3760 #define CLK_APBCLK0_PS2CKEN_Msk (0x1ul << CLK_APBCLK0_PS2CKEN_Pos) /*!< CLK APBCLK0: PS2CKEN Mask */
<> 144:ef7eb2e8f9f7 3761
<> 144:ef7eb2e8f9f7 3762 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK APBCLK1: SC0CKEN Position */
<> 144:ef7eb2e8f9f7 3763 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK APBCLK1: SC0CKEN Mask */
<> 144:ef7eb2e8f9f7 3764
<> 144:ef7eb2e8f9f7 3765 #define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK APBCLK1: SC1CKEN Position */
<> 144:ef7eb2e8f9f7 3766 #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK APBCLK1: SC1CKEN Mask */
<> 144:ef7eb2e8f9f7 3767
<> 144:ef7eb2e8f9f7 3768 #define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK APBCLK1: SC2CKEN Position */
<> 144:ef7eb2e8f9f7 3769 #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK APBCLK1: SC2CKEN Mask */
<> 144:ef7eb2e8f9f7 3770
<> 144:ef7eb2e8f9f7 3771 #define CLK_APBCLK1_SC3CKEN_Pos (3) /*!< CLK APBCLK1: SC3CKEN Position */
<> 144:ef7eb2e8f9f7 3772 #define CLK_APBCLK1_SC3CKEN_Msk (0x1ul << CLK_APBCLK1_SC3CKEN_Pos) /*!< CLK APBCLK1: SC3CKEN Mask */
<> 144:ef7eb2e8f9f7 3773
<> 144:ef7eb2e8f9f7 3774 #define CLK_APBCLK1_SC4CKEN_Pos (4) /*!< CLK APBCLK1: SC4CKEN Position */
<> 144:ef7eb2e8f9f7 3775 #define CLK_APBCLK1_SC4CKEN_Msk (0x1ul << CLK_APBCLK1_SC4CKEN_Pos) /*!< CLK APBCLK1: SC4CKEN Mask */
<> 144:ef7eb2e8f9f7 3776
<> 144:ef7eb2e8f9f7 3777 #define CLK_APBCLK1_SC5CKEN_Pos (5) /*!< CLK APBCLK1: SC5CKEN Position */
<> 144:ef7eb2e8f9f7 3778 #define CLK_APBCLK1_SC5CKEN_Msk (0x1ul << CLK_APBCLK1_SC5CKEN_Pos) /*!< CLK APBCLK1: SC5CKEN Mask */
<> 144:ef7eb2e8f9f7 3779
<> 144:ef7eb2e8f9f7 3780 #define CLK_APBCLK1_I2C4CKEN_Pos (8) /*!< CLK APBCLK1: I2C4CKEN Position */
<> 144:ef7eb2e8f9f7 3781 #define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) /*!< CLK APBCLK1: I2C4CKEN Mask */
<> 144:ef7eb2e8f9f7 3782
<> 144:ef7eb2e8f9f7 3783 #define CLK_APBCLK1_PWM0CH01CKEN_Pos (16) /*!< CLK APBCLK1: PWM0CH01CKEN Position */
<> 144:ef7eb2e8f9f7 3784 #define CLK_APBCLK1_PWM0CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH01CKEN_Pos) /*!< CLK APBCLK1: PWM0CH01CKEN Mask */
<> 144:ef7eb2e8f9f7 3785
<> 144:ef7eb2e8f9f7 3786 #define CLK_APBCLK1_PWM0CH23CKEN_Pos (17) /*!< CLK APBCLK1: PWM0CH23CKEN Position */
<> 144:ef7eb2e8f9f7 3787 #define CLK_APBCLK1_PWM0CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH23CKEN_Pos) /*!< CLK APBCLK1: PWM0CH23CKEN Mask */
<> 144:ef7eb2e8f9f7 3788
<> 144:ef7eb2e8f9f7 3789 #define CLK_APBCLK1_PWM0CH45CKEN_Pos (18) /*!< CLK APBCLK1: PWM0CH45CKEN Position */
<> 144:ef7eb2e8f9f7 3790 #define CLK_APBCLK1_PWM0CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM0CH45CKEN_Pos) /*!< CLK APBCLK1: PWM0CH45CKEN Mask */
<> 144:ef7eb2e8f9f7 3791
<> 144:ef7eb2e8f9f7 3792 #define CLK_APBCLK1_PWM1CH01CKEN_Pos (19) /*!< CLK APBCLK1: PWM1CH01CKEN Position */
<> 144:ef7eb2e8f9f7 3793 #define CLK_APBCLK1_PWM1CH01CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH01CKEN_Pos) /*!< CLK APBCLK1: PWM1CH01CKEN Mask */
<> 144:ef7eb2e8f9f7 3794
<> 144:ef7eb2e8f9f7 3795 #define CLK_APBCLK1_PWM1CH23CKEN_Pos (20) /*!< CLK APBCLK1: PWM1CH23CKEN Position */
<> 144:ef7eb2e8f9f7 3796 #define CLK_APBCLK1_PWM1CH23CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH23CKEN_Pos) /*!< CLK APBCLK1: PWM1CH23CKEN Mask */
<> 144:ef7eb2e8f9f7 3797
<> 144:ef7eb2e8f9f7 3798 #define CLK_APBCLK1_PWM1CH45CKEN_Pos (21) /*!< CLK APBCLK1: PWM1CH45CKEN Position */
<> 144:ef7eb2e8f9f7 3799 #define CLK_APBCLK1_PWM1CH45CKEN_Msk (0x1ul << CLK_APBCLK1_PWM1CH45CKEN_Pos) /*!< CLK APBCLK1: PWM1CH45CKEN Mask */
<> 144:ef7eb2e8f9f7 3800
<> 144:ef7eb2e8f9f7 3801 #define CLK_APBCLK1_QEI0CKEN_Pos (22) /*!< CLK APBCLK1: QEI0CKEN Position */
<> 144:ef7eb2e8f9f7 3802 #define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) /*!< CLK APBCLK1: QEI0CKEN Mask */
<> 144:ef7eb2e8f9f7 3803
<> 144:ef7eb2e8f9f7 3804 #define CLK_APBCLK1_QEI1CKEN_Pos (23) /*!< CLK APBCLK1: QEI1CKEN Position */
<> 144:ef7eb2e8f9f7 3805 #define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) /*!< CLK APBCLK1: QEI1CKEN Mask */
<> 144:ef7eb2e8f9f7 3806
<> 144:ef7eb2e8f9f7 3807 #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK APBCLK1: ECAP0CKEN Position */
<> 144:ef7eb2e8f9f7 3808 #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK APBCLK1: ECAP0CKEN Mask */
<> 144:ef7eb2e8f9f7 3809
<> 144:ef7eb2e8f9f7 3810 #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK APBCLK1: ECAP1CKEN Position */
<> 144:ef7eb2e8f9f7 3811 #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK APBCLK1: ECAP1CKEN Mask */
<> 144:ef7eb2e8f9f7 3812
<> 144:ef7eb2e8f9f7 3813 #define CLK_APBCLK1_EPWM0CKEN_Pos (28) /*!< CLK APBCLK1: EPWM0CKEN Position */
<> 144:ef7eb2e8f9f7 3814 #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK APBCLK1: EPWM0CKEN Mask */
<> 144:ef7eb2e8f9f7 3815
<> 144:ef7eb2e8f9f7 3816 #define CLK_APBCLK1_EPWM1CKEN_Pos (29) /*!< CLK APBCLK1: EPWM1CKEN Position */
<> 144:ef7eb2e8f9f7 3817 #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK APBCLK1: EPWM1CKEN Mask */
<> 144:ef7eb2e8f9f7 3818
<> 144:ef7eb2e8f9f7 3819 #define CLK_APBCLK1_OPACKEN_Pos (30) /*!< CLK APBCLK1: OPACKEN Position */
<> 144:ef7eb2e8f9f7 3820 #define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) /*!< CLK APBCLK1: OPACKEN Mask */
<> 144:ef7eb2e8f9f7 3821
<> 144:ef7eb2e8f9f7 3822 #define CLK_APBCLK1_EADCCKEN_Pos (31) /*!< CLK APBCLK1: EADCCKEN Position */
<> 144:ef7eb2e8f9f7 3823 #define CLK_APBCLK1_EADCCKEN_Msk (0x1ul << CLK_APBCLK1_EADCCKEN_Pos) /*!< CLK APBCLK1: EADCCKEN Mask */
<> 144:ef7eb2e8f9f7 3824
<> 144:ef7eb2e8f9f7 3825 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK CLKSEL0: HCLKSEL Position */
<> 144:ef7eb2e8f9f7 3826 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK CLKSEL0: HCLKSEL Mask */
<> 144:ef7eb2e8f9f7 3827
<> 144:ef7eb2e8f9f7 3828 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK CLKSEL0: STCLKSEL Position */
<> 144:ef7eb2e8f9f7 3829 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK CLKSEL0: STCLKSEL Mask */
<> 144:ef7eb2e8f9f7 3830
<> 144:ef7eb2e8f9f7 3831 #define CLK_CLKSEL0_PCLKSEL_Pos (6) /*!< CLK CLKSEL0: PCLKSEL Position */
<> 144:ef7eb2e8f9f7 3832 #define CLK_CLKSEL0_PCLKSEL_Msk (0x1ul << CLK_CLKSEL0_PCLKSEL_Pos) /*!< CLK CLKSEL0: PCLKSEL Mask */
<> 144:ef7eb2e8f9f7 3833
<> 144:ef7eb2e8f9f7 3834 #define CLK_CLKSEL0_USBHSEL_Pos (8) /*!< CLK CLKSEL0: USBHSEL Position */
<> 144:ef7eb2e8f9f7 3835 #define CLK_CLKSEL0_USBHSEL_Msk (0x1ul << CLK_CLKSEL0_USBHSEL_Pos) /*!< CLK CLKSEL0: USBHSEL Mask */
<> 144:ef7eb2e8f9f7 3836
<> 144:ef7eb2e8f9f7 3837 #define CLK_CLKSEL0_CAPSEL_Pos (16) /*!< CLK CLKSEL0: CAPSEL Position */
<> 144:ef7eb2e8f9f7 3838 #define CLK_CLKSEL0_CAPSEL_Msk (0x3ul << CLK_CLKSEL0_CAPSEL_Pos) /*!< CLK CLKSEL0: CAPSEL Mask */
<> 144:ef7eb2e8f9f7 3839
<> 144:ef7eb2e8f9f7 3840 #define CLK_CLKSEL0_SDHSEL_Pos (20) /*!< CLK CLKSEL0: SDHSEL Position */
<> 144:ef7eb2e8f9f7 3841 #define CLK_CLKSEL0_SDHSEL_Msk (0x3ul << CLK_CLKSEL0_SDHSEL_Pos) /*!< CLK CLKSEL0: SDHSEL Mask */
<> 144:ef7eb2e8f9f7 3842
<> 144:ef7eb2e8f9f7 3843 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK CLKSEL1: WDTSEL Position */
<> 144:ef7eb2e8f9f7 3844 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK CLKSEL1: WDTSEL Mask */
<> 144:ef7eb2e8f9f7 3845
<> 144:ef7eb2e8f9f7 3846 #define CLK_CLKSEL1_ADCSEL_Pos (2) /*!< CLK CLKSEL1: ADCSEL Position */
<> 144:ef7eb2e8f9f7 3847 #define CLK_CLKSEL1_ADCSEL_Msk (0x3ul << CLK_CLKSEL1_ADCSEL_Pos) /*!< CLK CLKSEL1: ADCSEL Mask */
<> 144:ef7eb2e8f9f7 3848
<> 144:ef7eb2e8f9f7 3849 #define CLK_CLKSEL1_SPI0SEL_Pos (4) /*!< CLK CLKSEL1: SPI0SEL Position */
<> 144:ef7eb2e8f9f7 3850 #define CLK_CLKSEL1_SPI0SEL_Msk (0x1ul << CLK_CLKSEL1_SPI0SEL_Pos) /*!< CLK CLKSEL1: SPI0SEL Mask */
<> 144:ef7eb2e8f9f7 3851
<> 144:ef7eb2e8f9f7 3852 #define CLK_CLKSEL1_SPI1SEL_Pos (5) /*!< CLK CLKSEL1: SPI1SEL Position */
<> 144:ef7eb2e8f9f7 3853 #define CLK_CLKSEL1_SPI1SEL_Msk (0x1ul << CLK_CLKSEL1_SPI1SEL_Pos) /*!< CLK CLKSEL1: SPI1SEL Mask */
<> 144:ef7eb2e8f9f7 3854
<> 144:ef7eb2e8f9f7 3855 #define CLK_CLKSEL1_SPI2SEL_Pos (6) /*!< CLK CLKSEL1: SPI2SEL Position */
<> 144:ef7eb2e8f9f7 3856 #define CLK_CLKSEL1_SPI2SEL_Msk (0x1ul << CLK_CLKSEL1_SPI2SEL_Pos) /*!< CLK CLKSEL1: SPI2SEL Mask */
<> 144:ef7eb2e8f9f7 3857
<> 144:ef7eb2e8f9f7 3858 #define CLK_CLKSEL1_SPI3SEL_Pos (7) /*!< CLK CLKSEL1: SPI3SEL Position */
<> 144:ef7eb2e8f9f7 3859 #define CLK_CLKSEL1_SPI3SEL_Msk (0x1ul << CLK_CLKSEL1_SPI3SEL_Pos) /*!< CLK CLKSEL1: SPI3SEL Mask */
<> 144:ef7eb2e8f9f7 3860
<> 144:ef7eb2e8f9f7 3861 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK CLKSEL1: TMR0SEL Position */
<> 144:ef7eb2e8f9f7 3862 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK CLKSEL1: TMR0SEL Mask */
<> 144:ef7eb2e8f9f7 3863
<> 144:ef7eb2e8f9f7 3864 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK CLKSEL1: TMR1SEL Position */
<> 144:ef7eb2e8f9f7 3865 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK CLKSEL1: TMR1SEL Mask */
<> 144:ef7eb2e8f9f7 3866
<> 144:ef7eb2e8f9f7 3867 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK CLKSEL1: TMR2SEL Position */
<> 144:ef7eb2e8f9f7 3868 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK CLKSEL1: TMR2SEL Mask */
<> 144:ef7eb2e8f9f7 3869
<> 144:ef7eb2e8f9f7 3870 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK CLKSEL1: TMR3SEL Position */
<> 144:ef7eb2e8f9f7 3871 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK CLKSEL1: TMR3SEL Mask */
<> 144:ef7eb2e8f9f7 3872
<> 144:ef7eb2e8f9f7 3873 #define CLK_CLKSEL1_UARTSEL_Pos (24) /*!< CLK CLKSEL1: UARTSEL Position */
<> 144:ef7eb2e8f9f7 3874 #define CLK_CLKSEL1_UARTSEL_Msk (0x3ul << CLK_CLKSEL1_UARTSEL_Pos) /*!< CLK CLKSEL1: UARTSEL Mask */
<> 144:ef7eb2e8f9f7 3875
<> 144:ef7eb2e8f9f7 3876 #define CLK_CLKSEL1_CLKOSEL_Pos (28) /*!< CLK CLKSEL1: CLKOSEL Position */
<> 144:ef7eb2e8f9f7 3877 #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK CLKSEL1: CLKOSEL Mask */
<> 144:ef7eb2e8f9f7 3878
<> 144:ef7eb2e8f9f7 3879 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK CLKSEL1: WWDTSEL Position */
<> 144:ef7eb2e8f9f7 3880 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK CLKSEL1: WWDTSEL Mask */
<> 144:ef7eb2e8f9f7 3881
<> 144:ef7eb2e8f9f7 3882 #define CLK_CLKSEL2_PWM0CH01SEL_Pos (0) /*!< CLK CLKSEL2: PWM0CH01SEL Position */
<> 144:ef7eb2e8f9f7 3883 #define CLK_CLKSEL2_PWM0CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH01SEL_Pos) /*!< CLK CLKSEL2: PWM0CH01SEL Mask */
<> 144:ef7eb2e8f9f7 3884
<> 144:ef7eb2e8f9f7 3885 #define CLK_CLKSEL2_PWM0CH23SEL_Pos (4) /*!< CLK CLKSEL2: PWM0CH23SEL Position */
<> 144:ef7eb2e8f9f7 3886 #define CLK_CLKSEL2_PWM0CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH23SEL_Pos) /*!< CLK CLKSEL2: PWM0CH23SEL Mask */
<> 144:ef7eb2e8f9f7 3887
<> 144:ef7eb2e8f9f7 3888 #define CLK_CLKSEL2_PWM0CH45SEL_Pos (8) /*!< CLK CLKSEL2: PWM0CH45SEL Position */
<> 144:ef7eb2e8f9f7 3889 #define CLK_CLKSEL2_PWM0CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM0CH45SEL_Pos) /*!< CLK CLKSEL2: PWM0CH45SEL Mask */
<> 144:ef7eb2e8f9f7 3890
<> 144:ef7eb2e8f9f7 3891 #define CLK_CLKSEL2_PWM1CH01SEL_Pos (12) /*!< CLK CLKSEL2: PWM1CH01SEL Position */
<> 144:ef7eb2e8f9f7 3892 #define CLK_CLKSEL2_PWM1CH01SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH01SEL_Pos) /*!< CLK CLKSEL2: PWM1CH01SEL Mask */
<> 144:ef7eb2e8f9f7 3893
<> 144:ef7eb2e8f9f7 3894 #define CLK_CLKSEL2_PWM1CH23SEL_Pos (16) /*!< CLK CLKSEL2: PWM1CH23SEL Position */
<> 144:ef7eb2e8f9f7 3895 #define CLK_CLKSEL2_PWM1CH23SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH23SEL_Pos) /*!< CLK CLKSEL2: PWM1CH23SEL Mask */
<> 144:ef7eb2e8f9f7 3896
<> 144:ef7eb2e8f9f7 3897 #define CLK_CLKSEL2_PWM1CH45SEL_Pos (20) /*!< CLK CLKSEL2: PWM1CH45SEL Position */
<> 144:ef7eb2e8f9f7 3898 #define CLK_CLKSEL2_PWM1CH45SEL_Msk (0x7ul << CLK_CLKSEL2_PWM1CH45SEL_Pos) /*!< CLK CLKSEL2: PWM1CH45SEL Mask */
<> 144:ef7eb2e8f9f7 3899
<> 144:ef7eb2e8f9f7 3900 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK CLKSEL3: SC0SEL Position */
<> 144:ef7eb2e8f9f7 3901 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK CLKSEL3: SC0SEL Mask */
<> 144:ef7eb2e8f9f7 3902
<> 144:ef7eb2e8f9f7 3903 #define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK CLKSEL3: SC1SEL Position */
<> 144:ef7eb2e8f9f7 3904 #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK CLKSEL3: SC1SEL Mask */
<> 144:ef7eb2e8f9f7 3905
<> 144:ef7eb2e8f9f7 3906 #define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK CLKSEL3: SC2SEL Position */
<> 144:ef7eb2e8f9f7 3907 #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK CLKSEL3: SC2SEL Mask */
<> 144:ef7eb2e8f9f7 3908
<> 144:ef7eb2e8f9f7 3909 #define CLK_CLKSEL3_SC3SEL_Pos (6) /*!< CLK CLKSEL3: SC3SEL Position */
<> 144:ef7eb2e8f9f7 3910 #define CLK_CLKSEL3_SC3SEL_Msk (0x3ul << CLK_CLKSEL3_SC3SEL_Pos) /*!< CLK CLKSEL3: SC3SEL Mask */
<> 144:ef7eb2e8f9f7 3911
<> 144:ef7eb2e8f9f7 3912 #define CLK_CLKSEL3_SC4SEL_Pos (8) /*!< CLK CLKSEL3: SC4SEL Position */
<> 144:ef7eb2e8f9f7 3913 #define CLK_CLKSEL3_SC4SEL_Msk (0x3ul << CLK_CLKSEL3_SC4SEL_Pos) /*!< CLK CLKSEL3: SC4SEL Mask */
<> 144:ef7eb2e8f9f7 3914
<> 144:ef7eb2e8f9f7 3915 #define CLK_CLKSEL3_SC5SEL_Pos (10) /*!< CLK CLKSEL3: SC5SEL Position */
<> 144:ef7eb2e8f9f7 3916 #define CLK_CLKSEL3_SC5SEL_Msk (0x3ul << CLK_CLKSEL3_SC5SEL_Pos) /*!< CLK CLKSEL3: SC5SEL Mask */
<> 144:ef7eb2e8f9f7 3917
<> 144:ef7eb2e8f9f7 3918 #define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK CLKSEL3: I2S0SEL Position */
<> 144:ef7eb2e8f9f7 3919 #define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK CLKSEL3: I2S0SEL Mask */
<> 144:ef7eb2e8f9f7 3920
<> 144:ef7eb2e8f9f7 3921 #define CLK_CLKSEL3_I2S1SEL_Pos (18) /*!< CLK CLKSEL3: I2S1SEL Position */
<> 144:ef7eb2e8f9f7 3922 #define CLK_CLKSEL3_I2S1SEL_Msk (0x3ul << CLK_CLKSEL3_I2S1SEL_Pos) /*!< CLK CLKSEL3: I2S1SEL Mask */
<> 144:ef7eb2e8f9f7 3923
<> 144:ef7eb2e8f9f7 3924 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK CLKDIV0: HCLKDIV Position */
<> 144:ef7eb2e8f9f7 3925 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK CLKDIV0: HCLKDIV Mask */
<> 144:ef7eb2e8f9f7 3926
<> 144:ef7eb2e8f9f7 3927 #define CLK_CLKDIV0_USBHDIV_Pos (4) /*!< CLK CLKDIV0: USBHDIV Position */
<> 144:ef7eb2e8f9f7 3928 #define CLK_CLKDIV0_USBHDIV_Msk (0xful << CLK_CLKDIV0_USBHDIV_Pos) /*!< CLK CLKDIV0: USBHDIV Mask */
<> 144:ef7eb2e8f9f7 3929
<> 144:ef7eb2e8f9f7 3930 #define CLK_CLKDIV0_UARTDIV_Pos (8) /*!< CLK CLKDIV0: UARTDIV Position */
<> 144:ef7eb2e8f9f7 3931 #define CLK_CLKDIV0_UARTDIV_Msk (0xful << CLK_CLKDIV0_UARTDIV_Pos) /*!< CLK CLKDIV0: UARTDIV Mask */
<> 144:ef7eb2e8f9f7 3932
<> 144:ef7eb2e8f9f7 3933 #define CLK_CLKDIV0_ADCDIV_Pos (16) /*!< CLK CLKDIV0: ADCDIV Position */
<> 144:ef7eb2e8f9f7 3934 #define CLK_CLKDIV0_ADCDIV_Msk (0xfful << CLK_CLKDIV0_ADCDIV_Pos) /*!< CLK CLKDIV0: ADCDIV Mask */
<> 144:ef7eb2e8f9f7 3935
<> 144:ef7eb2e8f9f7 3936 #define CLK_CLKDIV0_SDHDIV_Pos (24) /*!< CLK CLKDIV0: SDHDIV Position */
<> 144:ef7eb2e8f9f7 3937 #define CLK_CLKDIV0_SDHDIV_Msk (0xfful << CLK_CLKDIV0_SDHDIV_Pos) /*!< CLK CLKDIV0: SDHDIV Mask */
<> 144:ef7eb2e8f9f7 3938
<> 144:ef7eb2e8f9f7 3939 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK CLKDIV1: SC0DIV Position */
<> 144:ef7eb2e8f9f7 3940 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK CLKDIV1: SC0DIV Mask */
<> 144:ef7eb2e8f9f7 3941
<> 144:ef7eb2e8f9f7 3942 #define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK CLKDIV1: SC1DIV Position */
<> 144:ef7eb2e8f9f7 3943 #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK CLKDIV1: SC1DIV Mask */
<> 144:ef7eb2e8f9f7 3944
<> 144:ef7eb2e8f9f7 3945 #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK CLKDIV1: SC2DIV Position */
<> 144:ef7eb2e8f9f7 3946 #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK CLKDIV1: SC2DIV Mask */
<> 144:ef7eb2e8f9f7 3947
<> 144:ef7eb2e8f9f7 3948 #define CLK_CLKDIV1_SC3DIV_Pos (24) /*!< CLK CLKDIV1: SC3DIV Position */
<> 144:ef7eb2e8f9f7 3949 #define CLK_CLKDIV1_SC3DIV_Msk (0xfful << CLK_CLKDIV1_SC3DIV_Pos) /*!< CLK CLKDIV1: SC3DIV Mask */
<> 144:ef7eb2e8f9f7 3950
<> 144:ef7eb2e8f9f7 3951 #define CLK_CLKDIV2_SC4DIV_Pos (0) /*!< CLK CLKDIV2: SC4DIV Position */
<> 144:ef7eb2e8f9f7 3952 #define CLK_CLKDIV2_SC4DIV_Msk (0xfful << CLK_CLKDIV2_SC4DIV_Pos) /*!< CLK CLKDIV2: SC4DIV Mask */
<> 144:ef7eb2e8f9f7 3953
<> 144:ef7eb2e8f9f7 3954 #define CLK_CLKDIV2_SC5DIV_Pos (8) /*!< CLK CLKDIV2: SC5DIV Position */
<> 144:ef7eb2e8f9f7 3955 #define CLK_CLKDIV2_SC5DIV_Msk (0xfful << CLK_CLKDIV2_SC5DIV_Pos) /*!< CLK CLKDIV2: SC5DIV Mask */
<> 144:ef7eb2e8f9f7 3956
<> 144:ef7eb2e8f9f7 3957 #define CLK_CLKDIV3_CAPDIV_Pos (0) /*!< CLK CLKDIV3: CAPDIV Position */
<> 144:ef7eb2e8f9f7 3958 #define CLK_CLKDIV3_CAPDIV_Msk (0xfful << CLK_CLKDIV3_CAPDIV_Pos) /*!< CLK CLKDIV3: CAPDIV Mask */
<> 144:ef7eb2e8f9f7 3959
<> 144:ef7eb2e8f9f7 3960 #define CLK_CLKDIV3_VSENSEDIV_Pos (8) /*!< CLK CLKDIV3: VSENSEDIV Position */
<> 144:ef7eb2e8f9f7 3961 #define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLK CLKDIV3: VSENSEDIV Mask */
<> 144:ef7eb2e8f9f7 3962
<> 144:ef7eb2e8f9f7 3963 #define CLK_CLKDIV3_EMACDIV_Pos (16) /*!< CLK CLKDIV3: EMACDIV Position */
<> 144:ef7eb2e8f9f7 3964 #define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) /*!< CLK CLKDIV3: EMACDIV Mask */
<> 144:ef7eb2e8f9f7 3965
<> 144:ef7eb2e8f9f7 3966 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK PLLCTL: FBDIV Position */
<> 144:ef7eb2e8f9f7 3967 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK PLLCTL: FBDIV Mask */
<> 144:ef7eb2e8f9f7 3968
<> 144:ef7eb2e8f9f7 3969 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK PLLCTL: INDIV Position */
<> 144:ef7eb2e8f9f7 3970 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK PLLCTL: INDIV Mask */
<> 144:ef7eb2e8f9f7 3971
<> 144:ef7eb2e8f9f7 3972 #define CLK_PLLCTL_OUTDV_Pos (14) /*!< CLK PLLCTL: OUTDV Position */
<> 144:ef7eb2e8f9f7 3973 #define CLK_PLLCTL_OUTDV_Msk (0x3ul << CLK_PLLCTL_OUTDV_Pos) /*!< CLK PLLCTL: OUTDV Mask */
<> 144:ef7eb2e8f9f7 3974
<> 144:ef7eb2e8f9f7 3975 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK PLLCTL: PD Position */
<> 144:ef7eb2e8f9f7 3976 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK PLLCTL: PD Mask */
<> 144:ef7eb2e8f9f7 3977
<> 144:ef7eb2e8f9f7 3978 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK PLLCTL: BP Position */
<> 144:ef7eb2e8f9f7 3979 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK PLLCTL: BP Mask */
<> 144:ef7eb2e8f9f7 3980
<> 144:ef7eb2e8f9f7 3981 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK PLLCTL: OE Position */
<> 144:ef7eb2e8f9f7 3982 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK PLLCTL: OE Mask */
<> 144:ef7eb2e8f9f7 3983
<> 144:ef7eb2e8f9f7 3984 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK PLLCTL: PLLSRC Position */
<> 144:ef7eb2e8f9f7 3985 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK PLLCTL: PLLSRC Mask */
<> 144:ef7eb2e8f9f7 3986
<> 144:ef7eb2e8f9f7 3987 #define CLK_PLLCTL_PLLREMAP_Pos (20) /*!< CLK PLLCTL: PLLREMAP Position */
<> 144:ef7eb2e8f9f7 3988 #define CLK_PLLCTL_PLLREMAP_Msk (0x1ul << CLK_PLLCTL_PLLREMAP_Pos) /*!< CLK PLLCTL: PLLREMAP Mask */
<> 144:ef7eb2e8f9f7 3989
<> 144:ef7eb2e8f9f7 3990 #define CLK_PLL2CTL_PLL2DIV_Pos (0) /*!< CLK PLL2CTL: PLL2DIV Position */
<> 144:ef7eb2e8f9f7 3991 #define CLK_PLL2CTL_PLL2DIV_Msk (0xfful << CLK_PLL2CTL_PLL2DIV_Pos) /*!< CLK PLL2CTL: PLL2DIV Mask */
<> 144:ef7eb2e8f9f7 3992
<> 144:ef7eb2e8f9f7 3993 #define CLK_PLL2CTL_PLL2CKEN_Pos (8) /*!< CLK PLL2CTL: PLL2CKEN Position */
<> 144:ef7eb2e8f9f7 3994 #define CLK_PLL2CTL_PLL2CKEN_Msk (0x1ul << CLK_PLL2CTL_PLL2CKEN_Pos) /*!< CLK PLL2CTL: PLL2CKEN Mask */
<> 144:ef7eb2e8f9f7 3995
<> 144:ef7eb2e8f9f7 3996 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK STATUS: HXTSTB Position */
<> 144:ef7eb2e8f9f7 3997 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK STATUS: HXTSTB Mask */
<> 144:ef7eb2e8f9f7 3998
<> 144:ef7eb2e8f9f7 3999 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK STATUS: LXTSTB Position */
<> 144:ef7eb2e8f9f7 4000 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK STATUS: LXTSTB Mask */
<> 144:ef7eb2e8f9f7 4001
<> 144:ef7eb2e8f9f7 4002 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK STATUS: PLLSTB Position */
<> 144:ef7eb2e8f9f7 4003 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK STATUS: PLLSTB Mask */
<> 144:ef7eb2e8f9f7 4004
<> 144:ef7eb2e8f9f7 4005 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK STATUS: LIRCSTB Position */
<> 144:ef7eb2e8f9f7 4006 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK STATUS: LIRCSTB Mask */
<> 144:ef7eb2e8f9f7 4007
<> 144:ef7eb2e8f9f7 4008 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK STATUS: HIRCSTB Position */
<> 144:ef7eb2e8f9f7 4009 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK STATUS: HIRCSTB Mask */
<> 144:ef7eb2e8f9f7 4010
<> 144:ef7eb2e8f9f7 4011 #define CLK_STATUS_PLL2STB_Pos (5) /*!< CLK STATUS: PLL2STB Position */
<> 144:ef7eb2e8f9f7 4012 #define CLK_STATUS_PLL2STB_Msk (0x1ul << CLK_STATUS_PLL2STB_Pos) /*!< CLK STATUS: PLL2STB Mask */
<> 144:ef7eb2e8f9f7 4013
<> 144:ef7eb2e8f9f7 4014 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK STATUS: CLKSFAIL Position */
<> 144:ef7eb2e8f9f7 4015 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK STATUS: CLKSFAIL Mask */
<> 144:ef7eb2e8f9f7 4016
<> 144:ef7eb2e8f9f7 4017 #define CLK_CLKOCTL_FSEL_Pos (0) /*!< CLK CLKOCTL: FSEL Position */
<> 144:ef7eb2e8f9f7 4018 #define CLK_CLKOCTL_FSEL_Msk (0xful << CLK_CLKOCTL_FSEL_Pos) /*!< CLK CLKOCTL: FSEL Mask */
<> 144:ef7eb2e8f9f7 4019
<> 144:ef7eb2e8f9f7 4020 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK CLKOCTL: CLKOEN Position */
<> 144:ef7eb2e8f9f7 4021 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK CLKOCTL: CLKOEN Mask */
<> 144:ef7eb2e8f9f7 4022
<> 144:ef7eb2e8f9f7 4023 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK CLKOCTL: DIV1EN Position */
<> 144:ef7eb2e8f9f7 4024 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK CLKOCTL: DIV1EN Mask */
<> 144:ef7eb2e8f9f7 4025
<> 144:ef7eb2e8f9f7 4026 #define CLK_CLKDCTL_SYSFDEN_Pos (0) /*!< CLK CLKDCTL: SYSFDEN Position */
<> 144:ef7eb2e8f9f7 4027 #define CLK_CLKDCTL_SYSFDEN_Msk (0x1ul << CLK_CLKDCTL_SYSFDEN_Pos) /*!< CLK CLKDCTL: SYSFDEN Mask */
<> 144:ef7eb2e8f9f7 4028
<> 144:ef7eb2e8f9f7 4029 #define CLK_CLKDCTL_SYSFIEN_Pos (1) /*!< CLK CLKDCTL: SYSFIEN Position */
<> 144:ef7eb2e8f9f7 4030 #define CLK_CLKDCTL_SYSFIEN_Msk (0x1ul << CLK_CLKDCTL_SYSFIEN_Pos) /*!< CLK CLKDCTL: SYSFIEN Mask */
<> 144:ef7eb2e8f9f7 4031
<> 144:ef7eb2e8f9f7 4032 #define CLK_CLKDCTL_SYSFIF_Pos (2) /*!< CLK CLKDCTL: SYSFIF Position */
<> 144:ef7eb2e8f9f7 4033 #define CLK_CLKDCTL_SYSFIF_Msk (0x1ul << CLK_CLKDCTL_SYSFIF_Pos) /*!< CLK CLKDCTL: SYSFIF Mask */
<> 144:ef7eb2e8f9f7 4034
<> 144:ef7eb2e8f9f7 4035 #define CLK_CLKDCTL_IRCDEN_Pos (8) /*!< CLK CLKDCTL: IRCDEN Position */
<> 144:ef7eb2e8f9f7 4036 #define CLK_CLKDCTL_IRCDEN_Msk (0x1ul << CLK_CLKDCTL_IRCDEN_Pos) /*!< CLK CLKDCTL: IRCDEN Mask */
<> 144:ef7eb2e8f9f7 4037
<> 144:ef7eb2e8f9f7 4038 #define CLK_CLKDCTL_IRCFIEN_Pos (9) /*!< CLK CLKDCTL: IRCFIEN Position */
<> 144:ef7eb2e8f9f7 4039 #define CLK_CLKDCTL_IRCFIEN_Msk (0x1ul << CLK_CLKDCTL_IRCFIEN_Pos) /*!< CLK CLKDCTL: IRCFIEN Mask */
<> 144:ef7eb2e8f9f7 4040
<> 144:ef7eb2e8f9f7 4041 #define CLK_CLKDCTL_IRCFIF_Pos (10) /*!< CLK CLKDCTL: IRCFIF Position */
<> 144:ef7eb2e8f9f7 4042 #define CLK_CLKDCTL_IRCFIF_Msk (0x1ul << CLK_CLKDCTL_IRCFIF_Pos) /*!< CLK CLKDCTL: IRCFIF Mask */
<> 144:ef7eb2e8f9f7 4043
<> 144:ef7eb2e8f9f7 4044 /**@}*/ /* CLK_CONST */
<> 144:ef7eb2e8f9f7 4045 /**@}*/ /* end of CLK register group */
<> 144:ef7eb2e8f9f7 4046
<> 144:ef7eb2e8f9f7 4047
<> 144:ef7eb2e8f9f7 4048 /*---------------------- Cyclic Redundancy Check Controller -------------------------*/
<> 144:ef7eb2e8f9f7 4049 /**
<> 144:ef7eb2e8f9f7 4050 @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
<> 144:ef7eb2e8f9f7 4051 Memory Mapped Structure for CRC Controller
<> 144:ef7eb2e8f9f7 4052 @{ */
<> 144:ef7eb2e8f9f7 4053
<> 144:ef7eb2e8f9f7 4054 typedef struct {
<> 144:ef7eb2e8f9f7 4055
<> 144:ef7eb2e8f9f7 4056
<> 144:ef7eb2e8f9f7 4057 /**
<> 144:ef7eb2e8f9f7 4058 * CTL
<> 144:ef7eb2e8f9f7 4059 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4060 * Offset: 0x00 CRC Control Register
<> 144:ef7eb2e8f9f7 4061 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4062 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4063 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4064 * |[0] |CRCEN |CRC Channel Enable Control
<> 144:ef7eb2e8f9f7 4065 * | | |0 = CRC function Disabled.
<> 144:ef7eb2e8f9f7 4066 * | | |1 = CRC function Enabled.
<> 144:ef7eb2e8f9f7 4067 * |[1] |CRCRST |CRC Engine Reset
<> 144:ef7eb2e8f9f7 4068 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 4069 * | | |1 = Reset the internal CRC state machine and internal buffer.
<> 144:ef7eb2e8f9f7 4070 * | | |The contents of control register will not be cleared.
<> 144:ef7eb2e8f9f7 4071 * | | |This bit will automatically be cleared after few clock cycles.
<> 144:ef7eb2e8f9f7 4072 * | | |Note: Setting this bit will reload the initial seed value.
<> 144:ef7eb2e8f9f7 4073 * |[24] |DATREV |Write Data Order Reverse
<> 144:ef7eb2e8f9f7 4074 * | | |0 = No bit order reversed for CRC write data in.
<> 144:ef7eb2e8f9f7 4075 * | | |1 = Bit order reversed for CRC write data in (per byte).
<> 144:ef7eb2e8f9f7 4076 * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
<> 144:ef7eb2e8f9f7 4077 * |[25] |CHKSREV |Checksum Reverse
<> 144:ef7eb2e8f9f7 4078 * | | |0 = No bit order reverse for CRC checksum.
<> 144:ef7eb2e8f9f7 4079 * | | |1 = Bit order reverse for CRC checksum.
<> 144:ef7eb2e8f9f7 4080 * | | |Note: If the checksum data is 0XDD7B0F2E, the bit order reversed for CRC checksum is 0x74F0DEBB.
<> 144:ef7eb2e8f9f7 4081 * |[26] |DATFMT |Write Data Complement
<> 144:ef7eb2e8f9f7 4082 * | | |0 = No bit order reversed for CRC write data in.
<> 144:ef7eb2e8f9f7 4083 * | | |1 = 1's complement for CRC write data in.
<> 144:ef7eb2e8f9f7 4084 * |[27] |CHKSFMT |Checksum Complement
<> 144:ef7eb2e8f9f7 4085 * | | |0 = No bit order reverse for CRC checksum.
<> 144:ef7eb2e8f9f7 4086 * | | |1 = 1's complement for CRC checksum.
<> 144:ef7eb2e8f9f7 4087 * |[28:29] |DATLEN |CPU Write Data Length
<> 144:ef7eb2e8f9f7 4088 * | | |This field indicates the write data length.
<> 144:ef7eb2e8f9f7 4089 * | | |00 = Data length is 8-bit mode.
<> 144:ef7eb2e8f9f7 4090 * | | |01 = Data length is 16-bit mode.
<> 144:ef7eb2e8f9f7 4091 * | | |1x = Data length is 32-bit mode.
<> 144:ef7eb2e8f9f7 4092 * | | |Note: When the data length is 8-bit mode, the valid data is DATA [7:0]; if the data length is 16-bit mode, the valid data is DATA [15:0].
<> 144:ef7eb2e8f9f7 4093 * |[30:31] |CRCMODE |CRC Polynomial Mode Selection
<> 144:ef7eb2e8f9f7 4094 * | | |00 = CRC-CCITT Polynomial mode.
<> 144:ef7eb2e8f9f7 4095 * | | |01 = CRC-8 Polynomial mode.
<> 144:ef7eb2e8f9f7 4096 * | | |10 = CRC-16 Polynomial mode.
<> 144:ef7eb2e8f9f7 4097 * | | |11 = CRC-32 Polynomial mode.
<> 144:ef7eb2e8f9f7 4098 */
<> 144:ef7eb2e8f9f7 4099 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 4100
<> 144:ef7eb2e8f9f7 4101 /**
<> 144:ef7eb2e8f9f7 4102 * DAT
<> 144:ef7eb2e8f9f7 4103 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4104 * Offset: 0x04 CRC Write Data Register
<> 144:ef7eb2e8f9f7 4105 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4106 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4107 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4108 * |[0:31] |DATA |CRC Write Data Bits
<> 144:ef7eb2e8f9f7 4109 * | | |Software can write data to this field to perform CRC operation, or uses PDMA function to get the data from memory
<> 144:ef7eb2e8f9f7 4110 * | | |Note1: The CRC_CTL [DATFMT] and CRC_CTL [DATREV] bit setting will affect this field; for example, if DATREV = 1, if the write data in DATA register is 0xAABBCCDD, the read data from DATA register will be 0x55DD33BB.
<> 144:ef7eb2e8f9f7 4111 */
<> 144:ef7eb2e8f9f7 4112 __IO uint32_t DAT;
<> 144:ef7eb2e8f9f7 4113
<> 144:ef7eb2e8f9f7 4114 /**
<> 144:ef7eb2e8f9f7 4115 * SEED
<> 144:ef7eb2e8f9f7 4116 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4117 * Offset: 0x08 CRC Seed Register
<> 144:ef7eb2e8f9f7 4118 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4119 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4120 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4121 * |[0:31] |SEED |CRC Seed Bits
<> 144:ef7eb2e8f9f7 4122 * | | |This field indicates the CRC seed value.
<> 144:ef7eb2e8f9f7 4123 */
<> 144:ef7eb2e8f9f7 4124 __IO uint32_t SEED;
<> 144:ef7eb2e8f9f7 4125
<> 144:ef7eb2e8f9f7 4126 /**
<> 144:ef7eb2e8f9f7 4127 * CHECKSUM
<> 144:ef7eb2e8f9f7 4128 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4129 * Offset: 0x0C CRC Checksum Register
<> 144:ef7eb2e8f9f7 4130 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4131 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4132 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4133 * |[0:31] |CHECKSUM |CRC Checksum Bits
<> 144:ef7eb2e8f9f7 4134 * | | |This field indicates the CRC checksum.
<> 144:ef7eb2e8f9f7 4135 */
<> 144:ef7eb2e8f9f7 4136 __I uint32_t CHECKSUM;
<> 144:ef7eb2e8f9f7 4137
<> 144:ef7eb2e8f9f7 4138 } CRC_T;
<> 144:ef7eb2e8f9f7 4139
<> 144:ef7eb2e8f9f7 4140 /**
<> 144:ef7eb2e8f9f7 4141 @addtogroup CRC_CONST CRC Bit Field Definition
<> 144:ef7eb2e8f9f7 4142 Constant Definitions for CRC Controller
<> 144:ef7eb2e8f9f7 4143 @{ */
<> 144:ef7eb2e8f9f7 4144
<> 144:ef7eb2e8f9f7 4145 #define CRC_CTL_CRCEN_Pos (0) /*!< CRC CTL: CRCEN Position */
<> 144:ef7eb2e8f9f7 4146 #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) /*!< CRC CTL: CRCEN Mask */
<> 144:ef7eb2e8f9f7 4147
<> 144:ef7eb2e8f9f7 4148 #define CRC_CTL_CRCRST_Pos (1) /*!< CRC CTL: CRCRST Position */
<> 144:ef7eb2e8f9f7 4149 #define CRC_CTL_CRCRST_Msk (0x1ul << CRC_CTL_CRCRST_Pos) /*!< CRC CTL: CRCRST Mask */
<> 144:ef7eb2e8f9f7 4150
<> 144:ef7eb2e8f9f7 4151 #define CRC_CTL_DATREV_Pos (24) /*!< CRC CTL: DATREV Position */
<> 144:ef7eb2e8f9f7 4152 #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) /*!< CRC CTL: DATREV Mask */
<> 144:ef7eb2e8f9f7 4153
<> 144:ef7eb2e8f9f7 4154 #define CRC_CTL_CHKSREV_Pos (25) /*!< CRC CTL: CHKSREV Position */
<> 144:ef7eb2e8f9f7 4155 #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) /*!< CRC CTL: CHKSREV Mask */
<> 144:ef7eb2e8f9f7 4156
<> 144:ef7eb2e8f9f7 4157 #define CRC_CTL_DATFMT_Pos (26) /*!< CRC CTL: DATFMT Position */
<> 144:ef7eb2e8f9f7 4158 #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) /*!< CRC CTL: DATFMT Mask */
<> 144:ef7eb2e8f9f7 4159
<> 144:ef7eb2e8f9f7 4160 #define CRC_CTL_CHKSFMT_Pos (27) /*!< CRC CTL: CHKSFMT Position */
<> 144:ef7eb2e8f9f7 4161 #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) /*!< CRC CTL: CHKSFMT Mask */
<> 144:ef7eb2e8f9f7 4162
<> 144:ef7eb2e8f9f7 4163 #define CRC_CTL_DATLEN_Pos (28) /*!< CRC CTL: DATLEN Position */
<> 144:ef7eb2e8f9f7 4164 #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) /*!< CRC CTL: DATLEN Mask */
<> 144:ef7eb2e8f9f7 4165
<> 144:ef7eb2e8f9f7 4166 #define CRC_CTL_CRCMODE_Pos (30) /*!< CRC CTL: CRCMODE Position */
<> 144:ef7eb2e8f9f7 4167 #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) /*!< CRC CTL: CRCMODE Mask */
<> 144:ef7eb2e8f9f7 4168
<> 144:ef7eb2e8f9f7 4169 #define CRC_DAT_DATA_Pos (0) /*!< CRC DAT: DATA Position */
<> 144:ef7eb2e8f9f7 4170 #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) /*!< CRC DAT: DATA Mask */
<> 144:ef7eb2e8f9f7 4171
<> 144:ef7eb2e8f9f7 4172 #define CRC_SEED_SEED_Pos (0) /*!< CRC SEED: SEED Position */
<> 144:ef7eb2e8f9f7 4173 #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) /*!< CRC SEED: SEED Mask */
<> 144:ef7eb2e8f9f7 4174
<> 144:ef7eb2e8f9f7 4175 #define CRC_CHECKSUM_CHECKSUM_Pos (0) /*!< CRC CHECKSUM: CHECKSUM Position */
<> 144:ef7eb2e8f9f7 4176 #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) /*!< CRC CHECKSUM: CHECKSUM Mask */
<> 144:ef7eb2e8f9f7 4177
<> 144:ef7eb2e8f9f7 4178 /**@}*/ /* CRC_CONST */
<> 144:ef7eb2e8f9f7 4179 /**@}*/ /* end of CRC register group */
<> 144:ef7eb2e8f9f7 4180
<> 144:ef7eb2e8f9f7 4181
<> 144:ef7eb2e8f9f7 4182 /*---------------------- Cryptographic Accelerator -------------------------*/
<> 144:ef7eb2e8f9f7 4183 /**
<> 144:ef7eb2e8f9f7 4184 @addtogroup CRPT Cryptographic Accelerator(CRPT)
<> 144:ef7eb2e8f9f7 4185 Memory Mapped Structure for CRPT Controller
<> 144:ef7eb2e8f9f7 4186 @{ */
<> 144:ef7eb2e8f9f7 4187
<> 144:ef7eb2e8f9f7 4188 typedef struct {
<> 144:ef7eb2e8f9f7 4189 /**
<> 144:ef7eb2e8f9f7 4190 * INTEN
<> 144:ef7eb2e8f9f7 4191 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4192 * Offset: 0x00 Crypto Interrupt Enable Control Register
<> 144:ef7eb2e8f9f7 4193 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4194 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4195 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4196 * |[0] |AESIEN |AES Interrupt Enable Control
<> 144:ef7eb2e8f9f7 4197 * | | |0 = AES interrupt Disabled.
<> 144:ef7eb2e8f9f7 4198 * | | |1 = AES interrupt Enabled.
<> 144:ef7eb2e8f9f7 4199 * | | |In DMA mode, an interrupt will be triggered when amount of data set in AES_DMA_CNT is fed into the AES engine.
<> 144:ef7eb2e8f9f7 4200 * | | |In Non-DMA mode, an interrupt will be triggered when the AES engine finishes the operation.
<> 144:ef7eb2e8f9f7 4201 * |[1] |AESERRIEN |AES Error Flag Enable Control
<> 144:ef7eb2e8f9f7 4202 * | | |0 = AES error interrupt flag Disabled.
<> 144:ef7eb2e8f9f7 4203 * | | |1 = AES error interrupt flag Enabled.
<> 144:ef7eb2e8f9f7 4204 * |[8] |TDESIEN |TDES/DES Interrupt Enable Control
<> 144:ef7eb2e8f9f7 4205 * | | |0 = TDES/DES interrupt Disabled.
<> 144:ef7eb2e8f9f7 4206 * | | |1 = TDES/DES interrupt Enabled.
<> 144:ef7eb2e8f9f7 4207 * | | |In DMA mode, an interrupt will be triggered when amount of data set in TDES_DMA_CNT is fed into the TDES engine.
<> 144:ef7eb2e8f9f7 4208 * | | |In Non-DMA mode, an interrupt will be triggered when the TDES engine finishes the operation.
<> 144:ef7eb2e8f9f7 4209 * |[9] |TDESERRIEN|TDES/DES Error Flag Enable Control
<> 144:ef7eb2e8f9f7 4210 * | | |0 = TDES/DES error interrupt flag Disabled.
<> 144:ef7eb2e8f9f7 4211 * | | |1 = TDES/DES error interrupt flag Enabled.
<> 144:ef7eb2e8f9f7 4212 * |[16] |PRNGIEN |PRNG Interrupt Enable Control
<> 144:ef7eb2e8f9f7 4213 * | | |0 = PRNG interrupt Disabled.
<> 144:ef7eb2e8f9f7 4214 * | | |1 = PRNG interrupt Enabled.
<> 144:ef7eb2e8f9f7 4215 * |[24] |SHAIEN |SHA Interrupt Enable Control
<> 144:ef7eb2e8f9f7 4216 * | | |0 = SHA interrupt Disabled.
<> 144:ef7eb2e8f9f7 4217 * | | |1 = SHA interrupt Enabled.
<> 144:ef7eb2e8f9f7 4218 * | | |In DMA mode, an interrupt will be triggered when amount of data set in SHA _DMA_CNT is fed into the SHA engine.
<> 144:ef7eb2e8f9f7 4219 * | | |In Non-DMA mode, an interrupt will be triggered when the SHA engine finishes the operation.
<> 144:ef7eb2e8f9f7 4220 * |[25] |SHAERRIEN |SHA Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 4221 * | | |0 = SHA error interrupt flag Disabled.
<> 144:ef7eb2e8f9f7 4222 * | | |1 = SHA error interrupt flag Enabled.
<> 144:ef7eb2e8f9f7 4223 */
<> 144:ef7eb2e8f9f7 4224 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 4225
<> 144:ef7eb2e8f9f7 4226 /**
<> 144:ef7eb2e8f9f7 4227 * INTSTS
<> 144:ef7eb2e8f9f7 4228 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4229 * Offset: 0x04 Crypto Interrupt Flag
<> 144:ef7eb2e8f9f7 4230 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4231 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4232 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4233 * |[0] |AESIF |AES Finish Interrupt Flag
<> 144:ef7eb2e8f9f7 4234 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
<> 144:ef7eb2e8f9f7 4235 * | | |0 = No AES interrupt.
<> 144:ef7eb2e8f9f7 4236 * | | |1 = AES encryption/decryption done interrupt.
<> 144:ef7eb2e8f9f7 4237 * |[1] |AESERRIF |AES Error Flag
<> 144:ef7eb2e8f9f7 4238 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
<> 144:ef7eb2e8f9f7 4239 * | | |0 = No AES error.
<> 144:ef7eb2e8f9f7 4240 * | | |1 = AES encryption/decryption done interrupt.
<> 144:ef7eb2e8f9f7 4241 * |[8] |TDESIF |TDES/DES Finish Interrupt Flag
<> 144:ef7eb2e8f9f7 4242 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
<> 144:ef7eb2e8f9f7 4243 * | | |0 = No TDES/DES interrupt.
<> 144:ef7eb2e8f9f7 4244 * | | |1 = TDES/DES encryption/decryption done interrupt.
<> 144:ef7eb2e8f9f7 4245 * |[9] |TDESERRIF |TDES/DES Error Flag
<> 144:ef7eb2e8f9f7 4246 * | | |This bit includes the operating and setting error.
<> 144:ef7eb2e8f9f7 4247 * | | |The detailed flag is shown in the TDES _FLAG register.
<> 144:ef7eb2e8f9f7 4248 * | | |This includes operating and setting error.
<> 144:ef7eb2e8f9f7 4249 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
<> 144:ef7eb2e8f9f7 4250 * | | |0 = No TDES/DES error.
<> 144:ef7eb2e8f9f7 4251 * | | |1 = TDES/DES encryption/decryption error interrupt.
<> 144:ef7eb2e8f9f7 4252 * |[16] |PRNGIF |PRNG Finish Interrupt Flag
<> 144:ef7eb2e8f9f7 4253 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
<> 144:ef7eb2e8f9f7 4254 * | | |0 = No PRNG interrupt.
<> 144:ef7eb2e8f9f7 4255 * | | |1 = PRNG key generation done interrupt.
<> 144:ef7eb2e8f9f7 4256 * |[24] |SHAIF |SHA Finish Interrupt Flag
<> 144:ef7eb2e8f9f7 4257 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
<> 144:ef7eb2e8f9f7 4258 * | | |0 = No SHA interrupt.
<> 144:ef7eb2e8f9f7 4259 * | | |1 = SHA operation done interrupt.
<> 144:ef7eb2e8f9f7 4260 * |[25] |SHAERRIF |SHA Error Flag
<> 144:ef7eb2e8f9f7 4261 * | | |This register includes operating and setting error. The detail flag is shown in SHA _FLAG register.
<> 144:ef7eb2e8f9f7 4262 * | | |This bit is cleared by writing 1, and it has no effect by writing 0.
<> 144:ef7eb2e8f9f7 4263 * | | |0 = No SHA error.
<> 144:ef7eb2e8f9f7 4264 * | | |1 = SHA error interrupt.
<> 144:ef7eb2e8f9f7 4265 */
<> 144:ef7eb2e8f9f7 4266 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 4267
<> 144:ef7eb2e8f9f7 4268 /**
<> 144:ef7eb2e8f9f7 4269 * PRNG_CTL
<> 144:ef7eb2e8f9f7 4270 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4271 * Offset: 0x08 PRNG Control Register
<> 144:ef7eb2e8f9f7 4272 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4273 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4274 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4275 * |[0] |START |Start PRNG Engine
<> 144:ef7eb2e8f9f7 4276 * | | |0 = Stop PRNG engine.
<> 144:ef7eb2e8f9f7 4277 * | | |1 = Generate new key and store the new key to register CRPT_PRNG_KEYx , which will be cleared when the new key is generated.
<> 144:ef7eb2e8f9f7 4278 * |[1] |SEEDRLD |Reload New Seed For PRNG Engine
<> 144:ef7eb2e8f9f7 4279 * | | |0 = Generating key based on the current seed.
<> 144:ef7eb2e8f9f7 4280 * | | |1 = Reload new seed.
<> 144:ef7eb2e8f9f7 4281 * |[2:3] |KEYSZ |PRNG Generate Key Size
<> 144:ef7eb2e8f9f7 4282 * | | |00 = 64 bits.
<> 144:ef7eb2e8f9f7 4283 * | | |01 = 128 bits.
<> 144:ef7eb2e8f9f7 4284 * | | |10 = 192 bits.
<> 144:ef7eb2e8f9f7 4285 * | | |11 = 256 bits.
<> 144:ef7eb2e8f9f7 4286 * |[8] |BUSY |PRNG Busy (Read Only)
<> 144:ef7eb2e8f9f7 4287 * | | |0 = PRNG engine is idle.
<> 144:ef7eb2e8f9f7 4288 * | | |1 = Indicate that the PRNG engine is generating CRPT_PRNG_KEYx.
<> 144:ef7eb2e8f9f7 4289 */
<> 144:ef7eb2e8f9f7 4290 __IO uint32_t PRNG_CTL;
<> 144:ef7eb2e8f9f7 4291
<> 144:ef7eb2e8f9f7 4292 /**
<> 144:ef7eb2e8f9f7 4293 * PRNG_SEED
<> 144:ef7eb2e8f9f7 4294 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4295 * Offset: 0x0C Seed for PRNG
<> 144:ef7eb2e8f9f7 4296 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4297 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4298 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4299 * |[0:31] |CRPT_PRNG_SEED|Seed For PRNG (Write Only)
<> 144:ef7eb2e8f9f7 4300 * | | |The bits store the seed for PRNG engine.
<> 144:ef7eb2e8f9f7 4301 */
<> 144:ef7eb2e8f9f7 4302 __O uint32_t PRNG_SEED;
<> 144:ef7eb2e8f9f7 4303
<> 144:ef7eb2e8f9f7 4304 /**
<> 144:ef7eb2e8f9f7 4305 * PRNG_KEY0
<> 144:ef7eb2e8f9f7 4306 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4307 * Offset: 0x10 PRNG Generated Key0
<> 144:ef7eb2e8f9f7 4308 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4309 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4310 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4311 * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
<> 144:ef7eb2e8f9f7 4312 * | | |The bits store the key that is generated by PRNG.
<> 144:ef7eb2e8f9f7 4313 */
<> 144:ef7eb2e8f9f7 4314 __I uint32_t PRNG_KEY0;
<> 144:ef7eb2e8f9f7 4315
<> 144:ef7eb2e8f9f7 4316 /**
<> 144:ef7eb2e8f9f7 4317 * PRNG_KEY1
<> 144:ef7eb2e8f9f7 4318 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4319 * Offset: 0x14 PRNG Generated Key1
<> 144:ef7eb2e8f9f7 4320 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4321 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4322 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4323 * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
<> 144:ef7eb2e8f9f7 4324 * | | |The bits store the key that is generated by PRNG.
<> 144:ef7eb2e8f9f7 4325 */
<> 144:ef7eb2e8f9f7 4326 __I uint32_t PRNG_KEY1;
<> 144:ef7eb2e8f9f7 4327
<> 144:ef7eb2e8f9f7 4328 /**
<> 144:ef7eb2e8f9f7 4329 * PRNG_KEY2
<> 144:ef7eb2e8f9f7 4330 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4331 * Offset: 0x18 PRNG Generated Key2
<> 144:ef7eb2e8f9f7 4332 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4333 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4334 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4335 * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
<> 144:ef7eb2e8f9f7 4336 * | | |The bits store the key that is generated by PRNG.
<> 144:ef7eb2e8f9f7 4337 */
<> 144:ef7eb2e8f9f7 4338 __I uint32_t PRNG_KEY2;
<> 144:ef7eb2e8f9f7 4339
<> 144:ef7eb2e8f9f7 4340 /**
<> 144:ef7eb2e8f9f7 4341 * PRNG_KEY3
<> 144:ef7eb2e8f9f7 4342 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4343 * Offset: 0x1C PRNG Generated Key3
<> 144:ef7eb2e8f9f7 4344 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4345 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4346 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4347 * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
<> 144:ef7eb2e8f9f7 4348 * | | |The bits store the key that is generated by PRNG.
<> 144:ef7eb2e8f9f7 4349 */
<> 144:ef7eb2e8f9f7 4350 __I uint32_t PRNG_KEY3;
<> 144:ef7eb2e8f9f7 4351
<> 144:ef7eb2e8f9f7 4352 /**
<> 144:ef7eb2e8f9f7 4353 * PRNG_KEY4
<> 144:ef7eb2e8f9f7 4354 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4355 * Offset: 0x20 PRNG Generated Key4
<> 144:ef7eb2e8f9f7 4356 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4357 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4358 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4359 * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
<> 144:ef7eb2e8f9f7 4360 * | | |The bits store the key that is generated by PRNG.
<> 144:ef7eb2e8f9f7 4361 */
<> 144:ef7eb2e8f9f7 4362 __I uint32_t PRNG_KEY4;
<> 144:ef7eb2e8f9f7 4363
<> 144:ef7eb2e8f9f7 4364 /**
<> 144:ef7eb2e8f9f7 4365 * PRNG_KEY5
<> 144:ef7eb2e8f9f7 4366 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4367 * Offset: 0x24 PRNG Generated Key5
<> 144:ef7eb2e8f9f7 4368 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4369 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4370 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4371 * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
<> 144:ef7eb2e8f9f7 4372 * | | |The bits store the key that is generated by PRNG.
<> 144:ef7eb2e8f9f7 4373 */
<> 144:ef7eb2e8f9f7 4374 __I uint32_t PRNG_KEY5;
<> 144:ef7eb2e8f9f7 4375
<> 144:ef7eb2e8f9f7 4376 /**
<> 144:ef7eb2e8f9f7 4377 * PRNG_KEY6
<> 144:ef7eb2e8f9f7 4378 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4379 * Offset: 0x28 PRNG Generated Key6
<> 144:ef7eb2e8f9f7 4380 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4381 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4382 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4383 * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
<> 144:ef7eb2e8f9f7 4384 * | | |The bits store the key that is generated by PRNG.
<> 144:ef7eb2e8f9f7 4385 */
<> 144:ef7eb2e8f9f7 4386 __I uint32_t PRNG_KEY6;
<> 144:ef7eb2e8f9f7 4387
<> 144:ef7eb2e8f9f7 4388 /**
<> 144:ef7eb2e8f9f7 4389 * PRNG_KEY7
<> 144:ef7eb2e8f9f7 4390 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4391 * Offset: 0x2C PRNG Generated Key7
<> 144:ef7eb2e8f9f7 4392 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4393 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4394 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4395 * |[0:31] |KEYx |Store PRNG Generated Key (Read Only)
<> 144:ef7eb2e8f9f7 4396 * | | |The bits store the key that is generated by PRNG.
<> 144:ef7eb2e8f9f7 4397 */
<> 144:ef7eb2e8f9f7 4398 __I uint32_t PRNG_KEY7;
<> 144:ef7eb2e8f9f7 4399 uint32_t RESERVE0[8];
<> 144:ef7eb2e8f9f7 4400
<> 144:ef7eb2e8f9f7 4401
<> 144:ef7eb2e8f9f7 4402 /**
<> 144:ef7eb2e8f9f7 4403 * AES_FDBCK0
<> 144:ef7eb2e8f9f7 4404 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4405 * Offset: 0x50 AES Engine Output Feedback Data after Cryptographic Operation
<> 144:ef7eb2e8f9f7 4406 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4407 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4408 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4409 * |[0:31] |FDBCK |AES Feedback Information
<> 144:ef7eb2e8f9f7 4410 * | | |The feedback value is 128 bits in size.
<> 144:ef7eb2e8f9f7 4411 * | | |The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
<> 144:ef7eb2e8f9f7 4412 * | | |The AES engine outputs feedback information for IV in the next block's operation.
<> 144:ef7eb2e8f9f7 4413 * | | |Software can use this feedback information to implement more than four DMA channels.
<> 144:ef7eb2e8f9f7 4414 * | | |Software can store that feedback value temporarily.
<> 144:ef7eb2e8f9f7 4415 * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
<> 144:ef7eb2e8f9f7 4416 */
<> 144:ef7eb2e8f9f7 4417 __I uint32_t AES_FDBCK0;
<> 144:ef7eb2e8f9f7 4418
<> 144:ef7eb2e8f9f7 4419 /**
<> 144:ef7eb2e8f9f7 4420 * AES_FDBCK1
<> 144:ef7eb2e8f9f7 4421 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4422 * Offset: 0x54 AES Engine Output Feedback Data after Cryptographic Operation
<> 144:ef7eb2e8f9f7 4423 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4424 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4425 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4426 * |[0:31] |FDBCK |AES Feedback Information
<> 144:ef7eb2e8f9f7 4427 * | | |The feedback value is 128 bits in size.
<> 144:ef7eb2e8f9f7 4428 * | | |The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
<> 144:ef7eb2e8f9f7 4429 * | | |The AES engine outputs feedback information for IV in the next block's operation.
<> 144:ef7eb2e8f9f7 4430 * | | |Software can use this feedback information to implement more than four DMA channels.
<> 144:ef7eb2e8f9f7 4431 * | | |Software can store that feedback value temporarily.
<> 144:ef7eb2e8f9f7 4432 * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
<> 144:ef7eb2e8f9f7 4433 */
<> 144:ef7eb2e8f9f7 4434 __I uint32_t AES_FDBCK1;
<> 144:ef7eb2e8f9f7 4435
<> 144:ef7eb2e8f9f7 4436 /**
<> 144:ef7eb2e8f9f7 4437 * AES_FDBCK2
<> 144:ef7eb2e8f9f7 4438 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4439 * Offset: 0x58 AES Engine Output Feedback Data after Cryptographic Operation
<> 144:ef7eb2e8f9f7 4440 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4441 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4442 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4443 * |[0:31] |FDBCK |AES Feedback Information
<> 144:ef7eb2e8f9f7 4444 * | | |The feedback value is 128 bits in size.
<> 144:ef7eb2e8f9f7 4445 * | | |The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
<> 144:ef7eb2e8f9f7 4446 * | | |The AES engine outputs feedback information for IV in the next block's operation.
<> 144:ef7eb2e8f9f7 4447 * | | |Software can use this feedback information to implement more than four DMA channels.
<> 144:ef7eb2e8f9f7 4448 * | | |Software can store that feedback value temporarily.
<> 144:ef7eb2e8f9f7 4449 * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
<> 144:ef7eb2e8f9f7 4450 */
<> 144:ef7eb2e8f9f7 4451 __I uint32_t AES_FDBCK2;
<> 144:ef7eb2e8f9f7 4452
<> 144:ef7eb2e8f9f7 4453 /**
<> 144:ef7eb2e8f9f7 4454 * AES_FDBCK3
<> 144:ef7eb2e8f9f7 4455 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4456 * Offset: 0x5C AES Engine Output Feedback Data after Cryptographic Operation
<> 144:ef7eb2e8f9f7 4457 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4458 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4459 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4460 * |[0:31] |FDBCK |AES Feedback Information
<> 144:ef7eb2e8f9f7 4461 * | | |The feedback value is 128 bits in size.
<> 144:ef7eb2e8f9f7 4462 * | | |The AES engine uses the data from AES_FEEEDBACK as the data inputted to AES_IV for the next block in DMA cascade mode.
<> 144:ef7eb2e8f9f7 4463 * | | |The AES engine outputs feedback information for IV in the next block's operation.
<> 144:ef7eb2e8f9f7 4464 * | | |Software can use this feedback information to implement more than four DMA channels.
<> 144:ef7eb2e8f9f7 4465 * | | |Software can store that feedback value temporarily.
<> 144:ef7eb2e8f9f7 4466 * | | |After switching back, fill the stored feedback value to this register in the same channel operation, and then continue the operation with the original setting.
<> 144:ef7eb2e8f9f7 4467 */
<> 144:ef7eb2e8f9f7 4468 __I uint32_t AES_FDBCK3;
<> 144:ef7eb2e8f9f7 4469
<> 144:ef7eb2e8f9f7 4470 /**
<> 144:ef7eb2e8f9f7 4471 * TDES_FDBCKH
<> 144:ef7eb2e8f9f7 4472 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4473 * Offset: 0x60 TDES/DES Engine Output Feedback High Word Data after Cryptographic Operation
<> 144:ef7eb2e8f9f7 4474 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4475 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4476 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4477 * |[0:31] |FDBCK |TDES/DES Feedback
<> 144:ef7eb2e8f9f7 4478 * | | |The feedback value is 64 bits in size.
<> 144:ef7eb2e8f9f7 4479 * | | |The TDES/DES engine uses the data from CRPT_TDES_FEEEDBACK as the data inputted to CRPT_TDES_IV for the next block in DMA cascade mode.
<> 144:ef7eb2e8f9f7 4480 * | | |The feedback register is for CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 4481 * | | |TDES/DES engine outputs feedback information for IV in the next block's operation.
<> 144:ef7eb2e8f9f7 4482 * | | |Software can use this feedback information to implement more than four DMA channels.
<> 144:ef7eb2e8f9f7 4483 * | | |Software can store that feedback value temporarily.
<> 144:ef7eb2e8f9f7 4484 * | | |After switching back, fill the stored feedback value to this register in the same channel operation.
<> 144:ef7eb2e8f9f7 4485 * | | |Then can continue the operation with the original setting.
<> 144:ef7eb2e8f9f7 4486 */
<> 144:ef7eb2e8f9f7 4487 __I uint32_t TDES_FDBCKH;
<> 144:ef7eb2e8f9f7 4488
<> 144:ef7eb2e8f9f7 4489 /**
<> 144:ef7eb2e8f9f7 4490 * TDES_FDBCKL
<> 144:ef7eb2e8f9f7 4491 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4492 * Offset: 0x64 TDES/DES Engine Output Feedback Low Word Data after Cryptographic Operation
<> 144:ef7eb2e8f9f7 4493 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4494 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4495 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4496 * |[0:31] |FDBCK |TDES/DES Feedback
<> 144:ef7eb2e8f9f7 4497 * | | |The feedback value is 64 bits in size.
<> 144:ef7eb2e8f9f7 4498 * | | |The TDES/DES engine uses the data from CRPT_TDES_FEEEDBACK as the data inputted to CRPT_TDES_IV for the next block in DMA cascade mode.
<> 144:ef7eb2e8f9f7 4499 * | | |The feedback register is for CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 4500 * | | |TDES/DES engine outputs feedback information for IV in the next block's operation.
<> 144:ef7eb2e8f9f7 4501 * | | |Software can use this feedback information to implement more than four DMA channels.
<> 144:ef7eb2e8f9f7 4502 * | | |Software can store that feedback value temporarily.
<> 144:ef7eb2e8f9f7 4503 * | | |After switching back, fill the stored feedback value to this register in the same channel operation.
<> 144:ef7eb2e8f9f7 4504 * | | |Then can continue the operation with the original setting.
<> 144:ef7eb2e8f9f7 4505 */
<> 144:ef7eb2e8f9f7 4506 __I uint32_t TDES_FDBCKL;
<> 144:ef7eb2e8f9f7 4507 uint32_t RESERVE1[38];
<> 144:ef7eb2e8f9f7 4508
<> 144:ef7eb2e8f9f7 4509
<> 144:ef7eb2e8f9f7 4510 /**
<> 144:ef7eb2e8f9f7 4511 * AES_CTL
<> 144:ef7eb2e8f9f7 4512 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4513 * Offset: 0x100 AES Control Register
<> 144:ef7eb2e8f9f7 4514 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4515 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4516 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4517 * |[0] |START |AES Engine Start
<> 144:ef7eb2e8f9f7 4518 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 4519 * | | |1 = Start AES engine. BUSY flag will be set.
<> 144:ef7eb2e8f9f7 4520 * | | |Note: This bit is always 0 when it's read back.
<> 144:ef7eb2e8f9f7 4521 * |[1] |STOP |AES Engine Stop
<> 144:ef7eb2e8f9f7 4522 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 4523 * | | |1 = Stop AES engine.
<> 144:ef7eb2e8f9f7 4524 * | | |Note: This bit is always 0 when it's read back.
<> 144:ef7eb2e8f9f7 4525 * |[2:3] |KEYSZ |AES Key Size
<> 144:ef7eb2e8f9f7 4526 * | | |This bit defines three different key size for AES operation.
<> 144:ef7eb2e8f9f7 4527 * | | |2'b00 = 128 bits key.
<> 144:ef7eb2e8f9f7 4528 * | | |2'b01 = 192 bits key.
<> 144:ef7eb2e8f9f7 4529 * | | |2'b10 = 256 bits key.
<> 144:ef7eb2e8f9f7 4530 * | | |2'b11 = Reserved.
<> 144:ef7eb2e8f9f7 4531 * | | |If the AES accelerator is operating and the corresponding flag BUSY is 1, updating this register has no effect.
<> 144:ef7eb2e8f9f7 4532 * |[5] |DMALAST |AES Last Block
<> 144:ef7eb2e8f9f7 4533 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
<> 144:ef7eb2e8f9f7 4534 * | | |In Non-DMA mode, this bit must be set when feeding in the last block of data in ECB, CBC, CTR, OFB, and CFB mode, and feeding in the (last-1) block of data at CBC-CS1, CBC-CS2, and CBC-CS3 mode.
<> 144:ef7eb2e8f9f7 4535 * | | |This bit is always 0 when it's read back. Must be written again once START is triggered.
<> 144:ef7eb2e8f9f7 4536 * |[6] |DMACSCAD |AES Engine DMA With Cascade Mode
<> 144:ef7eb2e8f9f7 4537 * | | |0 = DMA cascade function Disabled.
<> 144:ef7eb2e8f9f7 4538 * | | |1 = In DMA cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
<> 144:ef7eb2e8f9f7 4539 * |[7] |DMAEN |AES Engine DMA Enable Control
<> 144:ef7eb2e8f9f7 4540 * | | |0 = AES DMA engine Disabled.
<> 144:ef7eb2e8f9f7 4541 * | | |The AES engine operates in Non-DMA mode, and gets data from the port CRPT_AES_DATIN.
<> 144:ef7eb2e8f9f7 4542 * | | |1 = AES DMA engine Enabled.
<> 144:ef7eb2e8f9f7 4543 * | | |The AES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
<> 144:ef7eb2e8f9f7 4544 * |[8:15] |OPMODE |AES Engine Operation Modes
<> 144:ef7eb2e8f9f7 4545 * | | |0x00 = ECB (Electronic Codebook Mode)
<> 144:ef7eb2e8f9f7 4546 * | | |0x01 = CBC (Cipher Block Chaining Mode).
<> 144:ef7eb2e8f9f7 4547 * | | |0x02 = CFB (Cipher Feedback Mode).
<> 144:ef7eb2e8f9f7 4548 * | | |0x03 = OFB (Output Feedback Mode).
<> 144:ef7eb2e8f9f7 4549 * | | |0x04 = CTR (Counter Mode).
<> 144:ef7eb2e8f9f7 4550 * | | |0x10 = CBC-CS1 (CBC Ciphertext-Stealing 1 Mode).
<> 144:ef7eb2e8f9f7 4551 * | | |0x11 = CBC-CS2 (CBC Ciphertext-Stealing 2 Mode).
<> 144:ef7eb2e8f9f7 4552 * | | |0x12 = CBC-CS3 (CBC Ciphertext-Stealing 3 Mode).
<> 144:ef7eb2e8f9f7 4553 * |[16] |ENCRPT |AES Encryption/Decryption
<> 144:ef7eb2e8f9f7 4554 * | | |0 = AES engine executes decryption operation.
<> 144:ef7eb2e8f9f7 4555 * | | |1 = AES engine executes encryption operation.
<> 144:ef7eb2e8f9f7 4556 * |[22] |OUTSWAP |AES Engine Output Data Swap
<> 144:ef7eb2e8f9f7 4557 * | | |0 = Keep the original order.
<> 144:ef7eb2e8f9f7 4558 * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
<> 144:ef7eb2e8f9f7 4559 * |[23] |INSWAP |AES Engine Input Data Swap
<> 144:ef7eb2e8f9f7 4560 * | | |0 = Keep the original order.
<> 144:ef7eb2e8f9f7 4561 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
<> 144:ef7eb2e8f9f7 4562 * |[24:25] |CHANNEL |AES Engine Working Channel
<> 144:ef7eb2e8f9f7 4563 * | | |00 = Current control register setting is for channel 0.
<> 144:ef7eb2e8f9f7 4564 * | | |01 = Current control register setting is for channel 1.
<> 144:ef7eb2e8f9f7 4565 * | | |10 = Current control register setting is for channel 2.
<> 144:ef7eb2e8f9f7 4566 * | | |11 = Current control register setting is for channel 3.
<> 144:ef7eb2e8f9f7 4567 * |[26:30] |KEYUNPRT |Unprotect Key
<> 144:ef7eb2e8f9f7 4568 * | | |Writing 0 to CRPT_AES_CTL [31] and "10110" to CRPT_AES_CTL [30:26] is to unprotect the AES key.
<> 144:ef7eb2e8f9f7 4569 * | | |The KEYUNPRT can be read and written.
<> 144:ef7eb2e8f9f7 4570 * | | |When it is written as the AES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
<> 144:ef7eb2e8f9f7 4571 * |[31] |KEYPRT |Protect Key
<> 144:ef7eb2e8f9f7 4572 * | | |Read as a flag to reflect KEYPRT.
<> 144:ef7eb2e8f9f7 4573 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 4574 * | | |1 = Protect the content of the AES key from reading.
<> 144:ef7eb2e8f9f7 4575 * | | |The return value for reading CRPT_AESn_KEYx is not the content of the registers CRPT_AESn_KEYx.
<> 144:ef7eb2e8f9f7 4576 * | | |Once it is set, it can be cleared by asserting KEYUNPRT.
<> 144:ef7eb2e8f9f7 4577 * | | |And the key content would be cleared as well.
<> 144:ef7eb2e8f9f7 4578 */
<> 144:ef7eb2e8f9f7 4579 __IO uint32_t AES_CTL;
<> 144:ef7eb2e8f9f7 4580
<> 144:ef7eb2e8f9f7 4581 /**
<> 144:ef7eb2e8f9f7 4582 * AES_STS
<> 144:ef7eb2e8f9f7 4583 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4584 * Offset: 0x104 AES Engine Flag
<> 144:ef7eb2e8f9f7 4585 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4586 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4587 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4588 * |[0] |BUSY |AES Engine Busy
<> 144:ef7eb2e8f9f7 4589 * | | |0 = The AES engine is idle or finished.
<> 144:ef7eb2e8f9f7 4590 * | | |1 = The AES engine is under processing.
<> 144:ef7eb2e8f9f7 4591 * |[8] |INBUFEMPTY|AES Input Buffer Empty
<> 144:ef7eb2e8f9f7 4592 * | | |0 = There are some data in input buffer waiting for the AES engine to process.
<> 144:ef7eb2e8f9f7 4593 * | | |1 = AES input buffer is empty.
<> 144:ef7eb2e8f9f7 4594 * | | |Software needs to feed data to the AES engine.
<> 144:ef7eb2e8f9f7 4595 * | | |Otherwise, the AES engine will be pending to wait for input data.
<> 144:ef7eb2e8f9f7 4596 * |[9] |INBUFFULL |AES Input Buffer Full Flag
<> 144:ef7eb2e8f9f7 4597 * | | |0 = AES input buffer is not full. Software can feed the data into the AES engine.
<> 144:ef7eb2e8f9f7 4598 * | | |1 = AES input buffer is full.
<> 144:ef7eb2e8f9f7 4599 * | | |Software cannot feed data to the AES engine.
<> 144:ef7eb2e8f9f7 4600 * | | |Otherwise, the flag INBUFERR will be set to 1.
<> 144:ef7eb2e8f9f7 4601 * |[10] |INBUFERR |AES Input Buffer Error Flag
<> 144:ef7eb2e8f9f7 4602 * | | |0 = No error.
<> 144:ef7eb2e8f9f7 4603 * | | |1 = Error happens during feeding data to the AES engine.
<> 144:ef7eb2e8f9f7 4604 * |[12] |CNTERR |AES_CNT Setting Error
<> 144:ef7eb2e8f9f7 4605 * | | |0 = No error in AES_CNT setting.
<> 144:ef7eb2e8f9f7 4606 * | | |1 = AES_CNT is not a multiply of 16 in ECB, CBC, CFB, OFB, and CTR mode.
<> 144:ef7eb2e8f9f7 4607 * |[16] |OUTBUFEMPTY|AES Out Buffer Empty
<> 144:ef7eb2e8f9f7 4608 * | | |0 = AES output buffer is not empty. There are some valid data kept in output buffer.
<> 144:ef7eb2e8f9f7 4609 * | | |1 = AES output buffer is empty.
<> 144:ef7eb2e8f9f7 4610 * | | |Software cannot get data from AES_DATA_OUT.
<> 144:ef7eb2e8f9f7 4611 * | | |Otherwise, the flag OUTBUFERR will be set to 1 since the output buffer is empty.
<> 144:ef7eb2e8f9f7 4612 * |[17] |OUTBUFFULL|AES Out Buffer Full Flag
<> 144:ef7eb2e8f9f7 4613 * | | |0 = AES output buffer is not full.
<> 144:ef7eb2e8f9f7 4614 * | | |1 = AES output buffer is full, and software needs to get data from AES_DATA_OUT.
<> 144:ef7eb2e8f9f7 4615 * | | |Otherwise, the AES engine will be pending since the output buffer is full.
<> 144:ef7eb2e8f9f7 4616 * |[18] |OUTBUFERR |AES Out Buffer Error Flag
<> 144:ef7eb2e8f9f7 4617 * | | |0 = No error.
<> 144:ef7eb2e8f9f7 4618 * | | |1 = Error happens during getting the result from AES engine.
<> 144:ef7eb2e8f9f7 4619 * |[20] |BUSERR |AES DMA Access Bus Error Flag
<> 144:ef7eb2e8f9f7 4620 * | | |0 = No error.
<> 144:ef7eb2e8f9f7 4621 * | | |1 = Bus error will stop DMA operation and AES engine.
<> 144:ef7eb2e8f9f7 4622 */
<> 144:ef7eb2e8f9f7 4623 __I uint32_t AES_STS;
<> 144:ef7eb2e8f9f7 4624
<> 144:ef7eb2e8f9f7 4625 /**
<> 144:ef7eb2e8f9f7 4626 * AES_DATIN
<> 144:ef7eb2e8f9f7 4627 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4628 * Offset: 0x108 AES Engine Data Input Port Register
<> 144:ef7eb2e8f9f7 4629 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4630 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4631 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4632 * |[0:31] |DATIN |AES Engine Input Port
<> 144:ef7eb2e8f9f7 4633 * | | |CPU feeds data to AES engine through this port by checking CRPT_AES_STS. Feed data as INBUFFULL is 0.
<> 144:ef7eb2e8f9f7 4634 */
<> 144:ef7eb2e8f9f7 4635 __IO uint32_t AES_DATIN;
<> 144:ef7eb2e8f9f7 4636
<> 144:ef7eb2e8f9f7 4637 /**
<> 144:ef7eb2e8f9f7 4638 * AES_DATOUT
<> 144:ef7eb2e8f9f7 4639 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4640 * Offset: 0x10C AES Engine Data Output Port Register
<> 144:ef7eb2e8f9f7 4641 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4642 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4643 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4644 * |[0:31] |DATOUT |AES Engine Output Port
<> 144:ef7eb2e8f9f7 4645 * | | |CPU gets results from the AES engine through this port by checking CRPT_AES_STS.
<> 144:ef7eb2e8f9f7 4646 * | | |Get data as OUTBUFEMPTY is 0.
<> 144:ef7eb2e8f9f7 4647 */
<> 144:ef7eb2e8f9f7 4648 __I uint32_t AES_DATOUT;
<> 144:ef7eb2e8f9f7 4649
<> 144:ef7eb2e8f9f7 4650 /**
<> 144:ef7eb2e8f9f7 4651 * AES0_KEY0
<> 144:ef7eb2e8f9f7 4652 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4653 * Offset: 0x110 AES Key Word 0 Register for Channel 0
<> 144:ef7eb2e8f9f7 4654 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4655 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4656 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4657 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4658 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4659 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4660 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4661 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4662 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4663 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4664 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4665 */
<> 144:ef7eb2e8f9f7 4666 __IO uint32_t AES0_KEY0;
<> 144:ef7eb2e8f9f7 4667
<> 144:ef7eb2e8f9f7 4668 /**
<> 144:ef7eb2e8f9f7 4669 * AES0_KEY1
<> 144:ef7eb2e8f9f7 4670 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4671 * Offset: 0x114 AES Key Word 1 Register for Channel 0
<> 144:ef7eb2e8f9f7 4672 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4673 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4674 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4675 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4676 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4677 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4678 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4679 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4680 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4681 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4682 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4683 */
<> 144:ef7eb2e8f9f7 4684 __IO uint32_t AES0_KEY1;
<> 144:ef7eb2e8f9f7 4685
<> 144:ef7eb2e8f9f7 4686 /**
<> 144:ef7eb2e8f9f7 4687 * AES0_KEY2
<> 144:ef7eb2e8f9f7 4688 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4689 * Offset: 0x118 AES Key Word 2 Register for Channel 0
<> 144:ef7eb2e8f9f7 4690 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4691 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4692 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4693 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4694 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4695 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4696 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4697 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4698 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4699 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4700 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4701 */
<> 144:ef7eb2e8f9f7 4702 __IO uint32_t AES0_KEY2;
<> 144:ef7eb2e8f9f7 4703
<> 144:ef7eb2e8f9f7 4704 /**
<> 144:ef7eb2e8f9f7 4705 * AES0_KEY3
<> 144:ef7eb2e8f9f7 4706 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4707 * Offset: 0x11C AES Key Word 3 Register for Channel 0
<> 144:ef7eb2e8f9f7 4708 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4709 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4710 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4711 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4712 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4713 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4714 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4715 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4716 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4717 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4718 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4719 */
<> 144:ef7eb2e8f9f7 4720 __IO uint32_t AES0_KEY3;
<> 144:ef7eb2e8f9f7 4721
<> 144:ef7eb2e8f9f7 4722 /**
<> 144:ef7eb2e8f9f7 4723 * AES0_KEY4
<> 144:ef7eb2e8f9f7 4724 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4725 * Offset: 0x120 AES Key Word 4 Register for Channel 0
<> 144:ef7eb2e8f9f7 4726 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4727 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4728 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4729 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4730 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4731 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4732 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4733 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4734 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4735 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4736 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4737 */
<> 144:ef7eb2e8f9f7 4738 __IO uint32_t AES0_KEY4;
<> 144:ef7eb2e8f9f7 4739
<> 144:ef7eb2e8f9f7 4740 /**
<> 144:ef7eb2e8f9f7 4741 * AES0_KEY5
<> 144:ef7eb2e8f9f7 4742 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4743 * Offset: 0x124 AES Key Word 5 Register for Channel 0
<> 144:ef7eb2e8f9f7 4744 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4745 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4746 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4747 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4748 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4749 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4750 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4751 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4752 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4753 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4754 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4755 */
<> 144:ef7eb2e8f9f7 4756 __IO uint32_t AES0_KEY5;
<> 144:ef7eb2e8f9f7 4757
<> 144:ef7eb2e8f9f7 4758 /**
<> 144:ef7eb2e8f9f7 4759 * AES0_KEY6
<> 144:ef7eb2e8f9f7 4760 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4761 * Offset: 0x128 AES Key Word 6 Register for Channel 0
<> 144:ef7eb2e8f9f7 4762 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4763 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4764 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4765 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4766 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4767 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4768 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4769 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4770 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4771 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4772 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4773 */
<> 144:ef7eb2e8f9f7 4774 __IO uint32_t AES0_KEY6;
<> 144:ef7eb2e8f9f7 4775
<> 144:ef7eb2e8f9f7 4776 /**
<> 144:ef7eb2e8f9f7 4777 * AES0_KEY7
<> 144:ef7eb2e8f9f7 4778 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4779 * Offset: 0x12C AES Key Word 7 Register for Channel 0
<> 144:ef7eb2e8f9f7 4780 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4781 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4782 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4783 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4784 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4785 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4786 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4787 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4788 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4789 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4790 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4791 */
<> 144:ef7eb2e8f9f7 4792 __IO uint32_t AES0_KEY7;
<> 144:ef7eb2e8f9f7 4793
<> 144:ef7eb2e8f9f7 4794 /**
<> 144:ef7eb2e8f9f7 4795 * AES0_IV0
<> 144:ef7eb2e8f9f7 4796 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4797 * Offset: 0x130 AES Initial Vector Word 0 Register for Channel 0
<> 144:ef7eb2e8f9f7 4798 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4799 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4800 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4801 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 4802 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4803 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 4804 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 4805 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 4806 */
<> 144:ef7eb2e8f9f7 4807 __IO uint32_t AES0_IV0;
<> 144:ef7eb2e8f9f7 4808
<> 144:ef7eb2e8f9f7 4809 /**
<> 144:ef7eb2e8f9f7 4810 * AES0_IV1
<> 144:ef7eb2e8f9f7 4811 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4812 * Offset: 0x134 AES Initial Vector Word 1 Register for Channel 0
<> 144:ef7eb2e8f9f7 4813 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4814 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4815 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4816 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 4817 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4818 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 4819 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 4820 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 4821 */
<> 144:ef7eb2e8f9f7 4822 __IO uint32_t AES0_IV1;
<> 144:ef7eb2e8f9f7 4823
<> 144:ef7eb2e8f9f7 4824 /**
<> 144:ef7eb2e8f9f7 4825 * AES0_IV2
<> 144:ef7eb2e8f9f7 4826 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4827 * Offset: 0x138 AES Initial Vector Word 2 Register for Channel 0
<> 144:ef7eb2e8f9f7 4828 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4829 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4830 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4831 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 4832 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4833 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 4834 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 4835 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 4836 */
<> 144:ef7eb2e8f9f7 4837 __IO uint32_t AES0_IV2;
<> 144:ef7eb2e8f9f7 4838
<> 144:ef7eb2e8f9f7 4839 /**
<> 144:ef7eb2e8f9f7 4840 * AES0_IV3
<> 144:ef7eb2e8f9f7 4841 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4842 * Offset: 0x13C AES Initial Vector Word 3 Register for Channel 0
<> 144:ef7eb2e8f9f7 4843 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4844 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4845 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4846 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 4847 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4848 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 4849 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 4850 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 4851 */
<> 144:ef7eb2e8f9f7 4852 __IO uint32_t AES0_IV3;
<> 144:ef7eb2e8f9f7 4853
<> 144:ef7eb2e8f9f7 4854 /**
<> 144:ef7eb2e8f9f7 4855 * AES0_SADDR
<> 144:ef7eb2e8f9f7 4856 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4857 * Offset: 0x140 AES DMA Source Address Register for Channel 0
<> 144:ef7eb2e8f9f7 4858 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4859 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4860 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4861 * |[0:31] |SADDR |AES DMA Source Address
<> 144:ef7eb2e8f9f7 4862 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 4863 * | | |The AES_SADR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 4864 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
<> 144:ef7eb2e8f9f7 4865 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 4866 * | | |In other words, bit 1 and 0 of AES_SADR are ignored.
<> 144:ef7eb2e8f9f7 4867 * | | |AES_SADR can be read and written.
<> 144:ef7eb2e8f9f7 4868 * | | |Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 4869 * | | |But the value of AES_SADR will be updated later on.
<> 144:ef7eb2e8f9f7 4870 * | | |Consequently, software can prepare the DMA source address for the next AES operation.
<> 144:ef7eb2e8f9f7 4871 * | | |In DMA mode, software can update the next AES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 4872 * | | |The value of AES_SADR and AES_DADR can be the same.
<> 144:ef7eb2e8f9f7 4873 */
<> 144:ef7eb2e8f9f7 4874 __IO uint32_t AES0_SADDR;
<> 144:ef7eb2e8f9f7 4875
<> 144:ef7eb2e8f9f7 4876 /**
<> 144:ef7eb2e8f9f7 4877 * AES0_DADDR
<> 144:ef7eb2e8f9f7 4878 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4879 * Offset: 0x144 AES DMA Destination Address Register for Channel 0
<> 144:ef7eb2e8f9f7 4880 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4881 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4882 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4883 * |[0:31] |DADDR |AES DMA Destination Address
<> 144:ef7eb2e8f9f7 4884 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 4885 * | | |The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
<> 144:ef7eb2e8f9f7 4886 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
<> 144:ef7eb2e8f9f7 4887 * | | |The start of destination address should be located at word boundary.
<> 144:ef7eb2e8f9f7 4888 * | | |In other words, bit 1 and 0 of AES_DADR are ignored.
<> 144:ef7eb2e8f9f7 4889 * | | |AES_DADR can be read and written.
<> 144:ef7eb2e8f9f7 4890 * | | |Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 4891 * | | |But the value of AES_DADR will be updated later on.
<> 144:ef7eb2e8f9f7 4892 * | | |Consequently, software can prepare the destination address for the next AES operation.
<> 144:ef7eb2e8f9f7 4893 * | | |In DMA mode, software can update the next AES_DADR before triggering START.
<> 144:ef7eb2e8f9f7 4894 * | | |The value of AES_SADR and AES_DADR can be the same.
<> 144:ef7eb2e8f9f7 4895 */
<> 144:ef7eb2e8f9f7 4896 __IO uint32_t AES0_DADDR;
<> 144:ef7eb2e8f9f7 4897
<> 144:ef7eb2e8f9f7 4898 /**
<> 144:ef7eb2e8f9f7 4899 * AES0_CNT
<> 144:ef7eb2e8f9f7 4900 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4901 * Offset: 0x148 AES Byte Count Register for Channel 0
<> 144:ef7eb2e8f9f7 4902 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4903 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4904 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4905 * |[0:31] |CNT |AES Byte Count
<> 144:ef7eb2e8f9f7 4906 * | | |The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 4907 * | | |The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 4908 * | | |AES_CNT can be read and written.
<> 144:ef7eb2e8f9f7 4909 * | | |Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 4910 * | | |But the value of AES_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 4911 * | | |Consequently, software can prepare the byte count of data for the next AES operation.
<> 144:ef7eb2e8f9f7 4912 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
<> 144:ef7eb2e8f9f7 4913 * | | |Operations that are less than one block will output unexpected result.
<> 144:ef7eb2e8f9f7 4914 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 4915 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
<> 144:ef7eb2e8f9f7 4916 */
<> 144:ef7eb2e8f9f7 4917 __IO uint32_t AES0_CNT;
<> 144:ef7eb2e8f9f7 4918
<> 144:ef7eb2e8f9f7 4919 /**
<> 144:ef7eb2e8f9f7 4920 * AES1_KEY0
<> 144:ef7eb2e8f9f7 4921 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4922 * Offset: 0x14C AES Key Word 0 Register for Channel 1
<> 144:ef7eb2e8f9f7 4923 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4924 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4925 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4926 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4927 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4928 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4929 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4930 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4931 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4932 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4933 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4934 */
<> 144:ef7eb2e8f9f7 4935 __IO uint32_t AES1_KEY0;
<> 144:ef7eb2e8f9f7 4936
<> 144:ef7eb2e8f9f7 4937 /**
<> 144:ef7eb2e8f9f7 4938 * AES1_KEY1
<> 144:ef7eb2e8f9f7 4939 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4940 * Offset: 0x150 AES Key Word 1 Register for Channel 1
<> 144:ef7eb2e8f9f7 4941 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4942 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4943 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4944 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4945 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4946 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4947 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4948 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4949 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4950 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4951 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4952 */
<> 144:ef7eb2e8f9f7 4953 __IO uint32_t AES1_KEY1;
<> 144:ef7eb2e8f9f7 4954
<> 144:ef7eb2e8f9f7 4955 /**
<> 144:ef7eb2e8f9f7 4956 * AES1_KEY2
<> 144:ef7eb2e8f9f7 4957 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4958 * Offset: 0x154 AES Key Word 2 Register for Channel 1
<> 144:ef7eb2e8f9f7 4959 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4960 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4961 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4962 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4963 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4964 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4965 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4966 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4967 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4968 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4969 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4970 */
<> 144:ef7eb2e8f9f7 4971 __IO uint32_t AES1_KEY2;
<> 144:ef7eb2e8f9f7 4972
<> 144:ef7eb2e8f9f7 4973 /**
<> 144:ef7eb2e8f9f7 4974 * AES1_KEY3
<> 144:ef7eb2e8f9f7 4975 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4976 * Offset: 0x158 AES Key Word 3 Register for Channel 1
<> 144:ef7eb2e8f9f7 4977 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4978 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4979 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4980 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4981 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 4982 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 4983 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 4984 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 4985 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4986 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4987 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 4988 */
<> 144:ef7eb2e8f9f7 4989 __IO uint32_t AES1_KEY3;
<> 144:ef7eb2e8f9f7 4990
<> 144:ef7eb2e8f9f7 4991 /**
<> 144:ef7eb2e8f9f7 4992 * AES1_KEY4
<> 144:ef7eb2e8f9f7 4993 * ===================================================================================================
<> 144:ef7eb2e8f9f7 4994 * Offset: 0x15C AES Key Word 4 Register for Channel 1
<> 144:ef7eb2e8f9f7 4995 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 4996 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 4997 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 4998 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 4999 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5000 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5001 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5002 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5003 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5004 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5005 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5006 */
<> 144:ef7eb2e8f9f7 5007 __IO uint32_t AES1_KEY4;
<> 144:ef7eb2e8f9f7 5008
<> 144:ef7eb2e8f9f7 5009 /**
<> 144:ef7eb2e8f9f7 5010 * AES1_KEY5
<> 144:ef7eb2e8f9f7 5011 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5012 * Offset: 0x160 AES Key Word 5 Register for Channel 1
<> 144:ef7eb2e8f9f7 5013 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5014 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5015 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5016 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5017 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5018 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5019 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5020 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5021 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5022 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5023 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5024 */
<> 144:ef7eb2e8f9f7 5025 __IO uint32_t AES1_KEY5;
<> 144:ef7eb2e8f9f7 5026
<> 144:ef7eb2e8f9f7 5027 /**
<> 144:ef7eb2e8f9f7 5028 * AES1_KEY6
<> 144:ef7eb2e8f9f7 5029 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5030 * Offset: 0x164 AES Key Word 6 Register for Channel 1
<> 144:ef7eb2e8f9f7 5031 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5032 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5033 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5034 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5035 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5036 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5037 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5038 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5039 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5040 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5041 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5042 */
<> 144:ef7eb2e8f9f7 5043 __IO uint32_t AES1_KEY6;
<> 144:ef7eb2e8f9f7 5044
<> 144:ef7eb2e8f9f7 5045 /**
<> 144:ef7eb2e8f9f7 5046 * AES1_KEY7
<> 144:ef7eb2e8f9f7 5047 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5048 * Offset: 0x168 AES Key Word 7 Register for Channel 1
<> 144:ef7eb2e8f9f7 5049 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5050 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5051 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5052 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5053 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5054 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5055 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5056 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5057 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5058 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5059 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5060 */
<> 144:ef7eb2e8f9f7 5061 __IO uint32_t AES1_KEY7;
<> 144:ef7eb2e8f9f7 5062
<> 144:ef7eb2e8f9f7 5063 /**
<> 144:ef7eb2e8f9f7 5064 * AES1_IV0
<> 144:ef7eb2e8f9f7 5065 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5066 * Offset: 0x16C AES Initial Vector Word 0 Register for Channel 1
<> 144:ef7eb2e8f9f7 5067 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5068 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5069 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5070 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5071 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5072 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5073 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5074 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5075 */
<> 144:ef7eb2e8f9f7 5076 __IO uint32_t AES1_IV0;
<> 144:ef7eb2e8f9f7 5077
<> 144:ef7eb2e8f9f7 5078 /**
<> 144:ef7eb2e8f9f7 5079 * AES1_IV1
<> 144:ef7eb2e8f9f7 5080 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5081 * Offset: 0x170 AES Initial Vector Word 1 Register for Channel 1
<> 144:ef7eb2e8f9f7 5082 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5083 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5084 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5085 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5086 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5087 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5088 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5089 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5090 */
<> 144:ef7eb2e8f9f7 5091 __IO uint32_t AES1_IV1;
<> 144:ef7eb2e8f9f7 5092
<> 144:ef7eb2e8f9f7 5093 /**
<> 144:ef7eb2e8f9f7 5094 * AES1_IV2
<> 144:ef7eb2e8f9f7 5095 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5096 * Offset: 0x174 AES Initial Vector Word 2 Register for Channel 1
<> 144:ef7eb2e8f9f7 5097 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5098 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5099 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5100 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5101 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5102 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5103 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5104 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5105 */
<> 144:ef7eb2e8f9f7 5106 __IO uint32_t AES1_IV2;
<> 144:ef7eb2e8f9f7 5107
<> 144:ef7eb2e8f9f7 5108 /**
<> 144:ef7eb2e8f9f7 5109 * AES1_IV3
<> 144:ef7eb2e8f9f7 5110 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5111 * Offset: 0x178 AES Initial Vector Word 3 Register for Channel 1
<> 144:ef7eb2e8f9f7 5112 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5113 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5114 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5115 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5116 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5117 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5118 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5119 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5120 */
<> 144:ef7eb2e8f9f7 5121 __IO uint32_t AES1_IV3;
<> 144:ef7eb2e8f9f7 5122
<> 144:ef7eb2e8f9f7 5123 /**
<> 144:ef7eb2e8f9f7 5124 * AES1_SADDR
<> 144:ef7eb2e8f9f7 5125 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5126 * Offset: 0x17C AES DMA Source Address Register for Channel 1
<> 144:ef7eb2e8f9f7 5127 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5128 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5129 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5130 * |[0:31] |SADDR |AES DMA Source Address
<> 144:ef7eb2e8f9f7 5131 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 5132 * | | |The AES_SADR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 5133 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
<> 144:ef7eb2e8f9f7 5134 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 5135 * | | |In other words, bit 1 and 0 of AES_SADR are ignored.
<> 144:ef7eb2e8f9f7 5136 * | | |AES_SADR can be read and written.
<> 144:ef7eb2e8f9f7 5137 * | | |Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5138 * | | |But the value of AES_SADR will be updated later on.
<> 144:ef7eb2e8f9f7 5139 * | | |Consequently, software can prepare the DMA source address for the next AES operation.
<> 144:ef7eb2e8f9f7 5140 * | | |In DMA mode, software can update the next AES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 5141 * | | |The value of AES_SADR and AES_DADR can be the same.
<> 144:ef7eb2e8f9f7 5142 */
<> 144:ef7eb2e8f9f7 5143 __IO uint32_t AES1_SADDR;
<> 144:ef7eb2e8f9f7 5144
<> 144:ef7eb2e8f9f7 5145 /**
<> 144:ef7eb2e8f9f7 5146 * AES1_DADDR
<> 144:ef7eb2e8f9f7 5147 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5148 * Offset: 0x180 AES DMA Destination Address Register for Channel 1
<> 144:ef7eb2e8f9f7 5149 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5150 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5151 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5152 * |[0:31] |DADDR |AES DMA Destination Address
<> 144:ef7eb2e8f9f7 5153 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 5154 * | | |The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
<> 144:ef7eb2e8f9f7 5155 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
<> 144:ef7eb2e8f9f7 5156 * | | |The start of destination address should be located at word boundary.
<> 144:ef7eb2e8f9f7 5157 * | | |In other words, bit 1 and 0 of AES_DADR are ignored.
<> 144:ef7eb2e8f9f7 5158 * | | |AES_DADR can be read and written.
<> 144:ef7eb2e8f9f7 5159 * | | |Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5160 * | | |But the value of AES_DADR will be updated later on.
<> 144:ef7eb2e8f9f7 5161 * | | |Consequently, software can prepare the destination address for the next AES operation.
<> 144:ef7eb2e8f9f7 5162 * | | |In DMA mode, software can update the next AES_DADR before triggering START.
<> 144:ef7eb2e8f9f7 5163 * | | |The value of AES_SADR and AES_DADR can be the same.
<> 144:ef7eb2e8f9f7 5164 */
<> 144:ef7eb2e8f9f7 5165 __IO uint32_t AES1_DADDR;
<> 144:ef7eb2e8f9f7 5166
<> 144:ef7eb2e8f9f7 5167 /**
<> 144:ef7eb2e8f9f7 5168 * AES1_CNT
<> 144:ef7eb2e8f9f7 5169 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5170 * Offset: 0x184 AES Byte Count Register for Channel 1
<> 144:ef7eb2e8f9f7 5171 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5172 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5173 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5174 * |[0:31] |CNT |AES Byte Count
<> 144:ef7eb2e8f9f7 5175 * | | |The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 5176 * | | |The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 5177 * | | |AES_CNT can be read and written.
<> 144:ef7eb2e8f9f7 5178 * | | |Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5179 * | | |But the value of AES_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 5180 * | | |Consequently, software can prepare the byte count of data for the next AES operation.
<> 144:ef7eb2e8f9f7 5181 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
<> 144:ef7eb2e8f9f7 5182 * | | |Operations that are less than one block will output unexpected result.
<> 144:ef7eb2e8f9f7 5183 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 5184 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
<> 144:ef7eb2e8f9f7 5185 */
<> 144:ef7eb2e8f9f7 5186 __IO uint32_t AES1_CNT;
<> 144:ef7eb2e8f9f7 5187
<> 144:ef7eb2e8f9f7 5188 /**
<> 144:ef7eb2e8f9f7 5189 * AES2_KEY0
<> 144:ef7eb2e8f9f7 5190 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5191 * Offset: 0x188 AES Key Word 0 Register for Channel 2
<> 144:ef7eb2e8f9f7 5192 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5193 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5194 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5195 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5196 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5197 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5198 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5199 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5200 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5201 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5202 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5203 */
<> 144:ef7eb2e8f9f7 5204 __IO uint32_t AES2_KEY0;
<> 144:ef7eb2e8f9f7 5205
<> 144:ef7eb2e8f9f7 5206 /**
<> 144:ef7eb2e8f9f7 5207 * AES2_KEY1
<> 144:ef7eb2e8f9f7 5208 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5209 * Offset: 0x18C AES Key Word 1 Register for Channel 2
<> 144:ef7eb2e8f9f7 5210 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5211 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5212 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5213 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5214 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5215 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5216 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5217 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5218 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5219 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5220 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5221 */
<> 144:ef7eb2e8f9f7 5222 __IO uint32_t AES2_KEY1;
<> 144:ef7eb2e8f9f7 5223
<> 144:ef7eb2e8f9f7 5224 /**
<> 144:ef7eb2e8f9f7 5225 * AES2_KEY2
<> 144:ef7eb2e8f9f7 5226 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5227 * Offset: 0x190 AES Key Word 2 Register for Channel 2
<> 144:ef7eb2e8f9f7 5228 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5229 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5230 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5231 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5232 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5233 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5234 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5235 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5236 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5237 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5238 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5239 */
<> 144:ef7eb2e8f9f7 5240 __IO uint32_t AES2_KEY2;
<> 144:ef7eb2e8f9f7 5241
<> 144:ef7eb2e8f9f7 5242 /**
<> 144:ef7eb2e8f9f7 5243 * AES2_KEY3
<> 144:ef7eb2e8f9f7 5244 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5245 * Offset: 0x194 AES Key Word 3 Register for Channel 2
<> 144:ef7eb2e8f9f7 5246 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5247 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5248 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5249 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5250 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5251 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5252 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5253 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5254 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5255 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5256 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5257 */
<> 144:ef7eb2e8f9f7 5258 __IO uint32_t AES2_KEY3;
<> 144:ef7eb2e8f9f7 5259
<> 144:ef7eb2e8f9f7 5260 /**
<> 144:ef7eb2e8f9f7 5261 * AES2_KEY4
<> 144:ef7eb2e8f9f7 5262 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5263 * Offset: 0x198 AES Key Word 4 Register for Channel 2
<> 144:ef7eb2e8f9f7 5264 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5265 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5266 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5267 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5268 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5269 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5270 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5271 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5272 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5273 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5274 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5275 */
<> 144:ef7eb2e8f9f7 5276 __IO uint32_t AES2_KEY4;
<> 144:ef7eb2e8f9f7 5277
<> 144:ef7eb2e8f9f7 5278 /**
<> 144:ef7eb2e8f9f7 5279 * AES2_KEY5
<> 144:ef7eb2e8f9f7 5280 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5281 * Offset: 0x19C AES Key Word 5 Register for Channel 2
<> 144:ef7eb2e8f9f7 5282 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5283 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5284 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5285 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5286 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5287 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5288 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5289 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5290 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5291 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5292 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5293 */
<> 144:ef7eb2e8f9f7 5294 __IO uint32_t AES2_KEY5;
<> 144:ef7eb2e8f9f7 5295
<> 144:ef7eb2e8f9f7 5296 /**
<> 144:ef7eb2e8f9f7 5297 * AES2_KEY6
<> 144:ef7eb2e8f9f7 5298 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5299 * Offset: 0x1A0 AES Key Word 6 Register for Channel 2
<> 144:ef7eb2e8f9f7 5300 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5301 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5302 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5303 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5304 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5305 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5306 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5307 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5308 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5309 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5310 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5311 */
<> 144:ef7eb2e8f9f7 5312 __IO uint32_t AES2_KEY6;
<> 144:ef7eb2e8f9f7 5313
<> 144:ef7eb2e8f9f7 5314 /**
<> 144:ef7eb2e8f9f7 5315 * AES2_KEY7
<> 144:ef7eb2e8f9f7 5316 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5317 * Offset: 0x1A4 AES Key Word 7 Register for Channel 2
<> 144:ef7eb2e8f9f7 5318 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5319 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5320 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5321 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5322 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5323 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5324 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5325 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5326 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5327 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5328 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5329 */
<> 144:ef7eb2e8f9f7 5330 __IO uint32_t AES2_KEY7;
<> 144:ef7eb2e8f9f7 5331
<> 144:ef7eb2e8f9f7 5332 /**
<> 144:ef7eb2e8f9f7 5333 * AES2_IV0
<> 144:ef7eb2e8f9f7 5334 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5335 * Offset: 0x1A8 AES Initial Vector Word 0 Register for Channel 2
<> 144:ef7eb2e8f9f7 5336 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5337 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5338 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5339 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5340 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5341 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5342 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5343 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5344 */
<> 144:ef7eb2e8f9f7 5345 __IO uint32_t AES2_IV0;
<> 144:ef7eb2e8f9f7 5346
<> 144:ef7eb2e8f9f7 5347 /**
<> 144:ef7eb2e8f9f7 5348 * AES2_IV1
<> 144:ef7eb2e8f9f7 5349 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5350 * Offset: 0x1AC AES Initial Vector Word 1 Register for Channel 2
<> 144:ef7eb2e8f9f7 5351 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5352 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5353 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5354 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5355 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5356 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5357 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5358 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5359 */
<> 144:ef7eb2e8f9f7 5360 __IO uint32_t AES2_IV1;
<> 144:ef7eb2e8f9f7 5361
<> 144:ef7eb2e8f9f7 5362 /**
<> 144:ef7eb2e8f9f7 5363 * AES2_IV2
<> 144:ef7eb2e8f9f7 5364 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5365 * Offset: 0x1B0 AES Initial Vector Word 2 Register for Channel 2
<> 144:ef7eb2e8f9f7 5366 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5367 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5368 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5369 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5370 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5371 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5372 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5373 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5374 */
<> 144:ef7eb2e8f9f7 5375 __IO uint32_t AES2_IV2;
<> 144:ef7eb2e8f9f7 5376
<> 144:ef7eb2e8f9f7 5377 /**
<> 144:ef7eb2e8f9f7 5378 * AES2_IV3
<> 144:ef7eb2e8f9f7 5379 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5380 * Offset: 0x1B4 AES Initial Vector Word 3 Register for Channel 2
<> 144:ef7eb2e8f9f7 5381 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5382 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5383 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5384 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5385 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5386 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5387 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5388 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5389 */
<> 144:ef7eb2e8f9f7 5390 __IO uint32_t AES2_IV3;
<> 144:ef7eb2e8f9f7 5391
<> 144:ef7eb2e8f9f7 5392 /**
<> 144:ef7eb2e8f9f7 5393 * AES2_SADDR
<> 144:ef7eb2e8f9f7 5394 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5395 * Offset: 0x1B8 AES DMA Source Address Register for Channel 2
<> 144:ef7eb2e8f9f7 5396 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5397 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5398 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5399 * |[0:31] |SADDR |AES DMA Source Address
<> 144:ef7eb2e8f9f7 5400 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 5401 * | | |The AES_SADR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 5402 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
<> 144:ef7eb2e8f9f7 5403 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 5404 * | | |In other words, bit 1 and 0 of AES_SADR are ignored.
<> 144:ef7eb2e8f9f7 5405 * | | |AES_SADR can be read and written.
<> 144:ef7eb2e8f9f7 5406 * | | |Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5407 * | | |But the value of AES_SADR will be updated later on.
<> 144:ef7eb2e8f9f7 5408 * | | |Consequently, software can prepare the DMA source address for the next AES operation.
<> 144:ef7eb2e8f9f7 5409 * | | |In DMA mode, software can update the next AES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 5410 * | | |The value of AES_SADR and AES_DADR can be the same.
<> 144:ef7eb2e8f9f7 5411 */
<> 144:ef7eb2e8f9f7 5412 __IO uint32_t AES2_SADDR;
<> 144:ef7eb2e8f9f7 5413
<> 144:ef7eb2e8f9f7 5414 /**
<> 144:ef7eb2e8f9f7 5415 * AES2_DADDR
<> 144:ef7eb2e8f9f7 5416 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5417 * Offset: 0x1BC AES DMA Destination Address Register for Channel 2
<> 144:ef7eb2e8f9f7 5418 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5419 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5420 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5421 * |[0:31] |DADDR |AES DMA Destination Address
<> 144:ef7eb2e8f9f7 5422 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 5423 * | | |The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
<> 144:ef7eb2e8f9f7 5424 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
<> 144:ef7eb2e8f9f7 5425 * | | |The start of destination address should be located at word boundary.
<> 144:ef7eb2e8f9f7 5426 * | | |In other words, bit 1 and 0 of AES_DADR are ignored.
<> 144:ef7eb2e8f9f7 5427 * | | |AES_DADR can be read and written.
<> 144:ef7eb2e8f9f7 5428 * | | |Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5429 * | | |But the value of AES_DADR will be updated later on.
<> 144:ef7eb2e8f9f7 5430 * | | |Consequently, software can prepare the destination address for the next AES operation.
<> 144:ef7eb2e8f9f7 5431 * | | |In DMA mode, software can update the next AES_DADR before triggering START.
<> 144:ef7eb2e8f9f7 5432 * | | |The value of AES_SADR and AES_DADR can be the same.
<> 144:ef7eb2e8f9f7 5433 */
<> 144:ef7eb2e8f9f7 5434 __IO uint32_t AES2_DADDR;
<> 144:ef7eb2e8f9f7 5435
<> 144:ef7eb2e8f9f7 5436 /**
<> 144:ef7eb2e8f9f7 5437 * AES2_CNT
<> 144:ef7eb2e8f9f7 5438 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5439 * Offset: 0x1C0 AES Byte Count Register for Channel 2
<> 144:ef7eb2e8f9f7 5440 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5441 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5442 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5443 * |[0:31] |CNT |AES Byte Count
<> 144:ef7eb2e8f9f7 5444 * | | |The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 5445 * | | |The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 5446 * | | |AES_CNT can be read and written.
<> 144:ef7eb2e8f9f7 5447 * | | |Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5448 * | | |But the value of AES_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 5449 * | | |Consequently, software can prepare the byte count of data for the next AES operation.
<> 144:ef7eb2e8f9f7 5450 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
<> 144:ef7eb2e8f9f7 5451 * | | |Operations that are less than one block will output unexpected result.
<> 144:ef7eb2e8f9f7 5452 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 5453 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
<> 144:ef7eb2e8f9f7 5454 */
<> 144:ef7eb2e8f9f7 5455 __IO uint32_t AES2_CNT;
<> 144:ef7eb2e8f9f7 5456
<> 144:ef7eb2e8f9f7 5457 /**
<> 144:ef7eb2e8f9f7 5458 * AES3_KEY0
<> 144:ef7eb2e8f9f7 5459 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5460 * Offset: 0x1C4 AES Key Word 0 Register for Channel 3
<> 144:ef7eb2e8f9f7 5461 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5462 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5463 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5464 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5465 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5466 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5467 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5468 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5469 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5470 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5471 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5472 */
<> 144:ef7eb2e8f9f7 5473 __IO uint32_t AES3_KEY0;
<> 144:ef7eb2e8f9f7 5474
<> 144:ef7eb2e8f9f7 5475 /**
<> 144:ef7eb2e8f9f7 5476 * AES3_KEY1
<> 144:ef7eb2e8f9f7 5477 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5478 * Offset: 0x1C8 AES Key Word 1 Register for Channel 3
<> 144:ef7eb2e8f9f7 5479 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5480 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5481 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5482 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5483 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5484 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5485 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5486 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5487 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5488 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5489 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5490 */
<> 144:ef7eb2e8f9f7 5491 __IO uint32_t AES3_KEY1;
<> 144:ef7eb2e8f9f7 5492
<> 144:ef7eb2e8f9f7 5493 /**
<> 144:ef7eb2e8f9f7 5494 * AES3_KEY2
<> 144:ef7eb2e8f9f7 5495 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5496 * Offset: 0x1CC AES Key Word 2 Register for Channel 3
<> 144:ef7eb2e8f9f7 5497 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5498 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5499 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5500 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5501 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5502 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5503 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5504 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5505 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5506 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5507 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5508 */
<> 144:ef7eb2e8f9f7 5509 __IO uint32_t AES3_KEY2;
<> 144:ef7eb2e8f9f7 5510
<> 144:ef7eb2e8f9f7 5511 /**
<> 144:ef7eb2e8f9f7 5512 * AES3_KEY3
<> 144:ef7eb2e8f9f7 5513 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5514 * Offset: 0x1D0 AES Key Word 3 Register for Channel 3
<> 144:ef7eb2e8f9f7 5515 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5516 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5517 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5518 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5519 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5520 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5521 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5522 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5523 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5524 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5525 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5526 */
<> 144:ef7eb2e8f9f7 5527 __IO uint32_t AES3_KEY3;
<> 144:ef7eb2e8f9f7 5528
<> 144:ef7eb2e8f9f7 5529 /**
<> 144:ef7eb2e8f9f7 5530 * AES3_KEY4
<> 144:ef7eb2e8f9f7 5531 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5532 * Offset: 0x1D4 AES Key Word 4 Register for Channel 3
<> 144:ef7eb2e8f9f7 5533 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5534 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5535 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5536 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5537 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5538 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5539 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5540 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5541 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5542 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5543 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5544 */
<> 144:ef7eb2e8f9f7 5545 __IO uint32_t AES3_KEY4;
<> 144:ef7eb2e8f9f7 5546
<> 144:ef7eb2e8f9f7 5547 /**
<> 144:ef7eb2e8f9f7 5548 * AES3_KEY5
<> 144:ef7eb2e8f9f7 5549 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5550 * Offset: 0x1D8 AES Key Word 5 Register for Channel 3
<> 144:ef7eb2e8f9f7 5551 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5552 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5553 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5554 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5555 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5556 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5557 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5558 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5559 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5560 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5561 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5562 */
<> 144:ef7eb2e8f9f7 5563 __IO uint32_t AES3_KEY5;
<> 144:ef7eb2e8f9f7 5564
<> 144:ef7eb2e8f9f7 5565 /**
<> 144:ef7eb2e8f9f7 5566 * AES3_KEY6
<> 144:ef7eb2e8f9f7 5567 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5568 * Offset: 0x1DC AES Key Word 6 Register for Channel 3
<> 144:ef7eb2e8f9f7 5569 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5570 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5571 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5572 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5573 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5574 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5575 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5576 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5577 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5578 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5579 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5580 */
<> 144:ef7eb2e8f9f7 5581 __IO uint32_t AES3_KEY6;
<> 144:ef7eb2e8f9f7 5582
<> 144:ef7eb2e8f9f7 5583 /**
<> 144:ef7eb2e8f9f7 5584 * AES3_KEY7
<> 144:ef7eb2e8f9f7 5585 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5586 * Offset: 0x1E0 AES Key Word 7 Register for Channel 3
<> 144:ef7eb2e8f9f7 5587 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5588 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5589 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5590 * |[0:31] |KEY |AES Key X
<> 144:ef7eb2e8f9f7 5591 * | | |The KEY keeps the security key for AES operation.
<> 144:ef7eb2e8f9f7 5592 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5593 * | | |x = 0, 1..7.
<> 144:ef7eb2e8f9f7 5594 * | | |The security key for AES accelerator can be 128, 192, or 256 bits and four, six, or eight 32-bit registers are to store each security key.
<> 144:ef7eb2e8f9f7 5595 * | | |{AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 128-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5596 * | | |{AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 192-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5597 * | | |{AES_KEY7, AES_KEY6, AES_KEY5, AES_KEY4, AES_KEY3, AES_KEY2, AES_KEY1, AES_KEY0} stores the 256-bit security key for AES operation.
<> 144:ef7eb2e8f9f7 5598 */
<> 144:ef7eb2e8f9f7 5599 __IO uint32_t AES3_KEY7;
<> 144:ef7eb2e8f9f7 5600
<> 144:ef7eb2e8f9f7 5601 /**
<> 144:ef7eb2e8f9f7 5602 * AES3_IV0
<> 144:ef7eb2e8f9f7 5603 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5604 * Offset: 0x1E4 AES Initial Vector Word 0 Register for Channel 3
<> 144:ef7eb2e8f9f7 5605 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5606 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5607 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5608 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5609 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5610 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5611 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5612 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5613 */
<> 144:ef7eb2e8f9f7 5614 __IO uint32_t AES3_IV0;
<> 144:ef7eb2e8f9f7 5615
<> 144:ef7eb2e8f9f7 5616 /**
<> 144:ef7eb2e8f9f7 5617 * AES3_IV1
<> 144:ef7eb2e8f9f7 5618 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5619 * Offset: 0x1E8 AES Initial Vector Word 1 Register for Channel 3
<> 144:ef7eb2e8f9f7 5620 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5621 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5622 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5623 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5624 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5625 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5626 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5627 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5628 */
<> 144:ef7eb2e8f9f7 5629 __IO uint32_t AES3_IV1;
<> 144:ef7eb2e8f9f7 5630
<> 144:ef7eb2e8f9f7 5631 /**
<> 144:ef7eb2e8f9f7 5632 * AES3_IV2
<> 144:ef7eb2e8f9f7 5633 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5634 * Offset: 0x1EC AES Initial Vector Word 2 Register for Channel 3
<> 144:ef7eb2e8f9f7 5635 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5636 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5637 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5638 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5639 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5640 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5641 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5642 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5643 */
<> 144:ef7eb2e8f9f7 5644 __IO uint32_t AES3_IV2;
<> 144:ef7eb2e8f9f7 5645
<> 144:ef7eb2e8f9f7 5646 /**
<> 144:ef7eb2e8f9f7 5647 * AES3_IV3
<> 144:ef7eb2e8f9f7 5648 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5649 * Offset: 0x1F0 AES Initial Vector Word 3 Register for Channel 3
<> 144:ef7eb2e8f9f7 5650 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5651 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5652 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5653 * |[0:31] |IV |AES Initial Vector Word X
<> 144:ef7eb2e8f9f7 5654 * | | |n = 0, 1..3.
<> 144:ef7eb2e8f9f7 5655 * | | |x = 0, 1..3.
<> 144:ef7eb2e8f9f7 5656 * | | |Four initial vectors (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) are for AES operating in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5657 * | | |Four registers (AES_IV0, AES_IV1, AES_IV2, and AES_IV3) act as Nonce counter when the AES engine is operating in CTR mode.
<> 144:ef7eb2e8f9f7 5658 */
<> 144:ef7eb2e8f9f7 5659 __IO uint32_t AES3_IV3;
<> 144:ef7eb2e8f9f7 5660
<> 144:ef7eb2e8f9f7 5661 /**
<> 144:ef7eb2e8f9f7 5662 * AES3_SADDR
<> 144:ef7eb2e8f9f7 5663 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5664 * Offset: 0x1F4 AES DMA Source Address Register for Channel 3
<> 144:ef7eb2e8f9f7 5665 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5666 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5667 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5668 * |[0:31] |SADDR |AES DMA Source Address
<> 144:ef7eb2e8f9f7 5669 * | | |The AES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 5670 * | | |The AES_SADR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 5671 * | | |Based on the source address, the AES accelerator can read the plain text from system memory and do AES operation.
<> 144:ef7eb2e8f9f7 5672 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 5673 * | | |In other words, bit 1 and 0 of AES_SADR are ignored.
<> 144:ef7eb2e8f9f7 5674 * | | |AES_SADR can be read and written.
<> 144:ef7eb2e8f9f7 5675 * | | |Writing to AES_SADR while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5676 * | | |But the value of AES_SADR will be updated later on.
<> 144:ef7eb2e8f9f7 5677 * | | |Consequently, software can prepare the DMA source address for the next AES operation.
<> 144:ef7eb2e8f9f7 5678 * | | |In DMA mode, software can update the next AES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 5679 * | | |The value of AES_SADR and AES_DADR can be the same.
<> 144:ef7eb2e8f9f7 5680 */
<> 144:ef7eb2e8f9f7 5681 __IO uint32_t AES3_SADDR;
<> 144:ef7eb2e8f9f7 5682
<> 144:ef7eb2e8f9f7 5683 /**
<> 144:ef7eb2e8f9f7 5684 * AES3_DADDR
<> 144:ef7eb2e8f9f7 5685 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5686 * Offset: 0x1F8 AES DMA Destination Address Register for Channel 3
<> 144:ef7eb2e8f9f7 5687 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5688 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5689 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5690 * |[0:31] |DADDR |AES DMA Destination Address
<> 144:ef7eb2e8f9f7 5691 * | | |The AES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 5692 * | | |The AES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
<> 144:ef7eb2e8f9f7 5693 * | | |Based on the destination address, the AES accelerator can write the cipher text back to system memory after the AES operation is finished.
<> 144:ef7eb2e8f9f7 5694 * | | |The start of destination address should be located at word boundary.
<> 144:ef7eb2e8f9f7 5695 * | | |In other words, bit 1 and 0 of AES_DADR are ignored.
<> 144:ef7eb2e8f9f7 5696 * | | |AES_DADR can be read and written.
<> 144:ef7eb2e8f9f7 5697 * | | |Writing to AES_DADR while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5698 * | | |But the value of AES_DADR will be updated later on.
<> 144:ef7eb2e8f9f7 5699 * | | |Consequently, software can prepare the destination address for the next AES operation.
<> 144:ef7eb2e8f9f7 5700 * | | |In DMA mode, software can update the next AES_DADR before triggering START.
<> 144:ef7eb2e8f9f7 5701 * | | |The value of AES_SADR and AES_DADR can be the same.
<> 144:ef7eb2e8f9f7 5702 */
<> 144:ef7eb2e8f9f7 5703 __IO uint32_t AES3_DADDR;
<> 144:ef7eb2e8f9f7 5704
<> 144:ef7eb2e8f9f7 5705 /**
<> 144:ef7eb2e8f9f7 5706 * AES3_CNT
<> 144:ef7eb2e8f9f7 5707 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5708 * Offset: 0x1FC AES Byte Count Register for Channel 3
<> 144:ef7eb2e8f9f7 5709 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5710 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5711 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5712 * |[0:31] |CNT |AES Byte Count
<> 144:ef7eb2e8f9f7 5713 * | | |The AES_CNT keeps the byte count of source text that is for the AES engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 5714 * | | |The AES_CNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 5715 * | | |AES_CNT can be read and written.
<> 144:ef7eb2e8f9f7 5716 * | | |Writing to AES_CNT while the AES accelerator is operating doesn't affect the current AES operation.
<> 144:ef7eb2e8f9f7 5717 * | | |But the value of AES_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 5718 * | | |Consequently, software can prepare the byte count of data for the next AES operation.
<> 144:ef7eb2e8f9f7 5719 * | | |According to CBC-CS1, CBC-CS2, and CBC-CS3 standard, the count of operation data must be at least one block.
<> 144:ef7eb2e8f9f7 5720 * | | |Operations that are less than one block will output unexpected result.
<> 144:ef7eb2e8f9f7 5721 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, AES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 5722 * | | |In Non-DMA CBC-CS1, CBC-CS2, and CBC-CS3 mode, AES_CNT must be set as byte count for the last two blocks of data before feeding in the last two blocks of data.
<> 144:ef7eb2e8f9f7 5723 */
<> 144:ef7eb2e8f9f7 5724 __IO uint32_t AES3_CNT;
<> 144:ef7eb2e8f9f7 5725
<> 144:ef7eb2e8f9f7 5726 /**
<> 144:ef7eb2e8f9f7 5727 * TDES_CTL
<> 144:ef7eb2e8f9f7 5728 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5729 * Offset: 0x200 TDES/DES Control Register
<> 144:ef7eb2e8f9f7 5730 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5731 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5732 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5733 * |[0] |START |TDES/DES Engine Start
<> 144:ef7eb2e8f9f7 5734 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 5735 * | | |1 = Start TDES/DES engine. The flag BUSY would be set.
<> 144:ef7eb2e8f9f7 5736 * | | |Note: The bit is always 0 when it's read back.
<> 144:ef7eb2e8f9f7 5737 * |[1] |STOP |TDES/DES Engine Stop
<> 144:ef7eb2e8f9f7 5738 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 5739 * | | |1 = Stop TDES/DES engine.
<> 144:ef7eb2e8f9f7 5740 * | | |Note: The bit is always 0 when it's read back.
<> 144:ef7eb2e8f9f7 5741 * |[2] |TMODE |TDES/DES Engine Operating Mode
<> 144:ef7eb2e8f9f7 5742 * | | |0 = Set DES mode for TDES/DES engine.
<> 144:ef7eb2e8f9f7 5743 * | | |1 = Set Triple DES mode for TDES/DES engine.
<> 144:ef7eb2e8f9f7 5744 * |[3] |3KEYS |TDES/DES Key Number
<> 144:ef7eb2e8f9f7 5745 * | | |0 = Select KEY1 and KEY2 in TDES/DES engine.
<> 144:ef7eb2e8f9f7 5746 * | | |1 = Triple keys in TDES/DES engine Enabled.
<> 144:ef7eb2e8f9f7 5747 * |[5] |DMALAST |TDES/DES Engine Start For The Last Block
<> 144:ef7eb2e8f9f7 5748 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
<> 144:ef7eb2e8f9f7 5749 * | | |In Non-DMA mode, this bit must be set as feeding in last block of data.
<> 144:ef7eb2e8f9f7 5750 * |[6] |DMACSCAD |TDES/DES Engine DMA With Cascade Mode
<> 144:ef7eb2e8f9f7 5751 * | | |0 = DMA cascade function Disabled.
<> 144:ef7eb2e8f9f7 5752 * | | |1 = In DMA Cascade mode, software can update DMA source address register, destination address register, and byte count register during a cascade operation, without finishing the accelerator operation.
<> 144:ef7eb2e8f9f7 5753 * |[7] |DMAEN |TDES/DES Engine DMA Enable Control
<> 144:ef7eb2e8f9f7 5754 * | | |0 = TDES_DMA engine Disabled.
<> 144:ef7eb2e8f9f7 5755 * | | |TDES engine operates in Non-DMA mode, and get data from the port CRPT_TDES_DATIN.
<> 144:ef7eb2e8f9f7 5756 * | | |1 = TDES_DMA engine Enabled.
<> 144:ef7eb2e8f9f7 5757 * | | |TDES engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
<> 144:ef7eb2e8f9f7 5758 * |[8:10] |OPMODE |TDES/DES Engine Operation Mode
<> 144:ef7eb2e8f9f7 5759 * | | |0x00 = ECB (Electronic Codebook Mode).
<> 144:ef7eb2e8f9f7 5760 * | | |0x01 = CBC (Cipher Block Chaining Mode).
<> 144:ef7eb2e8f9f7 5761 * | | |0x02 = CFB (Cipher Feedback Mode).
<> 144:ef7eb2e8f9f7 5762 * | | |0x03 = OFB (Output Feedback Mode).
<> 144:ef7eb2e8f9f7 5763 * | | |0x04 = CTR (Counter Mode).
<> 144:ef7eb2e8f9f7 5764 * | | |Others = CTR (Counter Mode).
<> 144:ef7eb2e8f9f7 5765 * |[16] |ENCRPT |TDES/DES Encryption/Decryption
<> 144:ef7eb2e8f9f7 5766 * | | |0 = TDES engine executes decryption operation.
<> 144:ef7eb2e8f9f7 5767 * | | |1 = TDES engine executes encryption operation.
<> 144:ef7eb2e8f9f7 5768 * |[21] |BLKSWAP |TDES/DES Engine Block Double Word Endian Swap
<> 144:ef7eb2e8f9f7 5769 * | | |0 = Keep the original order, e.g. {WORD_H, WORD_L}.
<> 144:ef7eb2e8f9f7 5770 * | | |1 = When this bit is set to 1, the TDES engine would exchange high and low word in the sequence {WORD_L, WORD_H}.
<> 144:ef7eb2e8f9f7 5771 * |[22] |OUTSWAP |TDES/DES Engine Output Data Swap
<> 144:ef7eb2e8f9f7 5772 * | | |0 = Keep the original order.
<> 144:ef7eb2e8f9f7 5773 * | | |1 = The order that CPU outputs data from the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
<> 144:ef7eb2e8f9f7 5774 * |[23] |INSWAP |TDES/DES Engine Input Data Swap
<> 144:ef7eb2e8f9f7 5775 * | | |0 = Keep the original order.
<> 144:ef7eb2e8f9f7 5776 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
<> 144:ef7eb2e8f9f7 5777 * |[24:25] |CHANNEL |TDES/DES Engine Working Channel
<> 144:ef7eb2e8f9f7 5778 * | | |00 = Current control register setting is for channel 0.
<> 144:ef7eb2e8f9f7 5779 * | | |01 = Current control register setting is for channel 1.
<> 144:ef7eb2e8f9f7 5780 * | | |10 = Current control register setting is for channel 2.
<> 144:ef7eb2e8f9f7 5781 * | | |11 = Current control register setting is for channel 3.
<> 144:ef7eb2e8f9f7 5782 * |[26:30] |KEYUNPRT |Unprotect Key
<> 144:ef7eb2e8f9f7 5783 * | | |Writing 0 to CRPT_TDES_CTL [31] and "10110" to CRPT_TDES_CTL [30:26] is to unprotect TDES key.
<> 144:ef7eb2e8f9f7 5784 * | | |The KEYUNPRT can be read and written.
<> 144:ef7eb2e8f9f7 5785 * | | |When it is written as the TDES engine is operating, BUSY flag is 1, there would be no effect on KEYUNPRT.
<> 144:ef7eb2e8f9f7 5786 * |[31] |KEYPRT |Protect Key
<> 144:ef7eb2e8f9f7 5787 * | | |Read as a flag to reflect KEYPRT.
<> 144:ef7eb2e8f9f7 5788 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 5789 * | | |1 = This bit is to protect the content of TDES key from reading.
<> 144:ef7eb2e8f9f7 5790 * | | |The return value for reading CRPT_ TDESn_KEYxH/L is not the content in the registers CRPT_ TDESn_KEYxH/L.
<> 144:ef7eb2e8f9f7 5791 * | | |Once it is set, it can be cleared by asserting KEYUNPRT.
<> 144:ef7eb2e8f9f7 5792 * | | |The key content would be cleared as well.
<> 144:ef7eb2e8f9f7 5793 */
<> 144:ef7eb2e8f9f7 5794 __IO uint32_t TDES_CTL;
<> 144:ef7eb2e8f9f7 5795
<> 144:ef7eb2e8f9f7 5796 /**
<> 144:ef7eb2e8f9f7 5797 * TDES_STS
<> 144:ef7eb2e8f9f7 5798 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5799 * Offset: 0x204 TDES/DES Engine Flag
<> 144:ef7eb2e8f9f7 5800 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5801 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5802 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5803 * |[0] |BUSY |TDES/DES Engine Busy
<> 144:ef7eb2e8f9f7 5804 * | | |0 = TDES/DES engine is idle or finished.
<> 144:ef7eb2e8f9f7 5805 * | | |1 = TDES/DES engine is under processing.
<> 144:ef7eb2e8f9f7 5806 * |[8] |INBUFEMPTY|TDES/DES In Buffer Empty
<> 144:ef7eb2e8f9f7 5807 * | | |0 = There are some data in input buffer waiting for the TDES/DES engine to process.
<> 144:ef7eb2e8f9f7 5808 * | | |1 = TDES/DES input buffer is empty.
<> 144:ef7eb2e8f9f7 5809 * | | |Software needs to feed data to the TDES/DES engine.
<> 144:ef7eb2e8f9f7 5810 * | | |Otherwise, the TDES/DES engine will be pending to wait for input data.
<> 144:ef7eb2e8f9f7 5811 * |[9] |INBUFFULL |TDES/DES In Buffer Full Flag
<> 144:ef7eb2e8f9f7 5812 * | | |0 = TDES/DES input buffer is not full. Software can feed the data into the TDES/DES engine.
<> 144:ef7eb2e8f9f7 5813 * | | |1 = TDES input buffer is full.
<> 144:ef7eb2e8f9f7 5814 * | | |Software cannot feed data to the TDES/DES engine.
<> 144:ef7eb2e8f9f7 5815 * | | |Otherwise, the flag INBUFERR will be set to 1.
<> 144:ef7eb2e8f9f7 5816 * |[10] |INBUFERR |TDES/DES In Buffer Error Flag
<> 144:ef7eb2e8f9f7 5817 * | | |0 = No error.
<> 144:ef7eb2e8f9f7 5818 * | | |1 = Error happens during feeding data to the TDES/DES engine.
<> 144:ef7eb2e8f9f7 5819 * |[16] |OUTBUFEMPTY|TDES/DES Output Buffer Empty Flag
<> 144:ef7eb2e8f9f7 5820 * | | |0 = TDES/DES output buffer is not empty. There are some valid data kept in output buffer.
<> 144:ef7eb2e8f9f7 5821 * | | |1 = TDES/DES output buffer is empty, Software cannot get data from TDES_DATA_OUT.
<> 144:ef7eb2e8f9f7 5822 * | | |Otherwise the flag OUTBUFERR will be set to 1, since output buffer is empty.
<> 144:ef7eb2e8f9f7 5823 * |[17] |OUTBUFFULL|TDES/DES Output Buffer Full Flag
<> 144:ef7eb2e8f9f7 5824 * | | |0 = TDES/DES output buffer is not full.
<> 144:ef7eb2e8f9f7 5825 * | | |1 = TDES/DES output buffer is full, and software needs to get data from TDES_DATA_OUT.
<> 144:ef7eb2e8f9f7 5826 * | | |Otherwise, the TDES/DES engine will be pending since output buffer is full.
<> 144:ef7eb2e8f9f7 5827 * |[18] |OUTBUFERR |TDES/DES Out Buffer Error Flag
<> 144:ef7eb2e8f9f7 5828 * | | |0 = No error.
<> 144:ef7eb2e8f9f7 5829 * | | |1 = Error happens during getting test result from TDES/DES engine.
<> 144:ef7eb2e8f9f7 5830 * |[20] |BUSERR |TDES/DES DMA Access Bus Error Flag
<> 144:ef7eb2e8f9f7 5831 * | | |0 = No error.
<> 144:ef7eb2e8f9f7 5832 * | | |1 = Bus error will stop DMA operation and TDES/DES engine.
<> 144:ef7eb2e8f9f7 5833 */
<> 144:ef7eb2e8f9f7 5834 __I uint32_t TDES_STS;
<> 144:ef7eb2e8f9f7 5835
<> 144:ef7eb2e8f9f7 5836 /**
<> 144:ef7eb2e8f9f7 5837 * TDES0_KEY1H
<> 144:ef7eb2e8f9f7 5838 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5839 * Offset: 0x208 TDES/DES Key 1 High Word Register for Channel 0
<> 144:ef7eb2e8f9f7 5840 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5841 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5842 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5843 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 5844 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 5845 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 5846 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 5847 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 5848 */
<> 144:ef7eb2e8f9f7 5849 __IO uint32_t TDES0_KEY1H;
<> 144:ef7eb2e8f9f7 5850
<> 144:ef7eb2e8f9f7 5851 /**
<> 144:ef7eb2e8f9f7 5852 * TDES0_KEY1L
<> 144:ef7eb2e8f9f7 5853 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5854 * Offset: 0x20C TDES/DES Key 1 Low Word Register for Channel 0
<> 144:ef7eb2e8f9f7 5855 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5856 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5857 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5858 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 5859 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 5860 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 5861 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 5862 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 5863 */
<> 144:ef7eb2e8f9f7 5864 __IO uint32_t TDES0_KEY1L;
<> 144:ef7eb2e8f9f7 5865
<> 144:ef7eb2e8f9f7 5866 /**
<> 144:ef7eb2e8f9f7 5867 * TDES0_KEY2H
<> 144:ef7eb2e8f9f7 5868 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5869 * Offset: 0x210 TDES Key 2 High Word Register for Channel 0
<> 144:ef7eb2e8f9f7 5870 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5871 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5872 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5873 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 5874 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 5875 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 5876 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 5877 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 5878 */
<> 144:ef7eb2e8f9f7 5879 __IO uint32_t TDES0_KEY2H;
<> 144:ef7eb2e8f9f7 5880
<> 144:ef7eb2e8f9f7 5881 /**
<> 144:ef7eb2e8f9f7 5882 * TDES0_KEY2L
<> 144:ef7eb2e8f9f7 5883 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5884 * Offset: 0x214 TDES Key 2 Low Word Register for Channel 0
<> 144:ef7eb2e8f9f7 5885 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5886 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5887 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5888 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 5889 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 5890 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 5891 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 5892 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 5893 */
<> 144:ef7eb2e8f9f7 5894 __IO uint32_t TDES0_KEY2L;
<> 144:ef7eb2e8f9f7 5895
<> 144:ef7eb2e8f9f7 5896 /**
<> 144:ef7eb2e8f9f7 5897 * TDES0_KEY3H
<> 144:ef7eb2e8f9f7 5898 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5899 * Offset: 0x218 TDES Key 3 High Word Register for Channel 0
<> 144:ef7eb2e8f9f7 5900 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5901 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5902 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5903 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 5904 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 5905 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 5906 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 5907 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 5908 */
<> 144:ef7eb2e8f9f7 5909 __IO uint32_t TDES0_KEY3H;
<> 144:ef7eb2e8f9f7 5910
<> 144:ef7eb2e8f9f7 5911 /**
<> 144:ef7eb2e8f9f7 5912 * TDES0_KEY3L
<> 144:ef7eb2e8f9f7 5913 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5914 * Offset: 0x21C TDES Key 3 Low Word Register for Channel 0
<> 144:ef7eb2e8f9f7 5915 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5916 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5917 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5918 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 5919 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 5920 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 5921 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 5922 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 5923 */
<> 144:ef7eb2e8f9f7 5924 __IO uint32_t TDES0_KEY3L;
<> 144:ef7eb2e8f9f7 5925
<> 144:ef7eb2e8f9f7 5926 /**
<> 144:ef7eb2e8f9f7 5927 * TDES0_IVH
<> 144:ef7eb2e8f9f7 5928 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5929 * Offset: 0x220 TDES/DES Initial Vector High Word Register for Channel 0
<> 144:ef7eb2e8f9f7 5930 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5931 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5932 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5933 * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
<> 144:ef7eb2e8f9f7 5934 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5935 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
<> 144:ef7eb2e8f9f7 5936 */
<> 144:ef7eb2e8f9f7 5937 __IO uint32_t TDES0_IVH;
<> 144:ef7eb2e8f9f7 5938
<> 144:ef7eb2e8f9f7 5939 /**
<> 144:ef7eb2e8f9f7 5940 * TDES0_IVL
<> 144:ef7eb2e8f9f7 5941 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5942 * Offset: 0x224 TDES/DES Initial Vector Low Word Register for Channel 0
<> 144:ef7eb2e8f9f7 5943 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5944 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5945 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5946 * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
<> 144:ef7eb2e8f9f7 5947 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 5948 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
<> 144:ef7eb2e8f9f7 5949 */
<> 144:ef7eb2e8f9f7 5950 __IO uint32_t TDES0_IVL;
<> 144:ef7eb2e8f9f7 5951
<> 144:ef7eb2e8f9f7 5952 /**
<> 144:ef7eb2e8f9f7 5953 * TDES0_SADDR
<> 144:ef7eb2e8f9f7 5954 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5955 * Offset: 0x228 TDES/DES DMA Source Address Register for Channel 0
<> 144:ef7eb2e8f9f7 5956 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5957 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5958 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5959 * |[0:31] |SADDR |TDES/DES DMA Source Address
<> 144:ef7eb2e8f9f7 5960 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 5961 * | | |The TDES_SADR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 5962 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
<> 144:ef7eb2e8f9f7 5963 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 5964 * | | |In other words, bit 1 and 0 of TDES_SADR are ignored.
<> 144:ef7eb2e8f9f7 5965 * | | |TDES_SADR can be read and written.
<> 144:ef7eb2e8f9f7 5966 * | | |Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 5967 * | | |But the value of TDES_SADR will be updated later on.
<> 144:ef7eb2e8f9f7 5968 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
<> 144:ef7eb2e8f9f7 5969 * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 5970 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 5971 */
<> 144:ef7eb2e8f9f7 5972 __IO uint32_t TDES0_SADDR;
<> 144:ef7eb2e8f9f7 5973
<> 144:ef7eb2e8f9f7 5974 /**
<> 144:ef7eb2e8f9f7 5975 * TDES0_DADDR
<> 144:ef7eb2e8f9f7 5976 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5977 * Offset: 0x22C TDES/DES DMA Destination Address Register for Channel 0
<> 144:ef7eb2e8f9f7 5978 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 5979 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 5980 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 5981 * |[0:31] |DADDR |TDES/DES DMA Destination Address
<> 144:ef7eb2e8f9f7 5982 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 5983 * | | |The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
<> 144:ef7eb2e8f9f7 5984 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
<> 144:ef7eb2e8f9f7 5985 * | | |The start of destination address should be located at word boundary.
<> 144:ef7eb2e8f9f7 5986 * | | |In other words, bit 1 and 0 of TDES_DADR are ignored.
<> 144:ef7eb2e8f9f7 5987 * | | |TDES_DADR can be read and written.
<> 144:ef7eb2e8f9f7 5988 * | | |Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 5989 * | | |But the value of TDES_DADR will be updated later on.
<> 144:ef7eb2e8f9f7 5990 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
<> 144:ef7eb2e8f9f7 5991 * | | |In DMA mode, software can update the next TDES_DADR before triggering START.
<> 144:ef7eb2e8f9f7 5992 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 5993 */
<> 144:ef7eb2e8f9f7 5994 __IO uint32_t TDES0_DADDR;
<> 144:ef7eb2e8f9f7 5995
<> 144:ef7eb2e8f9f7 5996 /**
<> 144:ef7eb2e8f9f7 5997 * TDES0_CNT
<> 144:ef7eb2e8f9f7 5998 * ===================================================================================================
<> 144:ef7eb2e8f9f7 5999 * Offset: 0x230 TDES/DES Byte Count Register for Channel 0
<> 144:ef7eb2e8f9f7 6000 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6001 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6002 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6003 * |[0:31] |CNT |TDES/DES Byte Count
<> 144:ef7eb2e8f9f7 6004 * | | |The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 6005 * | | |The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 6006 * | | |TDES_CNT can be read and written.
<> 144:ef7eb2e8f9f7 6007 * | | |Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6008 * | | |But the value of TDES_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 6009 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
<> 144:ef7eb2e8f9f7 6010 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 6011 */
<> 144:ef7eb2e8f9f7 6012 __IO uint32_t TDES0_CNT;
<> 144:ef7eb2e8f9f7 6013
<> 144:ef7eb2e8f9f7 6014 /**
<> 144:ef7eb2e8f9f7 6015 * TDES_DATIN
<> 144:ef7eb2e8f9f7 6016 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6017 * Offset: 0x234 TDES/DES Engine Input data Word Register
<> 144:ef7eb2e8f9f7 6018 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6019 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6020 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6021 * |[0:31] |DATIN |TDES/DES Engine Input Port
<> 144:ef7eb2e8f9f7 6022 * | | |CPU feeds data to TDES/DES engine through this port by checking CRPT_TDES_STS.
<> 144:ef7eb2e8f9f7 6023 * | | |Feed data as INBUFFULL is 0.
<> 144:ef7eb2e8f9f7 6024 */
<> 144:ef7eb2e8f9f7 6025 __IO uint32_t TDES_DATIN;
<> 144:ef7eb2e8f9f7 6026
<> 144:ef7eb2e8f9f7 6027 /**
<> 144:ef7eb2e8f9f7 6028 * TDES_DATOUT
<> 144:ef7eb2e8f9f7 6029 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6030 * Offset: 0x238 TDES/DES Engine Output data Word Register
<> 144:ef7eb2e8f9f7 6031 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6032 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6033 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6034 * |[0:31] |DATOUT |TDES/DES Engine Output Port
<> 144:ef7eb2e8f9f7 6035 * | | |CPU gets result from the TDES/DES engine through this port by checking CRPT_TDES_STS.
<> 144:ef7eb2e8f9f7 6036 * | | |Get data as OUTBUFEMPTY is 0.
<> 144:ef7eb2e8f9f7 6037 */
<> 144:ef7eb2e8f9f7 6038 __I uint32_t TDES_DATOUT;
<> 144:ef7eb2e8f9f7 6039 uint32_t RESERVE2[3];
<> 144:ef7eb2e8f9f7 6040
<> 144:ef7eb2e8f9f7 6041
<> 144:ef7eb2e8f9f7 6042 /**
<> 144:ef7eb2e8f9f7 6043 * TDES1_KEY1H
<> 144:ef7eb2e8f9f7 6044 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6045 * Offset: 0x248 TDES/DES Key 1 High Word Register for Channel 1
<> 144:ef7eb2e8f9f7 6046 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6047 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6048 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6049 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6050 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6051 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6052 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6053 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6054 */
<> 144:ef7eb2e8f9f7 6055 __IO uint32_t TDES1_KEY1H;
<> 144:ef7eb2e8f9f7 6056
<> 144:ef7eb2e8f9f7 6057 /**
<> 144:ef7eb2e8f9f7 6058 * TDES1_KEY1L
<> 144:ef7eb2e8f9f7 6059 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6060 * Offset: 0x24C TDES/DES Key 1 Low Word Register for Channel 1
<> 144:ef7eb2e8f9f7 6061 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6062 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6063 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6064 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6065 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6066 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6067 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6068 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6069 */
<> 144:ef7eb2e8f9f7 6070 __IO uint32_t TDES1_KEY1L;
<> 144:ef7eb2e8f9f7 6071
<> 144:ef7eb2e8f9f7 6072 /**
<> 144:ef7eb2e8f9f7 6073 * TDES1_KEY2H
<> 144:ef7eb2e8f9f7 6074 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6075 * Offset: 0x250 TDES Key 2 High Word Register for Channel 1
<> 144:ef7eb2e8f9f7 6076 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6077 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6078 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6079 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6080 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6081 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6082 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6083 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6084 */
<> 144:ef7eb2e8f9f7 6085 __IO uint32_t TDES1_KEY2H;
<> 144:ef7eb2e8f9f7 6086
<> 144:ef7eb2e8f9f7 6087 /**
<> 144:ef7eb2e8f9f7 6088 * TDES1_KEY2L
<> 144:ef7eb2e8f9f7 6089 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6090 * Offset: 0x254 TDES Key 2 Low Word Register for Channel 1
<> 144:ef7eb2e8f9f7 6091 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6092 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6093 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6094 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6095 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6096 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6097 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6098 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6099 */
<> 144:ef7eb2e8f9f7 6100 __IO uint32_t TDES1_KEY2L;
<> 144:ef7eb2e8f9f7 6101
<> 144:ef7eb2e8f9f7 6102 /**
<> 144:ef7eb2e8f9f7 6103 * TDES1_KEY3H
<> 144:ef7eb2e8f9f7 6104 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6105 * Offset: 0x258 TDES Key 3 High Word Register for Channel 1
<> 144:ef7eb2e8f9f7 6106 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6107 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6108 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6109 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6110 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6111 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6112 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6113 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6114 */
<> 144:ef7eb2e8f9f7 6115 __IO uint32_t TDES1_KEY3H;
<> 144:ef7eb2e8f9f7 6116
<> 144:ef7eb2e8f9f7 6117 /**
<> 144:ef7eb2e8f9f7 6118 * TDES1_KEY3L
<> 144:ef7eb2e8f9f7 6119 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6120 * Offset: 0x25C TDES Key 3 Low Word Register for Channel 1
<> 144:ef7eb2e8f9f7 6121 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6122 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6123 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6124 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6125 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6126 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6127 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6128 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6129 */
<> 144:ef7eb2e8f9f7 6130 __IO uint32_t TDES1_KEY3L;
<> 144:ef7eb2e8f9f7 6131
<> 144:ef7eb2e8f9f7 6132 /**
<> 144:ef7eb2e8f9f7 6133 * TDES1_IVH
<> 144:ef7eb2e8f9f7 6134 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6135 * Offset: 0x260 TDES/DES Initial Vector High Word Register for Channel 1
<> 144:ef7eb2e8f9f7 6136 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6137 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6138 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6139 * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
<> 144:ef7eb2e8f9f7 6140 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 6141 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
<> 144:ef7eb2e8f9f7 6142 */
<> 144:ef7eb2e8f9f7 6143 __IO uint32_t TDES1_IVH;
<> 144:ef7eb2e8f9f7 6144
<> 144:ef7eb2e8f9f7 6145 /**
<> 144:ef7eb2e8f9f7 6146 * TDES1_IVL
<> 144:ef7eb2e8f9f7 6147 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6148 * Offset: 0x264 TDES/DES Initial Vector Low Word Register for Channel 1
<> 144:ef7eb2e8f9f7 6149 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6150 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6151 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6152 * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
<> 144:ef7eb2e8f9f7 6153 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 6154 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
<> 144:ef7eb2e8f9f7 6155 */
<> 144:ef7eb2e8f9f7 6156 __IO uint32_t TDES1_IVL;
<> 144:ef7eb2e8f9f7 6157
<> 144:ef7eb2e8f9f7 6158 /**
<> 144:ef7eb2e8f9f7 6159 * TDES1_SADDR
<> 144:ef7eb2e8f9f7 6160 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6161 * Offset: 0x268 TDES/DES DMA Source Address Register for Channel 1
<> 144:ef7eb2e8f9f7 6162 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6163 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6164 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6165 * |[0:31] |SADDR |TDES/DES DMA Source Address
<> 144:ef7eb2e8f9f7 6166 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 6167 * | | |The TDES_SADR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 6168 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
<> 144:ef7eb2e8f9f7 6169 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 6170 * | | |In other words, bit 1 and 0 of TDES_SADR are ignored.
<> 144:ef7eb2e8f9f7 6171 * | | |TDES_SADR can be read and written.
<> 144:ef7eb2e8f9f7 6172 * | | |Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6173 * | | |But the value of TDES_SADR will be updated later on.
<> 144:ef7eb2e8f9f7 6174 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
<> 144:ef7eb2e8f9f7 6175 * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 6176 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 6177 */
<> 144:ef7eb2e8f9f7 6178 __IO uint32_t TDES1_SADDR;
<> 144:ef7eb2e8f9f7 6179
<> 144:ef7eb2e8f9f7 6180 /**
<> 144:ef7eb2e8f9f7 6181 * TDES1_DADDR
<> 144:ef7eb2e8f9f7 6182 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6183 * Offset: 0x26C TDES/DES DMA Destination Address Register for Channel 1
<> 144:ef7eb2e8f9f7 6184 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6185 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6186 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6187 * |[0:31] |DADDR |TDES/DES DMA Destination Address
<> 144:ef7eb2e8f9f7 6188 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 6189 * | | |The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
<> 144:ef7eb2e8f9f7 6190 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
<> 144:ef7eb2e8f9f7 6191 * | | |The start of destination address should be located at word boundary.
<> 144:ef7eb2e8f9f7 6192 * | | |In other words, bit 1 and 0 of TDES_DADR are ignored.
<> 144:ef7eb2e8f9f7 6193 * | | |TDES_DADR can be read and written.
<> 144:ef7eb2e8f9f7 6194 * | | |Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6195 * | | |But the value of TDES_DADR will be updated later on.
<> 144:ef7eb2e8f9f7 6196 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
<> 144:ef7eb2e8f9f7 6197 * | | |In DMA mode, software can update the next TDES_DADR before triggering START.
<> 144:ef7eb2e8f9f7 6198 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 6199 */
<> 144:ef7eb2e8f9f7 6200 __IO uint32_t TDES1_DADDR;
<> 144:ef7eb2e8f9f7 6201
<> 144:ef7eb2e8f9f7 6202 /**
<> 144:ef7eb2e8f9f7 6203 * TDES1_CNT
<> 144:ef7eb2e8f9f7 6204 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6205 * Offset: 0x270 TDES/DES Byte Count Register for Channel 1
<> 144:ef7eb2e8f9f7 6206 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6207 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6208 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6209 * |[0:31] |CNT |TDES/DES Byte Count
<> 144:ef7eb2e8f9f7 6210 * | | |The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 6211 * | | |The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 6212 * | | |TDES_CNT can be read and written.
<> 144:ef7eb2e8f9f7 6213 * | | |Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6214 * | | |But the value of TDES_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 6215 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
<> 144:ef7eb2e8f9f7 6216 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 6217 */
<> 144:ef7eb2e8f9f7 6218 __IO uint32_t TDES1_CNT;
<> 144:ef7eb2e8f9f7 6219 uint32_t RESERVE3[5];
<> 144:ef7eb2e8f9f7 6220
<> 144:ef7eb2e8f9f7 6221
<> 144:ef7eb2e8f9f7 6222 /**
<> 144:ef7eb2e8f9f7 6223 * TDES2_KEY1H
<> 144:ef7eb2e8f9f7 6224 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6225 * Offset: 0x288 TDES/DES Key 1 High Word Register for Channel 2
<> 144:ef7eb2e8f9f7 6226 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6227 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6228 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6229 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6230 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6231 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6232 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6233 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6234 */
<> 144:ef7eb2e8f9f7 6235 __IO uint32_t TDES2_KEY1H;
<> 144:ef7eb2e8f9f7 6236
<> 144:ef7eb2e8f9f7 6237 /**
<> 144:ef7eb2e8f9f7 6238 * TDES2_KEY1L
<> 144:ef7eb2e8f9f7 6239 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6240 * Offset: 0x28C TDES/DES Key 1 Low Word Register for Channel 2
<> 144:ef7eb2e8f9f7 6241 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6242 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6243 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6244 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6245 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6246 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6247 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6248 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6249 */
<> 144:ef7eb2e8f9f7 6250 __IO uint32_t TDES2_KEY1L;
<> 144:ef7eb2e8f9f7 6251
<> 144:ef7eb2e8f9f7 6252 /**
<> 144:ef7eb2e8f9f7 6253 * TDES2_KEY2H
<> 144:ef7eb2e8f9f7 6254 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6255 * Offset: 0x290 TDES Key 2 High Word Register for Channel 2
<> 144:ef7eb2e8f9f7 6256 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6257 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6258 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6259 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6260 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6261 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6262 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6263 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6264 */
<> 144:ef7eb2e8f9f7 6265 __IO uint32_t TDES2_KEY2H;
<> 144:ef7eb2e8f9f7 6266
<> 144:ef7eb2e8f9f7 6267 /**
<> 144:ef7eb2e8f9f7 6268 * TDES2_KEY2L
<> 144:ef7eb2e8f9f7 6269 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6270 * Offset: 0x294 TDES Key 2 Low Word Register for Channel 2
<> 144:ef7eb2e8f9f7 6271 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6272 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6273 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6274 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6275 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6276 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6277 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6278 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6279 */
<> 144:ef7eb2e8f9f7 6280 __IO uint32_t TDES2_KEY2L;
<> 144:ef7eb2e8f9f7 6281
<> 144:ef7eb2e8f9f7 6282 /**
<> 144:ef7eb2e8f9f7 6283 * TDES2_KEY3H
<> 144:ef7eb2e8f9f7 6284 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6285 * Offset: 0x298 TDES Key 3 High Word Register for Channel 2
<> 144:ef7eb2e8f9f7 6286 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6287 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6288 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6289 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6290 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6291 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6292 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6293 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6294 */
<> 144:ef7eb2e8f9f7 6295 __IO uint32_t TDES2_KEY3H;
<> 144:ef7eb2e8f9f7 6296
<> 144:ef7eb2e8f9f7 6297 /**
<> 144:ef7eb2e8f9f7 6298 * TDES2_KEY3L
<> 144:ef7eb2e8f9f7 6299 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6300 * Offset: 0x29C TDES Key 3 Low Word Register for Channel 2
<> 144:ef7eb2e8f9f7 6301 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6302 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6303 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6304 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6305 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6306 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6307 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6308 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6309 */
<> 144:ef7eb2e8f9f7 6310 __IO uint32_t TDES2_KEY3L;
<> 144:ef7eb2e8f9f7 6311
<> 144:ef7eb2e8f9f7 6312 /**
<> 144:ef7eb2e8f9f7 6313 * TDES2_IVH
<> 144:ef7eb2e8f9f7 6314 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6315 * Offset: 0x2A0 TDES/DES Initial Vector High Word Register for Channel 2
<> 144:ef7eb2e8f9f7 6316 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6317 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6318 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6319 * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
<> 144:ef7eb2e8f9f7 6320 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 6321 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
<> 144:ef7eb2e8f9f7 6322 */
<> 144:ef7eb2e8f9f7 6323 __IO uint32_t TDES2_IVH;
<> 144:ef7eb2e8f9f7 6324
<> 144:ef7eb2e8f9f7 6325 /**
<> 144:ef7eb2e8f9f7 6326 * TDES2_IVL
<> 144:ef7eb2e8f9f7 6327 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6328 * Offset: 0x2A4 TDES/DES Initial Vector Low Word Register for Channel 2
<> 144:ef7eb2e8f9f7 6329 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6330 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6331 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6332 * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
<> 144:ef7eb2e8f9f7 6333 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 6334 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
<> 144:ef7eb2e8f9f7 6335 */
<> 144:ef7eb2e8f9f7 6336 __IO uint32_t TDES2_IVL;
<> 144:ef7eb2e8f9f7 6337
<> 144:ef7eb2e8f9f7 6338 /**
<> 144:ef7eb2e8f9f7 6339 * TDES2_SADDR
<> 144:ef7eb2e8f9f7 6340 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6341 * Offset: 0x2A8 TDES/DES DMA Source Address Register for Channel 2
<> 144:ef7eb2e8f9f7 6342 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6343 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6344 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6345 * |[0:31] |SADDR |TDES/DES DMA Source Address
<> 144:ef7eb2e8f9f7 6346 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 6347 * | | |The TDES_SADR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 6348 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
<> 144:ef7eb2e8f9f7 6349 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 6350 * | | |In other words, bit 1 and 0 of TDES_SADR are ignored.
<> 144:ef7eb2e8f9f7 6351 * | | |TDES_SADR can be read and written.
<> 144:ef7eb2e8f9f7 6352 * | | |Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6353 * | | |But the value of TDES_SADR will be updated later on.
<> 144:ef7eb2e8f9f7 6354 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
<> 144:ef7eb2e8f9f7 6355 * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 6356 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 6357 */
<> 144:ef7eb2e8f9f7 6358 __IO uint32_t TDES2_SADDR;
<> 144:ef7eb2e8f9f7 6359
<> 144:ef7eb2e8f9f7 6360 /**
<> 144:ef7eb2e8f9f7 6361 * TDES2_DADDR
<> 144:ef7eb2e8f9f7 6362 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6363 * Offset: 0x2AC TDES/DES DMA Destination Address Register for Channel 2
<> 144:ef7eb2e8f9f7 6364 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6365 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6366 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6367 * |[0:31] |DADDR |TDES/DES DMA Destination Address
<> 144:ef7eb2e8f9f7 6368 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 6369 * | | |The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
<> 144:ef7eb2e8f9f7 6370 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
<> 144:ef7eb2e8f9f7 6371 * | | |The start of destination address should be located at word boundary.
<> 144:ef7eb2e8f9f7 6372 * | | |In other words, bit 1 and 0 of TDES_DADR are ignored.
<> 144:ef7eb2e8f9f7 6373 * | | |TDES_DADR can be read and written.
<> 144:ef7eb2e8f9f7 6374 * | | |Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6375 * | | |But the value of TDES_DADR will be updated later on.
<> 144:ef7eb2e8f9f7 6376 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
<> 144:ef7eb2e8f9f7 6377 * | | |In DMA mode, software can update the next TDES_DADR before triggering START.
<> 144:ef7eb2e8f9f7 6378 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 6379 */
<> 144:ef7eb2e8f9f7 6380 __IO uint32_t TDES2_DADDR;
<> 144:ef7eb2e8f9f7 6381
<> 144:ef7eb2e8f9f7 6382 /**
<> 144:ef7eb2e8f9f7 6383 * TDES2_CNT
<> 144:ef7eb2e8f9f7 6384 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6385 * Offset: 0x2B0 TDES/DES Byte Count Register for Channel 2
<> 144:ef7eb2e8f9f7 6386 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6387 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6388 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6389 * |[0:31] |CNT |TDES/DES Byte Count
<> 144:ef7eb2e8f9f7 6390 * | | |The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 6391 * | | |The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 6392 * | | |TDES_CNT can be read and written.
<> 144:ef7eb2e8f9f7 6393 * | | |Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6394 * | | |But the value of TDES_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 6395 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
<> 144:ef7eb2e8f9f7 6396 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 6397 */
<> 144:ef7eb2e8f9f7 6398 __IO uint32_t TDES2_CNT;
<> 144:ef7eb2e8f9f7 6399 uint32_t RESERVE4[5];
<> 144:ef7eb2e8f9f7 6400
<> 144:ef7eb2e8f9f7 6401
<> 144:ef7eb2e8f9f7 6402 /**
<> 144:ef7eb2e8f9f7 6403 * TDES3_KEY1H
<> 144:ef7eb2e8f9f7 6404 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6405 * Offset: 0x2C8 TDES/DES Key 1 High Word Register for Channel 3
<> 144:ef7eb2e8f9f7 6406 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6407 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6408 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6409 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6410 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6411 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6412 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6413 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6414 */
<> 144:ef7eb2e8f9f7 6415 __IO uint32_t TDES3_KEY1H;
<> 144:ef7eb2e8f9f7 6416
<> 144:ef7eb2e8f9f7 6417 /**
<> 144:ef7eb2e8f9f7 6418 * TDES3_KEY1L
<> 144:ef7eb2e8f9f7 6419 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6420 * Offset: 0x2CC TDES/DES Key 1 Low Word Register for Channel 3
<> 144:ef7eb2e8f9f7 6421 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6422 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6423 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6424 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6425 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6426 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6427 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6428 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6429 */
<> 144:ef7eb2e8f9f7 6430 __IO uint32_t TDES3_KEY1L;
<> 144:ef7eb2e8f9f7 6431
<> 144:ef7eb2e8f9f7 6432 /**
<> 144:ef7eb2e8f9f7 6433 * TDES3_KEY2H
<> 144:ef7eb2e8f9f7 6434 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6435 * Offset: 0x2D0 TDES Key 2 High Word Register for Channel 3
<> 144:ef7eb2e8f9f7 6436 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6437 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6438 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6439 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6440 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6441 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6442 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6443 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6444 */
<> 144:ef7eb2e8f9f7 6445 __IO uint32_t TDES3_KEY2H;
<> 144:ef7eb2e8f9f7 6446
<> 144:ef7eb2e8f9f7 6447 /**
<> 144:ef7eb2e8f9f7 6448 * TDES3_KEY2L
<> 144:ef7eb2e8f9f7 6449 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6450 * Offset: 0x2D4 TDES Key 2 Low Word Register for Channel 3
<> 144:ef7eb2e8f9f7 6451 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6452 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6453 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6454 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6455 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6456 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6457 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6458 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6459 */
<> 144:ef7eb2e8f9f7 6460 __IO uint32_t TDES3_KEY2L;
<> 144:ef7eb2e8f9f7 6461
<> 144:ef7eb2e8f9f7 6462 /**
<> 144:ef7eb2e8f9f7 6463 * TDES3_KEY3H
<> 144:ef7eb2e8f9f7 6464 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6465 * Offset: 0x2D8 TDES Key 3 High Word Register for Channel 3
<> 144:ef7eb2e8f9f7 6466 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6467 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6468 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6469 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6470 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6471 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6472 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6473 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6474 */
<> 144:ef7eb2e8f9f7 6475 __IO uint32_t TDES3_KEY3H;
<> 144:ef7eb2e8f9f7 6476
<> 144:ef7eb2e8f9f7 6477 /**
<> 144:ef7eb2e8f9f7 6478 * TDES3_KEY3L
<> 144:ef7eb2e8f9f7 6479 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6480 * Offset: 0x2DC TDES Key 3 Low Word Register for Channel 3
<> 144:ef7eb2e8f9f7 6481 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6482 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6483 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6484 * |[0:31] |KEYH_KEYL |TDES/DES Key X High/Low Word
<> 144:ef7eb2e8f9f7 6485 * | | |The key registers for TDES/DES algorithm calculation
<> 144:ef7eb2e8f9f7 6486 * | | |The security key for the TDES/DES accelerator is 64 bits.
<> 144:ef7eb2e8f9f7 6487 * | | |Thus, it needs two 32-bit registers to store a security key.
<> 144:ef7eb2e8f9f7 6488 * | | |The register TDES_KEYxH is used to keep the bit [63:32] of security key for the TDES/DES operation, while the register TDES_KEYxL is used to keep the bit [31:0].
<> 144:ef7eb2e8f9f7 6489 */
<> 144:ef7eb2e8f9f7 6490 __IO uint32_t TDES3_KEY3L;
<> 144:ef7eb2e8f9f7 6491
<> 144:ef7eb2e8f9f7 6492 /**
<> 144:ef7eb2e8f9f7 6493 * TDES3_IVH
<> 144:ef7eb2e8f9f7 6494 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6495 * Offset: 0x2E0 TDES/DES Initial Vector High Word Register for Channel 3
<> 144:ef7eb2e8f9f7 6496 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6497 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6498 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6499 * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
<> 144:ef7eb2e8f9f7 6500 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 6501 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
<> 144:ef7eb2e8f9f7 6502 */
<> 144:ef7eb2e8f9f7 6503 __IO uint32_t TDES3_IVH;
<> 144:ef7eb2e8f9f7 6504
<> 144:ef7eb2e8f9f7 6505 /**
<> 144:ef7eb2e8f9f7 6506 * TDES3_IVL
<> 144:ef7eb2e8f9f7 6507 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6508 * Offset: 0x2E4 TDES/DES Initial Vector Low Word Register for Channel 3
<> 144:ef7eb2e8f9f7 6509 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6510 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6511 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6512 * |[0:31] |IVH_IVL |TDES/DES Initial Vector High/Low Word
<> 144:ef7eb2e8f9f7 6513 * | | |Initial vector (IV) is for TDES/DES engine in CBC, CFB, and OFB mode.
<> 144:ef7eb2e8f9f7 6514 * | | |IV is Nonce counter for TDES/DES engine in CTR mode.
<> 144:ef7eb2e8f9f7 6515 */
<> 144:ef7eb2e8f9f7 6516 __IO uint32_t TDES3_IVL;
<> 144:ef7eb2e8f9f7 6517
<> 144:ef7eb2e8f9f7 6518 /**
<> 144:ef7eb2e8f9f7 6519 * TDES3_SADDR
<> 144:ef7eb2e8f9f7 6520 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6521 * Offset: 0x2E8 TDES/DES DMA Source Address Register for Channel 3
<> 144:ef7eb2e8f9f7 6522 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6523 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6524 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6525 * |[0:31] |SADDR |TDES/DES DMA Source Address
<> 144:ef7eb2e8f9f7 6526 * | | |The TDES/DES accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 6527 * | | |The TDES_SADR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 6528 * | | |Based on the source address, the TDES/DES accelerator can read the plain text from system memory and do TDES/DES operation.
<> 144:ef7eb2e8f9f7 6529 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 6530 * | | |In other words, bit 1 and 0 of TDES_SADR are ignored.
<> 144:ef7eb2e8f9f7 6531 * | | |TDES_SADR can be read and written.
<> 144:ef7eb2e8f9f7 6532 * | | |Writing to TDES_SADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6533 * | | |But the value of TDES_SADR will be updated later on.
<> 144:ef7eb2e8f9f7 6534 * | | |Consequently, software can prepare the DMA source address for the next TDES/DES operation.
<> 144:ef7eb2e8f9f7 6535 * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 6536 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 6537 */
<> 144:ef7eb2e8f9f7 6538 __IO uint32_t TDES3_SADDR;
<> 144:ef7eb2e8f9f7 6539
<> 144:ef7eb2e8f9f7 6540 /**
<> 144:ef7eb2e8f9f7 6541 * TDES3_DADDR
<> 144:ef7eb2e8f9f7 6542 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6543 * Offset: 0x2EC TDES/DES DMA Destination Address Register for Channel 3
<> 144:ef7eb2e8f9f7 6544 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6545 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6546 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6547 * |[0:31] |DADDR |TDES/DES DMA Destination Address
<> 144:ef7eb2e8f9f7 6548 * | | |The TDES/DES accelerator supports DMA function to transfer the cipher text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 6549 * | | |The TDES_DADR keeps the destination address of the data buffer where the engine output's text will be stored.
<> 144:ef7eb2e8f9f7 6550 * | | |Based on the destination address, the TDES/DES accelerator can write the cipher text back to system memory after the TDES/DES operation is finished.
<> 144:ef7eb2e8f9f7 6551 * | | |The start of destination address should be located at word boundary.
<> 144:ef7eb2e8f9f7 6552 * | | |In other words, bit 1 and 0 of TDES_DADR are ignored.
<> 144:ef7eb2e8f9f7 6553 * | | |TDES_DADR can be read and written.
<> 144:ef7eb2e8f9f7 6554 * | | |Writing to TDES_DADR while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6555 * | | |But the value of TDES_DADR will be updated later on.
<> 144:ef7eb2e8f9f7 6556 * | | |Consequently, software can prepare the destination address for the next TDES/DES operation.
<> 144:ef7eb2e8f9f7 6557 * | | |In DMA mode, software can update the next TDES_DADR before triggering START.
<> 144:ef7eb2e8f9f7 6558 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 6559 */
<> 144:ef7eb2e8f9f7 6560 __IO uint32_t TDES3_DADDR;
<> 144:ef7eb2e8f9f7 6561
<> 144:ef7eb2e8f9f7 6562 /**
<> 144:ef7eb2e8f9f7 6563 * TDES3_CNT
<> 144:ef7eb2e8f9f7 6564 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6565 * Offset: 0x2F0 TDES/DES Byte Count Register for Channel 3
<> 144:ef7eb2e8f9f7 6566 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6567 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6568 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6569 * |[0:31] |CNT |TDES/DES Byte Count
<> 144:ef7eb2e8f9f7 6570 * | | |The TDES_CNT keeps the byte count of source text that is for the TDES/DES engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 6571 * | | |The TDES_CNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 6572 * | | |TDES_CNT can be read and written.
<> 144:ef7eb2e8f9f7 6573 * | | |Writing to TDES_CNT while the TDES/DES accelerator is operating doesn't affect the current TDES/DES operation.
<> 144:ef7eb2e8f9f7 6574 * | | |But the value of TDES_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 6575 * | | |Consequently, software can prepare the byte count of data for the next TDES /DES operation.
<> 144:ef7eb2e8f9f7 6576 * | | |In Non-DMA ECB, CBC, CFB, OFB, and CTR mode, TDES_CNT must be set as byte count for the last block of data before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 6577 */
<> 144:ef7eb2e8f9f7 6578 __IO uint32_t TDES3_CNT;
<> 144:ef7eb2e8f9f7 6579 uint32_t RESERVE5[3];
<> 144:ef7eb2e8f9f7 6580
<> 144:ef7eb2e8f9f7 6581
<> 144:ef7eb2e8f9f7 6582 /**
<> 144:ef7eb2e8f9f7 6583 * SHA_CTL
<> 144:ef7eb2e8f9f7 6584 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6585 * Offset: 0x300 SHA Control Register
<> 144:ef7eb2e8f9f7 6586 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6587 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6588 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6589 * |[0] |START |SHA Engine Start
<> 144:ef7eb2e8f9f7 6590 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 6591 * | | |1 = Start SHA engine. BUSY flag will be set.
<> 144:ef7eb2e8f9f7 6592 * | | |Note: This bit is always 0 when it's read back.
<> 144:ef7eb2e8f9f7 6593 * |[1] |STOP |SHA Engine Stop
<> 144:ef7eb2e8f9f7 6594 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 6595 * | | |1 = Stop SHA engine.
<> 144:ef7eb2e8f9f7 6596 * | | |Note: This bit is always 0 when it's read back.
<> 144:ef7eb2e8f9f7 6597 * |[5] |DMALAST |SHA Last Block
<> 144:ef7eb2e8f9f7 6598 * | | |In DMA mode, this bit must be set as beginning the last DMA cascade round.
<> 144:ef7eb2e8f9f7 6599 * | | |In Non-DMA mode, this bit must be set as feeding in last byte of data.
<> 144:ef7eb2e8f9f7 6600 * |[7] |DMAEN |SHA Engine DMA Enable Control
<> 144:ef7eb2e8f9f7 6601 * | | |0 = SHA_DMA engine Disabled.
<> 144:ef7eb2e8f9f7 6602 * | | |The SHA engine operates in Non-DMA mode, and gets data from the port CRPT_SHA_DATIN.
<> 144:ef7eb2e8f9f7 6603 * | | |1 = SHA_DMA engine Enabled.
<> 144:ef7eb2e8f9f7 6604 * | | |The SHA engine operates in DMA mode, and data movement from/to the engine is done by DMA logic.
<> 144:ef7eb2e8f9f7 6605 * |[8:10] |OPMODE |SHA Engine Operation Modes
<> 144:ef7eb2e8f9f7 6606 * | | |000 = SHA160.
<> 144:ef7eb2e8f9f7 6607 * | | |100 = SHA256.
<> 144:ef7eb2e8f9f7 6608 * | | |101 = SHA224.
<> 144:ef7eb2e8f9f7 6609 * | | |Note: These bits can be read and written, but writing to them wouldn't take effect as BUSY is 1.
<> 144:ef7eb2e8f9f7 6610 * |[22] |OUTSWAP |SHA Engine Output Data Swap
<> 144:ef7eb2e8f9f7 6611 * | | |0 = Keep the original order.
<> 144:ef7eb2e8f9f7 6612 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
<> 144:ef7eb2e8f9f7 6613 * |[23] |INSWAP |SHA Engine Input Data Swap
<> 144:ef7eb2e8f9f7 6614 * | | |0 = Keep the original order.
<> 144:ef7eb2e8f9f7 6615 * | | |1 = The order that CPU feeds data to the accelerator will be changed from {byte3, byte2, byte1, byte0} to {byte0, byte1, byte2, byte3}.
<> 144:ef7eb2e8f9f7 6616 */
<> 144:ef7eb2e8f9f7 6617 __IO uint32_t SHA_CTL;
<> 144:ef7eb2e8f9f7 6618
<> 144:ef7eb2e8f9f7 6619 /**
<> 144:ef7eb2e8f9f7 6620 * SHA_STS
<> 144:ef7eb2e8f9f7 6621 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6622 * Offset: 0x304 SHA Status Flag
<> 144:ef7eb2e8f9f7 6623 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6624 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6625 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6626 * |[0] |BUSY |SHA Engine Busy
<> 144:ef7eb2e8f9f7 6627 * | | |0 = SHA engine is idle or finished.
<> 144:ef7eb2e8f9f7 6628 * | | |1 = SHA engine is busy.
<> 144:ef7eb2e8f9f7 6629 * |[1] |DMABUSY |SHA Engine DMA Busy Flag
<> 144:ef7eb2e8f9f7 6630 * | | |0 = SHA DMA engine is idle or finished.
<> 144:ef7eb2e8f9f7 6631 * | | |1 = SHA DMA engine is busy.
<> 144:ef7eb2e8f9f7 6632 * |[8] |DMAERR |SHA Engine DMA Error Flag
<> 144:ef7eb2e8f9f7 6633 * | | |0 = Show the SHA engine access normal.
<> 144:ef7eb2e8f9f7 6634 * | | |1 = Show the SHA engine access error.
<> 144:ef7eb2e8f9f7 6635 * |[16] |DATINREQ |SHA Non-DMA Mode Data Input Request
<> 144:ef7eb2e8f9f7 6636 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 6637 * | | |1 = Request SHA Non-DMA mode data input.
<> 144:ef7eb2e8f9f7 6638 */
<> 144:ef7eb2e8f9f7 6639 __I uint32_t SHA_STS;
<> 144:ef7eb2e8f9f7 6640
<> 144:ef7eb2e8f9f7 6641 /**
<> 144:ef7eb2e8f9f7 6642 * SHA_DGST0
<> 144:ef7eb2e8f9f7 6643 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6644 * Offset: 0x308 SHA Digest Message 0
<> 144:ef7eb2e8f9f7 6645 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6646 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6647 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6648 * |[0:31] |DGST |SHA Digest Message Word
<> 144:ef7eb2e8f9f7 6649 * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
<> 144:ef7eb2e8f9f7 6650 * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
<> 144:ef7eb2e8f9f7 6651 * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
<> 144:ef7eb2e8f9f7 6652 */
<> 144:ef7eb2e8f9f7 6653 __I uint32_t SHA_DGST0;
<> 144:ef7eb2e8f9f7 6654
<> 144:ef7eb2e8f9f7 6655 /**
<> 144:ef7eb2e8f9f7 6656 * SHA_DGST1
<> 144:ef7eb2e8f9f7 6657 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6658 * Offset: 0x30C SHA Digest Message 1
<> 144:ef7eb2e8f9f7 6659 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6660 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6661 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6662 * |[0:31] |DGST |SHA Digest Message Word
<> 144:ef7eb2e8f9f7 6663 * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
<> 144:ef7eb2e8f9f7 6664 * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
<> 144:ef7eb2e8f9f7 6665 * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
<> 144:ef7eb2e8f9f7 6666 */
<> 144:ef7eb2e8f9f7 6667 __I uint32_t SHA_DGST1;
<> 144:ef7eb2e8f9f7 6668
<> 144:ef7eb2e8f9f7 6669 /**
<> 144:ef7eb2e8f9f7 6670 * SHA_DGST2
<> 144:ef7eb2e8f9f7 6671 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6672 * Offset: 0x310 SHA Digest Message 2
<> 144:ef7eb2e8f9f7 6673 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6674 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6675 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6676 * |[0:31] |DGST |SHA Digest Message Word
<> 144:ef7eb2e8f9f7 6677 * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
<> 144:ef7eb2e8f9f7 6678 * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
<> 144:ef7eb2e8f9f7 6679 * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
<> 144:ef7eb2e8f9f7 6680 */
<> 144:ef7eb2e8f9f7 6681 __I uint32_t SHA_DGST2;
<> 144:ef7eb2e8f9f7 6682
<> 144:ef7eb2e8f9f7 6683 /**
<> 144:ef7eb2e8f9f7 6684 * SHA_DGST3
<> 144:ef7eb2e8f9f7 6685 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6686 * Offset: 0x314 SHA Digest Message 3
<> 144:ef7eb2e8f9f7 6687 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6688 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6689 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6690 * |[0:31] |DGST |SHA Digest Message Word
<> 144:ef7eb2e8f9f7 6691 * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
<> 144:ef7eb2e8f9f7 6692 * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
<> 144:ef7eb2e8f9f7 6693 * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
<> 144:ef7eb2e8f9f7 6694 */
<> 144:ef7eb2e8f9f7 6695 __I uint32_t SHA_DGST3;
<> 144:ef7eb2e8f9f7 6696
<> 144:ef7eb2e8f9f7 6697 /**
<> 144:ef7eb2e8f9f7 6698 * SHA_DGST4
<> 144:ef7eb2e8f9f7 6699 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6700 * Offset: 0x318 SHA Digest Message 4
<> 144:ef7eb2e8f9f7 6701 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6702 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6703 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6704 * |[0:31] |DGST |SHA Digest Message Word
<> 144:ef7eb2e8f9f7 6705 * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
<> 144:ef7eb2e8f9f7 6706 * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
<> 144:ef7eb2e8f9f7 6707 * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
<> 144:ef7eb2e8f9f7 6708 */
<> 144:ef7eb2e8f9f7 6709 __I uint32_t SHA_DGST4;
<> 144:ef7eb2e8f9f7 6710
<> 144:ef7eb2e8f9f7 6711 /**
<> 144:ef7eb2e8f9f7 6712 * SHA_DGST5
<> 144:ef7eb2e8f9f7 6713 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6714 * Offset: 0x31C SHA Digest Message 5
<> 144:ef7eb2e8f9f7 6715 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6716 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6717 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6718 * |[0:31] |DGST |SHA Digest Message Word
<> 144:ef7eb2e8f9f7 6719 * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
<> 144:ef7eb2e8f9f7 6720 * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
<> 144:ef7eb2e8f9f7 6721 * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
<> 144:ef7eb2e8f9f7 6722 */
<> 144:ef7eb2e8f9f7 6723 __I uint32_t SHA_DGST5;
<> 144:ef7eb2e8f9f7 6724
<> 144:ef7eb2e8f9f7 6725 /**
<> 144:ef7eb2e8f9f7 6726 * SHA_DGST6
<> 144:ef7eb2e8f9f7 6727 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6728 * Offset: 0x320 SHA Digest Message 6
<> 144:ef7eb2e8f9f7 6729 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6730 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6731 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6732 * |[0:31] |DGST |SHA Digest Message Word
<> 144:ef7eb2e8f9f7 6733 * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
<> 144:ef7eb2e8f9f7 6734 * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
<> 144:ef7eb2e8f9f7 6735 * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
<> 144:ef7eb2e8f9f7 6736 */
<> 144:ef7eb2e8f9f7 6737 __I uint32_t SHA_DGST6;
<> 144:ef7eb2e8f9f7 6738
<> 144:ef7eb2e8f9f7 6739 /**
<> 144:ef7eb2e8f9f7 6740 * SHA_DGST7
<> 144:ef7eb2e8f9f7 6741 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6742 * Offset: 0x324 SHA Digest Message 7
<> 144:ef7eb2e8f9f7 6743 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6744 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6745 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6746 * |[0:31] |DGST |SHA Digest Message Word
<> 144:ef7eb2e8f9f7 6747 * | | |For SHA-160, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST4.
<> 144:ef7eb2e8f9f7 6748 * | | |For SHA-224, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST6.
<> 144:ef7eb2e8f9f7 6749 * | | |For SHA-256, the digest is stored in CRPT_SHA_DGST0 ~ CRPT_SHA_DGST7.
<> 144:ef7eb2e8f9f7 6750 */
<> 144:ef7eb2e8f9f7 6751 __I uint32_t SHA_DGST7;
<> 144:ef7eb2e8f9f7 6752 uint32_t RESERVE6[8];
<> 144:ef7eb2e8f9f7 6753
<> 144:ef7eb2e8f9f7 6754
<> 144:ef7eb2e8f9f7 6755 /**
<> 144:ef7eb2e8f9f7 6756 * SHA_KEYCNT
<> 144:ef7eb2e8f9f7 6757 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6758 * Offset: 0x348 SHA Key Byte Count Register
<> 144:ef7eb2e8f9f7 6759 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6760 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6761 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6762 * |[0:31] |KEYCNT |SHA Key Byte Count
<> 144:ef7eb2e8f9f7 6763 * | | |The CRPT_SHA_KEYCNT keeps the byte count of key that SHA engine operates.
<> 144:ef7eb2e8f9f7 6764 * | | |The register is 32-bit and the maximum byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 6765 * | | |It can be read and written.
<> 144:ef7eb2e8f9f7 6766 * | | |Writing to the register CRPT_SHA_KEYCNT as the SHA accelerator operating doesn't affect the current SHA operation.
<> 144:ef7eb2e8f9f7 6767 * | | |But the value of SHA _KEY_CNT will be updated later on.
<> 144:ef7eb2e8f9f7 6768 * | | |Consequently, software can prepare the key count for the next SHA operation.
<> 144:ef7eb2e8f9f7 6769 */
<> 144:ef7eb2e8f9f7 6770 __IO uint32_t SHA_KEYCNT;
<> 144:ef7eb2e8f9f7 6771
<> 144:ef7eb2e8f9f7 6772 /**
<> 144:ef7eb2e8f9f7 6773 * SHA_SADDR
<> 144:ef7eb2e8f9f7 6774 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6775 * Offset: 0x34C SHA DMA Source Address Register
<> 144:ef7eb2e8f9f7 6776 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6777 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6778 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6779 * |[0:31] |SADDR |SHA DMA Source Address
<> 144:ef7eb2e8f9f7 6780 * | | |The SHA accelerator supports DMA function to transfer the plain text between system memory and embedded FIFO.
<> 144:ef7eb2e8f9f7 6781 * | | |The CRPT_SHA_SADDR keeps the source address of the data buffer where the source text is stored.
<> 144:ef7eb2e8f9f7 6782 * | | |Based on the source address, the SHA accelerator can read the plain text from system memory and do SHA operation.
<> 144:ef7eb2e8f9f7 6783 * | | |The start of source address should be located at word boundary.
<> 144:ef7eb2e8f9f7 6784 * | | |In other words, bit 1 and 0 of CRPT_SHA_SADDR are ignored.
<> 144:ef7eb2e8f9f7 6785 * | | |CRPT_SHA_SADDR can be read and written.
<> 144:ef7eb2e8f9f7 6786 * | | |Writing to CRPT_SHA_SADDR while the SHA accelerator is operating doesn't affect the current SHA operation.
<> 144:ef7eb2e8f9f7 6787 * | | |But the value of CRPT_SHA_SADDR will be updated later on.
<> 144:ef7eb2e8f9f7 6788 * | | |Consequently, software can prepare the DMA source address for the next SHA operation.
<> 144:ef7eb2e8f9f7 6789 * | | |In DMA mode, software can update the next TDES_SADR before triggering START.
<> 144:ef7eb2e8f9f7 6790 * | | |TDES_SADR and TDES_DADR can be the same in the value.
<> 144:ef7eb2e8f9f7 6791 */
<> 144:ef7eb2e8f9f7 6792 __IO uint32_t SHA_SADDR;
<> 144:ef7eb2e8f9f7 6793
<> 144:ef7eb2e8f9f7 6794 /**
<> 144:ef7eb2e8f9f7 6795 * SHA_DMACNT
<> 144:ef7eb2e8f9f7 6796 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6797 * Offset: 0x350 SHA Byte Count Register
<> 144:ef7eb2e8f9f7 6798 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6799 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6800 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6801 * |[0:31] |DMACNT |SHA Operation Byte Count
<> 144:ef7eb2e8f9f7 6802 * | | |The CRPT_SHA_DMACNT keeps the byte count of source text that is for the SHA engine operating in DMA mode.
<> 144:ef7eb2e8f9f7 6803 * | | |The CRPT_SHA_DMACNT is 32-bit and the maximum of byte count is 4G bytes.
<> 144:ef7eb2e8f9f7 6804 * | | |CRPT_SHA_DMACNT can be read and written.
<> 144:ef7eb2e8f9f7 6805 * | | |Writing to CRPT_SHA_DMACNT while the SHA accelerator is operating doesn't affect the current SHA operation.
<> 144:ef7eb2e8f9f7 6806 * | | |But the value of CRPT_SHA_DMACNT will be updated later on.
<> 144:ef7eb2e8f9f7 6807 * | | |Consequently, software can prepare the byte count of data for the next SHA operation.
<> 144:ef7eb2e8f9f7 6808 * | | |In Non-DMA mode, CRPT_SHA_DMACNT must be set as the byte count of the last block before feeding in the last block of data.
<> 144:ef7eb2e8f9f7 6809 */
<> 144:ef7eb2e8f9f7 6810 __IO uint32_t SHA_DMACNT;
<> 144:ef7eb2e8f9f7 6811
<> 144:ef7eb2e8f9f7 6812 /**
<> 144:ef7eb2e8f9f7 6813 * SHA_DATIN
<> 144:ef7eb2e8f9f7 6814 * ===================================================================================================
<> 144:ef7eb2e8f9f7 6815 * Offset: 0x354 SHA Engine Non-DMA Mode Data Input Port Register
<> 144:ef7eb2e8f9f7 6816 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 6817 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 6818 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 6819 * |[0:31] |DATIN |SHA Engine Input Port
<> 144:ef7eb2e8f9f7 6820 * | | |CPU feeds data to SHA engine through this port by checking CRPT_SHA_STS. Feed data as DATINREQ is 1.
<> 144:ef7eb2e8f9f7 6821 */
<> 144:ef7eb2e8f9f7 6822 __IO uint32_t SHA_DATIN;
<> 144:ef7eb2e8f9f7 6823
<> 144:ef7eb2e8f9f7 6824 } CRPT_T;
<> 144:ef7eb2e8f9f7 6825
<> 144:ef7eb2e8f9f7 6826 /**
<> 144:ef7eb2e8f9f7 6827 @addtogroup CRPT_CONST CRPT Bit Field Definition
<> 144:ef7eb2e8f9f7 6828 Constant Definitions for CRPT Controller
<> 144:ef7eb2e8f9f7 6829 @{ */
<> 144:ef7eb2e8f9f7 6830
<> 144:ef7eb2e8f9f7 6831 #define CRPT_INTEN_AESIEN_Pos (0) /*!< CRPT INTEN: AESIEN Position */
<> 144:ef7eb2e8f9f7 6832 #define CRPT_INTEN_AESIEN_Msk (0x1ul << CRPT_INTEN_AESIEN_Pos) /*!< CRPT INTEN: AESIEN Mask */
<> 144:ef7eb2e8f9f7 6833
<> 144:ef7eb2e8f9f7 6834 #define CRPT_INTEN_AESERRIEN_Pos (1) /*!< CRPT INTEN: AESERRIEN Position */
<> 144:ef7eb2e8f9f7 6835 #define CRPT_INTEN_AESERRIEN_Msk (0x1ul << CRPT_INTEN_AESERRIEN_Pos) /*!< CRPT INTEN: AESERRIEN Mask */
<> 144:ef7eb2e8f9f7 6836
<> 144:ef7eb2e8f9f7 6837 #define CRPT_INTEN_TDESIEN_Pos (8) /*!< CRPT INTEN: TDESIEN Position */
<> 144:ef7eb2e8f9f7 6838 #define CRPT_INTEN_TDESIEN_Msk (0x1ul << CRPT_INTEN_TDESIEN_Pos) /*!< CRPT INTEN: TDESIEN Mask */
<> 144:ef7eb2e8f9f7 6839
<> 144:ef7eb2e8f9f7 6840 #define CRPT_INTEN_TDESERRIEN_Pos (9) /*!< CRPT INTEN: TDESERRIEN Position */
<> 144:ef7eb2e8f9f7 6841 #define CRPT_INTEN_TDESERRIEN_Msk (0x1ul << CRPT_INTEN_TDESERRIEN_Pos) /*!< CRPT INTEN: TDESERRIEN Mask */
<> 144:ef7eb2e8f9f7 6842
<> 144:ef7eb2e8f9f7 6843 #define CRPT_INTEN_PRNGIEN_Pos (16) /*!< CRPT INTEN: PRNGIEN Position */
<> 144:ef7eb2e8f9f7 6844 #define CRPT_INTEN_PRNGIEN_Msk (0x1ul << CRPT_INTEN_PRNGIEN_Pos) /*!< CRPT INTEN: PRNGIEN Mask */
<> 144:ef7eb2e8f9f7 6845
<> 144:ef7eb2e8f9f7 6846 #define CRPT_INTEN_SHAIEN_Pos (24) /*!< CRPT INTEN: SHAIEN Position */
<> 144:ef7eb2e8f9f7 6847 #define CRPT_INTEN_SHAIEN_Msk (0x1ul << CRPT_INTEN_SHAIEN_Pos) /*!< CRPT INTEN: SHAIEN Mask */
<> 144:ef7eb2e8f9f7 6848
<> 144:ef7eb2e8f9f7 6849 #define CRPT_INTEN_SHAERRIEN_Pos (25) /*!< CRPT INTEN: SHAERRIEN Position */
<> 144:ef7eb2e8f9f7 6850 #define CRPT_INTEN_SHAERRIEN_Msk (0x1ul << CRPT_INTEN_SHAERRIEN_Pos) /*!< CRPT INTEN: SHAERRIEN Mask */
<> 144:ef7eb2e8f9f7 6851
<> 144:ef7eb2e8f9f7 6852 #define CRPT_INTSTS_AESIF_Pos (0) /*!< CRPT INTSTS: AESIF Position */
<> 144:ef7eb2e8f9f7 6853 #define CRPT_INTSTS_AESIF_Msk (0x1ul << CRPT_INTSTS_AESIF_Pos) /*!< CRPT INTSTS: AESIF Mask */
<> 144:ef7eb2e8f9f7 6854
<> 144:ef7eb2e8f9f7 6855 #define CRPT_INTSTS_AESERRIF_Pos (1) /*!< CRPT INTSTS: AESERRIF Position */
<> 144:ef7eb2e8f9f7 6856 #define CRPT_INTSTS_AESERRIF_Msk (0x1ul << CRPT_INTSTS_AESERRIF_Pos) /*!< CRPT INTSTS: AESERRIF Mask */
<> 144:ef7eb2e8f9f7 6857
<> 144:ef7eb2e8f9f7 6858 #define CRPT_INTSTS_TDESIF_Pos (8) /*!< CRPT INTSTS: TDESIF Position */
<> 144:ef7eb2e8f9f7 6859 #define CRPT_INTSTS_TDESIF_Msk (0x1ul << CRPT_INTSTS_TDESIF_Pos) /*!< CRPT INTSTS: TDESIF Mask */
<> 144:ef7eb2e8f9f7 6860
<> 144:ef7eb2e8f9f7 6861 #define CRPT_INTSTS_TDESERRIF_Pos (9) /*!< CRPT INTSTS: TDESERRIF Position */
<> 144:ef7eb2e8f9f7 6862 #define CRPT_INTSTS_TDESERRIF_Msk (0x1ul << CRPT_INTSTS_TDESERRIF_Pos) /*!< CRPT INTSTS: TDESERRIF Mask */
<> 144:ef7eb2e8f9f7 6863
<> 144:ef7eb2e8f9f7 6864 #define CRPT_INTSTS_PRNGIF_Pos (16) /*!< CRPT INTSTS: PRNGIF Position */
<> 144:ef7eb2e8f9f7 6865 #define CRPT_INTSTS_PRNGIF_Msk (0x1ul << CRPT_INTSTS_PRNGIF_Pos) /*!< CRPT INTSTS: PRNGIF Mask */
<> 144:ef7eb2e8f9f7 6866
<> 144:ef7eb2e8f9f7 6867 #define CRPT_INTSTS_SHAIF_Pos (24) /*!< CRPT INTSTS: SHAIF Position */
<> 144:ef7eb2e8f9f7 6868 #define CRPT_INTSTS_SHAIF_Msk (0x1ul << CRPT_INTSTS_SHAIF_Pos) /*!< CRPT INTSTS: SHAIF Mask */
<> 144:ef7eb2e8f9f7 6869
<> 144:ef7eb2e8f9f7 6870 #define CRPT_INTSTS_SHAERRIF_Pos (25) /*!< CRPT INTSTS: SHAERRIF Position */
<> 144:ef7eb2e8f9f7 6871 #define CRPT_INTSTS_SHAERRIF_Msk (0x1ul << CRPT_INTSTS_SHAERRIF_Pos) /*!< CRPT INTSTS: SHAERRIF Mask */
<> 144:ef7eb2e8f9f7 6872
<> 144:ef7eb2e8f9f7 6873 #define CRPT_PRNG_CTL_START_Pos (0) /*!< CRPT PRNG_CTL: START Position */
<> 144:ef7eb2e8f9f7 6874 #define CRPT_PRNG_CTL_START_Msk (0x1ul << CRPT_PRNG_CTL_START_Pos) /*!< CRPT PRNG_CTL: START Mask */
<> 144:ef7eb2e8f9f7 6875
<> 144:ef7eb2e8f9f7 6876 #define CRPT_PRNG_CTL_SEEDRLD_Pos (1) /*!< CRPT PRNG_CTL: SEEDRLD Position */
<> 144:ef7eb2e8f9f7 6877 #define CRPT_PRNG_CTL_SEEDRLD_Msk (0x1ul << CRPT_PRNG_CTL_SEEDRLD_Pos) /*!< CRPT PRNG_CTL: SEEDRLD Mask */
<> 144:ef7eb2e8f9f7 6878
<> 144:ef7eb2e8f9f7 6879 #define CRPT_PRNG_CTL_KEYSZ_Pos (2) /*!< CRPT PRNG_CTL: KEYSZ Position */
<> 144:ef7eb2e8f9f7 6880 #define CRPT_PRNG_CTL_KEYSZ_Msk (0x3ul << CRPT_PRNG_CTL_KEYSZ_Pos) /*!< CRPT PRNG_CTL: KEYSZ Mask */
<> 144:ef7eb2e8f9f7 6881
<> 144:ef7eb2e8f9f7 6882 #define CRPT_PRNG_CTL_BUSY_Pos (8) /*!< CRPT PRNG_CTL: BUSY Position */
<> 144:ef7eb2e8f9f7 6883 #define CRPT_PRNG_CTL_BUSY_Msk (0x1ul << CRPT_PRNG_CTL_BUSY_Pos) /*!< CRPT PRNG_CTL: BUSY Mask */
<> 144:ef7eb2e8f9f7 6884
<> 144:ef7eb2e8f9f7 6885 #define CRPT_PRNG_SEED_SEED_Pos (0) /*!< CRPT PRNG_SEED: SEED Position */
<> 144:ef7eb2e8f9f7 6886 #define CRPT_PRNG_SEED_SEED_Msk (0xfffffffful << CRPT_PRNG_SEED_SEED_Pos) /*!< CRPT PRNG_SEED: SEED Mask */
<> 144:ef7eb2e8f9f7 6887
<> 144:ef7eb2e8f9f7 6888 #define CRPT_PRNG_KEY0_KEY_Pos (0) /*!< CRPT PRNG_KEY0: KEY Position */
<> 144:ef7eb2e8f9f7 6889 #define CRPT_PRNG_KEY0_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY0_KEY_Pos) /*!< CRPT PRNG_KEY0: KEY Mask */
<> 144:ef7eb2e8f9f7 6890
<> 144:ef7eb2e8f9f7 6891 #define CRPT_PRNG_KEY1_KEY_Pos (0) /*!< CRPT PRNG_KEY1: KEY Position */
<> 144:ef7eb2e8f9f7 6892 #define CRPT_PRNG_KEY1_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY1_KEY_Pos) /*!< CRPT PRNG_KEY1: KEY Mask */
<> 144:ef7eb2e8f9f7 6893
<> 144:ef7eb2e8f9f7 6894 #define CRPT_PRNG_KEY2_KEY_Pos (0) /*!< CRPT PRNG_KEY2: KEY Position */
<> 144:ef7eb2e8f9f7 6895 #define CRPT_PRNG_KEY2_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY2_KEY_Pos) /*!< CRPT PRNG_KEY2: KEY Mask */
<> 144:ef7eb2e8f9f7 6896
<> 144:ef7eb2e8f9f7 6897 #define CRPT_PRNG_KEY3_KEY_Pos (0) /*!< CRPT PRNG_KEY3: KEY Position */
<> 144:ef7eb2e8f9f7 6898 #define CRPT_PRNG_KEY3_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY3_KEY_Pos) /*!< CRPT PRNG_KEY3: KEY Mask */
<> 144:ef7eb2e8f9f7 6899
<> 144:ef7eb2e8f9f7 6900 #define CRPT_PRNG_KEY4_KEY_Pos (0) /*!< CRPT PRNG_KEY4: KEY Position */
<> 144:ef7eb2e8f9f7 6901 #define CRPT_PRNG_KEY4_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY4_KEY_Pos) /*!< CRPT PRNG_KEY4: KEY Mask */
<> 144:ef7eb2e8f9f7 6902
<> 144:ef7eb2e8f9f7 6903 #define CRPT_PRNG_KEY5_KEY_Pos (0) /*!< CRPT PRNG_KEY5: KEY Position */
<> 144:ef7eb2e8f9f7 6904 #define CRPT_PRNG_KEY5_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY5_KEY_Pos) /*!< CRPT PRNG_KEY5: KEY Mask */
<> 144:ef7eb2e8f9f7 6905
<> 144:ef7eb2e8f9f7 6906 #define CRPT_PRNG_KEY6_KEY_Pos (0) /*!< CRPT PRNG_KEY6: KEY Position */
<> 144:ef7eb2e8f9f7 6907 #define CRPT_PRNG_KEY6_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY6_KEY_Pos) /*!< CRPT PRNG_KEY6: KEY Mask */
<> 144:ef7eb2e8f9f7 6908
<> 144:ef7eb2e8f9f7 6909 #define CRPT_PRNG_KEY7_KEY_Pos (0) /*!< CRPT PRNG_KEY7: KEY Position */
<> 144:ef7eb2e8f9f7 6910 #define CRPT_PRNG_KEY7_KEY_Msk (0xfffffffful << CRPT_PRNG_KEY7_KEY_Pos) /*!< CRPT PRNG_KEY7: KEY Mask */
<> 144:ef7eb2e8f9f7 6911
<> 144:ef7eb2e8f9f7 6912 #define CRPT_AES_FDBCK0_FDBCK_Pos (0) /*!< CRPT AES_FDBCK0: FDBCK Position */
<> 144:ef7eb2e8f9f7 6913 #define CRPT_AES_FDBCK0_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK0_FDBCK_Pos) /*!< CRPT AES_FDBCK0: FDBCK Mask */
<> 144:ef7eb2e8f9f7 6914
<> 144:ef7eb2e8f9f7 6915 #define CRPT_AES_FDBCK1_FDBCK_Pos (0) /*!< CRPT AES_FDBCK1: FDBCK Position */
<> 144:ef7eb2e8f9f7 6916 #define CRPT_AES_FDBCK1_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK1_FDBCK_Pos) /*!< CRPT AES_FDBCK1: FDBCK Mask */
<> 144:ef7eb2e8f9f7 6917
<> 144:ef7eb2e8f9f7 6918 #define CRPT_AES_FDBCK2_FDBCK_Pos (0) /*!< CRPT AES_FDBCK2: FDBCK Position */
<> 144:ef7eb2e8f9f7 6919 #define CRPT_AES_FDBCK2_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK2_FDBCK_Pos) /*!< CRPT AES_FDBCK2: FDBCK Mask */
<> 144:ef7eb2e8f9f7 6920
<> 144:ef7eb2e8f9f7 6921 #define CRPT_AES_FDBCK3_FDBCK_Pos (0) /*!< CRPT AES_FDBCK3: FDBCK Position */
<> 144:ef7eb2e8f9f7 6922 #define CRPT_AES_FDBCK3_FDBCK_Msk (0xfffffffful << CRPT_AES_FDBCK3_FDBCK_Pos) /*!< CRPT AES_FDBCK3: FDBCK Mask */
<> 144:ef7eb2e8f9f7 6923
<> 144:ef7eb2e8f9f7 6924 #define CRPT_TDES_FDBCKH_FDBCK_Pos (0) /*!< CRPT TDES_FDBCKH: FDBCK Position */
<> 144:ef7eb2e8f9f7 6925 #define CRPT_TDES_FDBCKH_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKH_FDBCK_Pos) /*!< CRPT TDES_FDBCKH: FDBCK Mask */
<> 144:ef7eb2e8f9f7 6926
<> 144:ef7eb2e8f9f7 6927 #define CRPT_TDES_FDBCKL_FDBCK_Pos (0) /*!< CRPT TDES_FDBCKL: FDBCK Position */
<> 144:ef7eb2e8f9f7 6928 #define CRPT_TDES_FDBCKL_FDBCK_Msk (0xfffffffful << CRPT_TDES_FDBCKL_FDBCK_Pos) /*!< CRPT TDES_FDBCKL: FDBCK Mask */
<> 144:ef7eb2e8f9f7 6929
<> 144:ef7eb2e8f9f7 6930 #define CRPT_AES_CTL_START_Pos (0) /*!< CRPT AES_CTL: START Position */
<> 144:ef7eb2e8f9f7 6931 #define CRPT_AES_CTL_START_Msk (0x1ul << CRPT_AES_CTL_START_Pos) /*!< CRPT AES_CTL: START Mask */
<> 144:ef7eb2e8f9f7 6932
<> 144:ef7eb2e8f9f7 6933 #define CRPT_AES_CTL_STOP_Pos (1) /*!< CRPT AES_CTL: STOP Position */
<> 144:ef7eb2e8f9f7 6934 #define CRPT_AES_CTL_STOP_Msk (0x1ul << CRPT_AES_CTL_STOP_Pos) /*!< CRPT AES_CTL: STOP Mask */
<> 144:ef7eb2e8f9f7 6935
<> 144:ef7eb2e8f9f7 6936 #define CRPT_AES_CTL_KEYSZ_Pos (2) /*!< CRPT AES_CTL: KEYSZ Position */
<> 144:ef7eb2e8f9f7 6937 #define CRPT_AES_CTL_KEYSZ_Msk (0x3ul << CRPT_AES_CTL_KEYSZ_Pos) /*!< CRPT AES_CTL: KEYSZ Mask */
<> 144:ef7eb2e8f9f7 6938
<> 144:ef7eb2e8f9f7 6939 #define CRPT_AES_CTL_DMALAST_Pos (5) /*!< CRPT AES_CTL: DMALAST Position */
<> 144:ef7eb2e8f9f7 6940 #define CRPT_AES_CTL_DMALAST_Msk (0x1ul << CRPT_AES_CTL_DMALAST_Pos) /*!< CRPT AES_CTL: DMALAST Mask */
<> 144:ef7eb2e8f9f7 6941
<> 144:ef7eb2e8f9f7 6942 #define CRPT_AES_CTL_DMACSCAD_Pos (6) /*!< CRPT AES_CTL: DMACSCAD Position */
<> 144:ef7eb2e8f9f7 6943 #define CRPT_AES_CTL_DMACSCAD_Msk (0x1ul << CRPT_AES_CTL_DMACSCAD_Pos) /*!< CRPT AES_CTL: DMACSCAD Mask */
<> 144:ef7eb2e8f9f7 6944
<> 144:ef7eb2e8f9f7 6945 #define CRPT_AES_CTL_DMAEN_Pos (7) /*!< CRPT AES_CTL: DMAEN Position */
<> 144:ef7eb2e8f9f7 6946 #define CRPT_AES_CTL_DMAEN_Msk (0x1ul << CRPT_AES_CTL_DMAEN_Pos) /*!< CRPT AES_CTL: DMAEN Mask */
<> 144:ef7eb2e8f9f7 6947
<> 144:ef7eb2e8f9f7 6948 #define CRPT_AES_CTL_OPMODE_Pos (8) /*!< CRPT AES_CTL: OPMODE Position */
<> 144:ef7eb2e8f9f7 6949 #define CRPT_AES_CTL_OPMODE_Msk (0xfful << CRPT_AES_CTL_OPMODE_Pos) /*!< CRPT AES_CTL: OPMODE Mask */
<> 144:ef7eb2e8f9f7 6950
<> 144:ef7eb2e8f9f7 6951 #define CRPT_AES_CTL_ENCRPT_Pos (16) /*!< CRPT AES_CTL: ENCRPT Position */
<> 144:ef7eb2e8f9f7 6952 #define CRPT_AES_CTL_ENCRPT_Msk (0x1ul << CRPT_AES_CTL_ENCRPT_Pos) /*!< CRPT AES_CTL: ENCRPT Mask */
<> 144:ef7eb2e8f9f7 6953
<> 144:ef7eb2e8f9f7 6954 #define CRPT_AES_CTL_OUTSWAP_Pos (22) /*!< CRPT AES_CTL: OUTSWAP Position */
<> 144:ef7eb2e8f9f7 6955 #define CRPT_AES_CTL_OUTSWAP_Msk (0x1ul << CRPT_AES_CTL_OUTSWAP_Pos) /*!< CRPT AES_CTL: OUTSWAP Mask */
<> 144:ef7eb2e8f9f7 6956
<> 144:ef7eb2e8f9f7 6957 #define CRPT_AES_CTL_INSWAP_Pos (23) /*!< CRPT AES_CTL: INSWAP Position */
<> 144:ef7eb2e8f9f7 6958 #define CRPT_AES_CTL_INSWAP_Msk (0x1ul << CRPT_AES_CTL_INSWAP_Pos) /*!< CRPT AES_CTL: INSWAP Mask */
<> 144:ef7eb2e8f9f7 6959
<> 144:ef7eb2e8f9f7 6960 #define CRPT_AES_CTL_CHANNEL_Pos (24) /*!< CRPT AES_CTL: CHANNEL Position */
<> 144:ef7eb2e8f9f7 6961 #define CRPT_AES_CTL_CHANNEL_Msk (0x3ul << CRPT_AES_CTL_CHANNEL_Pos) /*!< CRPT AES_CTL: CHANNEL Mask */
<> 144:ef7eb2e8f9f7 6962
<> 144:ef7eb2e8f9f7 6963 #define CRPT_AES_CTL_KEYUNPRT_Pos (26) /*!< CRPT AES_CTL: KEYUNPRT Position */
<> 144:ef7eb2e8f9f7 6964 #define CRPT_AES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_AES_CTL_KEYUNPRT_Pos) /*!< CRPT AES_CTL: KEYUNPRT Mask */
<> 144:ef7eb2e8f9f7 6965
<> 144:ef7eb2e8f9f7 6966 #define CRPT_AES_CTL_KEYPRT_Pos (31) /*!< CRPT AES_CTL: KEYPRT Position */
<> 144:ef7eb2e8f9f7 6967 #define CRPT_AES_CTL_KEYPRT_Msk (0x1ul << CRPT_AES_CTL_KEYPRT_Pos) /*!< CRPT AES_CTL: KEYPRT Mask */
<> 144:ef7eb2e8f9f7 6968
<> 144:ef7eb2e8f9f7 6969 #define CRPT_AES_STS_BUSY_Pos (0) /*!< CRPT AES_STS: BUSY Position */
<> 144:ef7eb2e8f9f7 6970 #define CRPT_AES_STS_BUSY_Msk (0x1ul << CRPT_AES_STS_BUSY_Pos) /*!< CRPT AES_STS: BUSY Mask */
<> 144:ef7eb2e8f9f7 6971
<> 144:ef7eb2e8f9f7 6972 #define CRPT_AES_STS_INBUFEMPTY_Pos (8) /*!< CRPT AES_STS: INBUFEMPTY Position */
<> 144:ef7eb2e8f9f7 6973 #define CRPT_AES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_INBUFEMPTY_Pos) /*!< CRPT AES_STS: INBUFEMPTY Mask */
<> 144:ef7eb2e8f9f7 6974
<> 144:ef7eb2e8f9f7 6975 #define CRPT_AES_STS_INBUFFULL_Pos (9) /*!< CRPT AES_STS: INBUFFULL Position */
<> 144:ef7eb2e8f9f7 6976 #define CRPT_AES_STS_INBUFFULL_Msk (0x1ul << CRPT_AES_STS_INBUFFULL_Pos) /*!< CRPT AES_STS: INBUFFULL Mask */
<> 144:ef7eb2e8f9f7 6977
<> 144:ef7eb2e8f9f7 6978 #define CRPT_AES_STS_INBUFERR_Pos (10) /*!< CRPT AES_STS: INBUFERR Position */
<> 144:ef7eb2e8f9f7 6979 #define CRPT_AES_STS_INBUFERR_Msk (0x1ul << CRPT_AES_STS_INBUFERR_Pos) /*!< CRPT AES_STS: INBUFERR Mask */
<> 144:ef7eb2e8f9f7 6980
<> 144:ef7eb2e8f9f7 6981 #define CRPT_AES_STS_CNTERR_Pos (12) /*!< CRPT AES_STS: CNTERR Position */
<> 144:ef7eb2e8f9f7 6982 #define CRPT_AES_STS_CNTERR_Msk (0x1ul << CRPT_AES_STS_CNTERR_Pos) /*!< CRPT AES_STS: CNTERR Mask */
<> 144:ef7eb2e8f9f7 6983
<> 144:ef7eb2e8f9f7 6984 #define CRPT_AES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT AES_STS: OUTBUFEMPTY Position */
<> 144:ef7eb2e8f9f7 6985 #define CRPT_AES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_AES_STS_OUTBUFEMPTY_Pos) /*!< CRPT AES_STS: OUTBUFEMPTY Mask */
<> 144:ef7eb2e8f9f7 6986
<> 144:ef7eb2e8f9f7 6987 #define CRPT_AES_STS_OUTBUFFULL_Pos (17) /*!< CRPT AES_STS: OUTBUFFULL Position */
<> 144:ef7eb2e8f9f7 6988 #define CRPT_AES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_AES_STS_OUTBUFFULL_Pos) /*!< CRPT AES_STS: OUTBUFFULL Mask */
<> 144:ef7eb2e8f9f7 6989
<> 144:ef7eb2e8f9f7 6990 #define CRPT_AES_STS_OUTBUFERR_Pos (18) /*!< CRPT AES_STS: OUTBUFERR Position */
<> 144:ef7eb2e8f9f7 6991 #define CRPT_AES_STS_OUTBUFERR_Msk (0x1ul << CRPT_AES_STS_OUTBUFERR_Pos) /*!< CRPT AES_STS: OUTBUFERR Mask */
<> 144:ef7eb2e8f9f7 6992
<> 144:ef7eb2e8f9f7 6993 #define CRPT_AES_STS_BUSERR_Pos (20) /*!< CRPT AES_STS: BUSERR Position */
<> 144:ef7eb2e8f9f7 6994 #define CRPT_AES_STS_BUSERR_Msk (0x1ul << CRPT_AES_STS_BUSERR_Pos) /*!< CRPT AES_STS: BUSERR Mask */
<> 144:ef7eb2e8f9f7 6995
<> 144:ef7eb2e8f9f7 6996 #define CRPT_AES_DATIN_DATIN_Pos (0) /*!< CRPT AES_DATIN: DATIN Position */
<> 144:ef7eb2e8f9f7 6997 #define CRPT_AES_DATIN_DATIN_Msk (0xfffffffful << CRPT_AES_DATIN_DATIN_Pos) /*!< CRPT AES_DATIN: DATIN Mask */
<> 144:ef7eb2e8f9f7 6998
<> 144:ef7eb2e8f9f7 6999 #define CRPT_AES_DATOUT_DATOUT_Pos (0) /*!< CRPT AES_DATOUT: DATOUT Position */
<> 144:ef7eb2e8f9f7 7000 #define CRPT_AES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_AES_DATOUT_DATOUT_Pos) /*!< CRPT AES_DATOUT: DATOUT Mask */
<> 144:ef7eb2e8f9f7 7001
<> 144:ef7eb2e8f9f7 7002 #define CRPT_AES0_KEY0_KEY_Pos (0) /*!< CRPT AES0_KEY0: KEY Position */
<> 144:ef7eb2e8f9f7 7003 #define CRPT_AES0_KEY0_KEY_Msk (0xfffffffful << CRPT_AES0_KEY0_KEY_Pos) /*!< CRPT AES0_KEY0: KEY Mask */
<> 144:ef7eb2e8f9f7 7004
<> 144:ef7eb2e8f9f7 7005 #define CRPT_AES0_KEY1_KEY_Pos (0) /*!< CRPT AES0_KEY1: KEY Position */
<> 144:ef7eb2e8f9f7 7006 #define CRPT_AES0_KEY1_KEY_Msk (0xfffffffful << CRPT_AES0_KEY1_KEY_Pos) /*!< CRPT AES0_KEY1: KEY Mask */
<> 144:ef7eb2e8f9f7 7007
<> 144:ef7eb2e8f9f7 7008 #define CRPT_AES0_KEY2_KEY_Pos (0) /*!< CRPT AES0_KEY2: KEY Position */
<> 144:ef7eb2e8f9f7 7009 #define CRPT_AES0_KEY2_KEY_Msk (0xfffffffful << CRPT_AES0_KEY2_KEY_Pos) /*!< CRPT AES0_KEY2: KEY Mask */
<> 144:ef7eb2e8f9f7 7010
<> 144:ef7eb2e8f9f7 7011 #define CRPT_AES0_KEY3_KEY_Pos (0) /*!< CRPT AES0_KEY3: KEY Position */
<> 144:ef7eb2e8f9f7 7012 #define CRPT_AES0_KEY3_KEY_Msk (0xfffffffful << CRPT_AES0_KEY3_KEY_Pos) /*!< CRPT AES0_KEY3: KEY Mask */
<> 144:ef7eb2e8f9f7 7013
<> 144:ef7eb2e8f9f7 7014 #define CRPT_AES0_KEY4_KEY_Pos (0) /*!< CRPT AES0_KEY4: KEY Position */
<> 144:ef7eb2e8f9f7 7015 #define CRPT_AES0_KEY4_KEY_Msk (0xfffffffful << CRPT_AES0_KEY4_KEY_Pos) /*!< CRPT AES0_KEY4: KEY Mask */
<> 144:ef7eb2e8f9f7 7016
<> 144:ef7eb2e8f9f7 7017 #define CRPT_AES0_KEY5_KEY_Pos (0) /*!< CRPT AES0_KEY5: KEY Position */
<> 144:ef7eb2e8f9f7 7018 #define CRPT_AES0_KEY5_KEY_Msk (0xfffffffful << CRPT_AES0_KEY5_KEY_Pos) /*!< CRPT AES0_KEY5: KEY Mask */
<> 144:ef7eb2e8f9f7 7019
<> 144:ef7eb2e8f9f7 7020 #define CRPT_AES0_KEY6_KEY_Pos (0) /*!< CRPT AES0_KEY6: KEY Position */
<> 144:ef7eb2e8f9f7 7021 #define CRPT_AES0_KEY6_KEY_Msk (0xfffffffful << CRPT_AES0_KEY6_KEY_Pos) /*!< CRPT AES0_KEY6: KEY Mask */
<> 144:ef7eb2e8f9f7 7022
<> 144:ef7eb2e8f9f7 7023 #define CRPT_AES0_KEY7_KEY_Pos (0) /*!< CRPT AES0_KEY7: KEY Position */
<> 144:ef7eb2e8f9f7 7024 #define CRPT_AES0_KEY7_KEY_Msk (0xfffffffful << CRPT_AES0_KEY7_KEY_Pos) /*!< CRPT AES0_KEY7: KEY Mask */
<> 144:ef7eb2e8f9f7 7025
<> 144:ef7eb2e8f9f7 7026 #define CRPT_AES0_IV0_IV_Pos (0) /*!< CRPT AES0_IV0: IV Position */
<> 144:ef7eb2e8f9f7 7027 #define CRPT_AES0_IV0_IV_Msk (0xfffffffful << CRPT_AES0_IV0_IV_Pos) /*!< CRPT AES0_IV0: IV Mask */
<> 144:ef7eb2e8f9f7 7028
<> 144:ef7eb2e8f9f7 7029 #define CRPT_AES0_IV1_IV_Pos (0) /*!< CRPT AES0_IV1: IV Position */
<> 144:ef7eb2e8f9f7 7030 #define CRPT_AES0_IV1_IV_Msk (0xfffffffful << CRPT_AES0_IV1_IV_Pos) /*!< CRPT AES0_IV1: IV Mask */
<> 144:ef7eb2e8f9f7 7031
<> 144:ef7eb2e8f9f7 7032 #define CRPT_AES0_IV2_IV_Pos (0) /*!< CRPT AES0_IV2: IV Position */
<> 144:ef7eb2e8f9f7 7033 #define CRPT_AES0_IV2_IV_Msk (0xfffffffful << CRPT_AES0_IV2_IV_Pos) /*!< CRPT AES0_IV2: IV Mask */
<> 144:ef7eb2e8f9f7 7034
<> 144:ef7eb2e8f9f7 7035 #define CRPT_AES0_IV3_IV_Pos (0) /*!< CRPT AES0_IV3: IV Position */
<> 144:ef7eb2e8f9f7 7036 #define CRPT_AES0_IV3_IV_Msk (0xfffffffful << CRPT_AES0_IV3_IV_Pos) /*!< CRPT AES0_IV3: IV Mask */
<> 144:ef7eb2e8f9f7 7037
<> 144:ef7eb2e8f9f7 7038 #define CRPT_AES0_SADDR_SADDR_Pos (0) /*!< CRPT AES0_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7039 #define CRPT_AES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES0_SADDR_SADDR_Pos) /*!< CRPT AES0_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7040
<> 144:ef7eb2e8f9f7 7041 #define CRPT_AES0_DADDR_DADDR_Pos (0) /*!< CRPT AES0_DADDR: DADDR Position */
<> 144:ef7eb2e8f9f7 7042 #define CRPT_AES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES0_DADDR_DADDR_Pos) /*!< CRPT AES0_DADDR: DADDR Mask */
<> 144:ef7eb2e8f9f7 7043
<> 144:ef7eb2e8f9f7 7044 #define CRPT_AES0_CNT_CNT_Pos (0) /*!< CRPT AES0_CNT: CNT Position */
<> 144:ef7eb2e8f9f7 7045 #define CRPT_AES0_CNT_CNT_Msk (0xfffffffful << CRPT_AES0_CNT_CNT_Pos) /*!< CRPT AES0_CNT: CNT Mask */
<> 144:ef7eb2e8f9f7 7046
<> 144:ef7eb2e8f9f7 7047 #define CRPT_AES1_KEY0_KEY_Pos (0) /*!< CRPT AES1_KEY0: KEY Position */
<> 144:ef7eb2e8f9f7 7048 #define CRPT_AES1_KEY0_KEY_Msk (0xfffffffful << CRPT_AES1_KEY0_KEY_Pos) /*!< CRPT AES1_KEY0: KEY Mask */
<> 144:ef7eb2e8f9f7 7049
<> 144:ef7eb2e8f9f7 7050 #define CRPT_AES1_KEY1_KEY_Pos (0) /*!< CRPT AES1_KEY1: KEY Position */
<> 144:ef7eb2e8f9f7 7051 #define CRPT_AES1_KEY1_KEY_Msk (0xfffffffful << CRPT_AES1_KEY1_KEY_Pos) /*!< CRPT AES1_KEY1: KEY Mask */
<> 144:ef7eb2e8f9f7 7052
<> 144:ef7eb2e8f9f7 7053 #define CRPT_AES1_KEY2_KEY_Pos (0) /*!< CRPT AES1_KEY2: KEY Position */
<> 144:ef7eb2e8f9f7 7054 #define CRPT_AES1_KEY2_KEY_Msk (0xfffffffful << CRPT_AES1_KEY2_KEY_Pos) /*!< CRPT AES1_KEY2: KEY Mask */
<> 144:ef7eb2e8f9f7 7055
<> 144:ef7eb2e8f9f7 7056 #define CRPT_AES1_KEY3_KEY_Pos (0) /*!< CRPT AES1_KEY3: KEY Position */
<> 144:ef7eb2e8f9f7 7057 #define CRPT_AES1_KEY3_KEY_Msk (0xfffffffful << CRPT_AES1_KEY3_KEY_Pos) /*!< CRPT AES1_KEY3: KEY Mask */
<> 144:ef7eb2e8f9f7 7058
<> 144:ef7eb2e8f9f7 7059 #define CRPT_AES1_KEY4_KEY_Pos (0) /*!< CRPT AES1_KEY4: KEY Position */
<> 144:ef7eb2e8f9f7 7060 #define CRPT_AES1_KEY4_KEY_Msk (0xfffffffful << CRPT_AES1_KEY4_KEY_Pos) /*!< CRPT AES1_KEY4: KEY Mask */
<> 144:ef7eb2e8f9f7 7061
<> 144:ef7eb2e8f9f7 7062 #define CRPT_AES1_KEY5_KEY_Pos (0) /*!< CRPT AES1_KEY5: KEY Position */
<> 144:ef7eb2e8f9f7 7063 #define CRPT_AES1_KEY5_KEY_Msk (0xfffffffful << CRPT_AES1_KEY5_KEY_Pos) /*!< CRPT AES1_KEY5: KEY Mask */
<> 144:ef7eb2e8f9f7 7064
<> 144:ef7eb2e8f9f7 7065 #define CRPT_AES1_KEY6_KEY_Pos (0) /*!< CRPT AES1_KEY6: KEY Position */
<> 144:ef7eb2e8f9f7 7066 #define CRPT_AES1_KEY6_KEY_Msk (0xfffffffful << CRPT_AES1_KEY6_KEY_Pos) /*!< CRPT AES1_KEY6: KEY Mask */
<> 144:ef7eb2e8f9f7 7067
<> 144:ef7eb2e8f9f7 7068 #define CRPT_AES1_KEY7_KEY_Pos (0) /*!< CRPT AES1_KEY7: KEY Position */
<> 144:ef7eb2e8f9f7 7069 #define CRPT_AES1_KEY7_KEY_Msk (0xfffffffful << CRPT_AES1_KEY7_KEY_Pos) /*!< CRPT AES1_KEY7: KEY Mask */
<> 144:ef7eb2e8f9f7 7070
<> 144:ef7eb2e8f9f7 7071 #define CRPT_AES1_IV0_IV_Pos (0) /*!< CRPT AES1_IV0: IV Position */
<> 144:ef7eb2e8f9f7 7072 #define CRPT_AES1_IV0_IV_Msk (0xfffffffful << CRPT_AES1_IV0_IV_Pos) /*!< CRPT AES1_IV0: IV Mask */
<> 144:ef7eb2e8f9f7 7073
<> 144:ef7eb2e8f9f7 7074 #define CRPT_AES1_IV1_IV_Pos (0) /*!< CRPT AES1_IV1: IV Position */
<> 144:ef7eb2e8f9f7 7075 #define CRPT_AES1_IV1_IV_Msk (0xfffffffful << CRPT_AES1_IV1_IV_Pos) /*!< CRPT AES1_IV1: IV Mask */
<> 144:ef7eb2e8f9f7 7076
<> 144:ef7eb2e8f9f7 7077 #define CRPT_AES1_IV2_IV_Pos (0) /*!< CRPT AES1_IV2: IV Position */
<> 144:ef7eb2e8f9f7 7078 #define CRPT_AES1_IV2_IV_Msk (0xfffffffful << CRPT_AES1_IV2_IV_Pos) /*!< CRPT AES1_IV2: IV Mask */
<> 144:ef7eb2e8f9f7 7079
<> 144:ef7eb2e8f9f7 7080 #define CRPT_AES1_IV3_IV_Pos (0) /*!< CRPT AES1_IV3: IV Position */
<> 144:ef7eb2e8f9f7 7081 #define CRPT_AES1_IV3_IV_Msk (0xfffffffful << CRPT_AES1_IV3_IV_Pos) /*!< CRPT AES1_IV3: IV Mask */
<> 144:ef7eb2e8f9f7 7082
<> 144:ef7eb2e8f9f7 7083 #define CRPT_AES1_SADDR_SADDR_Pos (0) /*!< CRPT AES1_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7084 #define CRPT_AES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES1_SADDR_SADDR_Pos) /*!< CRPT AES1_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7085
<> 144:ef7eb2e8f9f7 7086 #define CRPT_AES1_DADDR_DADDR_Pos (0) /*!< CRPT AES1_DADDR: DADDR Position */
<> 144:ef7eb2e8f9f7 7087 #define CRPT_AES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES1_DADDR_DADDR_Pos) /*!< CRPT AES1_DADDR: DADDR Mask */
<> 144:ef7eb2e8f9f7 7088
<> 144:ef7eb2e8f9f7 7089 #define CRPT_AES1_CNT_CNT_Pos (0) /*!< CRPT AES1_CNT: CNT Position */
<> 144:ef7eb2e8f9f7 7090 #define CRPT_AES1_CNT_CNT_Msk (0xfffffffful << CRPT_AES1_CNT_CNT_Pos) /*!< CRPT AES1_CNT: CNT Mask */
<> 144:ef7eb2e8f9f7 7091
<> 144:ef7eb2e8f9f7 7092 #define CRPT_AES2_KEY0_KEY_Pos (0) /*!< CRPT AES2_KEY0: KEY Position */
<> 144:ef7eb2e8f9f7 7093 #define CRPT_AES2_KEY0_KEY_Msk (0xfffffffful << CRPT_AES2_KEY0_KEY_Pos) /*!< CRPT AES2_KEY0: KEY Mask */
<> 144:ef7eb2e8f9f7 7094
<> 144:ef7eb2e8f9f7 7095 #define CRPT_AES2_KEY1_KEY_Pos (0) /*!< CRPT AES2_KEY1: KEY Position */
<> 144:ef7eb2e8f9f7 7096 #define CRPT_AES2_KEY1_KEY_Msk (0xfffffffful << CRPT_AES2_KEY1_KEY_Pos) /*!< CRPT AES2_KEY1: KEY Mask */
<> 144:ef7eb2e8f9f7 7097
<> 144:ef7eb2e8f9f7 7098 #define CRPT_AES2_KEY2_KEY_Pos (0) /*!< CRPT AES2_KEY2: KEY Position */
<> 144:ef7eb2e8f9f7 7099 #define CRPT_AES2_KEY2_KEY_Msk (0xfffffffful << CRPT_AES2_KEY2_KEY_Pos) /*!< CRPT AES2_KEY2: KEY Mask */
<> 144:ef7eb2e8f9f7 7100
<> 144:ef7eb2e8f9f7 7101 #define CRPT_AES2_KEY3_KEY_Pos (0) /*!< CRPT AES2_KEY3: KEY Position */
<> 144:ef7eb2e8f9f7 7102 #define CRPT_AES2_KEY3_KEY_Msk (0xfffffffful << CRPT_AES2_KEY3_KEY_Pos) /*!< CRPT AES2_KEY3: KEY Mask */
<> 144:ef7eb2e8f9f7 7103
<> 144:ef7eb2e8f9f7 7104 #define CRPT_AES2_KEY4_KEY_Pos (0) /*!< CRPT AES2_KEY4: KEY Position */
<> 144:ef7eb2e8f9f7 7105 #define CRPT_AES2_KEY4_KEY_Msk (0xfffffffful << CRPT_AES2_KEY4_KEY_Pos) /*!< CRPT AES2_KEY4: KEY Mask */
<> 144:ef7eb2e8f9f7 7106
<> 144:ef7eb2e8f9f7 7107 #define CRPT_AES2_KEY5_KEY_Pos (0) /*!< CRPT AES2_KEY5: KEY Position */
<> 144:ef7eb2e8f9f7 7108 #define CRPT_AES2_KEY5_KEY_Msk (0xfffffffful << CRPT_AES2_KEY5_KEY_Pos) /*!< CRPT AES2_KEY5: KEY Mask */
<> 144:ef7eb2e8f9f7 7109
<> 144:ef7eb2e8f9f7 7110 #define CRPT_AES2_KEY6_KEY_Pos (0) /*!< CRPT AES2_KEY6: KEY Position */
<> 144:ef7eb2e8f9f7 7111 #define CRPT_AES2_KEY6_KEY_Msk (0xfffffffful << CRPT_AES2_KEY6_KEY_Pos) /*!< CRPT AES2_KEY6: KEY Mask */
<> 144:ef7eb2e8f9f7 7112
<> 144:ef7eb2e8f9f7 7113 #define CRPT_AES2_KEY7_KEY_Pos (0) /*!< CRPT AES2_KEY7: KEY Position */
<> 144:ef7eb2e8f9f7 7114 #define CRPT_AES2_KEY7_KEY_Msk (0xfffffffful << CRPT_AES2_KEY7_KEY_Pos) /*!< CRPT AES2_KEY7: KEY Mask */
<> 144:ef7eb2e8f9f7 7115
<> 144:ef7eb2e8f9f7 7116 #define CRPT_AES2_IV0_IV_Pos (0) /*!< CRPT AES2_IV0: IV Position */
<> 144:ef7eb2e8f9f7 7117 #define CRPT_AES2_IV0_IV_Msk (0xfffffffful << CRPT_AES2_IV0_IV_Pos) /*!< CRPT AES2_IV0: IV Mask */
<> 144:ef7eb2e8f9f7 7118
<> 144:ef7eb2e8f9f7 7119 #define CRPT_AES2_IV1_IV_Pos (0) /*!< CRPT AES2_IV1: IV Position */
<> 144:ef7eb2e8f9f7 7120 #define CRPT_AES2_IV1_IV_Msk (0xfffffffful << CRPT_AES2_IV1_IV_Pos) /*!< CRPT AES2_IV1: IV Mask */
<> 144:ef7eb2e8f9f7 7121
<> 144:ef7eb2e8f9f7 7122 #define CRPT_AES2_IV2_IV_Pos (0) /*!< CRPT AES2_IV2: IV Position */
<> 144:ef7eb2e8f9f7 7123 #define CRPT_AES2_IV2_IV_Msk (0xfffffffful << CRPT_AES2_IV2_IV_Pos) /*!< CRPT AES2_IV2: IV Mask */
<> 144:ef7eb2e8f9f7 7124
<> 144:ef7eb2e8f9f7 7125 #define CRPT_AES2_IV3_IV_Pos (0) /*!< CRPT AES2_IV3: IV Position */
<> 144:ef7eb2e8f9f7 7126 #define CRPT_AES2_IV3_IV_Msk (0xfffffffful << CRPT_AES2_IV3_IV_Pos) /*!< CRPT AES2_IV3: IV Mask */
<> 144:ef7eb2e8f9f7 7127
<> 144:ef7eb2e8f9f7 7128 #define CRPT_AES2_SADDR_SADDR_Pos (0) /*!< CRPT AES2_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7129 #define CRPT_AES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES2_SADDR_SADDR_Pos) /*!< CRPT AES2_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7130
<> 144:ef7eb2e8f9f7 7131 #define CRPT_AES2_DADDR_DADDR_Pos (0) /*!< CRPT AES2_DADDR: DADDR Position */
<> 144:ef7eb2e8f9f7 7132 #define CRPT_AES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES2_DADDR_DADDR_Pos) /*!< CRPT AES2_DADDR: DADDR Mask */
<> 144:ef7eb2e8f9f7 7133
<> 144:ef7eb2e8f9f7 7134 #define CRPT_AES2_CNT_CNT_Pos (0) /*!< CRPT AES2_CNT: CNT Position */
<> 144:ef7eb2e8f9f7 7135 #define CRPT_AES2_CNT_CNT_Msk (0xfffffffful << CRPT_AES2_CNT_CNT_Pos) /*!< CRPT AES2_CNT: CNT Mask */
<> 144:ef7eb2e8f9f7 7136
<> 144:ef7eb2e8f9f7 7137 #define CRPT_AES3_KEY0_KEY_Pos (0) /*!< CRPT AES3_KEY0: KEY Position */
<> 144:ef7eb2e8f9f7 7138 #define CRPT_AES3_KEY0_KEY_Msk (0xfffffffful << CRPT_AES3_KEY0_KEY_Pos) /*!< CRPT AES3_KEY0: KEY Mask */
<> 144:ef7eb2e8f9f7 7139
<> 144:ef7eb2e8f9f7 7140 #define CRPT_AES3_KEY1_KEY_Pos (0) /*!< CRPT AES3_KEY1: KEY Position */
<> 144:ef7eb2e8f9f7 7141 #define CRPT_AES3_KEY1_KEY_Msk (0xfffffffful << CRPT_AES3_KEY1_KEY_Pos) /*!< CRPT AES3_KEY1: KEY Mask */
<> 144:ef7eb2e8f9f7 7142
<> 144:ef7eb2e8f9f7 7143 #define CRPT_AES3_KEY2_KEY_Pos (0) /*!< CRPT AES3_KEY2: KEY Position */
<> 144:ef7eb2e8f9f7 7144 #define CRPT_AES3_KEY2_KEY_Msk (0xfffffffful << CRPT_AES3_KEY2_KEY_Pos) /*!< CRPT AES3_KEY2: KEY Mask */
<> 144:ef7eb2e8f9f7 7145
<> 144:ef7eb2e8f9f7 7146 #define CRPT_AES3_KEY3_KEY_Pos (0) /*!< CRPT AES3_KEY3: KEY Position */
<> 144:ef7eb2e8f9f7 7147 #define CRPT_AES3_KEY3_KEY_Msk (0xfffffffful << CRPT_AES3_KEY3_KEY_Pos) /*!< CRPT AES3_KEY3: KEY Mask */
<> 144:ef7eb2e8f9f7 7148
<> 144:ef7eb2e8f9f7 7149 #define CRPT_AES3_KEY4_KEY_Pos (0) /*!< CRPT AES3_KEY4: KEY Position */
<> 144:ef7eb2e8f9f7 7150 #define CRPT_AES3_KEY4_KEY_Msk (0xfffffffful << CRPT_AES3_KEY4_KEY_Pos) /*!< CRPT AES3_KEY4: KEY Mask */
<> 144:ef7eb2e8f9f7 7151
<> 144:ef7eb2e8f9f7 7152 #define CRPT_AES3_KEY5_KEY_Pos (0) /*!< CRPT AES3_KEY5: KEY Position */
<> 144:ef7eb2e8f9f7 7153 #define CRPT_AES3_KEY5_KEY_Msk (0xfffffffful << CRPT_AES3_KEY5_KEY_Pos) /*!< CRPT AES3_KEY5: KEY Mask */
<> 144:ef7eb2e8f9f7 7154
<> 144:ef7eb2e8f9f7 7155 #define CRPT_AES3_KEY6_KEY_Pos (0) /*!< CRPT AES3_KEY6: KEY Position */
<> 144:ef7eb2e8f9f7 7156 #define CRPT_AES3_KEY6_KEY_Msk (0xfffffffful << CRPT_AES3_KEY6_KEY_Pos) /*!< CRPT AES3_KEY6: KEY Mask */
<> 144:ef7eb2e8f9f7 7157
<> 144:ef7eb2e8f9f7 7158 #define CRPT_AES3_KEY7_KEY_Pos (0) /*!< CRPT AES3_KEY7: KEY Position */
<> 144:ef7eb2e8f9f7 7159 #define CRPT_AES3_KEY7_KEY_Msk (0xfffffffful << CRPT_AES3_KEY7_KEY_Pos) /*!< CRPT AES3_KEY7: KEY Mask */
<> 144:ef7eb2e8f9f7 7160
<> 144:ef7eb2e8f9f7 7161 #define CRPT_AES3_IV0_IV_Pos (0) /*!< CRPT AES3_IV0: IV Position */
<> 144:ef7eb2e8f9f7 7162 #define CRPT_AES3_IV0_IV_Msk (0xfffffffful << CRPT_AES3_IV0_IV_Pos) /*!< CRPT AES3_IV0: IV Mask */
<> 144:ef7eb2e8f9f7 7163
<> 144:ef7eb2e8f9f7 7164 #define CRPT_AES3_IV1_IV_Pos (0) /*!< CRPT AES3_IV1: IV Position */
<> 144:ef7eb2e8f9f7 7165 #define CRPT_AES3_IV1_IV_Msk (0xfffffffful << CRPT_AES3_IV1_IV_Pos) /*!< CRPT AES3_IV1: IV Mask */
<> 144:ef7eb2e8f9f7 7166
<> 144:ef7eb2e8f9f7 7167 #define CRPT_AES3_IV2_IV_Pos (0) /*!< CRPT AES3_IV2: IV Position */
<> 144:ef7eb2e8f9f7 7168 #define CRPT_AES3_IV2_IV_Msk (0xfffffffful << CRPT_AES3_IV2_IV_Pos) /*!< CRPT AES3_IV2: IV Mask */
<> 144:ef7eb2e8f9f7 7169
<> 144:ef7eb2e8f9f7 7170 #define CRPT_AES3_IV3_IV_Pos (0) /*!< CRPT AES3_IV3: IV Position */
<> 144:ef7eb2e8f9f7 7171 #define CRPT_AES3_IV3_IV_Msk (0xfffffffful << CRPT_AES3_IV3_IV_Pos) /*!< CRPT AES3_IV3: IV Mask */
<> 144:ef7eb2e8f9f7 7172
<> 144:ef7eb2e8f9f7 7173 #define CRPT_AES3_SADDR_SADDR_Pos (0) /*!< CRPT AES3_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7174 #define CRPT_AES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_AES3_SADDR_SADDR_Pos) /*!< CRPT AES3_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7175
<> 144:ef7eb2e8f9f7 7176 #define CRPT_AES3_DADDR_DADDR_Pos (0) /*!< CRPT AES3_DADDR: DADDR Position */
<> 144:ef7eb2e8f9f7 7177 #define CRPT_AES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_AES3_DADDR_DADDR_Pos) /*!< CRPT AES3_DADDR: DADDR Mask */
<> 144:ef7eb2e8f9f7 7178
<> 144:ef7eb2e8f9f7 7179 #define CRPT_AES3_CNT_CNT_Pos (0) /*!< CRPT AES3_CNT: CNT Position */
<> 144:ef7eb2e8f9f7 7180 #define CRPT_AES3_CNT_CNT_Msk (0xfffffffful << CRPT_AES3_CNT_CNT_Pos) /*!< CRPT AES3_CNT: CNT Mask */
<> 144:ef7eb2e8f9f7 7181
<> 144:ef7eb2e8f9f7 7182 #define CRPT_TDES_CTL_START_Pos (0) /*!< CRPT TDES_CTL: START Position */
<> 144:ef7eb2e8f9f7 7183 #define CRPT_TDES_CTL_START_Msk (0x1ul << CRPT_TDES_CTL_START_Pos) /*!< CRPT TDES_CTL: START Mask */
<> 144:ef7eb2e8f9f7 7184
<> 144:ef7eb2e8f9f7 7185 #define CRPT_TDES_CTL_STOP_Pos (1) /*!< CRPT TDES_CTL: STOP Position */
<> 144:ef7eb2e8f9f7 7186 #define CRPT_TDES_CTL_STOP_Msk (0x1ul << CRPT_TDES_CTL_STOP_Pos) /*!< CRPT TDES_CTL: STOP Mask */
<> 144:ef7eb2e8f9f7 7187
<> 144:ef7eb2e8f9f7 7188 #define CRPT_TDES_CTL_TMODE_Pos (2) /*!< CRPT TDES_CTL: TMODE Position */
<> 144:ef7eb2e8f9f7 7189 #define CRPT_TDES_CTL_TMODE_Msk (0x1ul << CRPT_TDES_CTL_TMODE_Pos) /*!< CRPT TDES_CTL: TMODE Mask */
<> 144:ef7eb2e8f9f7 7190
<> 144:ef7eb2e8f9f7 7191 #define CRPT_TDES_CTL_3KEYS_Pos (3) /*!< CRPT TDES_CTL: 3KEYS Position */
<> 144:ef7eb2e8f9f7 7192 #define CRPT_TDES_CTL_3KEYS_Msk (0x1ul << CRPT_TDES_CTL_3KEYS_Pos) /*!< CRPT TDES_CTL: 3KEYS Mask */
<> 144:ef7eb2e8f9f7 7193
<> 144:ef7eb2e8f9f7 7194 #define CRPT_TDES_CTL_DMALAST_Pos (5) /*!< CRPT TDES_CTL: DMALAST Position */
<> 144:ef7eb2e8f9f7 7195 #define CRPT_TDES_CTL_DMALAST_Msk (0x1ul << CRPT_TDES_CTL_DMALAST_Pos) /*!< CRPT TDES_CTL: DMALAST Mask */
<> 144:ef7eb2e8f9f7 7196
<> 144:ef7eb2e8f9f7 7197 #define CRPT_TDES_CTL_DMACSCAD_Pos (6) /*!< CRPT TDES_CTL: DMACSCAD Position */
<> 144:ef7eb2e8f9f7 7198 #define CRPT_TDES_CTL_DMACSCAD_Msk (0x1ul << CRPT_TDES_CTL_DMACSCAD_Pos) /*!< CRPT TDES_CTL: DMACSCAD Mask */
<> 144:ef7eb2e8f9f7 7199
<> 144:ef7eb2e8f9f7 7200 #define CRPT_TDES_CTL_DMAEN_Pos (7) /*!< CRPT TDES_CTL: DMAEN Position */
<> 144:ef7eb2e8f9f7 7201 #define CRPT_TDES_CTL_DMAEN_Msk (0x1ul << CRPT_TDES_CTL_DMAEN_Pos) /*!< CRPT TDES_CTL: DMAEN Mask */
<> 144:ef7eb2e8f9f7 7202
<> 144:ef7eb2e8f9f7 7203 #define CRPT_TDES_CTL_OPMODE_Pos (8) /*!< CRPT TDES_CTL: OPMODE Position */
<> 144:ef7eb2e8f9f7 7204 #define CRPT_TDES_CTL_OPMODE_Msk (0x7ul << CRPT_TDES_CTL_OPMODE_Pos) /*!< CRPT TDES_CTL: OPMODE Mask */
<> 144:ef7eb2e8f9f7 7205
<> 144:ef7eb2e8f9f7 7206 #define CRPT_TDES_CTL_ENCRPT_Pos (16) /*!< CRPT TDES_CTL: ENCRPT Position */
<> 144:ef7eb2e8f9f7 7207 #define CRPT_TDES_CTL_ENCRPT_Msk (0x1ul << CRPT_TDES_CTL_ENCRPT_Pos) /*!< CRPT TDES_CTL: ENCRPT Mask */
<> 144:ef7eb2e8f9f7 7208
<> 144:ef7eb2e8f9f7 7209 #define CRPT_TDES_CTL_BLKSWAP_Pos (21) /*!< CRPT TDES_CTL: BLKSWAP Position */
<> 144:ef7eb2e8f9f7 7210 #define CRPT_TDES_CTL_BLKSWAP_Msk (0x1ul << CRPT_TDES_CTL_BLKSWAP_Pos) /*!< CRPT TDES_CTL: BLKSWAP Mask */
<> 144:ef7eb2e8f9f7 7211
<> 144:ef7eb2e8f9f7 7212 #define CRPT_TDES_CTL_OUTSWAP_Pos (22) /*!< CRPT TDES_CTL: OUTSWAP Position */
<> 144:ef7eb2e8f9f7 7213 #define CRPT_TDES_CTL_OUTSWAP_Msk (0x1ul << CRPT_TDES_CTL_OUTSWAP_Pos) /*!< CRPT TDES_CTL: OUTSWAP Mask */
<> 144:ef7eb2e8f9f7 7214
<> 144:ef7eb2e8f9f7 7215 #define CRPT_TDES_CTL_INSWAP_Pos (23) /*!< CRPT TDES_CTL: INSWAP Position */
<> 144:ef7eb2e8f9f7 7216 #define CRPT_TDES_CTL_INSWAP_Msk (0x1ul << CRPT_TDES_CTL_INSWAP_Pos) /*!< CRPT TDES_CTL: INSWAP Mask */
<> 144:ef7eb2e8f9f7 7217
<> 144:ef7eb2e8f9f7 7218 #define CRPT_TDES_CTL_CHANNEL_Pos (24) /*!< CRPT TDES_CTL: CHANNEL Position */
<> 144:ef7eb2e8f9f7 7219 #define CRPT_TDES_CTL_CHANNEL_Msk (0x3ul << CRPT_TDES_CTL_CHANNEL_Pos) /*!< CRPT TDES_CTL: CHANNEL Mask */
<> 144:ef7eb2e8f9f7 7220
<> 144:ef7eb2e8f9f7 7221 #define CRPT_TDES_CTL_KEYUNPRT_Pos (26) /*!< CRPT TDES_CTL: KEYUNPRT Position */
<> 144:ef7eb2e8f9f7 7222 #define CRPT_TDES_CTL_KEYUNPRT_Msk (0x1ful << CRPT_TDES_CTL_KEYUNPRT_Pos) /*!< CRPT TDES_CTL: KEYUNPRT Mask */
<> 144:ef7eb2e8f9f7 7223
<> 144:ef7eb2e8f9f7 7224 #define CRPT_TDES_CTL_KEYPRT_Pos (31) /*!< CRPT TDES_CTL: KEYPRT Position */
<> 144:ef7eb2e8f9f7 7225 #define CRPT_TDES_CTL_KEYPRT_Msk (0x1ul << CRPT_TDES_CTL_KEYPRT_Pos) /*!< CRPT TDES_CTL: KEYPRT Mask */
<> 144:ef7eb2e8f9f7 7226
<> 144:ef7eb2e8f9f7 7227 #define CRPT_TDES_STS_BUSY_Pos (0) /*!< CRPT TDES_STS: BUSY Position */
<> 144:ef7eb2e8f9f7 7228 #define CRPT_TDES_STS_BUSY_Msk (0x1ul << CRPT_TDES_STS_BUSY_Pos) /*!< CRPT TDES_STS: BUSY Mask */
<> 144:ef7eb2e8f9f7 7229
<> 144:ef7eb2e8f9f7 7230 #define CRPT_TDES_STS_INBUFEMPTY_Pos (8) /*!< CRPT TDES_STS: INBUFEMPTY Position */
<> 144:ef7eb2e8f9f7 7231 #define CRPT_TDES_STS_INBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_INBUFEMPTY_Pos) /*!< CRPT TDES_STS: INBUFEMPTY Mask */
<> 144:ef7eb2e8f9f7 7232
<> 144:ef7eb2e8f9f7 7233 #define CRPT_TDES_STS_INBUFFULL_Pos (9) /*!< CRPT TDES_STS: INBUFFULL Position */
<> 144:ef7eb2e8f9f7 7234 #define CRPT_TDES_STS_INBUFFULL_Msk (0x1ul << CRPT_TDES_STS_INBUFFULL_Pos) /*!< CRPT TDES_STS: INBUFFULL Mask */
<> 144:ef7eb2e8f9f7 7235
<> 144:ef7eb2e8f9f7 7236 #define CRPT_TDES_STS_INBUFERR_Pos (10) /*!< CRPT TDES_STS: INBUFERR Position */
<> 144:ef7eb2e8f9f7 7237 #define CRPT_TDES_STS_INBUFERR_Msk (0x1ul << CRPT_TDES_STS_INBUFERR_Pos) /*!< CRPT TDES_STS: INBUFERR Mask */
<> 144:ef7eb2e8f9f7 7238
<> 144:ef7eb2e8f9f7 7239 #define CRPT_TDES_STS_OUTBUFEMPTY_Pos (16) /*!< CRPT TDES_STS: OUTBUFEMPTY Position */
<> 144:ef7eb2e8f9f7 7240 #define CRPT_TDES_STS_OUTBUFEMPTY_Msk (0x1ul << CRPT_TDES_STS_OUTBUFEMPTY_Pos) /*!< CRPT TDES_STS: OUTBUFEMPTY Mask */
<> 144:ef7eb2e8f9f7 7241
<> 144:ef7eb2e8f9f7 7242 #define CRPT_TDES_STS_OUTBUFFULL_Pos (17) /*!< CRPT TDES_STS: OUTBUFFULL Position */
<> 144:ef7eb2e8f9f7 7243 #define CRPT_TDES_STS_OUTBUFFULL_Msk (0x1ul << CRPT_TDES_STS_OUTBUFFULL_Pos) /*!< CRPT TDES_STS: OUTBUFFULL Mask */
<> 144:ef7eb2e8f9f7 7244
<> 144:ef7eb2e8f9f7 7245 #define CRPT_TDES_STS_OUTBUFERR_Pos (18) /*!< CRPT TDES_STS: OUTBUFERR Position */
<> 144:ef7eb2e8f9f7 7246 #define CRPT_TDES_STS_OUTBUFERR_Msk (0x1ul << CRPT_TDES_STS_OUTBUFERR_Pos) /*!< CRPT TDES_STS: OUTBUFERR Mask */
<> 144:ef7eb2e8f9f7 7247
<> 144:ef7eb2e8f9f7 7248 #define CRPT_TDES_STS_BUSERR_Pos (20) /*!< CRPT TDES_STS: BUSERR Position */
<> 144:ef7eb2e8f9f7 7249 #define CRPT_TDES_STS_BUSERR_Msk (0x1ul << CRPT_TDES_STS_BUSERR_Pos) /*!< CRPT TDES_STS: BUSERR Mask */
<> 144:ef7eb2e8f9f7 7250
<> 144:ef7eb2e8f9f7 7251 #define CRPT_TDES0_KEY1H_KEY_Pos (0) /*!< CRPT TDES0_KEY1H: KEY Position */
<> 144:ef7eb2e8f9f7 7252 #define CRPT_TDES0_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1H_KEY_Pos) /*!< CRPT TDES0_KEY1H: KEY Mask */
<> 144:ef7eb2e8f9f7 7253
<> 144:ef7eb2e8f9f7 7254 #define CRPT_TDES0_KEY1L_KEY_Pos (0) /*!< CRPT TDES0_KEY1L: KEY Position */
<> 144:ef7eb2e8f9f7 7255 #define CRPT_TDES0_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY1L_KEY_Pos) /*!< CRPT TDES0_KEY1L: KEY Mask */
<> 144:ef7eb2e8f9f7 7256
<> 144:ef7eb2e8f9f7 7257 #define CRPT_TDES0_KEY2H_KEY_Pos (0) /*!< CRPT TDES0_KEY2H: KEY Position */
<> 144:ef7eb2e8f9f7 7258 #define CRPT_TDES0_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2H_KEY_Pos) /*!< CRPT TDES0_KEY2H: KEY Mask */
<> 144:ef7eb2e8f9f7 7259
<> 144:ef7eb2e8f9f7 7260 #define CRPT_TDES0_KEY2L_KEY_Pos (0) /*!< CRPT TDES0_KEY2L: KEY Position */
<> 144:ef7eb2e8f9f7 7261 #define CRPT_TDES0_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY2L_KEY_Pos) /*!< CRPT TDES0_KEY2L: KEY Mask */
<> 144:ef7eb2e8f9f7 7262
<> 144:ef7eb2e8f9f7 7263 #define CRPT_TDES0_KEY3H_KEY_Pos (0) /*!< CRPT TDES0_KEY3H: KEY Position */
<> 144:ef7eb2e8f9f7 7264 #define CRPT_TDES0_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3H_KEY_Pos) /*!< CRPT TDES0_KEY3H: KEY Mask */
<> 144:ef7eb2e8f9f7 7265
<> 144:ef7eb2e8f9f7 7266 #define CRPT_TDES0_KEY3L_KEY_Pos (0) /*!< CRPT TDES0_KEY3L: KEY Position */
<> 144:ef7eb2e8f9f7 7267 #define CRPT_TDES0_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES0_KEY3L_KEY_Pos) /*!< CRPT TDES0_KEY3L: KEY Mask */
<> 144:ef7eb2e8f9f7 7268
<> 144:ef7eb2e8f9f7 7269 #define CRPT_TDES0_IVH_IV_Pos (0) /*!< CRPT TDES0_IVH: IV Position */
<> 144:ef7eb2e8f9f7 7270 #define CRPT_TDES0_IVH_IV_Msk (0xfffffffful << CRPT_TDES0_IVH_IV_Pos) /*!< CRPT TDES0_IVH: IV Mask */
<> 144:ef7eb2e8f9f7 7271
<> 144:ef7eb2e8f9f7 7272 #define CRPT_TDES0_IVL_IV_Pos (0) /*!< CRPT TDES0_IVL: IV Position */
<> 144:ef7eb2e8f9f7 7273 #define CRPT_TDES0_IVL_IV_Msk (0xfffffffful << CRPT_TDES0_IVL_IV_Pos) /*!< CRPT TDES0_IVL: IV Mask */
<> 144:ef7eb2e8f9f7 7274
<> 144:ef7eb2e8f9f7 7275 #define CRPT_TDES0_SADDR_SADDR_Pos (0) /*!< CRPT TDES0_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7276 #define CRPT_TDES0_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES0_SADDR_SADDR_Pos) /*!< CRPT TDES0_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7277
<> 144:ef7eb2e8f9f7 7278 #define CRPT_TDES0_DADDR_DADDR_Pos (0) /*!< CRPT TDES0_DADDR: DADDR Position */
<> 144:ef7eb2e8f9f7 7279 #define CRPT_TDES0_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES0_DADDR_DADDR_Pos) /*!< CRPT TDES0_DADDR: DADDR Mask */
<> 144:ef7eb2e8f9f7 7280
<> 144:ef7eb2e8f9f7 7281 #define CRPT_TDES0_CNT_CNT_Pos (0) /*!< CRPT TDES0_CNT: CNT Position */
<> 144:ef7eb2e8f9f7 7282 #define CRPT_TDES0_CNT_CNT_Msk (0xfffffffful << CRPT_TDES0_CNT_CNT_Pos) /*!< CRPT TDES0_CNT: CNT Mask */
<> 144:ef7eb2e8f9f7 7283
<> 144:ef7eb2e8f9f7 7284 #define CRPT_TDES_DATIN_DATIN_Pos (0) /*!< CRPT TDES_DATIN: DATIN Position */
<> 144:ef7eb2e8f9f7 7285 #define CRPT_TDES_DATIN_DATIN_Msk (0xfffffffful << CRPT_TDES_DATIN_DATIN_Pos) /*!< CRPT TDES_DATIN: DATIN Mask */
<> 144:ef7eb2e8f9f7 7286
<> 144:ef7eb2e8f9f7 7287 #define CRPT_TDES_DATOUT_DATOUT_Pos (0) /*!< CRPT TDES_DATOUT: DATOUT Position */
<> 144:ef7eb2e8f9f7 7288 #define CRPT_TDES_DATOUT_DATOUT_Msk (0xfffffffful << CRPT_TDES_DATOUT_DATOUT_Pos) /*!< CRPT TDES_DATOUT: DATOUT Mask */
<> 144:ef7eb2e8f9f7 7289
<> 144:ef7eb2e8f9f7 7290 #define CRPT_TDES1_KEY1H_KEY_Pos (0) /*!< CRPT TDES1_KEY1H: KEY Position */
<> 144:ef7eb2e8f9f7 7291 #define CRPT_TDES1_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1H_KEY_Pos) /*!< CRPT TDES1_KEY1H: KEY Mask */
<> 144:ef7eb2e8f9f7 7292
<> 144:ef7eb2e8f9f7 7293 #define CRPT_TDES1_KEY1L_KEYL_Pos (0) /*!< CRPT TDES1_KEY1L: KEY Position */
<> 144:ef7eb2e8f9f7 7294 #define CRPT_TDES1_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY1L_KEY_Pos) /*!< CRPT TDES1_KEY1L: KEY Mask */
<> 144:ef7eb2e8f9f7 7295
<> 144:ef7eb2e8f9f7 7296 #define CRPT_TDES1_KEY2H_KEY_Pos (0) /*!< CRPT TDES1_KEY2H: KEY Position */
<> 144:ef7eb2e8f9f7 7297 #define CRPT_TDES1_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2H_KEY_Pos) /*!< CRPT TDES1_KEY2H: KEY Mask */
<> 144:ef7eb2e8f9f7 7298
<> 144:ef7eb2e8f9f7 7299 #define CRPT_TDES1_KEY2L_KEY_Pos (0) /*!< CRPT TDES1_KEY2L: KEY Position */
<> 144:ef7eb2e8f9f7 7300 #define CRPT_TDES1_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY2L_KEY_Pos) /*!< CRPT TDES1_KEY2L: KEY Mask */
<> 144:ef7eb2e8f9f7 7301
<> 144:ef7eb2e8f9f7 7302 #define CRPT_TDES1_KEY3H_KEY_Pos (0) /*!< CRPT TDES1_KEY3H: KEY Position */
<> 144:ef7eb2e8f9f7 7303 #define CRPT_TDES1_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3H_KEY_Pos) /*!< CRPT TDES1_KEY3H: KEY Mask */
<> 144:ef7eb2e8f9f7 7304
<> 144:ef7eb2e8f9f7 7305 #define CRPT_TDES1_KEY3L_KEY_Pos (0) /*!< CRPT TDES1_KEY3L: KEY Position */
<> 144:ef7eb2e8f9f7 7306 #define CRPT_TDES1_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES1_KEY3L_KEY_Pos) /*!< CRPT TDES1_KEY3L: KEY Mask */
<> 144:ef7eb2e8f9f7 7307
<> 144:ef7eb2e8f9f7 7308 #define CRPT_TDES1_IVH_IV_Pos (0) /*!< CRPT TDES1_IVH: IV Position */
<> 144:ef7eb2e8f9f7 7309 #define CRPT_TDES1_IVH_IV_Msk (0xfffffffful << CRPT_TDES1_IVH_IV_Pos) /*!< CRPT TDES1_IVH: IV Mask */
<> 144:ef7eb2e8f9f7 7310
<> 144:ef7eb2e8f9f7 7311 #define CRPT_TDES1_IVL_IV_Pos (0) /*!< CRPT TDES1_IVL: IV Position */
<> 144:ef7eb2e8f9f7 7312 #define CRPT_TDES1_IVL_IV_Msk (0xfffffffful << CRPT_TDES1_IVL_IV_Pos) /*!< CRPT TDES1_IVL: IV Mask */
<> 144:ef7eb2e8f9f7 7313
<> 144:ef7eb2e8f9f7 7314 #define CRPT_TDES1_SADDR_SADDR_Pos (0) /*!< CRPT TDES1_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7315 #define CRPT_TDES1_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES1_SADDR_SADDR_Pos) /*!< CRPT TDES1_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7316
<> 144:ef7eb2e8f9f7 7317 #define CRPT_TDES1_DADDR_DADDR_Pos (0) /*!< CRPT TDES1_DADDR: DADDR Position */
<> 144:ef7eb2e8f9f7 7318 #define CRPT_TDES1_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES1_DADDR_DADDR_Pos) /*!< CRPT TDES1_DADDR: DADDR Mask */
<> 144:ef7eb2e8f9f7 7319
<> 144:ef7eb2e8f9f7 7320 #define CRPT_TDES1_CNT_CNT_Pos (0) /*!< CRPT TDES1_CNT: CNT Position */
<> 144:ef7eb2e8f9f7 7321 #define CRPT_TDES1_CNT_CNT_Msk (0xfffffffful << CRPT_TDES1_CNT_CNT_Pos) /*!< CRPT TDES1_CNT: CNT Mask */
<> 144:ef7eb2e8f9f7 7322
<> 144:ef7eb2e8f9f7 7323 #define CRPT_TDES2_KEY1H_KEY_Pos (0) /*!< CRPT TDES2_KEY1H: KEY Position */
<> 144:ef7eb2e8f9f7 7324 #define CRPT_TDES2_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1H_KEY_Pos) /*!< CRPT TDES2_KEY1H: KEY Mask */
<> 144:ef7eb2e8f9f7 7325
<> 144:ef7eb2e8f9f7 7326 #define CRPT_TDES2_KEY1L_KEY_Pos (0) /*!< CRPT TDES2_KEY1L: KEY Position */
<> 144:ef7eb2e8f9f7 7327 #define CRPT_TDES2_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY1L_KEY_Pos) /*!< CRPT TDES2_KEY1L: KEY Mask */
<> 144:ef7eb2e8f9f7 7328
<> 144:ef7eb2e8f9f7 7329 #define CRPT_TDES2_KEY2H_KEY_Pos (0) /*!< CRPT TDES2_KEY2H: KEY Position */
<> 144:ef7eb2e8f9f7 7330 #define CRPT_TDES2_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2H_KEY_Pos) /*!< CRPT TDES2_KEY2H: KEY Mask */
<> 144:ef7eb2e8f9f7 7331
<> 144:ef7eb2e8f9f7 7332 #define CRPT_TDES2_KEY2L_KEY_Pos (0) /*!< CRPT TDES2_KEY2L: KEY Position */
<> 144:ef7eb2e8f9f7 7333 #define CRPT_TDES2_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY2L_KEY_Pos) /*!< CRPT TDES2_KEY2L: KEY Mask */
<> 144:ef7eb2e8f9f7 7334
<> 144:ef7eb2e8f9f7 7335 #define CRPT_TDES2_KEY3H_KEY_Pos (0) /*!< CRPT TDES2_KEY3H: KEY Position */
<> 144:ef7eb2e8f9f7 7336 #define CRPT_TDES2_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3H_KEY_Pos) /*!< CRPT TDES2_KEY3H: KEY Mask */
<> 144:ef7eb2e8f9f7 7337
<> 144:ef7eb2e8f9f7 7338 #define CRPT_TDES2_KEY3L_KEY_Pos (0) /*!< CRPT TDES2_KEY3L: KEY Position */
<> 144:ef7eb2e8f9f7 7339 #define CRPT_TDES2_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES2_KEY3L_KEY_Pos) /*!< CRPT TDES2_KEY3L: KEY Mask */
<> 144:ef7eb2e8f9f7 7340
<> 144:ef7eb2e8f9f7 7341 #define CRPT_TDES2_IVH_IV_Pos (0) /*!< CRPT TDES2_IVH: IV Position */
<> 144:ef7eb2e8f9f7 7342 #define CRPT_TDES2_IVH_IV_Msk (0xfffffffful << CRPT_TDES2_IVH_IV_Pos) /*!< CRPT TDES2_IVH: IV Mask */
<> 144:ef7eb2e8f9f7 7343
<> 144:ef7eb2e8f9f7 7344 #define CRPT_TDES2_IVL_IV_Pos (0) /*!< CRPT TDES2_IVL: IV Position */
<> 144:ef7eb2e8f9f7 7345 #define CRPT_TDES2_IVL_IV_Msk (0xfffffffful << CRPT_TDES2_IVL_IV_Pos) /*!< CRPT TDES2_IVL: IV Mask */
<> 144:ef7eb2e8f9f7 7346
<> 144:ef7eb2e8f9f7 7347 #define CRPT_TDES2_SADDR_SADDR_Pos (0) /*!< CRPT TDES2_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7348 #define CRPT_TDES2_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES2_SADDR_SADDR_Pos) /*!< CRPT TDES2_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7349
<> 144:ef7eb2e8f9f7 7350 #define CRPT_TDES2_DADDR_DADDR_Pos (0) /*!< CRPT TDES2_DADDR: DADDR Position */
<> 144:ef7eb2e8f9f7 7351 #define CRPT_TDES2_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES2_DADDR_DADDR_Pos) /*!< CRPT TDES2_DADDR: DADDR Mask */
<> 144:ef7eb2e8f9f7 7352
<> 144:ef7eb2e8f9f7 7353 #define CRPT_TDES2_CNT_CNT_Pos (0) /*!< CRPT TDES2_CNT: CNT Position */
<> 144:ef7eb2e8f9f7 7354 #define CRPT_TDES2_CNT_CNT_Msk (0xfffffffful << CRPT_TDES2_CNT_CNT_Pos) /*!< CRPT TDES2_CNT: CNT Mask */
<> 144:ef7eb2e8f9f7 7355
<> 144:ef7eb2e8f9f7 7356 #define CRPT_TDES3_KEY1H_KEY_Pos (0) /*!< CRPT TDES3_KEY1H: KEY Position */
<> 144:ef7eb2e8f9f7 7357 #define CRPT_TDES3_KEY1H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1H_KEY_Pos) /*!< CRPT TDES3_KEY1H: KEY Mask */
<> 144:ef7eb2e8f9f7 7358
<> 144:ef7eb2e8f9f7 7359 #define CRPT_TDES3_KEY1L_KEY_Pos (0) /*!< CRPT TDES3_KEY1L: KEY Position */
<> 144:ef7eb2e8f9f7 7360 #define CRPT_TDES3_KEY1L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY1L_KEY_Pos) /*!< CRPT TDES3_KEY1L: KEY Mask */
<> 144:ef7eb2e8f9f7 7361
<> 144:ef7eb2e8f9f7 7362 #define CRPT_TDES3_KEY2H_KEY_Pos (0) /*!< CRPT TDES3_KEY2H: KEY Position */
<> 144:ef7eb2e8f9f7 7363 #define CRPT_TDES3_KEY2H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2H_KEY_Pos) /*!< CRPT TDES3_KEY2H: KEY Mask */
<> 144:ef7eb2e8f9f7 7364
<> 144:ef7eb2e8f9f7 7365 #define CRPT_TDES3_KEY2L_KEY_Pos (0) /*!< CRPT TDES3_KEY2L: KEY Position */
<> 144:ef7eb2e8f9f7 7366 #define CRPT_TDES3_KEY2L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY2L_KEY_Pos) /*!< CRPT TDES3_KEY2L: KEY Mask */
<> 144:ef7eb2e8f9f7 7367
<> 144:ef7eb2e8f9f7 7368 #define CRPT_TDES3_KEY3H_KEY_Pos (0) /*!< CRPT TDES3_KEY3H: KEY Position */
<> 144:ef7eb2e8f9f7 7369 #define CRPT_TDES3_KEY3H_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3H_KEY_Pos) /*!< CRPT TDES3_KEY3H: KEY Mask */
<> 144:ef7eb2e8f9f7 7370
<> 144:ef7eb2e8f9f7 7371 #define CRPT_TDES3_KEY3L_KEY_Pos (0) /*!< CRPT TDES3_KEY3L: KEY Position */
<> 144:ef7eb2e8f9f7 7372 #define CRPT_TDES3_KEY3L_KEY_Msk (0xfffffffful << CRPT_TDES3_KEY3L_KEY_Pos) /*!< CRPT TDES3_KEY3L: KEY Mask */
<> 144:ef7eb2e8f9f7 7373
<> 144:ef7eb2e8f9f7 7374 #define CRPT_TDES3_IVH_IV_Pos (0) /*!< CRPT TDES3_IVH: IV Position */
<> 144:ef7eb2e8f9f7 7375 #define CRPT_TDES3_IVH_IV_Msk (0xfffffffful << CRPT_TDES3_IVH_IV_Pos) /*!< CRPT TDES3_IVH: IV Mask */
<> 144:ef7eb2e8f9f7 7376
<> 144:ef7eb2e8f9f7 7377 #define CRPT_TDES3_IVL_IV_Pos (0) /*!< CRPT TDES3_IVL: IV Position */
<> 144:ef7eb2e8f9f7 7378 #define CRPT_TDES3_IVL_IV_Msk (0xfffffffful << CRPT_TDES3_IVL_IV_Pos) /*!< CRPT TDES3_IVL: IV Mask */
<> 144:ef7eb2e8f9f7 7379
<> 144:ef7eb2e8f9f7 7380 #define CRPT_TDES3_SADDR_SADDR_Pos (0) /*!< CRPT TDES3_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7381 #define CRPT_TDES3_SADDR_SADDR_Msk (0xfffffffful << CRPT_TDES3_SADDR_SADDR_Pos) /*!< CRPT TDES3_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7382
<> 144:ef7eb2e8f9f7 7383 #define CRPT_TDES3_DADDR_DADDR_Pos (0) /*!< CRPT TDES3_DADDR: DADDR Position */
<> 144:ef7eb2e8f9f7 7384 #define CRPT_TDES3_DADDR_DADDR_Msk (0xfffffffful << CRPT_TDES3_DADDR_DADDR_Pos) /*!< CRPT TDES3_DADDR: DADDR Mask */
<> 144:ef7eb2e8f9f7 7385
<> 144:ef7eb2e8f9f7 7386 #define CRPT_TDES3_CNT_CNT_Pos (0) /*!< CRPT TDES3_CNT: CNT Position */
<> 144:ef7eb2e8f9f7 7387 #define CRPT_TDES3_CNT_CNT_Msk (0xfffffffful << CRPT_TDES3_CNT_CNT_Pos) /*!< CRPT TDES3_CNT: CNT Mask */
<> 144:ef7eb2e8f9f7 7388
<> 144:ef7eb2e8f9f7 7389 #define CRPT_SHA_CTL_START_Pos (0) /*!< CRPT SHA_CTL: START Position */
<> 144:ef7eb2e8f9f7 7390 #define CRPT_SHA_CTL_START_Msk (0x1ul << CRPT_SHA_CTL_START_Pos) /*!< CRPT SHA_CTL: START Mask */
<> 144:ef7eb2e8f9f7 7391
<> 144:ef7eb2e8f9f7 7392 #define CRPT_SHA_CTL_STOP_Pos (1) /*!< CRPT SHA_CTL: STOP Position */
<> 144:ef7eb2e8f9f7 7393 #define CRPT_SHA_CTL_STOP_Msk (0x1ul << CRPT_SHA_CTL_STOP_Pos) /*!< CRPT SHA_CTL: STOP Mask */
<> 144:ef7eb2e8f9f7 7394
<> 144:ef7eb2e8f9f7 7395 #define CRPT_SHA_CTL_DMALAST_Pos (5) /*!< CRPT SHA_CTL: DMALAST Position */
<> 144:ef7eb2e8f9f7 7396 #define CRPT_SHA_CTL_DMALAST_Msk (0x1ul << CRPT_SHA_CTL_DMALAST_Pos) /*!< CRPT SHA_CTL: DMALAST Mask */
<> 144:ef7eb2e8f9f7 7397
<> 144:ef7eb2e8f9f7 7398 #define CRPT_SHA_CTL_DMAEN_Pos (7) /*!< CRPT SHA_CTL: DMAEN Position */
<> 144:ef7eb2e8f9f7 7399 #define CRPT_SHA_CTL_DMAEN_Msk (0x1ul << CRPT_SHA_CTL_DMAEN_Pos) /*!< CRPT SHA_CTL: DMAEN Mask */
<> 144:ef7eb2e8f9f7 7400
<> 144:ef7eb2e8f9f7 7401 #define CRPT_SHA_CTL_OPMODE_Pos (8) /*!< CRPT SHA_CTL: OPMODE Position */
<> 144:ef7eb2e8f9f7 7402 #define CRPT_SHA_CTL_OPMODE_Msk (0x7ul << CRPT_SHA_CTL_OPMODE_Pos) /*!< CRPT SHA_CTL: OPMODE Mask */
<> 144:ef7eb2e8f9f7 7403
<> 144:ef7eb2e8f9f7 7404 #define CRPT_SHA_CTL_OUTSWAP_Pos (22) /*!< CRPT SHA_CTL: OUTSWAP Position */
<> 144:ef7eb2e8f9f7 7405 #define CRPT_SHA_CTL_OUTSWAP_Msk (0x1ul << CRPT_SHA_CTL_OUTSWAP_Pos) /*!< CRPT SHA_CTL: OUTSWAP Mask */
<> 144:ef7eb2e8f9f7 7406
<> 144:ef7eb2e8f9f7 7407 #define CRPT_SHA_CTL_INSWAP_Pos (23) /*!< CRPT SHA_CTL: INSWAP Position */
<> 144:ef7eb2e8f9f7 7408 #define CRPT_SHA_CTL_INSWAP_Msk (0x1ul << CRPT_SHA_CTL_INSWAP_Pos) /*!< CRPT SHA_CTL: INSWAP Mask */
<> 144:ef7eb2e8f9f7 7409
<> 144:ef7eb2e8f9f7 7410 #define CRPT_SHA_STS_BUSY_Pos (0) /*!< CRPT SHA_STS: BUSY Position */
<> 144:ef7eb2e8f9f7 7411 #define CRPT_SHA_STS_BUSY_Msk (0x1ul << CRPT_SHA_STS_BUSY_Pos) /*!< CRPT SHA_STS: BUSY Mask */
<> 144:ef7eb2e8f9f7 7412
<> 144:ef7eb2e8f9f7 7413 #define CRPT_SHA_STS_DMABUSY_Pos (1) /*!< CRPT SHA_STS: DMABUSY Position */
<> 144:ef7eb2e8f9f7 7414 #define CRPT_SHA_STS_DMABUSY_Msk (0x1ul << CRPT_SHA_STS_DMABUSY_Pos) /*!< CRPT SHA_STS: DMABUSY Mask */
<> 144:ef7eb2e8f9f7 7415
<> 144:ef7eb2e8f9f7 7416 #define CRPT_SHA_STS_DMAERR_Pos (8) /*!< CRPT SHA_STS: DMAERR Position */
<> 144:ef7eb2e8f9f7 7417 #define CRPT_SHA_STS_DMAERR_Msk (0x1ul << CRPT_SHA_STS_DMAERR_Pos) /*!< CRPT SHA_STS: DMAERR Mask */
<> 144:ef7eb2e8f9f7 7418
<> 144:ef7eb2e8f9f7 7419 #define CRPT_SHA_STS_DATINREQ_Pos (16) /*!< CRPT SHA_STS: DATINREQ Position */
<> 144:ef7eb2e8f9f7 7420 #define CRPT_SHA_STS_DATINREQ_Msk (0x1ul << CRPT_SHA_STS_DATINREQ_Pos) /*!< CRPT SHA_STS: DATINREQ Mask */
<> 144:ef7eb2e8f9f7 7421
<> 144:ef7eb2e8f9f7 7422 #define CRPT_SHA_DGST0_DGST_Pos (0) /*!< CRPT SHA_DGST0: DGST Position */
<> 144:ef7eb2e8f9f7 7423 #define CRPT_SHA_DGST0_DGST_Msk (0xfffffffful << CRPT_SHA_DGST0_DGST_Pos) /*!< CRPT SHA_DGST0: DGST Mask */
<> 144:ef7eb2e8f9f7 7424
<> 144:ef7eb2e8f9f7 7425 #define CRPT_SHA_DGST1_DGST_Pos (0) /*!< CRPT SHA_DGST1: DGST Position */
<> 144:ef7eb2e8f9f7 7426 #define CRPT_SHA_DGST1_DGST_Msk (0xfffffffful << CRPT_SHA_DGST1_DGST_Pos) /*!< CRPT SHA_DGST1: DGST Mask */
<> 144:ef7eb2e8f9f7 7427
<> 144:ef7eb2e8f9f7 7428 #define CRPT_SHA_DGST2_DGST_Pos (0) /*!< CRPT SHA_DGST2: DGST Position */
<> 144:ef7eb2e8f9f7 7429 #define CRPT_SHA_DGST2_DGST_Msk (0xfffffffful << CRPT_SHA_DGST2_DGST_Pos) /*!< CRPT SHA_DGST2: DGST Mask */
<> 144:ef7eb2e8f9f7 7430
<> 144:ef7eb2e8f9f7 7431 #define CRPT_SHA_DGST3_DGST_Pos (0) /*!< CRPT SHA_DGST3: DGST Position */
<> 144:ef7eb2e8f9f7 7432 #define CRPT_SHA_DGST3_DGST_Msk (0xfffffffful << CRPT_SHA_DGST3_DGST_Pos) /*!< CRPT SHA_DGST3: DGST Mask */
<> 144:ef7eb2e8f9f7 7433
<> 144:ef7eb2e8f9f7 7434 #define CRPT_SHA_DGST4_DGST_Pos (0) /*!< CRPT SHA_DGST4: DGST Position */
<> 144:ef7eb2e8f9f7 7435 #define CRPT_SHA_DGST4_DGST_Msk (0xfffffffful << CRPT_SHA_DGST4_DGST_Pos) /*!< CRPT SHA_DGST4: DGST Mask */
<> 144:ef7eb2e8f9f7 7436
<> 144:ef7eb2e8f9f7 7437 #define CRPT_SHA_DGST5_DGST_Pos (0) /*!< CRPT SHA_DGST5: DGST Position */
<> 144:ef7eb2e8f9f7 7438 #define CRPT_SHA_DGST5_DGST_Msk (0xfffffffful << CRPT_SHA_DGST5_DGST_Pos) /*!< CRPT SHA_DGST5: DGST Mask */
<> 144:ef7eb2e8f9f7 7439
<> 144:ef7eb2e8f9f7 7440 #define CRPT_SHA_DGST6_DGST_Pos (0) /*!< CRPT SHA_DGST6: DGST Position */
<> 144:ef7eb2e8f9f7 7441 #define CRPT_SHA_DGST6_DGST_Msk (0xfffffffful << CRPT_SHA_DGST6_DGST_Pos) /*!< CRPT SHA_DGST6: DGST Mask */
<> 144:ef7eb2e8f9f7 7442
<> 144:ef7eb2e8f9f7 7443 #define CRPT_SHA_DGST7_DGST_Pos (0) /*!< CRPT SHA_DGST7: DGST Position */
<> 144:ef7eb2e8f9f7 7444 #define CRPT_SHA_DGST7_DGST_Msk (0xfffffffful << CRPT_SHA_DGST7_DGST_Pos) /*!< CRPT SHA_DGST7: DGST Mask */
<> 144:ef7eb2e8f9f7 7445
<> 144:ef7eb2e8f9f7 7446 #define CRPT_SHA_KEYCNT_KEYCNT_Pos (0) /*!< CRPT SHA_KEYCNT: KEYCNT Position */
<> 144:ef7eb2e8f9f7 7447 #define CRPT_SHA_KEYCNT_KEYCNT_Msk (0xfffffffful << CRPT_SHA_KEYCNT_KEYCNT_Pos) /*!< CRPT SHA_KEYCNT: KEYCNT Mask */
<> 144:ef7eb2e8f9f7 7448
<> 144:ef7eb2e8f9f7 7449 #define CRPT_SHA_SADDR_SADDR_Pos (0) /*!< CRPT SHA_SADDR: SADDR Position */
<> 144:ef7eb2e8f9f7 7450 #define CRPT_SHA_SADDR_SADDR_Msk (0xfffffffful << CRPT_SHA_SADDR_SADDR_Pos) /*!< CRPT SHA_SADDR: SADDR Mask */
<> 144:ef7eb2e8f9f7 7451
<> 144:ef7eb2e8f9f7 7452 #define CRPT_SHA_DMACNT_DMACNT_Pos (0) /*!< CRPT SHA_DMACNT: DMACNT Position */
<> 144:ef7eb2e8f9f7 7453 #define CRPT_SHA_DMACNT_DMACNT_Msk (0xfffffffful << CRPT_SHA_DMACNT_DMACNT_Pos) /*!< CRPT SHA_DMACNT: DMACNT Mask */
<> 144:ef7eb2e8f9f7 7454
<> 144:ef7eb2e8f9f7 7455 #define CRPT_SHA_DATIN_DATIN_Pos (0) /*!< CRPT SHA_DATIN: DATIN Position */
<> 144:ef7eb2e8f9f7 7456 #define CRPT_SHA_DATIN_DATIN_Msk (0xfffffffful << CRPT_SHA_DATIN_DATIN_Pos) /*!< CRPT SHA_DATIN: DATIN Mask */
<> 144:ef7eb2e8f9f7 7457
<> 144:ef7eb2e8f9f7 7458 /**@}*/ /* CRPT_CONST */
<> 144:ef7eb2e8f9f7 7459 /**@}*/ /* end of CRPT register group */
<> 144:ef7eb2e8f9f7 7460
<> 144:ef7eb2e8f9f7 7461
<> 144:ef7eb2e8f9f7 7462 /*---------------------- Enhanced Analog to Digital Converter -------------------------*/
<> 144:ef7eb2e8f9f7 7463 /**
<> 144:ef7eb2e8f9f7 7464 @addtogroup EADC Enhanced Analog to Digital Converter(EADC)
<> 144:ef7eb2e8f9f7 7465 Memory Mapped Structure for EADC Controller
<> 144:ef7eb2e8f9f7 7466 @{ */
<> 144:ef7eb2e8f9f7 7467
<> 144:ef7eb2e8f9f7 7468 typedef struct {
<> 144:ef7eb2e8f9f7 7469
<> 144:ef7eb2e8f9f7 7470
<> 144:ef7eb2e8f9f7 7471 /**
<> 144:ef7eb2e8f9f7 7472 * AD0DAT0
<> 144:ef7eb2e8f9f7 7473 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7474 * Offset: 0x00 A/D Data Register 0 for SAMPLE00
<> 144:ef7eb2e8f9f7 7475 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7476 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7477 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7478 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7479 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7480 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7481 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7482 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7483 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7484 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7485 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7486 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7487 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7488 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7489 */
<> 144:ef7eb2e8f9f7 7490 __I uint32_t AD0DAT0;
<> 144:ef7eb2e8f9f7 7491
<> 144:ef7eb2e8f9f7 7492 /**
<> 144:ef7eb2e8f9f7 7493 * AD0DAT1
<> 144:ef7eb2e8f9f7 7494 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7495 * Offset: 0x04 A/D Data Register 1 for SAMPLE01
<> 144:ef7eb2e8f9f7 7496 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7497 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7498 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7499 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7500 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7501 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7502 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7503 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7504 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7505 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7506 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7507 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7508 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7509 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7510 */
<> 144:ef7eb2e8f9f7 7511 __I uint32_t AD0DAT1;
<> 144:ef7eb2e8f9f7 7512
<> 144:ef7eb2e8f9f7 7513 /**
<> 144:ef7eb2e8f9f7 7514 * AD0DAT2
<> 144:ef7eb2e8f9f7 7515 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7516 * Offset: 0x08 A/D Data Register 2 for SAMPLE02
<> 144:ef7eb2e8f9f7 7517 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7518 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7519 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7520 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7521 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7522 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7523 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7524 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7525 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7526 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7527 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7528 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7529 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7530 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7531 */
<> 144:ef7eb2e8f9f7 7532 __I uint32_t AD0DAT2;
<> 144:ef7eb2e8f9f7 7533
<> 144:ef7eb2e8f9f7 7534 /**
<> 144:ef7eb2e8f9f7 7535 * AD0DAT3
<> 144:ef7eb2e8f9f7 7536 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7537 * Offset: 0x0C A/D Data Register 3 for SAMPLE03
<> 144:ef7eb2e8f9f7 7538 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7539 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7540 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7541 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7542 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7543 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7544 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7545 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7546 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7547 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7548 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7549 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7550 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7551 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7552 */
<> 144:ef7eb2e8f9f7 7553 __I uint32_t AD0DAT3;
<> 144:ef7eb2e8f9f7 7554
<> 144:ef7eb2e8f9f7 7555 /**
<> 144:ef7eb2e8f9f7 7556 * AD0DAT4
<> 144:ef7eb2e8f9f7 7557 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7558 * Offset: 0x10 A/D Data Register 4 for SAMPLE04
<> 144:ef7eb2e8f9f7 7559 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7560 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7561 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7562 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7563 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7564 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7565 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7566 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7567 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7568 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7569 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7570 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7571 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7572 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7573 */
<> 144:ef7eb2e8f9f7 7574 __I uint32_t AD0DAT4;
<> 144:ef7eb2e8f9f7 7575
<> 144:ef7eb2e8f9f7 7576 /**
<> 144:ef7eb2e8f9f7 7577 * AD0DAT5
<> 144:ef7eb2e8f9f7 7578 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7579 * Offset: 0x14 A/D Data Register 5 for SAMPLE05
<> 144:ef7eb2e8f9f7 7580 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7581 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7582 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7583 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7584 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7585 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7586 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7587 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7588 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7589 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7590 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7591 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7592 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7593 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7594 */
<> 144:ef7eb2e8f9f7 7595 __I uint32_t AD0DAT5;
<> 144:ef7eb2e8f9f7 7596
<> 144:ef7eb2e8f9f7 7597 /**
<> 144:ef7eb2e8f9f7 7598 * AD0DAT6
<> 144:ef7eb2e8f9f7 7599 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7600 * Offset: 0x18 A/D Data Register 6 for SAMPLE06
<> 144:ef7eb2e8f9f7 7601 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7602 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7603 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7604 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7605 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7606 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7607 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7608 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7609 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7610 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7611 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7612 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7613 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7614 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7615 */
<> 144:ef7eb2e8f9f7 7616 __I uint32_t AD0DAT6;
<> 144:ef7eb2e8f9f7 7617
<> 144:ef7eb2e8f9f7 7618 /**
<> 144:ef7eb2e8f9f7 7619 * AD0DAT7
<> 144:ef7eb2e8f9f7 7620 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7621 * Offset: 0x1C A/D Data Register 7 for SAMPLE07
<> 144:ef7eb2e8f9f7 7622 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7623 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7624 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7625 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7626 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7627 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7628 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7629 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7630 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7631 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7632 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7633 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7634 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7635 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7636 */
<> 144:ef7eb2e8f9f7 7637 __I uint32_t AD0DAT7;
<> 144:ef7eb2e8f9f7 7638
<> 144:ef7eb2e8f9f7 7639 /**
<> 144:ef7eb2e8f9f7 7640 * AD1DAT0
<> 144:ef7eb2e8f9f7 7641 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7642 * Offset: 0x20 A/D Data Register 8 for SAMPLE10
<> 144:ef7eb2e8f9f7 7643 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7644 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7645 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7646 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7647 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7648 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7649 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7650 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7651 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7652 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7653 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7654 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7655 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7656 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7657 */
<> 144:ef7eb2e8f9f7 7658 __I uint32_t AD1DAT0;
<> 144:ef7eb2e8f9f7 7659
<> 144:ef7eb2e8f9f7 7660 /**
<> 144:ef7eb2e8f9f7 7661 * AD1DAT1
<> 144:ef7eb2e8f9f7 7662 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7663 * Offset: 0x24 A/D Data Register 9 for SAMPLE11
<> 144:ef7eb2e8f9f7 7664 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7665 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7666 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7667 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7668 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7669 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7670 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7671 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7672 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7673 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7674 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7675 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7676 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7677 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7678 */
<> 144:ef7eb2e8f9f7 7679 __I uint32_t AD1DAT1;
<> 144:ef7eb2e8f9f7 7680
<> 144:ef7eb2e8f9f7 7681 /**
<> 144:ef7eb2e8f9f7 7682 * AD1DAT2
<> 144:ef7eb2e8f9f7 7683 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7684 * Offset: 0x28 A/D Data Register 10 for SAMPLE12
<> 144:ef7eb2e8f9f7 7685 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7686 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7687 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7688 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7689 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7690 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7691 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7692 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7693 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7694 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7695 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7696 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7697 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7698 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7699 */
<> 144:ef7eb2e8f9f7 7700 __I uint32_t AD1DAT2;
<> 144:ef7eb2e8f9f7 7701
<> 144:ef7eb2e8f9f7 7702 /**
<> 144:ef7eb2e8f9f7 7703 * AD1DAT3
<> 144:ef7eb2e8f9f7 7704 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7705 * Offset: 0x2C A/D Data Register 11 for SAMPLE13
<> 144:ef7eb2e8f9f7 7706 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7707 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7708 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7709 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7710 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7711 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7712 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7713 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7714 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7715 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7716 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7717 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7718 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7719 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7720 */
<> 144:ef7eb2e8f9f7 7721 __I uint32_t AD1DAT3;
<> 144:ef7eb2e8f9f7 7722
<> 144:ef7eb2e8f9f7 7723 /**
<> 144:ef7eb2e8f9f7 7724 * AD1DAT4
<> 144:ef7eb2e8f9f7 7725 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7726 * Offset: 0x30 A/D Data Register 12 for SAMPLE14
<> 144:ef7eb2e8f9f7 7727 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7728 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7729 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7730 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7731 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7732 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7733 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7734 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7735 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7736 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7737 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7738 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7739 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7740 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7741 */
<> 144:ef7eb2e8f9f7 7742 __I uint32_t AD1DAT4;
<> 144:ef7eb2e8f9f7 7743
<> 144:ef7eb2e8f9f7 7744 /**
<> 144:ef7eb2e8f9f7 7745 * AD1DAT5
<> 144:ef7eb2e8f9f7 7746 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7747 * Offset: 0x34 A/D Data Register 13 for SAMPLE15
<> 144:ef7eb2e8f9f7 7748 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7749 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7750 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7751 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7752 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7753 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7754 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7755 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7756 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7757 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7758 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7759 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7760 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7761 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7762 */
<> 144:ef7eb2e8f9f7 7763 __I uint32_t AD1DAT5;
<> 144:ef7eb2e8f9f7 7764
<> 144:ef7eb2e8f9f7 7765 /**
<> 144:ef7eb2e8f9f7 7766 * AD1DAT6
<> 144:ef7eb2e8f9f7 7767 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7768 * Offset: 0x38 A/D Data Register 14 for SAMPLE16
<> 144:ef7eb2e8f9f7 7769 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7770 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7771 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7772 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7773 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7774 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7775 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7776 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7777 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7778 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7779 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7780 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7781 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7782 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7783 */
<> 144:ef7eb2e8f9f7 7784 __I uint32_t AD1DAT6;
<> 144:ef7eb2e8f9f7 7785
<> 144:ef7eb2e8f9f7 7786 /**
<> 144:ef7eb2e8f9f7 7787 * AD1DAT7
<> 144:ef7eb2e8f9f7 7788 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7789 * Offset: 0x3C A/D Data Register 15 for SAMPLE17
<> 144:ef7eb2e8f9f7 7790 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7791 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7792 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7793 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 7794 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 7795 * |[16] |OV |Overrun Flag
<> 144:ef7eb2e8f9f7 7796 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is recent conversion result.
<> 144:ef7eb2e8f9f7 7797 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is overwrite.
<> 144:ef7eb2e8f9f7 7798 * | | |If converted data in RESULT (EADC_ADnDATx[11:0]) has not been read before new conversion result is loaded to this register, OV (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 7799 * | | |It is cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7800 * |[17] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 7801 * | | |0 = Data in RESULT (EADC_ADnDATx[11:0]) is not valid.
<> 144:ef7eb2e8f9f7 7802 * | | |1 = Data in RESULT (EADC_ADnDATx[11:0]) is valid.
<> 144:ef7eb2e8f9f7 7803 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 7804 */
<> 144:ef7eb2e8f9f7 7805 __I uint32_t AD1DAT7;
<> 144:ef7eb2e8f9f7 7806
<> 144:ef7eb2e8f9f7 7807 /**
<> 144:ef7eb2e8f9f7 7808 * CTL
<> 144:ef7eb2e8f9f7 7809 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7810 * Offset: 0x40 A/D Control Register
<> 144:ef7eb2e8f9f7 7811 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7812 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7813 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7814 * |[0] |ADCEN |A/D Converter Enable Control
<> 144:ef7eb2e8f9f7 7815 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 7816 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 7817 * | | |Before starting A/D conversion function, this bit should be set to 1.
<> 144:ef7eb2e8f9f7 7818 * | | |Clear it to 0 to disable A/D converter analog circuit power consumption.
<> 144:ef7eb2e8f9f7 7819 * |[1] |ADCRST |ADC0, ADC1 A/D Converter Control Circuits Reset
<> 144:ef7eb2e8f9f7 7820 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 7821 * | | |1 = Cause ADC control circuits reset to initial state, but not change the ADC registers value.
<> 144:ef7eb2e8f9f7 7822 * | | |The ADCRST (EADC_CTL [1]) bit remains 1 during ADC reset, when ADC reset end, the ADCRST (EADC_CTL [1]) bit is automatically cleared to 0.
<> 144:ef7eb2e8f9f7 7823 * |[2] |ADCIEN0 |Specific SAMPLE A/D ADINT0 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 7824 * | | |0 = Specific SAMPLE A/D ADINT0 interrupt function Disabled.
<> 144:ef7eb2e8f9f7 7825 * | | |1 = Specific SAMPLE A/D ADINT0 interrupt function Enabled.
<> 144:ef7eb2e8f9f7 7826 * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS1 [0]) flag upon the end of specific SAMPLE A/D conversion.
<> 144:ef7eb2e8f9f7 7827 * | | |If ADCIEN0 (EADC_CTL [2]) bit is set then conversion end interrupt request ADINT0 is generated.
<> 144:ef7eb2e8f9f7 7828 * |[3] |ADCIEN1 |Specific SAMPLE A/D ADINT1 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 7829 * | | |0 = Specific SAMPLE A/D ADINT1 interrupt function Disabled.
<> 144:ef7eb2e8f9f7 7830 * | | |1 = Specific SAMPLE A/D ADINT1 interrupt function Enabled.
<> 144:ef7eb2e8f9f7 7831 * | | |The A/D converter generates a conversion end ADIF0 (EADC_STATUS1 [1]) flag upon the end of specific SAMPLE A/D conversion.
<> 144:ef7eb2e8f9f7 7832 * | | |If ADCIEN1 EADC_CTL [3]) bit is set then conversion end interrupt request ADINT1 is generated.
<> 144:ef7eb2e8f9f7 7833 * |[4] |ADCIEN2 |Specific SAMPLE A/D ADINT2 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 7834 * | | |0 = Specific SAMPLE A/D ADINT2 interrupt function Disabled.
<> 144:ef7eb2e8f9f7 7835 * | | |1 = Specific SAMPLE A/D ADINT2 interrupt function Enabled.
<> 144:ef7eb2e8f9f7 7836 * | | |The A/D converter generates a conversion end ADIF2 (EADC_STATUS1 [2]) flag upon the end of specific SAMPLE A/D conversion.
<> 144:ef7eb2e8f9f7 7837 * | | |If ADCIEN2 (EADC_CTL [4]) bit is set then conversion end interrupt request ADINT2 is generated.
<> 144:ef7eb2e8f9f7 7838 * |[5] |ADCIEN3 |Specific SAMPLE A/D ADINT3 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 7839 * | | |0 = Specific SAMPLE A/D ADINT3 interrupt function Disabled.
<> 144:ef7eb2e8f9f7 7840 * | | |1 = Specific SAMPLE A/D ADINT3 interrupt function Enabled.
<> 144:ef7eb2e8f9f7 7841 * | | |The A/D converter generates a conversion end ADIF3 (EADC_STATUS1 [3]) flag upon the end of specific SAMPLE A/D conversion.
<> 144:ef7eb2e8f9f7 7842 * | | |If ADCIEN3 (EADC_CTL [5]) bit is set then conversion end interrupt request ADINT3 is generated.
<> 144:ef7eb2e8f9f7 7843 */
<> 144:ef7eb2e8f9f7 7844 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 7845 uint32_t RESERVE0[1];
<> 144:ef7eb2e8f9f7 7846
<> 144:ef7eb2e8f9f7 7847
<> 144:ef7eb2e8f9f7 7848 /**
<> 144:ef7eb2e8f9f7 7849 * SWTRG
<> 144:ef7eb2e8f9f7 7850 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7851 * Offset: 0x48 A/D SAMPLE Software Start Register
<> 144:ef7eb2e8f9f7 7852 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7853 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7854 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7855 * |[0:7] |SWTRG7_0 |A/D SAMPLE07~SAMPLE00 Software Force To Start ADC Conversion
<> 144:ef7eb2e8f9f7 7856 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 7857 * | | |1 = Start an ADC conversion when the priority is given to SAMPLE0x.
<> 144:ef7eb2e8f9f7 7858 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 7859 * |[8:15] |SWTRG15_8 |A/D SAMPLE17~SAMPLE10 Software Force To Start ADC Conversion
<> 144:ef7eb2e8f9f7 7860 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 7861 * | | |1 = Start an ADC conversion when the priority is given to SAMPLE1x.
<> 144:ef7eb2e8f9f7 7862 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 7863 */
<> 144:ef7eb2e8f9f7 7864 __O uint32_t SWTRG;
<> 144:ef7eb2e8f9f7 7865
<> 144:ef7eb2e8f9f7 7866 /**
<> 144:ef7eb2e8f9f7 7867 * PENDSTS
<> 144:ef7eb2e8f9f7 7868 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7869 * Offset: 0x4C A/D Start of Conversion Pending Flag Register
<> 144:ef7eb2e8f9f7 7870 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7871 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7872 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7873 * |[0:7] |STPF7_0 |A/D SAMPLE07~SAMPLE00 Start Of Conversion Pending Flag
<> 144:ef7eb2e8f9f7 7874 * | | |0 = There is no pending conversion for SAMPLE0x.
<> 144:ef7eb2e8f9f7 7875 * | | |1 = SAMPLE0x ADC start of conversion is pending.
<> 144:ef7eb2e8f9f7 7876 * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is started, the STPF bit is automatically cleared to 0.
<> 144:ef7eb2e8f9f7 7877 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 7878 * |[8:15] |STPF15_8 |A/D SAMPLE17~SAMPLE10 Start Of Conversion Pending Flag
<> 144:ef7eb2e8f9f7 7879 * | | |0 = There is no pending conversion for SAMPLE1x.
<> 144:ef7eb2e8f9f7 7880 * | | |1 = SAMPLE1x ADC start of conversion is pending.
<> 144:ef7eb2e8f9f7 7881 * | | |Note: This bit remains 1 during pending state, when the respective ADC conversion is started, the STPF bit is automatically cleared to 0.
<> 144:ef7eb2e8f9f7 7882 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 7883 */
<> 144:ef7eb2e8f9f7 7884 __I uint32_t PENDSTS;
<> 144:ef7eb2e8f9f7 7885
<> 144:ef7eb2e8f9f7 7886 /**
<> 144:ef7eb2e8f9f7 7887 * ADIFOV
<> 144:ef7eb2e8f9f7 7888 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7889 * Offset: 0x50 A/D ADINT3~0 Interrupt Flag Overrun Register
<> 144:ef7eb2e8f9f7 7890 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7891 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7892 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7893 * |[0] |ADFOV0 |A/D ADINT0 Interrupt Flag Overrun
<> 144:ef7eb2e8f9f7 7894 * | | |0 = ADINT0 interrupt flag is not overwritten to 1.
<> 144:ef7eb2e8f9f7 7895 * | | |1 = ADINT0 interrupt flag is overwritten to 1.
<> 144:ef7eb2e8f9f7 7896 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 7897 * |[1] |ADFOV1 |A/D ADINT1 Interrupt Flag Overrun
<> 144:ef7eb2e8f9f7 7898 * | | |0 = ADINT1 interrupt flag is not overwritten to 1.
<> 144:ef7eb2e8f9f7 7899 * | | |1 = ADINT1 interrupt flag is overwritten to 1.
<> 144:ef7eb2e8f9f7 7900 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 7901 * |[2] |ADFOV2 |A/D ADINT2 Interrupt Flag Overrun
<> 144:ef7eb2e8f9f7 7902 * | | |0 = ADINT2 interrupt flag is not overwritten to 1.
<> 144:ef7eb2e8f9f7 7903 * | | |1 = ADINT2 interrupt flag is overwritten to 1.
<> 144:ef7eb2e8f9f7 7904 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 7905 * |[3] |ADFOV3 |A/D ADINT3 Interrupt Flag Overrun
<> 144:ef7eb2e8f9f7 7906 * | | |0 = ADINT3 interrupt flag is not overwritten to 1.
<> 144:ef7eb2e8f9f7 7907 * | | |1 = ADINT3 interrupt flag is overwritten to 1.
<> 144:ef7eb2e8f9f7 7908 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 7909 */
<> 144:ef7eb2e8f9f7 7910 __IO uint32_t ADIFOV;
<> 144:ef7eb2e8f9f7 7911
<> 144:ef7eb2e8f9f7 7912 /**
<> 144:ef7eb2e8f9f7 7913 * OVSTS
<> 144:ef7eb2e8f9f7 7914 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7915 * Offset: 0x54 A/D SAMPLE Start of Conversion Overrun Flag Register
<> 144:ef7eb2e8f9f7 7916 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7917 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7918 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7919 * |[0:7] |SPOVF7_0 |A/D SAMPLE07~SAMPLE00 Start Of Conversion Overrun Flag
<> 144:ef7eb2e8f9f7 7920 * | | |0 = No SAMPLE0x event overrun.
<> 144:ef7eb2e8f9f7 7921 * | | |1 = Indicates a new SAMPLE0x event is generated while an old one event is pending.
<> 144:ef7eb2e8f9f7 7922 * | | |If there is a new trigger event comes when the SAMPLE is pending for the last trigger event, the overrun is happened and the SPOVF bit will be set as 1.
<> 144:ef7eb2e8f9f7 7923 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 7924 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 7925 * |[8:15] |SPOVF15_8 |A/D SAMPLE17~SAMPLE10 Start Of Conversion Overrun Flag
<> 144:ef7eb2e8f9f7 7926 * | | |0 = No SAMPLE1x event overrun.
<> 144:ef7eb2e8f9f7 7927 * | | |1 = Indicates a new SAMPLE1x event is generated while an old one event is pending.
<> 144:ef7eb2e8f9f7 7928 * | | |If there is a new trigger event comes when the SAMPLE is pending for the last trigger event, the overrun is happened and the SPOVF bit will be set as 1.
<> 144:ef7eb2e8f9f7 7929 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 7930 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 7931 */
<> 144:ef7eb2e8f9f7 7932 __IO uint32_t OVSTS;
<> 144:ef7eb2e8f9f7 7933
<> 144:ef7eb2e8f9f7 7934 /**
<> 144:ef7eb2e8f9f7 7935 * AD0SPCTL0
<> 144:ef7eb2e8f9f7 7936 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7937 * Offset: 0x58 A/D SAMPLE00 Control Register
<> 144:ef7eb2e8f9f7 7938 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7939 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7940 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7941 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 7942 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 7943 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 7944 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 7945 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 7946 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 7947 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 7948 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 7949 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 7950 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 7951 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 7952 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 7953 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 7954 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 7955 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 7956 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 7957 * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 7958 * | | |0000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 7959 * | | |0001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 7960 * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 7961 * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 7962 * | | |0100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 7963 * | | |0101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 7964 * | | |0110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 7965 * | | |0111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 7966 * | | |1000 = EPWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 7967 * | | |1001 = EPWM0_CH2 trigger.
<> 144:ef7eb2e8f9f7 7968 * | | |1010 = EPWM0_CH4 trigger.
<> 144:ef7eb2e8f9f7 7969 * | | |1011 = EPWM1_CH0 trigger.
<> 144:ef7eb2e8f9f7 7970 * | | |1100 = EPWM1_CH2 trigger.
<> 144:ef7eb2e8f9f7 7971 * | | |1101 = EPWM1_CH4 trigger.
<> 144:ef7eb2e8f9f7 7972 * | | |1110 = PWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 7973 * | | |1111 = PWM0_CH1 trigger.
<> 144:ef7eb2e8f9f7 7974 * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
<> 144:ef7eb2e8f9f7 7975 * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
<> 144:ef7eb2e8f9f7 7976 * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
<> 144:ef7eb2e8f9f7 7977 * | | |Trigger delay clock frequency:
<> 144:ef7eb2e8f9f7 7978 * | | |00 = ADC_CLK/1.
<> 144:ef7eb2e8f9f7 7979 * | | |01 = ADC_CLK/2.
<> 144:ef7eb2e8f9f7 7980 * | | |10 = ADC_CLK/4.
<> 144:ef7eb2e8f9f7 7981 * | | |11 = ADC_CLK/16.
<> 144:ef7eb2e8f9f7 7982 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 7983 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 7984 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 7985 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 7986 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 7987 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 7988 */
<> 144:ef7eb2e8f9f7 7989 __IO uint32_t AD0SPCTL0;
<> 144:ef7eb2e8f9f7 7990
<> 144:ef7eb2e8f9f7 7991 /**
<> 144:ef7eb2e8f9f7 7992 * AD0SPCTL1
<> 144:ef7eb2e8f9f7 7993 * ===================================================================================================
<> 144:ef7eb2e8f9f7 7994 * Offset: 0x5C A/D SAMPLE01 Control Register
<> 144:ef7eb2e8f9f7 7995 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 7996 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 7997 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 7998 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 7999 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8000 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8001 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8002 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8003 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8004 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8005 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8006 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8007 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8008 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8009 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8010 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8011 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8012 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8013 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8014 * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8015 * | | |0000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8016 * | | |0001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8017 * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8018 * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8019 * | | |0100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8020 * | | |0101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8021 * | | |0110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8022 * | | |0111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8023 * | | |1000 = EPWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8024 * | | |1001 = EPWM0_CH2 trigger.
<> 144:ef7eb2e8f9f7 8025 * | | |1010 = EPWM0_CH4 trigger.
<> 144:ef7eb2e8f9f7 8026 * | | |1011 = EPWM1_CH0 trigger.
<> 144:ef7eb2e8f9f7 8027 * | | |1100 = EPWM1_CH2 trigger.
<> 144:ef7eb2e8f9f7 8028 * | | |1101 = EPWM1_CH4 trigger.
<> 144:ef7eb2e8f9f7 8029 * | | |1110 = PWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8030 * | | |1111 = PWM0_CH1 trigger.
<> 144:ef7eb2e8f9f7 8031 * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
<> 144:ef7eb2e8f9f7 8032 * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
<> 144:ef7eb2e8f9f7 8033 * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
<> 144:ef7eb2e8f9f7 8034 * | | |Trigger delay clock frequency:
<> 144:ef7eb2e8f9f7 8035 * | | |00 = ADC_CLK/1.
<> 144:ef7eb2e8f9f7 8036 * | | |01 = ADC_CLK/2.
<> 144:ef7eb2e8f9f7 8037 * | | |10 = ADC_CLK/4.
<> 144:ef7eb2e8f9f7 8038 * | | |11 = ADC_CLK/16.
<> 144:ef7eb2e8f9f7 8039 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8040 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8041 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8042 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8043 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8044 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8045 */
<> 144:ef7eb2e8f9f7 8046 __IO uint32_t AD0SPCTL1;
<> 144:ef7eb2e8f9f7 8047
<> 144:ef7eb2e8f9f7 8048 /**
<> 144:ef7eb2e8f9f7 8049 * AD0SPCTL2
<> 144:ef7eb2e8f9f7 8050 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8051 * Offset: 0x60 A/D SAMPLE02 Control Register
<> 144:ef7eb2e8f9f7 8052 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8053 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8054 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8055 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8056 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8057 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8058 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8059 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8060 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8061 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8062 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8063 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8064 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8065 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8066 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8067 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8068 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8069 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8070 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8071 * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8072 * | | |0000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8073 * | | |0001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8074 * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8075 * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8076 * | | |0100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8077 * | | |0101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8078 * | | |0110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8079 * | | |0111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8080 * | | |1000 = EPWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8081 * | | |1001 = EPWM0_CH2 trigger.
<> 144:ef7eb2e8f9f7 8082 * | | |1010 = EPWM0_CH4 trigger.
<> 144:ef7eb2e8f9f7 8083 * | | |1011 = EPWM1_CH0 trigger.
<> 144:ef7eb2e8f9f7 8084 * | | |1100 = EPWM1_CH2 trigger.
<> 144:ef7eb2e8f9f7 8085 * | | |1101 = EPWM1_CH4 trigger.
<> 144:ef7eb2e8f9f7 8086 * | | |1110 = PWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8087 * | | |1111 = PWM0_CH1 trigger.
<> 144:ef7eb2e8f9f7 8088 * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
<> 144:ef7eb2e8f9f7 8089 * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
<> 144:ef7eb2e8f9f7 8090 * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
<> 144:ef7eb2e8f9f7 8091 * | | |Trigger delay clock frequency:
<> 144:ef7eb2e8f9f7 8092 * | | |00 = ADC_CLK/1.
<> 144:ef7eb2e8f9f7 8093 * | | |01 = ADC_CLK/2.
<> 144:ef7eb2e8f9f7 8094 * | | |10 = ADC_CLK/4.
<> 144:ef7eb2e8f9f7 8095 * | | |11 = ADC_CLK/16.
<> 144:ef7eb2e8f9f7 8096 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8097 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8098 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8099 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8100 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8101 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8102 */
<> 144:ef7eb2e8f9f7 8103 __IO uint32_t AD0SPCTL2;
<> 144:ef7eb2e8f9f7 8104
<> 144:ef7eb2e8f9f7 8105 /**
<> 144:ef7eb2e8f9f7 8106 * AD0SPCTL3
<> 144:ef7eb2e8f9f7 8107 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8108 * Offset: 0x64 A/D SAMPLE03 Control Register
<> 144:ef7eb2e8f9f7 8109 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8110 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8111 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8112 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8113 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8114 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8115 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8116 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8117 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8118 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8119 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8120 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8121 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8122 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8123 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8124 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8125 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8126 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8127 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8128 * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8129 * | | |0000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8130 * | | |0001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8131 * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8132 * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8133 * | | |0100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8134 * | | |0101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8135 * | | |0110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8136 * | | |0111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8137 * | | |1000 = EPWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8138 * | | |1001 = EPWM0_CH2 trigger.
<> 144:ef7eb2e8f9f7 8139 * | | |1010 = EPWM0_CH4 trigger.
<> 144:ef7eb2e8f9f7 8140 * | | |1011 = EPWM1_CH0 trigger.
<> 144:ef7eb2e8f9f7 8141 * | | |1100 = EPWM1_CH2 trigger.
<> 144:ef7eb2e8f9f7 8142 * | | |1101 = EPWM1_CH4 trigger.
<> 144:ef7eb2e8f9f7 8143 * | | |1110 = PWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8144 * | | |1111 = PWM0_CH1 trigger.
<> 144:ef7eb2e8f9f7 8145 * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
<> 144:ef7eb2e8f9f7 8146 * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
<> 144:ef7eb2e8f9f7 8147 * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
<> 144:ef7eb2e8f9f7 8148 * | | |Trigger delay clock frequency:
<> 144:ef7eb2e8f9f7 8149 * | | |00 = ADC_CLK/1.
<> 144:ef7eb2e8f9f7 8150 * | | |01 = ADC_CLK/2.
<> 144:ef7eb2e8f9f7 8151 * | | |10 = ADC_CLK/4.
<> 144:ef7eb2e8f9f7 8152 * | | |11 = ADC_CLK/16.
<> 144:ef7eb2e8f9f7 8153 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8154 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8155 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8156 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8157 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8158 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8159 */
<> 144:ef7eb2e8f9f7 8160 __IO uint32_t AD0SPCTL3;
<> 144:ef7eb2e8f9f7 8161
<> 144:ef7eb2e8f9f7 8162 /**
<> 144:ef7eb2e8f9f7 8163 * AD0SPCTL4
<> 144:ef7eb2e8f9f7 8164 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8165 * Offset: 0x68 A/D SAMPLE04 Control Register
<> 144:ef7eb2e8f9f7 8166 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8167 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8168 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8169 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8170 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8171 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8172 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8173 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8174 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8175 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8176 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8177 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8178 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8179 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8180 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8181 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8182 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8183 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8184 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8185 * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8186 * | | |000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8187 * | | |001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8188 * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8189 * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8190 * | | |100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8191 * | | |101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8192 * | | |110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8193 * | | |111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8194 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8195 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8196 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8197 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8198 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8199 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8200 */
<> 144:ef7eb2e8f9f7 8201 __IO uint32_t AD0SPCTL4;
<> 144:ef7eb2e8f9f7 8202
<> 144:ef7eb2e8f9f7 8203 /**
<> 144:ef7eb2e8f9f7 8204 * AD0SPCTL5
<> 144:ef7eb2e8f9f7 8205 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8206 * Offset: 0x6C A/D SAMPLE05 Control Register
<> 144:ef7eb2e8f9f7 8207 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8208 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8209 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8210 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8211 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8212 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8213 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8214 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8215 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8216 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8217 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8218 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8219 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8220 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8221 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8222 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8223 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8224 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8225 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8226 * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8227 * | | |000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8228 * | | |001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8229 * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8230 * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8231 * | | |100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8232 * | | |101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8233 * | | |110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8234 * | | |111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8235 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8236 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8237 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8238 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8239 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8240 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8241 */
<> 144:ef7eb2e8f9f7 8242 __IO uint32_t AD0SPCTL5;
<> 144:ef7eb2e8f9f7 8243
<> 144:ef7eb2e8f9f7 8244 /**
<> 144:ef7eb2e8f9f7 8245 * AD0SPCTL6
<> 144:ef7eb2e8f9f7 8246 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8247 * Offset: 0x70 A/D SAMPLE06 Control Register
<> 144:ef7eb2e8f9f7 8248 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8249 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8250 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8251 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8252 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8253 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8254 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8255 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8256 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8257 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8258 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8259 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8260 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8261 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8262 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8263 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8264 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8265 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8266 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8267 * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8268 * | | |000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8269 * | | |001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8270 * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8271 * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8272 * | | |100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8273 * | | |101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8274 * | | |110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8275 * | | |111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8276 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8277 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8278 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8279 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8280 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8281 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8282 */
<> 144:ef7eb2e8f9f7 8283 __IO uint32_t AD0SPCTL6;
<> 144:ef7eb2e8f9f7 8284
<> 144:ef7eb2e8f9f7 8285 /**
<> 144:ef7eb2e8f9f7 8286 * AD0SPCTL7
<> 144:ef7eb2e8f9f7 8287 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8288 * Offset: 0x74 A/D SAMPLE07 Control Register
<> 144:ef7eb2e8f9f7 8289 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8290 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8291 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8292 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8293 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8294 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8295 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8296 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8297 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8298 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8299 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8300 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8301 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8302 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8303 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8304 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8305 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8306 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8307 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8308 * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8309 * | | |000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8310 * | | |001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8311 * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8312 * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8313 * | | |100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8314 * | | |101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8315 * | | |110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8316 * | | |111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8317 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8318 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8319 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8320 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8321 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8322 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8323 */
<> 144:ef7eb2e8f9f7 8324 __IO uint32_t AD0SPCTL7;
<> 144:ef7eb2e8f9f7 8325
<> 144:ef7eb2e8f9f7 8326 /**
<> 144:ef7eb2e8f9f7 8327 * AD1SPCTL0
<> 144:ef7eb2e8f9f7 8328 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8329 * Offset: 0x78 A/D SAMPLE10 Control Register
<> 144:ef7eb2e8f9f7 8330 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8331 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8332 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8333 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8334 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8335 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8336 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8337 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8338 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8339 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8340 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8341 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8342 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8343 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8344 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8345 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8346 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8347 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8348 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8349 * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8350 * | | |0000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8351 * | | |0001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8352 * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8353 * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8354 * | | |0100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8355 * | | |0101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8356 * | | |0110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8357 * | | |0111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8358 * | | |1000 = EPWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8359 * | | |1001 = EPWM0_CH2 trigger.
<> 144:ef7eb2e8f9f7 8360 * | | |1010 = EPWM0_CH4 trigger.
<> 144:ef7eb2e8f9f7 8361 * | | |1011 = EPWM1_CH0 trigger.
<> 144:ef7eb2e8f9f7 8362 * | | |1100 = EPWM1_CH2 trigger.
<> 144:ef7eb2e8f9f7 8363 * | | |1101 = EPWM1_CH4 trigger.
<> 144:ef7eb2e8f9f7 8364 * | | |1110 = PWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8365 * | | |1111 = PWM0_CH1 trigger.
<> 144:ef7eb2e8f9f7 8366 * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
<> 144:ef7eb2e8f9f7 8367 * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
<> 144:ef7eb2e8f9f7 8368 * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
<> 144:ef7eb2e8f9f7 8369 * | | |Trigger delay clock frequency:
<> 144:ef7eb2e8f9f7 8370 * | | |00 = ADC_CLK/1.
<> 144:ef7eb2e8f9f7 8371 * | | |01 = ADC_CLK/2.
<> 144:ef7eb2e8f9f7 8372 * | | |10 = ADC_CLK/4.
<> 144:ef7eb2e8f9f7 8373 * | | |11 = ADC_CLK/16.
<> 144:ef7eb2e8f9f7 8374 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8375 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8376 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8377 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8378 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8379 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8380 */
<> 144:ef7eb2e8f9f7 8381 __IO uint32_t AD1SPCTL0;
<> 144:ef7eb2e8f9f7 8382
<> 144:ef7eb2e8f9f7 8383 /**
<> 144:ef7eb2e8f9f7 8384 * AD1SPCTL1
<> 144:ef7eb2e8f9f7 8385 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8386 * Offset: 0x7C A/D SAMPLE11 Control Register
<> 144:ef7eb2e8f9f7 8387 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8388 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8389 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8390 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8391 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8392 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8393 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8394 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8395 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8396 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8397 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8398 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8399 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8400 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8401 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8402 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8403 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8404 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8405 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8406 * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8407 * | | |0000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8408 * | | |0001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8409 * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8410 * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8411 * | | |0100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8412 * | | |0101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8413 * | | |0110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8414 * | | |0111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8415 * | | |1000 = EPWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8416 * | | |1001 = EPWM0_CH2 trigger.
<> 144:ef7eb2e8f9f7 8417 * | | |1010 = EPWM0_CH4 trigger.
<> 144:ef7eb2e8f9f7 8418 * | | |1011 = EPWM1_CH0 trigger.
<> 144:ef7eb2e8f9f7 8419 * | | |1100 = EPWM1_CH2 trigger.
<> 144:ef7eb2e8f9f7 8420 * | | |1101 = EPWM1_CH4 trigger.
<> 144:ef7eb2e8f9f7 8421 * | | |1110 = PWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8422 * | | |1111 = PWM0_CH1 trigger.
<> 144:ef7eb2e8f9f7 8423 * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
<> 144:ef7eb2e8f9f7 8424 * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
<> 144:ef7eb2e8f9f7 8425 * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
<> 144:ef7eb2e8f9f7 8426 * | | |Trigger delay clock frequency:
<> 144:ef7eb2e8f9f7 8427 * | | |00 = ADC_CLK/1.
<> 144:ef7eb2e8f9f7 8428 * | | |01 = ADC_CLK/2.
<> 144:ef7eb2e8f9f7 8429 * | | |10 = ADC_CLK/4.
<> 144:ef7eb2e8f9f7 8430 * | | |11 = ADC_CLK/16.
<> 144:ef7eb2e8f9f7 8431 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8432 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8433 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8434 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8435 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8436 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8437 */
<> 144:ef7eb2e8f9f7 8438 __IO uint32_t AD1SPCTL1;
<> 144:ef7eb2e8f9f7 8439
<> 144:ef7eb2e8f9f7 8440 /**
<> 144:ef7eb2e8f9f7 8441 * AD1SPCTL2
<> 144:ef7eb2e8f9f7 8442 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8443 * Offset: 0x80 A/D SAMPLE12 Control Register
<> 144:ef7eb2e8f9f7 8444 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8445 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8446 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8447 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8448 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8449 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8450 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8451 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8452 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8453 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8454 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8455 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8456 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8457 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8458 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8459 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8460 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8461 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8462 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8463 * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8464 * | | |0000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8465 * | | |0001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8466 * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8467 * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8468 * | | |0100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8469 * | | |0101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8470 * | | |0110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8471 * | | |0111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8472 * | | |1000 = EPWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8473 * | | |1001 = EPWM0_CH2 trigger.
<> 144:ef7eb2e8f9f7 8474 * | | |1010 = EPWM0_CH4 trigger.
<> 144:ef7eb2e8f9f7 8475 * | | |1011 = EPWM1_CH0 trigger.
<> 144:ef7eb2e8f9f7 8476 * | | |1100 = EPWM1_CH2 trigger.
<> 144:ef7eb2e8f9f7 8477 * | | |1101 = EPWM1_CH4 trigger.
<> 144:ef7eb2e8f9f7 8478 * | | |1110 = PWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8479 * | | |1111 = PWM0_CH1 trigger.
<> 144:ef7eb2e8f9f7 8480 * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
<> 144:ef7eb2e8f9f7 8481 * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
<> 144:ef7eb2e8f9f7 8482 * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
<> 144:ef7eb2e8f9f7 8483 * | | |Trigger delay clock frequency:
<> 144:ef7eb2e8f9f7 8484 * | | |00 = ADC_CLK/1.
<> 144:ef7eb2e8f9f7 8485 * | | |01 = ADC_CLK/2.
<> 144:ef7eb2e8f9f7 8486 * | | |10 = ADC_CLK/4.
<> 144:ef7eb2e8f9f7 8487 * | | |11 = ADC_CLK/16.
<> 144:ef7eb2e8f9f7 8488 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8489 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8490 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8491 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8492 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8493 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8494 */
<> 144:ef7eb2e8f9f7 8495 __IO uint32_t AD1SPCTL2;
<> 144:ef7eb2e8f9f7 8496
<> 144:ef7eb2e8f9f7 8497 /**
<> 144:ef7eb2e8f9f7 8498 * AD1SPCTL3
<> 144:ef7eb2e8f9f7 8499 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8500 * Offset: 0x84 A/D SAMPLE13 Control Register
<> 144:ef7eb2e8f9f7 8501 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8502 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8503 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8504 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8505 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8506 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8507 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8508 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8509 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8510 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8511 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8512 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8513 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8514 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8515 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8516 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8517 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8518 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8519 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8520 * |[4:7] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8521 * | | |0000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8522 * | | |0001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8523 * | | |0010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8524 * | | |0011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8525 * | | |0100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8526 * | | |0101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8527 * | | |0110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8528 * | | |0111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8529 * | | |1000 = EPWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8530 * | | |1001 = EPWM0_CH2 trigger.
<> 144:ef7eb2e8f9f7 8531 * | | |1010 = EPWM0_CH4 trigger.
<> 144:ef7eb2e8f9f7 8532 * | | |1011 = EPWM1_CH0 trigger.
<> 144:ef7eb2e8f9f7 8533 * | | |1100 = EPWM1_CH2 trigger.
<> 144:ef7eb2e8f9f7 8534 * | | |1101 = EPWM1_CH4 trigger.
<> 144:ef7eb2e8f9f7 8535 * | | |1110 = PWM0_CH0 trigger.
<> 144:ef7eb2e8f9f7 8536 * | | |1111 = PWM0_CH1 trigger.
<> 144:ef7eb2e8f9f7 8537 * |[8:15] |TRGDLYCNT |A/D SAMPLE Start Of Conversion Trigger Delay Time
<> 144:ef7eb2e8f9f7 8538 * | | |Trigger delay time = (TRGDLYCNT + 4) x Trigger delay clock period.
<> 144:ef7eb2e8f9f7 8539 * |[16:17] |TRGDLYDIV |A/D SAMPLE Start Of Conversion Trigger Delay Clock Divider Selection
<> 144:ef7eb2e8f9f7 8540 * | | |Trigger delay clock frequency:
<> 144:ef7eb2e8f9f7 8541 * | | |00 = ADC_CLK/1.
<> 144:ef7eb2e8f9f7 8542 * | | |01 = ADC_CLK/2.
<> 144:ef7eb2e8f9f7 8543 * | | |10 = ADC_CLK/4.
<> 144:ef7eb2e8f9f7 8544 * | | |11 = ADC_CLK/16.
<> 144:ef7eb2e8f9f7 8545 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8546 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8547 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8548 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8549 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8550 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8551 */
<> 144:ef7eb2e8f9f7 8552 __IO uint32_t AD1SPCTL3;
<> 144:ef7eb2e8f9f7 8553
<> 144:ef7eb2e8f9f7 8554 /**
<> 144:ef7eb2e8f9f7 8555 * AD1SPCTL4
<> 144:ef7eb2e8f9f7 8556 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8557 * Offset: 0x88 A/D SAMPLE14 Control Register
<> 144:ef7eb2e8f9f7 8558 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8559 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8560 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8561 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8562 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8563 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8564 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8565 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8566 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8567 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8568 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8569 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8570 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8571 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8572 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8573 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8574 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8575 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8576 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8577 * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8578 * | | |000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8579 * | | |001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8580 * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8581 * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8582 * | | |100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8583 * | | |101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8584 * | | |110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8585 * | | |111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8586 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8587 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8588 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8589 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8590 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8591 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8592 */
<> 144:ef7eb2e8f9f7 8593 __IO uint32_t AD1SPCTL4;
<> 144:ef7eb2e8f9f7 8594
<> 144:ef7eb2e8f9f7 8595 /**
<> 144:ef7eb2e8f9f7 8596 * AD1SPCTL5
<> 144:ef7eb2e8f9f7 8597 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8598 * Offset: 0x8C A/D SAMPLE15 Control Register
<> 144:ef7eb2e8f9f7 8599 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8600 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8601 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8602 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8603 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8604 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8605 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8606 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8607 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8608 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8609 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8610 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8611 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8612 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8613 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8614 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8615 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8616 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8617 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8618 * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8619 * | | |000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8620 * | | |001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8621 * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8622 * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8623 * | | |100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8624 * | | |101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8625 * | | |110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8626 * | | |111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8627 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8628 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8629 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8630 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8631 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8632 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8633 */
<> 144:ef7eb2e8f9f7 8634 __IO uint32_t AD1SPCTL5;
<> 144:ef7eb2e8f9f7 8635
<> 144:ef7eb2e8f9f7 8636 /**
<> 144:ef7eb2e8f9f7 8637 * AD1SPCTL6
<> 144:ef7eb2e8f9f7 8638 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8639 * Offset: 0x90 A/D SAMPLE16 Control Register
<> 144:ef7eb2e8f9f7 8640 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8641 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8642 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8643 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8644 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8645 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8646 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8647 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8648 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8649 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8650 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8651 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8652 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8653 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8654 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8655 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8656 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8657 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8658 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8659 * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8660 * | | |000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8661 * | | |001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8662 * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8663 * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8664 * | | |100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8665 * | | |101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8666 * | | |110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8667 * | | |111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8668 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8669 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8670 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8671 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8672 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8673 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8674 */
<> 144:ef7eb2e8f9f7 8675 __IO uint32_t AD1SPCTL6;
<> 144:ef7eb2e8f9f7 8676
<> 144:ef7eb2e8f9f7 8677 /**
<> 144:ef7eb2e8f9f7 8678 * AD1SPCTL7
<> 144:ef7eb2e8f9f7 8679 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8680 * Offset: 0x94 A/D SAMPLE17 Control Register
<> 144:ef7eb2e8f9f7 8681 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8682 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8683 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8684 * |[0:3] |CHSEL |A/D SAMPLE0,1 Channel Selection
<> 144:ef7eb2e8f9f7 8685 * | | |0000 = ADCn_CH0.
<> 144:ef7eb2e8f9f7 8686 * | | |0001 = ADCn_CH1.
<> 144:ef7eb2e8f9f7 8687 * | | |0010 = ADCn_CH2.
<> 144:ef7eb2e8f9f7 8688 * | | |0011 = ADCn_CH3.
<> 144:ef7eb2e8f9f7 8689 * | | |0100 = ADCn_CH4.
<> 144:ef7eb2e8f9f7 8690 * | | |0101 = ADCn_CH5.
<> 144:ef7eb2e8f9f7 8691 * | | |0110 = ADCn_CH6.
<> 144:ef7eb2e8f9f7 8692 * | | |0111 = ADCn_CH7.
<> 144:ef7eb2e8f9f7 8693 * | | |For SAMPLE0
<> 144:ef7eb2e8f9f7 8694 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8695 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8696 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8697 * | | |1011 = OP0.
<> 144:ef7eb2e8f9f7 8698 * | | |For SAMPLE1
<> 144:ef7eb2e8f9f7 8699 * | | |1000= OP1.
<> 144:ef7eb2e8f9f7 8700 * |[4:6] |TRGSEL |A/D SAMPLE Start Of Conversion Trigger Source Selection
<> 144:ef7eb2e8f9f7 8701 * | | |000 = Disable hardware trigger.
<> 144:ef7eb2e8f9f7 8702 * | | |001 = External pin (STADC) trigger.
<> 144:ef7eb2e8f9f7 8703 * | | |010 = ADC ADINT0 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8704 * | | |011 = ADC ADINT1 interrupt EOC pulse trigger.
<> 144:ef7eb2e8f9f7 8705 * | | |100 = Timer0 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8706 * | | |101 = Timer1 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8707 * | | |110 = Timer2 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8708 * | | |111 = Timer3 overflow pulse trigger.
<> 144:ef7eb2e8f9f7 8709 * |[20] |EXTREN |A/D External Pin Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8710 * | | |0 = A/D external pin rising edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8711 * | | |1 = A/D external pin rising edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8712 * |[21] |EXTFEN |A/D External Pin Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 8713 * | | |0 = A/D external pin falling edge trigger Disabled.
<> 144:ef7eb2e8f9f7 8714 * | | |1 = A/D external pin falling edge trigger Enabled.
<> 144:ef7eb2e8f9f7 8715 */
<> 144:ef7eb2e8f9f7 8716 __IO uint32_t AD1SPCTL7;
<> 144:ef7eb2e8f9f7 8717 uint32_t RESERVE1[3];
<> 144:ef7eb2e8f9f7 8718
<> 144:ef7eb2e8f9f7 8719
<> 144:ef7eb2e8f9f7 8720 /**
<> 144:ef7eb2e8f9f7 8721 * SIMUSEL
<> 144:ef7eb2e8f9f7 8722 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8723 * Offset: 0xA4 A/D SAMPLE Simultaneous Sampling Mode Select Register
<> 144:ef7eb2e8f9f7 8724 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8725 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8726 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8727 * |[0] |SIMUSEL0 |A/D SAMPLE00, SAMPLE10 Simultaneous Sampling Mode Selection
<> 144:ef7eb2e8f9f7 8728 * | | |0 = SAMPLE00, SAMPLE10 are in single sampling mode, both SAMPLE00 and SAMPLE10's 3 bits of CHSEL define the ADC channels to be converted.
<> 144:ef7eb2e8f9f7 8729 * | | |1 = SAMPLE00, SAMPLE10 are in simultaneous sampling mode, Only SAMPLE00 can trigger the both ADC conversions of SAMPLE00 and SAMPLE10, SAMPLE10 trigger select TRGSEL is ignored.
<> 144:ef7eb2e8f9f7 8730 * | | |If SAMPLE00's CHSEL = 1, and SAMPLE10's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
<> 144:ef7eb2e8f9f7 8731 * |[1] |SIMUSEL1 |A/D SAMPLE01, SAMPLE11 Simultaneous Sampling Mode Selection
<> 144:ef7eb2e8f9f7 8732 * | | |0 = SAMPLE01, SAMPLE11 are in single sampling mode, both SAMPLE01 and SAMPLE11's 3 bits of CHSEL define the ADC channels to be converted.
<> 144:ef7eb2e8f9f7 8733 * | | |1 = SAMPLE01, SAMPLE11 are in simultaneous sampling mode, Only SAMPLE01 can trigger the both ADC conversions of SAMPLE01 and SAMPLE11, SAMPLE11 trigger select TRGSEL is ignored.
<> 144:ef7eb2e8f9f7 8734 * | | |If SAMPLE01's CHSEL = 1, and SAMPLE11's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
<> 144:ef7eb2e8f9f7 8735 * |[2] |SIMUSEL2 |A/D SAMPLE02, SAMPLE12 Simultaneous Sampling Mode Selection
<> 144:ef7eb2e8f9f7 8736 * | | |0 = SAMPLE02, SAMPLE12 are in single sampling mode, both SAMPLE02 and SAMPLE12's 3 bits of CHSEL define the ADC channels to be converted.
<> 144:ef7eb2e8f9f7 8737 * | | |1 = SAMPLE02, SAMPLE12 are in simultaneous sampling mode, Only SAMPLE02 can trigger the both ADC conversions of SAMPLE02 and SAMPLE12, SAMPLE12 trigger select TRGSEL is ignored.
<> 144:ef7eb2e8f9f7 8738 * | | |If SAMPLE02's CHSEL = 1, and SAMPLE12's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
<> 144:ef7eb2e8f9f7 8739 * |[3] |SIMUSEL3 |A/D SAMPLE03, SAMPLE13 Simultaneous Sampling Mode Selection
<> 144:ef7eb2e8f9f7 8740 * | | |0 = SAMPLE03, SAMPLE13 are in single sampling mode, both SAMPLE03 and SAMPLE13's 3 bits of CHSEL define the ADC channels to be converted.
<> 144:ef7eb2e8f9f7 8741 * | | |1 = SAMPLE03, SAMPLE13 are in simultaneous sampling mode, Only SAMPLE03 can trigger the both ADC conversions of SAMPLE03 and SAMPLE13, SAMPLE13 trigger select TRGSEL is ignored.
<> 144:ef7eb2e8f9f7 8742 * | | |If SAMPLE03's CHSEL = 1, and SAMPLE13's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
<> 144:ef7eb2e8f9f7 8743 * |[4] |SIMUSEL4 |A/D SAMPLE04, SAMPLE14 Simultaneous Sampling Mode Selection
<> 144:ef7eb2e8f9f7 8744 * | | |0 = SAMPLE04, SAMPLE14 are in single sampling mode, both SAMPLE04 and SAMPLE14's 3 bits of CHSEL define the ADC channels to be converted.
<> 144:ef7eb2e8f9f7 8745 * | | |1 = SAMPLE04, SAMPLE14 are in simultaneous sampling mode, Only SAMPLE04 can trigger the both ADC conversions of SAMPLE04 and SAMPLE14, SAMPLE14 trigger select TRGSEL is ignored.
<> 144:ef7eb2e8f9f7 8746 * | | |If SAMPLE04's CHSEL = 1, and SAMPLE14's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
<> 144:ef7eb2e8f9f7 8747 * |[5] |SIMUSEL5 |A/D SAMPLE05, SAMPLE15 Simultaneous Sampling Mode Selection
<> 144:ef7eb2e8f9f7 8748 * | | |0 = SAMPLE05, SAMPLE15 are in single sampling mode, both SAMPLE05 and SAMPLE15's 3 bits of CHSEL define the ADC channels to be converted.
<> 144:ef7eb2e8f9f7 8749 * | | |1 = SAMPLE05, SAMPLE15 are in simultaneous sampling mode, Only SAMPLE05 can trigger the both ADC conversions of SAMPLE05 and SAMPLE15, SAMPLE15 trigger select TRGSEL is ignored.
<> 144:ef7eb2e8f9f7 8750 * | | |if SAMPLE05's CHSEL = 1, and SAMPLE15's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
<> 144:ef7eb2e8f9f7 8751 * |[6] |SIMUSEL6 |A/D SAMPLE06, SAMPLE16 Simultaneous Sampling Mode Selection
<> 144:ef7eb2e8f9f7 8752 * | | |0 = SAMPLE06, SAMPLE16 are in single sampling mode, both SAMPLE06 and SAMPLE16's 3 bits of CHSEL define the ADC channels to be converted.
<> 144:ef7eb2e8f9f7 8753 * | | |1 = SAMPLE06, SAMPLE16 are in simultaneous sampling mode, Only SAMPLE06 can trigger the both ADC conversions of SAMPLE06 and SAMPLE16, SAMPLE16 trigger select TRGSEL is ignored.
<> 144:ef7eb2e8f9f7 8754 * | | |If SAMPLE06's CHSEL = 1, and SAMPLE16's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
<> 144:ef7eb2e8f9f7 8755 * |[7] |SIMUSEL7 |A/D SAMPLE07, SAMPLE17 Simultaneous Sampling Mode Selection
<> 144:ef7eb2e8f9f7 8756 * | | |0 = SAMPLE07, SAMPLE17 are in single sampling mode, both SAMPLE07 and SAMPLE17's 3 bits of CHSEL define the ADC channels to be converted.
<> 144:ef7eb2e8f9f7 8757 * | | |1 = SAMPLE07, SAMPLE17 are in simultaneous sampling mode, Only SAMPLE07 can trigger the both ADC conversions of SAMPLE07 and SAMPLE17, SAMPLE17 trigger select TRGSEL is ignored.
<> 144:ef7eb2e8f9f7 8758 * | | |If SAMPLE07's CHSEL = 1, SAMPLE17's CHSEL = 3, the pair of channels are ADC0_CH1, ADC1_CH3, they will do the ADC conversion at the same time to reach the simulataneous sampling goal.
<> 144:ef7eb2e8f9f7 8759 */
<> 144:ef7eb2e8f9f7 8760 __IO uint32_t SIMUSEL;
<> 144:ef7eb2e8f9f7 8761
<> 144:ef7eb2e8f9f7 8762 /**
<> 144:ef7eb2e8f9f7 8763 * CMP0/1
<> 144:ef7eb2e8f9f7 8764 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8765 * Offset: 0xA8 A/D Result Compare Register 0
<> 144:ef7eb2e8f9f7 8766 * Offset: 0xAC A/D Result Compare Register 1
<> 144:ef7eb2e8f9f7 8767 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8768 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8769 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8770 * |[0] |ADCMPEN |A/D Result Compare Enable Control
<> 144:ef7eb2e8f9f7 8771 * | | |0 = Compare Disabled.
<> 144:ef7eb2e8f9f7 8772 * | | |1 = Compare Enabled.
<> 144:ef7eb2e8f9f7 8773 * | | |Set this bit to 1 to enable compare CMPDAT (EADC_CMPx[27:16]) with specified SAMPLE conversion result when converted data is loaded into ADDR register.
<> 144:ef7eb2e8f9f7 8774 * |[1] |ADCMPIE |A/D Result Compare Interrupt Enable Control
<> 144:ef7eb2e8f9f7 8775 * | | |0 = Compare function interrupt Disabled.
<> 144:ef7eb2e8f9f7 8776 * | | |1 = Compare function interrupt Enabled.
<> 144:ef7eb2e8f9f7 8777 * | | |If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPx[2]) and CMPMCNT (EADC_CMPx[11:8]), ADCMPF (EADC_STATUS1 [7:6]) bit will be asserted, in the meanwhile, if ADCMPIE (EADC_CMPx[1]) is set to 1, a compare interrupt request is generated.
<> 144:ef7eb2e8f9f7 8778 * |[2] |CMPCOND |Compare Condition
<> 144:ef7eb2e8f9f7 8779 * | | |0= Set the compare condition as that when a 12-bit A/D conversion result is less than the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one.
<> 144:ef7eb2e8f9f7 8780 * | | |1= Set the compare condition as that when a 12-bit A/D conversion result is greater or equal to the 12-bit CMPDAT (EADC_CMPx[27:16]), the internal match counter will increase one.
<> 144:ef7eb2e8f9f7 8781 * | | |Note: When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8]) + 1, the CMPF bit will be set.
<> 144:ef7eb2e8f9f7 8782 * |[3:5] |CMPSPL |Compare SAMPLE Selection
<> 144:ef7eb2e8f9f7 8783 * | | |000 = SAMPLE00 conversion result EADC_AD0DAT0 is selected to be compared.
<> 144:ef7eb2e8f9f7 8784 * | | |001 = SAMPLE01 conversion result EADC_AD0DAT1 is selected to be compared.
<> 144:ef7eb2e8f9f7 8785 * | | |010 = SAMPLE02 conversion result EADC_AD0DAT2 is selected to be compared.
<> 144:ef7eb2e8f9f7 8786 * | | |011 = SAMPLE03 conversion result EADC_AD0DAT3 is selected to be compared.
<> 144:ef7eb2e8f9f7 8787 * | | |100 = SAMPLE10 conversion result EADC_AD1DAT0 is selected to be compared.
<> 144:ef7eb2e8f9f7 8788 * | | |101 = SAMPLE11 conversion result EADC_AD1DAT1 is selected to be compared.
<> 144:ef7eb2e8f9f7 8789 * | | |110 = SAMPLE12 conversion result EADC_AD1DAT2 is selected to be compared.
<> 144:ef7eb2e8f9f7 8790 * | | |111 = SAMPLE13 conversion result EADC_AD1DAT3 is selected to be compared.
<> 144:ef7eb2e8f9f7 8791 * |[8:11] |CMPMCNT |Compare Match Count
<> 144:ef7eb2e8f9f7 8792 * | | |When the specified A/D SAMPLE analog conversion result matches the compare condition defined by CMPCOND (EADC_CMPx[2]), the internal match counter will increase 1.
<> 144:ef7eb2e8f9f7 8793 * | | |When the internal counter reaches the value to CMPMCNT (EADC_CMPx[11:8] + 1, the ADCMPF (EADC_STATUS1 [7:6]) bit will be set.
<> 144:ef7eb2e8f9f7 8794 * |[16:27] |CMPDAT |Compared Data
<> 144:ef7eb2e8f9f7 8795 * | | |The 12 bits data is used to compare with conversion result of specified SAMPLE.
<> 144:ef7eb2e8f9f7 8796 * | | |Software can use it to monitor the external analog input pin voltage transition without imposing a load on software.
<> 144:ef7eb2e8f9f7 8797 */
<> 144:ef7eb2e8f9f7 8798 __IO uint32_t CMP[2];
<> 144:ef7eb2e8f9f7 8799
<> 144:ef7eb2e8f9f7 8800 /**
<> 144:ef7eb2e8f9f7 8801 * STATUS0
<> 144:ef7eb2e8f9f7 8802 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8803 * Offset: 0xB0 A/D Status Register 0
<> 144:ef7eb2e8f9f7 8804 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8805 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8806 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8807 * |[0:7] |VALID7_0 |ADDR07~ ADDR00 Data Valid Flag (Read Only)
<> 144:ef7eb2e8f9f7 8808 * | | |It is a mirror of VALID bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.
<> 144:ef7eb2e8f9f7 8809 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 8810 * |[8:15] |VALID15_8 |ADDR17~ ADDR10 Data Valid Flag (Read Only)
<> 144:ef7eb2e8f9f7 8811 * | | |It is a mirror of VALID bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.
<> 144:ef7eb2e8f9f7 8812 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 8813 * |[16:23] |OV7_0 |ADDR07~ ADDR00 Overrun Flag (Read Only)
<> 144:ef7eb2e8f9f7 8814 * | | |It is a mirror to OV bit in SAMPLE0 A/D result data register EADC_AD0DAT0x.
<> 144:ef7eb2e8f9f7 8815 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 8816 * |[24:31] |OV15_8 |ADDR17~ADDR10 Overrun Flag (Read Only)
<> 144:ef7eb2e8f9f7 8817 * | | |It is a mirror to OV bit in SAMPLE1 A/D result data register EADC_AD0DAT1x.
<> 144:ef7eb2e8f9f7 8818 * | | |Note: x = 0~7.
<> 144:ef7eb2e8f9f7 8819 */
<> 144:ef7eb2e8f9f7 8820 __I uint32_t STATUS0;
<> 144:ef7eb2e8f9f7 8821
<> 144:ef7eb2e8f9f7 8822 /**
<> 144:ef7eb2e8f9f7 8823 * STATUS1
<> 144:ef7eb2e8f9f7 8824 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8825 * Offset: 0xB4 A/D Status Register 1
<> 144:ef7eb2e8f9f7 8826 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8827 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8828 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8829 * |[0] |ADIF0 |A/D ADINT0 Interrupt Flag
<> 144:ef7eb2e8f9f7 8830 * | | |0 = No ADINT0 interrupt pulse received.
<> 144:ef7eb2e8f9f7 8831 * | | |1 = ADINT0 interrupt pulse has been received.
<> 144:ef7eb2e8f9f7 8832 * | | |Note1: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 8833 * | | |Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
<> 144:ef7eb2e8f9f7 8834 * |[1] |ADIF1 |A/D ADINT1 Interrupt Flag
<> 144:ef7eb2e8f9f7 8835 * | | |0 = No ADINT1 interrupt pulse received.
<> 144:ef7eb2e8f9f7 8836 * | | |1 = ADINT1 interrupt pulse has been received.
<> 144:ef7eb2e8f9f7 8837 * | | |Note1: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 8838 * | | |Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
<> 144:ef7eb2e8f9f7 8839 * |[2] |ADIF2 |A/D ADINT2 Interrupt Flag
<> 144:ef7eb2e8f9f7 8840 * | | |0 = no ADINT2 interrupt pulse received.
<> 144:ef7eb2e8f9f7 8841 * | | |1 = ADINT2 interrupt pulse has been received.
<> 144:ef7eb2e8f9f7 8842 * | | |Note1: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 8843 * | | |Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
<> 144:ef7eb2e8f9f7 8844 * |[3] |ADIF3 |A/D ADINT3 Interrupt Flag
<> 144:ef7eb2e8f9f7 8845 * | | |0 = No ADINT3 interrupt pulse received.
<> 144:ef7eb2e8f9f7 8846 * | | |1 = ADINT3 interrupt pulse has been received.
<> 144:ef7eb2e8f9f7 8847 * | | |Note1: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 8848 * | | |Note2:This bit indicates whether an A/D conversion of specific SAMPLE has been completed
<> 144:ef7eb2e8f9f7 8849 * |[4] |ADCMPO0 |ADC Compare 0 Output Status
<> 144:ef7eb2e8f9f7 8850 * | | |The 12 bits compare0 data CMPDAT EADC_CMP0 [27:16]) is used to compare with conversion result of specified SAMPLE.
<> 144:ef7eb2e8f9f7 8851 * | | |Software can use it to monitor the external analog input pin voltage status.
<> 144:ef7eb2e8f9f7 8852 * | | |0 = Conversion result in ADDR less than CMPDAT (EADC_CMP0 [27:16]) setting.
<> 144:ef7eb2e8f9f7 8853 * | | |1 = Conversion result in ADDR great than or equal CMPDAT (EADC_CMP0 [27:16]) setting.
<> 144:ef7eb2e8f9f7 8854 * |[5] |ADCMPO1 |ADC Compare 1 Output Status
<> 144:ef7eb2e8f9f7 8855 * | | |The 12 bits compare1 data CMPDAT (EADC_CMP1 [27:16]) is used to compare with conversion result of specified SAMPLE.
<> 144:ef7eb2e8f9f7 8856 * | | |Software can use it to monitor the external analog input pin voltage status.
<> 144:ef7eb2e8f9f7 8857 * | | |0 = Conversion result in ADDR less than CMPDAT EADC_CMP1 [27:16]) setting.
<> 144:ef7eb2e8f9f7 8858 * | | |1 = Conversion result in ADDR great than or equal CMPDAT (EADC_CMP1 [27:16]) setting.
<> 144:ef7eb2e8f9f7 8859 * |[6] |ADCMPF0 |ADC Compare 0 Flag
<> 144:ef7eb2e8f9f7 8860 * | | |When the specific SAMPLE A/D conversion result meets setting condition in EADC_CMP0 then this bit is set to 1.
<> 144:ef7eb2e8f9f7 8861 * | | |0 = Conversion result in ADDR does not meet EADC_CMP0 setting.
<> 144:ef7eb2e8f9f7 8862 * | | |1 = Conversion result in ADDR meets EADC_CMP0 setting.
<> 144:ef7eb2e8f9f7 8863 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 8864 * |[7] |ADCMPF1 |ADC Compare 1 Flag
<> 144:ef7eb2e8f9f7 8865 * | | |When the specific SAMPLE A/D conversion result meets setting condition in EADC_CMP1 then this bit is set to 1.
<> 144:ef7eb2e8f9f7 8866 * | | |0 = Conversion result in ADDR does not meet EADC_CMP1 setting.
<> 144:ef7eb2e8f9f7 8867 * | | |1 = Conversion result in ADDR meets EADC_CMP1 setting.
<> 144:ef7eb2e8f9f7 8868 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 8869 * |[8] |BUSY0 |Busy/Idle (Read Only)
<> 144:ef7eb2e8f9f7 8870 * | | |0 = A/D converter 0 (ADC0) is in idle state.
<> 144:ef7eb2e8f9f7 8871 * | | |1 = A/D converter 0 (ADC0) is doing conversion.
<> 144:ef7eb2e8f9f7 8872 * |[12:15] |CHANNEL0 |Current Conversion Channel (Read Only)
<> 144:ef7eb2e8f9f7 8873 * | | |This filed reflects ADC0 current conversion channel when BUSY0 (EADC_STATUS1 [8]) = 1.
<> 144:ef7eb2e8f9f7 8874 * | | |When BUSY0 (EADC_STATUS1 [8]) = 0, it shows the last converted channel.
<> 144:ef7eb2e8f9f7 8875 * | | |0000 = ADC0_CH0.
<> 144:ef7eb2e8f9f7 8876 * | | |0001 = ADC0_CH1.
<> 144:ef7eb2e8f9f7 8877 * | | |0010 = ADC0_CH2.
<> 144:ef7eb2e8f9f7 8878 * | | |0011 = ADC0_CH3.
<> 144:ef7eb2e8f9f7 8879 * | | |0100 = ADC0_CH4.
<> 144:ef7eb2e8f9f7 8880 * | | |0100 = ADC0_CH5.
<> 144:ef7eb2e8f9f7 8881 * | | |0110 = ADC0_CH6.
<> 144:ef7eb2e8f9f7 8882 * | | |0111 = ADC0_CH7.
<> 144:ef7eb2e8f9f7 8883 * | | |1000 = VBG.
<> 144:ef7eb2e8f9f7 8884 * | | |1001 = VTEMP.
<> 144:ef7eb2e8f9f7 8885 * | | |1010 = AVSS.
<> 144:ef7eb2e8f9f7 8886 * | | |1011 = OPA0_O.
<> 144:ef7eb2e8f9f7 8887 * | | |Other = reserved.
<> 144:ef7eb2e8f9f7 8888 * |[16] |BUSY1 |Busy/Idle
<> 144:ef7eb2e8f9f7 8889 * | | |0 = A/D converter 1 (ADC1) is in idle state.
<> 144:ef7eb2e8f9f7 8890 * | | |1 = A/D converter 1 (ADC1) is doing conversion.
<> 144:ef7eb2e8f9f7 8891 * |[20:23] |CHANNEL1 |Current Conversion Channel (Read Only)
<> 144:ef7eb2e8f9f7 8892 * | | |This filed reflects ADC1 current conversion channel when BUSY1 (EADC_STATUS1 [16]) = 1.
<> 144:ef7eb2e8f9f7 8893 * | | |When BUSY1 (EADC_STATUS1 [16]) = 0, it shows the last converted channel.
<> 144:ef7eb2e8f9f7 8894 * | | |0000 = ADC1_CH0.
<> 144:ef7eb2e8f9f7 8895 * | | |0001 = ADC1_CH1.
<> 144:ef7eb2e8f9f7 8896 * | | |0010 = ADC1_CH2.
<> 144:ef7eb2e8f9f7 8897 * | | |0011 = ADC1_CH3.
<> 144:ef7eb2e8f9f7 8898 * | | |0100 = ADC1_CH4.
<> 144:ef7eb2e8f9f7 8899 * | | |0101 = ADC1_CH5.
<> 144:ef7eb2e8f9f7 8900 * | | |0110 = ADC1_CH6.
<> 144:ef7eb2e8f9f7 8901 * | | |0111 = ADC1_CH7.
<> 144:ef7eb2e8f9f7 8902 * | | |1000 = OPA1_O.
<> 144:ef7eb2e8f9f7 8903 * | | |Other = reversed.
<> 144:ef7eb2e8f9f7 8904 * |[24] |ADOVIF |All A/D Interrupt Flag Overrun Bits Check
<> 144:ef7eb2e8f9f7 8905 * | | |0 = None of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1.
<> 144:ef7eb2e8f9f7 8906 * | | |1 = Any one of ADINT interrupt flag ADFOVx (ADIFOVR [15:0]) is overwritten to 1.
<> 144:ef7eb2e8f9f7 8907 * | | |Note: This bit will keep 1 when any ADFOVx (ADIFOVR [15:0]) Flag is equal to 1.
<> 144:ef7eb2e8f9f7 8908 * |[25] |STOVF |For All A/D SAMPLE Start Of Conversion Overrun Flags Check
<> 144:ef7eb2e8f9f7 8909 * | | |0 = None of SAMPLE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1.
<> 144:ef7eb2e8f9f7 8910 * | | |1 = Any one of SAMPLE event overrun flag SPOVFx (ADSPOVFR [15:0]) is set to 1.
<> 144:ef7eb2e8f9f7 8911 * | | |Note: This bit will keep 1 when any SPOVFx (ADSPOVFR [15:0]) Flag is equal to 1.
<> 144:ef7eb2e8f9f7 8912 * |[26] |AVALID |For All SAMPLE A/D Result Data Register ADDR Data Valid Flag Check
<> 144:ef7eb2e8f9f7 8913 * | | |0 = None of SAMPLE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1.
<> 144:ef7eb2e8f9f7 8914 * | | |1 = Any one of SAMPLE data register valid flag VALIDx (EADC_ADnDATx[17]) is set to 1.
<> 144:ef7eb2e8f9f7 8915 * | | |Note: This bit will keep 1 when any VALIDx (EADC_ADnDATx[17]) Flag is equal to 1.
<> 144:ef7eb2e8f9f7 8916 * |[27] |AOV |For All SAMPLE A/D Result Data Register Overrun Flags Check
<> 144:ef7eb2e8f9f7 8917 * | | |0 = None of SAMPLE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 8918 * | | |1 = Any one of SAMPLE data register overrun flag OVx (EADC_ADnDATx[16]) is set to 1.
<> 144:ef7eb2e8f9f7 8919 * | | |Note: This bit will keep 1 when any OVx (EADC_ADnDATx[16]) Flag is equal to 1.
<> 144:ef7eb2e8f9f7 8920 */
<> 144:ef7eb2e8f9f7 8921 __IO uint32_t STATUS1;
<> 144:ef7eb2e8f9f7 8922
<> 144:ef7eb2e8f9f7 8923 /**
<> 144:ef7eb2e8f9f7 8924 * EXTSMPT
<> 144:ef7eb2e8f9f7 8925 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8926 * Offset: 0xB8 A/D Timing Control Register
<> 144:ef7eb2e8f9f7 8927 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8928 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8929 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8930 * |[0:7] |EXTSMPT0 |ADC0 Extend Sampling Time
<> 144:ef7eb2e8f9f7 8931 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
<> 144:ef7eb2e8f9f7 8932 * | | |The range of start delay time is from 0~255 ADC clock.
<> 144:ef7eb2e8f9f7 8933 * |[16:23] |EXTSMPT1 |ADC1 Extend Sampling Time
<> 144:ef7eb2e8f9f7 8934 * | | |When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, SW can extend A/D sampling time after trigger source is coming to get enough sampling time.
<> 144:ef7eb2e8f9f7 8935 * | | |The range of start delay time is from 0~255 ADC clock.
<> 144:ef7eb2e8f9f7 8936 */
<> 144:ef7eb2e8f9f7 8937 __IO uint32_t EXTSMPT;
<> 144:ef7eb2e8f9f7 8938 uint32_t RESERVE2[17];
<> 144:ef7eb2e8f9f7 8939
<> 144:ef7eb2e8f9f7 8940
<> 144:ef7eb2e8f9f7 8941 /**
<> 144:ef7eb2e8f9f7 8942 * AD0DDAT0
<> 144:ef7eb2e8f9f7 8943 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8944 * Offset: 0x100 A/D double Data Register 0 for SAMPLE00
<> 144:ef7eb2e8f9f7 8945 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8946 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8947 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8948 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 8949 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 8950 * |[16] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 8951 * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 8952 * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
<> 144:ef7eb2e8f9f7 8953 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 8954 */
<> 144:ef7eb2e8f9f7 8955 __I uint32_t AD0DDAT0;
<> 144:ef7eb2e8f9f7 8956
<> 144:ef7eb2e8f9f7 8957 /**
<> 144:ef7eb2e8f9f7 8958 * AD0DDAT1
<> 144:ef7eb2e8f9f7 8959 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8960 * Offset: 0x104 A/D double Data Register 1 for SAMPLE01
<> 144:ef7eb2e8f9f7 8961 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8962 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8963 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8964 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 8965 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 8966 * |[16] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 8967 * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 8968 * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
<> 144:ef7eb2e8f9f7 8969 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 8970 */
<> 144:ef7eb2e8f9f7 8971 __I uint32_t AD0DDAT1;
<> 144:ef7eb2e8f9f7 8972
<> 144:ef7eb2e8f9f7 8973 /**
<> 144:ef7eb2e8f9f7 8974 * AD0DDAT2
<> 144:ef7eb2e8f9f7 8975 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8976 * Offset: 0x108 A/D double Data Register 2 for SAMPLE02
<> 144:ef7eb2e8f9f7 8977 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8978 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8979 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8980 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 8981 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 8982 * |[16] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 8983 * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 8984 * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
<> 144:ef7eb2e8f9f7 8985 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 8986 */
<> 144:ef7eb2e8f9f7 8987 __I uint32_t AD0DDAT2;
<> 144:ef7eb2e8f9f7 8988
<> 144:ef7eb2e8f9f7 8989 /**
<> 144:ef7eb2e8f9f7 8990 * AD0DDAT3
<> 144:ef7eb2e8f9f7 8991 * ===================================================================================================
<> 144:ef7eb2e8f9f7 8992 * Offset: 0x10C A/D double Data Register 3 for SAMPLE03
<> 144:ef7eb2e8f9f7 8993 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 8994 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 8995 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 8996 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 8997 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 8998 * |[16] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 8999 * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 9000 * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
<> 144:ef7eb2e8f9f7 9001 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 9002 */
<> 144:ef7eb2e8f9f7 9003 __I uint32_t AD0DDAT3;
<> 144:ef7eb2e8f9f7 9004 uint32_t RESERVE3[4];
<> 144:ef7eb2e8f9f7 9005
<> 144:ef7eb2e8f9f7 9006
<> 144:ef7eb2e8f9f7 9007 /**
<> 144:ef7eb2e8f9f7 9008 * AD1DDAT0
<> 144:ef7eb2e8f9f7 9009 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9010 * Offset: 0x120 A/D double Data Register 0 for SAMPLE10
<> 144:ef7eb2e8f9f7 9011 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9012 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9013 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9014 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 9015 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 9016 * |[16] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 9017 * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 9018 * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
<> 144:ef7eb2e8f9f7 9019 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 9020 */
<> 144:ef7eb2e8f9f7 9021 __I uint32_t AD1DDAT0;
<> 144:ef7eb2e8f9f7 9022
<> 144:ef7eb2e8f9f7 9023 /**
<> 144:ef7eb2e8f9f7 9024 * AD1DDAT1
<> 144:ef7eb2e8f9f7 9025 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9026 * Offset: 0x124 A/D double Data Register 1 for SAMPLE11
<> 144:ef7eb2e8f9f7 9027 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9028 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9029 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9030 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 9031 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 9032 * |[16] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 9033 * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 9034 * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
<> 144:ef7eb2e8f9f7 9035 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 9036 */
<> 144:ef7eb2e8f9f7 9037 __I uint32_t AD1DDAT1;
<> 144:ef7eb2e8f9f7 9038
<> 144:ef7eb2e8f9f7 9039 /**
<> 144:ef7eb2e8f9f7 9040 * AD1DDAT2
<> 144:ef7eb2e8f9f7 9041 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9042 * Offset: 0x128 A/D double Data Register 2 for SAMPLE12
<> 144:ef7eb2e8f9f7 9043 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9044 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9045 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9046 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 9047 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 9048 * |[16] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 9049 * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 9050 * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
<> 144:ef7eb2e8f9f7 9051 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 9052 */
<> 144:ef7eb2e8f9f7 9053 __I uint32_t AD1DDAT2;
<> 144:ef7eb2e8f9f7 9054
<> 144:ef7eb2e8f9f7 9055 /**
<> 144:ef7eb2e8f9f7 9056 * AD1DDAT3
<> 144:ef7eb2e8f9f7 9057 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9058 * Offset: 0x12C A/D double Data Register 3 for SAMPLE13
<> 144:ef7eb2e8f9f7 9059 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9060 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9061 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9062 * |[0:11] |RESULT |A/D Conversion Result
<> 144:ef7eb2e8f9f7 9063 * | | |This field contains 12 bits conversion result.
<> 144:ef7eb2e8f9f7 9064 * |[16] |VALID |Valid Flag
<> 144:ef7eb2e8f9f7 9065 * | | |0 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is not valid.
<> 144:ef7eb2e8f9f7 9066 * | | |1 = Double buffer data in RESULT (EADC_ADnDATx[11:0]) bits is valid.
<> 144:ef7eb2e8f9f7 9067 * | | |This bit is set to 1 when corresponding SAMPLE channel analog input conversion is completed and cleared by hardware after EADC_ADnDATx register is read.
<> 144:ef7eb2e8f9f7 9068 */
<> 144:ef7eb2e8f9f7 9069 __I uint32_t AD1DDAT3;
<> 144:ef7eb2e8f9f7 9070
<> 144:ef7eb2e8f9f7 9071 /**
<> 144:ef7eb2e8f9f7 9072 * DBMEN
<> 144:ef7eb2e8f9f7 9073 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9074 * Offset: 0x130 A/D Double Buffer Mode select
<> 144:ef7eb2e8f9f7 9075 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9076 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9077 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9078 * |[0] |AD0DBM0 |Double Buffer Mode For SAMPLE00
<> 144:ef7eb2e8f9f7 9079 * | | |0 = SAMPLE00 has one sample result register. (default).
<> 144:ef7eb2e8f9f7 9080 * | | |1 =SAMPLE00 has two sample result registers.
<> 144:ef7eb2e8f9f7 9081 * |[1] |AD0DBM1 |Double Buffer Mode For SAMPLE01
<> 144:ef7eb2e8f9f7 9082 * | | |0 = SAMPLE01 has one sample result register. (default).
<> 144:ef7eb2e8f9f7 9083 * | | |1 = SAMPLE01 has two sample result registers.
<> 144:ef7eb2e8f9f7 9084 * |[2] |AD0DBM2 |Double Buffer Mode For SAMPLE02
<> 144:ef7eb2e8f9f7 9085 * | | |0 = SAMPLE02 has one sample result register. (default).
<> 144:ef7eb2e8f9f7 9086 * | | |1 =SAMPLE02 has two sample result registers.
<> 144:ef7eb2e8f9f7 9087 * |[3] |AD0DBM3 |Double Buffer Mode For SAMPLE03
<> 144:ef7eb2e8f9f7 9088 * | | |0 = SAMPLE03 has one sample result register. (default).
<> 144:ef7eb2e8f9f7 9089 * | | |1 =SAMPLE03 has two sample result registers.
<> 144:ef7eb2e8f9f7 9090 * |[8] |AD1DBM0 |Double Buffer Mode For SAMPLE10
<> 144:ef7eb2e8f9f7 9091 * | | |0 = SAMPLE10 has one sample result register. (default)
<> 144:ef7eb2e8f9f7 9092 * | | |1 =SAMPLE10 has two sample result registers.
<> 144:ef7eb2e8f9f7 9093 * |[9] |AD1DBM1 |Double Buffer Mode For SAMPLE11
<> 144:ef7eb2e8f9f7 9094 * | | |0 = SAMPLE11 has one sample result register. (default).
<> 144:ef7eb2e8f9f7 9095 * | | |1 =SAMPLE11 has two sample result registers.
<> 144:ef7eb2e8f9f7 9096 * |[10] |AD1DBM2 |Double Buffer Mode For SAMPLE12
<> 144:ef7eb2e8f9f7 9097 * | | |0 = SAMPLE12 has one sample result register. (default).
<> 144:ef7eb2e8f9f7 9098 * | | |1 =SAMPLE12 has two sample result registers.
<> 144:ef7eb2e8f9f7 9099 * |[11] |AD1DBM3 |Double Buffer Mode For SAMPLE13
<> 144:ef7eb2e8f9f7 9100 * | | |0 = SAMPLE13 has one sample result register. (default)
<> 144:ef7eb2e8f9f7 9101 * | | |1 =SAMPLE13 has two sample result registers.
<> 144:ef7eb2e8f9f7 9102 */
<> 144:ef7eb2e8f9f7 9103 __IO uint32_t DBMEN;
<> 144:ef7eb2e8f9f7 9104
<> 144:ef7eb2e8f9f7 9105 /**
<> 144:ef7eb2e8f9f7 9106 * INTSRC0
<> 144:ef7eb2e8f9f7 9107 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9108 * Offset: 0x134 A/D Interrupt 0 Source Enable Control Register
<> 144:ef7eb2e8f9f7 9109 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9110 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9111 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9112 * |[0] |AD0SPIE0 |SAMPLE00 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9113 * | | |0 = SAMPLE00 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9114 * | | |1 = SAMPLE00 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9115 * |[1] |AD0SPIE1 |SAMPLE01 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9116 * | | |0 = SAMPLE01 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9117 * | | |1 = SAMPLE01 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9118 * |[2] |AD0SPIE2 |SAMPLE02 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9119 * | | |0 = SAMPLE02 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9120 * | | |1 = SAMPLE02 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9121 * |[3] |AD0SPIE3 |SAMPLE03 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9122 * | | |0 = SAMPLE03 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9123 * | | |1 = SAMPLE03 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9124 * |[4] |AD0SPIE4 |SAMPLE04 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9125 * | | |0 = SAMPLE04 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9126 * | | |1 = SAMPLE04 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9127 * |[5] |AD0SPIE5 |SAMPLE05 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9128 * | | |0 = SAMPLE05 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9129 * | | |1 = SAMPLE05 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9130 * |[6] |AD0SPIE6 |SAMPLE06 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9131 * | | |0 = SAMPLE06 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9132 * | | |1 = SAMPLE06 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9133 * |[7] |AD0SPIE7 |SAMPLE07 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9134 * | | |0 = SAMPLE07 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9135 * | | |1 = SAMPLE07 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9136 * |[8] |AD1SPIE0 |SAMPLE10 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9137 * | | |0 = SAMPLE10 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9138 * | | |1 = SAMPLE10 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9139 * |[9] |AD1SPIE1 |SAMPLE11 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9140 * | | |0 = SAMPLE11 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9141 * | | |1 = SAMPLE11 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9142 * |[10] |AD1SPIE2 |SAMPLE12 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9143 * | | |0 = SAMPLE12 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9144 * | | |1 = SAMPLE12 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9145 * |[11] |AD1SPIE3 |SAMPLE13 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9146 * | | |0 = SAMPLE13 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9147 * | | |1 = SAMPLE13 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9148 * |[12] |AD1SPIE4 |SAMPLE14 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9149 * | | |0 = SAMPLE14 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9150 * | | |1 = SAMPLE14 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9151 * |[13] |AD1SPIE5 |SAMPLE15 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9152 * | | |0 = SAMPLE15 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9153 * | | |1 = SAMPLE15 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9154 * |[14] |AD1SPIE6 |SAMPLE16 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9155 * | | |0 = SAMPLE16 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9156 * | | |1 = SAMPLE16 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9157 * |[15] |AD1SPIE7 |SAMPLE17 Interrupt Mask Enable Control
<> 144:ef7eb2e8f9f7 9158 * | | |0 = SAMPLE17 interrupt mask Disabled.
<> 144:ef7eb2e8f9f7 9159 * | | |1 = SAMPLE17 interrupt mask Enabled.
<> 144:ef7eb2e8f9f7 9160 */
<> 144:ef7eb2e8f9f7 9161 __IO uint32_t INTSRC[4];
<> 144:ef7eb2e8f9f7 9162
<> 144:ef7eb2e8f9f7 9163 /**
<> 144:ef7eb2e8f9f7 9164 * AD0TRGEN0
<> 144:ef7eb2e8f9f7 9165 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9166 * Offset: 0x144 A/D trigger condition for SAMPLE00
<> 144:ef7eb2e8f9f7 9167 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9168 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9169 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9170 * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9171 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9172 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9173 * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9174 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9175 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9176 * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9177 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9178 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9179 * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9180 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9181 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9182 * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9183 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9184 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9185 * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9186 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9187 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9188 * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9189 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9190 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9191 * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9192 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9193 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9194 * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9195 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9196 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9197 * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9198 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9199 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9200 * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9201 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9202 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9203 * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9204 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9205 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9206 * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9207 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9208 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9209 * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9210 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9211 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9212 * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9213 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9214 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9215 * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9216 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9217 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9218 * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9219 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9220 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9221 * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9222 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9223 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9224 * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9225 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9226 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9227 * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9228 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9229 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9230 * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9231 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9232 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9233 * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9234 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9235 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9236 * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9237 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9238 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9239 * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9240 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9241 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9242 * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9243 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9244 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9245 * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9246 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9247 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9248 * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9249 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9250 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9251 * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9252 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9253 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9254 * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9255 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9256 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9257 * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9258 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9259 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9260 * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9261 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9262 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9263 * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9264 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9265 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9266 */
<> 144:ef7eb2e8f9f7 9267 __IO uint32_t AD0TRGEN0;
<> 144:ef7eb2e8f9f7 9268
<> 144:ef7eb2e8f9f7 9269 /**
<> 144:ef7eb2e8f9f7 9270 * AD0TRGEN1
<> 144:ef7eb2e8f9f7 9271 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9272 * Offset: 0x148 A/D trigger condition for SAMPLE01
<> 144:ef7eb2e8f9f7 9273 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9274 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9275 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9276 * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9277 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9278 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9279 * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9280 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9281 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9282 * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9283 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9284 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9285 * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9286 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9287 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9288 * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9289 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9290 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9291 * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9292 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9293 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9294 * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9295 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9296 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9297 * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9298 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9299 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9300 * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9301 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9302 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9303 * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9304 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9305 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9306 * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9307 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9308 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9309 * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9310 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9311 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9312 * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9313 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9314 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9315 * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9316 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9317 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9318 * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9319 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9320 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9321 * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9322 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9323 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9324 * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9325 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9326 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9327 * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9328 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9329 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9330 * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9331 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9332 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9333 * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9334 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9335 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9336 * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9337 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9338 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9339 * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9340 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9341 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9342 * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9343 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9344 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9345 * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9346 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9347 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9348 * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9349 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9350 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9351 * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9352 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9353 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9354 * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9355 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9356 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9357 * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9358 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9359 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9360 * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9361 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9362 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9363 * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9364 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9365 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9366 * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9367 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9368 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9369 * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9370 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9371 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9372 */
<> 144:ef7eb2e8f9f7 9373 __IO uint32_t AD0TRGEN1;
<> 144:ef7eb2e8f9f7 9374
<> 144:ef7eb2e8f9f7 9375 /**
<> 144:ef7eb2e8f9f7 9376 * AD0TRGEN2
<> 144:ef7eb2e8f9f7 9377 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9378 * Offset: 0x14C A/D trigger condition for SAMPLE02
<> 144:ef7eb2e8f9f7 9379 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9380 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9381 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9382 * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9383 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9384 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9385 * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9386 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9387 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9388 * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9389 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9390 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9391 * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9392 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9393 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9394 * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9395 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9396 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9397 * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9398 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9399 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9400 * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9401 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9402 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9403 * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9404 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9405 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9406 * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9407 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9408 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9409 * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9410 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9411 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9412 * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9413 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9414 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9415 * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9416 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9417 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9418 * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9419 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9420 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9421 * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9422 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9423 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9424 * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9425 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9426 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9427 * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9428 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9429 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9430 * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9431 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9432 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9433 * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9434 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9435 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9436 * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9437 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9438 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9439 * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9440 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9441 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9442 * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9443 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9444 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9445 * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9446 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9447 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9448 * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9449 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9450 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9451 * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9452 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9453 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9454 * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9455 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9456 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9457 * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9458 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9459 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9460 * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9461 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9462 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9463 * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9464 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9465 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9466 * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9467 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9468 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9469 * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9470 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9471 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9472 * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9473 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9474 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9475 * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9476 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9477 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9478 */
<> 144:ef7eb2e8f9f7 9479 __IO uint32_t AD0TRGEN2;
<> 144:ef7eb2e8f9f7 9480
<> 144:ef7eb2e8f9f7 9481 /**
<> 144:ef7eb2e8f9f7 9482 * AD0TRGEN3
<> 144:ef7eb2e8f9f7 9483 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9484 * Offset: 0x150 A/D trigger condition for SAMPLE03
<> 144:ef7eb2e8f9f7 9485 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9486 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9487 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9488 * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9489 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9490 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9491 * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9492 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9493 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9494 * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9495 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9496 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9497 * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9498 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9499 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9500 * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9501 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9502 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9503 * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9504 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9505 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9506 * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9507 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9508 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9509 * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9510 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9511 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9512 * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9513 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9514 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9515 * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9516 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9517 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9518 * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9519 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9520 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9521 * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9522 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9523 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9524 * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9525 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9526 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9527 * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9528 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9529 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9530 * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9531 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9532 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9533 * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9534 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9535 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9536 * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9537 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9538 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9539 * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9540 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9541 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9542 * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9543 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9544 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9545 * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9546 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9547 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9548 * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9549 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9550 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9551 * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9552 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9553 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9554 * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9555 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9556 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9557 * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9558 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9559 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9560 * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9561 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9562 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9563 * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9564 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9565 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9566 * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9567 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9568 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9569 * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9570 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9571 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9572 * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9573 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9574 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9575 * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9576 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9577 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9578 * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9579 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9580 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9581 * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9582 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9583 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9584 */
<> 144:ef7eb2e8f9f7 9585 __IO uint32_t AD0TRGEN3;
<> 144:ef7eb2e8f9f7 9586
<> 144:ef7eb2e8f9f7 9587 /**
<> 144:ef7eb2e8f9f7 9588 * AD1TRGEN0
<> 144:ef7eb2e8f9f7 9589 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9590 * Offset: 0x154 A/D trigger condition for SAMPLE10
<> 144:ef7eb2e8f9f7 9591 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9592 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9593 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9594 * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9595 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9596 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9597 * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9598 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9599 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9600 * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9601 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9602 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9603 * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9604 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9605 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9606 * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9607 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9608 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9609 * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9610 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9611 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9612 * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9613 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9614 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9615 * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9616 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9617 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9618 * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9619 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9620 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9621 * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9622 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9623 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9624 * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9625 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9626 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9627 * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9628 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9629 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9630 * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9631 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9632 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9633 * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9634 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9635 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9636 * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9637 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9638 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9639 * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9640 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9641 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9642 * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9643 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9644 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9645 * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9646 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9647 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9648 * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9649 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9650 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9651 * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9652 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9653 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9654 * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9655 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9656 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9657 * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9658 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9659 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9660 * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9661 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9662 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9663 * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9664 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9665 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9666 * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9667 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9668 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9669 * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9670 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9671 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9672 * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9673 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9674 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9675 * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9676 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9677 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9678 * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9679 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9680 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9681 * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9682 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9683 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9684 * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9685 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9686 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9687 * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9688 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9689 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9690 */
<> 144:ef7eb2e8f9f7 9691 __IO uint32_t AD1TRGEN0;
<> 144:ef7eb2e8f9f7 9692
<> 144:ef7eb2e8f9f7 9693 /**
<> 144:ef7eb2e8f9f7 9694 * AD1TRGEN1
<> 144:ef7eb2e8f9f7 9695 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9696 * Offset: 0x158 A/D trigger condition for SAMPLE11
<> 144:ef7eb2e8f9f7 9697 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9698 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9699 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9700 * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9701 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9702 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9703 * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9704 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9705 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9706 * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9707 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9708 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9709 * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9710 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9711 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9712 * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9713 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9714 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9715 * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9716 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9717 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9718 * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9719 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9720 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9721 * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9722 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9723 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9724 * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9725 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9726 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9727 * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9728 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9729 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9730 * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9731 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9732 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9733 * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9734 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9735 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9736 * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9737 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9738 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9739 * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9740 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9741 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9742 * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9743 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9744 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9745 * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9746 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9747 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9748 * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9749 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9750 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9751 * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9752 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9753 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9754 * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9755 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9756 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9757 * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9758 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9759 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9760 * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9761 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9762 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9763 * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9764 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9765 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9766 * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9767 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9768 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9769 * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9770 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9771 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9772 * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9773 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9774 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9775 * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9776 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9777 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9778 * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9779 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9780 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9781 * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9782 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9783 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9784 * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9785 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9786 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9787 * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9788 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9789 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9790 * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9791 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9792 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9793 * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9794 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9795 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9796 */
<> 144:ef7eb2e8f9f7 9797 __IO uint32_t AD1TRGEN1;
<> 144:ef7eb2e8f9f7 9798
<> 144:ef7eb2e8f9f7 9799 /**
<> 144:ef7eb2e8f9f7 9800 * AD1TRGEN2
<> 144:ef7eb2e8f9f7 9801 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9802 * Offset: 0x15C A/D trigger condition for SAMPLE12
<> 144:ef7eb2e8f9f7 9803 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9804 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9805 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9806 * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9807 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9808 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9809 * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9810 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9811 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9812 * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9813 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9814 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9815 * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9816 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9817 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9818 * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9819 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9820 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9821 * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9822 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9823 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9824 * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9825 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9826 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9827 * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9828 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9829 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9830 * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9831 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9832 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9833 * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9834 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9835 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9836 * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9837 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9838 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9839 * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9840 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9841 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9842 * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9843 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9844 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9845 * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9846 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9847 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9848 * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9849 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9850 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9851 * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9852 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9853 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9854 * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9855 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9856 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9857 * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9858 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9859 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9860 * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9861 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9862 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9863 * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9864 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9865 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9866 * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9867 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9868 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9869 * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9870 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9871 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9872 * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9873 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9874 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9875 * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9876 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9877 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9878 * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9879 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9880 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9881 * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9882 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9883 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9884 * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9885 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9886 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9887 * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9888 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9889 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9890 * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9891 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9892 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9893 * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9894 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9895 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9896 * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9897 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9898 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9899 * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9900 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9901 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9902 */
<> 144:ef7eb2e8f9f7 9903 __IO uint32_t AD1TRGEN2;
<> 144:ef7eb2e8f9f7 9904
<> 144:ef7eb2e8f9f7 9905 /**
<> 144:ef7eb2e8f9f7 9906 * AD1TRGEN3
<> 144:ef7eb2e8f9f7 9907 * ===================================================================================================
<> 144:ef7eb2e8f9f7 9908 * Offset: 0x160 A/D trigger condition for SAMPLE13
<> 144:ef7eb2e8f9f7 9909 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 9910 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 9911 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 9912 * |[0] |EPWM00REN |EPWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9913 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9914 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9915 * |[1] |EPWM00FEN |EPWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9916 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9917 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9918 * |[2] |EPWM00PEN |EPWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9919 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9920 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9921 * |[3] |EPWM00CEN |EPWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9922 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9923 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9924 * |[4] |EPWM02REN |EPWM0_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9925 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9926 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9927 * |[5] |EPWM02FEN |EPWM0_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9928 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9929 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9930 * |[6] |EPWM02PEN |EPWM0_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9931 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9932 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9933 * |[7] |EPWM02CEN |EPWM0_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9934 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9935 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9936 * |[8] |EPWM04REN |EPWM0_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9937 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9938 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9939 * |[9] |EPWM04FEN |EPWM0_CH4 Falling Rdge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9940 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9941 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9942 * |[10] |EPWM04PEN |EPWM0_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9943 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9944 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9945 * |[11] |EPWM04CEN |EPWM0_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9946 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9947 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9948 * |[12] |EPWM10REN |EPWM1_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9949 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9950 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9951 * |[13] |EPWM10FEN |EPWM1_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9952 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9953 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9954 * |[14] |EPWM10PEN |EPWM1_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9955 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9956 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9957 * |[15] |EPWM10CEN |EPWM1_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9958 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9959 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9960 * |[16] |EPWM12REN |EPWM1_CH2 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9961 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9962 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9963 * |[17] |EPWM120FEN|EPWM1_CH2 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9964 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9965 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9966 * |[18] |EPWM12PEN |EPWM1_CH2 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9967 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9968 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9969 * |[19] |EPWM12CEN |EPWM1_CH2 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9970 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9971 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9972 * |[20] |EPWM14REN |EPWM1_CH4 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9973 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9974 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9975 * |[21] |EPWM14FEN |EPWM1_CH4 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9976 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9977 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9978 * |[22] |EPWM14PEN |EPWM1_CH4 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9979 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9980 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9981 * |[23] |EPWM14CEN |EPWM1_CH4 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9982 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9983 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9984 * |[24] |PWM00REN |PWM0_CH0 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9985 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9986 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9987 * |[25] |PWM00FEN |PWM0_CH0 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9988 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9989 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9990 * |[26] |PWM00PEN |PWM0_CH0 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 9991 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9992 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9993 * |[27] |PWM00CEN |PWM0_CH0 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 9994 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9995 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9996 * |[28] |PWM01REN |PWM0_CH1 Rising Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 9997 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 9998 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 9999 * |[29] |PWM01FEN |PWM0_CH1 Falling Edge Trigger Enable Control
<> 144:ef7eb2e8f9f7 10000 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 10001 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 10002 * |[30] |PWM01PEN |PWM0_CH1 Period Trigger Enable Control
<> 144:ef7eb2e8f9f7 10003 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 10004 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 10005 * |[31] |PWM01CEN |PWM0_CH1 Center Trigger Enable Control
<> 144:ef7eb2e8f9f7 10006 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 10007 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 10008 */
<> 144:ef7eb2e8f9f7 10009 __IO uint32_t AD1TRGEN3;
<> 144:ef7eb2e8f9f7 10010
<> 144:ef7eb2e8f9f7 10011 } EADC_T;
<> 144:ef7eb2e8f9f7 10012
<> 144:ef7eb2e8f9f7 10013 /**
<> 144:ef7eb2e8f9f7 10014 @addtogroup EADC_CONST EADC Bit Field Definition
<> 144:ef7eb2e8f9f7 10015 Constant Definitions for EADC Controller
<> 144:ef7eb2e8f9f7 10016 @{ */
<> 144:ef7eb2e8f9f7 10017
<> 144:ef7eb2e8f9f7 10018 #define EADC_AD0DAT0_RESULT_Pos (0) /*!< EADC AD0DAT0: RESULT Position */
<> 144:ef7eb2e8f9f7 10019 #define EADC_AD0DAT0_RESULT_Msk (0xffful << EADC_AD0DAT0_RESULT_Pos) /*!< EADC AD0DAT0: RESULT Mask */
<> 144:ef7eb2e8f9f7 10020
<> 144:ef7eb2e8f9f7 10021 #define EADC_AD0DAT0_OV_Pos (16) /*!< EADC AD0DAT0: OV Position */
<> 144:ef7eb2e8f9f7 10022 #define EADC_AD0DAT0_OV_Msk (0x1ul << EADC_AD0DAT0_OV_Pos) /*!< EADC AD0DAT0: OV Mask */
<> 144:ef7eb2e8f9f7 10023
<> 144:ef7eb2e8f9f7 10024 #define EADC_AD0DAT0_VALID_Pos (17) /*!< EADC AD0DAT0: VALID Position */
<> 144:ef7eb2e8f9f7 10025 #define EADC_AD0DAT0_VALID_Msk (0x1ul << EADC_AD0DAT0_VALID_Pos) /*!< EADC AD0DAT0: VALID Mask */
<> 144:ef7eb2e8f9f7 10026
<> 144:ef7eb2e8f9f7 10027 #define EADC_AD0DAT1_RESULT_Pos (0) /*!< EADC AD0DAT1: RESULT Position */
<> 144:ef7eb2e8f9f7 10028 #define EADC_AD0DAT1_RESULT_Msk (0xffful << EADC_AD0DAT1_RESULT_Pos) /*!< EADC AD0DAT1: RESULT Mask */
<> 144:ef7eb2e8f9f7 10029
<> 144:ef7eb2e8f9f7 10030 #define EADC_AD0DAT1_OV_Pos (16) /*!< EADC AD0DAT1: OV Position */
<> 144:ef7eb2e8f9f7 10031 #define EADC_AD0DAT1_OV_Msk (0x1ul << EADC_AD0DAT1_OV_Pos) /*!< EADC AD0DAT1: OV Mask */
<> 144:ef7eb2e8f9f7 10032
<> 144:ef7eb2e8f9f7 10033 #define EADC_AD0DAT1_VALID_Pos (17) /*!< EADC AD0DAT1: VALID Position */
<> 144:ef7eb2e8f9f7 10034 #define EADC_AD0DAT1_VALID_Msk (0x1ul << EADC_AD0DAT1_VALID_Pos) /*!< EADC AD0DAT1: VALID Mask */
<> 144:ef7eb2e8f9f7 10035
<> 144:ef7eb2e8f9f7 10036 #define EADC_AD0DAT2_RESULT_Pos (0) /*!< EADC AD0DAT2: RESULT Position */
<> 144:ef7eb2e8f9f7 10037 #define EADC_AD0DAT2_RESULT_Msk (0xffful << EADC_AD0DAT2_RESULT_Pos) /*!< EADC AD0DAT2: RESULT Mask */
<> 144:ef7eb2e8f9f7 10038
<> 144:ef7eb2e8f9f7 10039 #define EADC_AD0DAT2_OV_Pos (16) /*!< EADC AD0DAT2: OV Position */
<> 144:ef7eb2e8f9f7 10040 #define EADC_AD0DAT2_OV_Msk (0x1ul << EADC_AD0DAT2_OV_Pos) /*!< EADC AD0DAT2: OV Mask */
<> 144:ef7eb2e8f9f7 10041
<> 144:ef7eb2e8f9f7 10042 #define EADC_AD0DAT2_VALID_Pos (17) /*!< EADC AD0DAT2: VALID Position */
<> 144:ef7eb2e8f9f7 10043 #define EADC_AD0DAT2_VALID_Msk (0x1ul << EADC_AD0DAT2_VALID_Pos) /*!< EADC AD0DAT2: VALID Mask */
<> 144:ef7eb2e8f9f7 10044
<> 144:ef7eb2e8f9f7 10045 #define EADC_AD0DAT3_RESULT_Pos (0) /*!< EADC AD0DAT3: RESULT Position */
<> 144:ef7eb2e8f9f7 10046 #define EADC_AD0DAT3_RESULT_Msk (0xffful << EADC_AD0DAT3_RESULT_Pos) /*!< EADC AD0DAT3: RESULT Mask */
<> 144:ef7eb2e8f9f7 10047
<> 144:ef7eb2e8f9f7 10048 #define EADC_AD0DAT3_OV_Pos (16) /*!< EADC AD0DAT3: OV Position */
<> 144:ef7eb2e8f9f7 10049 #define EADC_AD0DAT3_OV_Msk (0x1ul << EADC_AD0DAT3_OV_Pos) /*!< EADC AD0DAT3: OV Mask */
<> 144:ef7eb2e8f9f7 10050
<> 144:ef7eb2e8f9f7 10051 #define EADC_AD0DAT3_VALID_Pos (17) /*!< EADC AD0DAT3: VALID Position */
<> 144:ef7eb2e8f9f7 10052 #define EADC_AD0DAT3_VALID_Msk (0x1ul << EADC_AD0DAT3_VALID_Pos) /*!< EADC AD0DAT3: VALID Mask */
<> 144:ef7eb2e8f9f7 10053
<> 144:ef7eb2e8f9f7 10054 #define EADC_AD0DAT4_RESULT_Pos (0) /*!< EADC AD0DAT4: RESULT Position */
<> 144:ef7eb2e8f9f7 10055 #define EADC_AD0DAT4_RESULT_Msk (0xffful << EADC_AD0DAT4_RESULT_Pos) /*!< EADC AD0DAT4: RESULT Mask */
<> 144:ef7eb2e8f9f7 10056
<> 144:ef7eb2e8f9f7 10057 #define EADC_AD0DAT4_OV_Pos (16) /*!< EADC AD0DAT4: OV Position */
<> 144:ef7eb2e8f9f7 10058 #define EADC_AD0DAT4_OV_Msk (0x1ul << EADC_AD0DAT4_OV_Pos) /*!< EADC AD0DAT4: OV Mask */
<> 144:ef7eb2e8f9f7 10059
<> 144:ef7eb2e8f9f7 10060 #define EADC_AD0DAT4_VALID_Pos (17) /*!< EADC AD0DAT4: VALID Position */
<> 144:ef7eb2e8f9f7 10061 #define EADC_AD0DAT4_VALID_Msk (0x1ul << EADC_AD0DAT4_VALID_Pos) /*!< EADC AD0DAT4: VALID Mask */
<> 144:ef7eb2e8f9f7 10062
<> 144:ef7eb2e8f9f7 10063 #define EADC_AD0DAT5_RESULT_Pos (0) /*!< EADC AD0DAT5: RESULT Position */
<> 144:ef7eb2e8f9f7 10064 #define EADC_AD0DAT5_RESULT_Msk (0xffful << EADC_AD0DAT5_RESULT_Pos) /*!< EADC AD0DAT5: RESULT Mask */
<> 144:ef7eb2e8f9f7 10065
<> 144:ef7eb2e8f9f7 10066 #define EADC_AD0DAT5_OV_Pos (16) /*!< EADC AD0DAT5: OV Position */
<> 144:ef7eb2e8f9f7 10067 #define EADC_AD0DAT5_OV_Msk (0x1ul << EADC_AD0DAT5_OV_Pos) /*!< EADC AD0DAT5: OV Mask */
<> 144:ef7eb2e8f9f7 10068
<> 144:ef7eb2e8f9f7 10069 #define EADC_AD0DAT5_VALID_Pos (17) /*!< EADC AD0DAT5: VALID Position */
<> 144:ef7eb2e8f9f7 10070 #define EADC_AD0DAT5_VALID_Msk (0x1ul << EADC_AD0DAT5_VALID_Pos) /*!< EADC AD0DAT5: VALID Mask */
<> 144:ef7eb2e8f9f7 10071
<> 144:ef7eb2e8f9f7 10072 #define EADC_AD0DAT6_RESULT_Pos (0) /*!< EADC AD0DAT6: RESULT Position */
<> 144:ef7eb2e8f9f7 10073 #define EADC_AD0DAT6_RESULT_Msk (0xffful << EADC_AD0DAT6_RESULT_Pos) /*!< EADC AD0DAT6: RESULT Mask */
<> 144:ef7eb2e8f9f7 10074
<> 144:ef7eb2e8f9f7 10075 #define EADC_AD0DAT6_OV_Pos (16) /*!< EADC AD0DAT6: OV Position */
<> 144:ef7eb2e8f9f7 10076 #define EADC_AD0DAT6_OV_Msk (0x1ul << EADC_AD0DAT6_OV_Pos) /*!< EADC AD0DAT6: OV Mask */
<> 144:ef7eb2e8f9f7 10077
<> 144:ef7eb2e8f9f7 10078 #define EADC_AD0DAT6_VALID_Pos (17) /*!< EADC AD0DAT6: VALID Position */
<> 144:ef7eb2e8f9f7 10079 #define EADC_AD0DAT6_VALID_Msk (0x1ul << EADC_AD0DAT6_VALID_Pos) /*!< EADC AD0DAT6: VALID Mask */
<> 144:ef7eb2e8f9f7 10080
<> 144:ef7eb2e8f9f7 10081 #define EADC_AD0DAT7_RESULT_Pos (0) /*!< EADC AD0DAT7: RESULT Position */
<> 144:ef7eb2e8f9f7 10082 #define EADC_AD0DAT7_RESULT_Msk (0xffful << EADC_AD0DAT7_RESULT_Pos) /*!< EADC AD0DAT7: RESULT Mask */
<> 144:ef7eb2e8f9f7 10083
<> 144:ef7eb2e8f9f7 10084 #define EADC_AD0DAT7_OV_Pos (16) /*!< EADC AD0DAT7: OV Position */
<> 144:ef7eb2e8f9f7 10085 #define EADC_AD0DAT7_OV_Msk (0x1ul << EADC_AD0DAT7_OV_Pos) /*!< EADC AD0DAT7: OV Mask */
<> 144:ef7eb2e8f9f7 10086
<> 144:ef7eb2e8f9f7 10087 #define EADC_AD0DAT7_VALID_Pos (17) /*!< EADC AD0DAT7: VALID Position */
<> 144:ef7eb2e8f9f7 10088 #define EADC_AD0DAT7_VALID_Msk (0x1ul << EADC_AD0DAT7_VALID_Pos) /*!< EADC AD0DAT7: VALID Mask */
<> 144:ef7eb2e8f9f7 10089
<> 144:ef7eb2e8f9f7 10090 #define EADC_AD1DAT0_RESULT_Pos (0) /*!< EADC AD1DAT0: RESULT Position */
<> 144:ef7eb2e8f9f7 10091 #define EADC_AD1DAT0_RESULT_Msk (0xffful << EADC_AD1DAT0_RESULT_Pos) /*!< EADC AD1DAT0: RESULT Mask */
<> 144:ef7eb2e8f9f7 10092
<> 144:ef7eb2e8f9f7 10093 #define EADC_AD1DAT0_OV_Pos (16) /*!< EADC AD1DAT0: OV Position */
<> 144:ef7eb2e8f9f7 10094 #define EADC_AD1DAT0_OV_Msk (0x1ul << EADC_AD1DAT0_OV_Pos) /*!< EADC AD1DAT0: OV Mask */
<> 144:ef7eb2e8f9f7 10095
<> 144:ef7eb2e8f9f7 10096 #define EADC_AD1DAT0_VALID_Pos (17) /*!< EADC AD1DAT0: VALID Position */
<> 144:ef7eb2e8f9f7 10097 #define EADC_AD1DAT0_VALID_Msk (0x1ul << EADC_AD1DAT0_VALID_Pos) /*!< EADC AD1DAT0: VALID Mask */
<> 144:ef7eb2e8f9f7 10098
<> 144:ef7eb2e8f9f7 10099 #define EADC_AD1DAT1_RESULT_Pos (0) /*!< EADC AD1DAT1: RESULT Position */
<> 144:ef7eb2e8f9f7 10100 #define EADC_AD1DAT1_RESULT_Msk (0xffful << EADC_AD1DAT1_RESULT_Pos) /*!< EADC AD1DAT1: RESULT Mask */
<> 144:ef7eb2e8f9f7 10101
<> 144:ef7eb2e8f9f7 10102 #define EADC_AD1DAT1_OV_Pos (16) /*!< EADC AD1DAT1: OV Position */
<> 144:ef7eb2e8f9f7 10103 #define EADC_AD1DAT1_OV_Msk (0x1ul << EADC_AD1DAT1_OV_Pos) /*!< EADC AD1DAT1: OV Mask */
<> 144:ef7eb2e8f9f7 10104
<> 144:ef7eb2e8f9f7 10105 #define EADC_AD1DAT1_VALID_Pos (17) /*!< EADC AD1DAT1: VALID Position */
<> 144:ef7eb2e8f9f7 10106 #define EADC_AD1DAT1_VALID_Msk (0x1ul << EADC_AD1DAT1_VALID_Pos) /*!< EADC AD1DAT1: VALID Mask */
<> 144:ef7eb2e8f9f7 10107
<> 144:ef7eb2e8f9f7 10108 #define EADC_AD1DAT2_RESULT_Pos (0) /*!< EADC AD1DAT2: RESULT Position */
<> 144:ef7eb2e8f9f7 10109 #define EADC_AD1DAT2_RESULT_Msk (0xffful << EADC_AD1DAT2_RESULT_Pos) /*!< EADC AD1DAT2: RESULT Mask */
<> 144:ef7eb2e8f9f7 10110
<> 144:ef7eb2e8f9f7 10111 #define EADC_AD1DAT2_OV_Pos (16) /*!< EADC AD1DAT2: OV Position */
<> 144:ef7eb2e8f9f7 10112 #define EADC_AD1DAT2_OV_Msk (0x1ul << EADC_AD1DAT2_OV_Pos) /*!< EADC AD1DAT2: OV Mask */
<> 144:ef7eb2e8f9f7 10113
<> 144:ef7eb2e8f9f7 10114 #define EADC_AD1DAT2_VALID_Pos (17) /*!< EADC AD1DAT2: VALID Position */
<> 144:ef7eb2e8f9f7 10115 #define EADC_AD1DAT2_VALID_Msk (0x1ul << EADC_AD1DAT2_VALID_Pos) /*!< EADC AD1DAT2: VALID Mask */
<> 144:ef7eb2e8f9f7 10116
<> 144:ef7eb2e8f9f7 10117 #define EADC_AD1DAT3_RESULT_Pos (0) /*!< EADC AD1DAT3: RESULT Position */
<> 144:ef7eb2e8f9f7 10118 #define EADC_AD1DAT3_RESULT_Msk (0xffful << EADC_AD1DAT3_RESULT_Pos) /*!< EADC AD1DAT3: RESULT Mask */
<> 144:ef7eb2e8f9f7 10119
<> 144:ef7eb2e8f9f7 10120 #define EADC_AD1DAT3_OV_Pos (16) /*!< EADC AD1DAT3: OV Position */
<> 144:ef7eb2e8f9f7 10121 #define EADC_AD1DAT3_OV_Msk (0x1ul << EADC_AD1DAT3_OV_Pos) /*!< EADC AD1DAT3: OV Mask */
<> 144:ef7eb2e8f9f7 10122
<> 144:ef7eb2e8f9f7 10123 #define EADC_AD1DAT3_VALID_Pos (17) /*!< EADC AD1DAT3: VALID Position */
<> 144:ef7eb2e8f9f7 10124 #define EADC_AD1DAT3_VALID_Msk (0x1ul << EADC_AD1DAT3_VALID_Pos) /*!< EADC AD1DAT3: VALID Mask */
<> 144:ef7eb2e8f9f7 10125
<> 144:ef7eb2e8f9f7 10126 #define EADC_AD1DAT4_RESULT_Pos (0) /*!< EADC AD1DAT4: RESULT Position */
<> 144:ef7eb2e8f9f7 10127 #define EADC_AD1DAT4_RESULT_Msk (0xffful << EADC_AD1DAT4_RESULT_Pos) /*!< EADC AD1DAT4: RESULT Mask */
<> 144:ef7eb2e8f9f7 10128
<> 144:ef7eb2e8f9f7 10129 #define EADC_AD1DAT4_OV_Pos (16) /*!< EADC AD1DAT4: OV Position */
<> 144:ef7eb2e8f9f7 10130 #define EADC_AD1DAT4_OV_Msk (0x1ul << EADC_AD1DAT4_OV_Pos) /*!< EADC AD1DAT4: OV Mask */
<> 144:ef7eb2e8f9f7 10131
<> 144:ef7eb2e8f9f7 10132 #define EADC_AD1DAT4_VALID_Pos (17) /*!< EADC AD1DAT4: VALID Position */
<> 144:ef7eb2e8f9f7 10133 #define EADC_AD1DAT4_VALID_Msk (0x1ul << EADC_AD1DAT4_VALID_Pos) /*!< EADC AD1DAT4: VALID Mask */
<> 144:ef7eb2e8f9f7 10134
<> 144:ef7eb2e8f9f7 10135 #define EADC_AD1DAT5_RESULT_Pos (0) /*!< EADC AD1DAT5: RESULT Position */
<> 144:ef7eb2e8f9f7 10136 #define EADC_AD1DAT5_RESULT_Msk (0xffful << EADC_AD1DAT5_RESULT_Pos) /*!< EADC AD1DAT5: RESULT Mask */
<> 144:ef7eb2e8f9f7 10137
<> 144:ef7eb2e8f9f7 10138 #define EADC_AD1DAT5_OV_Pos (16) /*!< EADC AD1DAT5: OV Position */
<> 144:ef7eb2e8f9f7 10139 #define EADC_AD1DAT5_OV_Msk (0x1ul << EADC_AD1DAT5_OV_Pos) /*!< EADC AD1DAT5: OV Mask */
<> 144:ef7eb2e8f9f7 10140
<> 144:ef7eb2e8f9f7 10141 #define EADC_AD1DAT5_VALID_Pos (17) /*!< EADC AD1DAT5: VALID Position */
<> 144:ef7eb2e8f9f7 10142 #define EADC_AD1DAT5_VALID_Msk (0x1ul << EADC_AD1DAT5_VALID_Pos) /*!< EADC AD1DAT5: VALID Mask */
<> 144:ef7eb2e8f9f7 10143
<> 144:ef7eb2e8f9f7 10144 #define EADC_AD1DAT6_RESULT_Pos (0) /*!< EADC AD1DAT6: RESULT Position */
<> 144:ef7eb2e8f9f7 10145 #define EADC_AD1DAT6_RESULT_Msk (0xffful << EADC_AD1DAT6_RESULT_Pos) /*!< EADC AD1DAT6: RESULT Mask */
<> 144:ef7eb2e8f9f7 10146
<> 144:ef7eb2e8f9f7 10147 #define EADC_AD1DAT6_OV_Pos (16) /*!< EADC AD1DAT6: OV Position */
<> 144:ef7eb2e8f9f7 10148 #define EADC_AD1DAT6_OV_Msk (0x1ul << EADC_AD1DAT6_OV_Pos) /*!< EADC AD1DAT6: OV Mask */
<> 144:ef7eb2e8f9f7 10149
<> 144:ef7eb2e8f9f7 10150 #define EADC_AD1DAT6_VALID_Pos (17) /*!< EADC AD1DAT6: VALID Position */
<> 144:ef7eb2e8f9f7 10151 #define EADC_AD1DAT6_VALID_Msk (0x1ul << EADC_AD1DAT6_VALID_Pos) /*!< EADC AD1DAT6: VALID Mask */
<> 144:ef7eb2e8f9f7 10152
<> 144:ef7eb2e8f9f7 10153 #define EADC_AD1DAT7_RESULT_Pos (0) /*!< EADC AD1DAT7: RESULT Position */
<> 144:ef7eb2e8f9f7 10154 #define EADC_AD1DAT7_RESULT_Msk (0xffful << EADC_AD1DAT7_RESULT_Pos) /*!< EADC AD1DAT7: RESULT Mask */
<> 144:ef7eb2e8f9f7 10155
<> 144:ef7eb2e8f9f7 10156 #define EADC_AD1DAT7_OV_Pos (16) /*!< EADC AD1DAT7: OV Position */
<> 144:ef7eb2e8f9f7 10157 #define EADC_AD1DAT7_OV_Msk (0x1ul << EADC_AD1DAT7_OV_Pos) /*!< EADC AD1DAT7: OV Mask */
<> 144:ef7eb2e8f9f7 10158
<> 144:ef7eb2e8f9f7 10159 #define EADC_AD1DAT7_VALID_Pos (17) /*!< EADC AD1DAT7: VALID Position */
<> 144:ef7eb2e8f9f7 10160 #define EADC_AD1DAT7_VALID_Msk (0x1ul << EADC_AD1DAT7_VALID_Pos) /*!< EADC AD1DAT7: VALID Mask */
<> 144:ef7eb2e8f9f7 10161
<> 144:ef7eb2e8f9f7 10162 #define EADC_CTL_ADCEN_Pos (0) /*!< EADC CTL: ADCEN Position */
<> 144:ef7eb2e8f9f7 10163 #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) /*!< EADC CTL: ADCEN Mask */
<> 144:ef7eb2e8f9f7 10164
<> 144:ef7eb2e8f9f7 10165 #define EADC_CTL_ADCRST_Pos (1) /*!< EADC CTL: ADCRST Position */
<> 144:ef7eb2e8f9f7 10166 #define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) /*!< EADC CTL: ADCRST Mask */
<> 144:ef7eb2e8f9f7 10167
<> 144:ef7eb2e8f9f7 10168 #define EADC_CTL_ADCIEN0_Pos (2) /*!< EADC CTL: ADCIEN0 Position */
<> 144:ef7eb2e8f9f7 10169 #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) /*!< EADC CTL: ADCIEN0 Mask */
<> 144:ef7eb2e8f9f7 10170
<> 144:ef7eb2e8f9f7 10171 #define EADC_CTL_ADCIEN1_Pos (3) /*!< EADC CTL: ADCIEN1 Position */
<> 144:ef7eb2e8f9f7 10172 #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) /*!< EADC CTL: ADCIEN1 Mask */
<> 144:ef7eb2e8f9f7 10173
<> 144:ef7eb2e8f9f7 10174 #define EADC_CTL_ADCIEN2_Pos (4) /*!< EADC CTL: ADCIEN2 Position */
<> 144:ef7eb2e8f9f7 10175 #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) /*!< EADC CTL: ADCIEN2 Mask */
<> 144:ef7eb2e8f9f7 10176
<> 144:ef7eb2e8f9f7 10177 #define EADC_CTL_ADCIEN3_Pos (5) /*!< EADC CTL: ADCIEN3 Position */
<> 144:ef7eb2e8f9f7 10178 #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) /*!< EADC CTL: ADCIEN3 Mask */
<> 144:ef7eb2e8f9f7 10179
<> 144:ef7eb2e8f9f7 10180 #define EADC_SWTRG_SWTRG7_0_Pos (0) /*!< EADC SWTRG: SWTRG7_0 Position */
<> 144:ef7eb2e8f9f7 10181 #define EADC_SWTRG_SWTRG7_0_Msk (0xfful << EADC_SWTRG_SWTRG7_0_Pos) /*!< EADC SWTRG: SWTRG7_0 Mask */
<> 144:ef7eb2e8f9f7 10182
<> 144:ef7eb2e8f9f7 10183 #define EADC_SWTRG_SWTRG15_8_Pos (8) /*!< EADC SWTRG: SWTRG15_8 Position */
<> 144:ef7eb2e8f9f7 10184 #define EADC_SWTRG_SWTRG15_8_Msk (0xfful << EADC_SWTRG_SWTRG15_8_Pos) /*!< EADC SWTRG: SWTRG15_8 Mask */
<> 144:ef7eb2e8f9f7 10185
<> 144:ef7eb2e8f9f7 10186 #define EADC_PENDSTS_STPF7_0_Pos (0) /*!< EADC PENDSTS: STPF7_0 Position */
<> 144:ef7eb2e8f9f7 10187 #define EADC_PENDSTS_STPF7_0_Msk (0xfful << EADC_PENDSTS_STPF7_0_Pos) /*!< EADC PENDSTS: STPF7_0 Mask */
<> 144:ef7eb2e8f9f7 10188
<> 144:ef7eb2e8f9f7 10189 #define EADC_PENDSTS_STPF15_8_Pos (8) /*!< EADC PENDSTS: STPF15_8 Position */
<> 144:ef7eb2e8f9f7 10190 #define EADC_PENDSTS_STPF15_8_Msk (0xfful << EADC_PENDSTS_STPF15_8_Pos) /*!< EADC PENDSTS: STPF15_8 Mask */
<> 144:ef7eb2e8f9f7 10191
<> 144:ef7eb2e8f9f7 10192 #define EADC_ADIFOV_ADFOV0_Pos (0) /*!< EADC ADIFOV: ADFOV0 Position */
<> 144:ef7eb2e8f9f7 10193 #define EADC_ADIFOV_ADFOV0_Msk (0x1ul << EADC_ADIFOV_ADFOV0_Pos) /*!< EADC ADIFOV: ADFOV0 Mask */
<> 144:ef7eb2e8f9f7 10194
<> 144:ef7eb2e8f9f7 10195 #define EADC_ADIFOV_ADFOV1_Pos (1) /*!< EADC ADIFOV: ADFOV1 Position */
<> 144:ef7eb2e8f9f7 10196 #define EADC_ADIFOV_ADFOV1_Msk (0x1ul << EADC_ADIFOV_ADFOV1_Pos) /*!< EADC ADIFOV: ADFOV1 Mask */
<> 144:ef7eb2e8f9f7 10197
<> 144:ef7eb2e8f9f7 10198 #define EADC_ADIFOV_ADFOV2_Pos (2) /*!< EADC ADIFOV: ADFOV2 Position */
<> 144:ef7eb2e8f9f7 10199 #define EADC_ADIFOV_ADFOV2_Msk (0x1ul << EADC_ADIFOV_ADFOV2_Pos) /*!< EADC ADIFOV: ADFOV2 Mask */
<> 144:ef7eb2e8f9f7 10200
<> 144:ef7eb2e8f9f7 10201 #define EADC_ADIFOV_ADFOV3_Pos (3) /*!< EADC ADIFOV: ADFOV3 Position */
<> 144:ef7eb2e8f9f7 10202 #define EADC_ADIFOV_ADFOV3_Msk (0x1ul << EADC_ADIFOV_ADFOV3_Pos) /*!< EADC ADIFOV: ADFOV3 Mask */
<> 144:ef7eb2e8f9f7 10203
<> 144:ef7eb2e8f9f7 10204 #define EADC_OVSTS_SPOVF7_0_Pos (0) /*!< EADC OVSTS: SPOVF7_0 Position */
<> 144:ef7eb2e8f9f7 10205 #define EADC_OVSTS_SPOVF7_0_Msk (0xfful << EADC_OVSTS_SPOVF7_0_Pos) /*!< EADC OVSTS: SPOVF7_0 Mask */
<> 144:ef7eb2e8f9f7 10206
<> 144:ef7eb2e8f9f7 10207 #define EADC_OVSTS_SPOVF15_8_Pos (8) /*!< EADC OVSTS: SPOVF15_8 Position */
<> 144:ef7eb2e8f9f7 10208 #define EADC_OVSTS_SPOVF15_8_Msk (0xfful << EADC_OVSTS_SPOVF15_8_Pos) /*!< EADC OVSTS: SPOVF15_8 Mask */
<> 144:ef7eb2e8f9f7 10209
<> 144:ef7eb2e8f9f7 10210 #define EADC_AD0SPCTL0_CHSEL_Pos (0) /*!< EADC AD0SPCTL0: CHSEL Position */
<> 144:ef7eb2e8f9f7 10211 #define EADC_AD0SPCTL0_CHSEL_Msk (0xful << EADC_AD0SPCTL0_CHSEL_Pos) /*!< EADC AD0SPCTL0: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10212
<> 144:ef7eb2e8f9f7 10213 #define EADC_AD0SPCTL0_TRGSEL_Pos (4) /*!< EADC AD0SPCTL0: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10214 #define EADC_AD0SPCTL0_TRGSEL_Msk (0xful << EADC_AD0SPCTL0_TRGSEL_Pos) /*!< EADC AD0SPCTL0: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10215
<> 144:ef7eb2e8f9f7 10216 #define EADC_AD0SPCTL0_TRGDLYCNT_Pos (8) /*!< EADC AD0SPCTL0: TRGDLYCNT Position */
<> 144:ef7eb2e8f9f7 10217 #define EADC_AD0SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL0_TRGDLYCNT_Pos) /*!< EADC AD0SPCTL0: TRGDLYCNT Mask */
<> 144:ef7eb2e8f9f7 10218
<> 144:ef7eb2e8f9f7 10219 #define EADC_AD0SPCTL0_TRGDLYDIV_Pos (16) /*!< EADC AD0SPCTL0: TRGDLYDIV Position */
<> 144:ef7eb2e8f9f7 10220 #define EADC_AD0SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL0_TRGDLYDIV_Pos) /*!< EADC AD0SPCTL0: TRGDLYDIV Mask */
<> 144:ef7eb2e8f9f7 10221
<> 144:ef7eb2e8f9f7 10222 #define EADC_AD0SPCTL0_EXTREN_Pos (20) /*!< EADC AD0SPCTL0: EXTREN Position */
<> 144:ef7eb2e8f9f7 10223 #define EADC_AD0SPCTL0_EXTREN_Msk (0x1ul << EADC_AD0SPCTL0_EXTREN_Pos) /*!< EADC AD0SPCTL0: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10224
<> 144:ef7eb2e8f9f7 10225 #define EADC_AD0SPCTL0_EXTFEN_Pos (21) /*!< EADC AD0SPCTL0: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10226 #define EADC_AD0SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL0_EXTFEN_Pos) /*!< EADC AD0SPCTL0: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10227
<> 144:ef7eb2e8f9f7 10228 #define EADC_AD0SPCTL1_CHSEL_Pos (0) /*!< EADC AD0SPCTL1: CHSEL Position */
<> 144:ef7eb2e8f9f7 10229 #define EADC_AD0SPCTL1_CHSEL_Msk (0xful << EADC_AD0SPCTL1_CHSEL_Pos) /*!< EADC AD0SPCTL1: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10230
<> 144:ef7eb2e8f9f7 10231 #define EADC_AD0SPCTL1_TRGSEL_Pos (4) /*!< EADC AD0SPCTL1: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10232 #define EADC_AD0SPCTL1_TRGSEL_Msk (0xful << EADC_AD0SPCTL1_TRGSEL_Pos) /*!< EADC AD0SPCTL1: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10233
<> 144:ef7eb2e8f9f7 10234 #define EADC_AD0SPCTL1_TRGDLYCNT_Pos (8) /*!< EADC AD0SPCTL1: TRGDLYCNT Position */
<> 144:ef7eb2e8f9f7 10235 #define EADC_AD0SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL1_TRGDLYCNT_Pos) /*!< EADC AD0SPCTL1: TRGDLYCNT Mask */
<> 144:ef7eb2e8f9f7 10236
<> 144:ef7eb2e8f9f7 10237 #define EADC_AD0SPCTL1_TRGDLYDIV_Pos (16) /*!< EADC AD0SPCTL1: TRGDLYDIV Position */
<> 144:ef7eb2e8f9f7 10238 #define EADC_AD0SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL1_TRGDLYDIV_Pos) /*!< EADC AD0SPCTL1: TRGDLYDIV Mask */
<> 144:ef7eb2e8f9f7 10239
<> 144:ef7eb2e8f9f7 10240 #define EADC_AD0SPCTL1_EXTREN_Pos (20) /*!< EADC AD0SPCTL1: EXTREN Position */
<> 144:ef7eb2e8f9f7 10241 #define EADC_AD0SPCTL1_EXTREN_Msk (0x1ul << EADC_AD0SPCTL1_EXTREN_Pos) /*!< EADC AD0SPCTL1: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10242
<> 144:ef7eb2e8f9f7 10243 #define EADC_AD0SPCTL1_EXTFEN_Pos (21) /*!< EADC AD0SPCTL1: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10244 #define EADC_AD0SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL1_EXTFEN_Pos) /*!< EADC AD0SPCTL1: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10245
<> 144:ef7eb2e8f9f7 10246 #define EADC_AD0SPCTL2_CHSEL_Pos (0) /*!< EADC AD0SPCTL2: CHSEL Position */
<> 144:ef7eb2e8f9f7 10247 #define EADC_AD0SPCTL2_CHSEL_Msk (0xful << EADC_AD0SPCTL2_CHSEL_Pos) /*!< EADC AD0SPCTL2: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10248
<> 144:ef7eb2e8f9f7 10249 #define EADC_AD0SPCTL2_TRGSEL_Pos (4) /*!< EADC AD0SPCTL2: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10250 #define EADC_AD0SPCTL2_TRGSEL_Msk (0xful << EADC_AD0SPCTL2_TRGSEL_Pos) /*!< EADC AD0SPCTL2: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10251
<> 144:ef7eb2e8f9f7 10252 #define EADC_AD0SPCTL2_TRGDLYCNT_Pos (8) /*!< EADC AD0SPCTL2: TRGDLYCNT Position */
<> 144:ef7eb2e8f9f7 10253 #define EADC_AD0SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL2_TRGDLYCNT_Pos) /*!< EADC AD0SPCTL2: TRGDLYCNT Mask */
<> 144:ef7eb2e8f9f7 10254
<> 144:ef7eb2e8f9f7 10255 #define EADC_AD0SPCTL2_TRGDLYDIV_Pos (16) /*!< EADC AD0SPCTL2: TRGDLYDIV Position */
<> 144:ef7eb2e8f9f7 10256 #define EADC_AD0SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL2_TRGDLYDIV_Pos) /*!< EADC AD0SPCTL2: TRGDLYDIV Mask */
<> 144:ef7eb2e8f9f7 10257
<> 144:ef7eb2e8f9f7 10258 #define EADC_AD0SPCTL2_EXTREN_Pos (20) /*!< EADC AD0SPCTL2: EXTREN Position */
<> 144:ef7eb2e8f9f7 10259 #define EADC_AD0SPCTL2_EXTREN_Msk (0x1ul << EADC_AD0SPCTL2_EXTREN_Pos) /*!< EADC AD0SPCTL2: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10260
<> 144:ef7eb2e8f9f7 10261 #define EADC_AD0SPCTL2_EXTFEN_Pos (21) /*!< EADC AD0SPCTL2: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10262 #define EADC_AD0SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL2_EXTFEN_Pos) /*!< EADC AD0SPCTL2: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10263
<> 144:ef7eb2e8f9f7 10264 #define EADC_AD0SPCTL3_CHSEL_Pos (0) /*!< EADC AD0SPCTL3: CHSEL Position */
<> 144:ef7eb2e8f9f7 10265 #define EADC_AD0SPCTL3_CHSEL_Msk (0xful << EADC_AD0SPCTL3_CHSEL_Pos) /*!< EADC AD0SPCTL3: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10266
<> 144:ef7eb2e8f9f7 10267 #define EADC_AD0SPCTL3_TRGSEL_Pos (4) /*!< EADC AD0SPCTL3: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10268 #define EADC_AD0SPCTL3_TRGSEL_Msk (0xful << EADC_AD0SPCTL3_TRGSEL_Pos) /*!< EADC AD0SPCTL3: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10269
<> 144:ef7eb2e8f9f7 10270 #define EADC_AD0SPCTL3_TRGDLYCNT_Pos (8) /*!< EADC AD0SPCTL3: TRGDLYCNT Position */
<> 144:ef7eb2e8f9f7 10271 #define EADC_AD0SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD0SPCTL3_TRGDLYCNT_Pos) /*!< EADC AD0SPCTL3: TRGDLYCNT Mask */
<> 144:ef7eb2e8f9f7 10272
<> 144:ef7eb2e8f9f7 10273 #define EADC_AD0SPCTL3_TRGDLYDIV_Pos (16) /*!< EADC AD0SPCTL3: TRGDLYDIV Position */
<> 144:ef7eb2e8f9f7 10274 #define EADC_AD0SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD0SPCTL3_TRGDLYDIV_Pos) /*!< EADC AD0SPCTL3: TRGDLYDIV Mask */
<> 144:ef7eb2e8f9f7 10275
<> 144:ef7eb2e8f9f7 10276 #define EADC_AD0SPCTL3_EXTREN_Pos (20) /*!< EADC AD0SPCTL3: EXTREN Position */
<> 144:ef7eb2e8f9f7 10277 #define EADC_AD0SPCTL3_EXTREN_Msk (0x1ul << EADC_AD0SPCTL3_EXTREN_Pos) /*!< EADC AD0SPCTL3: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10278
<> 144:ef7eb2e8f9f7 10279 #define EADC_AD0SPCTL3_EXTFEN_Pos (21) /*!< EADC AD0SPCTL3: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10280 #define EADC_AD0SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL3_EXTFEN_Pos) /*!< EADC AD0SPCTL3: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10281
<> 144:ef7eb2e8f9f7 10282 #define EADC_AD0SPCTL4_CHSEL_Pos (0) /*!< EADC AD0SPCTL4: CHSEL Position */
<> 144:ef7eb2e8f9f7 10283 #define EADC_AD0SPCTL4_CHSEL_Msk (0xful << EADC_AD0SPCTL4_CHSEL_Pos) /*!< EADC AD0SPCTL4: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10284
<> 144:ef7eb2e8f9f7 10285 #define EADC_AD0SPCTL4_TRGSEL_Pos (4) /*!< EADC AD0SPCTL4: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10286 #define EADC_AD0SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL4_TRGSEL_Pos) /*!< EADC AD0SPCTL4: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10287
<> 144:ef7eb2e8f9f7 10288 #define EADC_AD0SPCTL4_EXTREN_Pos (20) /*!< EADC AD0SPCTL4: EXTREN Position */
<> 144:ef7eb2e8f9f7 10289 #define EADC_AD0SPCTL4_EXTREN_Msk (0x1ul << EADC_AD0SPCTL4_EXTREN_Pos) /*!< EADC AD0SPCTL4: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10290
<> 144:ef7eb2e8f9f7 10291 #define EADC_AD0SPCTL4_EXTFEN_Pos (21) /*!< EADC AD0SPCTL4: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10292 #define EADC_AD0SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL4_EXTFEN_Pos) /*!< EADC AD0SPCTL4: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10293
<> 144:ef7eb2e8f9f7 10294 #define EADC_AD0SPCTL5_CHSEL_Pos (0) /*!< EADC AD0SPCTL5: CHSEL Position */
<> 144:ef7eb2e8f9f7 10295 #define EADC_AD0SPCTL5_CHSEL_Msk (0xful << EADC_AD0SPCTL5_CHSEL_Pos) /*!< EADC AD0SPCTL5: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10296
<> 144:ef7eb2e8f9f7 10297 #define EADC_AD0SPCTL5_TRGSEL_Pos (4) /*!< EADC AD0SPCTL5: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10298 #define EADC_AD0SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL5_TRGSEL_Pos) /*!< EADC AD0SPCTL5: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10299
<> 144:ef7eb2e8f9f7 10300 #define EADC_AD0SPCTL5_EXTREN_Pos (20) /*!< EADC AD0SPCTL5: EXTREN Position */
<> 144:ef7eb2e8f9f7 10301 #define EADC_AD0SPCTL5_EXTREN_Msk (0x1ul << EADC_AD0SPCTL5_EXTREN_Pos) /*!< EADC AD0SPCTL5: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10302
<> 144:ef7eb2e8f9f7 10303 #define EADC_AD0SPCTL5_EXTFEN_Pos (21) /*!< EADC AD0SPCTL5: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10304 #define EADC_AD0SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL5_EXTFEN_Pos) /*!< EADC AD0SPCTL5: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10305
<> 144:ef7eb2e8f9f7 10306 #define EADC_AD0SPCTL6_CHSEL_Pos (0) /*!< EADC AD0SPCTL6: CHSEL Position */
<> 144:ef7eb2e8f9f7 10307 #define EADC_AD0SPCTL6_CHSEL_Msk (0xful << EADC_AD0SPCTL6_CHSEL_Pos) /*!< EADC AD0SPCTL6: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10308
<> 144:ef7eb2e8f9f7 10309 #define EADC_AD0SPCTL6_TRGSEL_Pos (4) /*!< EADC AD0SPCTL6: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10310 #define EADC_AD0SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL6_TRGSEL_Pos) /*!< EADC AD0SPCTL6: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10311
<> 144:ef7eb2e8f9f7 10312 #define EADC_AD0SPCTL6_EXTREN_Pos (20) /*!< EADC AD0SPCTL6: EXTREN Position */
<> 144:ef7eb2e8f9f7 10313 #define EADC_AD0SPCTL6_EXTREN_Msk (0x1ul << EADC_AD0SPCTL6_EXTREN_Pos) /*!< EADC AD0SPCTL6: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10314
<> 144:ef7eb2e8f9f7 10315 #define EADC_AD0SPCTL6_EXTFEN_Pos (21) /*!< EADC AD0SPCTL6: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10316 #define EADC_AD0SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL6_EXTFEN_Pos) /*!< EADC AD0SPCTL6: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10317
<> 144:ef7eb2e8f9f7 10318 #define EADC_AD0SPCTL7_CHSEL_Pos (0) /*!< EADC AD0SPCTL7: CHSEL Position */
<> 144:ef7eb2e8f9f7 10319 #define EADC_AD0SPCTL7_CHSEL_Msk (0xful << EADC_AD0SPCTL7_CHSEL_Pos) /*!< EADC AD0SPCTL7: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10320
<> 144:ef7eb2e8f9f7 10321 #define EADC_AD0SPCTL7_TRGSEL_Pos (4) /*!< EADC AD0SPCTL7: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10322 #define EADC_AD0SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD0SPCTL7_TRGSEL_Pos) /*!< EADC AD0SPCTL7: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10323
<> 144:ef7eb2e8f9f7 10324 #define EADC_AD0SPCTL7_EXTREN_Pos (20) /*!< EADC AD0SPCTL7: EXTREN Position */
<> 144:ef7eb2e8f9f7 10325 #define EADC_AD0SPCTL7_EXTREN_Msk (0x1ul << EADC_AD0SPCTL7_EXTREN_Pos) /*!< EADC AD0SPCTL7: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10326
<> 144:ef7eb2e8f9f7 10327 #define EADC_AD0SPCTL7_EXTFEN_Pos (21) /*!< EADC AD0SPCTL7: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10328 #define EADC_AD0SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD0SPCTL7_EXTFEN_Pos) /*!< EADC AD0SPCTL7: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10329
<> 144:ef7eb2e8f9f7 10330 #define EADC_AD1SPCTL0_CHSEL_Pos (0) /*!< EADC AD1SPCTL0: CHSEL Position */
<> 144:ef7eb2e8f9f7 10331 #define EADC_AD1SPCTL0_CHSEL_Msk (0xful << EADC_AD1SPCTL0_CHSEL_Pos) /*!< EADC AD1SPCTL0: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10332
<> 144:ef7eb2e8f9f7 10333 #define EADC_AD1SPCTL0_TRGSEL_Pos (4) /*!< EADC AD1SPCTL0: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10334 #define EADC_AD1SPCTL0_TRGSEL_Msk (0xful << EADC_AD1SPCTL0_TRGSEL_Pos) /*!< EADC AD1SPCTL0: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10335
<> 144:ef7eb2e8f9f7 10336 #define EADC_AD1SPCTL0_TRGDLYCNT_Pos (8) /*!< EADC AD1SPCTL0: TRGDLYCNT Position */
<> 144:ef7eb2e8f9f7 10337 #define EADC_AD1SPCTL0_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL0_TRGDLYCNT_Pos) /*!< EADC AD1SPCTL0: TRGDLYCNT Mask */
<> 144:ef7eb2e8f9f7 10338
<> 144:ef7eb2e8f9f7 10339 #define EADC_AD1SPCTL0_TRGDLYDIV_Pos (16) /*!< EADC AD1SPCTL0: TRGDLYDIV Position */
<> 144:ef7eb2e8f9f7 10340 #define EADC_AD1SPCTL0_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL0_TRGDLYDIV_Pos) /*!< EADC AD1SPCTL0: TRGDLYDIV Mask */
<> 144:ef7eb2e8f9f7 10341
<> 144:ef7eb2e8f9f7 10342 #define EADC_AD1SPCTL0_EXTREN_Pos (20) /*!< EADC AD1SPCTL0: EXTREN Position */
<> 144:ef7eb2e8f9f7 10343 #define EADC_AD1SPCTL0_EXTREN_Msk (0x1ul << EADC_AD1SPCTL0_EXTREN_Pos) /*!< EADC AD1SPCTL0: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10344
<> 144:ef7eb2e8f9f7 10345 #define EADC_AD1SPCTL0_EXTFEN_Pos (21) /*!< EADC AD1SPCTL0: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10346 #define EADC_AD1SPCTL0_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL0_EXTFEN_Pos) /*!< EADC AD1SPCTL0: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10347
<> 144:ef7eb2e8f9f7 10348 #define EADC_AD1SPCTL1_CHSEL_Pos (0) /*!< EADC AD1SPCTL1: CHSEL Position */
<> 144:ef7eb2e8f9f7 10349 #define EADC_AD1SPCTL1_CHSEL_Msk (0xful << EADC_AD1SPCTL1_CHSEL_Pos) /*!< EADC AD1SPCTL1: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10350
<> 144:ef7eb2e8f9f7 10351 #define EADC_AD1SPCTL1_TRGSEL_Pos (4) /*!< EADC AD1SPCTL1: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10352 #define EADC_AD1SPCTL1_TRGSEL_Msk (0xful << EADC_AD1SPCTL1_TRGSEL_Pos) /*!< EADC AD1SPCTL1: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10353
<> 144:ef7eb2e8f9f7 10354 #define EADC_AD1SPCTL1_TRGDLYCNT_Pos (8) /*!< EADC AD1SPCTL1: TRGDLYCNT Position */
<> 144:ef7eb2e8f9f7 10355 #define EADC_AD1SPCTL1_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL1_TRGDLYCNT_Pos) /*!< EADC AD1SPCTL1: TRGDLYCNT Mask */
<> 144:ef7eb2e8f9f7 10356
<> 144:ef7eb2e8f9f7 10357 #define EADC_AD1SPCTL1_TRGDLYDIV_Pos (16) /*!< EADC AD1SPCTL1: TRGDLYDIV Position */
<> 144:ef7eb2e8f9f7 10358 #define EADC_AD1SPCTL1_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL1_TRGDLYDIV_Pos) /*!< EADC AD1SPCTL1: TRGDLYDIV Mask */
<> 144:ef7eb2e8f9f7 10359
<> 144:ef7eb2e8f9f7 10360 #define EADC_AD1SPCTL1_EXTREN_Pos (20) /*!< EADC AD1SPCTL1: EXTREN Position */
<> 144:ef7eb2e8f9f7 10361 #define EADC_AD1SPCTL1_EXTREN_Msk (0x1ul << EADC_AD1SPCTL1_EXTREN_Pos) /*!< EADC AD1SPCTL1: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10362
<> 144:ef7eb2e8f9f7 10363 #define EADC_AD1SPCTL1_EXTFEN_Pos (21) /*!< EADC AD1SPCTL1: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10364 #define EADC_AD1SPCTL1_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL1_EXTFEN_Pos) /*!< EADC AD1SPCTL1: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10365
<> 144:ef7eb2e8f9f7 10366 #define EADC_AD1SPCTL2_CHSEL_Pos (0) /*!< EADC AD1SPCTL2: CHSEL Position */
<> 144:ef7eb2e8f9f7 10367 #define EADC_AD1SPCTL2_CHSEL_Msk (0xful << EADC_AD1SPCTL2_CHSEL_Pos) /*!< EADC AD1SPCTL2: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10368
<> 144:ef7eb2e8f9f7 10369 #define EADC_AD1SPCTL2_TRGSEL_Pos (4) /*!< EADC AD1SPCTL2: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10370 #define EADC_AD1SPCTL2_TRGSEL_Msk (0xful << EADC_AD1SPCTL2_TRGSEL_Pos) /*!< EADC AD1SPCTL2: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10371
<> 144:ef7eb2e8f9f7 10372 #define EADC_AD1SPCTL2_TRGDLYCNT_Pos (8) /*!< EADC AD1SPCTL2: TRGDLYCNT Position */
<> 144:ef7eb2e8f9f7 10373 #define EADC_AD1SPCTL2_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL2_TRGDLYCNT_Pos) /*!< EADC AD1SPCTL2: TRGDLYCNT Mask */
<> 144:ef7eb2e8f9f7 10374
<> 144:ef7eb2e8f9f7 10375 #define EADC_AD1SPCTL2_TRGDLYDIV_Pos (16) /*!< EADC AD1SPCTL2: TRGDLYDIV Position */
<> 144:ef7eb2e8f9f7 10376 #define EADC_AD1SPCTL2_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL2_TRGDLYDIV_Pos) /*!< EADC AD1SPCTL2: TRGDLYDIV Mask */
<> 144:ef7eb2e8f9f7 10377
<> 144:ef7eb2e8f9f7 10378 #define EADC_AD1SPCTL2_EXTREN_Pos (20) /*!< EADC AD1SPCTL2: EXTREN Position */
<> 144:ef7eb2e8f9f7 10379 #define EADC_AD1SPCTL2_EXTREN_Msk (0x1ul << EADC_AD1SPCTL2_EXTREN_Pos) /*!< EADC AD1SPCTL2: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10380
<> 144:ef7eb2e8f9f7 10381 #define EADC_AD1SPCTL2_EXTFEN_Pos (21) /*!< EADC AD1SPCTL2: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10382 #define EADC_AD1SPCTL2_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL2_EXTFEN_Pos) /*!< EADC AD1SPCTL2: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10383
<> 144:ef7eb2e8f9f7 10384 #define EADC_AD1SPCTL3_CHSEL_Pos (0) /*!< EADC AD1SPCTL3: CHSEL Position */
<> 144:ef7eb2e8f9f7 10385 #define EADC_AD1SPCTL3_CHSEL_Msk (0xful << EADC_AD1SPCTL3_CHSEL_Pos) /*!< EADC AD1SPCTL3: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10386
<> 144:ef7eb2e8f9f7 10387 #define EADC_AD1SPCTL3_TRGSEL_Pos (4) /*!< EADC AD1SPCTL3: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10388 #define EADC_AD1SPCTL3_TRGSEL_Msk (0xful << EADC_AD1SPCTL3_TRGSEL_Pos) /*!< EADC AD1SPCTL3: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10389
<> 144:ef7eb2e8f9f7 10390 #define EADC_AD1SPCTL3_TRGDLYCNT_Pos (8) /*!< EADC AD1SPCTL3: TRGDLYCNT Position */
<> 144:ef7eb2e8f9f7 10391 #define EADC_AD1SPCTL3_TRGDLYCNT_Msk (0xfful << EADC_AD1SPCTL3_TRGDLYCNT_Pos) /*!< EADC AD1SPCTL3: TRGDLYCNT Mask */
<> 144:ef7eb2e8f9f7 10392
<> 144:ef7eb2e8f9f7 10393 #define EADC_AD1SPCTL3_TRGDLYDIV_Pos (16) /*!< EADC AD1SPCTL3: TRGDLYDIV Position */
<> 144:ef7eb2e8f9f7 10394 #define EADC_AD1SPCTL3_TRGDLYDIV_Msk (0x3ul << EADC_AD1SPCTL3_TRGDLYDIV_Pos) /*!< EADC AD1SPCTL3: TRGDLYDIV Mask */
<> 144:ef7eb2e8f9f7 10395
<> 144:ef7eb2e8f9f7 10396 #define EADC_AD1SPCTL3_EXTREN_Pos (20) /*!< EADC AD1SPCTL3: EXTREN Position */
<> 144:ef7eb2e8f9f7 10397 #define EADC_AD1SPCTL3_EXTREN_Msk (0x1ul << EADC_AD1SPCTL3_EXTREN_Pos) /*!< EADC AD1SPCTL3: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10398
<> 144:ef7eb2e8f9f7 10399 #define EADC_AD1SPCTL3_EXTFEN_Pos (21) /*!< EADC AD1SPCTL3: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10400 #define EADC_AD1SPCTL3_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL3_EXTFEN_Pos) /*!< EADC AD1SPCTL3: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10401
<> 144:ef7eb2e8f9f7 10402 #define EADC_AD1SPCTL4_CHSEL_Pos (0) /*!< EADC AD1SPCTL4: CHSEL Position */
<> 144:ef7eb2e8f9f7 10403 #define EADC_AD1SPCTL4_CHSEL_Msk (0xful << EADC_AD1SPCTL4_CHSEL_Pos) /*!< EADC AD1SPCTL4: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10404
<> 144:ef7eb2e8f9f7 10405 #define EADC_AD1SPCTL4_TRGSEL_Pos (4) /*!< EADC AD1SPCTL4: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10406 #define EADC_AD1SPCTL4_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL4_TRGSEL_Pos) /*!< EADC AD1SPCTL4: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10407
<> 144:ef7eb2e8f9f7 10408 #define EADC_AD1SPCTL4_EXTREN_Pos (20) /*!< EADC AD1SPCTL4: EXTREN Position */
<> 144:ef7eb2e8f9f7 10409 #define EADC_AD1SPCTL4_EXTREN_Msk (0x1ul << EADC_AD1SPCTL4_EXTREN_Pos) /*!< EADC AD1SPCTL4: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10410
<> 144:ef7eb2e8f9f7 10411 #define EADC_AD1SPCTL4_EXTFEN_Pos (21) /*!< EADC AD1SPCTL4: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10412 #define EADC_AD1SPCTL4_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL4_EXTFEN_Pos) /*!< EADC AD1SPCTL4: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10413
<> 144:ef7eb2e8f9f7 10414 #define EADC_AD1SPCTL5_CHSEL_Pos (0) /*!< EADC AD1SPCTL5: CHSEL Position */
<> 144:ef7eb2e8f9f7 10415 #define EADC_AD1SPCTL5_CHSEL_Msk (0xful << EADC_AD1SPCTL5_CHSEL_Pos) /*!< EADC AD1SPCTL5: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10416
<> 144:ef7eb2e8f9f7 10417 #define EADC_AD1SPCTL5_TRGSEL_Pos (4) /*!< EADC AD1SPCTL5: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10418 #define EADC_AD1SPCTL5_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL5_TRGSEL_Pos) /*!< EADC AD1SPCTL5: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10419
<> 144:ef7eb2e8f9f7 10420 #define EADC_AD1SPCTL5_EXTREN_Pos (20) /*!< EADC AD1SPCTL5: EXTREN Position */
<> 144:ef7eb2e8f9f7 10421 #define EADC_AD1SPCTL5_EXTREN_Msk (0x1ul << EADC_AD1SPCTL5_EXTREN_Pos) /*!< EADC AD1SPCTL5: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10422
<> 144:ef7eb2e8f9f7 10423 #define EADC_AD1SPCTL5_EXTFEN_Pos (21) /*!< EADC AD1SPCTL5: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10424 #define EADC_AD1SPCTL5_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL5_EXTFEN_Pos) /*!< EADC AD1SPCTL5: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10425
<> 144:ef7eb2e8f9f7 10426 #define EADC_AD1SPCTL6_CHSEL_Pos (0) /*!< EADC AD1SPCTL6: CHSEL Position */
<> 144:ef7eb2e8f9f7 10427 #define EADC_AD1SPCTL6_CHSEL_Msk (0xful << EADC_AD1SPCTL6_CHSEL_Pos) /*!< EADC AD1SPCTL6: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10428
<> 144:ef7eb2e8f9f7 10429 #define EADC_AD1SPCTL6_TRGSEL_Pos (4) /*!< EADC AD1SPCTL6: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10430 #define EADC_AD1SPCTL6_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL6_TRGSEL_Pos) /*!< EADC AD1SPCTL6: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10431
<> 144:ef7eb2e8f9f7 10432 #define EADC_AD1SPCTL6_EXTREN_Pos (20) /*!< EADC AD1SPCTL6: EXTREN Position */
<> 144:ef7eb2e8f9f7 10433 #define EADC_AD1SPCTL6_EXTREN_Msk (0x1ul << EADC_AD1SPCTL6_EXTREN_Pos) /*!< EADC AD1SPCTL6: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10434
<> 144:ef7eb2e8f9f7 10435 #define EADC_AD1SPCTL6_EXTFEN_Pos (21) /*!< EADC AD1SPCTL6: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10436 #define EADC_AD1SPCTL6_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL6_EXTFEN_Pos) /*!< EADC AD1SPCTL6: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10437
<> 144:ef7eb2e8f9f7 10438 #define EADC_AD1SPCTL7_CHSEL_Pos (0) /*!< EADC AD1SPCTL7: CHSEL Position */
<> 144:ef7eb2e8f9f7 10439 #define EADC_AD1SPCTL7_CHSEL_Msk (0xful << EADC_AD1SPCTL7_CHSEL_Pos) /*!< EADC AD1SPCTL7: CHSEL Mask */
<> 144:ef7eb2e8f9f7 10440
<> 144:ef7eb2e8f9f7 10441 #define EADC_AD1SPCTL7_TRGSEL_Pos (4) /*!< EADC AD1SPCTL7: TRGSEL Position */
<> 144:ef7eb2e8f9f7 10442 #define EADC_AD1SPCTL7_TRGSEL_Msk (0x7ul << EADC_AD1SPCTL7_TRGSEL_Pos) /*!< EADC AD1SPCTL7: TRGSEL Mask */
<> 144:ef7eb2e8f9f7 10443
<> 144:ef7eb2e8f9f7 10444 #define EADC_AD1SPCTL7_EXTREN_Pos (20) /*!< EADC AD1SPCTL7: EXTREN Position */
<> 144:ef7eb2e8f9f7 10445 #define EADC_AD1SPCTL7_EXTREN_Msk (0x1ul << EADC_AD1SPCTL7_EXTREN_Pos) /*!< EADC AD1SPCTL7: EXTREN Mask */
<> 144:ef7eb2e8f9f7 10446
<> 144:ef7eb2e8f9f7 10447 #define EADC_AD1SPCTL7_EXTFEN_Pos (21) /*!< EADC AD1SPCTL7: EXTFEN Position */
<> 144:ef7eb2e8f9f7 10448 #define EADC_AD1SPCTL7_EXTFEN_Msk (0x1ul << EADC_AD1SPCTL7_EXTFEN_Pos) /*!< EADC AD1SPCTL7: EXTFEN Mask */
<> 144:ef7eb2e8f9f7 10449
<> 144:ef7eb2e8f9f7 10450 #define EADC_SIMUSEL_SIMUSEL0_Pos (0) /*!< EADC SIMUSEL: SIMUSEL0 Position */
<> 144:ef7eb2e8f9f7 10451 #define EADC_SIMUSEL_SIMUSEL0_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL0_Pos) /*!< EADC SIMUSEL: SIMUSEL0 Mask */
<> 144:ef7eb2e8f9f7 10452
<> 144:ef7eb2e8f9f7 10453 #define EADC_SIMUSEL_SIMUSEL1_Pos (1) /*!< EADC SIMUSEL: SIMUSEL1 Position */
<> 144:ef7eb2e8f9f7 10454 #define EADC_SIMUSEL_SIMUSEL1_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL1_Pos) /*!< EADC SIMUSEL: SIMUSEL1 Mask */
<> 144:ef7eb2e8f9f7 10455
<> 144:ef7eb2e8f9f7 10456 #define EADC_SIMUSEL_SIMUSEL2_Pos (2) /*!< EADC SIMUSEL: SIMUSEL2 Position */
<> 144:ef7eb2e8f9f7 10457 #define EADC_SIMUSEL_SIMUSEL2_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL2_Pos) /*!< EADC SIMUSEL: SIMUSEL2 Mask */
<> 144:ef7eb2e8f9f7 10458
<> 144:ef7eb2e8f9f7 10459 #define EADC_SIMUSEL_SIMUSEL3_Pos (3) /*!< EADC SIMUSEL: SIMUSEL3 Position */
<> 144:ef7eb2e8f9f7 10460 #define EADC_SIMUSEL_SIMUSEL3_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL3_Pos) /*!< EADC SIMUSEL: SIMUSEL3 Mask */
<> 144:ef7eb2e8f9f7 10461
<> 144:ef7eb2e8f9f7 10462 #define EADC_SIMUSEL_SIMUSEL4_Pos (4) /*!< EADC SIMUSEL: SIMUSEL4 Position */
<> 144:ef7eb2e8f9f7 10463 #define EADC_SIMUSEL_SIMUSEL4_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL4_Pos) /*!< EADC SIMUSEL: SIMUSEL4 Mask */
<> 144:ef7eb2e8f9f7 10464
<> 144:ef7eb2e8f9f7 10465 #define EADC_SIMUSEL_SIMUSEL5_Pos (5) /*!< EADC SIMUSEL: SIMUSEL5 Position */
<> 144:ef7eb2e8f9f7 10466 #define EADC_SIMUSEL_SIMUSEL5_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL5_Pos) /*!< EADC SIMUSEL: SIMUSEL5 Mask */
<> 144:ef7eb2e8f9f7 10467
<> 144:ef7eb2e8f9f7 10468 #define EADC_SIMUSEL_SIMUSEL6_Pos (6) /*!< EADC SIMUSEL: SIMUSEL6 Position */
<> 144:ef7eb2e8f9f7 10469 #define EADC_SIMUSEL_SIMUSEL6_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL6_Pos) /*!< EADC SIMUSEL: SIMUSEL6 Mask */
<> 144:ef7eb2e8f9f7 10470
<> 144:ef7eb2e8f9f7 10471 #define EADC_SIMUSEL_SIMUSEL7_Pos (7) /*!< EADC SIMUSEL: SIMUSEL7 Position */
<> 144:ef7eb2e8f9f7 10472 #define EADC_SIMUSEL_SIMUSEL7_Msk (0x1ul << EADC_SIMUSEL_SIMUSEL7_Pos) /*!< EADC SIMUSEL: SIMUSEL7 Mask */
<> 144:ef7eb2e8f9f7 10473
<> 144:ef7eb2e8f9f7 10474 #define EADC_CMP0_ADCMPEN_Pos (0) /*!< EADC CMP0: ADCMPEN Position */
<> 144:ef7eb2e8f9f7 10475 #define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) /*!< EADC CMP0: ADCMPEN Mask */
<> 144:ef7eb2e8f9f7 10476
<> 144:ef7eb2e8f9f7 10477 #define EADC_CMP0_ADCMPIE_Pos (1) /*!< EADC CMP0: ADCMPIE Position */
<> 144:ef7eb2e8f9f7 10478 #define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) /*!< EADC CMP0: ADCMPIE Mask */
<> 144:ef7eb2e8f9f7 10479
<> 144:ef7eb2e8f9f7 10480 #define EADC_CMP0_CMPCOND_Pos (2) /*!< EADC CMP0: CMPCOND Position */
<> 144:ef7eb2e8f9f7 10481 #define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) /*!< EADC CMP0: CMPCOND Mask */
<> 144:ef7eb2e8f9f7 10482
<> 144:ef7eb2e8f9f7 10483 #define EADC_CMP0_CMPSPL_Pos (3) /*!< EADC CMP0: CMPSPL Position */
<> 144:ef7eb2e8f9f7 10484 #define EADC_CMP0_CMPSPL_Msk (0x7ul << EADC_CMP0_CMPSPL_Pos) /*!< EADC CMP0: CMPSPL Mask */
<> 144:ef7eb2e8f9f7 10485
<> 144:ef7eb2e8f9f7 10486 #define EADC_CMP0_CMPMCNT_Pos (8) /*!< EADC CMP0: CMPMCNT Position */
<> 144:ef7eb2e8f9f7 10487 #define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) /*!< EADC CMP0: CMPMCNT Mask */
<> 144:ef7eb2e8f9f7 10488
<> 144:ef7eb2e8f9f7 10489 #define EADC_CMP0_CMPDAT_Pos (16) /*!< EADC CMP0: CMPDAT Position */
<> 144:ef7eb2e8f9f7 10490 #define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) /*!< EADC CMP0: CMPDAT Mask */
<> 144:ef7eb2e8f9f7 10491
<> 144:ef7eb2e8f9f7 10492 #define EADC_CMP1_ADCMPEN_Pos (0) /*!< EADC CMP1: ADCMPEN Position */
<> 144:ef7eb2e8f9f7 10493 #define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) /*!< EADC CMP1: ADCMPEN Mask */
<> 144:ef7eb2e8f9f7 10494
<> 144:ef7eb2e8f9f7 10495 #define EADC_CMP1_ADCMPIE_Pos (1) /*!< EADC CMP1: ADCMPIE Position */
<> 144:ef7eb2e8f9f7 10496 #define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) /*!< EADC CMP1: ADCMPIE Mask */
<> 144:ef7eb2e8f9f7 10497
<> 144:ef7eb2e8f9f7 10498 #define EADC_CMP1_CMPCOND_Pos (2) /*!< EADC CMP1: CMPCOND Position */
<> 144:ef7eb2e8f9f7 10499 #define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) /*!< EADC CMP1: CMPCOND Mask */
<> 144:ef7eb2e8f9f7 10500
<> 144:ef7eb2e8f9f7 10501 #define EADC_CMP1_CMPSPL_Pos (3) /*!< EADC CMP1: CMPSPL Position */
<> 144:ef7eb2e8f9f7 10502 #define EADC_CMP1_CMPSPL_Msk (0x7ul << EADC_CMP1_CMPSPL_Pos) /*!< EADC CMP1: CMPSPL Mask */
<> 144:ef7eb2e8f9f7 10503
<> 144:ef7eb2e8f9f7 10504 #define EADC_CMP1_CMPMCNT_Pos (8) /*!< EADC CMP1: CMPMCNT Position */
<> 144:ef7eb2e8f9f7 10505 #define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) /*!< EADC CMP1: CMPMCNT Mask */
<> 144:ef7eb2e8f9f7 10506
<> 144:ef7eb2e8f9f7 10507 #define EADC_CMP1_CMPDAT_Pos (16) /*!< EADC CMP1: CMPDAT Position */
<> 144:ef7eb2e8f9f7 10508 #define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) /*!< EADC CMP1: CMPDAT Mask */
<> 144:ef7eb2e8f9f7 10509
<> 144:ef7eb2e8f9f7 10510 #define EADC_STATUS0_VALID_Pos (0) /*!< EADC STATUS0: VALID Position */
<> 144:ef7eb2e8f9f7 10511 #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) /*!< EADC STATUS0: VALID Mask */
<> 144:ef7eb2e8f9f7 10512
<> 144:ef7eb2e8f9f7 10513 #define EADC_STATUS0_OV_Pos (16) /*!< EADC STATUS0: OV Position */
<> 144:ef7eb2e8f9f7 10514 #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) /*!< EADC STATUS0: OV Mask */
<> 144:ef7eb2e8f9f7 10515
<> 144:ef7eb2e8f9f7 10516 #define EADC_STATUS1_ADIF0_Pos (0) /*!< EADC STATUS1: ADIF0 Position */
<> 144:ef7eb2e8f9f7 10517 #define EADC_STATUS1_ADIF0_Msk (0x1ul << EADC_STATUS1_ADIF0_Pos) /*!< EADC STATUS1: ADIF0 Mask */
<> 144:ef7eb2e8f9f7 10518
<> 144:ef7eb2e8f9f7 10519 #define EADC_STATUS1_ADIF1_Pos (1) /*!< EADC STATUS1: ADIF1 Position */
<> 144:ef7eb2e8f9f7 10520 #define EADC_STATUS1_ADIF1_Msk (0x1ul << EADC_STATUS1_ADIF1_Pos) /*!< EADC STATUS1: ADIF1 Mask */
<> 144:ef7eb2e8f9f7 10521
<> 144:ef7eb2e8f9f7 10522 #define EADC_STATUS1_ADIF2_Pos (2) /*!< EADC STATUS1: ADIF2 Position */
<> 144:ef7eb2e8f9f7 10523 #define EADC_STATUS1_ADIF2_Msk (0x1ul << EADC_STATUS1_ADIF2_Pos) /*!< EADC STATUS1: ADIF2 Mask */
<> 144:ef7eb2e8f9f7 10524
<> 144:ef7eb2e8f9f7 10525 #define EADC_STATUS1_ADIF3_Pos (3) /*!< EADC STATUS1: ADIF3 Position */
<> 144:ef7eb2e8f9f7 10526 #define EADC_STATUS1_ADIF3_Msk (0x1ul << EADC_STATUS1_ADIF3_Pos) /*!< EADC STATUS1: ADIF3 Mask */
<> 144:ef7eb2e8f9f7 10527
<> 144:ef7eb2e8f9f7 10528 #define EADC_STATUS1_ADCMPO0_Pos (4) /*!< EADC STATUS1: ADCMPO0 Position */
<> 144:ef7eb2e8f9f7 10529 #define EADC_STATUS1_ADCMPO0_Msk (0x1ul << EADC_STATUS1_ADCMPO0_Pos) /*!< EADC STATUS1: ADCMPO0 Mask */
<> 144:ef7eb2e8f9f7 10530
<> 144:ef7eb2e8f9f7 10531 #define EADC_STATUS1_ADCMPO1_Pos (5) /*!< EADC STATUS1: ADCMPO1 Position */
<> 144:ef7eb2e8f9f7 10532 #define EADC_STATUS1_ADCMPO1_Msk (0x1ul << EADC_STATUS1_ADCMPO1_Pos) /*!< EADC STATUS1: ADCMPO1 Mask */
<> 144:ef7eb2e8f9f7 10533
<> 144:ef7eb2e8f9f7 10534 #define EADC_STATUS1_ADCMPF0_Pos (6) /*!< EADC STATUS1: ADCMPF0 Position */
<> 144:ef7eb2e8f9f7 10535 #define EADC_STATUS1_ADCMPF0_Msk (0x1ul << EADC_STATUS1_ADCMPF0_Pos) /*!< EADC STATUS1: ADCMPF0 Mask */
<> 144:ef7eb2e8f9f7 10536
<> 144:ef7eb2e8f9f7 10537 #define EADC_STATUS1_ADCMPF1_Pos (7) /*!< EADC STATUS1: ADCMPF1 Position */
<> 144:ef7eb2e8f9f7 10538 #define EADC_STATUS1_ADCMPF1_Msk (0x1ul << EADC_STATUS1_ADCMPF1_Pos) /*!< EADC STATUS1: ADCMPF1 Mask */
<> 144:ef7eb2e8f9f7 10539
<> 144:ef7eb2e8f9f7 10540 #define EADC_STATUS1_BUSY0_Pos (8) /*!< EADC STATUS1: BUSY0 Position */
<> 144:ef7eb2e8f9f7 10541 #define EADC_STATUS1_BUSY0_Msk (0x1ul << EADC_STATUS1_BUSY0_Pos) /*!< EADC STATUS1: BUSY0 Mask */
<> 144:ef7eb2e8f9f7 10542
<> 144:ef7eb2e8f9f7 10543 #define EADC_STATUS1_CHANNEL0_Pos (12) /*!< EADC STATUS1: CHANNEL0 Position */
<> 144:ef7eb2e8f9f7 10544 #define EADC_STATUS1_CHANNEL0_Msk (0xful << EADC_STATUS1_CHANNEL0_Pos) /*!< EADC STATUS1: CHANNEL0 Mask */
<> 144:ef7eb2e8f9f7 10545
<> 144:ef7eb2e8f9f7 10546 #define EADC_STATUS1_BUSY1_Pos (16) /*!< EADC STATUS1: BUSY1 Position */
<> 144:ef7eb2e8f9f7 10547 #define EADC_STATUS1_BUSY1_Msk (0x1ul << EADC_STATUS1_BUSY1_Pos) /*!< EADC STATUS1: BUSY1 Mask */
<> 144:ef7eb2e8f9f7 10548
<> 144:ef7eb2e8f9f7 10549 #define EADC_STATUS1_CHANNEL1_Pos (20) /*!< EADC STATUS1: CHANNEL1 Position */
<> 144:ef7eb2e8f9f7 10550 #define EADC_STATUS1_CHANNEL1_Msk (0xful << EADC_STATUS1_CHANNEL1_Pos) /*!< EADC STATUS1: CHANNEL1 Mask */
<> 144:ef7eb2e8f9f7 10551
<> 144:ef7eb2e8f9f7 10552 #define EADC_STATUS1_ADOVIF_Pos (24) /*!< EADC STATUS1: ADOVIF Position */
<> 144:ef7eb2e8f9f7 10553 #define EADC_STATUS1_ADOVIF_Msk (0x1ul << EADC_STATUS1_ADOVIF_Pos) /*!< EADC STATUS1: ADOVIF Mask */
<> 144:ef7eb2e8f9f7 10554
<> 144:ef7eb2e8f9f7 10555 #define EADC_STATUS1_STOVF_Pos (25) /*!< EADC STATUS1: STOVF Position */
<> 144:ef7eb2e8f9f7 10556 #define EADC_STATUS1_STOVF_Msk (0x1ul << EADC_STATUS1_STOVF_Pos) /*!< EADC STATUS1: STOVF Mask */
<> 144:ef7eb2e8f9f7 10557
<> 144:ef7eb2e8f9f7 10558 #define EADC_STATUS1_AVALID_Pos (26) /*!< EADC STATUS1: AVALID Position */
<> 144:ef7eb2e8f9f7 10559 #define EADC_STATUS1_AVALID_Msk (0x1ul << EADC_STATUS1_AVALID_Pos) /*!< EADC STATUS1: AVALID Mask */
<> 144:ef7eb2e8f9f7 10560
<> 144:ef7eb2e8f9f7 10561 #define EADC_STATUS1_AOV_Pos (27) /*!< EADC STATUS1: AOV Position */
<> 144:ef7eb2e8f9f7 10562 #define EADC_STATUS1_AOV_Msk (0x1ul << EADC_STATUS1_AOV_Pos) /*!< EADC STATUS1: AOV Mask */
<> 144:ef7eb2e8f9f7 10563
<> 144:ef7eb2e8f9f7 10564 #define EADC_EXTSMPT_EXTSMPT0_Pos (0) /*!< EADC EXTSMPT: EXTSMPT0 Position */
<> 144:ef7eb2e8f9f7 10565 #define EADC_EXTSMPT_EXTSMPT0_Msk (0xfful << EADC_EXTSMPT_EXTSMPT0_Pos) /*!< EADC EXTSMPT: EXTSMPT0 Mask */
<> 144:ef7eb2e8f9f7 10566
<> 144:ef7eb2e8f9f7 10567 #define EADC_EXTSMPT_EXTSMPT1_Pos (16) /*!< EADC EXTSMPT: EXTSMPT1 Position */
<> 144:ef7eb2e8f9f7 10568 #define EADC_EXTSMPT_EXTSMPT1_Msk (0xfful << EADC_EXTSMPT_EXTSMPT1_Pos) /*!< EADC EXTSMPT: EXTSMPT1 Mask */
<> 144:ef7eb2e8f9f7 10569
<> 144:ef7eb2e8f9f7 10570 #define EADC_AD0DDAT0_RESULT_Pos (0) /*!< EADC AD0DDAT0: RESULT Position */
<> 144:ef7eb2e8f9f7 10571 #define EADC_AD0DDAT0_RESULT_Msk (0xffful << EADC_AD0DDAT0_RESULT_Pos) /*!< EADC AD0DDAT0: RESULT Mask */
<> 144:ef7eb2e8f9f7 10572
<> 144:ef7eb2e8f9f7 10573 #define EADC_AD0DDAT0_VALID_Pos (16) /*!< EADC AD0DDAT0: VALID Position */
<> 144:ef7eb2e8f9f7 10574 #define EADC_AD0DDAT0_VALID_Msk (0x1ul << EADC_AD0DDAT0_VALID_Pos) /*!< EADC AD0DDAT0: VALID Mask */
<> 144:ef7eb2e8f9f7 10575
<> 144:ef7eb2e8f9f7 10576 #define EADC_AD0DDAT1_RESULT_Pos (0) /*!< EADC AD0DDAT1: RESULT Position */
<> 144:ef7eb2e8f9f7 10577 #define EADC_AD0DDAT1_RESULT_Msk (0xffful << EADC_AD0DDAT1_RESULT_Pos) /*!< EADC AD0DDAT1: RESULT Mask */
<> 144:ef7eb2e8f9f7 10578
<> 144:ef7eb2e8f9f7 10579 #define EADC_AD0DDAT1_VALID_Pos (16) /*!< EADC AD0DDAT1: VALID Position */
<> 144:ef7eb2e8f9f7 10580 #define EADC_AD0DDAT1_VALID_Msk (0x1ul << EADC_AD0DDAT1_VALID_Pos) /*!< EADC AD0DDAT1: VALID Mask */
<> 144:ef7eb2e8f9f7 10581
<> 144:ef7eb2e8f9f7 10582 #define EADC_AD0DDAT2_RESULT_Pos (0) /*!< EADC AD0DDAT2: RESULT Position */
<> 144:ef7eb2e8f9f7 10583 #define EADC_AD0DDAT2_RESULT_Msk (0xffful << EADC_AD0DDAT2_RESULT_Pos) /*!< EADC AD0DDAT2: RESULT Mask */
<> 144:ef7eb2e8f9f7 10584
<> 144:ef7eb2e8f9f7 10585 #define EADC_AD0DDAT2_VALID_Pos (16) /*!< EADC AD0DDAT2: VALID Position */
<> 144:ef7eb2e8f9f7 10586 #define EADC_AD0DDAT2_VALID_Msk (0x1ul << EADC_AD0DDAT2_VALID_Pos) /*!< EADC AD0DDAT2: VALID Mask */
<> 144:ef7eb2e8f9f7 10587
<> 144:ef7eb2e8f9f7 10588 #define EADC_AD0DDAT3_RESULT_Pos (0) /*!< EADC AD0DDAT3: RESULT Position */
<> 144:ef7eb2e8f9f7 10589 #define EADC_AD0DDAT3_RESULT_Msk (0xffful << EADC_AD0DDAT3_RESULT_Pos) /*!< EADC AD0DDAT3: RESULT Mask */
<> 144:ef7eb2e8f9f7 10590
<> 144:ef7eb2e8f9f7 10591 #define EADC_AD0DDAT3_VALID_Pos (16) /*!< EADC AD0DDAT3: VALID Position */
<> 144:ef7eb2e8f9f7 10592 #define EADC_AD0DDAT3_VALID_Msk (0x1ul << EADC_AD0DDAT3_VALID_Pos) /*!< EADC AD0DDAT3: VALID Mask */
<> 144:ef7eb2e8f9f7 10593
<> 144:ef7eb2e8f9f7 10594 #define EADC_AD1DDAT0_RESULT_Pos (0) /*!< EADC AD1DDAT0: RESULT Position */
<> 144:ef7eb2e8f9f7 10595 #define EADC_AD1DDAT0_RESULT_Msk (0xffful << EADC_AD1DDAT0_RESULT_Pos) /*!< EADC AD1DDAT0: RESULT Mask */
<> 144:ef7eb2e8f9f7 10596
<> 144:ef7eb2e8f9f7 10597 #define EADC_AD1DDAT0_VALID_Pos (16) /*!< EADC AD1DDAT0: VALID Position */
<> 144:ef7eb2e8f9f7 10598 #define EADC_AD1DDAT0_VALID_Msk (0x1ul << EADC_AD1DDAT0_VALID_Pos) /*!< EADC AD1DDAT0: VALID Mask */
<> 144:ef7eb2e8f9f7 10599
<> 144:ef7eb2e8f9f7 10600 #define EADC_AD1DDAT1_RESULT_Pos (0) /*!< EADC AD1DDAT1: RESULT Position */
<> 144:ef7eb2e8f9f7 10601 #define EADC_AD1DDAT1_RESULT_Msk (0xffful << EADC_AD1DDAT1_RESULT_Pos) /*!< EADC AD1DDAT1: RESULT Mask */
<> 144:ef7eb2e8f9f7 10602
<> 144:ef7eb2e8f9f7 10603 #define EADC_AD1DDAT1_VALID_Pos (16) /*!< EADC AD1DDAT1: VALID Position */
<> 144:ef7eb2e8f9f7 10604 #define EADC_AD1DDAT1_VALID_Msk (0x1ul << EADC_AD1DDAT1_VALID_Pos) /*!< EADC AD1DDAT1: VALID Mask */
<> 144:ef7eb2e8f9f7 10605
<> 144:ef7eb2e8f9f7 10606 #define EADC_AD1DDAT2_RESULT_Pos (0) /*!< EADC AD1DDAT2: RESULT Position */
<> 144:ef7eb2e8f9f7 10607 #define EADC_AD1DDAT2_RESULT_Msk (0xffful << EADC_AD1DDAT2_RESULT_Pos) /*!< EADC AD1DDAT2: RESULT Mask */
<> 144:ef7eb2e8f9f7 10608
<> 144:ef7eb2e8f9f7 10609 #define EADC_AD1DDAT2_VALID_Pos (16) /*!< EADC AD1DDAT2: VALID Position */
<> 144:ef7eb2e8f9f7 10610 #define EADC_AD1DDAT2_VALID_Msk (0x1ul << EADC_AD1DDAT2_VALID_Pos) /*!< EADC AD1DDAT2: VALID Mask */
<> 144:ef7eb2e8f9f7 10611
<> 144:ef7eb2e8f9f7 10612 #define EADC_AD1DDAT3_RESULT_Pos (0) /*!< EADC AD1DDAT3: RESULT Position */
<> 144:ef7eb2e8f9f7 10613 #define EADC_AD1DDAT3_RESULT_Msk (0xffful << EADC_AD1DDAT3_RESULT_Pos) /*!< EADC AD1DDAT3: RESULT Mask */
<> 144:ef7eb2e8f9f7 10614
<> 144:ef7eb2e8f9f7 10615 #define EADC_AD1DDAT3_VALID_Pos (16) /*!< EADC AD1DDAT3: VALID Position */
<> 144:ef7eb2e8f9f7 10616 #define EADC_AD1DDAT3_VALID_Msk (0x1ul << EADC_AD1DDAT3_VALID_Pos) /*!< EADC AD1DDAT3: VALID Mask */
<> 144:ef7eb2e8f9f7 10617
<> 144:ef7eb2e8f9f7 10618 #define EADC_DBMEN_AD0DBM0_Pos (0) /*!< EADC DBMEN: AD0DBM0 Position */
<> 144:ef7eb2e8f9f7 10619 #define EADC_DBMEN_AD0DBM0_Msk (0x1ul << EADC_DBMEN_AD0DBM0_Pos) /*!< EADC DBMEN: AD0DBM0 Mask */
<> 144:ef7eb2e8f9f7 10620
<> 144:ef7eb2e8f9f7 10621 #define EADC_DBMEN_AD0DBM1_Pos (1) /*!< EADC DBMEN: AD0DBM1 Position */
<> 144:ef7eb2e8f9f7 10622 #define EADC_DBMEN_AD0DBM1_Msk (0x1ul << EADC_DBMEN_AD0DBM1_Pos) /*!< EADC DBMEN: AD0DBM1 Mask */
<> 144:ef7eb2e8f9f7 10623
<> 144:ef7eb2e8f9f7 10624 #define EADC_DBMEN_AD0DBM2_Pos (2) /*!< EADC DBMEN: AD0DBM2 Position */
<> 144:ef7eb2e8f9f7 10625 #define EADC_DBMEN_AD0DBM2_Msk (0x1ul << EADC_DBMEN_AD0DBM2_Pos) /*!< EADC DBMEN: AD0DBM2 Mask */
<> 144:ef7eb2e8f9f7 10626
<> 144:ef7eb2e8f9f7 10627 #define EADC_DBMEN_AD0DBM3_Pos (3) /*!< EADC DBMEN: AD0DBM3 Position */
<> 144:ef7eb2e8f9f7 10628 #define EADC_DBMEN_AD0DBM3_Msk (0x1ul << EADC_DBMEN_AD0DBM3_Pos) /*!< EADC DBMEN: AD0DBM3 Mask */
<> 144:ef7eb2e8f9f7 10629
<> 144:ef7eb2e8f9f7 10630 #define EADC_DBMEN_AD1DBM0_Pos (8) /*!< EADC DBMEN: AD1DBM0 Position */
<> 144:ef7eb2e8f9f7 10631 #define EADC_DBMEN_AD1DBM0_Msk (0x1ul << EADC_DBMEN_AD1DBM0_Pos) /*!< EADC DBMEN: AD1DBM0 Mask */
<> 144:ef7eb2e8f9f7 10632
<> 144:ef7eb2e8f9f7 10633 #define EADC_DBMEN_AD1DBM1_Pos (9) /*!< EADC DBMEN: AD1DBM1 Position */
<> 144:ef7eb2e8f9f7 10634 #define EADC_DBMEN_AD1DBM1_Msk (0x1ul << EADC_DBMEN_AD1DBM1_Pos) /*!< EADC DBMEN: AD1DBM1 Mask */
<> 144:ef7eb2e8f9f7 10635
<> 144:ef7eb2e8f9f7 10636 #define EADC_DBMEN_AD1DBM2_Pos (10) /*!< EADC DBMEN: AD1DBM2 Position */
<> 144:ef7eb2e8f9f7 10637 #define EADC_DBMEN_AD1DBM2_Msk (0x1ul << EADC_DBMEN_AD1DBM2_Pos) /*!< EADC DBMEN: AD1DBM2 Mask */
<> 144:ef7eb2e8f9f7 10638
<> 144:ef7eb2e8f9f7 10639 #define EADC_DBMEN_AD1DBM3_Pos (11) /*!< EADC DBMEN: AD1DBM3 Position */
<> 144:ef7eb2e8f9f7 10640 #define EADC_DBMEN_AD1DBM3_Msk (0x1ul << EADC_DBMEN_AD1DBM3_Pos) /*!< EADC DBMEN: AD1DBM3 Mask */
<> 144:ef7eb2e8f9f7 10641
<> 144:ef7eb2e8f9f7 10642 #define EADC_INTSRC0_AD0SPIE0_Pos (0) /*!< EADC INTSRC0: AD0SPIE0 Position */
<> 144:ef7eb2e8f9f7 10643 #define EADC_INTSRC0_AD0SPIE0_Msk (0x1ul << EADC_INTSRC0_AD0SPIE0_Pos) /*!< EADC INTSRC0: AD0SPIE0 Mask */
<> 144:ef7eb2e8f9f7 10644
<> 144:ef7eb2e8f9f7 10645 #define EADC_INTSRC0_AD0SPIE1_Pos (1) /*!< EADC INTSRC0: AD0SPIE1 Position */
<> 144:ef7eb2e8f9f7 10646 #define EADC_INTSRC0_AD0SPIE1_Msk (0x1ul << EADC_INTSRC0_AD0SPIE1_Pos) /*!< EADC INTSRC0: AD0SPIE1 Mask */
<> 144:ef7eb2e8f9f7 10647
<> 144:ef7eb2e8f9f7 10648 #define EADC_INTSRC0_AD0SPIE2_Pos (2) /*!< EADC INTSRC0: AD0SPIE2 Position */
<> 144:ef7eb2e8f9f7 10649 #define EADC_INTSRC0_AD0SPIE2_Msk (0x1ul << EADC_INTSRC0_AD0SPIE2_Pos) /*!< EADC INTSRC0: AD0SPIE2 Mask */
<> 144:ef7eb2e8f9f7 10650
<> 144:ef7eb2e8f9f7 10651 #define EADC_INTSRC0_AD0SPIE3_Pos (3) /*!< EADC INTSRC0: AD0SPIE3 Position */
<> 144:ef7eb2e8f9f7 10652 #define EADC_INTSRC0_AD0SPIE3_Msk (0x1ul << EADC_INTSRC0_AD0SPIE3_Pos) /*!< EADC INTSRC0: AD0SPIE3 Mask */
<> 144:ef7eb2e8f9f7 10653
<> 144:ef7eb2e8f9f7 10654 #define EADC_INTSRC0_AD0SPIE4_Pos (4) /*!< EADC INTSRC0: AD0SPIE4 Position */
<> 144:ef7eb2e8f9f7 10655 #define EADC_INTSRC0_AD0SPIE4_Msk (0x1ul << EADC_INTSRC0_AD0SPIE4_Pos) /*!< EADC INTSRC0: AD0SPIE4 Mask */
<> 144:ef7eb2e8f9f7 10656
<> 144:ef7eb2e8f9f7 10657 #define EADC_INTSRC0_AD0SPIE5_Pos (5) /*!< EADC INTSRC0: AD0SPIE5 Position */
<> 144:ef7eb2e8f9f7 10658 #define EADC_INTSRC0_AD0SPIE5_Msk (0x1ul << EADC_INTSRC0_AD0SPIE5_Pos) /*!< EADC INTSRC0: AD0SPIE5 Mask */
<> 144:ef7eb2e8f9f7 10659
<> 144:ef7eb2e8f9f7 10660 #define EADC_INTSRC0_AD0SPIE6_Pos (6) /*!< EADC INTSRC0: AD0SPIE6 Position */
<> 144:ef7eb2e8f9f7 10661 #define EADC_INTSRC0_AD0SPIE6_Msk (0x1ul << EADC_INTSRC0_AD0SPIE6_Pos) /*!< EADC INTSRC0: AD0SPIE6 Mask */
<> 144:ef7eb2e8f9f7 10662
<> 144:ef7eb2e8f9f7 10663 #define EADC_INTSRC0_AD0SPIE7_Pos (7) /*!< EADC INTSRC0: AD0SPIE7 Position */
<> 144:ef7eb2e8f9f7 10664 #define EADC_INTSRC0_AD0SPIE7_Msk (0x1ul << EADC_INTSRC0_AD0SPIE7_Pos) /*!< EADC INTSRC0: AD0SPIE7 Mask */
<> 144:ef7eb2e8f9f7 10665
<> 144:ef7eb2e8f9f7 10666 #define EADC_INTSRC0_AD1SPIE0_Pos (8) /*!< EADC INTSRC0: AD1SPIE0 Position */
<> 144:ef7eb2e8f9f7 10667 #define EADC_INTSRC0_AD1SPIE0_Msk (0x1ul << EADC_INTSRC0_AD1SPIE0_Pos) /*!< EADC INTSRC0: AD1SPIE0 Mask */
<> 144:ef7eb2e8f9f7 10668
<> 144:ef7eb2e8f9f7 10669 #define EADC_INTSRC0_AD1SPIE1_Pos (9) /*!< EADC INTSRC0: AD1SPIE1 Position */
<> 144:ef7eb2e8f9f7 10670 #define EADC_INTSRC0_AD1SPIE1_Msk (0x1ul << EADC_INTSRC0_AD1SPIE1_Pos) /*!< EADC INTSRC0: AD1SPIE1 Mask */
<> 144:ef7eb2e8f9f7 10671
<> 144:ef7eb2e8f9f7 10672 #define EADC_INTSRC0_AD1SPIE2_Pos (10) /*!< EADC INTSRC0: AD1SPIE2 Position */
<> 144:ef7eb2e8f9f7 10673 #define EADC_INTSRC0_AD1SPIE2_Msk (0x1ul << EADC_INTSRC0_AD1SPIE2_Pos) /*!< EADC INTSRC0: AD1SPIE2 Mask */
<> 144:ef7eb2e8f9f7 10674
<> 144:ef7eb2e8f9f7 10675 #define EADC_INTSRC0_AD1SPIE3_Pos (11) /*!< EADC INTSRC0: AD1SPIE3 Position */
<> 144:ef7eb2e8f9f7 10676 #define EADC_INTSRC0_AD1SPIE3_Msk (0x1ul << EADC_INTSRC0_AD1SPIE3_Pos) /*!< EADC INTSRC0: AD1SPIE3 Mask */
<> 144:ef7eb2e8f9f7 10677
<> 144:ef7eb2e8f9f7 10678 #define EADC_INTSRC0_AD1SPIE4_Pos (12) /*!< EADC INTSRC0: AD1SPIE4 Position */
<> 144:ef7eb2e8f9f7 10679 #define EADC_INTSRC0_AD1SPIE4_Msk (0x1ul << EADC_INTSRC0_AD1SPIE4_Pos) /*!< EADC INTSRC0: AD1SPIE4 Mask */
<> 144:ef7eb2e8f9f7 10680
<> 144:ef7eb2e8f9f7 10681 #define EADC_INTSRC0_AD1SPIE5_Pos (13) /*!< EADC INTSRC0: AD1SPIE5 Position */
<> 144:ef7eb2e8f9f7 10682 #define EADC_INTSRC0_AD1SPIE5_Msk (0x1ul << EADC_INTSRC0_AD1SPIE5_Pos) /*!< EADC INTSRC0: AD1SPIE5 Mask */
<> 144:ef7eb2e8f9f7 10683
<> 144:ef7eb2e8f9f7 10684 #define EADC_INTSRC0_AD1SPIE6_Pos (14) /*!< EADC INTSRC0: AD1SPIE6 Position */
<> 144:ef7eb2e8f9f7 10685 #define EADC_INTSRC0_AD1SPIE6_Msk (0x1ul << EADC_INTSRC0_AD1SPIE6_Pos) /*!< EADC INTSRC0: AD1SPIE6 Mask */
<> 144:ef7eb2e8f9f7 10686
<> 144:ef7eb2e8f9f7 10687 #define EADC_INTSRC0_AD1SPIE7_Pos (15) /*!< EADC INTSRC0: AD1SPIE7 Position */
<> 144:ef7eb2e8f9f7 10688 #define EADC_INTSRC0_AD1SPIE7_Msk (0x1ul << EADC_INTSRC0_AD1SPIE7_Pos) /*!< EADC INTSRC0: AD1SPIE7 Mask */
<> 144:ef7eb2e8f9f7 10689
<> 144:ef7eb2e8f9f7 10690 #define EADC_INTSRC1_AD0SPIE0_Pos (0) /*!< EADC INTSRC1: AD0SPIE0 Position */
<> 144:ef7eb2e8f9f7 10691 #define EADC_INTSRC1_AD0SPIE0_Msk (0x1ul << EADC_INTSRC1_AD0SPIE0_Pos) /*!< EADC INTSRC1: AD0SPIE0 Mask */
<> 144:ef7eb2e8f9f7 10692
<> 144:ef7eb2e8f9f7 10693 #define EADC_INTSRC1_AD0SPIE1_Pos (1) /*!< EADC INTSRC1: AD0SPIE1 Position */
<> 144:ef7eb2e8f9f7 10694 #define EADC_INTSRC1_AD0SPIE1_Msk (0x1ul << EADC_INTSRC1_AD0SPIE1_Pos) /*!< EADC INTSRC1: AD0SPIE1 Mask */
<> 144:ef7eb2e8f9f7 10695
<> 144:ef7eb2e8f9f7 10696 #define EADC_INTSRC1_AD0SPIE2_Pos (2) /*!< EADC INTSRC1: AD0SPIE2 Position */
<> 144:ef7eb2e8f9f7 10697 #define EADC_INTSRC1_AD0SPIE2_Msk (0x1ul << EADC_INTSRC1_AD0SPIE2_Pos) /*!< EADC INTSRC1: AD0SPIE2 Mask */
<> 144:ef7eb2e8f9f7 10698
<> 144:ef7eb2e8f9f7 10699 #define EADC_INTSRC1_AD0SPIE3_Pos (3) /*!< EADC INTSRC1: AD0SPIE3 Position */
<> 144:ef7eb2e8f9f7 10700 #define EADC_INTSRC1_AD0SPIE3_Msk (0x1ul << EADC_INTSRC1_AD0SPIE3_Pos) /*!< EADC INTSRC1: AD0SPIE3 Mask */
<> 144:ef7eb2e8f9f7 10701
<> 144:ef7eb2e8f9f7 10702 #define EADC_INTSRC1_AD0SPIE4_Pos (4) /*!< EADC INTSRC1: AD0SPIE4 Position */
<> 144:ef7eb2e8f9f7 10703 #define EADC_INTSRC1_AD0SPIE4_Msk (0x1ul << EADC_INTSRC1_AD0SPIE4_Pos) /*!< EADC INTSRC1: AD0SPIE4 Mask */
<> 144:ef7eb2e8f9f7 10704
<> 144:ef7eb2e8f9f7 10705 #define EADC_INTSRC1_AD0SPIE5_Pos (5) /*!< EADC INTSRC1: AD0SPIE5 Position */
<> 144:ef7eb2e8f9f7 10706 #define EADC_INTSRC1_AD0SPIE5_Msk (0x1ul << EADC_INTSRC1_AD0SPIE5_Pos) /*!< EADC INTSRC1: AD0SPIE5 Mask */
<> 144:ef7eb2e8f9f7 10707
<> 144:ef7eb2e8f9f7 10708 #define EADC_INTSRC1_AD0SPIE6_Pos (6) /*!< EADC INTSRC1: AD0SPIE6 Position */
<> 144:ef7eb2e8f9f7 10709 #define EADC_INTSRC1_AD0SPIE6_Msk (0x1ul << EADC_INTSRC1_AD0SPIE6_Pos) /*!< EADC INTSRC1: AD0SPIE6 Mask */
<> 144:ef7eb2e8f9f7 10710
<> 144:ef7eb2e8f9f7 10711 #define EADC_INTSRC1_AD0SPIE7_Pos (7) /*!< EADC INTSRC1: AD0SPIE7 Position */
<> 144:ef7eb2e8f9f7 10712 #define EADC_INTSRC1_AD0SPIE7_Msk (0x1ul << EADC_INTSRC1_AD0SPIE7_Pos) /*!< EADC INTSRC1: AD0SPIE7 Mask */
<> 144:ef7eb2e8f9f7 10713
<> 144:ef7eb2e8f9f7 10714 #define EADC_INTSRC1_AD1SPIE0_Pos (8) /*!< EADC INTSRC1: AD1SPIE0 Position */
<> 144:ef7eb2e8f9f7 10715 #define EADC_INTSRC1_AD1SPIE0_Msk (0x1ul << EADC_INTSRC1_AD1SPIE0_Pos) /*!< EADC INTSRC1: AD1SPIE0 Mask */
<> 144:ef7eb2e8f9f7 10716
<> 144:ef7eb2e8f9f7 10717 #define EADC_INTSRC1_AD1SPIE1_Pos (9) /*!< EADC INTSRC1: AD1SPIE1 Position */
<> 144:ef7eb2e8f9f7 10718 #define EADC_INTSRC1_AD1SPIE1_Msk (0x1ul << EADC_INTSRC1_AD1SPIE1_Pos) /*!< EADC INTSRC1: AD1SPIE1 Mask */
<> 144:ef7eb2e8f9f7 10719
<> 144:ef7eb2e8f9f7 10720 #define EADC_INTSRC1_AD1SPIE2_Pos (10) /*!< EADC INTSRC1: AD1SPIE2 Position */
<> 144:ef7eb2e8f9f7 10721 #define EADC_INTSRC1_AD1SPIE2_Msk (0x1ul << EADC_INTSRC1_AD1SPIE2_Pos) /*!< EADC INTSRC1: AD1SPIE2 Mask */
<> 144:ef7eb2e8f9f7 10722
<> 144:ef7eb2e8f9f7 10723 #define EADC_INTSRC1_AD1SPIE3_Pos (11) /*!< EADC INTSRC1: AD1SPIE3 Position */
<> 144:ef7eb2e8f9f7 10724 #define EADC_INTSRC1_AD1SPIE3_Msk (0x1ul << EADC_INTSRC1_AD1SPIE3_Pos) /*!< EADC INTSRC1: AD1SPIE3 Mask */
<> 144:ef7eb2e8f9f7 10725
<> 144:ef7eb2e8f9f7 10726 #define EADC_INTSRC1_AD1SPIE4_Pos (12) /*!< EADC INTSRC1: AD1SPIE4 Position */
<> 144:ef7eb2e8f9f7 10727 #define EADC_INTSRC1_AD1SPIE4_Msk (0x1ul << EADC_INTSRC1_AD1SPIE4_Pos) /*!< EADC INTSRC1: AD1SPIE4 Mask */
<> 144:ef7eb2e8f9f7 10728
<> 144:ef7eb2e8f9f7 10729 #define EADC_INTSRC1_AD1SPIE5_Pos (13) /*!< EADC INTSRC1: AD1SPIE5 Position */
<> 144:ef7eb2e8f9f7 10730 #define EADC_INTSRC1_AD1SPIE5_Msk (0x1ul << EADC_INTSRC1_AD1SPIE5_Pos) /*!< EADC INTSRC1: AD1SPIE5 Mask */
<> 144:ef7eb2e8f9f7 10731
<> 144:ef7eb2e8f9f7 10732 #define EADC_INTSRC1_AD1SPIE6_Pos (14) /*!< EADC INTSRC1: AD1SPIE6 Position */
<> 144:ef7eb2e8f9f7 10733 #define EADC_INTSRC1_AD1SPIE6_Msk (0x1ul << EADC_INTSRC1_AD1SPIE6_Pos) /*!< EADC INTSRC1: AD1SPIE6 Mask */
<> 144:ef7eb2e8f9f7 10734
<> 144:ef7eb2e8f9f7 10735 #define EADC_INTSRC1_AD1SPIE7_Pos (15) /*!< EADC INTSRC1: AD1SPIE7 Position */
<> 144:ef7eb2e8f9f7 10736 #define EADC_INTSRC1_AD1SPIE7_Msk (0x1ul << EADC_INTSRC1_AD1SPIE7_Pos) /*!< EADC INTSRC1: AD1SPIE7 Mask */
<> 144:ef7eb2e8f9f7 10737
<> 144:ef7eb2e8f9f7 10738 #define EADC_INTSRC2_AD0SPIE0_Pos (0) /*!< EADC INTSRC2: AD0SPIE0 Position */
<> 144:ef7eb2e8f9f7 10739 #define EADC_INTSRC2_AD0SPIE0_Msk (0x1ul << EADC_INTSRC2_AD0SPIE0_Pos) /*!< EADC INTSRC2: AD0SPIE0 Mask */
<> 144:ef7eb2e8f9f7 10740
<> 144:ef7eb2e8f9f7 10741 #define EADC_INTSRC2_AD0SPIE1_Pos (1) /*!< EADC INTSRC2: AD0SPIE1 Position */
<> 144:ef7eb2e8f9f7 10742 #define EADC_INTSRC2_AD0SPIE1_Msk (0x1ul << EADC_INTSRC2_AD0SPIE1_Pos) /*!< EADC INTSRC2: AD0SPIE1 Mask */
<> 144:ef7eb2e8f9f7 10743
<> 144:ef7eb2e8f9f7 10744 #define EADC_INTSRC2_AD0SPIE2_Pos (2) /*!< EADC INTSRC2: AD0SPIE2 Position */
<> 144:ef7eb2e8f9f7 10745 #define EADC_INTSRC2_AD0SPIE2_Msk (0x1ul << EADC_INTSRC2_AD0SPIE2_Pos) /*!< EADC INTSRC2: AD0SPIE2 Mask */
<> 144:ef7eb2e8f9f7 10746
<> 144:ef7eb2e8f9f7 10747 #define EADC_INTSRC2_AD0SPIE3_Pos (3) /*!< EADC INTSRC2: AD0SPIE3 Position */
<> 144:ef7eb2e8f9f7 10748 #define EADC_INTSRC2_AD0SPIE3_Msk (0x1ul << EADC_INTSRC2_AD0SPIE3_Pos) /*!< EADC INTSRC2: AD0SPIE3 Mask */
<> 144:ef7eb2e8f9f7 10749
<> 144:ef7eb2e8f9f7 10750 #define EADC_INTSRC2_AD0SPIE4_Pos (4) /*!< EADC INTSRC2: AD0SPIE4 Position */
<> 144:ef7eb2e8f9f7 10751 #define EADC_INTSRC2_AD0SPIE4_Msk (0x1ul << EADC_INTSRC2_AD0SPIE4_Pos) /*!< EADC INTSRC2: AD0SPIE4 Mask */
<> 144:ef7eb2e8f9f7 10752
<> 144:ef7eb2e8f9f7 10753 #define EADC_INTSRC2_AD0SPIE5_Pos (5) /*!< EADC INTSRC2: AD0SPIE5 Position */
<> 144:ef7eb2e8f9f7 10754 #define EADC_INTSRC2_AD0SPIE5_Msk (0x1ul << EADC_INTSRC2_AD0SPIE5_Pos) /*!< EADC INTSRC2: AD0SPIE5 Mask */
<> 144:ef7eb2e8f9f7 10755
<> 144:ef7eb2e8f9f7 10756 #define EADC_INTSRC2_AD0SPIE6_Pos (6) /*!< EADC INTSRC2: AD0SPIE6 Position */
<> 144:ef7eb2e8f9f7 10757 #define EADC_INTSRC2_AD0SPIE6_Msk (0x1ul << EADC_INTSRC2_AD0SPIE6_Pos) /*!< EADC INTSRC2: AD0SPIE6 Mask */
<> 144:ef7eb2e8f9f7 10758
<> 144:ef7eb2e8f9f7 10759 #define EADC_INTSRC2_AD0SPIE7_Pos (7) /*!< EADC INTSRC2: AD0SPIE7 Position */
<> 144:ef7eb2e8f9f7 10760 #define EADC_INTSRC2_AD0SPIE7_Msk (0x1ul << EADC_INTSRC2_AD0SPIE7_Pos) /*!< EADC INTSRC2: AD0SPIE7 Mask */
<> 144:ef7eb2e8f9f7 10761
<> 144:ef7eb2e8f9f7 10762 #define EADC_INTSRC2_AD1SPIE0_Pos (8) /*!< EADC INTSRC2: AD1SPIE0 Position */
<> 144:ef7eb2e8f9f7 10763 #define EADC_INTSRC2_AD1SPIE0_Msk (0x1ul << EADC_INTSRC2_AD1SPIE0_Pos) /*!< EADC INTSRC2: AD1SPIE0 Mask */
<> 144:ef7eb2e8f9f7 10764
<> 144:ef7eb2e8f9f7 10765 #define EADC_INTSRC2_AD1SPIE1_Pos (9) /*!< EADC INTSRC2: AD1SPIE1 Position */
<> 144:ef7eb2e8f9f7 10766 #define EADC_INTSRC2_AD1SPIE1_Msk (0x1ul << EADC_INTSRC2_AD1SPIE1_Pos) /*!< EADC INTSRC2: AD1SPIE1 Mask */
<> 144:ef7eb2e8f9f7 10767
<> 144:ef7eb2e8f9f7 10768 #define EADC_INTSRC2_AD1SPIE2_Pos (10) /*!< EADC INTSRC2: AD1SPIE2 Position */
<> 144:ef7eb2e8f9f7 10769 #define EADC_INTSRC2_AD1SPIE2_Msk (0x1ul << EADC_INTSRC2_AD1SPIE2_Pos) /*!< EADC INTSRC2: AD1SPIE2 Mask */
<> 144:ef7eb2e8f9f7 10770
<> 144:ef7eb2e8f9f7 10771 #define EADC_INTSRC2_AD1SPIE3_Pos (11) /*!< EADC INTSRC2: AD1SPIE3 Position */
<> 144:ef7eb2e8f9f7 10772 #define EADC_INTSRC2_AD1SPIE3_Msk (0x1ul << EADC_INTSRC2_AD1SPIE3_Pos) /*!< EADC INTSRC2: AD1SPIE3 Mask */
<> 144:ef7eb2e8f9f7 10773
<> 144:ef7eb2e8f9f7 10774 #define EADC_INTSRC2_AD1SPIE4_Pos (12) /*!< EADC INTSRC2: AD1SPIE4 Position */
<> 144:ef7eb2e8f9f7 10775 #define EADC_INTSRC2_AD1SPIE4_Msk (0x1ul << EADC_INTSRC2_AD1SPIE4_Pos) /*!< EADC INTSRC2: AD1SPIE4 Mask */
<> 144:ef7eb2e8f9f7 10776
<> 144:ef7eb2e8f9f7 10777 #define EADC_INTSRC2_AD1SPIE5_Pos (13) /*!< EADC INTSRC2: AD1SPIE5 Position */
<> 144:ef7eb2e8f9f7 10778 #define EADC_INTSRC2_AD1SPIE5_Msk (0x1ul << EADC_INTSRC2_AD1SPIE5_Pos) /*!< EADC INTSRC2: AD1SPIE5 Mask */
<> 144:ef7eb2e8f9f7 10779
<> 144:ef7eb2e8f9f7 10780 #define EADC_INTSRC2_AD1SPIE6_Pos (14) /*!< EADC INTSRC2: AD1SPIE6 Position */
<> 144:ef7eb2e8f9f7 10781 #define EADC_INTSRC2_AD1SPIE6_Msk (0x1ul << EADC_INTSRC2_AD1SPIE6_Pos) /*!< EADC INTSRC2: AD1SPIE6 Mask */
<> 144:ef7eb2e8f9f7 10782
<> 144:ef7eb2e8f9f7 10783 #define EADC_INTSRC2_AD1SPIE7_Pos (15) /*!< EADC INTSRC2: AD1SPIE7 Position */
<> 144:ef7eb2e8f9f7 10784 #define EADC_INTSRC2_AD1SPIE7_Msk (0x1ul << EADC_INTSRC2_AD1SPIE7_Pos) /*!< EADC INTSRC2: AD1SPIE7 Mask */
<> 144:ef7eb2e8f9f7 10785
<> 144:ef7eb2e8f9f7 10786 #define EADC_INTSRC3_AD0SPIE0_Pos (0) /*!< EADC INTSRC3: AD0SPIE0 Position */
<> 144:ef7eb2e8f9f7 10787 #define EADC_INTSRC3_AD0SPIE0_Msk (0x1ul << EADC_INTSRC3_AD0SPIE0_Pos) /*!< EADC INTSRC3: AD0SPIE0 Mask */
<> 144:ef7eb2e8f9f7 10788
<> 144:ef7eb2e8f9f7 10789 #define EADC_INTSRC3_AD0SPIE1_Pos (1) /*!< EADC INTSRC3: AD0SPIE1 Position */
<> 144:ef7eb2e8f9f7 10790 #define EADC_INTSRC3_AD0SPIE1_Msk (0x1ul << EADC_INTSRC3_AD0SPIE1_Pos) /*!< EADC INTSRC3: AD0SPIE1 Mask */
<> 144:ef7eb2e8f9f7 10791
<> 144:ef7eb2e8f9f7 10792 #define EADC_INTSRC3_AD0SPIE2_Pos (2) /*!< EADC INTSRC3: AD0SPIE2 Position */
<> 144:ef7eb2e8f9f7 10793 #define EADC_INTSRC3_AD0SPIE2_Msk (0x1ul << EADC_INTSRC3_AD0SPIE2_Pos) /*!< EADC INTSRC3: AD0SPIE2 Mask */
<> 144:ef7eb2e8f9f7 10794
<> 144:ef7eb2e8f9f7 10795 #define EADC_INTSRC3_AD0SPIE3_Pos (3) /*!< EADC INTSRC3: AD0SPIE3 Position */
<> 144:ef7eb2e8f9f7 10796 #define EADC_INTSRC3_AD0SPIE3_Msk (0x1ul << EADC_INTSRC3_AD0SPIE3_Pos) /*!< EADC INTSRC3: AD0SPIE3 Mask */
<> 144:ef7eb2e8f9f7 10797
<> 144:ef7eb2e8f9f7 10798 #define EADC_INTSRC3_AD0SPIE4_Pos (4) /*!< EADC INTSRC3: AD0SPIE4 Position */
<> 144:ef7eb2e8f9f7 10799 #define EADC_INTSRC3_AD0SPIE4_Msk (0x1ul << EADC_INTSRC3_AD0SPIE4_Pos) /*!< EADC INTSRC3: AD0SPIE4 Mask */
<> 144:ef7eb2e8f9f7 10800
<> 144:ef7eb2e8f9f7 10801 #define EADC_INTSRC3_AD0SPIE5_Pos (5) /*!< EADC INTSRC3: AD0SPIE5 Position */
<> 144:ef7eb2e8f9f7 10802 #define EADC_INTSRC3_AD0SPIE5_Msk (0x1ul << EADC_INTSRC3_AD0SPIE5_Pos) /*!< EADC INTSRC3: AD0SPIE5 Mask */
<> 144:ef7eb2e8f9f7 10803
<> 144:ef7eb2e8f9f7 10804 #define EADC_INTSRC3_AD0SPIE6_Pos (6) /*!< EADC INTSRC3: AD0SPIE6 Position */
<> 144:ef7eb2e8f9f7 10805 #define EADC_INTSRC3_AD0SPIE6_Msk (0x1ul << EADC_INTSRC3_AD0SPIE6_Pos) /*!< EADC INTSRC3: AD0SPIE6 Mask */
<> 144:ef7eb2e8f9f7 10806
<> 144:ef7eb2e8f9f7 10807 #define EADC_INTSRC3_AD0SPIE7_Pos (7) /*!< EADC INTSRC3: AD0SPIE7 Position */
<> 144:ef7eb2e8f9f7 10808 #define EADC_INTSRC3_AD0SPIE7_Msk (0x1ul << EADC_INTSRC3_AD0SPIE7_Pos) /*!< EADC INTSRC3: AD0SPIE7 Mask */
<> 144:ef7eb2e8f9f7 10809
<> 144:ef7eb2e8f9f7 10810 #define EADC_INTSRC3_AD1SPIE0_Pos (8) /*!< EADC INTSRC3: AD1SPIE0 Position */
<> 144:ef7eb2e8f9f7 10811 #define EADC_INTSRC3_AD1SPIE0_Msk (0x1ul << EADC_INTSRC3_AD1SPIE0_Pos) /*!< EADC INTSRC3: AD1SPIE0 Mask */
<> 144:ef7eb2e8f9f7 10812
<> 144:ef7eb2e8f9f7 10813 #define EADC_INTSRC3_AD1SPIE1_Pos (9) /*!< EADC INTSRC3: AD1SPIE1 Position */
<> 144:ef7eb2e8f9f7 10814 #define EADC_INTSRC3_AD1SPIE1_Msk (0x1ul << EADC_INTSRC3_AD1SPIE1_Pos) /*!< EADC INTSRC3: AD1SPIE1 Mask */
<> 144:ef7eb2e8f9f7 10815
<> 144:ef7eb2e8f9f7 10816 #define EADC_INTSRC3_AD1SPIE2_Pos (10) /*!< EADC INTSRC3: AD1SPIE2 Position */
<> 144:ef7eb2e8f9f7 10817 #define EADC_INTSRC3_AD1SPIE2_Msk (0x1ul << EADC_INTSRC3_AD1SPIE2_Pos) /*!< EADC INTSRC3: AD1SPIE2 Mask */
<> 144:ef7eb2e8f9f7 10818
<> 144:ef7eb2e8f9f7 10819 #define EADC_INTSRC3_AD1SPIE3_Pos (11) /*!< EADC INTSRC3: AD1SPIE3 Position */
<> 144:ef7eb2e8f9f7 10820 #define EADC_INTSRC3_AD1SPIE3_Msk (0x1ul << EADC_INTSRC3_AD1SPIE3_Pos) /*!< EADC INTSRC3: AD1SPIE3 Mask */
<> 144:ef7eb2e8f9f7 10821
<> 144:ef7eb2e8f9f7 10822 #define EADC_INTSRC3_AD1SPIE4_Pos (12) /*!< EADC INTSRC3: AD1SPIE4 Position */
<> 144:ef7eb2e8f9f7 10823 #define EADC_INTSRC3_AD1SPIE4_Msk (0x1ul << EADC_INTSRC3_AD1SPIE4_Pos) /*!< EADC INTSRC3: AD1SPIE4 Mask */
<> 144:ef7eb2e8f9f7 10824
<> 144:ef7eb2e8f9f7 10825 #define EADC_INTSRC3_AD1SPIE5_Pos (13) /*!< EADC INTSRC3: AD1SPIE5 Position */
<> 144:ef7eb2e8f9f7 10826 #define EADC_INTSRC3_AD1SPIE5_Msk (0x1ul << EADC_INTSRC3_AD1SPIE5_Pos) /*!< EADC INTSRC3: AD1SPIE5 Mask */
<> 144:ef7eb2e8f9f7 10827
<> 144:ef7eb2e8f9f7 10828 #define EADC_INTSRC3_AD1SPIE6_Pos (14) /*!< EADC INTSRC3: AD1SPIE6 Position */
<> 144:ef7eb2e8f9f7 10829 #define EADC_INTSRC3_AD1SPIE6_Msk (0x1ul << EADC_INTSRC3_AD1SPIE6_Pos) /*!< EADC INTSRC3: AD1SPIE6 Mask */
<> 144:ef7eb2e8f9f7 10830
<> 144:ef7eb2e8f9f7 10831 #define EADC_INTSRC3_AD1SPIE7_Pos (15) /*!< EADC INTSRC3: AD1SPIE7 Position */
<> 144:ef7eb2e8f9f7 10832 #define EADC_INTSRC3_AD1SPIE7_Msk (0x1ul << EADC_INTSRC3_AD1SPIE7_Pos) /*!< EADC INTSRC3: AD1SPIE7 Mask */
<> 144:ef7eb2e8f9f7 10833
<> 144:ef7eb2e8f9f7 10834 #define EADC_AD0TRGEN0_EPWM00REN_Pos (0) /*!< EADC AD0TRGEN0: EPWM00REN Position */
<> 144:ef7eb2e8f9f7 10835 #define EADC_AD0TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00REN_Pos) /*!< EADC AD0TRGEN0: EPWM00REN Mask */
<> 144:ef7eb2e8f9f7 10836
<> 144:ef7eb2e8f9f7 10837 #define EADC_AD0TRGEN0_EPWM00FEN_Pos (1) /*!< EADC AD0TRGEN0: EPWM00FEN Position */
<> 144:ef7eb2e8f9f7 10838 #define EADC_AD0TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00FEN_Pos) /*!< EADC AD0TRGEN0: EPWM00FEN Mask */
<> 144:ef7eb2e8f9f7 10839
<> 144:ef7eb2e8f9f7 10840 #define EADC_AD0TRGEN0_EPWM00PEN_Pos (2) /*!< EADC AD0TRGEN0: EPWM00PEN Position */
<> 144:ef7eb2e8f9f7 10841 #define EADC_AD0TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00PEN_Pos) /*!< EADC AD0TRGEN0: EPWM00PEN Mask */
<> 144:ef7eb2e8f9f7 10842
<> 144:ef7eb2e8f9f7 10843 #define EADC_AD0TRGEN0_EPWM00CEN_Pos (3) /*!< EADC AD0TRGEN0: EPWM00CEN Position */
<> 144:ef7eb2e8f9f7 10844 #define EADC_AD0TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM00CEN_Pos) /*!< EADC AD0TRGEN0: EPWM00CEN Mask */
<> 144:ef7eb2e8f9f7 10845
<> 144:ef7eb2e8f9f7 10846 #define EADC_AD0TRGEN0_EPWM02REN_Pos (4) /*!< EADC AD0TRGEN0: EPWM02REN Position */
<> 144:ef7eb2e8f9f7 10847 #define EADC_AD0TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02REN_Pos) /*!< EADC AD0TRGEN0: EPWM02REN Mask */
<> 144:ef7eb2e8f9f7 10848
<> 144:ef7eb2e8f9f7 10849 #define EADC_AD0TRGEN0_EPWM02FEN_Pos (5) /*!< EADC AD0TRGEN0: EPWM02FEN Position */
<> 144:ef7eb2e8f9f7 10850 #define EADC_AD0TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02FEN_Pos) /*!< EADC AD0TRGEN0: EPWM02FEN Mask */
<> 144:ef7eb2e8f9f7 10851
<> 144:ef7eb2e8f9f7 10852 #define EADC_AD0TRGEN0_EPWM02PEN_Pos (6) /*!< EADC AD0TRGEN0: EPWM02PEN Position */
<> 144:ef7eb2e8f9f7 10853 #define EADC_AD0TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02PEN_Pos) /*!< EADC AD0TRGEN0: EPWM02PEN Mask */
<> 144:ef7eb2e8f9f7 10854
<> 144:ef7eb2e8f9f7 10855 #define EADC_AD0TRGEN0_EPWM02CEN_Pos (7) /*!< EADC AD0TRGEN0: EPWM02CEN Position */
<> 144:ef7eb2e8f9f7 10856 #define EADC_AD0TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM02CEN_Pos) /*!< EADC AD0TRGEN0: EPWM02CEN Mask */
<> 144:ef7eb2e8f9f7 10857
<> 144:ef7eb2e8f9f7 10858 #define EADC_AD0TRGEN0_EPWM04REN_Pos (8) /*!< EADC AD0TRGEN0: EPWM04REN Position */
<> 144:ef7eb2e8f9f7 10859 #define EADC_AD0TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04REN_Pos) /*!< EADC AD0TRGEN0: EPWM04REN Mask */
<> 144:ef7eb2e8f9f7 10860
<> 144:ef7eb2e8f9f7 10861 #define EADC_AD0TRGEN0_EPWM04FEN_Pos (9) /*!< EADC AD0TRGEN0: EPWM04FEN Position */
<> 144:ef7eb2e8f9f7 10862 #define EADC_AD0TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04FEN_Pos) /*!< EADC AD0TRGEN0: EPWM04FEN Mask */
<> 144:ef7eb2e8f9f7 10863
<> 144:ef7eb2e8f9f7 10864 #define EADC_AD0TRGEN0_EPWM04PEN_Pos (10) /*!< EADC AD0TRGEN0: EPWM04PEN Position */
<> 144:ef7eb2e8f9f7 10865 #define EADC_AD0TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04PEN_Pos) /*!< EADC AD0TRGEN0: EPWM04PEN Mask */
<> 144:ef7eb2e8f9f7 10866
<> 144:ef7eb2e8f9f7 10867 #define EADC_AD0TRGEN0_EPWM04CEN_Pos (11) /*!< EADC AD0TRGEN0: EPWM04CEN Position */
<> 144:ef7eb2e8f9f7 10868 #define EADC_AD0TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM04CEN_Pos) /*!< EADC AD0TRGEN0: EPWM04CEN Mask */
<> 144:ef7eb2e8f9f7 10869
<> 144:ef7eb2e8f9f7 10870 #define EADC_AD0TRGEN0_EPWM10REN_Pos (12) /*!< EADC AD0TRGEN0: EPWM10REN Position */
<> 144:ef7eb2e8f9f7 10871 #define EADC_AD0TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10REN_Pos) /*!< EADC AD0TRGEN0: EPWM10REN Mask */
<> 144:ef7eb2e8f9f7 10872
<> 144:ef7eb2e8f9f7 10873 #define EADC_AD0TRGEN0_EPWM10FEN_Pos (13) /*!< EADC AD0TRGEN0: EPWM10FEN Position */
<> 144:ef7eb2e8f9f7 10874 #define EADC_AD0TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10FEN_Pos) /*!< EADC AD0TRGEN0: EPWM10FEN Mask */
<> 144:ef7eb2e8f9f7 10875
<> 144:ef7eb2e8f9f7 10876 #define EADC_AD0TRGEN0_EPWM10PEN_Pos (14) /*!< EADC AD0TRGEN0: EPWM10PEN Position */
<> 144:ef7eb2e8f9f7 10877 #define EADC_AD0TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10PEN_Pos) /*!< EADC AD0TRGEN0: EPWM10PEN Mask */
<> 144:ef7eb2e8f9f7 10878
<> 144:ef7eb2e8f9f7 10879 #define EADC_AD0TRGEN0_EPWM10CEN_Pos (15) /*!< EADC AD0TRGEN0: EPWM10CEN Position */
<> 144:ef7eb2e8f9f7 10880 #define EADC_AD0TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM10CEN_Pos) /*!< EADC AD0TRGEN0: EPWM10CEN Mask */
<> 144:ef7eb2e8f9f7 10881
<> 144:ef7eb2e8f9f7 10882 #define EADC_AD0TRGEN0_EPWM12REN_Pos (16) /*!< EADC AD0TRGEN0: EPWM12REN Position */
<> 144:ef7eb2e8f9f7 10883 #define EADC_AD0TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12REN_Pos) /*!< EADC AD0TRGEN0: EPWM12REN Mask */
<> 144:ef7eb2e8f9f7 10884
<> 144:ef7eb2e8f9f7 10885 #define EADC_AD0TRGEN0_EPWM120FEN_Pos (17) /*!< EADC AD0TRGEN0: EPWM120FEN Position */
<> 144:ef7eb2e8f9f7 10886 #define EADC_AD0TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM120FEN_Pos) /*!< EADC AD0TRGEN0: EPWM120FEN Mask */
<> 144:ef7eb2e8f9f7 10887
<> 144:ef7eb2e8f9f7 10888 #define EADC_AD0TRGEN0_EPWM12PEN_Pos (18) /*!< EADC AD0TRGEN0: EPWM12PEN Position */
<> 144:ef7eb2e8f9f7 10889 #define EADC_AD0TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12PEN_Pos) /*!< EADC AD0TRGEN0: EPWM12PEN Mask */
<> 144:ef7eb2e8f9f7 10890
<> 144:ef7eb2e8f9f7 10891 #define EADC_AD0TRGEN0_EPWM12CEN_Pos (19) /*!< EADC AD0TRGEN0: EPWM12CEN Position */
<> 144:ef7eb2e8f9f7 10892 #define EADC_AD0TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM12CEN_Pos) /*!< EADC AD0TRGEN0: EPWM12CEN Mask */
<> 144:ef7eb2e8f9f7 10893
<> 144:ef7eb2e8f9f7 10894 #define EADC_AD0TRGEN0_EPWM14REN_Pos (20) /*!< EADC AD0TRGEN0: EPWM14REN Position */
<> 144:ef7eb2e8f9f7 10895 #define EADC_AD0TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14REN_Pos) /*!< EADC AD0TRGEN0: EPWM14REN Mask */
<> 144:ef7eb2e8f9f7 10896
<> 144:ef7eb2e8f9f7 10897 #define EADC_AD0TRGEN0_EPWM14FEN_Pos (21) /*!< EADC AD0TRGEN0: EPWM14FEN Position */
<> 144:ef7eb2e8f9f7 10898 #define EADC_AD0TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14FEN_Pos) /*!< EADC AD0TRGEN0: EPWM14FEN Mask */
<> 144:ef7eb2e8f9f7 10899
<> 144:ef7eb2e8f9f7 10900 #define EADC_AD0TRGEN0_EPWM14PEN_Pos (22) /*!< EADC AD0TRGEN0: EPWM14PEN Position */
<> 144:ef7eb2e8f9f7 10901 #define EADC_AD0TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14PEN_Pos) /*!< EADC AD0TRGEN0: EPWM14PEN Mask */
<> 144:ef7eb2e8f9f7 10902
<> 144:ef7eb2e8f9f7 10903 #define EADC_AD0TRGEN0_EPWM14CEN_Pos (23) /*!< EADC AD0TRGEN0: EPWM14CEN Position */
<> 144:ef7eb2e8f9f7 10904 #define EADC_AD0TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN0_EPWM14CEN_Pos) /*!< EADC AD0TRGEN0: EPWM14CEN Mask */
<> 144:ef7eb2e8f9f7 10905
<> 144:ef7eb2e8f9f7 10906 #define EADC_AD0TRGEN0_PWM00REN_Pos (24) /*!< EADC AD0TRGEN0: PWM00REN Position */
<> 144:ef7eb2e8f9f7 10907 #define EADC_AD0TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00REN_Pos) /*!< EADC AD0TRGEN0: PWM00REN Mask */
<> 144:ef7eb2e8f9f7 10908
<> 144:ef7eb2e8f9f7 10909 #define EADC_AD0TRGEN0_PWM00FEN_Pos (25) /*!< EADC AD0TRGEN0: PWM00FEN Position */
<> 144:ef7eb2e8f9f7 10910 #define EADC_AD0TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00FEN_Pos) /*!< EADC AD0TRGEN0: PWM00FEN Mask */
<> 144:ef7eb2e8f9f7 10911
<> 144:ef7eb2e8f9f7 10912 #define EADC_AD0TRGEN0_PWM00PEN_Pos (26) /*!< EADC AD0TRGEN0: PWM00PEN Position */
<> 144:ef7eb2e8f9f7 10913 #define EADC_AD0TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00PEN_Pos) /*!< EADC AD0TRGEN0: PWM00PEN Mask */
<> 144:ef7eb2e8f9f7 10914
<> 144:ef7eb2e8f9f7 10915 #define EADC_AD0TRGEN0_PWM00CEN_Pos (27) /*!< EADC AD0TRGEN0: PWM00CEN Position */
<> 144:ef7eb2e8f9f7 10916 #define EADC_AD0TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM00CEN_Pos) /*!< EADC AD0TRGEN0: PWM00CEN Mask */
<> 144:ef7eb2e8f9f7 10917
<> 144:ef7eb2e8f9f7 10918 #define EADC_AD0TRGEN0_PWM01REN_Pos (28) /*!< EADC AD0TRGEN0: PWM01REN Position */
<> 144:ef7eb2e8f9f7 10919 #define EADC_AD0TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01REN_Pos) /*!< EADC AD0TRGEN0: PWM01REN Mask */
<> 144:ef7eb2e8f9f7 10920
<> 144:ef7eb2e8f9f7 10921 #define EADC_AD0TRGEN0_PWM01FEN_Pos (29) /*!< EADC AD0TRGEN0: PWM01FEN Position */
<> 144:ef7eb2e8f9f7 10922 #define EADC_AD0TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01FEN_Pos) /*!< EADC AD0TRGEN0: PWM01FEN Mask */
<> 144:ef7eb2e8f9f7 10923
<> 144:ef7eb2e8f9f7 10924 #define EADC_AD0TRGEN0_PWM01PEN_Pos (30) /*!< EADC AD0TRGEN0: PWM01PEN Position */
<> 144:ef7eb2e8f9f7 10925 #define EADC_AD0TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01PEN_Pos) /*!< EADC AD0TRGEN0: PWM01PEN Mask */
<> 144:ef7eb2e8f9f7 10926
<> 144:ef7eb2e8f9f7 10927 #define EADC_AD0TRGEN0_PWM01CEN_Pos (31) /*!< EADC AD0TRGEN0: PWM01CEN Position */
<> 144:ef7eb2e8f9f7 10928 #define EADC_AD0TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN0_PWM01CEN_Pos) /*!< EADC AD0TRGEN0: PWM01CEN Mask */
<> 144:ef7eb2e8f9f7 10929
<> 144:ef7eb2e8f9f7 10930 #define EADC_AD0TRGEN1_EPWM00REN_Pos (0) /*!< EADC AD0TRGEN1: EPWM00REN Position */
<> 144:ef7eb2e8f9f7 10931 #define EADC_AD0TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00REN_Pos) /*!< EADC AD0TRGEN1: EPWM00REN Mask */
<> 144:ef7eb2e8f9f7 10932
<> 144:ef7eb2e8f9f7 10933 #define EADC_AD0TRGEN1_EPWM00FEN_Pos (1) /*!< EADC AD0TRGEN1: EPWM00FEN Position */
<> 144:ef7eb2e8f9f7 10934 #define EADC_AD0TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00FEN_Pos) /*!< EADC AD0TRGEN1: EPWM00FEN Mask */
<> 144:ef7eb2e8f9f7 10935
<> 144:ef7eb2e8f9f7 10936 #define EADC_AD0TRGEN1_EPWM00PEN_Pos (2) /*!< EADC AD0TRGEN1: EPWM00PEN Position */
<> 144:ef7eb2e8f9f7 10937 #define EADC_AD0TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00PEN_Pos) /*!< EADC AD0TRGEN1: EPWM00PEN Mask */
<> 144:ef7eb2e8f9f7 10938
<> 144:ef7eb2e8f9f7 10939 #define EADC_AD0TRGEN1_EPWM00CEN_Pos (3) /*!< EADC AD0TRGEN1: EPWM00CEN Position */
<> 144:ef7eb2e8f9f7 10940 #define EADC_AD0TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM00CEN_Pos) /*!< EADC AD0TRGEN1: EPWM00CEN Mask */
<> 144:ef7eb2e8f9f7 10941
<> 144:ef7eb2e8f9f7 10942 #define EADC_AD0TRGEN1_EPWM02REN_Pos (4) /*!< EADC AD0TRGEN1: EPWM02REN Position */
<> 144:ef7eb2e8f9f7 10943 #define EADC_AD0TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02REN_Pos) /*!< EADC AD0TRGEN1: EPWM02REN Mask */
<> 144:ef7eb2e8f9f7 10944
<> 144:ef7eb2e8f9f7 10945 #define EADC_AD0TRGEN1_EPWM02FEN_Pos (5) /*!< EADC AD0TRGEN1: EPWM02FEN Position */
<> 144:ef7eb2e8f9f7 10946 #define EADC_AD0TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02FEN_Pos) /*!< EADC AD0TRGEN1: EPWM02FEN Mask */
<> 144:ef7eb2e8f9f7 10947
<> 144:ef7eb2e8f9f7 10948 #define EADC_AD0TRGEN1_EPWM02PEN_Pos (6) /*!< EADC AD0TRGEN1: EPWM02PEN Position */
<> 144:ef7eb2e8f9f7 10949 #define EADC_AD0TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02PEN_Pos) /*!< EADC AD0TRGEN1: EPWM02PEN Mask */
<> 144:ef7eb2e8f9f7 10950
<> 144:ef7eb2e8f9f7 10951 #define EADC_AD0TRGEN1_EPWM02CEN_Pos (7) /*!< EADC AD0TRGEN1: EPWM02CEN Position */
<> 144:ef7eb2e8f9f7 10952 #define EADC_AD0TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM02CEN_Pos) /*!< EADC AD0TRGEN1: EPWM02CEN Mask */
<> 144:ef7eb2e8f9f7 10953
<> 144:ef7eb2e8f9f7 10954 #define EADC_AD0TRGEN1_EPWM04REN_Pos (8) /*!< EADC AD0TRGEN1: EPWM04REN Position */
<> 144:ef7eb2e8f9f7 10955 #define EADC_AD0TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04REN_Pos) /*!< EADC AD0TRGEN1: EPWM04REN Mask */
<> 144:ef7eb2e8f9f7 10956
<> 144:ef7eb2e8f9f7 10957 #define EADC_AD0TRGEN1_EPWM04FEN_Pos (9) /*!< EADC AD0TRGEN1: EPWM04FEN Position */
<> 144:ef7eb2e8f9f7 10958 #define EADC_AD0TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04FEN_Pos) /*!< EADC AD0TRGEN1: EPWM04FEN Mask */
<> 144:ef7eb2e8f9f7 10959
<> 144:ef7eb2e8f9f7 10960 #define EADC_AD0TRGEN1_EPWM04PEN_Pos (10) /*!< EADC AD0TRGEN1: EPWM04PEN Position */
<> 144:ef7eb2e8f9f7 10961 #define EADC_AD0TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04PEN_Pos) /*!< EADC AD0TRGEN1: EPWM04PEN Mask */
<> 144:ef7eb2e8f9f7 10962
<> 144:ef7eb2e8f9f7 10963 #define EADC_AD0TRGEN1_EPWM04CEN_Pos (11) /*!< EADC AD0TRGEN1: EPWM04CEN Position */
<> 144:ef7eb2e8f9f7 10964 #define EADC_AD0TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM04CEN_Pos) /*!< EADC AD0TRGEN1: EPWM04CEN Mask */
<> 144:ef7eb2e8f9f7 10965
<> 144:ef7eb2e8f9f7 10966 #define EADC_AD0TRGEN1_EPWM10REN_Pos (12) /*!< EADC AD0TRGEN1: EPWM10REN Position */
<> 144:ef7eb2e8f9f7 10967 #define EADC_AD0TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10REN_Pos) /*!< EADC AD0TRGEN1: EPWM10REN Mask */
<> 144:ef7eb2e8f9f7 10968
<> 144:ef7eb2e8f9f7 10969 #define EADC_AD0TRGEN1_EPWM10FEN_Pos (13) /*!< EADC AD0TRGEN1: EPWM10FEN Position */
<> 144:ef7eb2e8f9f7 10970 #define EADC_AD0TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10FEN_Pos) /*!< EADC AD0TRGEN1: EPWM10FEN Mask */
<> 144:ef7eb2e8f9f7 10971
<> 144:ef7eb2e8f9f7 10972 #define EADC_AD0TRGEN1_EPWM10PEN_Pos (14) /*!< EADC AD0TRGEN1: EPWM10PEN Position */
<> 144:ef7eb2e8f9f7 10973 #define EADC_AD0TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10PEN_Pos) /*!< EADC AD0TRGEN1: EPWM10PEN Mask */
<> 144:ef7eb2e8f9f7 10974
<> 144:ef7eb2e8f9f7 10975 #define EADC_AD0TRGEN1_EPWM10CEN_Pos (15) /*!< EADC AD0TRGEN1: EPWM10CEN Position */
<> 144:ef7eb2e8f9f7 10976 #define EADC_AD0TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM10CEN_Pos) /*!< EADC AD0TRGEN1: EPWM10CEN Mask */
<> 144:ef7eb2e8f9f7 10977
<> 144:ef7eb2e8f9f7 10978 #define EADC_AD0TRGEN1_EPWM12REN_Pos (16) /*!< EADC AD0TRGEN1: EPWM12REN Position */
<> 144:ef7eb2e8f9f7 10979 #define EADC_AD0TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12REN_Pos) /*!< EADC AD0TRGEN1: EPWM12REN Mask */
<> 144:ef7eb2e8f9f7 10980
<> 144:ef7eb2e8f9f7 10981 #define EADC_AD0TRGEN1_EPWM120FEN_Pos (17) /*!< EADC AD0TRGEN1: EPWM120FEN Position */
<> 144:ef7eb2e8f9f7 10982 #define EADC_AD0TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM120FEN_Pos) /*!< EADC AD0TRGEN1: EPWM120FEN Mask */
<> 144:ef7eb2e8f9f7 10983
<> 144:ef7eb2e8f9f7 10984 #define EADC_AD0TRGEN1_EPWM12PEN_Pos (18) /*!< EADC AD0TRGEN1: EPWM12PEN Position */
<> 144:ef7eb2e8f9f7 10985 #define EADC_AD0TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12PEN_Pos) /*!< EADC AD0TRGEN1: EPWM12PEN Mask */
<> 144:ef7eb2e8f9f7 10986
<> 144:ef7eb2e8f9f7 10987 #define EADC_AD0TRGEN1_EPWM12CEN_Pos (19) /*!< EADC AD0TRGEN1: EPWM12CEN Position */
<> 144:ef7eb2e8f9f7 10988 #define EADC_AD0TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM12CEN_Pos) /*!< EADC AD0TRGEN1: EPWM12CEN Mask */
<> 144:ef7eb2e8f9f7 10989
<> 144:ef7eb2e8f9f7 10990 #define EADC_AD0TRGEN1_EPWM14REN_Pos (20) /*!< EADC AD0TRGEN1: EPWM14REN Position */
<> 144:ef7eb2e8f9f7 10991 #define EADC_AD0TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14REN_Pos) /*!< EADC AD0TRGEN1: EPWM14REN Mask */
<> 144:ef7eb2e8f9f7 10992
<> 144:ef7eb2e8f9f7 10993 #define EADC_AD0TRGEN1_EPWM14FEN_Pos (21) /*!< EADC AD0TRGEN1: EPWM14FEN Position */
<> 144:ef7eb2e8f9f7 10994 #define EADC_AD0TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14FEN_Pos) /*!< EADC AD0TRGEN1: EPWM14FEN Mask */
<> 144:ef7eb2e8f9f7 10995
<> 144:ef7eb2e8f9f7 10996 #define EADC_AD0TRGEN1_EPWM14PEN_Pos (22) /*!< EADC AD0TRGEN1: EPWM14PEN Position */
<> 144:ef7eb2e8f9f7 10997 #define EADC_AD0TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14PEN_Pos) /*!< EADC AD0TRGEN1: EPWM14PEN Mask */
<> 144:ef7eb2e8f9f7 10998
<> 144:ef7eb2e8f9f7 10999 #define EADC_AD0TRGEN1_EPWM14CEN_Pos (23) /*!< EADC AD0TRGEN1: EPWM14CEN Position */
<> 144:ef7eb2e8f9f7 11000 #define EADC_AD0TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN1_EPWM14CEN_Pos) /*!< EADC AD0TRGEN1: EPWM14CEN Mask */
<> 144:ef7eb2e8f9f7 11001
<> 144:ef7eb2e8f9f7 11002 #define EADC_AD0TRGEN1_PWM00REN_Pos (24) /*!< EADC AD0TRGEN1: PWM00REN Position */
<> 144:ef7eb2e8f9f7 11003 #define EADC_AD0TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00REN_Pos) /*!< EADC AD0TRGEN1: PWM00REN Mask */
<> 144:ef7eb2e8f9f7 11004
<> 144:ef7eb2e8f9f7 11005 #define EADC_AD0TRGEN1_PWM00FEN_Pos (25) /*!< EADC AD0TRGEN1: PWM00FEN Position */
<> 144:ef7eb2e8f9f7 11006 #define EADC_AD0TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00FEN_Pos) /*!< EADC AD0TRGEN1: PWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11007
<> 144:ef7eb2e8f9f7 11008 #define EADC_AD0TRGEN1_PWM00PEN_Pos (26) /*!< EADC AD0TRGEN1: PWM00PEN Position */
<> 144:ef7eb2e8f9f7 11009 #define EADC_AD0TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00PEN_Pos) /*!< EADC AD0TRGEN1: PWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11010
<> 144:ef7eb2e8f9f7 11011 #define EADC_AD0TRGEN1_PWM00CEN_Pos (27) /*!< EADC AD0TRGEN1: PWM00CEN Position */
<> 144:ef7eb2e8f9f7 11012 #define EADC_AD0TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM00CEN_Pos) /*!< EADC AD0TRGEN1: PWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11013
<> 144:ef7eb2e8f9f7 11014 #define EADC_AD0TRGEN1_PWM01REN_Pos (28) /*!< EADC AD0TRGEN1: PWM01REN Position */
<> 144:ef7eb2e8f9f7 11015 #define EADC_AD0TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01REN_Pos) /*!< EADC AD0TRGEN1: PWM01REN Mask */
<> 144:ef7eb2e8f9f7 11016
<> 144:ef7eb2e8f9f7 11017 #define EADC_AD0TRGEN1_PWM01FEN_Pos (29) /*!< EADC AD0TRGEN1: PWM01FEN Position */
<> 144:ef7eb2e8f9f7 11018 #define EADC_AD0TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01FEN_Pos) /*!< EADC AD0TRGEN1: PWM01FEN Mask */
<> 144:ef7eb2e8f9f7 11019
<> 144:ef7eb2e8f9f7 11020 #define EADC_AD0TRGEN1_PWM01PEN_Pos (30) /*!< EADC AD0TRGEN1: PWM01PEN Position */
<> 144:ef7eb2e8f9f7 11021 #define EADC_AD0TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01PEN_Pos) /*!< EADC AD0TRGEN1: PWM01PEN Mask */
<> 144:ef7eb2e8f9f7 11022
<> 144:ef7eb2e8f9f7 11023 #define EADC_AD0TRGEN1_PWM01CEN_Pos (31) /*!< EADC AD0TRGEN1: PWM01CEN Position */
<> 144:ef7eb2e8f9f7 11024 #define EADC_AD0TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN1_PWM01CEN_Pos) /*!< EADC AD0TRGEN1: PWM01CEN Mask */
<> 144:ef7eb2e8f9f7 11025
<> 144:ef7eb2e8f9f7 11026 #define EADC_AD0TRGEN2_EPWM00REN_Pos (0) /*!< EADC AD0TRGEN2: EPWM00REN Position */
<> 144:ef7eb2e8f9f7 11027 #define EADC_AD0TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00REN_Pos) /*!< EADC AD0TRGEN2: EPWM00REN Mask */
<> 144:ef7eb2e8f9f7 11028
<> 144:ef7eb2e8f9f7 11029 #define EADC_AD0TRGEN2_EPWM00FEN_Pos (1) /*!< EADC AD0TRGEN2: EPWM00FEN Position */
<> 144:ef7eb2e8f9f7 11030 #define EADC_AD0TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00FEN_Pos) /*!< EADC AD0TRGEN2: EPWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11031
<> 144:ef7eb2e8f9f7 11032 #define EADC_AD0TRGEN2_EPWM00PEN_Pos (2) /*!< EADC AD0TRGEN2: EPWM00PEN Position */
<> 144:ef7eb2e8f9f7 11033 #define EADC_AD0TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00PEN_Pos) /*!< EADC AD0TRGEN2: EPWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11034
<> 144:ef7eb2e8f9f7 11035 #define EADC_AD0TRGEN2_EPWM00CEN_Pos (3) /*!< EADC AD0TRGEN2: EPWM00CEN Position */
<> 144:ef7eb2e8f9f7 11036 #define EADC_AD0TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM00CEN_Pos) /*!< EADC AD0TRGEN2: EPWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11037
<> 144:ef7eb2e8f9f7 11038 #define EADC_AD0TRGEN2_EPWM02REN_Pos (4) /*!< EADC AD0TRGEN2: EPWM02REN Position */
<> 144:ef7eb2e8f9f7 11039 #define EADC_AD0TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02REN_Pos) /*!< EADC AD0TRGEN2: EPWM02REN Mask */
<> 144:ef7eb2e8f9f7 11040
<> 144:ef7eb2e8f9f7 11041 #define EADC_AD0TRGEN2_EPWM02FEN_Pos (5) /*!< EADC AD0TRGEN2: EPWM02FEN Position */
<> 144:ef7eb2e8f9f7 11042 #define EADC_AD0TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02FEN_Pos) /*!< EADC AD0TRGEN2: EPWM02FEN Mask */
<> 144:ef7eb2e8f9f7 11043
<> 144:ef7eb2e8f9f7 11044 #define EADC_AD0TRGEN2_EPWM02PEN_Pos (6) /*!< EADC AD0TRGEN2: EPWM02PEN Position */
<> 144:ef7eb2e8f9f7 11045 #define EADC_AD0TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02PEN_Pos) /*!< EADC AD0TRGEN2: EPWM02PEN Mask */
<> 144:ef7eb2e8f9f7 11046
<> 144:ef7eb2e8f9f7 11047 #define EADC_AD0TRGEN2_EPWM02CEN_Pos (7) /*!< EADC AD0TRGEN2: EPWM02CEN Position */
<> 144:ef7eb2e8f9f7 11048 #define EADC_AD0TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM02CEN_Pos) /*!< EADC AD0TRGEN2: EPWM02CEN Mask */
<> 144:ef7eb2e8f9f7 11049
<> 144:ef7eb2e8f9f7 11050 #define EADC_AD0TRGEN2_EPWM04REN_Pos (8) /*!< EADC AD0TRGEN2: EPWM04REN Position */
<> 144:ef7eb2e8f9f7 11051 #define EADC_AD0TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04REN_Pos) /*!< EADC AD0TRGEN2: EPWM04REN Mask */
<> 144:ef7eb2e8f9f7 11052
<> 144:ef7eb2e8f9f7 11053 #define EADC_AD0TRGEN2_EPWM04FEN_Pos (9) /*!< EADC AD0TRGEN2: EPWM04FEN Position */
<> 144:ef7eb2e8f9f7 11054 #define EADC_AD0TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04FEN_Pos) /*!< EADC AD0TRGEN2: EPWM04FEN Mask */
<> 144:ef7eb2e8f9f7 11055
<> 144:ef7eb2e8f9f7 11056 #define EADC_AD0TRGEN2_EPWM04PEN_Pos (10) /*!< EADC AD0TRGEN2: EPWM04PEN Position */
<> 144:ef7eb2e8f9f7 11057 #define EADC_AD0TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04PEN_Pos) /*!< EADC AD0TRGEN2: EPWM04PEN Mask */
<> 144:ef7eb2e8f9f7 11058
<> 144:ef7eb2e8f9f7 11059 #define EADC_AD0TRGEN2_EPWM04CEN_Pos (11) /*!< EADC AD0TRGEN2: EPWM04CEN Position */
<> 144:ef7eb2e8f9f7 11060 #define EADC_AD0TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM04CEN_Pos) /*!< EADC AD0TRGEN2: EPWM04CEN Mask */
<> 144:ef7eb2e8f9f7 11061
<> 144:ef7eb2e8f9f7 11062 #define EADC_AD0TRGEN2_EPWM10REN_Pos (12) /*!< EADC AD0TRGEN2: EPWM10REN Position */
<> 144:ef7eb2e8f9f7 11063 #define EADC_AD0TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10REN_Pos) /*!< EADC AD0TRGEN2: EPWM10REN Mask */
<> 144:ef7eb2e8f9f7 11064
<> 144:ef7eb2e8f9f7 11065 #define EADC_AD0TRGEN2_EPWM10FEN_Pos (13) /*!< EADC AD0TRGEN2: EPWM10FEN Position */
<> 144:ef7eb2e8f9f7 11066 #define EADC_AD0TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10FEN_Pos) /*!< EADC AD0TRGEN2: EPWM10FEN Mask */
<> 144:ef7eb2e8f9f7 11067
<> 144:ef7eb2e8f9f7 11068 #define EADC_AD0TRGEN2_EPWM10PEN_Pos (14) /*!< EADC AD0TRGEN2: EPWM10PEN Position */
<> 144:ef7eb2e8f9f7 11069 #define EADC_AD0TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10PEN_Pos) /*!< EADC AD0TRGEN2: EPWM10PEN Mask */
<> 144:ef7eb2e8f9f7 11070
<> 144:ef7eb2e8f9f7 11071 #define EADC_AD0TRGEN2_EPWM10CEN_Pos (15) /*!< EADC AD0TRGEN2: EPWM10CEN Position */
<> 144:ef7eb2e8f9f7 11072 #define EADC_AD0TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM10CEN_Pos) /*!< EADC AD0TRGEN2: EPWM10CEN Mask */
<> 144:ef7eb2e8f9f7 11073
<> 144:ef7eb2e8f9f7 11074 #define EADC_AD0TRGEN2_EPWM12REN_Pos (16) /*!< EADC AD0TRGEN2: EPWM12REN Position */
<> 144:ef7eb2e8f9f7 11075 #define EADC_AD0TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12REN_Pos) /*!< EADC AD0TRGEN2: EPWM12REN Mask */
<> 144:ef7eb2e8f9f7 11076
<> 144:ef7eb2e8f9f7 11077 #define EADC_AD0TRGEN2_EPWM120FEN_Pos (17) /*!< EADC AD0TRGEN2: EPWM120FEN Position */
<> 144:ef7eb2e8f9f7 11078 #define EADC_AD0TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM120FEN_Pos) /*!< EADC AD0TRGEN2: EPWM120FEN Mask */
<> 144:ef7eb2e8f9f7 11079
<> 144:ef7eb2e8f9f7 11080 #define EADC_AD0TRGEN2_EPWM12PEN_Pos (18) /*!< EADC AD0TRGEN2: EPWM12PEN Position */
<> 144:ef7eb2e8f9f7 11081 #define EADC_AD0TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12PEN_Pos) /*!< EADC AD0TRGEN2: EPWM12PEN Mask */
<> 144:ef7eb2e8f9f7 11082
<> 144:ef7eb2e8f9f7 11083 #define EADC_AD0TRGEN2_EPWM12CEN_Pos (19) /*!< EADC AD0TRGEN2: EPWM12CEN Position */
<> 144:ef7eb2e8f9f7 11084 #define EADC_AD0TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM12CEN_Pos) /*!< EADC AD0TRGEN2: EPWM12CEN Mask */
<> 144:ef7eb2e8f9f7 11085
<> 144:ef7eb2e8f9f7 11086 #define EADC_AD0TRGEN2_EPWM14REN_Pos (20) /*!< EADC AD0TRGEN2: EPWM14REN Position */
<> 144:ef7eb2e8f9f7 11087 #define EADC_AD0TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14REN_Pos) /*!< EADC AD0TRGEN2: EPWM14REN Mask */
<> 144:ef7eb2e8f9f7 11088
<> 144:ef7eb2e8f9f7 11089 #define EADC_AD0TRGEN2_EPWM14FEN_Pos (21) /*!< EADC AD0TRGEN2: EPWM14FEN Position */
<> 144:ef7eb2e8f9f7 11090 #define EADC_AD0TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14FEN_Pos) /*!< EADC AD0TRGEN2: EPWM14FEN Mask */
<> 144:ef7eb2e8f9f7 11091
<> 144:ef7eb2e8f9f7 11092 #define EADC_AD0TRGEN2_EPWM14PEN_Pos (22) /*!< EADC AD0TRGEN2: EPWM14PEN Position */
<> 144:ef7eb2e8f9f7 11093 #define EADC_AD0TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14PEN_Pos) /*!< EADC AD0TRGEN2: EPWM14PEN Mask */
<> 144:ef7eb2e8f9f7 11094
<> 144:ef7eb2e8f9f7 11095 #define EADC_AD0TRGEN2_EPWM14CEN_Pos (23) /*!< EADC AD0TRGEN2: EPWM14CEN Position */
<> 144:ef7eb2e8f9f7 11096 #define EADC_AD0TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN2_EPWM14CEN_Pos) /*!< EADC AD0TRGEN2: EPWM14CEN Mask */
<> 144:ef7eb2e8f9f7 11097
<> 144:ef7eb2e8f9f7 11098 #define EADC_AD0TRGEN2_PWM00REN_Pos (24) /*!< EADC AD0TRGEN2: PWM00REN Position */
<> 144:ef7eb2e8f9f7 11099 #define EADC_AD0TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00REN_Pos) /*!< EADC AD0TRGEN2: PWM00REN Mask */
<> 144:ef7eb2e8f9f7 11100
<> 144:ef7eb2e8f9f7 11101 #define EADC_AD0TRGEN2_PWM00FEN_Pos (25) /*!< EADC AD0TRGEN2: PWM00FEN Position */
<> 144:ef7eb2e8f9f7 11102 #define EADC_AD0TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00FEN_Pos) /*!< EADC AD0TRGEN2: PWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11103
<> 144:ef7eb2e8f9f7 11104 #define EADC_AD0TRGEN2_PWM00PEN_Pos (26) /*!< EADC AD0TRGEN2: PWM00PEN Position */
<> 144:ef7eb2e8f9f7 11105 #define EADC_AD0TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00PEN_Pos) /*!< EADC AD0TRGEN2: PWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11106
<> 144:ef7eb2e8f9f7 11107 #define EADC_AD0TRGEN2_PWM00CEN_Pos (27) /*!< EADC AD0TRGEN2: PWM00CEN Position */
<> 144:ef7eb2e8f9f7 11108 #define EADC_AD0TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM00CEN_Pos) /*!< EADC AD0TRGEN2: PWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11109
<> 144:ef7eb2e8f9f7 11110 #define EADC_AD0TRGEN2_PWM01REN_Pos (28) /*!< EADC AD0TRGEN2: PWM01REN Position */
<> 144:ef7eb2e8f9f7 11111 #define EADC_AD0TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01REN_Pos) /*!< EADC AD0TRGEN2: PWM01REN Mask */
<> 144:ef7eb2e8f9f7 11112
<> 144:ef7eb2e8f9f7 11113 #define EADC_AD0TRGEN2_PWM01FEN_Pos (29) /*!< EADC AD0TRGEN2: PWM01FEN Position */
<> 144:ef7eb2e8f9f7 11114 #define EADC_AD0TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01FEN_Pos) /*!< EADC AD0TRGEN2: PWM01FEN Mask */
<> 144:ef7eb2e8f9f7 11115
<> 144:ef7eb2e8f9f7 11116 #define EADC_AD0TRGEN2_PWM01PEN_Pos (30) /*!< EADC AD0TRGEN2: PWM01PEN Position */
<> 144:ef7eb2e8f9f7 11117 #define EADC_AD0TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01PEN_Pos) /*!< EADC AD0TRGEN2: PWM01PEN Mask */
<> 144:ef7eb2e8f9f7 11118
<> 144:ef7eb2e8f9f7 11119 #define EADC_AD0TRGEN2_PWM01CEN_Pos (31) /*!< EADC AD0TRGEN2: PWM01CEN Position */
<> 144:ef7eb2e8f9f7 11120 #define EADC_AD0TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN2_PWM01CEN_Pos) /*!< EADC AD0TRGEN2: PWM01CEN Mask */
<> 144:ef7eb2e8f9f7 11121
<> 144:ef7eb2e8f9f7 11122 #define EADC_AD0TRGEN3_EPWM00REN_Pos (0) /*!< EADC AD0TRGEN3: EPWM00REN Position */
<> 144:ef7eb2e8f9f7 11123 #define EADC_AD0TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00REN_Pos) /*!< EADC AD0TRGEN3: EPWM00REN Mask */
<> 144:ef7eb2e8f9f7 11124
<> 144:ef7eb2e8f9f7 11125 #define EADC_AD0TRGEN3_EPWM00FEN_Pos (1) /*!< EADC AD0TRGEN3: EPWM00FEN Position */
<> 144:ef7eb2e8f9f7 11126 #define EADC_AD0TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00FEN_Pos) /*!< EADC AD0TRGEN3: EPWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11127
<> 144:ef7eb2e8f9f7 11128 #define EADC_AD0TRGEN3_EPWM00PEN_Pos (2) /*!< EADC AD0TRGEN3: EPWM00PEN Position */
<> 144:ef7eb2e8f9f7 11129 #define EADC_AD0TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00PEN_Pos) /*!< EADC AD0TRGEN3: EPWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11130
<> 144:ef7eb2e8f9f7 11131 #define EADC_AD0TRGEN3_EPWM00CEN_Pos (3) /*!< EADC AD0TRGEN3: EPWM00CEN Position */
<> 144:ef7eb2e8f9f7 11132 #define EADC_AD0TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM00CEN_Pos) /*!< EADC AD0TRGEN3: EPWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11133
<> 144:ef7eb2e8f9f7 11134 #define EADC_AD0TRGEN3_EPWM02REN_Pos (4) /*!< EADC AD0TRGEN3: EPWM02REN Position */
<> 144:ef7eb2e8f9f7 11135 #define EADC_AD0TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02REN_Pos) /*!< EADC AD0TRGEN3: EPWM02REN Mask */
<> 144:ef7eb2e8f9f7 11136
<> 144:ef7eb2e8f9f7 11137 #define EADC_AD0TRGEN3_EPWM02FEN_Pos (5) /*!< EADC AD0TRGEN3: EPWM02FEN Position */
<> 144:ef7eb2e8f9f7 11138 #define EADC_AD0TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02FEN_Pos) /*!< EADC AD0TRGEN3: EPWM02FEN Mask */
<> 144:ef7eb2e8f9f7 11139
<> 144:ef7eb2e8f9f7 11140 #define EADC_AD0TRGEN3_EPWM02PEN_Pos (6) /*!< EADC AD0TRGEN3: EPWM02PEN Position */
<> 144:ef7eb2e8f9f7 11141 #define EADC_AD0TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02PEN_Pos) /*!< EADC AD0TRGEN3: EPWM02PEN Mask */
<> 144:ef7eb2e8f9f7 11142
<> 144:ef7eb2e8f9f7 11143 #define EADC_AD0TRGEN3_EPWM02CEN_Pos (7) /*!< EADC AD0TRGEN3: EPWM02CEN Position */
<> 144:ef7eb2e8f9f7 11144 #define EADC_AD0TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM02CEN_Pos) /*!< EADC AD0TRGEN3: EPWM02CEN Mask */
<> 144:ef7eb2e8f9f7 11145
<> 144:ef7eb2e8f9f7 11146 #define EADC_AD0TRGEN3_EPWM04REN_Pos (8) /*!< EADC AD0TRGEN3: EPWM04REN Position */
<> 144:ef7eb2e8f9f7 11147 #define EADC_AD0TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04REN_Pos) /*!< EADC AD0TRGEN3: EPWM04REN Mask */
<> 144:ef7eb2e8f9f7 11148
<> 144:ef7eb2e8f9f7 11149 #define EADC_AD0TRGEN3_EPWM04FEN_Pos (9) /*!< EADC AD0TRGEN3: EPWM04FEN Position */
<> 144:ef7eb2e8f9f7 11150 #define EADC_AD0TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04FEN_Pos) /*!< EADC AD0TRGEN3: EPWM04FEN Mask */
<> 144:ef7eb2e8f9f7 11151
<> 144:ef7eb2e8f9f7 11152 #define EADC_AD0TRGEN3_EPWM04PEN_Pos (10) /*!< EADC AD0TRGEN3: EPWM04PEN Position */
<> 144:ef7eb2e8f9f7 11153 #define EADC_AD0TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04PEN_Pos) /*!< EADC AD0TRGEN3: EPWM04PEN Mask */
<> 144:ef7eb2e8f9f7 11154
<> 144:ef7eb2e8f9f7 11155 #define EADC_AD0TRGEN3_EPWM04CEN_Pos (11) /*!< EADC AD0TRGEN3: EPWM04CEN Position */
<> 144:ef7eb2e8f9f7 11156 #define EADC_AD0TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM04CEN_Pos) /*!< EADC AD0TRGEN3: EPWM04CEN Mask */
<> 144:ef7eb2e8f9f7 11157
<> 144:ef7eb2e8f9f7 11158 #define EADC_AD0TRGEN3_EPWM10REN_Pos (12) /*!< EADC AD0TRGEN3: EPWM10REN Position */
<> 144:ef7eb2e8f9f7 11159 #define EADC_AD0TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10REN_Pos) /*!< EADC AD0TRGEN3: EPWM10REN Mask */
<> 144:ef7eb2e8f9f7 11160
<> 144:ef7eb2e8f9f7 11161 #define EADC_AD0TRGEN3_EPWM10FEN_Pos (13) /*!< EADC AD0TRGEN3: EPWM10FEN Position */
<> 144:ef7eb2e8f9f7 11162 #define EADC_AD0TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10FEN_Pos) /*!< EADC AD0TRGEN3: EPWM10FEN Mask */
<> 144:ef7eb2e8f9f7 11163
<> 144:ef7eb2e8f9f7 11164 #define EADC_AD0TRGEN3_EPWM10PEN_Pos (14) /*!< EADC AD0TRGEN3: EPWM10PEN Position */
<> 144:ef7eb2e8f9f7 11165 #define EADC_AD0TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10PEN_Pos) /*!< EADC AD0TRGEN3: EPWM10PEN Mask */
<> 144:ef7eb2e8f9f7 11166
<> 144:ef7eb2e8f9f7 11167 #define EADC_AD0TRGEN3_EPWM10CEN_Pos (15) /*!< EADC AD0TRGEN3: EPWM10CEN Position */
<> 144:ef7eb2e8f9f7 11168 #define EADC_AD0TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM10CEN_Pos) /*!< EADC AD0TRGEN3: EPWM10CEN Mask */
<> 144:ef7eb2e8f9f7 11169
<> 144:ef7eb2e8f9f7 11170 #define EADC_AD0TRGEN3_EPWM12REN_Pos (16) /*!< EADC AD0TRGEN3: EPWM12REN Position */
<> 144:ef7eb2e8f9f7 11171 #define EADC_AD0TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12REN_Pos) /*!< EADC AD0TRGEN3: EPWM12REN Mask */
<> 144:ef7eb2e8f9f7 11172
<> 144:ef7eb2e8f9f7 11173 #define EADC_AD0TRGEN3_EPWM120FEN_Pos (17) /*!< EADC AD0TRGEN3: EPWM120FEN Position */
<> 144:ef7eb2e8f9f7 11174 #define EADC_AD0TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM120FEN_Pos) /*!< EADC AD0TRGEN3: EPWM120FEN Mask */
<> 144:ef7eb2e8f9f7 11175
<> 144:ef7eb2e8f9f7 11176 #define EADC_AD0TRGEN3_EPWM12PEN_Pos (18) /*!< EADC AD0TRGEN3: EPWM12PEN Position */
<> 144:ef7eb2e8f9f7 11177 #define EADC_AD0TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12PEN_Pos) /*!< EADC AD0TRGEN3: EPWM12PEN Mask */
<> 144:ef7eb2e8f9f7 11178
<> 144:ef7eb2e8f9f7 11179 #define EADC_AD0TRGEN3_EPWM12CEN_Pos (19) /*!< EADC AD0TRGEN3: EPWM12CEN Position */
<> 144:ef7eb2e8f9f7 11180 #define EADC_AD0TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM12CEN_Pos) /*!< EADC AD0TRGEN3: EPWM12CEN Mask */
<> 144:ef7eb2e8f9f7 11181
<> 144:ef7eb2e8f9f7 11182 #define EADC_AD0TRGEN3_EPWM14REN_Pos (20) /*!< EADC AD0TRGEN3: EPWM14REN Position */
<> 144:ef7eb2e8f9f7 11183 #define EADC_AD0TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14REN_Pos) /*!< EADC AD0TRGEN3: EPWM14REN Mask */
<> 144:ef7eb2e8f9f7 11184
<> 144:ef7eb2e8f9f7 11185 #define EADC_AD0TRGEN3_EPWM14FEN_Pos (21) /*!< EADC AD0TRGEN3: EPWM14FEN Position */
<> 144:ef7eb2e8f9f7 11186 #define EADC_AD0TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14FEN_Pos) /*!< EADC AD0TRGEN3: EPWM14FEN Mask */
<> 144:ef7eb2e8f9f7 11187
<> 144:ef7eb2e8f9f7 11188 #define EADC_AD0TRGEN3_EPWM14PEN_Pos (22) /*!< EADC AD0TRGEN3: EPWM14PEN Position */
<> 144:ef7eb2e8f9f7 11189 #define EADC_AD0TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14PEN_Pos) /*!< EADC AD0TRGEN3: EPWM14PEN Mask */
<> 144:ef7eb2e8f9f7 11190
<> 144:ef7eb2e8f9f7 11191 #define EADC_AD0TRGEN3_EPWM14CEN_Pos (23) /*!< EADC AD0TRGEN3: EPWM14CEN Position */
<> 144:ef7eb2e8f9f7 11192 #define EADC_AD0TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD0TRGEN3_EPWM14CEN_Pos) /*!< EADC AD0TRGEN3: EPWM14CEN Mask */
<> 144:ef7eb2e8f9f7 11193
<> 144:ef7eb2e8f9f7 11194 #define EADC_AD0TRGEN3_PWM00REN_Pos (24) /*!< EADC AD0TRGEN3: PWM00REN Position */
<> 144:ef7eb2e8f9f7 11195 #define EADC_AD0TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00REN_Pos) /*!< EADC AD0TRGEN3: PWM00REN Mask */
<> 144:ef7eb2e8f9f7 11196
<> 144:ef7eb2e8f9f7 11197 #define EADC_AD0TRGEN3_PWM00FEN_Pos (25) /*!< EADC AD0TRGEN3: PWM00FEN Position */
<> 144:ef7eb2e8f9f7 11198 #define EADC_AD0TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00FEN_Pos) /*!< EADC AD0TRGEN3: PWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11199
<> 144:ef7eb2e8f9f7 11200 #define EADC_AD0TRGEN3_PWM00PEN_Pos (26) /*!< EADC AD0TRGEN3: PWM00PEN Position */
<> 144:ef7eb2e8f9f7 11201 #define EADC_AD0TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00PEN_Pos) /*!< EADC AD0TRGEN3: PWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11202
<> 144:ef7eb2e8f9f7 11203 #define EADC_AD0TRGEN3_PWM00CEN_Pos (27) /*!< EADC AD0TRGEN3: PWM00CEN Position */
<> 144:ef7eb2e8f9f7 11204 #define EADC_AD0TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM00CEN_Pos) /*!< EADC AD0TRGEN3: PWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11205
<> 144:ef7eb2e8f9f7 11206 #define EADC_AD0TRGEN3_PWM01REN_Pos (28) /*!< EADC AD0TRGEN3: PWM01REN Position */
<> 144:ef7eb2e8f9f7 11207 #define EADC_AD0TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01REN_Pos) /*!< EADC AD0TRGEN3: PWM01REN Mask */
<> 144:ef7eb2e8f9f7 11208
<> 144:ef7eb2e8f9f7 11209 #define EADC_AD0TRGEN3_PWM01FEN_Pos (29) /*!< EADC AD0TRGEN3: PWM01FEN Position */
<> 144:ef7eb2e8f9f7 11210 #define EADC_AD0TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01FEN_Pos) /*!< EADC AD0TRGEN3: PWM01FEN Mask */
<> 144:ef7eb2e8f9f7 11211
<> 144:ef7eb2e8f9f7 11212 #define EADC_AD0TRGEN3_PWM01PEN_Pos (30) /*!< EADC AD0TRGEN3: PWM01PEN Position */
<> 144:ef7eb2e8f9f7 11213 #define EADC_AD0TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01PEN_Pos) /*!< EADC AD0TRGEN3: PWM01PEN Mask */
<> 144:ef7eb2e8f9f7 11214
<> 144:ef7eb2e8f9f7 11215 #define EADC_AD0TRGEN3_PWM01CEN_Pos (31) /*!< EADC AD0TRGEN3: PWM01CEN Position */
<> 144:ef7eb2e8f9f7 11216 #define EADC_AD0TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD0TRGEN3_PWM01CEN_Pos) /*!< EADC AD0TRGEN3: PWM01CEN Mask */
<> 144:ef7eb2e8f9f7 11217
<> 144:ef7eb2e8f9f7 11218 #define EADC_AD1TRGEN0_EPWM00REN_Pos (0) /*!< EADC AD1TRGEN0: EPWM00REN Position */
<> 144:ef7eb2e8f9f7 11219 #define EADC_AD1TRGEN0_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00REN_Pos) /*!< EADC AD1TRGEN0: EPWM00REN Mask */
<> 144:ef7eb2e8f9f7 11220
<> 144:ef7eb2e8f9f7 11221 #define EADC_AD1TRGEN0_EPWM00FEN_Pos (1) /*!< EADC AD1TRGEN0: EPWM00FEN Position */
<> 144:ef7eb2e8f9f7 11222 #define EADC_AD1TRGEN0_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00FEN_Pos) /*!< EADC AD1TRGEN0: EPWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11223
<> 144:ef7eb2e8f9f7 11224 #define EADC_AD1TRGEN0_EPWM00PEN_Pos (2) /*!< EADC AD1TRGEN0: EPWM00PEN Position */
<> 144:ef7eb2e8f9f7 11225 #define EADC_AD1TRGEN0_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00PEN_Pos) /*!< EADC AD1TRGEN0: EPWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11226
<> 144:ef7eb2e8f9f7 11227 #define EADC_AD1TRGEN0_EPWM00CEN_Pos (3) /*!< EADC AD1TRGEN0: EPWM00CEN Position */
<> 144:ef7eb2e8f9f7 11228 #define EADC_AD1TRGEN0_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM00CEN_Pos) /*!< EADC AD1TRGEN0: EPWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11229
<> 144:ef7eb2e8f9f7 11230 #define EADC_AD1TRGEN0_EPWM02REN_Pos (4) /*!< EADC AD1TRGEN0: EPWM02REN Position */
<> 144:ef7eb2e8f9f7 11231 #define EADC_AD1TRGEN0_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02REN_Pos) /*!< EADC AD1TRGEN0: EPWM02REN Mask */
<> 144:ef7eb2e8f9f7 11232
<> 144:ef7eb2e8f9f7 11233 #define EADC_AD1TRGEN0_EPWM02FEN_Pos (5) /*!< EADC AD1TRGEN0: EPWM02FEN Position */
<> 144:ef7eb2e8f9f7 11234 #define EADC_AD1TRGEN0_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02FEN_Pos) /*!< EADC AD1TRGEN0: EPWM02FEN Mask */
<> 144:ef7eb2e8f9f7 11235
<> 144:ef7eb2e8f9f7 11236 #define EADC_AD1TRGEN0_EPWM02PEN_Pos (6) /*!< EADC AD1TRGEN0: EPWM02PEN Position */
<> 144:ef7eb2e8f9f7 11237 #define EADC_AD1TRGEN0_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02PEN_Pos) /*!< EADC AD1TRGEN0: EPWM02PEN Mask */
<> 144:ef7eb2e8f9f7 11238
<> 144:ef7eb2e8f9f7 11239 #define EADC_AD1TRGEN0_EPWM02CEN_Pos (7) /*!< EADC AD1TRGEN0: EPWM02CEN Position */
<> 144:ef7eb2e8f9f7 11240 #define EADC_AD1TRGEN0_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM02CEN_Pos) /*!< EADC AD1TRGEN0: EPWM02CEN Mask */
<> 144:ef7eb2e8f9f7 11241
<> 144:ef7eb2e8f9f7 11242 #define EADC_AD1TRGEN0_EPWM04REN_Pos (8) /*!< EADC AD1TRGEN0: EPWM04REN Position */
<> 144:ef7eb2e8f9f7 11243 #define EADC_AD1TRGEN0_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04REN_Pos) /*!< EADC AD1TRGEN0: EPWM04REN Mask */
<> 144:ef7eb2e8f9f7 11244
<> 144:ef7eb2e8f9f7 11245 #define EADC_AD1TRGEN0_EPWM04FEN_Pos (9) /*!< EADC AD1TRGEN0: EPWM04FEN Position */
<> 144:ef7eb2e8f9f7 11246 #define EADC_AD1TRGEN0_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04FEN_Pos) /*!< EADC AD1TRGEN0: EPWM04FEN Mask */
<> 144:ef7eb2e8f9f7 11247
<> 144:ef7eb2e8f9f7 11248 #define EADC_AD1TRGEN0_EPWM04PEN_Pos (10) /*!< EADC AD1TRGEN0: EPWM04PEN Position */
<> 144:ef7eb2e8f9f7 11249 #define EADC_AD1TRGEN0_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04PEN_Pos) /*!< EADC AD1TRGEN0: EPWM04PEN Mask */
<> 144:ef7eb2e8f9f7 11250
<> 144:ef7eb2e8f9f7 11251 #define EADC_AD1TRGEN0_EPWM04CEN_Pos (11) /*!< EADC AD1TRGEN0: EPWM04CEN Position */
<> 144:ef7eb2e8f9f7 11252 #define EADC_AD1TRGEN0_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM04CEN_Pos) /*!< EADC AD1TRGEN0: EPWM04CEN Mask */
<> 144:ef7eb2e8f9f7 11253
<> 144:ef7eb2e8f9f7 11254 #define EADC_AD1TRGEN0_EPWM10REN_Pos (12) /*!< EADC AD1TRGEN0: EPWM10REN Position */
<> 144:ef7eb2e8f9f7 11255 #define EADC_AD1TRGEN0_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10REN_Pos) /*!< EADC AD1TRGEN0: EPWM10REN Mask */
<> 144:ef7eb2e8f9f7 11256
<> 144:ef7eb2e8f9f7 11257 #define EADC_AD1TRGEN0_EPWM10FEN_Pos (13) /*!< EADC AD1TRGEN0: EPWM10FEN Position */
<> 144:ef7eb2e8f9f7 11258 #define EADC_AD1TRGEN0_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10FEN_Pos) /*!< EADC AD1TRGEN0: EPWM10FEN Mask */
<> 144:ef7eb2e8f9f7 11259
<> 144:ef7eb2e8f9f7 11260 #define EADC_AD1TRGEN0_EPWM10PEN_Pos (14) /*!< EADC AD1TRGEN0: EPWM10PEN Position */
<> 144:ef7eb2e8f9f7 11261 #define EADC_AD1TRGEN0_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10PEN_Pos) /*!< EADC AD1TRGEN0: EPWM10PEN Mask */
<> 144:ef7eb2e8f9f7 11262
<> 144:ef7eb2e8f9f7 11263 #define EADC_AD1TRGEN0_EPWM10CEN_Pos (15) /*!< EADC AD1TRGEN0: EPWM10CEN Position */
<> 144:ef7eb2e8f9f7 11264 #define EADC_AD1TRGEN0_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM10CEN_Pos) /*!< EADC AD1TRGEN0: EPWM10CEN Mask */
<> 144:ef7eb2e8f9f7 11265
<> 144:ef7eb2e8f9f7 11266 #define EADC_AD1TRGEN0_EPWM12REN_Pos (16) /*!< EADC AD1TRGEN0: EPWM12REN Position */
<> 144:ef7eb2e8f9f7 11267 #define EADC_AD1TRGEN0_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12REN_Pos) /*!< EADC AD1TRGEN0: EPWM12REN Mask */
<> 144:ef7eb2e8f9f7 11268
<> 144:ef7eb2e8f9f7 11269 #define EADC_AD1TRGEN0_EPWM120FEN_Pos (17) /*!< EADC AD1TRGEN0: EPWM120FEN Position */
<> 144:ef7eb2e8f9f7 11270 #define EADC_AD1TRGEN0_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM120FEN_Pos) /*!< EADC AD1TRGEN0: EPWM120FEN Mask */
<> 144:ef7eb2e8f9f7 11271
<> 144:ef7eb2e8f9f7 11272 #define EADC_AD1TRGEN0_EPWM12PEN_Pos (18) /*!< EADC AD1TRGEN0: EPWM12PEN Position */
<> 144:ef7eb2e8f9f7 11273 #define EADC_AD1TRGEN0_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12PEN_Pos) /*!< EADC AD1TRGEN0: EPWM12PEN Mask */
<> 144:ef7eb2e8f9f7 11274
<> 144:ef7eb2e8f9f7 11275 #define EADC_AD1TRGEN0_EPWM12CEN_Pos (19) /*!< EADC AD1TRGEN0: EPWM12CEN Position */
<> 144:ef7eb2e8f9f7 11276 #define EADC_AD1TRGEN0_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM12CEN_Pos) /*!< EADC AD1TRGEN0: EPWM12CEN Mask */
<> 144:ef7eb2e8f9f7 11277
<> 144:ef7eb2e8f9f7 11278 #define EADC_AD1TRGEN0_EPWM14REN_Pos (20) /*!< EADC AD1TRGEN0: EPWM14REN Position */
<> 144:ef7eb2e8f9f7 11279 #define EADC_AD1TRGEN0_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14REN_Pos) /*!< EADC AD1TRGEN0: EPWM14REN Mask */
<> 144:ef7eb2e8f9f7 11280
<> 144:ef7eb2e8f9f7 11281 #define EADC_AD1TRGEN0_EPWM14FEN_Pos (21) /*!< EADC AD1TRGEN0: EPWM14FEN Position */
<> 144:ef7eb2e8f9f7 11282 #define EADC_AD1TRGEN0_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14FEN_Pos) /*!< EADC AD1TRGEN0: EPWM14FEN Mask */
<> 144:ef7eb2e8f9f7 11283
<> 144:ef7eb2e8f9f7 11284 #define EADC_AD1TRGEN0_EPWM14PEN_Pos (22) /*!< EADC AD1TRGEN0: EPWM14PEN Position */
<> 144:ef7eb2e8f9f7 11285 #define EADC_AD1TRGEN0_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14PEN_Pos) /*!< EADC AD1TRGEN0: EPWM14PEN Mask */
<> 144:ef7eb2e8f9f7 11286
<> 144:ef7eb2e8f9f7 11287 #define EADC_AD1TRGEN0_EPWM14CEN_Pos (23) /*!< EADC AD1TRGEN0: EPWM14CEN Position */
<> 144:ef7eb2e8f9f7 11288 #define EADC_AD1TRGEN0_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN0_EPWM14CEN_Pos) /*!< EADC AD1TRGEN0: EPWM14CEN Mask */
<> 144:ef7eb2e8f9f7 11289
<> 144:ef7eb2e8f9f7 11290 #define EADC_AD1TRGEN0_PWM00REN_Pos (24) /*!< EADC AD1TRGEN0: PWM00REN Position */
<> 144:ef7eb2e8f9f7 11291 #define EADC_AD1TRGEN0_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00REN_Pos) /*!< EADC AD1TRGEN0: PWM00REN Mask */
<> 144:ef7eb2e8f9f7 11292
<> 144:ef7eb2e8f9f7 11293 #define EADC_AD1TRGEN0_PWM00FEN_Pos (25) /*!< EADC AD1TRGEN0: PWM00FEN Position */
<> 144:ef7eb2e8f9f7 11294 #define EADC_AD1TRGEN0_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00FEN_Pos) /*!< EADC AD1TRGEN0: PWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11295
<> 144:ef7eb2e8f9f7 11296 #define EADC_AD1TRGEN0_PWM00PEN_Pos (26) /*!< EADC AD1TRGEN0: PWM00PEN Position */
<> 144:ef7eb2e8f9f7 11297 #define EADC_AD1TRGEN0_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00PEN_Pos) /*!< EADC AD1TRGEN0: PWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11298
<> 144:ef7eb2e8f9f7 11299 #define EADC_AD1TRGEN0_PWM00CEN_Pos (27) /*!< EADC AD1TRGEN0: PWM00CEN Position */
<> 144:ef7eb2e8f9f7 11300 #define EADC_AD1TRGEN0_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM00CEN_Pos) /*!< EADC AD1TRGEN0: PWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11301
<> 144:ef7eb2e8f9f7 11302 #define EADC_AD1TRGEN0_PWM01REN_Pos (28) /*!< EADC AD1TRGEN0: PWM01REN Position */
<> 144:ef7eb2e8f9f7 11303 #define EADC_AD1TRGEN0_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01REN_Pos) /*!< EADC AD1TRGEN0: PWM01REN Mask */
<> 144:ef7eb2e8f9f7 11304
<> 144:ef7eb2e8f9f7 11305 #define EADC_AD1TRGEN0_PWM01FEN_Pos (29) /*!< EADC AD1TRGEN0: PWM01FEN Position */
<> 144:ef7eb2e8f9f7 11306 #define EADC_AD1TRGEN0_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01FEN_Pos) /*!< EADC AD1TRGEN0: PWM01FEN Mask */
<> 144:ef7eb2e8f9f7 11307
<> 144:ef7eb2e8f9f7 11308 #define EADC_AD1TRGEN0_PWM01PEN_Pos (30) /*!< EADC AD1TRGEN0: PWM01PEN Position */
<> 144:ef7eb2e8f9f7 11309 #define EADC_AD1TRGEN0_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01PEN_Pos) /*!< EADC AD1TRGEN0: PWM01PEN Mask */
<> 144:ef7eb2e8f9f7 11310
<> 144:ef7eb2e8f9f7 11311 #define EADC_AD1TRGEN0_PWM01CEN_Pos (31) /*!< EADC AD1TRGEN0: PWM01CEN Position */
<> 144:ef7eb2e8f9f7 11312 #define EADC_AD1TRGEN0_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN0_PWM01CEN_Pos) /*!< EADC AD1TRGEN0: PWM01CEN Mask */
<> 144:ef7eb2e8f9f7 11313
<> 144:ef7eb2e8f9f7 11314 #define EADC_AD1TRGEN1_EPWM00REN_Pos (0) /*!< EADC AD1TRGEN1: EPWM00REN Position */
<> 144:ef7eb2e8f9f7 11315 #define EADC_AD1TRGEN1_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00REN_Pos) /*!< EADC AD1TRGEN1: EPWM00REN Mask */
<> 144:ef7eb2e8f9f7 11316
<> 144:ef7eb2e8f9f7 11317 #define EADC_AD1TRGEN1_EPWM00FEN_Pos (1) /*!< EADC AD1TRGEN1: EPWM00FEN Position */
<> 144:ef7eb2e8f9f7 11318 #define EADC_AD1TRGEN1_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00FEN_Pos) /*!< EADC AD1TRGEN1: EPWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11319
<> 144:ef7eb2e8f9f7 11320 #define EADC_AD1TRGEN1_EPWM00PEN_Pos (2) /*!< EADC AD1TRGEN1: EPWM00PEN Position */
<> 144:ef7eb2e8f9f7 11321 #define EADC_AD1TRGEN1_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00PEN_Pos) /*!< EADC AD1TRGEN1: EPWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11322
<> 144:ef7eb2e8f9f7 11323 #define EADC_AD1TRGEN1_EPWM00CEN_Pos (3) /*!< EADC AD1TRGEN1: EPWM00CEN Position */
<> 144:ef7eb2e8f9f7 11324 #define EADC_AD1TRGEN1_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM00CEN_Pos) /*!< EADC AD1TRGEN1: EPWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11325
<> 144:ef7eb2e8f9f7 11326 #define EADC_AD1TRGEN1_EPWM02REN_Pos (4) /*!< EADC AD1TRGEN1: EPWM02REN Position */
<> 144:ef7eb2e8f9f7 11327 #define EADC_AD1TRGEN1_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02REN_Pos) /*!< EADC AD1TRGEN1: EPWM02REN Mask */
<> 144:ef7eb2e8f9f7 11328
<> 144:ef7eb2e8f9f7 11329 #define EADC_AD1TRGEN1_EPWM02FEN_Pos (5) /*!< EADC AD1TRGEN1: EPWM02FEN Position */
<> 144:ef7eb2e8f9f7 11330 #define EADC_AD1TRGEN1_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02FEN_Pos) /*!< EADC AD1TRGEN1: EPWM02FEN Mask */
<> 144:ef7eb2e8f9f7 11331
<> 144:ef7eb2e8f9f7 11332 #define EADC_AD1TRGEN1_EPWM02PEN_Pos (6) /*!< EADC AD1TRGEN1: EPWM02PEN Position */
<> 144:ef7eb2e8f9f7 11333 #define EADC_AD1TRGEN1_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02PEN_Pos) /*!< EADC AD1TRGEN1: EPWM02PEN Mask */
<> 144:ef7eb2e8f9f7 11334
<> 144:ef7eb2e8f9f7 11335 #define EADC_AD1TRGEN1_EPWM02CEN_Pos (7) /*!< EADC AD1TRGEN1: EPWM02CEN Position */
<> 144:ef7eb2e8f9f7 11336 #define EADC_AD1TRGEN1_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM02CEN_Pos) /*!< EADC AD1TRGEN1: EPWM02CEN Mask */
<> 144:ef7eb2e8f9f7 11337
<> 144:ef7eb2e8f9f7 11338 #define EADC_AD1TRGEN1_EPWM04REN_Pos (8) /*!< EADC AD1TRGEN1: EPWM04REN Position */
<> 144:ef7eb2e8f9f7 11339 #define EADC_AD1TRGEN1_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04REN_Pos) /*!< EADC AD1TRGEN1: EPWM04REN Mask */
<> 144:ef7eb2e8f9f7 11340
<> 144:ef7eb2e8f9f7 11341 #define EADC_AD1TRGEN1_EPWM04FEN_Pos (9) /*!< EADC AD1TRGEN1: EPWM04FEN Position */
<> 144:ef7eb2e8f9f7 11342 #define EADC_AD1TRGEN1_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04FEN_Pos) /*!< EADC AD1TRGEN1: EPWM04FEN Mask */
<> 144:ef7eb2e8f9f7 11343
<> 144:ef7eb2e8f9f7 11344 #define EADC_AD1TRGEN1_EPWM04PEN_Pos (10) /*!< EADC AD1TRGEN1: EPWM04PEN Position */
<> 144:ef7eb2e8f9f7 11345 #define EADC_AD1TRGEN1_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04PEN_Pos) /*!< EADC AD1TRGEN1: EPWM04PEN Mask */
<> 144:ef7eb2e8f9f7 11346
<> 144:ef7eb2e8f9f7 11347 #define EADC_AD1TRGEN1_EPWM04CEN_Pos (11) /*!< EADC AD1TRGEN1: EPWM04CEN Position */
<> 144:ef7eb2e8f9f7 11348 #define EADC_AD1TRGEN1_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM04CEN_Pos) /*!< EADC AD1TRGEN1: EPWM04CEN Mask */
<> 144:ef7eb2e8f9f7 11349
<> 144:ef7eb2e8f9f7 11350 #define EADC_AD1TRGEN1_EPWM10REN_Pos (12) /*!< EADC AD1TRGEN1: EPWM10REN Position */
<> 144:ef7eb2e8f9f7 11351 #define EADC_AD1TRGEN1_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10REN_Pos) /*!< EADC AD1TRGEN1: EPWM10REN Mask */
<> 144:ef7eb2e8f9f7 11352
<> 144:ef7eb2e8f9f7 11353 #define EADC_AD1TRGEN1_EPWM10FEN_Pos (13) /*!< EADC AD1TRGEN1: EPWM10FEN Position */
<> 144:ef7eb2e8f9f7 11354 #define EADC_AD1TRGEN1_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10FEN_Pos) /*!< EADC AD1TRGEN1: EPWM10FEN Mask */
<> 144:ef7eb2e8f9f7 11355
<> 144:ef7eb2e8f9f7 11356 #define EADC_AD1TRGEN1_EPWM10PEN_Pos (14) /*!< EADC AD1TRGEN1: EPWM10PEN Position */
<> 144:ef7eb2e8f9f7 11357 #define EADC_AD1TRGEN1_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10PEN_Pos) /*!< EADC AD1TRGEN1: EPWM10PEN Mask */
<> 144:ef7eb2e8f9f7 11358
<> 144:ef7eb2e8f9f7 11359 #define EADC_AD1TRGEN1_EPWM10CEN_Pos (15) /*!< EADC AD1TRGEN1: EPWM10CEN Position */
<> 144:ef7eb2e8f9f7 11360 #define EADC_AD1TRGEN1_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM10CEN_Pos) /*!< EADC AD1TRGEN1: EPWM10CEN Mask */
<> 144:ef7eb2e8f9f7 11361
<> 144:ef7eb2e8f9f7 11362 #define EADC_AD1TRGEN1_EPWM12REN_Pos (16) /*!< EADC AD1TRGEN1: EPWM12REN Position */
<> 144:ef7eb2e8f9f7 11363 #define EADC_AD1TRGEN1_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12REN_Pos) /*!< EADC AD1TRGEN1: EPWM12REN Mask */
<> 144:ef7eb2e8f9f7 11364
<> 144:ef7eb2e8f9f7 11365 #define EADC_AD1TRGEN1_EPWM120FEN_Pos (17) /*!< EADC AD1TRGEN1: EPWM120FEN Position */
<> 144:ef7eb2e8f9f7 11366 #define EADC_AD1TRGEN1_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM120FEN_Pos) /*!< EADC AD1TRGEN1: EPWM120FEN Mask */
<> 144:ef7eb2e8f9f7 11367
<> 144:ef7eb2e8f9f7 11368 #define EADC_AD1TRGEN1_EPWM12PEN_Pos (18) /*!< EADC AD1TRGEN1: EPWM12PEN Position */
<> 144:ef7eb2e8f9f7 11369 #define EADC_AD1TRGEN1_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12PEN_Pos) /*!< EADC AD1TRGEN1: EPWM12PEN Mask */
<> 144:ef7eb2e8f9f7 11370
<> 144:ef7eb2e8f9f7 11371 #define EADC_AD1TRGEN1_EPWM12CEN_Pos (19) /*!< EADC AD1TRGEN1: EPWM12CEN Position */
<> 144:ef7eb2e8f9f7 11372 #define EADC_AD1TRGEN1_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM12CEN_Pos) /*!< EADC AD1TRGEN1: EPWM12CEN Mask */
<> 144:ef7eb2e8f9f7 11373
<> 144:ef7eb2e8f9f7 11374 #define EADC_AD1TRGEN1_EPWM14REN_Pos (20) /*!< EADC AD1TRGEN1: EPWM14REN Position */
<> 144:ef7eb2e8f9f7 11375 #define EADC_AD1TRGEN1_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14REN_Pos) /*!< EADC AD1TRGEN1: EPWM14REN Mask */
<> 144:ef7eb2e8f9f7 11376
<> 144:ef7eb2e8f9f7 11377 #define EADC_AD1TRGEN1_EPWM14FEN_Pos (21) /*!< EADC AD1TRGEN1: EPWM14FEN Position */
<> 144:ef7eb2e8f9f7 11378 #define EADC_AD1TRGEN1_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14FEN_Pos) /*!< EADC AD1TRGEN1: EPWM14FEN Mask */
<> 144:ef7eb2e8f9f7 11379
<> 144:ef7eb2e8f9f7 11380 #define EADC_AD1TRGEN1_EPWM14PEN_Pos (22) /*!< EADC AD1TRGEN1: EPWM14PEN Position */
<> 144:ef7eb2e8f9f7 11381 #define EADC_AD1TRGEN1_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14PEN_Pos) /*!< EADC AD1TRGEN1: EPWM14PEN Mask */
<> 144:ef7eb2e8f9f7 11382
<> 144:ef7eb2e8f9f7 11383 #define EADC_AD1TRGEN1_EPWM14CEN_Pos (23) /*!< EADC AD1TRGEN1: EPWM14CEN Position */
<> 144:ef7eb2e8f9f7 11384 #define EADC_AD1TRGEN1_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN1_EPWM14CEN_Pos) /*!< EADC AD1TRGEN1: EPWM14CEN Mask */
<> 144:ef7eb2e8f9f7 11385
<> 144:ef7eb2e8f9f7 11386 #define EADC_AD1TRGEN1_PWM00REN_Pos (24) /*!< EADC AD1TRGEN1: PWM00REN Position */
<> 144:ef7eb2e8f9f7 11387 #define EADC_AD1TRGEN1_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00REN_Pos) /*!< EADC AD1TRGEN1: PWM00REN Mask */
<> 144:ef7eb2e8f9f7 11388
<> 144:ef7eb2e8f9f7 11389 #define EADC_AD1TRGEN1_PWM00FEN_Pos (25) /*!< EADC AD1TRGEN1: PWM00FEN Position */
<> 144:ef7eb2e8f9f7 11390 #define EADC_AD1TRGEN1_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00FEN_Pos) /*!< EADC AD1TRGEN1: PWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11391
<> 144:ef7eb2e8f9f7 11392 #define EADC_AD1TRGEN1_PWM00PEN_Pos (26) /*!< EADC AD1TRGEN1: PWM00PEN Position */
<> 144:ef7eb2e8f9f7 11393 #define EADC_AD1TRGEN1_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00PEN_Pos) /*!< EADC AD1TRGEN1: PWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11394
<> 144:ef7eb2e8f9f7 11395 #define EADC_AD1TRGEN1_PWM00CEN_Pos (27) /*!< EADC AD1TRGEN1: PWM00CEN Position */
<> 144:ef7eb2e8f9f7 11396 #define EADC_AD1TRGEN1_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM00CEN_Pos) /*!< EADC AD1TRGEN1: PWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11397
<> 144:ef7eb2e8f9f7 11398 #define EADC_AD1TRGEN1_PWM01REN_Pos (28) /*!< EADC AD1TRGEN1: PWM01REN Position */
<> 144:ef7eb2e8f9f7 11399 #define EADC_AD1TRGEN1_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01REN_Pos) /*!< EADC AD1TRGEN1: PWM01REN Mask */
<> 144:ef7eb2e8f9f7 11400
<> 144:ef7eb2e8f9f7 11401 #define EADC_AD1TRGEN1_PWM01FEN_Pos (29) /*!< EADC AD1TRGEN1: PWM01FEN Position */
<> 144:ef7eb2e8f9f7 11402 #define EADC_AD1TRGEN1_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01FEN_Pos) /*!< EADC AD1TRGEN1: PWM01FEN Mask */
<> 144:ef7eb2e8f9f7 11403
<> 144:ef7eb2e8f9f7 11404 #define EADC_AD1TRGEN1_PWM01PEN_Pos (30) /*!< EADC AD1TRGEN1: PWM01PEN Position */
<> 144:ef7eb2e8f9f7 11405 #define EADC_AD1TRGEN1_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01PEN_Pos) /*!< EADC AD1TRGEN1: PWM01PEN Mask */
<> 144:ef7eb2e8f9f7 11406
<> 144:ef7eb2e8f9f7 11407 #define EADC_AD1TRGEN1_PWM01CEN_Pos (31) /*!< EADC AD1TRGEN1: PWM01CEN Position */
<> 144:ef7eb2e8f9f7 11408 #define EADC_AD1TRGEN1_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN1_PWM01CEN_Pos) /*!< EADC AD1TRGEN1: PWM01CEN Mask */
<> 144:ef7eb2e8f9f7 11409
<> 144:ef7eb2e8f9f7 11410 #define EADC_AD1TRGEN2_EPWM00REN_Pos (0) /*!< EADC AD1TRGEN2: EPWM00REN Position */
<> 144:ef7eb2e8f9f7 11411 #define EADC_AD1TRGEN2_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00REN_Pos) /*!< EADC AD1TRGEN2: EPWM00REN Mask */
<> 144:ef7eb2e8f9f7 11412
<> 144:ef7eb2e8f9f7 11413 #define EADC_AD1TRGEN2_EPWM00FEN_Pos (1) /*!< EADC AD1TRGEN2: EPWM00FEN Position */
<> 144:ef7eb2e8f9f7 11414 #define EADC_AD1TRGEN2_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00FEN_Pos) /*!< EADC AD1TRGEN2: EPWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11415
<> 144:ef7eb2e8f9f7 11416 #define EADC_AD1TRGEN2_EPWM00PEN_Pos (2) /*!< EADC AD1TRGEN2: EPWM00PEN Position */
<> 144:ef7eb2e8f9f7 11417 #define EADC_AD1TRGEN2_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00PEN_Pos) /*!< EADC AD1TRGEN2: EPWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11418
<> 144:ef7eb2e8f9f7 11419 #define EADC_AD1TRGEN2_EPWM00CEN_Pos (3) /*!< EADC AD1TRGEN2: EPWM00CEN Position */
<> 144:ef7eb2e8f9f7 11420 #define EADC_AD1TRGEN2_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM00CEN_Pos) /*!< EADC AD1TRGEN2: EPWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11421
<> 144:ef7eb2e8f9f7 11422 #define EADC_AD1TRGEN2_EPWM02REN_Pos (4) /*!< EADC AD1TRGEN2: EPWM02REN Position */
<> 144:ef7eb2e8f9f7 11423 #define EADC_AD1TRGEN2_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02REN_Pos) /*!< EADC AD1TRGEN2: EPWM02REN Mask */
<> 144:ef7eb2e8f9f7 11424
<> 144:ef7eb2e8f9f7 11425 #define EADC_AD1TRGEN2_EPWM02FEN_Pos (5) /*!< EADC AD1TRGEN2: EPWM02FEN Position */
<> 144:ef7eb2e8f9f7 11426 #define EADC_AD1TRGEN2_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02FEN_Pos) /*!< EADC AD1TRGEN2: EPWM02FEN Mask */
<> 144:ef7eb2e8f9f7 11427
<> 144:ef7eb2e8f9f7 11428 #define EADC_AD1TRGEN2_EPWM02PEN_Pos (6) /*!< EADC AD1TRGEN2: EPWM02PEN Position */
<> 144:ef7eb2e8f9f7 11429 #define EADC_AD1TRGEN2_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02PEN_Pos) /*!< EADC AD1TRGEN2: EPWM02PEN Mask */
<> 144:ef7eb2e8f9f7 11430
<> 144:ef7eb2e8f9f7 11431 #define EADC_AD1TRGEN2_EPWM02CEN_Pos (7) /*!< EADC AD1TRGEN2: EPWM02CEN Position */
<> 144:ef7eb2e8f9f7 11432 #define EADC_AD1TRGEN2_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM02CEN_Pos) /*!< EADC AD1TRGEN2: EPWM02CEN Mask */
<> 144:ef7eb2e8f9f7 11433
<> 144:ef7eb2e8f9f7 11434 #define EADC_AD1TRGEN2_EPWM04REN_Pos (8) /*!< EADC AD1TRGEN2: EPWM04REN Position */
<> 144:ef7eb2e8f9f7 11435 #define EADC_AD1TRGEN2_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04REN_Pos) /*!< EADC AD1TRGEN2: EPWM04REN Mask */
<> 144:ef7eb2e8f9f7 11436
<> 144:ef7eb2e8f9f7 11437 #define EADC_AD1TRGEN2_EPWM04FEN_Pos (9) /*!< EADC AD1TRGEN2: EPWM04FEN Position */
<> 144:ef7eb2e8f9f7 11438 #define EADC_AD1TRGEN2_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04FEN_Pos) /*!< EADC AD1TRGEN2: EPWM04FEN Mask */
<> 144:ef7eb2e8f9f7 11439
<> 144:ef7eb2e8f9f7 11440 #define EADC_AD1TRGEN2_EPWM04PEN_Pos (10) /*!< EADC AD1TRGEN2: EPWM04PEN Position */
<> 144:ef7eb2e8f9f7 11441 #define EADC_AD1TRGEN2_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04PEN_Pos) /*!< EADC AD1TRGEN2: EPWM04PEN Mask */
<> 144:ef7eb2e8f9f7 11442
<> 144:ef7eb2e8f9f7 11443 #define EADC_AD1TRGEN2_EPWM04CEN_Pos (11) /*!< EADC AD1TRGEN2: EPWM04CEN Position */
<> 144:ef7eb2e8f9f7 11444 #define EADC_AD1TRGEN2_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM04CEN_Pos) /*!< EADC AD1TRGEN2: EPWM04CEN Mask */
<> 144:ef7eb2e8f9f7 11445
<> 144:ef7eb2e8f9f7 11446 #define EADC_AD1TRGEN2_EPWM10REN_Pos (12) /*!< EADC AD1TRGEN2: EPWM10REN Position */
<> 144:ef7eb2e8f9f7 11447 #define EADC_AD1TRGEN2_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10REN_Pos) /*!< EADC AD1TRGEN2: EPWM10REN Mask */
<> 144:ef7eb2e8f9f7 11448
<> 144:ef7eb2e8f9f7 11449 #define EADC_AD1TRGEN2_EPWM10FEN_Pos (13) /*!< EADC AD1TRGEN2: EPWM10FEN Position */
<> 144:ef7eb2e8f9f7 11450 #define EADC_AD1TRGEN2_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10FEN_Pos) /*!< EADC AD1TRGEN2: EPWM10FEN Mask */
<> 144:ef7eb2e8f9f7 11451
<> 144:ef7eb2e8f9f7 11452 #define EADC_AD1TRGEN2_EPWM10PEN_Pos (14) /*!< EADC AD1TRGEN2: EPWM10PEN Position */
<> 144:ef7eb2e8f9f7 11453 #define EADC_AD1TRGEN2_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10PEN_Pos) /*!< EADC AD1TRGEN2: EPWM10PEN Mask */
<> 144:ef7eb2e8f9f7 11454
<> 144:ef7eb2e8f9f7 11455 #define EADC_AD1TRGEN2_EPWM10CEN_Pos (15) /*!< EADC AD1TRGEN2: EPWM10CEN Position */
<> 144:ef7eb2e8f9f7 11456 #define EADC_AD1TRGEN2_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM10CEN_Pos) /*!< EADC AD1TRGEN2: EPWM10CEN Mask */
<> 144:ef7eb2e8f9f7 11457
<> 144:ef7eb2e8f9f7 11458 #define EADC_AD1TRGEN2_EPWM12REN_Pos (16) /*!< EADC AD1TRGEN2: EPWM12REN Position */
<> 144:ef7eb2e8f9f7 11459 #define EADC_AD1TRGEN2_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12REN_Pos) /*!< EADC AD1TRGEN2: EPWM12REN Mask */
<> 144:ef7eb2e8f9f7 11460
<> 144:ef7eb2e8f9f7 11461 #define EADC_AD1TRGEN2_EPWM120FEN_Pos (17) /*!< EADC AD1TRGEN2: EPWM120FEN Position */
<> 144:ef7eb2e8f9f7 11462 #define EADC_AD1TRGEN2_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM120FEN_Pos) /*!< EADC AD1TRGEN2: EPWM120FEN Mask */
<> 144:ef7eb2e8f9f7 11463
<> 144:ef7eb2e8f9f7 11464 #define EADC_AD1TRGEN2_EPWM12PEN_Pos (18) /*!< EADC AD1TRGEN2: EPWM12PEN Position */
<> 144:ef7eb2e8f9f7 11465 #define EADC_AD1TRGEN2_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12PEN_Pos) /*!< EADC AD1TRGEN2: EPWM12PEN Mask */
<> 144:ef7eb2e8f9f7 11466
<> 144:ef7eb2e8f9f7 11467 #define EADC_AD1TRGEN2_EPWM12CEN_Pos (19) /*!< EADC AD1TRGEN2: EPWM12CEN Position */
<> 144:ef7eb2e8f9f7 11468 #define EADC_AD1TRGEN2_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM12CEN_Pos) /*!< EADC AD1TRGEN2: EPWM12CEN Mask */
<> 144:ef7eb2e8f9f7 11469
<> 144:ef7eb2e8f9f7 11470 #define EADC_AD1TRGEN2_EPWM14REN_Pos (20) /*!< EADC AD1TRGEN2: EPWM14REN Position */
<> 144:ef7eb2e8f9f7 11471 #define EADC_AD1TRGEN2_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14REN_Pos) /*!< EADC AD1TRGEN2: EPWM14REN Mask */
<> 144:ef7eb2e8f9f7 11472
<> 144:ef7eb2e8f9f7 11473 #define EADC_AD1TRGEN2_EPWM14FEN_Pos (21) /*!< EADC AD1TRGEN2: EPWM14FEN Position */
<> 144:ef7eb2e8f9f7 11474 #define EADC_AD1TRGEN2_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14FEN_Pos) /*!< EADC AD1TRGEN2: EPWM14FEN Mask */
<> 144:ef7eb2e8f9f7 11475
<> 144:ef7eb2e8f9f7 11476 #define EADC_AD1TRGEN2_EPWM14PEN_Pos (22) /*!< EADC AD1TRGEN2: EPWM14PEN Position */
<> 144:ef7eb2e8f9f7 11477 #define EADC_AD1TRGEN2_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14PEN_Pos) /*!< EADC AD1TRGEN2: EPWM14PEN Mask */
<> 144:ef7eb2e8f9f7 11478
<> 144:ef7eb2e8f9f7 11479 #define EADC_AD1TRGEN2_EPWM14CEN_Pos (23) /*!< EADC AD1TRGEN2: EPWM14CEN Position */
<> 144:ef7eb2e8f9f7 11480 #define EADC_AD1TRGEN2_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN2_EPWM14CEN_Pos) /*!< EADC AD1TRGEN2: EPWM14CEN Mask */
<> 144:ef7eb2e8f9f7 11481
<> 144:ef7eb2e8f9f7 11482 #define EADC_AD1TRGEN2_PWM00REN_Pos (24) /*!< EADC AD1TRGEN2: PWM00REN Position */
<> 144:ef7eb2e8f9f7 11483 #define EADC_AD1TRGEN2_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00REN_Pos) /*!< EADC AD1TRGEN2: PWM00REN Mask */
<> 144:ef7eb2e8f9f7 11484
<> 144:ef7eb2e8f9f7 11485 #define EADC_AD1TRGEN2_PWM00FEN_Pos (25) /*!< EADC AD1TRGEN2: PWM00FEN Position */
<> 144:ef7eb2e8f9f7 11486 #define EADC_AD1TRGEN2_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00FEN_Pos) /*!< EADC AD1TRGEN2: PWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11487
<> 144:ef7eb2e8f9f7 11488 #define EADC_AD1TRGEN2_PWM00PEN_Pos (26) /*!< EADC AD1TRGEN2: PWM00PEN Position */
<> 144:ef7eb2e8f9f7 11489 #define EADC_AD1TRGEN2_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00PEN_Pos) /*!< EADC AD1TRGEN2: PWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11490
<> 144:ef7eb2e8f9f7 11491 #define EADC_AD1TRGEN2_PWM00CEN_Pos (27) /*!< EADC AD1TRGEN2: PWM00CEN Position */
<> 144:ef7eb2e8f9f7 11492 #define EADC_AD1TRGEN2_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM00CEN_Pos) /*!< EADC AD1TRGEN2: PWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11493
<> 144:ef7eb2e8f9f7 11494 #define EADC_AD1TRGEN2_PWM01REN_Pos (28) /*!< EADC AD1TRGEN2: PWM01REN Position */
<> 144:ef7eb2e8f9f7 11495 #define EADC_AD1TRGEN2_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01REN_Pos) /*!< EADC AD1TRGEN2: PWM01REN Mask */
<> 144:ef7eb2e8f9f7 11496
<> 144:ef7eb2e8f9f7 11497 #define EADC_AD1TRGEN2_PWM01FEN_Pos (29) /*!< EADC AD1TRGEN2: PWM01FEN Position */
<> 144:ef7eb2e8f9f7 11498 #define EADC_AD1TRGEN2_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01FEN_Pos) /*!< EADC AD1TRGEN2: PWM01FEN Mask */
<> 144:ef7eb2e8f9f7 11499
<> 144:ef7eb2e8f9f7 11500 #define EADC_AD1TRGEN2_PWM01PEN_Pos (30) /*!< EADC AD1TRGEN2: PWM01PEN Position */
<> 144:ef7eb2e8f9f7 11501 #define EADC_AD1TRGEN2_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01PEN_Pos) /*!< EADC AD1TRGEN2: PWM01PEN Mask */
<> 144:ef7eb2e8f9f7 11502
<> 144:ef7eb2e8f9f7 11503 #define EADC_AD1TRGEN2_PWM01CEN_Pos (31) /*!< EADC AD1TRGEN2: PWM01CEN Position */
<> 144:ef7eb2e8f9f7 11504 #define EADC_AD1TRGEN2_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN2_PWM01CEN_Pos) /*!< EADC AD1TRGEN2: PWM01CEN Mask */
<> 144:ef7eb2e8f9f7 11505
<> 144:ef7eb2e8f9f7 11506 #define EADC_AD1TRGEN3_EPWM00REN_Pos (0) /*!< EADC AD1TRGEN3: EPWM00REN Position */
<> 144:ef7eb2e8f9f7 11507 #define EADC_AD1TRGEN3_EPWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00REN_Pos) /*!< EADC AD1TRGEN3: EPWM00REN Mask */
<> 144:ef7eb2e8f9f7 11508
<> 144:ef7eb2e8f9f7 11509 #define EADC_AD1TRGEN3_EPWM00FEN_Pos (1) /*!< EADC AD1TRGEN3: EPWM00FEN Position */
<> 144:ef7eb2e8f9f7 11510 #define EADC_AD1TRGEN3_EPWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00FEN_Pos) /*!< EADC AD1TRGEN3: EPWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11511
<> 144:ef7eb2e8f9f7 11512 #define EADC_AD1TRGEN3_EPWM00PEN_Pos (2) /*!< EADC AD1TRGEN3: EPWM00PEN Position */
<> 144:ef7eb2e8f9f7 11513 #define EADC_AD1TRGEN3_EPWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00PEN_Pos) /*!< EADC AD1TRGEN3: EPWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11514
<> 144:ef7eb2e8f9f7 11515 #define EADC_AD1TRGEN3_EPWM00CEN_Pos (3) /*!< EADC AD1TRGEN3: EPWM00CEN Position */
<> 144:ef7eb2e8f9f7 11516 #define EADC_AD1TRGEN3_EPWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM00CEN_Pos) /*!< EADC AD1TRGEN3: EPWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11517
<> 144:ef7eb2e8f9f7 11518 #define EADC_AD1TRGEN3_EPWM02REN_Pos (4) /*!< EADC AD1TRGEN3: EPWM02REN Position */
<> 144:ef7eb2e8f9f7 11519 #define EADC_AD1TRGEN3_EPWM02REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02REN_Pos) /*!< EADC AD1TRGEN3: EPWM02REN Mask */
<> 144:ef7eb2e8f9f7 11520
<> 144:ef7eb2e8f9f7 11521 #define EADC_AD1TRGEN3_EPWM02FEN_Pos (5) /*!< EADC AD1TRGEN3: EPWM02FEN Position */
<> 144:ef7eb2e8f9f7 11522 #define EADC_AD1TRGEN3_EPWM02FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02FEN_Pos) /*!< EADC AD1TRGEN3: EPWM02FEN Mask */
<> 144:ef7eb2e8f9f7 11523
<> 144:ef7eb2e8f9f7 11524 #define EADC_AD1TRGEN3_EPWM02PEN_Pos (6) /*!< EADC AD1TRGEN3: EPWM02PEN Position */
<> 144:ef7eb2e8f9f7 11525 #define EADC_AD1TRGEN3_EPWM02PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02PEN_Pos) /*!< EADC AD1TRGEN3: EPWM02PEN Mask */
<> 144:ef7eb2e8f9f7 11526
<> 144:ef7eb2e8f9f7 11527 #define EADC_AD1TRGEN3_EPWM02CEN_Pos (7) /*!< EADC AD1TRGEN3: EPWM02CEN Position */
<> 144:ef7eb2e8f9f7 11528 #define EADC_AD1TRGEN3_EPWM02CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM02CEN_Pos) /*!< EADC AD1TRGEN3: EPWM02CEN Mask */
<> 144:ef7eb2e8f9f7 11529
<> 144:ef7eb2e8f9f7 11530 #define EADC_AD1TRGEN3_EPWM04REN_Pos (8) /*!< EADC AD1TRGEN3: EPWM04REN Position */
<> 144:ef7eb2e8f9f7 11531 #define EADC_AD1TRGEN3_EPWM04REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04REN_Pos) /*!< EADC AD1TRGEN3: EPWM04REN Mask */
<> 144:ef7eb2e8f9f7 11532
<> 144:ef7eb2e8f9f7 11533 #define EADC_AD1TRGEN3_EPWM04FEN_Pos (9) /*!< EADC AD1TRGEN3: EPWM04FEN Position */
<> 144:ef7eb2e8f9f7 11534 #define EADC_AD1TRGEN3_EPWM04FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04FEN_Pos) /*!< EADC AD1TRGEN3: EPWM04FEN Mask */
<> 144:ef7eb2e8f9f7 11535
<> 144:ef7eb2e8f9f7 11536 #define EADC_AD1TRGEN3_EPWM04PEN_Pos (10) /*!< EADC AD1TRGEN3: EPWM04PEN Position */
<> 144:ef7eb2e8f9f7 11537 #define EADC_AD1TRGEN3_EPWM04PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04PEN_Pos) /*!< EADC AD1TRGEN3: EPWM04PEN Mask */
<> 144:ef7eb2e8f9f7 11538
<> 144:ef7eb2e8f9f7 11539 #define EADC_AD1TRGEN3_EPWM04CEN_Pos (11) /*!< EADC AD1TRGEN3: EPWM04CEN Position */
<> 144:ef7eb2e8f9f7 11540 #define EADC_AD1TRGEN3_EPWM04CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM04CEN_Pos) /*!< EADC AD1TRGEN3: EPWM04CEN Mask */
<> 144:ef7eb2e8f9f7 11541
<> 144:ef7eb2e8f9f7 11542 #define EADC_AD1TRGEN3_EPWM10REN_Pos (12) /*!< EADC AD1TRGEN3: EPWM10REN Position */
<> 144:ef7eb2e8f9f7 11543 #define EADC_AD1TRGEN3_EPWM10REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10REN_Pos) /*!< EADC AD1TRGEN3: EPWM10REN Mask */
<> 144:ef7eb2e8f9f7 11544
<> 144:ef7eb2e8f9f7 11545 #define EADC_AD1TRGEN3_EPWM10FEN_Pos (13) /*!< EADC AD1TRGEN3: EPWM10FEN Position */
<> 144:ef7eb2e8f9f7 11546 #define EADC_AD1TRGEN3_EPWM10FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10FEN_Pos) /*!< EADC AD1TRGEN3: EPWM10FEN Mask */
<> 144:ef7eb2e8f9f7 11547
<> 144:ef7eb2e8f9f7 11548 #define EADC_AD1TRGEN3_EPWM10PEN_Pos (14) /*!< EADC AD1TRGEN3: EPWM10PEN Position */
<> 144:ef7eb2e8f9f7 11549 #define EADC_AD1TRGEN3_EPWM10PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10PEN_Pos) /*!< EADC AD1TRGEN3: EPWM10PEN Mask */
<> 144:ef7eb2e8f9f7 11550
<> 144:ef7eb2e8f9f7 11551 #define EADC_AD1TRGEN3_EPWM10CEN_Pos (15) /*!< EADC AD1TRGEN3: EPWM10CEN Position */
<> 144:ef7eb2e8f9f7 11552 #define EADC_AD1TRGEN3_EPWM10CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM10CEN_Pos) /*!< EADC AD1TRGEN3: EPWM10CEN Mask */
<> 144:ef7eb2e8f9f7 11553
<> 144:ef7eb2e8f9f7 11554 #define EADC_AD1TRGEN3_EPWM12REN_Pos (16) /*!< EADC AD1TRGEN3: EPWM12REN Position */
<> 144:ef7eb2e8f9f7 11555 #define EADC_AD1TRGEN3_EPWM12REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12REN_Pos) /*!< EADC AD1TRGEN3: EPWM12REN Mask */
<> 144:ef7eb2e8f9f7 11556
<> 144:ef7eb2e8f9f7 11557 #define EADC_AD1TRGEN3_EPWM120FEN_Pos (17) /*!< EADC AD1TRGEN3: EPWM120FEN Position */
<> 144:ef7eb2e8f9f7 11558 #define EADC_AD1TRGEN3_EPWM120FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM120FEN_Pos) /*!< EADC AD1TRGEN3: EPWM120FEN Mask */
<> 144:ef7eb2e8f9f7 11559
<> 144:ef7eb2e8f9f7 11560 #define EADC_AD1TRGEN3_EPWM12PEN_Pos (18) /*!< EADC AD1TRGEN3: EPWM12PEN Position */
<> 144:ef7eb2e8f9f7 11561 #define EADC_AD1TRGEN3_EPWM12PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12PEN_Pos) /*!< EADC AD1TRGEN3: EPWM12PEN Mask */
<> 144:ef7eb2e8f9f7 11562
<> 144:ef7eb2e8f9f7 11563 #define EADC_AD1TRGEN3_EPWM12CEN_Pos (19) /*!< EADC AD1TRGEN3: EPWM12CEN Position */
<> 144:ef7eb2e8f9f7 11564 #define EADC_AD1TRGEN3_EPWM12CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM12CEN_Pos) /*!< EADC AD1TRGEN3: EPWM12CEN Mask */
<> 144:ef7eb2e8f9f7 11565
<> 144:ef7eb2e8f9f7 11566 #define EADC_AD1TRGEN3_EPWM14REN_Pos (20) /*!< EADC AD1TRGEN3: EPWM14REN Position */
<> 144:ef7eb2e8f9f7 11567 #define EADC_AD1TRGEN3_EPWM14REN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14REN_Pos) /*!< EADC AD1TRGEN3: EPWM14REN Mask */
<> 144:ef7eb2e8f9f7 11568
<> 144:ef7eb2e8f9f7 11569 #define EADC_AD1TRGEN3_EPWM14FEN_Pos (21) /*!< EADC AD1TRGEN3: EPWM14FEN Position */
<> 144:ef7eb2e8f9f7 11570 #define EADC_AD1TRGEN3_EPWM14FEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14FEN_Pos) /*!< EADC AD1TRGEN3: EPWM14FEN Mask */
<> 144:ef7eb2e8f9f7 11571
<> 144:ef7eb2e8f9f7 11572 #define EADC_AD1TRGEN3_EPWM14PEN_Pos (22) /*!< EADC AD1TRGEN3: EPWM14PEN Position */
<> 144:ef7eb2e8f9f7 11573 #define EADC_AD1TRGEN3_EPWM14PEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14PEN_Pos) /*!< EADC AD1TRGEN3: EPWM14PEN Mask */
<> 144:ef7eb2e8f9f7 11574
<> 144:ef7eb2e8f9f7 11575 #define EADC_AD1TRGEN3_EPWM14CEN_Pos (23) /*!< EADC AD1TRGEN3: EPWM14CEN Position */
<> 144:ef7eb2e8f9f7 11576 #define EADC_AD1TRGEN3_EPWM14CEN_Msk (0x1ul << EADC_AD1TRGEN3_EPWM14CEN_Pos) /*!< EADC AD1TRGEN3: EPWM14CEN Mask */
<> 144:ef7eb2e8f9f7 11577
<> 144:ef7eb2e8f9f7 11578 #define EADC_AD1TRGEN3_PWM00REN_Pos (24) /*!< EADC AD1TRGEN3: PWM00REN Position */
<> 144:ef7eb2e8f9f7 11579 #define EADC_AD1TRGEN3_PWM00REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00REN_Pos) /*!< EADC AD1TRGEN3: PWM00REN Mask */
<> 144:ef7eb2e8f9f7 11580
<> 144:ef7eb2e8f9f7 11581 #define EADC_AD1TRGEN3_PWM00FEN_Pos (25) /*!< EADC AD1TRGEN3: PWM00FEN Position */
<> 144:ef7eb2e8f9f7 11582 #define EADC_AD1TRGEN3_PWM00FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00FEN_Pos) /*!< EADC AD1TRGEN3: PWM00FEN Mask */
<> 144:ef7eb2e8f9f7 11583
<> 144:ef7eb2e8f9f7 11584 #define EADC_AD1TRGEN3_PWM00PEN_Pos (26) /*!< EADC AD1TRGEN3: PWM00PEN Position */
<> 144:ef7eb2e8f9f7 11585 #define EADC_AD1TRGEN3_PWM00PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00PEN_Pos) /*!< EADC AD1TRGEN3: PWM00PEN Mask */
<> 144:ef7eb2e8f9f7 11586
<> 144:ef7eb2e8f9f7 11587 #define EADC_AD1TRGEN3_PWM00CEN_Pos (27) /*!< EADC AD1TRGEN3: PWM00CEN Position */
<> 144:ef7eb2e8f9f7 11588 #define EADC_AD1TRGEN3_PWM00CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM00CEN_Pos) /*!< EADC AD1TRGEN3: PWM00CEN Mask */
<> 144:ef7eb2e8f9f7 11589
<> 144:ef7eb2e8f9f7 11590 #define EADC_AD1TRGEN3_PWM01REN_Pos (28) /*!< EADC AD1TRGEN3: PWM01REN Position */
<> 144:ef7eb2e8f9f7 11591 #define EADC_AD1TRGEN3_PWM01REN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01REN_Pos) /*!< EADC AD1TRGEN3: PWM01REN Mask */
<> 144:ef7eb2e8f9f7 11592
<> 144:ef7eb2e8f9f7 11593 #define EADC_AD1TRGEN3_PWM01FEN_Pos (29) /*!< EADC AD1TRGEN3: PWM01FEN Position */
<> 144:ef7eb2e8f9f7 11594 #define EADC_AD1TRGEN3_PWM01FEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01FEN_Pos) /*!< EADC AD1TRGEN3: PWM01FEN Mask */
<> 144:ef7eb2e8f9f7 11595
<> 144:ef7eb2e8f9f7 11596 #define EADC_AD1TRGEN3_PWM01PEN_Pos (30) /*!< EADC AD1TRGEN3: PWM01PEN Position */
<> 144:ef7eb2e8f9f7 11597 #define EADC_AD1TRGEN3_PWM01PEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01PEN_Pos) /*!< EADC AD1TRGEN3: PWM01PEN Mask */
<> 144:ef7eb2e8f9f7 11598
<> 144:ef7eb2e8f9f7 11599 #define EADC_AD1TRGEN3_PWM01CEN_Pos (31) /*!< EADC AD1TRGEN3: PWM01CEN Position */
<> 144:ef7eb2e8f9f7 11600 #define EADC_AD1TRGEN3_PWM01CEN_Msk (0x1ul << EADC_AD1TRGEN3_PWM01CEN_Pos) /*!< EADC AD1TRGEN3: PWM01CEN Mask */
<> 144:ef7eb2e8f9f7 11601
<> 144:ef7eb2e8f9f7 11602 /**@}*/ /* EADC_CONST */
<> 144:ef7eb2e8f9f7 11603 /**@}*/ /* end of EADC register group */
<> 144:ef7eb2e8f9f7 11604
<> 144:ef7eb2e8f9f7 11605
<> 144:ef7eb2e8f9f7 11606 /*---------------------- External Bus Interface Controller -------------------------*/
<> 144:ef7eb2e8f9f7 11607 /**
<> 144:ef7eb2e8f9f7 11608 @addtogroup EBI External Bus Interface Controller(EBI)
<> 144:ef7eb2e8f9f7 11609 Memory Mapped Structure for EBI Controller
<> 144:ef7eb2e8f9f7 11610 @{ */
<> 144:ef7eb2e8f9f7 11611
<> 144:ef7eb2e8f9f7 11612 typedef struct {
<> 144:ef7eb2e8f9f7 11613
<> 144:ef7eb2e8f9f7 11614
<> 144:ef7eb2e8f9f7 11615 /**
<> 144:ef7eb2e8f9f7 11616 * CTL
<> 144:ef7eb2e8f9f7 11617 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11618 * Offset: 0x00 External Bus Interface General Control Register
<> 144:ef7eb2e8f9f7 11619 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11620 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11621 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11622 * |[8:10] |MCLKDIV |External Output Clock Divider
<> 144:ef7eb2e8f9f7 11623 * | | |The frequency of EBI output clock is controlled by MCLKDIV as below:
<> 144:ef7eb2e8f9f7 11624 * | | |000 = HCLK/1.
<> 144:ef7eb2e8f9f7 11625 * | | |001 = HCLK/2.
<> 144:ef7eb2e8f9f7 11626 * | | |010 = HCLK/4.
<> 144:ef7eb2e8f9f7 11627 * | | |011 = HCLK/8.
<> 144:ef7eb2e8f9f7 11628 * | | |100 = HCLK/16.
<> 144:ef7eb2e8f9f7 11629 * | | |101 = HCLK/32.
<> 144:ef7eb2e8f9f7 11630 * | | |11x = Default.
<> 144:ef7eb2e8f9f7 11631 * | | |Note: Default value of output clock is HCLK/1
<> 144:ef7eb2e8f9f7 11632 * |[24:27] |CRYPTOEN |Encrypt/Decrypt Function Enable Control (For 4 Individual Chip Select)
<> 144:ef7eb2e8f9f7 11633 * | | |0 = Encrypt/Decrypt function Disabled.
<> 144:ef7eb2e8f9f7 11634 * | | |1 = Encrypt/Decrypt function Enabled.
<> 144:ef7eb2e8f9f7 11635 * |[28:31] |CSPOLINV |Reverse Chip Select
<> 144:ef7eb2e8f9f7 11636 * | | |The original design Chip Select is active low nCS.
<> 144:ef7eb2e8f9f7 11637 * | | |"Chip Select Active High" can be specified by customers-Bit[28+n] is for nCS[n], where n=0~3.
<> 144:ef7eb2e8f9f7 11638 * | | |0 = nCS (chip select active low).
<> 144:ef7eb2e8f9f7 11639 * | | |1 = CS (chip select active high).
<> 144:ef7eb2e8f9f7 11640 */
<> 144:ef7eb2e8f9f7 11641 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 11642
<> 144:ef7eb2e8f9f7 11643 /**
<> 144:ef7eb2e8f9f7 11644 * TCTL
<> 144:ef7eb2e8f9f7 11645 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11646 * Offset: 0x04 - 0x10 External Bus Interface Bank0~3 Timing Control Register
<> 144:ef7eb2e8f9f7 11647 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11648 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11649 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11650 * |[0:2] |TALE |Bank Expand Time Of ALE
<> 144:ef7eb2e8f9f7 11651 * | | |The ALE width (tALE) to latch the address can be controlled by TALE.
<> 144:ef7eb2e8f9f7 11652 * | | |tALE = (TALE+1)*MCLK.
<> 144:ef7eb2e8f9f7 11653 * |[3:7] |TACC |EBI Bank Data Access Time
<> 144:ef7eb2e8f9f7 11654 * | | |TACC define data access time (tACC).
<> 144:ef7eb2e8f9f7 11655 * | | |tACC = (TACC +1) * MCLK.
<> 144:ef7eb2e8f9f7 11656 * |[8:10] |TAHD |EBI Bank Data Access Hold Time
<> 144:ef7eb2e8f9f7 11657 * | | |TAHD define data access hold time (tAHD).
<> 144:ef7eb2e8f9f7 11658 * | | |tAHD = (TAHD +1) * MCLK.
<> 144:ef7eb2e8f9f7 11659 * |[12:15] |W2X |Bank Idle State Cycle After Write
<> 144:ef7eb2e8f9f7 11660 * | | |When write action is finish, idle state is inserted and nCS[0] return to high if W2X is not zero.
<> 144:ef7eb2e8f9f7 11661 * | | |Idle state cycle = (W2X*MCLK).
<> 144:ef7eb2e8f9f7 11662 * | | |0 = reserved.
<> 144:ef7eb2e8f9f7 11663 * |[16:19] |R2W |Bank Idle State Cycle Between Read-Write
<> 144:ef7eb2e8f9f7 11664 * | | |When read action is finish and next action is going to write, idle state is inserted and nCS[0] return to high if R2W is not zero.
<> 144:ef7eb2e8f9f7 11665 * | | |Idle state cycle = (R2W*MCLK).
<> 144:ef7eb2e8f9f7 11666 * | | |0 = reserved.
<> 144:ef7eb2e8f9f7 11667 * |[24:27] |R2R |Bank Idle State Cycle Between Read-Read
<> 144:ef7eb2e8f9f7 11668 * | | |When read action is finish and next action is going to read, idle state is inserted and nCS[0] return to high if R2R is not zero.
<> 144:ef7eb2e8f9f7 11669 * | | |Idle state cycle = (R2R*MCLK).
<> 144:ef7eb2e8f9f7 11670 * | | |0 = reserved.
<> 144:ef7eb2e8f9f7 11671 * |[28] |CSEN |EBI Bank Enable Control
<> 144:ef7eb2e8f9f7 11672 * | | |This bit is the functional enable bit for EBI.
<> 144:ef7eb2e8f9f7 11673 * | | |0 = EBI function Disabled.
<> 144:ef7eb2e8f9f7 11674 * | | |1 = EBI function Enabled.
<> 144:ef7eb2e8f9f7 11675 * |[29] |DW16 |EBI Bank Data Width 16-Bit
<> 144:ef7eb2e8f9f7 11676 * | | |This bit defines if the data bus is 8-bit or 16-bit.
<> 144:ef7eb2e8f9f7 11677 * | | |0 = EBI data width is 8-bit.
<> 144:ef7eb2e8f9f7 11678 * | | |1 = EBI data width is 16-bit.
<> 144:ef7eb2e8f9f7 11679 * |[30] |SEPEN |EBI Bank Address/Data Bus Separating Enable Control
<> 144:ef7eb2e8f9f7 11680 * | | |0 = Address/Data Bus Separating Disabled.
<> 144:ef7eb2e8f9f7 11681 * | | |1 = Address/Data Bus Separating Enabled.
<> 144:ef7eb2e8f9f7 11682 */
<> 144:ef7eb2e8f9f7 11683 __IO uint32_t TCTL[3];
<> 144:ef7eb2e8f9f7 11684
<> 144:ef7eb2e8f9f7 11685 /**
<> 144:ef7eb2e8f9f7 11686 * KEY0
<> 144:ef7eb2e8f9f7 11687 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11688 * Offset: 0x14 External Bus Interface Crypto Key Word 0
<> 144:ef7eb2e8f9f7 11689 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11690 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11691 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11692 * |[0:31] |KEY0 |Crypto Key Word 0 (key[31:0]).
<> 144:ef7eb2e8f9f7 11693 */
<> 144:ef7eb2e8f9f7 11694 __IO uint32_t KEY0;
<> 144:ef7eb2e8f9f7 11695
<> 144:ef7eb2e8f9f7 11696 /**
<> 144:ef7eb2e8f9f7 11697 * KEY1
<> 144:ef7eb2e8f9f7 11698 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11699 * Offset: 0x18 External Bus Interface Crypto Key Word 1
<> 144:ef7eb2e8f9f7 11700 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11701 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11702 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11703 * |[0:31] |KEY |Crypto Key Word 1 (key[63:32]).
<> 144:ef7eb2e8f9f7 11704 */
<> 144:ef7eb2e8f9f7 11705 __IO uint32_t KEY1;
<> 144:ef7eb2e8f9f7 11706
<> 144:ef7eb2e8f9f7 11707 /**
<> 144:ef7eb2e8f9f7 11708 * KEY2
<> 144:ef7eb2e8f9f7 11709 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11710 * Offset: 0x1C External Bus Interface Crypto Key Word 2
<> 144:ef7eb2e8f9f7 11711 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11712 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11713 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11714 * |[0:31] |KEY |Crypto Key Word 2 (key[95:64]).
<> 144:ef7eb2e8f9f7 11715 */
<> 144:ef7eb2e8f9f7 11716 __IO uint32_t KEY2;
<> 144:ef7eb2e8f9f7 11717
<> 144:ef7eb2e8f9f7 11718 /**
<> 144:ef7eb2e8f9f7 11719 * KEY3
<> 144:ef7eb2e8f9f7 11720 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11721 * Offset: 0x20 External Bus Interface Crypto Key Word 3
<> 144:ef7eb2e8f9f7 11722 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11723 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11724 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11725 * |[0:31] |KEY |Crypto Key Word 3 (key[127:96]).
<> 144:ef7eb2e8f9f7 11726 */
<> 144:ef7eb2e8f9f7 11727 __IO uint32_t KEY3;
<> 144:ef7eb2e8f9f7 11728
<> 144:ef7eb2e8f9f7 11729 } EBI_T;
<> 144:ef7eb2e8f9f7 11730
<> 144:ef7eb2e8f9f7 11731 /**
<> 144:ef7eb2e8f9f7 11732 @addtogroup EBI_CONST EBI Bit Field Definition
<> 144:ef7eb2e8f9f7 11733 Constant Definitions for EBI Controller
<> 144:ef7eb2e8f9f7 11734 @{ */
<> 144:ef7eb2e8f9f7 11735
<> 144:ef7eb2e8f9f7 11736 #define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI CTL: MCLKDIV Position */
<> 144:ef7eb2e8f9f7 11737 #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI CTL: MCLKDIV Mask */
<> 144:ef7eb2e8f9f7 11738
<> 144:ef7eb2e8f9f7 11739 #define EBI_CTL_CRYPTOEN_Pos (24) /*!< EBI CTL: CRYPTOEN Position */
<> 144:ef7eb2e8f9f7 11740 #define EBI_CTL_CRYPTOEN_Msk (0xful << EBI_CTL_CRYPTOEN_Pos) /*!< EBI CTL: CRYPTOEN Mask */
<> 144:ef7eb2e8f9f7 11741
<> 144:ef7eb2e8f9f7 11742 #define EBI_CTL_CSPOLINV_Pos (28) /*!< EBI CTL: CSPOLINV Position */
<> 144:ef7eb2e8f9f7 11743 #define EBI_CTL_CSPOLINV_Msk (0xful << EBI_CTL_CSPOLINV_Pos) /*!< EBI CTL: CSPOLINV Mask */
<> 144:ef7eb2e8f9f7 11744
<> 144:ef7eb2e8f9f7 11745 #define EBI_TCTL_TALE_Pos (0) /*!< EBI TCTL: TALE Position */
<> 144:ef7eb2e8f9f7 11746 #define EBI_TCTL_TALE_Msk (0x7ul << EBI_TCTL_TALE_Pos) /*!< EBI TCTL: TALE Mask */
<> 144:ef7eb2e8f9f7 11747
<> 144:ef7eb2e8f9f7 11748 #define EBI_TCTL_TACC_Pos (3) /*!< EBI TCTL: TACC Position */
<> 144:ef7eb2e8f9f7 11749 #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI TCTL: TACC Mask */
<> 144:ef7eb2e8f9f7 11750
<> 144:ef7eb2e8f9f7 11751 #define EBI_TCTL_TAHD_Pos (8) /*!< EBI TCTL: TAHD Position */
<> 144:ef7eb2e8f9f7 11752 #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI TCTL: TAHD Mask */
<> 144:ef7eb2e8f9f7 11753
<> 144:ef7eb2e8f9f7 11754 #define EBI_TCTL_W2X_Pos (12) /*!< EBI TCTL: W2X Position */
<> 144:ef7eb2e8f9f7 11755 #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI TCTL: W2X Mask */
<> 144:ef7eb2e8f9f7 11756
<> 144:ef7eb2e8f9f7 11757 #define EBI_TCTL_R2W_Pos (16) /*!< EBI TCTL: R2W Position */
<> 144:ef7eb2e8f9f7 11758 #define EBI_TCTL_R2W_Msk (0xful << EBI_TCTL_R2W_Pos) /*!< EBI TCTL: R2W Mask */
<> 144:ef7eb2e8f9f7 11759
<> 144:ef7eb2e8f9f7 11760 #define EBI_TCTL_R2R_Pos (24) /*!< EBI TCTL: R2R Position */
<> 144:ef7eb2e8f9f7 11761 #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI TCTL: R2R Mask */
<> 144:ef7eb2e8f9f7 11762
<> 144:ef7eb2e8f9f7 11763 #define EBI_TCTL_CSEN_Pos (28) /*!< EBI TCTL: CSEN Position */
<> 144:ef7eb2e8f9f7 11764 #define EBI_TCTL_CSEN_Msk (0x1ul << EBI_TCTL_CSEN_Pos) /*!< EBI TCTL: CSEN Mask */
<> 144:ef7eb2e8f9f7 11765
<> 144:ef7eb2e8f9f7 11766 #define EBI_TCTL_DW16_Pos (29) /*!< EBI TCTL: DW16 Position */
<> 144:ef7eb2e8f9f7 11767 #define EBI_TCTL_DW16_Msk (0x1ul << EBI_TCTL_DW16_Pos) /*!< EBI TCTL: DW16 Mask */
<> 144:ef7eb2e8f9f7 11768
<> 144:ef7eb2e8f9f7 11769 #define EBI_TCTL_SEPEN_Pos (30) /*!< EBI TCTL: SEPEN Position */
<> 144:ef7eb2e8f9f7 11770 #define EBI_TCTL_SEPEN_Msk (0x1ul << EBI_TCTL_SEPEN_Pos) /*!< EBI TCTL: SEPEN Mask */
<> 144:ef7eb2e8f9f7 11771
<> 144:ef7eb2e8f9f7 11772 #define EBI_KEY0_KEY_Pos (0) /*!< EBI KEY0: KEY Position */
<> 144:ef7eb2e8f9f7 11773 #define EBI_KEY0_KEY_Msk (0xfffffffful << EBI_KEY0_KEY_Pos) /*!< EBI KEY0: KEY Mask */
<> 144:ef7eb2e8f9f7 11774
<> 144:ef7eb2e8f9f7 11775 #define EBI_KEY1_KEY_Pos (0) /*!< EBI KEY1: KEY Position */
<> 144:ef7eb2e8f9f7 11776 #define EBI_KEY1_KEY_Msk (0xfffffffful << EBI_KEY1_KEY_Pos) /*!< EBI KEY1: KEY Mask */
<> 144:ef7eb2e8f9f7 11777
<> 144:ef7eb2e8f9f7 11778 #define EBI_KEY2_KEY_Pos (0) /*!< EBI KEY2: KEY Position */
<> 144:ef7eb2e8f9f7 11779 #define EBI_KEY2_KEY_Msk (0xfffffffful << EBI_KEY2_KEY_Pos) /*!< EBI KEY2: KEY Mask */
<> 144:ef7eb2e8f9f7 11780
<> 144:ef7eb2e8f9f7 11781 #define EBI_KEY3_KEY_Pos (0) /*!< EBI KEY3: KEY Position */
<> 144:ef7eb2e8f9f7 11782 #define EBI_KEY3_KEY_Msk (0xfffffffful << EBI_KEY3_KEY_Pos) /*!< EBI KEY3: KEY Mask */
<> 144:ef7eb2e8f9f7 11783
<> 144:ef7eb2e8f9f7 11784 /**@}*/ /* EBI_CONST */
<> 144:ef7eb2e8f9f7 11785 /**@}*/ /* end of EBI register group */
<> 144:ef7eb2e8f9f7 11786
<> 144:ef7eb2e8f9f7 11787
<> 144:ef7eb2e8f9f7 11788 /*---------------------- Ethernet MAC Controller -------------------------*/
<> 144:ef7eb2e8f9f7 11789 /**
<> 144:ef7eb2e8f9f7 11790 @addtogroup EMAC Ethernet MAC Controller(EMAC)
<> 144:ef7eb2e8f9f7 11791 Memory Mapped Structure for EMAC Controller
<> 144:ef7eb2e8f9f7 11792 @{ */
<> 144:ef7eb2e8f9f7 11793
<> 144:ef7eb2e8f9f7 11794 typedef struct {
<> 144:ef7eb2e8f9f7 11795
<> 144:ef7eb2e8f9f7 11796
<> 144:ef7eb2e8f9f7 11797 /**
<> 144:ef7eb2e8f9f7 11798 * CAMCTL
<> 144:ef7eb2e8f9f7 11799 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11800 * Offset: 0x00 CAM Comparison Control Register
<> 144:ef7eb2e8f9f7 11801 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11802 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11803 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11804 * |[0] |AUP |Accept Unicast Packet
<> 144:ef7eb2e8f9f7 11805 * | | |The AUP controls the unicast packet reception.
<> 144:ef7eb2e8f9f7 11806 * | | |If AUP is enabled, EMAC receives all incoming packet its destination MAC address is a unicast address.
<> 144:ef7eb2e8f9f7 11807 * | | |0 = EMAC receives packet depends on the CAM comparison result.
<> 144:ef7eb2e8f9f7 11808 * | | |1 = EMAC receives all unicast packets.
<> 144:ef7eb2e8f9f7 11809 * |[1] |AMP |Accept Multicast Packet
<> 144:ef7eb2e8f9f7 11810 * | | |The AMP controls the multicast packet reception.
<> 144:ef7eb2e8f9f7 11811 * | | |If AMP is enabled, EMAC receives all incoming packet its destination MAC address is a multicast address.
<> 144:ef7eb2e8f9f7 11812 * | | |0 = EMAC receives packet depends on the CAM comparison result.
<> 144:ef7eb2e8f9f7 11813 * | | |1 = EMAC receives all multicast packets.
<> 144:ef7eb2e8f9f7 11814 * |[2] |ABP |Accept Broadcast Packet
<> 144:ef7eb2e8f9f7 11815 * | | |The ABP controls the broadcast packet reception.
<> 144:ef7eb2e8f9f7 11816 * | | |If ABP is enabled, EMAC receives all incoming packet its destination MAC address is a broadcast address.
<> 144:ef7eb2e8f9f7 11817 * | | |0 = EMAC receives packet depends on the CAM comparison result.
<> 144:ef7eb2e8f9f7 11818 * | | |1 = EMAC receives all broadcast packets.
<> 144:ef7eb2e8f9f7 11819 * |[3] |COMPEN |Complement CAM Comparison Enable
<> 144:ef7eb2e8f9f7 11820 * | | |The COMPEN controls the complement of the CAM comparison result.
<> 144:ef7eb2e8f9f7 11821 * | | |If the CMPEN and COMPEN are both enabled, the incoming packet with specific destination MAC address configured in CAM entry will be dropped.
<> 144:ef7eb2e8f9f7 11822 * | | |And the incoming packet with destination MAC address does not configured in any CAM entry will be received.
<> 144:ef7eb2e8f9f7 11823 * | | |0 = The CAM comparison result does not complement.
<> 144:ef7eb2e8f9f7 11824 * | | |1 = The CAM comparison result complemented.
<> 144:ef7eb2e8f9f7 11825 * |[4] |CMPEN |CAM Compare Enable
<> 144:ef7eb2e8f9f7 11826 * | | |The CMPEN controls the enable of CAM comparison function for destination MAC address recognition.
<> 144:ef7eb2e8f9f7 11827 * | | |If software wants to receive a packet with specific destination MAC address, configures the MAC address into CAM 12~0, then enables that CAM entry and set CMPEN to 1.
<> 144:ef7eb2e8f9f7 11828 * | | |0 = CAM comparison function for destination MAC address recognition disabled.
<> 144:ef7eb2e8f9f7 11829 * | | |1 = CAM comparison function for destination MAC address recognition enabled.
<> 144:ef7eb2e8f9f7 11830 */
<> 144:ef7eb2e8f9f7 11831 __IO uint32_t CAMCTL;
<> 144:ef7eb2e8f9f7 11832
<> 144:ef7eb2e8f9f7 11833 /**
<> 144:ef7eb2e8f9f7 11834 * CAMEN
<> 144:ef7eb2e8f9f7 11835 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11836 * Offset: 0x04 CAM Enable Register
<> 144:ef7eb2e8f9f7 11837 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11838 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11839 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11840 * |[0] |CAMxEN |CAM Entry X Enable Control
<> 144:ef7eb2e8f9f7 11841 * | | |The CAMxEN controls the validation of CAM entry x.
<> 144:ef7eb2e8f9f7 11842 * | | |The CAM entry 13, 14 and 15 are for PAUSE control frame transmission.
<> 144:ef7eb2e8f9f7 11843 * | | |If software wants to transmit a PAUSE control frame out to network, the enable bits of these three CAM entries all must be enabled first.
<> 144:ef7eb2e8f9f7 11844 * | | |0 = CAM entry x Disabled.
<> 144:ef7eb2e8f9f7 11845 * | | |1 = CAM entry x Enabled.
<> 144:ef7eb2e8f9f7 11846 */
<> 144:ef7eb2e8f9f7 11847 __IO uint32_t CAMEN;
<> 144:ef7eb2e8f9f7 11848
<> 144:ef7eb2e8f9f7 11849 /**
<> 144:ef7eb2e8f9f7 11850 * CAM0M
<> 144:ef7eb2e8f9f7 11851 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11852 * Offset: 0x08 CAM0 Most Significant Word Register
<> 144:ef7eb2e8f9f7 11853 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11854 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11855 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11856 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 11857 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 11858 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 11859 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 11860 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 11861 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11862 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11863 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 11864 */
<> 144:ef7eb2e8f9f7 11865 __IO uint32_t CAM0M;
<> 144:ef7eb2e8f9f7 11866
<> 144:ef7eb2e8f9f7 11867 /**
<> 144:ef7eb2e8f9f7 11868 * CAM0L
<> 144:ef7eb2e8f9f7 11869 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11870 * Offset: 0x0C CAM0 Least Significant Word Register
<> 144:ef7eb2e8f9f7 11871 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11872 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11873 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11874 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 11875 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 11876 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 11877 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11878 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11879 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 11880 */
<> 144:ef7eb2e8f9f7 11881 __IO uint32_t CAM0L;
<> 144:ef7eb2e8f9f7 11882
<> 144:ef7eb2e8f9f7 11883 /**
<> 144:ef7eb2e8f9f7 11884 * CAM1M
<> 144:ef7eb2e8f9f7 11885 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11886 * Offset: 0x10 CAM1 Most Significant Word Register
<> 144:ef7eb2e8f9f7 11887 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11888 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11889 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11890 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 11891 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 11892 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 11893 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 11894 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 11895 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11896 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11897 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 11898 */
<> 144:ef7eb2e8f9f7 11899 __IO uint32_t CAM1M;
<> 144:ef7eb2e8f9f7 11900
<> 144:ef7eb2e8f9f7 11901 /**
<> 144:ef7eb2e8f9f7 11902 * CAM1L
<> 144:ef7eb2e8f9f7 11903 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11904 * Offset: 0x14 CAM1 Least Significant Word Register
<> 144:ef7eb2e8f9f7 11905 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11906 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11907 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11908 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 11909 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 11910 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 11911 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11912 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11913 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 11914 */
<> 144:ef7eb2e8f9f7 11915 __IO uint32_t CAM1L;
<> 144:ef7eb2e8f9f7 11916
<> 144:ef7eb2e8f9f7 11917 /**
<> 144:ef7eb2e8f9f7 11918 * CAM2M
<> 144:ef7eb2e8f9f7 11919 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11920 * Offset: 0x18 CAM2 Most Significant Word Register
<> 144:ef7eb2e8f9f7 11921 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11922 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11923 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11924 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 11925 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 11926 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 11927 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 11928 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 11929 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11930 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11931 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 11932 */
<> 144:ef7eb2e8f9f7 11933 __IO uint32_t CAM2M;
<> 144:ef7eb2e8f9f7 11934
<> 144:ef7eb2e8f9f7 11935 /**
<> 144:ef7eb2e8f9f7 11936 * CAM2L
<> 144:ef7eb2e8f9f7 11937 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11938 * Offset: 0x1C CAM2 Least Significant Word Register
<> 144:ef7eb2e8f9f7 11939 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11940 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11941 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11942 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 11943 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 11944 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 11945 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11946 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11947 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 11948 */
<> 144:ef7eb2e8f9f7 11949 __IO uint32_t CAM2L;
<> 144:ef7eb2e8f9f7 11950
<> 144:ef7eb2e8f9f7 11951 /**
<> 144:ef7eb2e8f9f7 11952 * CAM3M
<> 144:ef7eb2e8f9f7 11953 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11954 * Offset: 0x20 CAM3 Most Significant Word Register
<> 144:ef7eb2e8f9f7 11955 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11956 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11957 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11958 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 11959 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 11960 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 11961 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 11962 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 11963 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11964 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11965 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 11966 */
<> 144:ef7eb2e8f9f7 11967 __IO uint32_t CAM3M;
<> 144:ef7eb2e8f9f7 11968
<> 144:ef7eb2e8f9f7 11969 /**
<> 144:ef7eb2e8f9f7 11970 * CAM3L
<> 144:ef7eb2e8f9f7 11971 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11972 * Offset: 0x24 CAM3 Least Significant Word Register
<> 144:ef7eb2e8f9f7 11973 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11974 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11975 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11976 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 11977 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 11978 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 11979 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11980 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11981 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 11982 */
<> 144:ef7eb2e8f9f7 11983 __IO uint32_t CAM3L;
<> 144:ef7eb2e8f9f7 11984
<> 144:ef7eb2e8f9f7 11985 /**
<> 144:ef7eb2e8f9f7 11986 * CAM4M
<> 144:ef7eb2e8f9f7 11987 * ===================================================================================================
<> 144:ef7eb2e8f9f7 11988 * Offset: 0x28 CAM4 Most Significant Word Register
<> 144:ef7eb2e8f9f7 11989 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 11990 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 11991 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 11992 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 11993 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 11994 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 11995 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 11996 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 11997 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 11998 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 11999 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12000 */
<> 144:ef7eb2e8f9f7 12001 __IO uint32_t CAM4M;
<> 144:ef7eb2e8f9f7 12002
<> 144:ef7eb2e8f9f7 12003 /**
<> 144:ef7eb2e8f9f7 12004 * CAM4L
<> 144:ef7eb2e8f9f7 12005 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12006 * Offset: 0x2C CAM4 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12007 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12008 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12009 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12010 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12011 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12012 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12013 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12014 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12015 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12016 */
<> 144:ef7eb2e8f9f7 12017 __IO uint32_t CAM4L;
<> 144:ef7eb2e8f9f7 12018
<> 144:ef7eb2e8f9f7 12019 /**
<> 144:ef7eb2e8f9f7 12020 * CAM5M
<> 144:ef7eb2e8f9f7 12021 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12022 * Offset: 0x30 CAM5 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12023 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12024 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12025 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12026 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12027 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12028 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12029 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12030 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12031 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12032 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12033 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12034 */
<> 144:ef7eb2e8f9f7 12035 __IO uint32_t CAM5M;
<> 144:ef7eb2e8f9f7 12036
<> 144:ef7eb2e8f9f7 12037 /**
<> 144:ef7eb2e8f9f7 12038 * CAM5L
<> 144:ef7eb2e8f9f7 12039 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12040 * Offset: 0x34 CAM5 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12041 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12042 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12043 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12044 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12045 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12046 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12047 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12048 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12049 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12050 */
<> 144:ef7eb2e8f9f7 12051 __IO uint32_t CAM5L;
<> 144:ef7eb2e8f9f7 12052
<> 144:ef7eb2e8f9f7 12053 /**
<> 144:ef7eb2e8f9f7 12054 * CAM6M
<> 144:ef7eb2e8f9f7 12055 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12056 * Offset: 0x38 CAM6 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12057 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12058 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12059 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12060 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12061 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12062 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12063 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12064 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12065 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12066 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12067 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12068 */
<> 144:ef7eb2e8f9f7 12069 __IO uint32_t CAM6M;
<> 144:ef7eb2e8f9f7 12070
<> 144:ef7eb2e8f9f7 12071 /**
<> 144:ef7eb2e8f9f7 12072 * CAM6L
<> 144:ef7eb2e8f9f7 12073 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12074 * Offset: 0x3C CAM6 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12075 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12076 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12077 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12078 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12079 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12080 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12081 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12082 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12083 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12084 */
<> 144:ef7eb2e8f9f7 12085 __IO uint32_t CAM6L;
<> 144:ef7eb2e8f9f7 12086
<> 144:ef7eb2e8f9f7 12087 /**
<> 144:ef7eb2e8f9f7 12088 * CAM7M
<> 144:ef7eb2e8f9f7 12089 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12090 * Offset: 0x40 CAM7 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12091 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12092 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12093 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12094 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12095 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12096 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12097 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12098 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12099 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12100 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12101 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12102 */
<> 144:ef7eb2e8f9f7 12103 __IO uint32_t CAM7M;
<> 144:ef7eb2e8f9f7 12104
<> 144:ef7eb2e8f9f7 12105 /**
<> 144:ef7eb2e8f9f7 12106 * CAM7L
<> 144:ef7eb2e8f9f7 12107 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12108 * Offset: 0x44 CAM7 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12109 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12110 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12111 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12112 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12113 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12114 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12115 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12116 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12117 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12118 */
<> 144:ef7eb2e8f9f7 12119 __IO uint32_t CAM7L;
<> 144:ef7eb2e8f9f7 12120
<> 144:ef7eb2e8f9f7 12121 /**
<> 144:ef7eb2e8f9f7 12122 * CAM8M
<> 144:ef7eb2e8f9f7 12123 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12124 * Offset: 0x48 CAM8 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12125 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12126 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12127 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12128 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12129 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12130 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12131 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12132 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12133 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12134 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12135 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12136 */
<> 144:ef7eb2e8f9f7 12137 __IO uint32_t CAM8M;
<> 144:ef7eb2e8f9f7 12138
<> 144:ef7eb2e8f9f7 12139 /**
<> 144:ef7eb2e8f9f7 12140 * CAM8L
<> 144:ef7eb2e8f9f7 12141 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12142 * Offset: 0x4C CAM8 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12143 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12144 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12145 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12146 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12147 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12148 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12149 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12150 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12151 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12152 */
<> 144:ef7eb2e8f9f7 12153 __IO uint32_t CAM8L;
<> 144:ef7eb2e8f9f7 12154
<> 144:ef7eb2e8f9f7 12155 /**
<> 144:ef7eb2e8f9f7 12156 * CAM9M
<> 144:ef7eb2e8f9f7 12157 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12158 * Offset: 0x50 CAM9 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12159 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12160 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12161 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12162 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12163 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12164 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12165 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12166 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12167 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12168 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12169 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12170 */
<> 144:ef7eb2e8f9f7 12171 __IO uint32_t CAM9M;
<> 144:ef7eb2e8f9f7 12172
<> 144:ef7eb2e8f9f7 12173 /**
<> 144:ef7eb2e8f9f7 12174 * CAM9L
<> 144:ef7eb2e8f9f7 12175 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12176 * Offset: 0x54 CAM9 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12177 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12178 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12179 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12180 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12181 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12182 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12183 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12184 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12185 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12186 */
<> 144:ef7eb2e8f9f7 12187 __IO uint32_t CAM9L;
<> 144:ef7eb2e8f9f7 12188
<> 144:ef7eb2e8f9f7 12189 /**
<> 144:ef7eb2e8f9f7 12190 * CAM10M
<> 144:ef7eb2e8f9f7 12191 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12192 * Offset: 0x58 CAM10 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12193 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12194 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12195 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12196 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12197 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12198 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12199 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12200 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12201 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12202 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12203 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12204 */
<> 144:ef7eb2e8f9f7 12205 __IO uint32_t CAM10M;
<> 144:ef7eb2e8f9f7 12206
<> 144:ef7eb2e8f9f7 12207 /**
<> 144:ef7eb2e8f9f7 12208 * CAM10L
<> 144:ef7eb2e8f9f7 12209 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12210 * Offset: 0x5C CAM10 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12211 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12212 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12213 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12214 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12215 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12216 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12217 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12218 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12219 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12220 */
<> 144:ef7eb2e8f9f7 12221 __IO uint32_t CAM10L;
<> 144:ef7eb2e8f9f7 12222
<> 144:ef7eb2e8f9f7 12223 /**
<> 144:ef7eb2e8f9f7 12224 * CAM11M
<> 144:ef7eb2e8f9f7 12225 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12226 * Offset: 0x60 CAM11 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12227 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12228 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12229 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12230 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12231 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12232 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12233 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12234 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12235 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12236 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12237 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12238 */
<> 144:ef7eb2e8f9f7 12239 __IO uint32_t CAM11M;
<> 144:ef7eb2e8f9f7 12240
<> 144:ef7eb2e8f9f7 12241 /**
<> 144:ef7eb2e8f9f7 12242 * CAM11L
<> 144:ef7eb2e8f9f7 12243 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12244 * Offset: 0x64 CAM11 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12245 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12246 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12247 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12248 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12249 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12250 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12251 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12252 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12253 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12254 */
<> 144:ef7eb2e8f9f7 12255 __IO uint32_t CAM11L;
<> 144:ef7eb2e8f9f7 12256
<> 144:ef7eb2e8f9f7 12257 /**
<> 144:ef7eb2e8f9f7 12258 * CAM12M
<> 144:ef7eb2e8f9f7 12259 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12260 * Offset: 0x68 CAM12 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12261 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12262 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12263 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12264 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12265 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12266 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12267 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12268 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12269 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12270 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12271 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12272 */
<> 144:ef7eb2e8f9f7 12273 __IO uint32_t CAM12M;
<> 144:ef7eb2e8f9f7 12274
<> 144:ef7eb2e8f9f7 12275 /**
<> 144:ef7eb2e8f9f7 12276 * CAM12L
<> 144:ef7eb2e8f9f7 12277 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12278 * Offset: 0x6C CAM12 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12279 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12280 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12281 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12282 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12283 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12284 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12285 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12286 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12287 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12288 */
<> 144:ef7eb2e8f9f7 12289 __IO uint32_t CAM12L;
<> 144:ef7eb2e8f9f7 12290
<> 144:ef7eb2e8f9f7 12291 /**
<> 144:ef7eb2e8f9f7 12292 * CAM13M
<> 144:ef7eb2e8f9f7 12293 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12294 * Offset: 0x70 CAM13 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12295 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12296 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12297 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12298 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12299 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12300 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12301 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12302 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12303 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12304 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12305 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12306 */
<> 144:ef7eb2e8f9f7 12307 __IO uint32_t CAM13M;
<> 144:ef7eb2e8f9f7 12308
<> 144:ef7eb2e8f9f7 12309 /**
<> 144:ef7eb2e8f9f7 12310 * CAM13L
<> 144:ef7eb2e8f9f7 12311 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12312 * Offset: 0x74 CAM13 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12313 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12314 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12315 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12316 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12317 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12318 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12319 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12320 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12321 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12322 */
<> 144:ef7eb2e8f9f7 12323 __IO uint32_t CAM13L;
<> 144:ef7eb2e8f9f7 12324
<> 144:ef7eb2e8f9f7 12325 /**
<> 144:ef7eb2e8f9f7 12326 * CAM14M
<> 144:ef7eb2e8f9f7 12327 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12328 * Offset: 0x78 CAM14 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12329 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12330 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12331 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12332 * |[0:7] |MACADDR2 |MAC Address Byte 2
<> 144:ef7eb2e8f9f7 12333 * |[8:15] |MACADDR3 |MAC Address Byte 3
<> 144:ef7eb2e8f9f7 12334 * |[16:23] |MACADDR4 |MAC Address Byte 4
<> 144:ef7eb2e8f9f7 12335 * |[24:31] |MACADDR5 |MAC Address Byte 5
<> 144:ef7eb2e8f9f7 12336 * | | |The CAMxM keeps the bit 47~16 of MAC address.
<> 144:ef7eb2e8f9f7 12337 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12338 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12339 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12340 */
<> 144:ef7eb2e8f9f7 12341 __IO uint32_t CAM14M;
<> 144:ef7eb2e8f9f7 12342
<> 144:ef7eb2e8f9f7 12343 /**
<> 144:ef7eb2e8f9f7 12344 * CAM14L
<> 144:ef7eb2e8f9f7 12345 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12346 * Offset: 0x7C CAM14 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12347 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12348 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12349 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12350 * |[16:23] |MACADDR0 |MAC Address Byte 0
<> 144:ef7eb2e8f9f7 12351 * |[24:31] |MACADDR1 |MAC Address Byte 1
<> 144:ef7eb2e8f9f7 12352 * | | |The CAMxL keeps the bit 15~0 of MAC address.
<> 144:ef7eb2e8f9f7 12353 * | | |The x can be the 0~14.
<> 144:ef7eb2e8f9f7 12354 * | | |The register pair {EMAC_CAMxMSB, EMAC_CAMxLSB} represents a CAM entry and keeps a MAC address.
<> 144:ef7eb2e8f9f7 12355 * | | |For example, if the MAC address 00-50-BA-33-BA-44 kept in CAM entry 1, the register EMAC_CAM1M is 0x0050_BA33 and EMAC_CAM1L is 0xBA44_0000.
<> 144:ef7eb2e8f9f7 12356 */
<> 144:ef7eb2e8f9f7 12357 __IO uint32_t CAM14L;
<> 144:ef7eb2e8f9f7 12358
<> 144:ef7eb2e8f9f7 12359 /**
<> 144:ef7eb2e8f9f7 12360 * CAM15MSB
<> 144:ef7eb2e8f9f7 12361 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12362 * Offset: 0x80 CAM15 Most Significant Word Register
<> 144:ef7eb2e8f9f7 12363 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12364 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12365 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12366 * |[0:15] |OPCODE |OP Code Field of PAUSE Control Frame
<> 144:ef7eb2e8f9f7 12367 * | | |In the PAUSE control frame, an op code field defined and is 0x0001.
<> 144:ef7eb2e8f9f7 12368 * |[16:31] |LENGTH |LENGTH Field of PAUSE Control Frame
<> 144:ef7eb2e8f9f7 12369 * | | |In the PAUSE control frame, a LENGTH field defined and is 0x8808.
<> 144:ef7eb2e8f9f7 12370 */
<> 144:ef7eb2e8f9f7 12371 __IO uint32_t CAM15MSB;
<> 144:ef7eb2e8f9f7 12372
<> 144:ef7eb2e8f9f7 12373 /**
<> 144:ef7eb2e8f9f7 12374 * CAM15LSB
<> 144:ef7eb2e8f9f7 12375 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12376 * Offset: 0x84 CAM15 Least Significant Word Register
<> 144:ef7eb2e8f9f7 12377 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12378 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12379 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12380 * |[24:31] |OPERAND |Pause Parameter
<> 144:ef7eb2e8f9f7 12381 * | | |In the PAUSE control frame, an OPERAND field defined and controls how much time the destination Ethernet MAC Controller paused.
<> 144:ef7eb2e8f9f7 12382 * | | |The unit of the OPERAND is a slot time, the 512 bits time.
<> 144:ef7eb2e8f9f7 12383 */
<> 144:ef7eb2e8f9f7 12384 __IO uint32_t CAM15LSB;
<> 144:ef7eb2e8f9f7 12385
<> 144:ef7eb2e8f9f7 12386 /**
<> 144:ef7eb2e8f9f7 12387 * TXDSA
<> 144:ef7eb2e8f9f7 12388 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12389 * Offset: 0x88 Transmit Descriptor Link List Start Address Register
<> 144:ef7eb2e8f9f7 12390 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12391 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12392 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12393 * |[0:31] |TXDSA |Transmit Descriptor Link-List Start Address
<> 144:ef7eb2e8f9f7 12394 * | | |The TXDSA keeps the start address of transmit descriptor link-list.
<> 144:ef7eb2e8f9f7 12395 * | | |If the software enables the bit TXON (EMAC_CTL[8]), the content of TXDSA will be loaded into the current transmit descriptor start address register (EMAC_CTXDSA).
<> 144:ef7eb2e8f9f7 12396 * | | |The TXDSA does not be updated by EMAC.
<> 144:ef7eb2e8f9f7 12397 * | | |During the operation, EMAC will ignore the bits [1:0] of TXDSA.
<> 144:ef7eb2e8f9f7 12398 * | | |This means that each TX descriptor always must locate at word boundary memory address.
<> 144:ef7eb2e8f9f7 12399 */
<> 144:ef7eb2e8f9f7 12400 __IO uint32_t TXDSA;
<> 144:ef7eb2e8f9f7 12401
<> 144:ef7eb2e8f9f7 12402 /**
<> 144:ef7eb2e8f9f7 12403 * RXDSA
<> 144:ef7eb2e8f9f7 12404 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12405 * Offset: 0x8C Receive Descriptor Link List Start Address Register
<> 144:ef7eb2e8f9f7 12406 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12407 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12408 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12409 * |[0:31] |RXDSA |Receive Descriptor Link-List Start Address
<> 144:ef7eb2e8f9f7 12410 * | | |The RXDSA keeps the start address of receive descriptor link-list.
<> 144:ef7eb2e8f9f7 12411 * | | |If the S/W enables the bit RXON (EMAC_CTL[0]), the content of RXDSA will be loaded into the current receive descriptor start address register (EMAC_CRXDSA).
<> 144:ef7eb2e8f9f7 12412 * | | |The RXDSA does not be updated by EMAC.
<> 144:ef7eb2e8f9f7 12413 * | | |During the operation, EMAC will ignore the bits [1:0] of RXDSA.
<> 144:ef7eb2e8f9f7 12414 * | | |This means that each RX descriptor always must locate at word boundary memory address.
<> 144:ef7eb2e8f9f7 12415 */
<> 144:ef7eb2e8f9f7 12416 __IO uint32_t RXDSA;
<> 144:ef7eb2e8f9f7 12417
<> 144:ef7eb2e8f9f7 12418 /**
<> 144:ef7eb2e8f9f7 12419 * CTL
<> 144:ef7eb2e8f9f7 12420 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12421 * Offset: 0x90 MAC Control Register
<> 144:ef7eb2e8f9f7 12422 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12423 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12424 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12425 * |[0] |RXON |Frame Reception ON
<> 144:ef7eb2e8f9f7 12426 * | | |The RXON controls the normal packet reception of EMAC.
<> 144:ef7eb2e8f9f7 12427 * | | |If the RXON is set to high, the EMAC starts the packet reception process, including the RX descriptor fetching, packet reception and RX descriptor modification.
<> 144:ef7eb2e8f9f7 12428 * | | |It is necessary to finish EMAC initial sequence before enable RXON.
<> 144:ef7eb2e8f9f7 12429 * | | |Otherwise, the EMAC operation is undefined.
<> 144:ef7eb2e8f9f7 12430 * | | |If the RXON is disabled during EMAC is receiving an incoming packet, the EMAC stops the packet reception process after the current packet reception finished.
<> 144:ef7eb2e8f9f7 12431 * | | |0 = Packet reception process stopped.
<> 144:ef7eb2e8f9f7 12432 * | | |1 = Packet reception process started.
<> 144:ef7eb2e8f9f7 12433 * |[1] |ALP |Accept Long Packet
<> 144:ef7eb2e8f9f7 12434 * | | |The ALP controls the long packet, which packet length is greater than 1518 bytes, reception.
<> 144:ef7eb2e8f9f7 12435 * | | |If the ALP is set to high, the EMAC will accept the long packet.
<> 144:ef7eb2e8f9f7 12436 * | | |Otherwise, the long packet will be dropped.
<> 144:ef7eb2e8f9f7 12437 * | | |0 = Ethernet MAC controller dropped the long packet.
<> 144:ef7eb2e8f9f7 12438 * | | |1 = Ethernet MAC controller received the long packet.
<> 144:ef7eb2e8f9f7 12439 * |[2] |ARP |Accept Runt Packet
<> 144:ef7eb2e8f9f7 12440 * | | |The ARP controls the runt packet, which length is less than 64 bytes, reception.
<> 144:ef7eb2e8f9f7 12441 * | | |If the ARP is set to high, the EMAC will accept the runt packet.
<> 144:ef7eb2e8f9f7 12442 * | | |Otherwise, the runt packet will be dropped.
<> 144:ef7eb2e8f9f7 12443 * | | |0 = Ethernet MAC controller dropped the runt packet.
<> 144:ef7eb2e8f9f7 12444 * | | |1 = Ethernet MAC controller received the runt packet.
<> 144:ef7eb2e8f9f7 12445 * |[3] |ACP |Accept Control Packet
<> 144:ef7eb2e8f9f7 12446 * | | |The ACP controls the control frame reception.
<> 144:ef7eb2e8f9f7 12447 * | | |If the ACP is set to high, the EMAC will accept the control frame.
<> 144:ef7eb2e8f9f7 12448 * | | |Otherwise, the control frame will be dropped.
<> 144:ef7eb2e8f9f7 12449 * | | |It is recommended that S/W only enable ACP while EMAC is operating on full duplex mode.
<> 144:ef7eb2e8f9f7 12450 * | | |0 = Ethernet MAC controller dropped the control frame.
<> 144:ef7eb2e8f9f7 12451 * | | |1 = Ethernet MAC controller received the control frame.
<> 144:ef7eb2e8f9f7 12452 * |[4] |AEP |Accept CRC Error Packet
<> 144:ef7eb2e8f9f7 12453 * | | |The AEP controls the EMAC accepts or drops the CRC error packet.
<> 144:ef7eb2e8f9f7 12454 * | | |If the AEP is set to high, the incoming packet with CRC error will be received by EMAC as a good packet.
<> 144:ef7eb2e8f9f7 12455 * | | |0 = Ethernet MAC controller dropped the CRC error packet.
<> 144:ef7eb2e8f9f7 12456 * | | |1 = Ethernet MAC controller received the CRC error packet.
<> 144:ef7eb2e8f9f7 12457 * |[5] |STRIPCRC |Strip CRC Checksum
<> 144:ef7eb2e8f9f7 12458 * | | |The STRIPCRC controls if the length of incoming packet is calculated with 4 bytes CRC checksum.
<> 144:ef7eb2e8f9f7 12459 * | | |If the STRIPCRC is set to high, 4 bytes CRC checksum is excluded from length calculation of incoming packet.
<> 144:ef7eb2e8f9f7 12460 * | | |0 = The 4 bytes CRC checksum is included in packet length calculation.
<> 144:ef7eb2e8f9f7 12461 * | | |1 = The 4 bytes CRC checksum is excluded in packet length calculation.
<> 144:ef7eb2e8f9f7 12462 * |[6] |WOLEN |Wake On LAN Enable
<> 144:ef7eb2e8f9f7 12463 * | | |The WOLEN high enables the functionality that Ethernet MAC controller checked if the incoming packet is Magic Packet and wakeup system from Power-down mode.
<> 144:ef7eb2e8f9f7 12464 * | | |If incoming packet was a Magic Packet and the system was in Power-down, the Ethernet MAC controller would generate a wakeup event to wake system up from Power-down mode.
<> 144:ef7eb2e8f9f7 12465 * | | |0 = Wake-up by Magic Packet function Disabled.
<> 144:ef7eb2e8f9f7 12466 * | | |1 = Wake-up by Magic Packet function Enabled.
<> 144:ef7eb2e8f9f7 12467 * |[8] |TXON |Frame Transmission ON
<> 144:ef7eb2e8f9f7 12468 * | | |The TXON controls the normal packet transmission of EMAC.
<> 144:ef7eb2e8f9f7 12469 * | | |If the TXON is set to high, the EMAC starts the packet transmission process, including the TX descriptor fetching, packet transmission and TX descriptor modification.
<> 144:ef7eb2e8f9f7 12470 * | | |It is must to finish EMAC initial sequence before enable TXON.
<> 144:ef7eb2e8f9f7 12471 * | | |Otherwise, the EMAC operation is undefined.
<> 144:ef7eb2e8f9f7 12472 * | | |If the TXON is disabled during EMAC is transmitting a packet out, the EMAC stops the packet transmission process after the current packet transmission finished.
<> 144:ef7eb2e8f9f7 12473 * | | |0 = Packet transmission process stopped.
<> 144:ef7eb2e8f9f7 12474 * | | |1 = Packet transmission process started.
<> 144:ef7eb2e8f9f7 12475 * |[9] |NODEF |No Deferral
<> 144:ef7eb2e8f9f7 12476 * | | |The NODEF controls the enable of deferral exceed counter.
<> 144:ef7eb2e8f9f7 12477 * | | |If NODEF is set to high, the deferral exceed counter is disabled.
<> 144:ef7eb2e8f9f7 12478 * | | |The NODEF is only useful while EMAC is operating on half duplex mode.
<> 144:ef7eb2e8f9f7 12479 * | | |0 = The deferral exceed counter Enabled.
<> 144:ef7eb2e8f9f7 12480 * | | |1 = The deferral exceed counter Disabled.
<> 144:ef7eb2e8f9f7 12481 * |[16] |SDPZ |Send PAUSE Frame
<> 144:ef7eb2e8f9f7 12482 * | | |The SDPZ controls the PAUSE control frame transmission.
<> 144:ef7eb2e8f9f7 12483 * | | |If S/W wants to send a PAUSE control frame out, the CAM entry 13, 14 and 15 must be configured first and the corresponding CAM enable bit of CAMEN register also must be set.
<> 144:ef7eb2e8f9f7 12484 * | | |Then, set SDPZ to 1 enables the PAUSE control frame transmission.
<> 144:ef7eb2e8f9f7 12485 * | | |The SDPZ is a self-clear bit.
<> 144:ef7eb2e8f9f7 12486 * | | |This means after the PAUSE control frame transmission has completed, the SDPZ will be cleared automatically.
<> 144:ef7eb2e8f9f7 12487 * | | |It is recommended that only enabling SNDPAUSE while EMAC is operating in Full Duplex mode.
<> 144:ef7eb2e8f9f7 12488 * | | |0 = PAUSE control frame transmission completed.
<> 144:ef7eb2e8f9f7 12489 * | | |1 = PAUSE control frame transmission Enabled.
<> 144:ef7eb2e8f9f7 12490 * |[17] |SQECHKEN |SQE Checking Enable
<> 144:ef7eb2e8f9f7 12491 * | | |The SQECHKEN controls the enable of SQE checking.
<> 144:ef7eb2e8f9f7 12492 * | | |The SQE checking is only available while EMAC is operating on 10M bps and half duplex mode.
<> 144:ef7eb2e8f9f7 12493 * | | |In other words, the SQECHKEN cannot affect EMAC operation, if the EMAC is operating on 100M bps or full duplex mode.
<> 144:ef7eb2e8f9f7 12494 * | | |0 = SQE checking Disabled while EMAC is operating in 10Mbps and Half Duplex mode.
<> 144:ef7eb2e8f9f7 12495 * | | |1 = SQE checking Enabled while EMAC is operating in 10Mbps and Half Duplex mode.
<> 144:ef7eb2e8f9f7 12496 * |[18] |FUDUP |Full Duplex Mode Selection
<> 144:ef7eb2e8f9f7 12497 * | | |The FUDUP controls that if EMAC is operating on full or half duplex mode.
<> 144:ef7eb2e8f9f7 12498 * | | |0 = EMAC operates in half duplex mode.
<> 144:ef7eb2e8f9f7 12499 * | | |1 = EMAC operates in full duplex mode.
<> 144:ef7eb2e8f9f7 12500 * |[19] |RMIIRXCTL |RMII RX Control
<> 144:ef7eb2e8f9f7 12501 * | | |The RMIIRXCTL control the receive data sample in RMII mode.
<> 144:ef7eb2e8f9f7 12502 * | | |It's necessary to set this bit high when RMIIEN (EMAC_CTL[ [22]) is high.
<> 144:ef7eb2e8f9f7 12503 * | | |0 = RMII RX control disabled.
<> 144:ef7eb2e8f9f7 12504 * | | |1 = RMII RX control enabled.
<> 144:ef7eb2e8f9f7 12505 * |[20] |OPMODE |Operation Mode Selection
<> 144:ef7eb2e8f9f7 12506 * | | |The OPMODE defines that if the EMAC is operating on 10M or 100M bps mode.
<> 144:ef7eb2e8f9f7 12507 * | | |The RST (EMAC_CTL[24]) would not affect OPMODE value.
<> 144:ef7eb2e8f9f7 12508 * | | |0 = EMAC operates in 10Mbps mode.
<> 144:ef7eb2e8f9f7 12509 * | | |1 = EMAC operates in 100Mbps mode.
<> 144:ef7eb2e8f9f7 12510 * |[22] |RMIIEN |RMII Mode Enable
<> 144:ef7eb2e8f9f7 12511 * | | |This bit controls if Ethernet MAC controller connected with off-chip Ethernet PHY by MII interface or RMII interface.
<> 144:ef7eb2e8f9f7 12512 * | | |The RST (EMAC_CTL[24]) would not affect RMIIEN value.
<> 144:ef7eb2e8f9f7 12513 * | | |0 = Ethernet MAC controller MII mode Enabled.
<> 144:ef7eb2e8f9f7 12514 * | | |1 = Ethernet MAC controller RMII mode Enabled.
<> 144:ef7eb2e8f9f7 12515 * |[24] |RST |Software Reset
<> 144:ef7eb2e8f9f7 12516 * | | |The RST implements a reset function to make the EMAC return default state.
<> 144:ef7eb2e8f9f7 12517 * | | |The RST is a self-clear bit.
<> 144:ef7eb2e8f9f7 12518 * | | |This means after the software reset finished, the RST will be cleared automatically.
<> 144:ef7eb2e8f9f7 12519 * | | |Enable RST can also reset all control and status registers, exclusive of the control bits RMIIEN (EMAC_CTL[22]), LOOPBK (EMAC_CTL[21]) and OPMODE (EMAC_CTL[20]).
<> 144:ef7eb2e8f9f7 12520 * | | |The EMAC re-initial is necessary after the software reset completed.
<> 144:ef7eb2e8f9f7 12521 * | | |0 = Software reset completed.
<> 144:ef7eb2e8f9f7 12522 * | | |1 = Software reset Enabled.
<> 144:ef7eb2e8f9f7 12523 */
<> 144:ef7eb2e8f9f7 12524 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 12525
<> 144:ef7eb2e8f9f7 12526 /**
<> 144:ef7eb2e8f9f7 12527 * MIIMDAT
<> 144:ef7eb2e8f9f7 12528 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12529 * Offset: 0x94 MII Management Data Register
<> 144:ef7eb2e8f9f7 12530 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12531 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12532 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12533 * |[0:15] |DATA |MII Management Data
<> 144:ef7eb2e8f9f7 12534 * | | |The DATA is the 16 bits data that will be written into the registers of external PHY for MII Management write command or the data from the registers of external PHY for MII Management read command.
<> 144:ef7eb2e8f9f7 12535 */
<> 144:ef7eb2e8f9f7 12536 __IO uint32_t MIIMDAT;
<> 144:ef7eb2e8f9f7 12537
<> 144:ef7eb2e8f9f7 12538 /**
<> 144:ef7eb2e8f9f7 12539 * MIIMCTL
<> 144:ef7eb2e8f9f7 12540 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12541 * Offset: 0x98 MII Management Control and Address Register
<> 144:ef7eb2e8f9f7 12542 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12543 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12544 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12545 * |[0:4] |PHYREG |PHY Register Address
<> 144:ef7eb2e8f9f7 12546 * | | |The PHYREG keeps the address to indicate which register of external PHY is the target of the MII management command.
<> 144:ef7eb2e8f9f7 12547 * |[8:12] |PHYADDR |PHY Address
<> 144:ef7eb2e8f9f7 12548 * | | |The PHYADDR keeps the address to differentiate which external PHY is the target of the MII management command.
<> 144:ef7eb2e8f9f7 12549 * |[16] |WRITE |Write Command
<> 144:ef7eb2e8f9f7 12550 * | | |The Write defines the MII management command is a read or write.
<> 144:ef7eb2e8f9f7 12551 * | | |0 = MII management command is a read command.
<> 144:ef7eb2e8f9f7 12552 * | | |1 = MII management command is a write command.
<> 144:ef7eb2e8f9f7 12553 * |[17] |BUSY |Busy Bit
<> 144:ef7eb2e8f9f7 12554 * | | |The BUSY controls the enable of the MII management frame generation.
<> 144:ef7eb2e8f9f7 12555 * | | |If S/W wants to access registers of external PHY, it set BUSY to high and EMAC generates the MII management frame to external PHY through MII Management I/F.
<> 144:ef7eb2e8f9f7 12556 * | | |The BUSY is a self-clear bit.
<> 144:ef7eb2e8f9f7 12557 * | | |This means the BUSY will be cleared automatically after the MII management command finished.
<> 144:ef7eb2e8f9f7 12558 * | | |0 = MII management command generation finished.
<> 144:ef7eb2e8f9f7 12559 * | | |1 = MII management command generation Enabled.
<> 144:ef7eb2e8f9f7 12560 * |[18] |PREAMSP |Preamble Suppress
<> 144:ef7eb2e8f9f7 12561 * | | |The PREAMSP controls the preamble field generation of MII management frame.
<> 144:ef7eb2e8f9f7 12562 * | | |If the PREAMSP is set to high, the preamble field generation of MII management frame is skipped.
<> 144:ef7eb2e8f9f7 12563 * | | |0 = Preamble field generation of MII management frame not skipped.
<> 144:ef7eb2e8f9f7 12564 * | | |1 = Preamble field generation of MII management frame skipped.
<> 144:ef7eb2e8f9f7 12565 * |[19] |MDCON |MDC Clock ON Always
<> 144:ef7eb2e8f9f7 12566 * | | |The MDC controls the MDC clock generation.
<> 144:ef7eb2e8f9f7 12567 * | | |If the MDCON is set to high, the MDC clock actives always.
<> 144:ef7eb2e8f9f7 12568 * | | |Otherwise, the MDC will only active while S/W issues a MII management command.
<> 144:ef7eb2e8f9f7 12569 * | | |0 = MDC clock only actives while S/W issues a MII management command.
<> 144:ef7eb2e8f9f7 12570 * | | |1 = MDC clock actives always.
<> 144:ef7eb2e8f9f7 12571 */
<> 144:ef7eb2e8f9f7 12572 __IO uint32_t MIIMCTL;
<> 144:ef7eb2e8f9f7 12573
<> 144:ef7eb2e8f9f7 12574 /**
<> 144:ef7eb2e8f9f7 12575 * FIFOCTL
<> 144:ef7eb2e8f9f7 12576 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12577 * Offset: 0x9C FIFO Threshold Control Register
<> 144:ef7eb2e8f9f7 12578 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12579 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12580 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12581 * |[0:1] |RXFIFOTH |RXFIFO Low Threshold
<> 144:ef7eb2e8f9f7 12582 * | | |The RXFIFOTH controls when RXDMA requests internal arbiter for data transfer between RXFIFO and system memory.
<> 144:ef7eb2e8f9f7 12583 * | | |The RXFIFOTH defines not only the high threshold of RXFIFO, but also the low threshold.
<> 144:ef7eb2e8f9f7 12584 * | | |The low threshold is the half of high threshold always.
<> 144:ef7eb2e8f9f7 12585 * | | |During the packet reception, if the RXFIFO reaches the high threshold, the RXDMA starts to transfer frame data from RXFIFO to system memory.
<> 144:ef7eb2e8f9f7 12586 * | | |If the frame data in RXFIFO is less than low threshold, RXDMA stops to transfer the frame data to system memory.
<> 144:ef7eb2e8f9f7 12587 * | | |00 = Depend on the burst length setting.
<> 144:ef7eb2e8f9f7 12588 * | | |If the burst length is 8 words, high threshold is 8 words, too.
<> 144:ef7eb2e8f9f7 12589 * | | |01 = RXFIFO high threshold is 64B and low threshold is 32B.
<> 144:ef7eb2e8f9f7 12590 * | | |10 = RXFIFO high threshold is 128B and low threshold is 64B.
<> 144:ef7eb2e8f9f7 12591 * | | |11 = RXFIFO high threshold is 192B and low threshold is 96B.
<> 144:ef7eb2e8f9f7 12592 * |[8:9] |TXFIFOTH |TXFIFO Low Threshold
<> 144:ef7eb2e8f9f7 12593 * | | |The TXFIFOTH controls when TXDMA requests internal arbiter for data transfer between system memory and TXFIFO.
<> 144:ef7eb2e8f9f7 12594 * | | |The TXFIFOTH defines not only the low threshold of TXFIFO, but also the high threshold.
<> 144:ef7eb2e8f9f7 12595 * | | |The high threshold is the twice of low threshold always.During the packet transmission, if the TXFIFO reaches the high threshold, the TXDMA stops generate request to transfer frame data from system memory to TXFIFO.
<> 144:ef7eb2e8f9f7 12596 * | | |If the frame data in TXFIFO is less than low threshold, TXDMA starts to transfer frame data from system memory to TXFIFO.
<> 144:ef7eb2e8f9f7 12597 * | | |The TXFIFOTH also defines when the TXMAC starts to transmit frame out to network.
<> 144:ef7eb2e8f9f7 12598 * | | |The TXMAC starts to transmit the frame out while the TXFIFO first time reaches the high threshold during the transmission of the frame.
<> 144:ef7eb2e8f9f7 12599 * | | |If the frame data length is less than TXFIFO high threshold, the TXMAC starts to transmit the frame out after the frame data are all inside the TXFIFO.
<> 144:ef7eb2e8f9f7 12600 * | | |00 = Undefined.
<> 144:ef7eb2e8f9f7 12601 * | | |01 = TXFIFO low threshold is 64B and high threshold is 128B.
<> 144:ef7eb2e8f9f7 12602 * | | |10 = TXFIFO low threshold is 80B and high threshold is 160B.
<> 144:ef7eb2e8f9f7 12603 * | | |11 = TXFIFO low threshold is 96B and high threshold is 192B.
<> 144:ef7eb2e8f9f7 12604 * |[20:21] |BURSTLEN |DMA Burst Length
<> 144:ef7eb2e8f9f7 12605 * | | |This defines the burst length of AHB bus cycle while EMAC accesses system memory.
<> 144:ef7eb2e8f9f7 12606 * | | |00 = 16 words.
<> 144:ef7eb2e8f9f7 12607 * | | |01 = 16 words.
<> 144:ef7eb2e8f9f7 12608 * | | |10 = 8 words.
<> 144:ef7eb2e8f9f7 12609 * | | |11 = 4 words.
<> 144:ef7eb2e8f9f7 12610 */
<> 144:ef7eb2e8f9f7 12611 __IO uint32_t FIFOCTL;
<> 144:ef7eb2e8f9f7 12612
<> 144:ef7eb2e8f9f7 12613 /**
<> 144:ef7eb2e8f9f7 12614 * TXST
<> 144:ef7eb2e8f9f7 12615 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12616 * Offset: 0xA0 Transmit Start Demand Register
<> 144:ef7eb2e8f9f7 12617 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12618 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12619 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12620 * |[0:31] |TXST |Transmit Start Demand
<> 144:ef7eb2e8f9f7 12621 * | | |If the TX descriptor is not available for use of TXDMA after the TXON (EMAC_CTL[8]) is enabled, the FSM (Finite State Machine) of TXDMA enters the Halt state and the frame transmission is halted.
<> 144:ef7eb2e8f9f7 12622 * | | |After the S/W has prepared the new TX descriptor for frame transmission, it must issue a write command to EMAC_TXST register to make TXDMA to leave Halt state and continue the frame transmission.
<> 144:ef7eb2e8f9f7 12623 * | | |The EMAC_TXST is a write only register and read from this register is undefined.
<> 144:ef7eb2e8f9f7 12624 * | | |The write to EMAC_TXST register takes effect only when TXDMA stayed at Halt state.
<> 144:ef7eb2e8f9f7 12625 */
<> 144:ef7eb2e8f9f7 12626 __O uint32_t TXST;
<> 144:ef7eb2e8f9f7 12627
<> 144:ef7eb2e8f9f7 12628 /**
<> 144:ef7eb2e8f9f7 12629 * RXST
<> 144:ef7eb2e8f9f7 12630 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12631 * Offset: 0xA4 Receive Start Demand Register
<> 144:ef7eb2e8f9f7 12632 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12633 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12634 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12635 * |[0:31] |RXST |Receive Start Demand
<> 144:ef7eb2e8f9f7 12636 * | | |If the RX descriptor is not available for use of RXDMA after the RXON (EMAC_CTL[0]) is enabled, the FSM (Finite State Machine) of RXDMA enters the Halt state and the frame reception is halted.
<> 144:ef7eb2e8f9f7 12637 * | | |After the S/W has prepared the new RX descriptor for frame reception, it must issue a write command to EMAC_RXST register to make RXDMA to leave Halt state and continue the frame reception.
<> 144:ef7eb2e8f9f7 12638 * | | |The EMAC_RXST is a write only register and read from this register is undefined.
<> 144:ef7eb2e8f9f7 12639 * | | |The write to EMAC_RXST register take effect only when RXDMA stayed at Halt state.
<> 144:ef7eb2e8f9f7 12640 */
<> 144:ef7eb2e8f9f7 12641 __O uint32_t RXST;
<> 144:ef7eb2e8f9f7 12642
<> 144:ef7eb2e8f9f7 12643 /**
<> 144:ef7eb2e8f9f7 12644 * MRFL
<> 144:ef7eb2e8f9f7 12645 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12646 * Offset: 0xA8 Maximum Receive Frame Control Register
<> 144:ef7eb2e8f9f7 12647 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12648 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12649 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12650 * |[0:15] |MRFL |Maximum Receive Frame Length
<> 144:ef7eb2e8f9f7 12651 * | | |The MRFL defines the maximum frame length for received frame.
<> 144:ef7eb2e8f9f7 12652 * | | |If the frame length of received frame is greater than MRFL, and bit MFLEIEN (EMAC_INTEN[8]) is also enabled, the bit MFLEIF (EMAC_INTSTS[8]) is set and the RX interrupt is triggered.
<> 144:ef7eb2e8f9f7 12653 * | | |It is recommended that only use MRFL to qualify the length of received frame while S/W wants to receive a frame which length is greater than 1518 bytes.
<> 144:ef7eb2e8f9f7 12654 */
<> 144:ef7eb2e8f9f7 12655 __IO uint32_t MRFL;
<> 144:ef7eb2e8f9f7 12656
<> 144:ef7eb2e8f9f7 12657 /**
<> 144:ef7eb2e8f9f7 12658 * INTEN
<> 144:ef7eb2e8f9f7 12659 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12660 * Offset: 0xAC MAC Interrupt Enable Register
<> 144:ef7eb2e8f9f7 12661 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12662 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12663 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12664 * |[0] |RXIEN |Receive Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12665 * | | |The RXIEN controls the RX interrupt generation.
<> 144:ef7eb2e8f9f7 12666 * | | |If RXIEN is enabled and RXIF (EMAC_INTSTS[0]) is high, EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12667 * | | |If RXIEN is disabled, no RX interrupt is generated to CPU even any status bit EMAC_INTSTS[15:1] is set and the corresponding bit of EMAC_INTEN is enabled.
<> 144:ef7eb2e8f9f7 12668 * | | |In other words, if S/W wants to receive RX interrupt from EMAC, this bit must be enabled.
<> 144:ef7eb2e8f9f7 12669 * | | |And, if S/W doesn't want to receive any RX interrupt from EMAC, disables this bit.
<> 144:ef7eb2e8f9f7 12670 * | | |0 = RXIF (EMAC_INTSTS[0]) is masked and RX interrupt generation Disabled.
<> 144:ef7eb2e8f9f7 12671 * | | |1 = RXIF (EMAC_INTSTS[0]) is not masked and RX interrupt generation Enabled.
<> 144:ef7eb2e8f9f7 12672 * |[1] |CRCEIEN |CRC Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12673 * | | |The CRCEIEN controls the CRCEIF (EMAC_INTSTS[1]) interrupt generation.
<> 144:ef7eb2e8f9f7 12674 * | | |If CRCEIF (EMAC_INTSTS[1]) is set, and both CRCEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12675 * | | |If CRCEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CRCEIF (EMAC_INTSTS[1]) is set.
<> 144:ef7eb2e8f9f7 12676 * | | |0 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12677 * | | |1 = CRCEIF (EMAC_INTSTS[1]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12678 * |[2] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12679 * | | |The RXOVIEN controls the RXOVIF (EMAC_INTSTS[2]) interrupt generation.
<> 144:ef7eb2e8f9f7 12680 * | | |If RXOVIF (EMAC_INTSTS[2]) is set, and both RXOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12681 * | | |If RXOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXOVIF (EMAC_INTSTS[2]) is set.
<> 144:ef7eb2e8f9f7 12682 * | | |0 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12683 * | | |1 = RXOVIF (EMAC_INTSTS[2]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12684 * |[3] |LPIEN |Long Packet Interrupt Enable
<> 144:ef7eb2e8f9f7 12685 * | | |The LPIEN controls the LPIF (EMAC_INTSTS[3]) interrupt generation.
<> 144:ef7eb2e8f9f7 12686 * | | |If LPIF (EMAC_INTSTS[3]) is set, and both LPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12687 * | | |If LPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the LPIF (EMAC_INTSTS[3]) is set.
<> 144:ef7eb2e8f9f7 12688 * | | |0 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12689 * | | |1 = LPIF (EMAC_INTSTS[3]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12690 * |[4] |RXGDIEN |Receive Good Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12691 * | | |The RXGDIEN controls the RXGDIF (EMAC_INTSTS[4]) interrupt generation.
<> 144:ef7eb2e8f9f7 12692 * | | |If RXGDIF (EMAC_INTSTS[4]) is set, and both RXGDIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12693 * | | |If RXGDIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXGDIF (EMAC_INTSTS[4]) is set.
<> 144:ef7eb2e8f9f7 12694 * | | |0 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12695 * | | |1 = RXGDIF (EMAC_INTSTS[4]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12696 * |[5] |ALIEIEN |Alignment Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12697 * | | |The ALIEIEN controls the ALIEIF (EMAC_INTSTS[5]) interrupt generation.
<> 144:ef7eb2e8f9f7 12698 * | | |If ALIEIF (EMAC_INTSTS[5]) is set, and both ALIEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12699 * | | |If ALIEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the ALIEIF (EMAC_INTSTS[5]) is set.
<> 144:ef7eb2e8f9f7 12700 * | | |0 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12701 * | | |1 = ALIEIF (EMAC_INTSTS[5]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12702 * |[6] |RPIEN |Runt Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12703 * | | |The RPIEN controls the RPIF (EMAC_INTSTS[6]) interrupt generation.
<> 144:ef7eb2e8f9f7 12704 * | | |If RPIF (EMAC_INTSTS[6]) is set, and both RPIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12705 * | | |If RPIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RPIF (EMAC_INTSTS[6]) is set.
<> 144:ef7eb2e8f9f7 12706 * | | |0 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12707 * | | |1 = RPIF (EMAC_INTSTS[6]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12708 * |[7] |MPCOVIEN |Miss Packet Counter Overrun Interrupt Enable
<> 144:ef7eb2e8f9f7 12709 * | | |The MPCOVIEN controls the MPCOVIF (EMAC_INTSTS[7]) interrupt generation.
<> 144:ef7eb2e8f9f7 12710 * | | |If MPCOVIF (EMAC_INTSTS[7]) is set, and both MPCOVIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12711 * | | |If MPCOVIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MPCOVIF (EMAC_INTSTS[7]) is set.
<> 144:ef7eb2e8f9f7 12712 * | | |0 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12713 * | | |1 = MPCOVIF (EMAC_INTSTS[7]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12714 * |[8] |MFLEIEN |Maximum Frame Length Exceed Interrupt Enable
<> 144:ef7eb2e8f9f7 12715 * | | |The MFLEIEN controls the MFLEIF (EMAC_INTSTS[8]) interrupt generation.
<> 144:ef7eb2e8f9f7 12716 * | | |If MFLEIF (EMAC_INTSTS[8]) is set, and both MFLEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12717 * | | |If MFLEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the MFLEIF (EMAC_INTSTS[8]) is set.
<> 144:ef7eb2e8f9f7 12718 * | | |0 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12719 * | | |1 = MFLEIF (EMAC_INTSTS[8]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12720 * |[9] |DENIEN |DMA Early Notification Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12721 * | | |The DENIEN controls the DENIF (EMAC_INTSTS[9]) interrupt generation.
<> 144:ef7eb2e8f9f7 12722 * | | |If DENIF (EMAC_INTSTS[9]) is set, and both DENIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12723 * | | |If DENIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the DENIF (EMAC_INTSTS[9]) is set.
<> 144:ef7eb2e8f9f7 12724 * | | |0 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12725 * | | |1 = TDENIF (EMAC_INTSTS[9]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12726 * |[10] |RDUIEN |Receive Descriptor Unavailable Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12727 * | | |The RDUIEN controls the RDUIF (EMAC_INTSTS[10]) interrupt generation.
<> 144:ef7eb2e8f9f7 12728 * | | |If RDUIF (EMAC_INTSTS[10]) is set, and both RDUIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12729 * | | |If RDUIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RDUIF (EMAC_MIOSTA[10]) register is set.
<> 144:ef7eb2e8f9f7 12730 * | | |0 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12731 * | | |1 = RDUIF (EMAC_INTSTS[10]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12732 * |[11] |RXBEIEN |Receive Bus Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12733 * | | |The RXBEIEN controls the RXBEIF (EMAC_INTSTS[11]) interrupt generation.
<> 144:ef7eb2e8f9f7 12734 * | | |If RXBEIF (EMAC_INTSTS[11]) is set, and both RXBEIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12735 * | | |If RXBEIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the RXBEIF (EMAC_INTSTS[11]) is set.
<> 144:ef7eb2e8f9f7 12736 * | | |0 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12737 * | | |1 = RXBEIF (EMAC_INTSTS[11]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12738 * |[14] |CFRIEN |Control Frame Receive Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12739 * | | |The CFRIEN controls the CFRIF (EMAC_INTSTS[14]) interrupt generation.
<> 144:ef7eb2e8f9f7 12740 * | | |If CFRIF (EMAC_INTSTS[14]) is set, and both CFRIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12741 * | | |If CFRIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the CFRIF (EMAC_INTSTS[14]) register is set.
<> 144:ef7eb2e8f9f7 12742 * | | |0 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12743 * | | |1 = CFRIF (EMAC_INTSTS[14]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12744 * |[15] |WOLIEN |Wake On LAN Interrupt Enable
<> 144:ef7eb2e8f9f7 12745 * | | |The WOLIEN controls the WOLIF (EMAC_INTSTS[15]) interrupt generation.
<> 144:ef7eb2e8f9f7 12746 * | | |If WOLIF (EMAC_INTSTS[15]) is set, and both WOLIEN and RXIEN (EMAC_INTEN[0]) are enabled, the EMAC generates the RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12747 * | | |If WOLIEN or RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated to CPU even the WOLIF (EMAC_INTSTS[15]) is set.
<> 144:ef7eb2e8f9f7 12748 * | | |0 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12749 * | | |1 = WOLIF (EMAC_INTSTS[15]) trigger RX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12750 * |[16] |TXIEN |Transmit Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12751 * | | |The TXIEN controls the TX interrupt generation.
<> 144:ef7eb2e8f9f7 12752 * | | |If TXIEN is enabled and TXIF (EMAC_INTSTS[16]) is high, EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12753 * | | |If TXIEN is disabled, no TX interrupt is generated to CPU even any status bit of EMAC_INTSTS[24:17] set and the corresponding bit of EMAC_INTEN is enabled.
<> 144:ef7eb2e8f9f7 12754 * | | |In other words, if S/W wants to receive TX interrupt from EMAC, this bit must be enabled.
<> 144:ef7eb2e8f9f7 12755 * | | |And, if S/W doesn't want to receive any TX interrupt from EMAC, disables this bit.
<> 144:ef7eb2e8f9f7 12756 * | | |0 = TXIF (EMAC_INTSTS[16]) is masked and TX interrupt generation Disabled.
<> 144:ef7eb2e8f9f7 12757 * | | |1 = TXIF (EMAC_INTSTS[16]) is not masked and TX interrupt generation Enabled.
<> 144:ef7eb2e8f9f7 12758 * |[17] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12759 * | | |The TXUDIEN controls the TXUDIF (EMAC_INTSTS[17]) interrupt generation.
<> 144:ef7eb2e8f9f7 12760 * | | |If TXUDIF (EMAC_INTSTS[17]) is set, and both TXUDIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12761 * | | |If TXUDIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXUDIF (EMAC_INTSTS[17]) is set.
<> 144:ef7eb2e8f9f7 12762 * | | |0 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12763 * | | |1 = TXUDIF (EMAC_INTSTS[17]) TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12764 * |[18] |TXCPIEN |Transmit Completion Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12765 * | | |The TXCPIEN controls the TXCPIF (EMAC_INTSTS[18]) interrupt generation.
<> 144:ef7eb2e8f9f7 12766 * | | |If TXCPIF (EMAC_INTSTS[18]) is set, and both TXCPIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12767 * | | |If TXCPIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXCPIF (EMAC_INTSTS[18]) is set.
<> 144:ef7eb2e8f9f7 12768 * | | |0 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12769 * | | |1 = TXCPIF (EMAC_INTSTS[18]) trigger TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12770 * |[19] |EXDEFIEN |Defer Exceed Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12771 * | | |The EXDEFIEN controls the EXDEFIF (EMAC_INTSTS[19]) interrupt generation.
<> 144:ef7eb2e8f9f7 12772 * | | |If EXDEFIF (EMAC_INTSTS[19]) is set, and both EXDEFIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12773 * | | |If EXDEFIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the EXDEFIF (EMAC_INTSTS[19]) is set.
<> 144:ef7eb2e8f9f7 12774 * | | |0 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12775 * | | |1 = EXDEFIF (EMAC_INTSTS[19]) trigger TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12776 * |[20] |NCSIEN |No Carrier Sense Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12777 * | | |The NCSIEN controls the NCSIF (EMAC_INTSTS[20]) interrupt generation.
<> 144:ef7eb2e8f9f7 12778 * | | |If NCSIF (EMAC_INTSTS[20]) is set, and both NCSIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12779 * | | |If NCSIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the NCSIF (EMAC_INTSTS[20]) is set.
<> 144:ef7eb2e8f9f7 12780 * | | |0 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12781 * | | |1 = NCSIF (EMAC_INTSTS[20]) trigger TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12782 * |[21] |TXABTIEN |Transmit Abort Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12783 * | | |The TXABTIEN controls the TXABTIF (EMAC_INTSTS[21]) interrupt generation.
<> 144:ef7eb2e8f9f7 12784 * | | |If TXABTIF (EMAC_INTSTS[21]) is set, and both TXABTIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12785 * | | |If TXABTIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXABTIF (EMAC_INTSTS[21]) is set.
<> 144:ef7eb2e8f9f7 12786 * | | |0 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12787 * | | |1 = TXABTIF (EMAC_INTSTS[21]) trigger TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12788 * |[22] |LCIEN |Late Collision Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12789 * | | |The LCIEN controls the LCIF (EMAC_INTSTS[22]) interrupt generation.
<> 144:ef7eb2e8f9f7 12790 * | | |If LCIF (EMAC_INTSTS[22]) is set, and both LCIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12791 * | | |If LCIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the LCIF (EMAC_INTSTS[22]) is set.
<> 144:ef7eb2e8f9f7 12792 * | | |0 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12793 * | | |1 = LCIF (EMAC_INTSTS[22]) trigger TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12794 * |[23] |TDUIEN |Transmit Descriptor Unavailable Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12795 * | | |The TDUIEN controls the TDUIF (EMAC_INTSTS[23]) interrupt generation.
<> 144:ef7eb2e8f9f7 12796 * | | |If TDUIF (EMAC_INTSTS[23]) is set, and both TDUIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12797 * | | |If TDUIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TDUIF (EMAC_INTSTS[23]) is set.
<> 144:ef7eb2e8f9f7 12798 * | | |0 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12799 * | | |1 = TDUIF (EMAC_INTSTS[23]) trigger TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12800 * |[24] |TXBEIEN |Transmit Bus Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12801 * | | |The TXBEIEN controls the TXBEIF (EMAC_INTSTS[24]) interrupt generation.
<> 144:ef7eb2e8f9f7 12802 * | | |If TXBEIF (EMAC_INTSTS[24]) is set, and both TXBEIEN and TXIEN (EMAC_INTEN[16]) are enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12803 * | | |If TXBEIEN or TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated to CPU even the TXBEIF (EMAC_INTSTS[24]) is set.
<> 144:ef7eb2e8f9f7 12804 * | | |0 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12805 * | | |1 = TXBEIF (EMAC_INTSTS[24]) trigger TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12806 * |[28] |TSALMIEN |Time Stamp Alarm Interrupt Enable Control
<> 144:ef7eb2e8f9f7 12807 * | | |The TSALMIEN controls the TSALMIF (EMAC_INTSTS[28]) interrupt generation.
<> 144:ef7eb2e8f9f7 12808 * | | |If TSALMIF (EMAC_INTSTS[28]) is set, and both TSALMIEN and TXIEN (EMAC_INTEN[16]) enabled, the EMAC generates the TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12809 * | | |If TSALMIEN or TXIEN (EMAC_INTEN[16]) disabled, no TX interrupt generated to CPU even the TXTSALMIF (EMAC_INTEN[28]) is set.
<> 144:ef7eb2e8f9f7 12810 * | | |0 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Disabled.
<> 144:ef7eb2e8f9f7 12811 * | | |1 = TXTSALMIF (EMAC_INTSTS[28]) trigger TX interrupt Enabled.
<> 144:ef7eb2e8f9f7 12812 */
<> 144:ef7eb2e8f9f7 12813 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 12814
<> 144:ef7eb2e8f9f7 12815 /**
<> 144:ef7eb2e8f9f7 12816 * INTSTS
<> 144:ef7eb2e8f9f7 12817 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12818 * Offset: 0xB0 MAC Interrupt Status Register
<> 144:ef7eb2e8f9f7 12819 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12820 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12821 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 12822 * |[0] |RXIF |Receive Interrupt
<> 144:ef7eb2e8f9f7 12823 * | | |The RXIF indicates the RX interrupt status.
<> 144:ef7eb2e8f9f7 12824 * | | |If RXIF high and its corresponding enable bit, RXIEN (EMAC_INTEN[0]), is also high indicates the EMAC generates RX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12825 * | | |If RXIF is high but RXIEN (EMAC_INTEN[0]) is disabled, no RX interrupt is generated.
<> 144:ef7eb2e8f9f7 12826 * | | |The RXIF is logic OR result of bit logic AND result of EMAC_INTSTS[15:1] and EMAC_INTEN[15:1].
<> 144:ef7eb2e8f9f7 12827 * | | |In other words, if any bit of EMAC_INTSTS[15:1] is high and its corresponding enable bit in EMAC_INTEN[15:1] is also enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12828 * | | |Because the RXIF is a logic OR result, clears EMAC_INTSTS[15:1] makes RXIF be cleared, too.
<> 144:ef7eb2e8f9f7 12829 * | | |0 = No status bit in EMAC_INTSTS[15:1] is set or no enable bit in EMAC_INTEN[15:1] is enabled.
<> 144:ef7eb2e8f9f7 12830 * | | |1 = At least one status in EMAC_INTSTS[15:1] is set and its corresponding enable bit in EMAC_INTEN[15:1] is enabled, too.
<> 144:ef7eb2e8f9f7 12831 * |[1] |CRCEIF |CRC Error Interrupt
<> 144:ef7eb2e8f9f7 12832 * | | |The CRCEIF high indicates the incoming packet incurred the CRC error and the packet is dropped.
<> 144:ef7eb2e8f9f7 12833 * | | |If the AEP (EMAC_CTL[4]) is set, the CRC error packet will be regarded as a good packet and CRCEIF will not be set.
<> 144:ef7eb2e8f9f7 12834 * | | |If the CRCEIF is high and CRCEIEN (EMAC_INTEN[1]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12835 * | | |Write 1 to this bit clears the CRCEIF status.
<> 144:ef7eb2e8f9f7 12836 * | | |0 = The frame does not incur CRC error.
<> 144:ef7eb2e8f9f7 12837 * | | |1 = The frame incurred CRC error.
<> 144:ef7eb2e8f9f7 12838 * |[2] |RXOVIF |Receive FIFO Overflow Interrupt
<> 144:ef7eb2e8f9f7 12839 * | | |The RXOVIF high indicates the RXFIFO overflow occurred during packet reception.
<> 144:ef7eb2e8f9f7 12840 * | | |While the RXFIFO overflow occurred, the EMAC drops the current receiving packer.
<> 144:ef7eb2e8f9f7 12841 * | | |If the RXFIFO overflow occurred often, it is recommended that modify RXFIFO threshold control, the RXFIFOTH of FFTCR register, to higher level.
<> 144:ef7eb2e8f9f7 12842 * | | |If the RXOVIF is high and RXOVIEN (EMAC_INTEN[2]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12843 * | | |Write 1 to this bit clears the RXOVIF status.
<> 144:ef7eb2e8f9f7 12844 * | | |0 = No RXFIFO overflow occurred during packet reception.
<> 144:ef7eb2e8f9f7 12845 * | | |1 = RXFIFO overflow occurred during packet reception.
<> 144:ef7eb2e8f9f7 12846 * |[3] |LPIF |Long Packet Interrupt Flag
<> 144:ef7eb2e8f9f7 12847 * | | |The LPIF high indicates the length of the incoming packet is greater than 1518 bytes and the incoming packet is dropped.
<> 144:ef7eb2e8f9f7 12848 * | | |If the ALP (EMAC_CTL[1]) is set, the long packet will be regarded as a good packet and LPIF will not be set.
<> 144:ef7eb2e8f9f7 12849 * | | |If the LPIF is high and LPIEN (EMAC_INTEN[3]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12850 * | | |Write 1 to this bit clears the LPIF status.
<> 144:ef7eb2e8f9f7 12851 * | | |0 = The incoming frame is not a long frame or S/W wants to receive a long frame.
<> 144:ef7eb2e8f9f7 12852 * | | |1 = The incoming frame is a long frame and dropped.
<> 144:ef7eb2e8f9f7 12853 * |[4] |RXGDIF |Receive Good Interrupt
<> 144:ef7eb2e8f9f7 12854 * | | |The RXGDIF high indicates the frame reception has completed.
<> 144:ef7eb2e8f9f7 12855 * | | |If the RXGDIF is high and RXGDIEN (EAMC_MIEN[4]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12856 * | | |Write 1 to this bit clears the RXGDIF status.
<> 144:ef7eb2e8f9f7 12857 * | | |0 = The frame reception has not complete yet.
<> 144:ef7eb2e8f9f7 12858 * | | |1 = The frame reception has completed.
<> 144:ef7eb2e8f9f7 12859 * |[5] |ALIEIF |Alignment Error Interrupt
<> 144:ef7eb2e8f9f7 12860 * | | |The ALIEIF high indicates the length of the incoming frame is not a multiple of byte.
<> 144:ef7eb2e8f9f7 12861 * | | |If the ALIEIF is high and ALIEIEN (EMAC_INTEN[5]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12862 * | | |Write 1 to this bit clears the ALIEIF status.
<> 144:ef7eb2e8f9f7 12863 * | | |0 = The frame length is a multiple of byte.
<> 144:ef7eb2e8f9f7 12864 * | | |1 = The frame length is not a multiple of byte.
<> 144:ef7eb2e8f9f7 12865 * |[6] |RPIF |Runt Packet Interrupt
<> 144:ef7eb2e8f9f7 12866 * | | |The RPIF high indicates the length of the incoming packet is less than 64 bytes and the packet is dropped.
<> 144:ef7eb2e8f9f7 12867 * | | |If the ARP (EMAC_CTL[2]) is set, the short packet is regarded as a good packet and RPIF will not be set.
<> 144:ef7eb2e8f9f7 12868 * | | |If the RPIF is high and RPIEN (EMAC_INTEN[6]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12869 * | | |Write 1 to this bit clears the RPIF status.
<> 144:ef7eb2e8f9f7 12870 * | | |0 = The incoming frame is not a short frame or S/W wants to receive a short frame.
<> 144:ef7eb2e8f9f7 12871 * | | |1 = The incoming frame is a short frame and dropped.
<> 144:ef7eb2e8f9f7 12872 * |[7] |MPCOVIF |Missed Packet Counter Overrun Interrupt Flag
<> 144:ef7eb2e8f9f7 12873 * | | |The MPCOVIF high indicates the MPCNT, Missed Packet Count, has overflow.
<> 144:ef7eb2e8f9f7 12874 * | | |If the MPCOVIF is high and MPCOVIEN (EMAC_INTEN[7]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12875 * | | |Write 1 to this bit clears the MPCOVIF status.
<> 144:ef7eb2e8f9f7 12876 * | | |0 = The MPCNT has not rolled over yet.
<> 144:ef7eb2e8f9f7 12877 * | | |1 = The MPCNT has rolled over yet.
<> 144:ef7eb2e8f9f7 12878 * |[8] |MFLEIF |Maximum Frame Length Exceed Interrupt Flag
<> 144:ef7eb2e8f9f7 12879 * | | |The MFLEIF high indicates the length of the incoming packet has exceeded the length limitation configured in DMARFC register and the incoming packet is dropped.
<> 144:ef7eb2e8f9f7 12880 * | | |If the MFLEIF is high and MFLEIEN (EMAC_INTEN[8]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12881 * | | |Write 1 to this bit clears the MFLEIF status.
<> 144:ef7eb2e8f9f7 12882 * | | |0 = The length of the incoming packet does not exceed the length limitation configured in DMARFC.
<> 144:ef7eb2e8f9f7 12883 * | | |1 = The length of the incoming packet has exceeded the length limitation configured in DMARFC.
<> 144:ef7eb2e8f9f7 12884 * |[9] |DENIF |DMA Early Notification Interrupt
<> 144:ef7eb2e8f9f7 12885 * | | |The DENIF high indicates the EMAC has received the LENGTH field of the incoming packet.
<> 144:ef7eb2e8f9f7 12886 * | | |If the DENIF is high and DENIENI (EMAC_INTEN[9]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12887 * | | |Write 1 to this bit clears the DENIF status.
<> 144:ef7eb2e8f9f7 12888 * | | |0 = The LENGTH field of incoming packet has not received yet.
<> 144:ef7eb2e8f9f7 12889 * | | |1 = The LENGTH field of incoming packet has received.
<> 144:ef7eb2e8f9f7 12890 * |[10] |RDUIF |Receive Descriptor Unavailable Interrupt
<> 144:ef7eb2e8f9f7 12891 * | | |The RDUIF high indicates that there is no available RX descriptor for packet reception and RXDMA will stay at Halt state.
<> 144:ef7eb2e8f9f7 12892 * | | |Once, the RXDMA enters the Halt state, S/W must issues a write command to RSDR register to make RXDMA leave Halt state while new RX descriptor is available.
<> 144:ef7eb2e8f9f7 12893 * | | |If the RDUIF is high and RDUIEN (EMAC_INTEN[10]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12894 * | | |Write 1 to this bit clears the RDUIF status.
<> 144:ef7eb2e8f9f7 12895 * | | |0 = RX descriptor is available.
<> 144:ef7eb2e8f9f7 12896 * | | |1 = RX descriptor is unavailable.
<> 144:ef7eb2e8f9f7 12897 * |[11] |RXBEIF |Receive Bus Error Interrupt
<> 144:ef7eb2e8f9f7 12898 * | | |The RXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through RXDMA during packet reception process.
<> 144:ef7eb2e8f9f7 12899 * | | |Reset EMAC is recommended while RXBEIF status is high.
<> 144:ef7eb2e8f9f7 12900 * | | |If the RXBEIF is high and RXBEIEN (EMAC_INTEN[11]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12901 * | | |Write 1 to this bit clears the RXBEIF status.
<> 144:ef7eb2e8f9f7 12902 * | | |0 = No ERROR response is received.
<> 144:ef7eb2e8f9f7 12903 * | | |1 = ERROR response is received.
<> 144:ef7eb2e8f9f7 12904 * |[14] |CFRIF |Control Frame Receive Interrupt
<> 144:ef7eb2e8f9f7 12905 * | | |The CFRIF high indicates EMAC receives a flow control frame.
<> 144:ef7eb2e8f9f7 12906 * | | |The CFRIF only available while EMAC is operating on full duplex mode.
<> 144:ef7eb2e8f9f7 12907 * | | |If the CFRIF is high and CFRIEN (EMAC_INTEN[14]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12908 * | | |Write 1 to this bit clears the CFRIF status.
<> 144:ef7eb2e8f9f7 12909 * | | |0 = The EMAC does not receive the flow control frame.
<> 144:ef7eb2e8f9f7 12910 * | | |1 = The EMAC receives a flow control frame.
<> 144:ef7eb2e8f9f7 12911 * |[15] |WOLIF |Wake On LAN Interrupt Flag
<> 144:ef7eb2e8f9f7 12912 * | | |The WOLIF high indicates EMAC receives a Magic Packet.
<> 144:ef7eb2e8f9f7 12913 * | | |The CFRIF only available while system is in power down mode and WOLEN is set high.
<> 144:ef7eb2e8f9f7 12914 * | | |If the WOLIF is high and WOLIEN (EMAC_INTEN[15]) is enabled, the RXIF will be high.
<> 144:ef7eb2e8f9f7 12915 * | | |Write 1 to this bit clears the WOLIF status.
<> 144:ef7eb2e8f9f7 12916 * | | |0 = The EMAC does not receive the Magic Packet.
<> 144:ef7eb2e8f9f7 12917 * | | |1 = The EMAC receives a Magic Packet.
<> 144:ef7eb2e8f9f7 12918 * |[16] |TXIF |Transmit Interrupt
<> 144:ef7eb2e8f9f7 12919 * | | |The TXIF indicates the TX interrupt status.
<> 144:ef7eb2e8f9f7 12920 * | | |If TXIF high and its corresponding enable bit, TXIEN (EMAC_INTEN[16]), is also high indicates the EMAC generates TX interrupt to CPU.
<> 144:ef7eb2e8f9f7 12921 * | | |If TXIF is high but TXIEN (EMAC_INTEN[16]) is disabled, no TX interrupt is generated.
<> 144:ef7eb2e8f9f7 12922 * | | |The TXIF is logic OR result of bit logic AND result of EMAC_INTSTS[28:17] and EMAC_INTEN[28:17].
<> 144:ef7eb2e8f9f7 12923 * | | |In other words, if any bit of EMAC_INTSTS[28:17] is high and its corresponding enable bit in EMAC_INTEN[28:17] is also enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12924 * | | |Because the TXIF is a logic OR result, clears EMAC_INTSTS[28:17] makes TXIF be cleared, too.
<> 144:ef7eb2e8f9f7 12925 * | | |0 = No status bit in EMAC_INTSTS[28:17] is set or no enable bit in EMAC_INTEN[28:17] is enabled.
<> 144:ef7eb2e8f9f7 12926 * | | |1 = At least one status in EMAC_INTSTS[28:17] is set and its corresponding enable bit in EMAC_INTEN[28:17] is enabled, too.
<> 144:ef7eb2e8f9f7 12927 * |[17] |TXUDIF |Transmit FIFO Underflow Interrupt
<> 144:ef7eb2e8f9f7 12928 * | | |The TXUDIF high indicates the TXFIFO underflow occurred during packet transmission.
<> 144:ef7eb2e8f9f7 12929 * | | |While the TXFIFO underflow occurred, the EMAC will retransmit the packet automatically without S/W intervention.
<> 144:ef7eb2e8f9f7 12930 * | | |If the TXFIFO underflow occurred often, it is recommended that modify TXFIFO threshold control, the TXFIFOTH of FFTCR register, to higher level.
<> 144:ef7eb2e8f9f7 12931 * | | |If the TXUDIF is high and TXUDIEN (EMAC_INTEN[17]) is enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12932 * | | |Write 1 to this bit clears the TXUDIF status.
<> 144:ef7eb2e8f9f7 12933 * | | |0 = No TXFIFO underflow occurred during packet transmission.
<> 144:ef7eb2e8f9f7 12934 * | | |1 = TXFIFO underflow occurred during packet transmission.
<> 144:ef7eb2e8f9f7 12935 * |[18] |TXCPIF |Transmit Completion Interrupt
<> 144:ef7eb2e8f9f7 12936 * | | |The TXCPIF indicates the packet transmission has completed correctly.
<> 144:ef7eb2e8f9f7 12937 * | | |If the TXCPIF is high and TXCPIEN (EMAC_INTEN[18]) is enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12938 * | | |Write 1 to this bit clears the TXCPIF status.
<> 144:ef7eb2e8f9f7 12939 * | | |0 = The packet transmission not completed.
<> 144:ef7eb2e8f9f7 12940 * | | |1 = The packet transmission has completed.
<> 144:ef7eb2e8f9f7 12941 * |[19] |EXDEFIF |Defer Exceed Interrupt
<> 144:ef7eb2e8f9f7 12942 * | | |The EXDEFIF high indicates the frame waiting for transmission has deferred over 0.32768ms on 100Mbps mode, or 3.2768ms on 10Mbps mode.
<> 144:ef7eb2e8f9f7 12943 * | | |The deferral exceed check will only be done while bit NODEF of MCMDR is disabled, and EMAC is operating on half-duplex mode.
<> 144:ef7eb2e8f9f7 12944 * | | |If the EXDEFIF is high and EXDEFIEN (EMAC_INTEN[19]) is enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12945 * | | |Write 1 to this bit clears the EXDEFIF status.
<> 144:ef7eb2e8f9f7 12946 * | | |0 = Frame waiting for transmission has not deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
<> 144:ef7eb2e8f9f7 12947 * | | |1 = Frame waiting for transmission has deferred over 0.32768ms (100Mbps) or 3.2768ms (10Mbps).
<> 144:ef7eb2e8f9f7 12948 * |[20] |NCSIF |No Carrier Sense Interrupt
<> 144:ef7eb2e8f9f7 12949 * | | |The NCSIF high indicates the MII I/F signal CRS does not active at the start of or during the packet transmission.
<> 144:ef7eb2e8f9f7 12950 * | | |The NCSIF is only available while EMAC is operating on half-duplex mode.
<> 144:ef7eb2e8f9f7 12951 * | | |If the NCSIF is high and NCSIEN (EMAC_INTEN[20]) is enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12952 * | | |Write 1 to this bit clears the NCSIF status.
<> 144:ef7eb2e8f9f7 12953 * | | |0 = CRS signal actives correctly.
<> 144:ef7eb2e8f9f7 12954 * | | |1 = CRS signal does not active at the start of or during the packet transmission.
<> 144:ef7eb2e8f9f7 12955 * |[21] |TXABTIF |Transmit Abort Interrupt
<> 144:ef7eb2e8f9f7 12956 * | | |The TXABTIF high indicates the packet incurred 16 consecutive collisions during transmission, and then the transmission process for this packet is aborted.
<> 144:ef7eb2e8f9f7 12957 * | | |The transmission abort is only available while EMAC is operating on half-duplex mode.
<> 144:ef7eb2e8f9f7 12958 * | | |If the TXABTIF is high and TXABTIEN (EMAC_INTEN[21]) is enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12959 * | | |Write 1 to this bit clears the TXABTIF status.
<> 144:ef7eb2e8f9f7 12960 * | | |0 = Packet does not incur 16 consecutive collisions during transmission.
<> 144:ef7eb2e8f9f7 12961 * | | |1 = Packet incurred 16 consecutive collisions during transmission.
<> 144:ef7eb2e8f9f7 12962 * |[22] |LCIF |Late Collision Interrupt
<> 144:ef7eb2e8f9f7 12963 * | | |The LCIF high indicates the collision occurred in the outside of 64 bytes collision window.
<> 144:ef7eb2e8f9f7 12964 * | | |This means after the 64 bytes of a frame has been transmitted out to the network, the collision still occurred.
<> 144:ef7eb2e8f9f7 12965 * | | |The late collision check will only be done while EMAC is operating on half-duplex mode.
<> 144:ef7eb2e8f9f7 12966 * | | |If the LCIF is high and LCIEN (EMAC_INTEN[22]) is enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12967 * | | |Write 1 to this bit clears the LCIF status.
<> 144:ef7eb2e8f9f7 12968 * | | |0 = No collision occurred in the outside of 64 bytes collision window.
<> 144:ef7eb2e8f9f7 12969 * | | |1 = Collision occurred in the outside of 64 bytes collision window.
<> 144:ef7eb2e8f9f7 12970 * |[23] |TDUIF |Transmit Descriptor Unavailable Interrupt
<> 144:ef7eb2e8f9f7 12971 * | | |The TDUIF high indicates that there is no available TX descriptor for packet transmission and TXDMA will stay at Halt state.
<> 144:ef7eb2e8f9f7 12972 * | | |Once, the TXDMA enters the Halt state, S/W must issues a write command to TSDR register to make TXDMA leave Halt state while new TX descriptor is available.
<> 144:ef7eb2e8f9f7 12973 * | | |If the TDUIF is high and TDUIEN (EMAC_INTEN[23]) is enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12974 * | | |Write 1 to this bit clears the TDUIF status.
<> 144:ef7eb2e8f9f7 12975 * | | |0 = TX descriptor is available.
<> 144:ef7eb2e8f9f7 12976 * | | |1 = TX descriptor is unavailable.
<> 144:ef7eb2e8f9f7 12977 * |[24] |TXBEIF |Transmit Bus Error Interrupt
<> 144:ef7eb2e8f9f7 12978 * | | |The TXBEIF high indicates the memory controller replies ERROR response while EMAC access system memory through TXDMA during packet transmission process.
<> 144:ef7eb2e8f9f7 12979 * | | |Reset EMAC is recommended while TXBEIF status is high.
<> 144:ef7eb2e8f9f7 12980 * | | |If the TXBEIF is high and TXBEIEN (EMAC_INTEN[24]) is enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12981 * | | |Write 1 to this bit clears the TXBEIF status.
<> 144:ef7eb2e8f9f7 12982 * | | |0 = No ERROR response is received.
<> 144:ef7eb2e8f9f7 12983 * | | |1 = ERROR response is received.
<> 144:ef7eb2e8f9f7 12984 * |[28] |TSALMIF |Time Stamp Alarm Interrupt
<> 144:ef7eb2e8f9f7 12985 * | | |The TSALMIF high indicates the EMAC_TSSEC register value equals to EMAC_ALMSEC register and EMAC_TSSUBSEC register value equals to register EMAC_TSMLSR.
<> 144:ef7eb2e8f9f7 12986 * | | |If TSALMIF is high and TSALMIEN (EMAC_INTEN[28]) enabled, the TXIF will be high.
<> 144:ef7eb2e8f9f7 12987 * | | |Write 1 to this bit clears the TSALMIF status.
<> 144:ef7eb2e8f9f7 12988 * | | |0 = EMAC_TSSEC did not equal EMAC_ALMSEC or EMAC_TSSUBSEC did not equal EMAC_ALMSUBSEC.
<> 144:ef7eb2e8f9f7 12989 * | | |1 = EMAC_TSSEC equals EMAC_ALMSEC and EMAC_TSSUBSEC equals EMAC_ALMSUBSEC.
<> 144:ef7eb2e8f9f7 12990 */
<> 144:ef7eb2e8f9f7 12991 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 12992
<> 144:ef7eb2e8f9f7 12993 /**
<> 144:ef7eb2e8f9f7 12994 * GENSTS
<> 144:ef7eb2e8f9f7 12995 * ===================================================================================================
<> 144:ef7eb2e8f9f7 12996 * Offset: 0xB4 MAC General Status Register
<> 144:ef7eb2e8f9f7 12997 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 12998 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 12999 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13000 * |[0] |CFRIF |Control Frame Received
<> 144:ef7eb2e8f9f7 13001 * | | |The CFRIF high indicates EMAC receives a flow control frame.
<> 144:ef7eb2e8f9f7 13002 * | | |The CFRIF only available while EMAC is operating on full duplex mode.
<> 144:ef7eb2e8f9f7 13003 * | | |0 = The EMAC does not receive the flow control frame.
<> 144:ef7eb2e8f9f7 13004 * | | |1 = The EMAC receives a flow control frame.
<> 144:ef7eb2e8f9f7 13005 * |[1] |RXHALT |Receive Halted
<> 144:ef7eb2e8f9f7 13006 * | | |The RXHALT high indicates the next normal packet reception process will be halted because the bit RXON of MCMDR is disabled be S/W.
<> 144:ef7eb2e8f9f7 13007 * | | |0 = Next normal packet reception process will go on.
<> 144:ef7eb2e8f9f7 13008 * | | |1 = Next normal packet reception process will be halted.
<> 144:ef7eb2e8f9f7 13009 * |[2] |RXFFULL |RXFIFO Full
<> 144:ef7eb2e8f9f7 13010 * | | |The RXFFULL indicates the RXFIFO is full due to four 64-byte packets are kept in RXFIFO and the following incoming packet will be dropped.
<> 144:ef7eb2e8f9f7 13011 * | | |0 = The RXFIFO is not full.
<> 144:ef7eb2e8f9f7 13012 * | | |1 = The RXFIFO is full and the following incoming packet will be dropped.
<> 144:ef7eb2e8f9f7 13013 * |[4:7] |COLCNT |Collision Count
<> 144:ef7eb2e8f9f7 13014 * | | |The COLCNT indicates that how many collisions occurred consecutively during a packet transmission.
<> 144:ef7eb2e8f9f7 13015 * | | |If the packet incurred 16 consecutive collisions during transmission, the COLCNT will be 0 and bit TXABTIF will be set to 1.
<> 144:ef7eb2e8f9f7 13016 * |[8] |DEF |Deferred Transmission
<> 144:ef7eb2e8f9f7 13017 * | | |The DEF high indicates the packet transmission has deferred once.
<> 144:ef7eb2e8f9f7 13018 * | | |The DEF is only available while EMAC is operating on half-duplex mode.
<> 144:ef7eb2e8f9f7 13019 * | | |0 = Packet transmission does not defer.
<> 144:ef7eb2e8f9f7 13020 * | | |1 = Packet transmission has deferred once.
<> 144:ef7eb2e8f9f7 13021 * |[9] |TXPAUSED |Transmission Paused
<> 144:ef7eb2e8f9f7 13022 * | | |The TXPAUSED high indicates the next normal packet transmission process will be paused temporally because EMAC received a PAUSE control frame.
<> 144:ef7eb2e8f9f7 13023 * | | |0 = Next normal packet transmission process will go on.
<> 144:ef7eb2e8f9f7 13024 * | | |1 = Next normal packet transmission process will be paused.
<> 144:ef7eb2e8f9f7 13025 * |[10] |SQE |Signal Quality Error
<> 144:ef7eb2e8f9f7 13026 * | | |The SQE high indicates the SQE error found at end of packet transmission on 10Mbps half-duplex mode.
<> 144:ef7eb2e8f9f7 13027 * | | |The SQE error check will only be done while both bit SQECHKEN (EMAC_CTL[17]) is enabled and EMAC is operating on 10Mbps half-duplex mode.
<> 144:ef7eb2e8f9f7 13028 * | | |0 = No SQE error found at end of packet transmission.
<> 144:ef7eb2e8f9f7 13029 * | | |1 = SQE error found at end of packet transmission.
<> 144:ef7eb2e8f9f7 13030 * |[11] |TXHALT |Transmission Halted
<> 144:ef7eb2e8f9f7 13031 * | | |The TXHALT high indicates the next normal packet transmission process will be halted because the bit TXON (EMAC_CTL[8]) is disabled be S/W.
<> 144:ef7eb2e8f9f7 13032 * | | |0 = Next normal packet transmission process will go on.
<> 144:ef7eb2e8f9f7 13033 * | | |1 = Next normal packet transmission process will be halted.
<> 144:ef7eb2e8f9f7 13034 * |[12] |RPSTS |Remote Pause Status
<> 144:ef7eb2e8f9f7 13035 * | | |The RPSTS indicates that remote pause counter down counting actives.
<> 144:ef7eb2e8f9f7 13036 * | | |After Ethernet MAC controller sent PAUSE frame out successfully, it starts the remote pause counter down counting.
<> 144:ef7eb2e8f9f7 13037 * | | |When this bit high, it's predictable that remote Ethernet MAC controller wouldn't start the packet transmission until the down counting done.
<> 144:ef7eb2e8f9f7 13038 * | | |0 = Remote pause counter down counting done.
<> 144:ef7eb2e8f9f7 13039 * | | |1 = Remote pause counter down counting actives.
<> 144:ef7eb2e8f9f7 13040 */
<> 144:ef7eb2e8f9f7 13041 __IO uint32_t GENSTS;
<> 144:ef7eb2e8f9f7 13042
<> 144:ef7eb2e8f9f7 13043 /**
<> 144:ef7eb2e8f9f7 13044 * MPCNT
<> 144:ef7eb2e8f9f7 13045 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13046 * Offset: 0xB8 Missed Packet Count Register
<> 144:ef7eb2e8f9f7 13047 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13048 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13049 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13050 * |[0:15] |MPCNT |Miss Packet Count
<> 144:ef7eb2e8f9f7 13051 * | | |The MPCNT indicates the number of packets that were dropped due to various types of receive errors.
<> 144:ef7eb2e8f9f7 13052 * | | |The following type of receiving error makes missed packet counter increase:.
<> 144:ef7eb2e8f9f7 13053 * | | |1. Incoming packet is incurred RXFIFO overflow.
<> 144:ef7eb2e8f9f7 13054 * | | |2. Incoming packet is dropped due to RXON is disabled.
<> 144:ef7eb2e8f9f7 13055 * | | |3. Incoming packet is incurred CRC error.
<> 144:ef7eb2e8f9f7 13056 */
<> 144:ef7eb2e8f9f7 13057 __IO uint32_t MPCNT;
<> 144:ef7eb2e8f9f7 13058
<> 144:ef7eb2e8f9f7 13059 /**
<> 144:ef7eb2e8f9f7 13060 * RPCNT
<> 144:ef7eb2e8f9f7 13061 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13062 * Offset: 0xBC MAC Receive Pause Count Register
<> 144:ef7eb2e8f9f7 13063 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13064 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13065 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13066 * |[0:15] |RPCNT |MAC Receive Pause Count
<> 144:ef7eb2e8f9f7 13067 * | | |The RPCNT keeps the OPERAND field of the PAUSE control frame.
<> 144:ef7eb2e8f9f7 13068 * | | |It indicates how many slot time (512 bit time) the TX of EMAC will be paused.
<> 144:ef7eb2e8f9f7 13069 */
<> 144:ef7eb2e8f9f7 13070 __I uint32_t RPCNT;
<> 144:ef7eb2e8f9f7 13071 uint32_t RESERVE0[2];
<> 144:ef7eb2e8f9f7 13072
<> 144:ef7eb2e8f9f7 13073
<> 144:ef7eb2e8f9f7 13074 /**
<> 144:ef7eb2e8f9f7 13075 * FRSTS
<> 144:ef7eb2e8f9f7 13076 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13077 * Offset: 0xC8 DMA Receive Frame Status Register
<> 144:ef7eb2e8f9f7 13078 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13079 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13080 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13081 * |[0:15] |RXFLT |Receive Frame LENGTH
<> 144:ef7eb2e8f9f7 13082 * | | |The RXFLT keeps the LENGTH field of each incoming Ethernet packet.
<> 144:ef7eb2e8f9f7 13083 * | | |If the bit DENIEN (EMAC_INTEN[9]) is enabled and the LENGTH field of incoming packet has received, the bit DENIF (EMAC_INTSTS[9]) will be set and trigger interrupt.
<> 144:ef7eb2e8f9f7 13084 * | | |And, the content of LENGTH field will be stored in RXFLT.
<> 144:ef7eb2e8f9f7 13085 */
<> 144:ef7eb2e8f9f7 13086 __IO uint32_t FRSTS;
<> 144:ef7eb2e8f9f7 13087
<> 144:ef7eb2e8f9f7 13088 /**
<> 144:ef7eb2e8f9f7 13089 * CTXDSA
<> 144:ef7eb2e8f9f7 13090 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13091 * Offset: 0xCC Current Transmit Descriptor Start Address Register
<> 144:ef7eb2e8f9f7 13092 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13093 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13094 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13095 * |[0:31] |CTXDSA |Current Transmit Descriptor Start Address
<> 144:ef7eb2e8f9f7 13096 * | | |The CTXDSA keeps the start address of TX descriptor that is used by TXDMA currently.
<> 144:ef7eb2e8f9f7 13097 * | | |The CTXDSA is read only and write to this register has no effect.
<> 144:ef7eb2e8f9f7 13098 */
<> 144:ef7eb2e8f9f7 13099 __I uint32_t CTXDSA;
<> 144:ef7eb2e8f9f7 13100
<> 144:ef7eb2e8f9f7 13101 /**
<> 144:ef7eb2e8f9f7 13102 * CTXBSA
<> 144:ef7eb2e8f9f7 13103 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13104 * Offset: 0xD0 Current Transmit Buffer Start Address Register
<> 144:ef7eb2e8f9f7 13105 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13106 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13107 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13108 * |[0:31] |CTXBSA |Current Transmit Buffer Start Address
<> 144:ef7eb2e8f9f7 13109 * | | |The CTXDSA keeps the start address of TX frame buffer that is used by TXDMA currently.
<> 144:ef7eb2e8f9f7 13110 * | | |The CTXBSA is read only and write to this register has no effect.
<> 144:ef7eb2e8f9f7 13111 */
<> 144:ef7eb2e8f9f7 13112 __I uint32_t CTXBSA;
<> 144:ef7eb2e8f9f7 13113
<> 144:ef7eb2e8f9f7 13114 /**
<> 144:ef7eb2e8f9f7 13115 * CRXDSA
<> 144:ef7eb2e8f9f7 13116 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13117 * Offset: 0xD4 Current Receive Descriptor Start Address Register
<> 144:ef7eb2e8f9f7 13118 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13119 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13120 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13121 * |[0:31] |CRXDSA |Current Receive Descriptor Start Address
<> 144:ef7eb2e8f9f7 13122 * | | |The CRXDSA keeps the start address of RX descriptor that is used by RXDMA currently.
<> 144:ef7eb2e8f9f7 13123 * | | |The CRXDSA is read only and write to this register has no effect.
<> 144:ef7eb2e8f9f7 13124 */
<> 144:ef7eb2e8f9f7 13125 __I uint32_t CRXDSA;
<> 144:ef7eb2e8f9f7 13126
<> 144:ef7eb2e8f9f7 13127 /**
<> 144:ef7eb2e8f9f7 13128 * CRXBSA
<> 144:ef7eb2e8f9f7 13129 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13130 * Offset: 0xD8 Current Receive Buffer Start Address Register
<> 144:ef7eb2e8f9f7 13131 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13132 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13133 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13134 * |[0:31] |CRXBSA |Current Receive Buffer Start Address
<> 144:ef7eb2e8f9f7 13135 * | | |The CRXBSA keeps the start address of RX frame buffer that is used by RXDMA currently.
<> 144:ef7eb2e8f9f7 13136 * | | |The CRXBSA is read only and write to this register has no effect.
<> 144:ef7eb2e8f9f7 13137 */
<> 144:ef7eb2e8f9f7 13138 __I uint32_t CRXBSA;
<> 144:ef7eb2e8f9f7 13139 uint32_t RESERVE1[9];
<> 144:ef7eb2e8f9f7 13140
<> 144:ef7eb2e8f9f7 13141
<> 144:ef7eb2e8f9f7 13142 /**
<> 144:ef7eb2e8f9f7 13143 * TSCTL
<> 144:ef7eb2e8f9f7 13144 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13145 * Offset: 0x100 Time Stamp Control Register
<> 144:ef7eb2e8f9f7 13146 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13147 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13148 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13149 * |[0] |TSEN |Time Stamp Function Enable Control
<> 144:ef7eb2e8f9f7 13150 * | | |This bit controls if the IEEE 1588 PTP time stamp function is enabled or not.
<> 144:ef7eb2e8f9f7 13151 * | | |Set this bit high to enable IEEE 1588 PTP time stamp function while set this bit low to disable IEEE 1588 PTP time stamp function.
<> 144:ef7eb2e8f9f7 13152 * | | |0 = I EEE 1588 PTP time stamp function Disabled.
<> 144:ef7eb2e8f9f7 13153 * | | |1 = IEEE 1588 PTP time stamp function Enabled.
<> 144:ef7eb2e8f9f7 13154 * |[1] |TSIEN |Time Stamp Counter Initialization Enable Control
<> 144:ef7eb2e8f9f7 13155 * | | |Set this bit high enables Ethernet MAC controller to load value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stampe counter.
<> 144:ef7eb2e8f9f7 13156 * | | |After the load operation finished, Ethernet MAC controller clear this bit to low automatically.
<> 144:ef7eb2e8f9f7 13157 * | | |0 = Time stamp counter initialization done.
<> 144:ef7eb2e8f9f7 13158 * | | |1 = Time stamp counter initialization Enabled.
<> 144:ef7eb2e8f9f7 13159 * |[2] |TSMODE |Time Stamp Fine Update Enable Control
<> 144:ef7eb2e8f9f7 13160 * | | |This bit chooses the time stamp counter update mode.
<> 144:ef7eb2e8f9f7 13161 * | | |0 = Time stamp counter is in coarse update mode.
<> 144:ef7eb2e8f9f7 13162 * | | |1 = Time stamp counter is in fine update mode.
<> 144:ef7eb2e8f9f7 13163 * |[3] |TSUPDATE |Time Stamp Counter Time Update Enable Control
<> 144:ef7eb2e8f9f7 13164 * | | |Set this bit high enables Ethernet MAC controller to add value of register EMAC_UPDSEC and EMAC_UPDSUBSEC to PTP time stamp counter.
<> 144:ef7eb2e8f9f7 13165 * | | |After the add operation finished, Ethernet MAC controller clear this bit to low automatically.
<> 144:ef7eb2e8f9f7 13166 * | | |0 = No action.
<> 144:ef7eb2e8f9f7 13167 * | | |1 = EMAC_UPDSEC updated to EMAC_TSSEC and EMAC_UPDSUBSEC updated to EMAC_TSSUBSEC.
<> 144:ef7eb2e8f9f7 13168 * |[5] |TSALMEN |Time Stamp Alarm Enable Control
<> 144:ef7eb2e8f9f7 13169 * | | |Set this bit high enable Ethernet MAC controller to set TSALMIF (EMAC_INTSTS[28]) high when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
<> 144:ef7eb2e8f9f7 13170 * | | |0 = Alarm disabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
<> 144:ef7eb2e8f9f7 13171 * | | |1 = Alarm enabled when EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC.
<> 144:ef7eb2e8f9f7 13172 */
<> 144:ef7eb2e8f9f7 13173 __IO uint32_t TSCTL;
<> 144:ef7eb2e8f9f7 13174 uint32_t RESERVE2[3];
<> 144:ef7eb2e8f9f7 13175
<> 144:ef7eb2e8f9f7 13176
<> 144:ef7eb2e8f9f7 13177 /**
<> 144:ef7eb2e8f9f7 13178 * TSSEC
<> 144:ef7eb2e8f9f7 13179 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13180 * Offset: 0x110 Time Stamp Most Significant Register
<> 144:ef7eb2e8f9f7 13181 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13182 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13183 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13184 * |[0:31] |SEC |Time Stamp Counter Second
<> 144:ef7eb2e8f9f7 13185 * | | |This register reflects the bit [63:32] value of 64-bit reference timing counter.
<> 144:ef7eb2e8f9f7 13186 * | | |This 32-bit value is used as the second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
<> 144:ef7eb2e8f9f7 13187 */
<> 144:ef7eb2e8f9f7 13188 __I uint32_t TSSEC;
<> 144:ef7eb2e8f9f7 13189
<> 144:ef7eb2e8f9f7 13190 /**
<> 144:ef7eb2e8f9f7 13191 * TSSUBSEC
<> 144:ef7eb2e8f9f7 13192 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13193 * Offset: 0x114 Time Stamp Least Significant Register
<> 144:ef7eb2e8f9f7 13194 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13195 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13196 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13197 * |[0:31] |SUBSEC |Time Stamp Counter Sub-Second
<> 144:ef7eb2e8f9f7 13198 * | | |This register reflects the bit [31:0] value of 64-bit reference timing counter.
<> 144:ef7eb2e8f9f7 13199 * | | |This 32-bit value is used as the sub-second part of time stamp when TSEN (EMAC_TSCTL[0]) is high.
<> 144:ef7eb2e8f9f7 13200 */
<> 144:ef7eb2e8f9f7 13201 __I uint32_t TSSUBSEC;
<> 144:ef7eb2e8f9f7 13202
<> 144:ef7eb2e8f9f7 13203 /**
<> 144:ef7eb2e8f9f7 13204 * TSINC
<> 144:ef7eb2e8f9f7 13205 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13206 * Offset: 0x118 Time Stamp Increment Register
<> 144:ef7eb2e8f9f7 13207 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13208 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13209 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13210 * |[0:7] |CNTINC |Time Stamp Counter Increment
<> 144:ef7eb2e8f9f7 13211 * | | |Time stamp counter increment value.
<> 144:ef7eb2e8f9f7 13212 * | | |If TSEN (EMAC_TSCTL[0]) is high, EMAC adds EMAC_TSSUBSEC with this 8-bit value every time when it wants to increase the EMAC_TSSUBSEC value.
<> 144:ef7eb2e8f9f7 13213 */
<> 144:ef7eb2e8f9f7 13214 __IO uint32_t TSINC;
<> 144:ef7eb2e8f9f7 13215
<> 144:ef7eb2e8f9f7 13216 /**
<> 144:ef7eb2e8f9f7 13217 * TSADDEND
<> 144:ef7eb2e8f9f7 13218 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13219 * Offset: 0x11C Time Stamp Addend Register
<> 144:ef7eb2e8f9f7 13220 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13221 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13222 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13223 * |[0:31] |ADDEND |Time Stamp Counter Addend
<> 144:ef7eb2e8f9f7 13224 * | | |This register keeps a 32-bit value for accumulator to enable increment of EMAC_TSSUBSEC.
<> 144:ef7eb2e8f9f7 13225 * | | |If TSEN (EMAC_TSCTL[0]) and TSMODE (EMAC_TSCTL[2]) are both high, EMAC increases accumulator with this 32-bit value in each HCLK.
<> 144:ef7eb2e8f9f7 13226 * | | |Once the accumulator is overflow, it generates a enable to increase EMAC_TSSUBSEC with an 8-bit value kept in register EMAC_TSINC.
<> 144:ef7eb2e8f9f7 13227 */
<> 144:ef7eb2e8f9f7 13228 __IO uint32_t TSADDEND;
<> 144:ef7eb2e8f9f7 13229
<> 144:ef7eb2e8f9f7 13230 /**
<> 144:ef7eb2e8f9f7 13231 * UPDSEC
<> 144:ef7eb2e8f9f7 13232 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13233 * Offset: 0x120 Time Stamp Most Significant Update Register
<> 144:ef7eb2e8f9f7 13234 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13235 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13236 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13237 * |[0:31] |SEC |Time Stamp Counter Second Update
<> 144:ef7eb2e8f9f7 13238 * | | |When TSIEN (EMAC_TSCTL[1]) is high.
<> 144:ef7eb2e8f9f7 13239 * | | |EMAC loads this 32-bit value to EMAC_TSSEC directly.
<> 144:ef7eb2e8f9f7 13240 * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSEC with this 32-bit value.
<> 144:ef7eb2e8f9f7 13241 */
<> 144:ef7eb2e8f9f7 13242 __IO uint32_t UPDSEC;
<> 144:ef7eb2e8f9f7 13243
<> 144:ef7eb2e8f9f7 13244 /**
<> 144:ef7eb2e8f9f7 13245 * UPDSUBSEC
<> 144:ef7eb2e8f9f7 13246 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13247 * Offset: 0x124 Time Stamp Least Significant Update Register
<> 144:ef7eb2e8f9f7 13248 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13249 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13250 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13251 * |[0:31] |SUBSEC |Time Stamp Counter Sub-Second Update
<> 144:ef7eb2e8f9f7 13252 * | | |When TSIEN (EMAC_TSCTL[1]) is high.
<> 144:ef7eb2e8f9f7 13253 * | | |EMAC loads this 32-bit value to EMAC_TSSUBSEC directly.
<> 144:ef7eb2e8f9f7 13254 * | | |When TSUPDATE (EMAC_TSCTL[3]) is high, EMAC increases EMAC_TSSUBSEC with this 32-bit value.
<> 144:ef7eb2e8f9f7 13255 */
<> 144:ef7eb2e8f9f7 13256 __IO uint32_t UPDSUBSEC;
<> 144:ef7eb2e8f9f7 13257
<> 144:ef7eb2e8f9f7 13258 /**
<> 144:ef7eb2e8f9f7 13259 * ALMSEC
<> 144:ef7eb2e8f9f7 13260 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13261 * Offset: 0x128 Time Stamp Most Significant Alarm Register
<> 144:ef7eb2e8f9f7 13262 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13263 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13264 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13265 * |[0:31] |SEC |Time Stamp Counter Second Alarm
<> 144:ef7eb2e8f9f7 13266 * | | |Time stamp counter second part alarm value.
<> 144:ef7eb2e8f9f7 13267 * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high.
<> 144:ef7eb2e8f9f7 13268 * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
<> 144:ef7eb2e8f9f7 13269 */
<> 144:ef7eb2e8f9f7 13270 __IO uint32_t ALMSEC;
<> 144:ef7eb2e8f9f7 13271
<> 144:ef7eb2e8f9f7 13272 /**
<> 144:ef7eb2e8f9f7 13273 * ALMSUBSEC
<> 144:ef7eb2e8f9f7 13274 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13275 * Offset: 0x12C Time Stamp Least Significant Alarm Register
<> 144:ef7eb2e8f9f7 13276 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13277 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13278 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13279 * |[0:31] |SUBSEC |Time Stamp Counter Sub-Second Alarm
<> 144:ef7eb2e8f9f7 13280 * | | |Time stamp counter sub-second part alarm value.
<> 144:ef7eb2e8f9f7 13281 * | | |This value is only useful when ALMEN (EMAC_TSCTL[5]) high.
<> 144:ef7eb2e8f9f7 13282 * | | |If ALMEN (EMAC_TSCTL[5]) is high, EMAC_TSSEC equals to EMAC_ALMSEC and EMAC_TSSUBSEC equals to EMAC_ALMSUBSEC, Ethernet MAC controller set TSALMIF (EMAC_INTSTS[28]) high.
<> 144:ef7eb2e8f9f7 13283 */
<> 144:ef7eb2e8f9f7 13284 __IO uint32_t ALMSUBSEC;
<> 144:ef7eb2e8f9f7 13285
<> 144:ef7eb2e8f9f7 13286 } EMAC_T;
<> 144:ef7eb2e8f9f7 13287
<> 144:ef7eb2e8f9f7 13288 /**
<> 144:ef7eb2e8f9f7 13289 @addtogroup EMAC_CONST EMAC Bit Field Definition
<> 144:ef7eb2e8f9f7 13290 Constant Definitions for EMAC Controller
<> 144:ef7eb2e8f9f7 13291 @{ */
<> 144:ef7eb2e8f9f7 13292
<> 144:ef7eb2e8f9f7 13293 #define EMAC_CAMCTL_AUP_Pos (0) /*!< EMAC CAMCTL: AUP Position */
<> 144:ef7eb2e8f9f7 13294 #define EMAC_CAMCTL_AUP_Msk (0x1ul << EMAC_CAMCTL_AUP_Pos) /*!< EMAC CAMCTL: AUP Mask */
<> 144:ef7eb2e8f9f7 13295
<> 144:ef7eb2e8f9f7 13296 #define EMAC_CAMCTL_AMP_Pos (1) /*!< EMAC CAMCTL: AMP Position */
<> 144:ef7eb2e8f9f7 13297 #define EMAC_CAMCTL_AMP_Msk (0x1ul << EMAC_CAMCTL_AMP_Pos) /*!< EMAC CAMCTL: AMP Mask */
<> 144:ef7eb2e8f9f7 13298
<> 144:ef7eb2e8f9f7 13299 #define EMAC_CAMCTL_ABP_Pos (2) /*!< EMAC CAMCTL: ABP Position */
<> 144:ef7eb2e8f9f7 13300 #define EMAC_CAMCTL_ABP_Msk (0x1ul << EMAC_CAMCTL_ABP_Pos) /*!< EMAC CAMCTL: ABP Mask */
<> 144:ef7eb2e8f9f7 13301
<> 144:ef7eb2e8f9f7 13302 #define EMAC_CAMCTL_COMPEN_Pos (3) /*!< EMAC CAMCTL: COMPEN Position */
<> 144:ef7eb2e8f9f7 13303 #define EMAC_CAMCTL_COMPEN_Msk (0x1ul << EMAC_CAMCTL_COMPEN_Pos) /*!< EMAC CAMCTL: COMPEN Mask */
<> 144:ef7eb2e8f9f7 13304
<> 144:ef7eb2e8f9f7 13305 #define EMAC_CAMCTL_CMPEN_Pos (4) /*!< EMAC CAMCTL: CMPEN Position */
<> 144:ef7eb2e8f9f7 13306 #define EMAC_CAMCTL_CMPEN_Msk (0x1ul << EMAC_CAMCTL_CMPEN_Pos) /*!< EMAC CAMCTL: CMPEN Mask */
<> 144:ef7eb2e8f9f7 13307
<> 144:ef7eb2e8f9f7 13308 #define EMAC_CAMEN_CAMxEN_Pos (0) /*!< EMAC CAMEN: CAMxEN Position */
<> 144:ef7eb2e8f9f7 13309 #define EMAC_CAMEN_CAMxEN_Msk (0x1ul << EMAC_CAMEN_CAMxEN_Pos) /*!< EMAC CAMEN: CAMxEN Mask */
<> 144:ef7eb2e8f9f7 13310
<> 144:ef7eb2e8f9f7 13311 #define EMAC_CAM0M_MACADDR2_Pos (0) /*!< EMAC CAM0M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13312 #define EMAC_CAM0M_MACADDR2_Msk (0xfful << EMAC_CAM0M_MACADDR2_Pos) /*!< EMAC CAM0M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13313
<> 144:ef7eb2e8f9f7 13314 #define EMAC_CAM0M_MACADDR3_Pos (8) /*!< EMAC CAM0M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13315 #define EMAC_CAM0M_MACADDR3_Msk (0xfful << EMAC_CAM0M_MACADDR3_Pos) /*!< EMAC CAM0M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13316
<> 144:ef7eb2e8f9f7 13317 #define EMAC_CAM0M_MACADDR4_Pos (16) /*!< EMAC CAM0M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13318 #define EMAC_CAM0M_MACADDR4_Msk (0xfful << EMAC_CAM0M_MACADDR4_Pos) /*!< EMAC CAM0M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13319
<> 144:ef7eb2e8f9f7 13320 #define EMAC_CAM0M_MACADDR5_Pos (24) /*!< EMAC CAM0M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13321 #define EMAC_CAM0M_MACADDR5_Msk (0xfful << EMAC_CAM0M_MACADDR5_Pos) /*!< EMAC CAM0M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13322
<> 144:ef7eb2e8f9f7 13323 #define EMAC_CAM0L_Rserved_Pos (0) /*!< EMAC CAM0L: Rserved Position */
<> 144:ef7eb2e8f9f7 13324 #define EMAC_CAM0L_Rserved_Msk (0xfffful << EMAC_CAM0L_Rserved_Pos) /*!< EMAC CAM0L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13325
<> 144:ef7eb2e8f9f7 13326 #define EMAC_CAM0L_MACADDR0_Pos (16) /*!< EMAC CAM0L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13327 #define EMAC_CAM0L_MACADDR0_Msk (0xfful << EMAC_CAM0L_MACADDR0_Pos) /*!< EMAC CAM0L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13328
<> 144:ef7eb2e8f9f7 13329 #define EMAC_CAM0L_MACADDR1_Pos (24) /*!< EMAC CAM0L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13330 #define EMAC_CAM0L_MACADDR1_Msk (0xfful << EMAC_CAM0L_MACADDR1_Pos) /*!< EMAC CAM0L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13331
<> 144:ef7eb2e8f9f7 13332 #define EMAC_CAM1M_MACADDR2_Pos (0) /*!< EMAC CAM1M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13333 #define EMAC_CAM1M_MACADDR2_Msk (0xfful << EMAC_CAM1M_MACADDR2_Pos) /*!< EMAC CAM1M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13334
<> 144:ef7eb2e8f9f7 13335 #define EMAC_CAM1M_MACADDR3_Pos (8) /*!< EMAC CAM1M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13336 #define EMAC_CAM1M_MACADDR3_Msk (0xfful << EMAC_CAM1M_MACADDR3_Pos) /*!< EMAC CAM1M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13337
<> 144:ef7eb2e8f9f7 13338 #define EMAC_CAM1M_MACADDR4_Pos (16) /*!< EMAC CAM1M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13339 #define EMAC_CAM1M_MACADDR4_Msk (0xfful << EMAC_CAM1M_MACADDR4_Pos) /*!< EMAC CAM1M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13340
<> 144:ef7eb2e8f9f7 13341 #define EMAC_CAM1M_MACADDR5_Pos (24) /*!< EMAC CAM1M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13342 #define EMAC_CAM1M_MACADDR5_Msk (0xfful << EMAC_CAM1M_MACADDR5_Pos) /*!< EMAC CAM1M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13343
<> 144:ef7eb2e8f9f7 13344 #define EMAC_CAM1L_Rserved_Pos (0) /*!< EMAC CAM1L: Rserved Position */
<> 144:ef7eb2e8f9f7 13345 #define EMAC_CAM1L_Rserved_Msk (0xfffful << EMAC_CAM1L_Rserved_Pos) /*!< EMAC CAM1L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13346
<> 144:ef7eb2e8f9f7 13347 #define EMAC_CAM1L_MACADDR0_Pos (16) /*!< EMAC CAM1L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13348 #define EMAC_CAM1L_MACADDR0_Msk (0xfful << EMAC_CAM1L_MACADDR0_Pos) /*!< EMAC CAM1L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13349
<> 144:ef7eb2e8f9f7 13350 #define EMAC_CAM1L_MACADDR1_Pos (24) /*!< EMAC CAM1L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13351 #define EMAC_CAM1L_MACADDR1_Msk (0xfful << EMAC_CAM1L_MACADDR1_Pos) /*!< EMAC CAM1L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13352
<> 144:ef7eb2e8f9f7 13353 #define EMAC_CAM2M_MACADDR2_Pos (0) /*!< EMAC CAM2M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13354 #define EMAC_CAM2M_MACADDR2_Msk (0xfful << EMAC_CAM2M_MACADDR2_Pos) /*!< EMAC CAM2M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13355
<> 144:ef7eb2e8f9f7 13356 #define EMAC_CAM2M_MACADDR3_Pos (8) /*!< EMAC CAM2M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13357 #define EMAC_CAM2M_MACADDR3_Msk (0xfful << EMAC_CAM2M_MACADDR3_Pos) /*!< EMAC CAM2M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13358
<> 144:ef7eb2e8f9f7 13359 #define EMAC_CAM2M_MACADDR4_Pos (16) /*!< EMAC CAM2M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13360 #define EMAC_CAM2M_MACADDR4_Msk (0xfful << EMAC_CAM2M_MACADDR4_Pos) /*!< EMAC CAM2M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13361
<> 144:ef7eb2e8f9f7 13362 #define EMAC_CAM2M_MACADDR5_Pos (24) /*!< EMAC CAM2M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13363 #define EMAC_CAM2M_MACADDR5_Msk (0xfful << EMAC_CAM2M_MACADDR5_Pos) /*!< EMAC CAM2M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13364
<> 144:ef7eb2e8f9f7 13365 #define EMAC_CAM2L_Rserved_Pos (0) /*!< EMAC CAM2L: Rserved Position */
<> 144:ef7eb2e8f9f7 13366 #define EMAC_CAM2L_Rserved_Msk (0xfffful << EMAC_CAM2L_Rserved_Pos) /*!< EMAC CAM2L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13367
<> 144:ef7eb2e8f9f7 13368 #define EMAC_CAM2L_MACADDR0_Pos (16) /*!< EMAC CAM2L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13369 #define EMAC_CAM2L_MACADDR0_Msk (0xfful << EMAC_CAM2L_MACADDR0_Pos) /*!< EMAC CAM2L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13370
<> 144:ef7eb2e8f9f7 13371 #define EMAC_CAM2L_MACADDR1_Pos (24) /*!< EMAC CAM2L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13372 #define EMAC_CAM2L_MACADDR1_Msk (0xfful << EMAC_CAM2L_MACADDR1_Pos) /*!< EMAC CAM2L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13373
<> 144:ef7eb2e8f9f7 13374 #define EMAC_CAM3M_MACADDR2_Pos (0) /*!< EMAC CAM3M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13375 #define EMAC_CAM3M_MACADDR2_Msk (0xfful << EMAC_CAM3M_MACADDR2_Pos) /*!< EMAC CAM3M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13376
<> 144:ef7eb2e8f9f7 13377 #define EMAC_CAM3M_MACADDR3_Pos (8) /*!< EMAC CAM3M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13378 #define EMAC_CAM3M_MACADDR3_Msk (0xfful << EMAC_CAM3M_MACADDR3_Pos) /*!< EMAC CAM3M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13379
<> 144:ef7eb2e8f9f7 13380 #define EMAC_CAM3M_MACADDR4_Pos (16) /*!< EMAC CAM3M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13381 #define EMAC_CAM3M_MACADDR4_Msk (0xfful << EMAC_CAM3M_MACADDR4_Pos) /*!< EMAC CAM3M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13382
<> 144:ef7eb2e8f9f7 13383 #define EMAC_CAM3M_MACADDR5_Pos (24) /*!< EMAC CAM3M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13384 #define EMAC_CAM3M_MACADDR5_Msk (0xfful << EMAC_CAM3M_MACADDR5_Pos) /*!< EMAC CAM3M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13385
<> 144:ef7eb2e8f9f7 13386 #define EMAC_CAM3L_Rserved_Pos (0) /*!< EMAC CAM3L: Rserved Position */
<> 144:ef7eb2e8f9f7 13387 #define EMAC_CAM3L_Rserved_Msk (0xfffful << EMAC_CAM3L_Rserved_Pos) /*!< EMAC CAM3L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13388
<> 144:ef7eb2e8f9f7 13389 #define EMAC_CAM3L_MACADDR0_Pos (16) /*!< EMAC CAM3L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13390 #define EMAC_CAM3L_MACADDR0_Msk (0xfful << EMAC_CAM3L_MACADDR0_Pos) /*!< EMAC CAM3L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13391
<> 144:ef7eb2e8f9f7 13392 #define EMAC_CAM3L_MACADDR1_Pos (24) /*!< EMAC CAM3L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13393 #define EMAC_CAM3L_MACADDR1_Msk (0xfful << EMAC_CAM3L_MACADDR1_Pos) /*!< EMAC CAM3L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13394
<> 144:ef7eb2e8f9f7 13395 #define EMAC_CAM4M_MACADDR2_Pos (0) /*!< EMAC CAM4M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13396 #define EMAC_CAM4M_MACADDR2_Msk (0xfful << EMAC_CAM4M_MACADDR2_Pos) /*!< EMAC CAM4M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13397
<> 144:ef7eb2e8f9f7 13398 #define EMAC_CAM4M_MACADDR3_Pos (8) /*!< EMAC CAM4M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13399 #define EMAC_CAM4M_MACADDR3_Msk (0xfful << EMAC_CAM4M_MACADDR3_Pos) /*!< EMAC CAM4M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13400
<> 144:ef7eb2e8f9f7 13401 #define EMAC_CAM4M_MACADDR4_Pos (16) /*!< EMAC CAM4M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13402 #define EMAC_CAM4M_MACADDR4_Msk (0xfful << EMAC_CAM4M_MACADDR4_Pos) /*!< EMAC CAM4M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13403
<> 144:ef7eb2e8f9f7 13404 #define EMAC_CAM4M_MACADDR5_Pos (24) /*!< EMAC CAM4M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13405 #define EMAC_CAM4M_MACADDR5_Msk (0xfful << EMAC_CAM4M_MACADDR5_Pos) /*!< EMAC CAM4M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13406
<> 144:ef7eb2e8f9f7 13407 #define EMAC_CAM4L_Rserved_Pos (0) /*!< EMAC CAM4L: Rserved Position */
<> 144:ef7eb2e8f9f7 13408 #define EMAC_CAM4L_Rserved_Msk (0xfffful << EMAC_CAM4L_Rserved_Pos) /*!< EMAC CAM4L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13409
<> 144:ef7eb2e8f9f7 13410 #define EMAC_CAM4L_MACADDR0_Pos (16) /*!< EMAC CAM4L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13411 #define EMAC_CAM4L_MACADDR0_Msk (0xfful << EMAC_CAM4L_MACADDR0_Pos) /*!< EMAC CAM4L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13412
<> 144:ef7eb2e8f9f7 13413 #define EMAC_CAM4L_MACADDR1_Pos (24) /*!< EMAC CAM4L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13414 #define EMAC_CAM4L_MACADDR1_Msk (0xfful << EMAC_CAM4L_MACADDR1_Pos) /*!< EMAC CAM4L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13415
<> 144:ef7eb2e8f9f7 13416 #define EMAC_CAM5M_MACADDR2_Pos (0) /*!< EMAC CAM5M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13417 #define EMAC_CAM5M_MACADDR2_Msk (0xfful << EMAC_CAM5M_MACADDR2_Pos) /*!< EMAC CAM5M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13418
<> 144:ef7eb2e8f9f7 13419 #define EMAC_CAM5M_MACADDR3_Pos (8) /*!< EMAC CAM5M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13420 #define EMAC_CAM5M_MACADDR3_Msk (0xfful << EMAC_CAM5M_MACADDR3_Pos) /*!< EMAC CAM5M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13421
<> 144:ef7eb2e8f9f7 13422 #define EMAC_CAM5M_MACADDR4_Pos (16) /*!< EMAC CAM5M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13423 #define EMAC_CAM5M_MACADDR4_Msk (0xfful << EMAC_CAM5M_MACADDR4_Pos) /*!< EMAC CAM5M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13424
<> 144:ef7eb2e8f9f7 13425 #define EMAC_CAM5M_MACADDR5_Pos (24) /*!< EMAC CAM5M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13426 #define EMAC_CAM5M_MACADDR5_Msk (0xfful << EMAC_CAM5M_MACADDR5_Pos) /*!< EMAC CAM5M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13427
<> 144:ef7eb2e8f9f7 13428 #define EMAC_CAM5L_Rserved_Pos (0) /*!< EMAC CAM5L: Rserved Position */
<> 144:ef7eb2e8f9f7 13429 #define EMAC_CAM5L_Rserved_Msk (0xfffful << EMAC_CAM5L_Rserved_Pos) /*!< EMAC CAM5L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13430
<> 144:ef7eb2e8f9f7 13431 #define EMAC_CAM5L_MACADDR0_Pos (16) /*!< EMAC CAM5L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13432 #define EMAC_CAM5L_MACADDR0_Msk (0xfful << EMAC_CAM5L_MACADDR0_Pos) /*!< EMAC CAM5L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13433
<> 144:ef7eb2e8f9f7 13434 #define EMAC_CAM5L_MACADDR1_Pos (24) /*!< EMAC CAM5L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13435 #define EMAC_CAM5L_MACADDR1_Msk (0xfful << EMAC_CAM5L_MACADDR1_Pos) /*!< EMAC CAM5L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13436
<> 144:ef7eb2e8f9f7 13437 #define EMAC_CAM6M_MACADDR2_Pos (0) /*!< EMAC CAM6M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13438 #define EMAC_CAM6M_MACADDR2_Msk (0xfful << EMAC_CAM6M_MACADDR2_Pos) /*!< EMAC CAM6M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13439
<> 144:ef7eb2e8f9f7 13440 #define EMAC_CAM6M_MACADDR3_Pos (8) /*!< EMAC CAM6M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13441 #define EMAC_CAM6M_MACADDR3_Msk (0xfful << EMAC_CAM6M_MACADDR3_Pos) /*!< EMAC CAM6M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13442
<> 144:ef7eb2e8f9f7 13443 #define EMAC_CAM6M_MACADDR4_Pos (16) /*!< EMAC CAM6M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13444 #define EMAC_CAM6M_MACADDR4_Msk (0xfful << EMAC_CAM6M_MACADDR4_Pos) /*!< EMAC CAM6M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13445
<> 144:ef7eb2e8f9f7 13446 #define EMAC_CAM6M_MACADDR5_Pos (24) /*!< EMAC CAM6M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13447 #define EMAC_CAM6M_MACADDR5_Msk (0xfful << EMAC_CAM6M_MACADDR5_Pos) /*!< EMAC CAM6M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13448
<> 144:ef7eb2e8f9f7 13449 #define EMAC_CAM6L_Rserved_Pos (0) /*!< EMAC CAM6L: Rserved Position */
<> 144:ef7eb2e8f9f7 13450 #define EMAC_CAM6L_Rserved_Msk (0xfffful << EMAC_CAM6L_Rserved_Pos) /*!< EMAC CAM6L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13451
<> 144:ef7eb2e8f9f7 13452 #define EMAC_CAM6L_MACADDR0_Pos (16) /*!< EMAC CAM6L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13453 #define EMAC_CAM6L_MACADDR0_Msk (0xfful << EMAC_CAM6L_MACADDR0_Pos) /*!< EMAC CAM6L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13454
<> 144:ef7eb2e8f9f7 13455 #define EMAC_CAM6L_MACADDR1_Pos (24) /*!< EMAC CAM6L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13456 #define EMAC_CAM6L_MACADDR1_Msk (0xfful << EMAC_CAM6L_MACADDR1_Pos) /*!< EMAC CAM6L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13457
<> 144:ef7eb2e8f9f7 13458 #define EMAC_CAM7M_MACADDR2_Pos (0) /*!< EMAC CAM7M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13459 #define EMAC_CAM7M_MACADDR2_Msk (0xfful << EMAC_CAM7M_MACADDR2_Pos) /*!< EMAC CAM7M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13460
<> 144:ef7eb2e8f9f7 13461 #define EMAC_CAM7M_MACADDR3_Pos (8) /*!< EMAC CAM7M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13462 #define EMAC_CAM7M_MACADDR3_Msk (0xfful << EMAC_CAM7M_MACADDR3_Pos) /*!< EMAC CAM7M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13463
<> 144:ef7eb2e8f9f7 13464 #define EMAC_CAM7M_MACADDR4_Pos (16) /*!< EMAC CAM7M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13465 #define EMAC_CAM7M_MACADDR4_Msk (0xfful << EMAC_CAM7M_MACADDR4_Pos) /*!< EMAC CAM7M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13466
<> 144:ef7eb2e8f9f7 13467 #define EMAC_CAM7M_MACADDR5_Pos (24) /*!< EMAC CAM7M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13468 #define EMAC_CAM7M_MACADDR5_Msk (0xfful << EMAC_CAM7M_MACADDR5_Pos) /*!< EMAC CAM7M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13469
<> 144:ef7eb2e8f9f7 13470 #define EMAC_CAM7L_Rserved_Pos (0) /*!< EMAC CAM7L: Rserved Position */
<> 144:ef7eb2e8f9f7 13471 #define EMAC_CAM7L_Rserved_Msk (0xfffful << EMAC_CAM7L_Rserved_Pos) /*!< EMAC CAM7L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13472
<> 144:ef7eb2e8f9f7 13473 #define EMAC_CAM7L_MACADDR0_Pos (16) /*!< EMAC CAM7L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13474 #define EMAC_CAM7L_MACADDR0_Msk (0xfful << EMAC_CAM7L_MACADDR0_Pos) /*!< EMAC CAM7L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13475
<> 144:ef7eb2e8f9f7 13476 #define EMAC_CAM7L_MACADDR1_Pos (24) /*!< EMAC CAM7L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13477 #define EMAC_CAM7L_MACADDR1_Msk (0xfful << EMAC_CAM7L_MACADDR1_Pos) /*!< EMAC CAM7L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13478
<> 144:ef7eb2e8f9f7 13479 #define EMAC_CAM8M_MACADDR2_Pos (0) /*!< EMAC CAM8M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13480 #define EMAC_CAM8M_MACADDR2_Msk (0xfful << EMAC_CAM8M_MACADDR2_Pos) /*!< EMAC CAM8M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13481
<> 144:ef7eb2e8f9f7 13482 #define EMAC_CAM8M_MACADDR3_Pos (8) /*!< EMAC CAM8M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13483 #define EMAC_CAM8M_MACADDR3_Msk (0xfful << EMAC_CAM8M_MACADDR3_Pos) /*!< EMAC CAM8M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13484
<> 144:ef7eb2e8f9f7 13485 #define EMAC_CAM8M_MACADDR4_Pos (16) /*!< EMAC CAM8M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13486 #define EMAC_CAM8M_MACADDR4_Msk (0xfful << EMAC_CAM8M_MACADDR4_Pos) /*!< EMAC CAM8M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13487
<> 144:ef7eb2e8f9f7 13488 #define EMAC_CAM8M_MACADDR5_Pos (24) /*!< EMAC CAM8M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13489 #define EMAC_CAM8M_MACADDR5_Msk (0xfful << EMAC_CAM8M_MACADDR5_Pos) /*!< EMAC CAM8M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13490
<> 144:ef7eb2e8f9f7 13491 #define EMAC_CAM8L_Rserved_Pos (0) /*!< EMAC CAM8L: Rserved Position */
<> 144:ef7eb2e8f9f7 13492 #define EMAC_CAM8L_Rserved_Msk (0xfffful << EMAC_CAM8L_Rserved_Pos) /*!< EMAC CAM8L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13493
<> 144:ef7eb2e8f9f7 13494 #define EMAC_CAM8L_MACADDR0_Pos (16) /*!< EMAC CAM8L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13495 #define EMAC_CAM8L_MACADDR0_Msk (0xfful << EMAC_CAM8L_MACADDR0_Pos) /*!< EMAC CAM8L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13496
<> 144:ef7eb2e8f9f7 13497 #define EMAC_CAM8L_MACADDR1_Pos (24) /*!< EMAC CAM8L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13498 #define EMAC_CAM8L_MACADDR1_Msk (0xfful << EMAC_CAM8L_MACADDR1_Pos) /*!< EMAC CAM8L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13499
<> 144:ef7eb2e8f9f7 13500 #define EMAC_CAM9M_MACADDR2_Pos (0) /*!< EMAC CAM9M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13501 #define EMAC_CAM9M_MACADDR2_Msk (0xfful << EMAC_CAM9M_MACADDR2_Pos) /*!< EMAC CAM9M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13502
<> 144:ef7eb2e8f9f7 13503 #define EMAC_CAM9M_MACADDR3_Pos (8) /*!< EMAC CAM9M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13504 #define EMAC_CAM9M_MACADDR3_Msk (0xfful << EMAC_CAM9M_MACADDR3_Pos) /*!< EMAC CAM9M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13505
<> 144:ef7eb2e8f9f7 13506 #define EMAC_CAM9M_MACADDR4_Pos (16) /*!< EMAC CAM9M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13507 #define EMAC_CAM9M_MACADDR4_Msk (0xfful << EMAC_CAM9M_MACADDR4_Pos) /*!< EMAC CAM9M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13508
<> 144:ef7eb2e8f9f7 13509 #define EMAC_CAM9M_MACADDR5_Pos (24) /*!< EMAC CAM9M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13510 #define EMAC_CAM9M_MACADDR5_Msk (0xfful << EMAC_CAM9M_MACADDR5_Pos) /*!< EMAC CAM9M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13511
<> 144:ef7eb2e8f9f7 13512 #define EMAC_CAM9L_Rserved_Pos (0) /*!< EMAC CAM9L: Rserved Position */
<> 144:ef7eb2e8f9f7 13513 #define EMAC_CAM9L_Rserved_Msk (0xfffful << EMAC_CAM9L_Rserved_Pos) /*!< EMAC CAM9L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13514
<> 144:ef7eb2e8f9f7 13515 #define EMAC_CAM9L_MACADDR0_Pos (16) /*!< EMAC CAM9L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13516 #define EMAC_CAM9L_MACADDR0_Msk (0xfful << EMAC_CAM9L_MACADDR0_Pos) /*!< EMAC CAM9L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13517
<> 144:ef7eb2e8f9f7 13518 #define EMAC_CAM9L_MACADDR1_Pos (24) /*!< EMAC CAM9L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13519 #define EMAC_CAM9L_MACADDR1_Msk (0xfful << EMAC_CAM9L_MACADDR1_Pos) /*!< EMAC CAM9L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13520
<> 144:ef7eb2e8f9f7 13521 #define EMAC_CAM10M_MACADDR2_Pos (0) /*!< EMAC CAM10M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13522 #define EMAC_CAM10M_MACADDR2_Msk (0xfful << EMAC_CAM10M_MACADDR2_Pos) /*!< EMAC CAM10M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13523
<> 144:ef7eb2e8f9f7 13524 #define EMAC_CAM10M_MACADDR3_Pos (8) /*!< EMAC CAM10M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13525 #define EMAC_CAM10M_MACADDR3_Msk (0xfful << EMAC_CAM10M_MACADDR3_Pos) /*!< EMAC CAM10M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13526
<> 144:ef7eb2e8f9f7 13527 #define EMAC_CAM10M_MACADDR4_Pos (16) /*!< EMAC CAM10M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13528 #define EMAC_CAM10M_MACADDR4_Msk (0xfful << EMAC_CAM10M_MACADDR4_Pos) /*!< EMAC CAM10M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13529
<> 144:ef7eb2e8f9f7 13530 #define EMAC_CAM10M_MACADDR5_Pos (24) /*!< EMAC CAM10M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13531 #define EMAC_CAM10M_MACADDR5_Msk (0xfful << EMAC_CAM10M_MACADDR5_Pos) /*!< EMAC CAM10M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13532
<> 144:ef7eb2e8f9f7 13533 #define EMAC_CAM10L_Rserved_Pos (0) /*!< EMAC CAM10L: Rserved Position */
<> 144:ef7eb2e8f9f7 13534 #define EMAC_CAM10L_Rserved_Msk (0xfffful << EMAC_CAM10L_Rserved_Pos) /*!< EMAC CAM10L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13535
<> 144:ef7eb2e8f9f7 13536 #define EMAC_CAM10L_MACADDR0_Pos (16) /*!< EMAC CAM10L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13537 #define EMAC_CAM10L_MACADDR0_Msk (0xfful << EMAC_CAM10L_MACADDR0_Pos) /*!< EMAC CAM10L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13538
<> 144:ef7eb2e8f9f7 13539 #define EMAC_CAM10L_MACADDR1_Pos (24) /*!< EMAC CAM10L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13540 #define EMAC_CAM10L_MACADDR1_Msk (0xfful << EMAC_CAM10L_MACADDR1_Pos) /*!< EMAC CAM10L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13541
<> 144:ef7eb2e8f9f7 13542 #define EMAC_CAM11M_MACADDR2_Pos (0) /*!< EMAC CAM11M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13543 #define EMAC_CAM11M_MACADDR2_Msk (0xfful << EMAC_CAM11M_MACADDR2_Pos) /*!< EMAC CAM11M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13544
<> 144:ef7eb2e8f9f7 13545 #define EMAC_CAM11M_MACADDR3_Pos (8) /*!< EMAC CAM11M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13546 #define EMAC_CAM11M_MACADDR3_Msk (0xfful << EMAC_CAM11M_MACADDR3_Pos) /*!< EMAC CAM11M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13547
<> 144:ef7eb2e8f9f7 13548 #define EMAC_CAM11M_MACADDR4_Pos (16) /*!< EMAC CAM11M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13549 #define EMAC_CAM11M_MACADDR4_Msk (0xfful << EMAC_CAM11M_MACADDR4_Pos) /*!< EMAC CAM11M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13550
<> 144:ef7eb2e8f9f7 13551 #define EMAC_CAM11M_MACADDR5_Pos (24) /*!< EMAC CAM11M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13552 #define EMAC_CAM11M_MACADDR5_Msk (0xfful << EMAC_CAM11M_MACADDR5_Pos) /*!< EMAC CAM11M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13553
<> 144:ef7eb2e8f9f7 13554 #define EMAC_CAM11L_Rserved_Pos (0) /*!< EMAC CAM11L: Rserved Position */
<> 144:ef7eb2e8f9f7 13555 #define EMAC_CAM11L_Rserved_Msk (0xfffful << EMAC_CAM11L_Rserved_Pos) /*!< EMAC CAM11L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13556
<> 144:ef7eb2e8f9f7 13557 #define EMAC_CAM11L_MACADDR0_Pos (16) /*!< EMAC CAM11L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13558 #define EMAC_CAM11L_MACADDR0_Msk (0xfful << EMAC_CAM11L_MACADDR0_Pos) /*!< EMAC CAM11L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13559
<> 144:ef7eb2e8f9f7 13560 #define EMAC_CAM11L_MACADDR1_Pos (24) /*!< EMAC CAM11L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13561 #define EMAC_CAM11L_MACADDR1_Msk (0xfful << EMAC_CAM11L_MACADDR1_Pos) /*!< EMAC CAM11L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13562
<> 144:ef7eb2e8f9f7 13563 #define EMAC_CAM12M_MACADDR2_Pos (0) /*!< EMAC CAM12M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13564 #define EMAC_CAM12M_MACADDR2_Msk (0xfful << EMAC_CAM12M_MACADDR2_Pos) /*!< EMAC CAM12M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13565
<> 144:ef7eb2e8f9f7 13566 #define EMAC_CAM12M_MACADDR3_Pos (8) /*!< EMAC CAM12M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13567 #define EMAC_CAM12M_MACADDR3_Msk (0xfful << EMAC_CAM12M_MACADDR3_Pos) /*!< EMAC CAM12M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13568
<> 144:ef7eb2e8f9f7 13569 #define EMAC_CAM12M_MACADDR4_Pos (16) /*!< EMAC CAM12M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13570 #define EMAC_CAM12M_MACADDR4_Msk (0xfful << EMAC_CAM12M_MACADDR4_Pos) /*!< EMAC CAM12M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13571
<> 144:ef7eb2e8f9f7 13572 #define EMAC_CAM12M_MACADDR5_Pos (24) /*!< EMAC CAM12M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13573 #define EMAC_CAM12M_MACADDR5_Msk (0xfful << EMAC_CAM12M_MACADDR5_Pos) /*!< EMAC CAM12M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13574
<> 144:ef7eb2e8f9f7 13575 #define EMAC_CAM12L_Rserved_Pos (0) /*!< EMAC CAM12L: Rserved Position */
<> 144:ef7eb2e8f9f7 13576 #define EMAC_CAM12L_Rserved_Msk (0xfffful << EMAC_CAM12L_Rserved_Pos) /*!< EMAC CAM12L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13577
<> 144:ef7eb2e8f9f7 13578 #define EMAC_CAM12L_MACADDR0_Pos (16) /*!< EMAC CAM12L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13579 #define EMAC_CAM12L_MACADDR0_Msk (0xfful << EMAC_CAM12L_MACADDR0_Pos) /*!< EMAC CAM12L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13580
<> 144:ef7eb2e8f9f7 13581 #define EMAC_CAM12L_MACADDR1_Pos (24) /*!< EMAC CAM12L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13582 #define EMAC_CAM12L_MACADDR1_Msk (0xfful << EMAC_CAM12L_MACADDR1_Pos) /*!< EMAC CAM12L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13583
<> 144:ef7eb2e8f9f7 13584 #define EMAC_CAM13M_MACADDR2_Pos (0) /*!< EMAC CAM13M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13585 #define EMAC_CAM13M_MACADDR2_Msk (0xfful << EMAC_CAM13M_MACADDR2_Pos) /*!< EMAC CAM13M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13586
<> 144:ef7eb2e8f9f7 13587 #define EMAC_CAM13M_MACADDR3_Pos (8) /*!< EMAC CAM13M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13588 #define EMAC_CAM13M_MACADDR3_Msk (0xfful << EMAC_CAM13M_MACADDR3_Pos) /*!< EMAC CAM13M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13589
<> 144:ef7eb2e8f9f7 13590 #define EMAC_CAM13M_MACADDR4_Pos (16) /*!< EMAC CAM13M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13591 #define EMAC_CAM13M_MACADDR4_Msk (0xfful << EMAC_CAM13M_MACADDR4_Pos) /*!< EMAC CAM13M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13592
<> 144:ef7eb2e8f9f7 13593 #define EMAC_CAM13M_MACADDR5_Pos (24) /*!< EMAC CAM13M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13594 #define EMAC_CAM13M_MACADDR5_Msk (0xfful << EMAC_CAM13M_MACADDR5_Pos) /*!< EMAC CAM13M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13595
<> 144:ef7eb2e8f9f7 13596 #define EMAC_CAM13L_Rserved_Pos (0) /*!< EMAC CAM13L: Rserved Position */
<> 144:ef7eb2e8f9f7 13597 #define EMAC_CAM13L_Rserved_Msk (0xfffful << EMAC_CAM13L_Rserved_Pos) /*!< EMAC CAM13L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13598
<> 144:ef7eb2e8f9f7 13599 #define EMAC_CAM13L_MACADDR0_Pos (16) /*!< EMAC CAM13L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13600 #define EMAC_CAM13L_MACADDR0_Msk (0xfful << EMAC_CAM13L_MACADDR0_Pos) /*!< EMAC CAM13L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13601
<> 144:ef7eb2e8f9f7 13602 #define EMAC_CAM13L_MACADDR1_Pos (24) /*!< EMAC CAM13L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13603 #define EMAC_CAM13L_MACADDR1_Msk (0xfful << EMAC_CAM13L_MACADDR1_Pos) /*!< EMAC CAM13L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13604
<> 144:ef7eb2e8f9f7 13605 #define EMAC_CAM14M_MACADDR2_Pos (0) /*!< EMAC CAM14M: MACADDR2 Position */
<> 144:ef7eb2e8f9f7 13606 #define EMAC_CAM14M_MACADDR2_Msk (0xfful << EMAC_CAM14M_MACADDR2_Pos) /*!< EMAC CAM14M: MACADDR2 Mask */
<> 144:ef7eb2e8f9f7 13607
<> 144:ef7eb2e8f9f7 13608 #define EMAC_CAM14M_MACADDR3_Pos (8) /*!< EMAC CAM14M: MACADDR3 Position */
<> 144:ef7eb2e8f9f7 13609 #define EMAC_CAM14M_MACADDR3_Msk (0xfful << EMAC_CAM14M_MACADDR3_Pos) /*!< EMAC CAM14M: MACADDR3 Mask */
<> 144:ef7eb2e8f9f7 13610
<> 144:ef7eb2e8f9f7 13611 #define EMAC_CAM14M_MACADDR4_Pos (16) /*!< EMAC CAM14M: MACADDR4 Position */
<> 144:ef7eb2e8f9f7 13612 #define EMAC_CAM14M_MACADDR4_Msk (0xfful << EMAC_CAM14M_MACADDR4_Pos) /*!< EMAC CAM14M: MACADDR4 Mask */
<> 144:ef7eb2e8f9f7 13613
<> 144:ef7eb2e8f9f7 13614 #define EMAC_CAM14M_MACADDR5_Pos (24) /*!< EMAC CAM14M: MACADDR5 Position */
<> 144:ef7eb2e8f9f7 13615 #define EMAC_CAM14M_MACADDR5_Msk (0xfful << EMAC_CAM14M_MACADDR5_Pos) /*!< EMAC CAM14M: MACADDR5 Mask */
<> 144:ef7eb2e8f9f7 13616
<> 144:ef7eb2e8f9f7 13617 #define EMAC_CAM14L_Rserved_Pos (0) /*!< EMAC CAM14L: Rserved Position */
<> 144:ef7eb2e8f9f7 13618 #define EMAC_CAM14L_Rserved_Msk (0xfffful << EMAC_CAM14L_Rserved_Pos) /*!< EMAC CAM14L: Rserved Mask */
<> 144:ef7eb2e8f9f7 13619
<> 144:ef7eb2e8f9f7 13620 #define EMAC_CAM14L_MACADDR0_Pos (16) /*!< EMAC CAM14L: MACADDR0 Position */
<> 144:ef7eb2e8f9f7 13621 #define EMAC_CAM14L_MACADDR0_Msk (0xfful << EMAC_CAM14L_MACADDR0_Pos) /*!< EMAC CAM14L: MACADDR0 Mask */
<> 144:ef7eb2e8f9f7 13622
<> 144:ef7eb2e8f9f7 13623 #define EMAC_CAM14L_MACADDR1_Pos (24) /*!< EMAC CAM14L: MACADDR1 Position */
<> 144:ef7eb2e8f9f7 13624 #define EMAC_CAM14L_MACADDR1_Msk (0xfful << EMAC_CAM14L_MACADDR1_Pos) /*!< EMAC CAM14L: MACADDR1 Mask */
<> 144:ef7eb2e8f9f7 13625
<> 144:ef7eb2e8f9f7 13626 #define EMAC_CAM15MSB_OPCODE_Pos (0) /*!< EMAC CAM15MSB: OPCODE Position */
<> 144:ef7eb2e8f9f7 13627 #define EMAC_CAM15MSB_OPCODE_Msk (0xfffful << EMAC_CAM15MSB_OPCODE_Pos) /*!< EMAC CAM15MSB: OPCODE Mask */
<> 144:ef7eb2e8f9f7 13628
<> 144:ef7eb2e8f9f7 13629 #define EMAC_CAM15MSB_LENGTH_Pos (16) /*!< EMAC CAM15MSB: LENGTH Position */
<> 144:ef7eb2e8f9f7 13630 #define EMAC_CAM15MSB_LENGTH_Msk (0xfffful << EMAC_CAM15MSB_LENGTH_Pos) /*!< EMAC CAM15MSB: LENGTH Mask */
<> 144:ef7eb2e8f9f7 13631
<> 144:ef7eb2e8f9f7 13632 #define EMAC_CAM15LSB_OPERAND_Pos (24) /*!< EMAC CAM15LSB: OPERAND Position */
<> 144:ef7eb2e8f9f7 13633 #define EMAC_CAM15LSB_OPERAND_Msk (0xfful << EMAC_CAM15LSB_OPERAND_Pos) /*!< EMAC CAM15LSB: OPERAND Mask */
<> 144:ef7eb2e8f9f7 13634
<> 144:ef7eb2e8f9f7 13635 #define EMAC_TXDSA_TXDSA_Pos (0) /*!< EMAC TXDSA: TXDSA Position */
<> 144:ef7eb2e8f9f7 13636 #define EMAC_TXDSA_TXDSA_Msk (0xfffffffful << EMAC_TXDSA_TXDSA_Pos) /*!< EMAC TXDSA: TXDSA Mask */
<> 144:ef7eb2e8f9f7 13637
<> 144:ef7eb2e8f9f7 13638 #define EMAC_RXDSA_RXDSA_Pos (0) /*!< EMAC RXDSA: RXDSA Position */
<> 144:ef7eb2e8f9f7 13639 #define EMAC_RXDSA_RXDSA_Msk (0xfffffffful << EMAC_RXDSA_RXDSA_Pos) /*!< EMAC RXDSA: RXDSA Mask */
<> 144:ef7eb2e8f9f7 13640
<> 144:ef7eb2e8f9f7 13641 #define EMAC_CTL_RXON_Pos (0) /*!< EMAC CTL: RXON Position */
<> 144:ef7eb2e8f9f7 13642 #define EMAC_CTL_RXON_Msk (0x1ul << EMAC_CTL_RXON_Pos) /*!< EMAC CTL: RXON Mask */
<> 144:ef7eb2e8f9f7 13643
<> 144:ef7eb2e8f9f7 13644 #define EMAC_CTL_ALP_Pos (1) /*!< EMAC CTL: ALP Position */
<> 144:ef7eb2e8f9f7 13645 #define EMAC_CTL_ALP_Msk (0x1ul << EMAC_CTL_ALP_Pos) /*!< EMAC CTL: ALP Mask */
<> 144:ef7eb2e8f9f7 13646
<> 144:ef7eb2e8f9f7 13647 #define EMAC_CTL_ARP_Pos (2) /*!< EMAC CTL: ARP Position */
<> 144:ef7eb2e8f9f7 13648 #define EMAC_CTL_ARP_Msk (0x1ul << EMAC_CTL_ARP_Pos) /*!< EMAC CTL: ARP Mask */
<> 144:ef7eb2e8f9f7 13649
<> 144:ef7eb2e8f9f7 13650 #define EMAC_CTL_ACP_Pos (3) /*!< EMAC CTL: ACP Position */
<> 144:ef7eb2e8f9f7 13651 #define EMAC_CTL_ACP_Msk (0x1ul << EMAC_CTL_ACP_Pos) /*!< EMAC CTL: ACP Mask */
<> 144:ef7eb2e8f9f7 13652
<> 144:ef7eb2e8f9f7 13653 #define EMAC_CTL_AEP_Pos (4) /*!< EMAC CTL: AEP Position */
<> 144:ef7eb2e8f9f7 13654 #define EMAC_CTL_AEP_Msk (0x1ul << EMAC_CTL_AEP_Pos) /*!< EMAC CTL: AEP Mask */
<> 144:ef7eb2e8f9f7 13655
<> 144:ef7eb2e8f9f7 13656 #define EMAC_CTL_STRIPCRC_Pos (5) /*!< EMAC CTL: STRIPCRC Position */
<> 144:ef7eb2e8f9f7 13657 #define EMAC_CTL_STRIPCRC_Msk (0x1ul << EMAC_CTL_STRIPCRC_Pos) /*!< EMAC CTL: STRIPCRC Mask */
<> 144:ef7eb2e8f9f7 13658
<> 144:ef7eb2e8f9f7 13659 #define EMAC_CTL_WOLEN_Pos (6) /*!< EMAC CTL: WOLEN Position */
<> 144:ef7eb2e8f9f7 13660 #define EMAC_CTL_WOLEN_Msk (0x1ul << EMAC_CTL_WOLEN_Pos) /*!< EMAC CTL: WOLEN Mask */
<> 144:ef7eb2e8f9f7 13661
<> 144:ef7eb2e8f9f7 13662 #define EMAC_CTL_TXON_Pos (8) /*!< EMAC CTL: TXON Position */
<> 144:ef7eb2e8f9f7 13663 #define EMAC_CTL_TXON_Msk (0x1ul << EMAC_CTL_TXON_Pos) /*!< EMAC CTL: TXON Mask */
<> 144:ef7eb2e8f9f7 13664
<> 144:ef7eb2e8f9f7 13665 #define EMAC_CTL_NODEF_Pos (9) /*!< EMAC CTL: NODEF Position */
<> 144:ef7eb2e8f9f7 13666 #define EMAC_CTL_NODEF_Msk (0x1ul << EMAC_CTL_NODEF_Pos) /*!< EMAC CTL: NODEF Mask */
<> 144:ef7eb2e8f9f7 13667
<> 144:ef7eb2e8f9f7 13668 #define EMAC_CTL_SDPZ_Pos (16) /*!< EMAC CTL: SDPZ Position */
<> 144:ef7eb2e8f9f7 13669 #define EMAC_CTL_SDPZ_Msk (0x1ul << EMAC_CTL_SDPZ_Pos) /*!< EMAC CTL: SDPZ Mask */
<> 144:ef7eb2e8f9f7 13670
<> 144:ef7eb2e8f9f7 13671 #define EMAC_CTL_SQECHKEN_Pos (17) /*!< EMAC CTL: SQECHKEN Position */
<> 144:ef7eb2e8f9f7 13672 #define EMAC_CTL_SQECHKEN_Msk (0x1ul << EMAC_CTL_SQECHKEN_Pos) /*!< EMAC CTL: SQECHKEN Mask */
<> 144:ef7eb2e8f9f7 13673
<> 144:ef7eb2e8f9f7 13674 #define EMAC_CTL_FUDUP_Pos (18) /*!< EMAC CTL: FUDUP Position */
<> 144:ef7eb2e8f9f7 13675 #define EMAC_CTL_FUDUP_Msk (0x1ul << EMAC_CTL_FUDUP_Pos) /*!< EMAC CTL: FUDUP Mask */
<> 144:ef7eb2e8f9f7 13676
<> 144:ef7eb2e8f9f7 13677 #define EMAC_CTL_RMIIRXCTL_Pos (19) /*!< EMAC CTL: RMIIRXCTL Position */
<> 144:ef7eb2e8f9f7 13678 #define EMAC_CTL_RMIIRXCTL_Msk (0x1ul << EMAC_CTL_RMIIRXCTL_Pos) /*!< EMAC CTL: RMIIRXCTL Mask */
<> 144:ef7eb2e8f9f7 13679
<> 144:ef7eb2e8f9f7 13680 #define EMAC_CTL_OPMODE_Pos (20) /*!< EMAC CTL: OPMODE Position */
<> 144:ef7eb2e8f9f7 13681 #define EMAC_CTL_OPMODE_Msk (0x1ul << EMAC_CTL_OPMODE_Pos) /*!< EMAC CTL: OPMODE Mask */
<> 144:ef7eb2e8f9f7 13682
<> 144:ef7eb2e8f9f7 13683 #define EMAC_CTL_RMIIEN_Pos (22) /*!< EMAC CTL: RMIIEN Position */
<> 144:ef7eb2e8f9f7 13684 #define EMAC_CTL_RMIIEN_Msk (0x1ul << EMAC_CTL_RMIIEN_Pos) /*!< EMAC CTL: RMIIEN Mask */
<> 144:ef7eb2e8f9f7 13685
<> 144:ef7eb2e8f9f7 13686 #define EMAC_CTL_RST_Pos (24) /*!< EMAC CTL: RST Position */
<> 144:ef7eb2e8f9f7 13687 #define EMAC_CTL_RST_Msk (0x1ul << EMAC_CTL_RST_Pos) /*!< EMAC CTL: RST Mask */
<> 144:ef7eb2e8f9f7 13688
<> 144:ef7eb2e8f9f7 13689 #define EMAC_MIIMDAT_DATA_Pos (0) /*!< EMAC MIIMDAT: DATA Position */
<> 144:ef7eb2e8f9f7 13690 #define EMAC_MIIMDAT_DATA_Msk (0xfffful << EMAC_MIIMDAT_DATA_Pos) /*!< EMAC MIIMDAT: DATA Mask */
<> 144:ef7eb2e8f9f7 13691
<> 144:ef7eb2e8f9f7 13692 #define EMAC_MIIMCTL_PHYREG_Pos (0) /*!< EMAC MIIMCTL: PHYREG Position */
<> 144:ef7eb2e8f9f7 13693 #define EMAC_MIIMCTL_PHYREG_Msk (0x1ful << EMAC_MIIMCTL_PHYREG_Pos) /*!< EMAC MIIMCTL: PHYREG Mask */
<> 144:ef7eb2e8f9f7 13694
<> 144:ef7eb2e8f9f7 13695 #define EMAC_MIIMCTL_PHYADDR_Pos (8) /*!< EMAC MIIMCTL: PHYADDR Position */
<> 144:ef7eb2e8f9f7 13696 #define EMAC_MIIMCTL_PHYADDR_Msk (0x1ful << EMAC_MIIMCTL_PHYADDR_Pos) /*!< EMAC MIIMCTL: PHYADDR Mask */
<> 144:ef7eb2e8f9f7 13697
<> 144:ef7eb2e8f9f7 13698 #define EMAC_MIIMCTL_WRITE_Pos (16) /*!< EMAC MIIMCTL: WRITE Position */
<> 144:ef7eb2e8f9f7 13699 #define EMAC_MIIMCTL_WRITE_Msk (0x1ul << EMAC_MIIMCTL_WRITE_Pos) /*!< EMAC MIIMCTL: WRITE Mask */
<> 144:ef7eb2e8f9f7 13700
<> 144:ef7eb2e8f9f7 13701 #define EMAC_MIIMCTL_BUSY_Pos (17) /*!< EMAC MIIMCTL: BUSY Position */
<> 144:ef7eb2e8f9f7 13702 #define EMAC_MIIMCTL_BUSY_Msk (0x1ul << EMAC_MIIMCTL_BUSY_Pos) /*!< EMAC MIIMCTL: BUSY Mask */
<> 144:ef7eb2e8f9f7 13703
<> 144:ef7eb2e8f9f7 13704 #define EMAC_MIIMCTL_PREAMSP_Pos (18) /*!< EMAC MIIMCTL: PREAMSP Position */
<> 144:ef7eb2e8f9f7 13705 #define EMAC_MIIMCTL_PREAMSP_Msk (0x1ul << EMAC_MIIMCTL_PREAMSP_Pos) /*!< EMAC MIIMCTL: PREAMSP Mask */
<> 144:ef7eb2e8f9f7 13706
<> 144:ef7eb2e8f9f7 13707 #define EMAC_MIIMCTL_MDCON_Pos (19) /*!< EMAC MIIMCTL: MDCON Position */
<> 144:ef7eb2e8f9f7 13708 #define EMAC_MIIMCTL_MDCON_Msk (0x1ul << EMAC_MIIMCTL_MDCON_Pos) /*!< EMAC MIIMCTL: MDCON Mask */
<> 144:ef7eb2e8f9f7 13709
<> 144:ef7eb2e8f9f7 13710 #define EMAC_FIFOCTL_RXFIFOTH_Pos (0) /*!< EMAC FIFOCTL: RXFIFOTH Position */
<> 144:ef7eb2e8f9f7 13711 #define EMAC_FIFOCTL_RXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_RXFIFOTH_Pos) /*!< EMAC FIFOCTL: RXFIFOTH Mask */
<> 144:ef7eb2e8f9f7 13712
<> 144:ef7eb2e8f9f7 13713 #define EMAC_FIFOCTL_TXFIFOTH_Pos (8) /*!< EMAC FIFOCTL: TXFIFOTH Position */
<> 144:ef7eb2e8f9f7 13714 #define EMAC_FIFOCTL_TXFIFOTH_Msk (0x3ul << EMAC_FIFOCTL_TXFIFOTH_Pos) /*!< EMAC FIFOCTL: TXFIFOTH Mask */
<> 144:ef7eb2e8f9f7 13715
<> 144:ef7eb2e8f9f7 13716 #define EMAC_FIFOCTL_BURSTLEN_Pos (20) /*!< EMAC FIFOCTL: BURSTLEN Position */
<> 144:ef7eb2e8f9f7 13717 #define EMAC_FIFOCTL_BURSTLEN_Msk (0x3ul << EMAC_FIFOCTL_BURSTLEN_Pos) /*!< EMAC FIFOCTL: BURSTLEN Mask */
<> 144:ef7eb2e8f9f7 13718
<> 144:ef7eb2e8f9f7 13719 #define EMAC_TXST_TXST_Pos (0) /*!< EMAC TXST: TXST Position */
<> 144:ef7eb2e8f9f7 13720 #define EMAC_TXST_TXST_Msk (0xfffffffful << EMAC_TXST_TXST_Pos) /*!< EMAC TXST: TXST Mask */
<> 144:ef7eb2e8f9f7 13721
<> 144:ef7eb2e8f9f7 13722 #define EMAC_RXST_RXST_Pos (0) /*!< EMAC RXST: RXST Position */
<> 144:ef7eb2e8f9f7 13723 #define EMAC_RXST_RXST_Msk (0xfffffffful << EMAC_RXST_RXST_Pos) /*!< EMAC RXST: RXST Mask */
<> 144:ef7eb2e8f9f7 13724
<> 144:ef7eb2e8f9f7 13725 #define EMAC_MRFL_MRFL_Pos (0) /*!< EMAC MRFL: MRFL Position */
<> 144:ef7eb2e8f9f7 13726 #define EMAC_MRFL_MRFL_Msk (0xfffful << EMAC_MRFL_MRFL_Pos) /*!< EMAC MRFL: MRFL Mask */
<> 144:ef7eb2e8f9f7 13727
<> 144:ef7eb2e8f9f7 13728 #define EMAC_INTEN_RXIEN_Pos (0) /*!< EMAC INTEN: RXIEN Position */
<> 144:ef7eb2e8f9f7 13729 #define EMAC_INTEN_RXIEN_Msk (0x1ul << EMAC_INTEN_RXIEN_Pos) /*!< EMAC INTEN: RXIEN Mask */
<> 144:ef7eb2e8f9f7 13730
<> 144:ef7eb2e8f9f7 13731 #define EMAC_INTEN_CRCEIEN_Pos (1) /*!< EMAC INTEN: CRCEIEN Position */
<> 144:ef7eb2e8f9f7 13732 #define EMAC_INTEN_CRCEIEN_Msk (0x1ul << EMAC_INTEN_CRCEIEN_Pos) /*!< EMAC INTEN: CRCEIEN Mask */
<> 144:ef7eb2e8f9f7 13733
<> 144:ef7eb2e8f9f7 13734 #define EMAC_INTEN_RXOVIEN_Pos (2) /*!< EMAC INTEN: RXOVIEN Position */
<> 144:ef7eb2e8f9f7 13735 #define EMAC_INTEN_RXOVIEN_Msk (0x1ul << EMAC_INTEN_RXOVIEN_Pos) /*!< EMAC INTEN: RXOVIEN Mask */
<> 144:ef7eb2e8f9f7 13736
<> 144:ef7eb2e8f9f7 13737 #define EMAC_INTEN_LPIEN_Pos (3) /*!< EMAC INTEN: LPIEN Position */
<> 144:ef7eb2e8f9f7 13738 #define EMAC_INTEN_LPIEN_Msk (0x1ul << EMAC_INTEN_LPIEN_Pos) /*!< EMAC INTEN: LPIEN Mask */
<> 144:ef7eb2e8f9f7 13739
<> 144:ef7eb2e8f9f7 13740 #define EMAC_INTEN_RXGDIEN_Pos (4) /*!< EMAC INTEN: RXGDIEN Position */
<> 144:ef7eb2e8f9f7 13741 #define EMAC_INTEN_RXGDIEN_Msk (0x1ul << EMAC_INTEN_RXGDIEN_Pos) /*!< EMAC INTEN: RXGDIEN Mask */
<> 144:ef7eb2e8f9f7 13742
<> 144:ef7eb2e8f9f7 13743 #define EMAC_INTEN_ALIEIEN_Pos (5) /*!< EMAC INTEN: ALIEIEN Position */
<> 144:ef7eb2e8f9f7 13744 #define EMAC_INTEN_ALIEIEN_Msk (0x1ul << EMAC_INTEN_ALIEIEN_Pos) /*!< EMAC INTEN: ALIEIEN Mask */
<> 144:ef7eb2e8f9f7 13745
<> 144:ef7eb2e8f9f7 13746 #define EMAC_INTEN_RPIEN_Pos (6) /*!< EMAC INTEN: RPIEN Position */
<> 144:ef7eb2e8f9f7 13747 #define EMAC_INTEN_RPIEN_Msk (0x1ul << EMAC_INTEN_RPIEN_Pos) /*!< EMAC INTEN: RPIEN Mask */
<> 144:ef7eb2e8f9f7 13748
<> 144:ef7eb2e8f9f7 13749 #define EMAC_INTEN_MPCOVIEN_Pos (7) /*!< EMAC INTEN: MPCOVIEN Position */
<> 144:ef7eb2e8f9f7 13750 #define EMAC_INTEN_MPCOVIEN_Msk (0x1ul << EMAC_INTEN_MPCOVIEN_Pos) /*!< EMAC INTEN: MPCOVIEN Mask */
<> 144:ef7eb2e8f9f7 13751
<> 144:ef7eb2e8f9f7 13752 #define EMAC_INTEN_MFLEIEN_Pos (8) /*!< EMAC INTEN: MFLEIEN Position */
<> 144:ef7eb2e8f9f7 13753 #define EMAC_INTEN_MFLEIEN_Msk (0x1ul << EMAC_INTEN_MFLEIEN_Pos) /*!< EMAC INTEN: MFLEIEN Mask */
<> 144:ef7eb2e8f9f7 13754
<> 144:ef7eb2e8f9f7 13755 #define EMAC_INTEN_DENIEN_Pos (9) /*!< EMAC INTEN: DENIEN Position */
<> 144:ef7eb2e8f9f7 13756 #define EMAC_INTEN_DENIEN_Msk (0x1ul << EMAC_INTEN_DENIEN_Pos) /*!< EMAC INTEN: DENIEN Mask */
<> 144:ef7eb2e8f9f7 13757
<> 144:ef7eb2e8f9f7 13758 #define EMAC_INTEN_RDUIEN_Pos (10) /*!< EMAC INTEN: RDUIEN Position */
<> 144:ef7eb2e8f9f7 13759 #define EMAC_INTEN_RDUIEN_Msk (0x1ul << EMAC_INTEN_RDUIEN_Pos) /*!< EMAC INTEN: RDUIEN Mask */
<> 144:ef7eb2e8f9f7 13760
<> 144:ef7eb2e8f9f7 13761 #define EMAC_INTEN_RXBEIEN_Pos (11) /*!< EMAC INTEN: RXBEIEN Position */
<> 144:ef7eb2e8f9f7 13762 #define EMAC_INTEN_RXBEIEN_Msk (0x1ul << EMAC_INTEN_RXBEIEN_Pos) /*!< EMAC INTEN: RXBEIEN Mask */
<> 144:ef7eb2e8f9f7 13763
<> 144:ef7eb2e8f9f7 13764 #define EMAC_INTEN_CFRIEN_Pos (14) /*!< EMAC INTEN: CFRIEN Position */
<> 144:ef7eb2e8f9f7 13765 #define EMAC_INTEN_CFRIEN_Msk (0x1ul << EMAC_INTEN_CFRIEN_Pos) /*!< EMAC INTEN: CFRIEN Mask */
<> 144:ef7eb2e8f9f7 13766
<> 144:ef7eb2e8f9f7 13767 #define EMAC_INTEN_WOLIEN_Pos (15) /*!< EMAC INTEN: WOLIEN Position */
<> 144:ef7eb2e8f9f7 13768 #define EMAC_INTEN_WOLIEN_Msk (0x1ul << EMAC_INTEN_WOLIEN_Pos) /*!< EMAC INTEN: WOLIEN Mask */
<> 144:ef7eb2e8f9f7 13769
<> 144:ef7eb2e8f9f7 13770 #define EMAC_INTEN_TXIEN_Pos (16) /*!< EMAC INTEN: TXIEN Position */
<> 144:ef7eb2e8f9f7 13771 #define EMAC_INTEN_TXIEN_Msk (0x1ul << EMAC_INTEN_TXIEN_Pos) /*!< EMAC INTEN: TXIEN Mask */
<> 144:ef7eb2e8f9f7 13772
<> 144:ef7eb2e8f9f7 13773 #define EMAC_INTEN_TXUDIEN_Pos (17) /*!< EMAC INTEN: TXUDIEN Position */
<> 144:ef7eb2e8f9f7 13774 #define EMAC_INTEN_TXUDIEN_Msk (0x1ul << EMAC_INTEN_TXUDIEN_Pos) /*!< EMAC INTEN: TXUDIEN Mask */
<> 144:ef7eb2e8f9f7 13775
<> 144:ef7eb2e8f9f7 13776 #define EMAC_INTEN_TXCPIEN_Pos (18) /*!< EMAC INTEN: TXCPIEN Position */
<> 144:ef7eb2e8f9f7 13777 #define EMAC_INTEN_TXCPIEN_Msk (0x1ul << EMAC_INTEN_TXCPIEN_Pos) /*!< EMAC INTEN: TXCPIEN Mask */
<> 144:ef7eb2e8f9f7 13778
<> 144:ef7eb2e8f9f7 13779 #define EMAC_INTEN_EXDEFIEN_Pos (19) /*!< EMAC INTEN: EXDEFIEN Position */
<> 144:ef7eb2e8f9f7 13780 #define EMAC_INTEN_EXDEFIEN_Msk (0x1ul << EMAC_INTEN_EXDEFIEN_Pos) /*!< EMAC INTEN: EXDEFIEN Mask */
<> 144:ef7eb2e8f9f7 13781
<> 144:ef7eb2e8f9f7 13782 #define EMAC_INTEN_NCSIEN_Pos (20) /*!< EMAC INTEN: NCSIEN Position */
<> 144:ef7eb2e8f9f7 13783 #define EMAC_INTEN_NCSIEN_Msk (0x1ul << EMAC_INTEN_NCSIEN_Pos) /*!< EMAC INTEN: NCSIEN Mask */
<> 144:ef7eb2e8f9f7 13784
<> 144:ef7eb2e8f9f7 13785 #define EMAC_INTEN_TXABTIEN_Pos (21) /*!< EMAC INTEN: TXABTIEN Position */
<> 144:ef7eb2e8f9f7 13786 #define EMAC_INTEN_TXABTIEN_Msk (0x1ul << EMAC_INTEN_TXABTIEN_Pos) /*!< EMAC INTEN: TXABTIEN Mask */
<> 144:ef7eb2e8f9f7 13787
<> 144:ef7eb2e8f9f7 13788 #define EMAC_INTEN_LCIEN_Pos (22) /*!< EMAC INTEN: LCIEN Position */
<> 144:ef7eb2e8f9f7 13789 #define EMAC_INTEN_LCIEN_Msk (0x1ul << EMAC_INTEN_LCIEN_Pos) /*!< EMAC INTEN: LCIEN Mask */
<> 144:ef7eb2e8f9f7 13790
<> 144:ef7eb2e8f9f7 13791 #define EMAC_INTEN_TDUIEN_Pos (23) /*!< EMAC INTEN: TDUIEN Position */
<> 144:ef7eb2e8f9f7 13792 #define EMAC_INTEN_TDUIEN_Msk (0x1ul << EMAC_INTEN_TDUIEN_Pos) /*!< EMAC INTEN: TDUIEN Mask */
<> 144:ef7eb2e8f9f7 13793
<> 144:ef7eb2e8f9f7 13794 #define EMAC_INTEN_TXBEIEN_Pos (24) /*!< EMAC INTEN: TXBEIEN Position */
<> 144:ef7eb2e8f9f7 13795 #define EMAC_INTEN_TXBEIEN_Msk (0x1ul << EMAC_INTEN_TXBEIEN_Pos) /*!< EMAC INTEN: TXBEIEN Mask */
<> 144:ef7eb2e8f9f7 13796
<> 144:ef7eb2e8f9f7 13797 #define EMAC_INTEN_TSALMIEN_Pos (28) /*!< EMAC INTEN: TSALMIEN Position */
<> 144:ef7eb2e8f9f7 13798 #define EMAC_INTEN_TSALMIEN_Msk (0x1ul << EMAC_INTEN_TSALMIEN_Pos) /*!< EMAC INTEN: TSALMIEN Mask */
<> 144:ef7eb2e8f9f7 13799
<> 144:ef7eb2e8f9f7 13800 #define EMAC_INTSTS_RXIF_Pos (0) /*!< EMAC INTSTS: RXIF Position */
<> 144:ef7eb2e8f9f7 13801 #define EMAC_INTSTS_RXIF_Msk (0x1ul << EMAC_INTSTS_RXIF_Pos) /*!< EMAC INTSTS: RXIF Mask */
<> 144:ef7eb2e8f9f7 13802
<> 144:ef7eb2e8f9f7 13803 #define EMAC_INTSTS_CRCEIF_Pos (1) /*!< EMAC INTSTS: CRCEIF Position */
<> 144:ef7eb2e8f9f7 13804 #define EMAC_INTSTS_CRCEIF_Msk (0x1ul << EMAC_INTSTS_CRCEIF_Pos) /*!< EMAC INTSTS: CRCEIF Mask */
<> 144:ef7eb2e8f9f7 13805
<> 144:ef7eb2e8f9f7 13806 #define EMAC_INTSTS_RXOVIF_Pos (2) /*!< EMAC INTSTS: RXOVIF Position */
<> 144:ef7eb2e8f9f7 13807 #define EMAC_INTSTS_RXOVIF_Msk (0x1ul << EMAC_INTSTS_RXOVIF_Pos) /*!< EMAC INTSTS: RXOVIF Mask */
<> 144:ef7eb2e8f9f7 13808
<> 144:ef7eb2e8f9f7 13809 #define EMAC_INTSTS_LPIF_Pos (3) /*!< EMAC INTSTS: LPIF Position */
<> 144:ef7eb2e8f9f7 13810 #define EMAC_INTSTS_LPIF_Msk (0x1ul << EMAC_INTSTS_LPIF_Pos) /*!< EMAC INTSTS: LPIF Mask */
<> 144:ef7eb2e8f9f7 13811
<> 144:ef7eb2e8f9f7 13812 #define EMAC_INTSTS_RXGDIF_Pos (4) /*!< EMAC INTSTS: RXGDIF Position */
<> 144:ef7eb2e8f9f7 13813 #define EMAC_INTSTS_RXGDIF_Msk (0x1ul << EMAC_INTSTS_RXGDIF_Pos) /*!< EMAC INTSTS: RXGDIF Mask */
<> 144:ef7eb2e8f9f7 13814
<> 144:ef7eb2e8f9f7 13815 #define EMAC_INTSTS_ALIEIF_Pos (5) /*!< EMAC INTSTS: ALIEIF Position */
<> 144:ef7eb2e8f9f7 13816 #define EMAC_INTSTS_ALIEIF_Msk (0x1ul << EMAC_INTSTS_ALIEIF_Pos) /*!< EMAC INTSTS: ALIEIF Mask */
<> 144:ef7eb2e8f9f7 13817
<> 144:ef7eb2e8f9f7 13818 #define EMAC_INTSTS_RPIF_Pos (6) /*!< EMAC INTSTS: RPIF Position */
<> 144:ef7eb2e8f9f7 13819 #define EMAC_INTSTS_RPIF_Msk (0x1ul << EMAC_INTSTS_RPIF_Pos) /*!< EMAC INTSTS: RPIF Mask */
<> 144:ef7eb2e8f9f7 13820
<> 144:ef7eb2e8f9f7 13821 #define EMAC_INTSTS_MPCOVIF_Pos (7) /*!< EMAC INTSTS: MPCOVIF Position */
<> 144:ef7eb2e8f9f7 13822 #define EMAC_INTSTS_MPCOVIF_Msk (0x1ul << EMAC_INTSTS_MPCOVIF_Pos) /*!< EMAC INTSTS: MPCOVIF Mask */
<> 144:ef7eb2e8f9f7 13823
<> 144:ef7eb2e8f9f7 13824 #define EMAC_INTSTS_MFLEIF_Pos (8) /*!< EMAC INTSTS: MFLEIF Position */
<> 144:ef7eb2e8f9f7 13825 #define EMAC_INTSTS_MFLEIF_Msk (0x1ul << EMAC_INTSTS_MFLEIF_Pos) /*!< EMAC INTSTS: MFLEIF Mask */
<> 144:ef7eb2e8f9f7 13826
<> 144:ef7eb2e8f9f7 13827 #define EMAC_INTSTS_DENIF_Pos (9) /*!< EMAC INTSTS: DENIF Position */
<> 144:ef7eb2e8f9f7 13828 #define EMAC_INTSTS_DENIF_Msk (0x1ul << EMAC_INTSTS_DENIF_Pos) /*!< EMAC INTSTS: DENIF Mask */
<> 144:ef7eb2e8f9f7 13829
<> 144:ef7eb2e8f9f7 13830 #define EMAC_INTSTS_RDUIF_Pos (10) /*!< EMAC INTSTS: RDUIF Position */
<> 144:ef7eb2e8f9f7 13831 #define EMAC_INTSTS_RDUIF_Msk (0x1ul << EMAC_INTSTS_RDUIF_Pos) /*!< EMAC INTSTS: RDUIF Mask */
<> 144:ef7eb2e8f9f7 13832
<> 144:ef7eb2e8f9f7 13833 #define EMAC_INTSTS_RXBEIF_Pos (11) /*!< EMAC INTSTS: RXBEIF Position */
<> 144:ef7eb2e8f9f7 13834 #define EMAC_INTSTS_RXBEIF_Msk (0x1ul << EMAC_INTSTS_RXBEIF_Pos) /*!< EMAC INTSTS: RXBEIF Mask */
<> 144:ef7eb2e8f9f7 13835
<> 144:ef7eb2e8f9f7 13836 #define EMAC_INTSTS_CFRIF_Pos (14) /*!< EMAC INTSTS: CFRIF Position */
<> 144:ef7eb2e8f9f7 13837 #define EMAC_INTSTS_CFRIF_Msk (0x1ul << EMAC_INTSTS_CFRIF_Pos) /*!< EMAC INTSTS: CFRIF Mask */
<> 144:ef7eb2e8f9f7 13838
<> 144:ef7eb2e8f9f7 13839 #define EMAC_INTSTS_WOLIF_Pos (15) /*!< EMAC INTSTS: WOLIF Position */
<> 144:ef7eb2e8f9f7 13840 #define EMAC_INTSTS_WOLIF_Msk (0x1ul << EMAC_INTSTS_WOLIF_Pos) /*!< EMAC INTSTS: WOLIF Mask */
<> 144:ef7eb2e8f9f7 13841
<> 144:ef7eb2e8f9f7 13842 #define EMAC_INTSTS_TXIF_Pos (16) /*!< EMAC INTSTS: TXIF Position */
<> 144:ef7eb2e8f9f7 13843 #define EMAC_INTSTS_TXIF_Msk (0x1ul << EMAC_INTSTS_TXIF_Pos) /*!< EMAC INTSTS: TXIF Mask */
<> 144:ef7eb2e8f9f7 13844
<> 144:ef7eb2e8f9f7 13845 #define EMAC_INTSTS_TXUDIF_Pos (17) /*!< EMAC INTSTS: TXUDIF Position */
<> 144:ef7eb2e8f9f7 13846 #define EMAC_INTSTS_TXUDIF_Msk (0x1ul << EMAC_INTSTS_TXUDIF_Pos) /*!< EMAC INTSTS: TXUDIF Mask */
<> 144:ef7eb2e8f9f7 13847
<> 144:ef7eb2e8f9f7 13848 #define EMAC_INTSTS_TXCPIF_Pos (18) /*!< EMAC INTSTS: TXCPIF Position */
<> 144:ef7eb2e8f9f7 13849 #define EMAC_INTSTS_TXCPIF_Msk (0x1ul << EMAC_INTSTS_TXCPIF_Pos) /*!< EMAC INTSTS: TXCPIF Mask */
<> 144:ef7eb2e8f9f7 13850
<> 144:ef7eb2e8f9f7 13851 #define EMAC_INTSTS_EXDEFIF_Pos (19) /*!< EMAC INTSTS: EXDEFIF Position */
<> 144:ef7eb2e8f9f7 13852 #define EMAC_INTSTS_EXDEFIF_Msk (0x1ul << EMAC_INTSTS_EXDEFIF_Pos) /*!< EMAC INTSTS: EXDEFIF Mask */
<> 144:ef7eb2e8f9f7 13853
<> 144:ef7eb2e8f9f7 13854 #define EMAC_INTSTS_NCSIF_Pos (20) /*!< EMAC INTSTS: NCSIF Position */
<> 144:ef7eb2e8f9f7 13855 #define EMAC_INTSTS_NCSIF_Msk (0x1ul << EMAC_INTSTS_NCSIF_Pos) /*!< EMAC INTSTS: NCSIF Mask */
<> 144:ef7eb2e8f9f7 13856
<> 144:ef7eb2e8f9f7 13857 #define EMAC_INTSTS_TXABTIF_Pos (21) /*!< EMAC INTSTS: TXABTIF Position */
<> 144:ef7eb2e8f9f7 13858 #define EMAC_INTSTS_TXABTIF_Msk (0x1ul << EMAC_INTSTS_TXABTIF_Pos) /*!< EMAC INTSTS: TXABTIF Mask */
<> 144:ef7eb2e8f9f7 13859
<> 144:ef7eb2e8f9f7 13860 #define EMAC_INTSTS_LCIF_Pos (22) /*!< EMAC INTSTS: LCIF Position */
<> 144:ef7eb2e8f9f7 13861 #define EMAC_INTSTS_LCIF_Msk (0x1ul << EMAC_INTSTS_LCIF_Pos) /*!< EMAC INTSTS: LCIF Mask */
<> 144:ef7eb2e8f9f7 13862
<> 144:ef7eb2e8f9f7 13863 #define EMAC_INTSTS_TDUIF_Pos (23) /*!< EMAC INTSTS: TDUIF Position */
<> 144:ef7eb2e8f9f7 13864 #define EMAC_INTSTS_TDUIF_Msk (0x1ul << EMAC_INTSTS_TDUIF_Pos) /*!< EMAC INTSTS: TDUIF Mask */
<> 144:ef7eb2e8f9f7 13865
<> 144:ef7eb2e8f9f7 13866 #define EMAC_INTSTS_TXBEIF_Pos (24) /*!< EMAC INTSTS: TXBEIF Position */
<> 144:ef7eb2e8f9f7 13867 #define EMAC_INTSTS_TXBEIF_Msk (0x1ul << EMAC_INTSTS_TXBEIF_Pos) /*!< EMAC INTSTS: TXBEIF Mask */
<> 144:ef7eb2e8f9f7 13868
<> 144:ef7eb2e8f9f7 13869 #define EMAC_INTSTS_TSALMIF_Pos (28) /*!< EMAC INTSTS: TSALMIF Position */
<> 144:ef7eb2e8f9f7 13870 #define EMAC_INTSTS_TSALMIF_Msk (0x1ul << EMAC_INTSTS_TSALMIF_Pos) /*!< EMAC INTSTS: TSALMIF Mask */
<> 144:ef7eb2e8f9f7 13871
<> 144:ef7eb2e8f9f7 13872 #define EMAC_GENSTS_CFRIF_Pos (0) /*!< EMAC GENSTS: CFRIF Position */
<> 144:ef7eb2e8f9f7 13873 #define EMAC_GENSTS_CFRIF_Msk (0x1ul << EMAC_GENSTS_CFRIF_Pos) /*!< EMAC GENSTS: CFRIF Mask */
<> 144:ef7eb2e8f9f7 13874
<> 144:ef7eb2e8f9f7 13875 #define EMAC_GENSTS_RXHALT_Pos (1) /*!< EMAC GENSTS: RXHALT Position */
<> 144:ef7eb2e8f9f7 13876 #define EMAC_GENSTS_RXHALT_Msk (0x1ul << EMAC_GENSTS_RXHALT_Pos) /*!< EMAC GENSTS: RXHALT Mask */
<> 144:ef7eb2e8f9f7 13877
<> 144:ef7eb2e8f9f7 13878 #define EMAC_GENSTS_RXFFULL_Pos (2) /*!< EMAC GENSTS: RXFFULL Position */
<> 144:ef7eb2e8f9f7 13879 #define EMAC_GENSTS_RXFFULL_Msk (0x1ul << EMAC_GENSTS_RXFFULL_Pos) /*!< EMAC GENSTS: RXFFULL Mask */
<> 144:ef7eb2e8f9f7 13880
<> 144:ef7eb2e8f9f7 13881 #define EMAC_GENSTS_COLCNT_Pos (4) /*!< EMAC GENSTS: COLCNT Position */
<> 144:ef7eb2e8f9f7 13882 #define EMAC_GENSTS_COLCNT_Msk (0xful << EMAC_GENSTS_COLCNT_Pos) /*!< EMAC GENSTS: COLCNT Mask */
<> 144:ef7eb2e8f9f7 13883
<> 144:ef7eb2e8f9f7 13884 #define EMAC_GENSTS_DEF_Pos (8) /*!< EMAC GENSTS: DEF Position */
<> 144:ef7eb2e8f9f7 13885 #define EMAC_GENSTS_DEF_Msk (0x1ul << EMAC_GENSTS_DEF_Pos) /*!< EMAC GENSTS: DEF Mask */
<> 144:ef7eb2e8f9f7 13886
<> 144:ef7eb2e8f9f7 13887 #define EMAC_GENSTS_TXPAUSED_Pos (9) /*!< EMAC GENSTS: TXPAUSED Position */
<> 144:ef7eb2e8f9f7 13888 #define EMAC_GENSTS_TXPAUSED_Msk (0x1ul << EMAC_GENSTS_TXPAUSED_Pos) /*!< EMAC GENSTS: TXPAUSED Mask */
<> 144:ef7eb2e8f9f7 13889
<> 144:ef7eb2e8f9f7 13890 #define EMAC_GENSTS_SQE_Pos (10) /*!< EMAC GENSTS: SQE Position */
<> 144:ef7eb2e8f9f7 13891 #define EMAC_GENSTS_SQE_Msk (0x1ul << EMAC_GENSTS_SQE_Pos) /*!< EMAC GENSTS: SQE Mask */
<> 144:ef7eb2e8f9f7 13892
<> 144:ef7eb2e8f9f7 13893 #define EMAC_GENSTS_TXHALT_Pos (11) /*!< EMAC GENSTS: TXHALT Position */
<> 144:ef7eb2e8f9f7 13894 #define EMAC_GENSTS_TXHALT_Msk (0x1ul << EMAC_GENSTS_TXHALT_Pos) /*!< EMAC GENSTS: TXHALT Mask */
<> 144:ef7eb2e8f9f7 13895
<> 144:ef7eb2e8f9f7 13896 #define EMAC_GENSTS_RPSTS_Pos (12) /*!< EMAC GENSTS: RPSTS Position */
<> 144:ef7eb2e8f9f7 13897 #define EMAC_GENSTS_RPSTS_Msk (0x1ul << EMAC_GENSTS_RPSTS_Pos) /*!< EMAC GENSTS: RPSTS Mask */
<> 144:ef7eb2e8f9f7 13898
<> 144:ef7eb2e8f9f7 13899 #define EMAC_MPCNT_MPCNT_Pos (0) /*!< EMAC MPCNT: MPCNT Position */
<> 144:ef7eb2e8f9f7 13900 #define EMAC_MPCNT_MPCNT_Msk (0xfffful << EMAC_MPCNT_MPCNT_Pos) /*!< EMAC MPCNT: MPCNT Mask */
<> 144:ef7eb2e8f9f7 13901
<> 144:ef7eb2e8f9f7 13902 #define EMAC_RPCNT_RPCNT_Pos (0) /*!< EMAC RPCNT: RPCNT Position */
<> 144:ef7eb2e8f9f7 13903 #define EMAC_RPCNT_RPCNT_Msk (0xfffful << EMAC_RPCNT_RPCNT_Pos) /*!< EMAC RPCNT: RPCNT Mask */
<> 144:ef7eb2e8f9f7 13904
<> 144:ef7eb2e8f9f7 13905 #define EMAC_FRSTS_RXFLT_Pos (0) /*!< EMAC FRSTS: RXFLT Position */
<> 144:ef7eb2e8f9f7 13906 #define EMAC_FRSTS_RXFLT_Msk (0xfffful << EMAC_FRSTS_RXFLT_Pos) /*!< EMAC FRSTS: RXFLT Mask */
<> 144:ef7eb2e8f9f7 13907
<> 144:ef7eb2e8f9f7 13908 #define EMAC_CTXDSA_CTXDSA_Pos (0) /*!< EMAC CTXDSA: CTXDSA Position */
<> 144:ef7eb2e8f9f7 13909 #define EMAC_CTXDSA_CTXDSA_Msk (0xfffffffful << EMAC_CTXDSA_CTXDSA_Pos) /*!< EMAC CTXDSA: CTXDSA Mask */
<> 144:ef7eb2e8f9f7 13910
<> 144:ef7eb2e8f9f7 13911 #define EMAC_CTXBSA_CTXBSA_Pos (0) /*!< EMAC CTXBSA: CTXBSA Position */
<> 144:ef7eb2e8f9f7 13912 #define EMAC_CTXBSA_CTXBSA_Msk (0xfffffffful << EMAC_CTXBSA_CTXBSA_Pos) /*!< EMAC CTXBSA: CTXBSA Mask */
<> 144:ef7eb2e8f9f7 13913
<> 144:ef7eb2e8f9f7 13914 #define EMAC_CRXDSA_CRXDSA_Pos (0) /*!< EMAC CRXDSA: CRXDSA Position */
<> 144:ef7eb2e8f9f7 13915 #define EMAC_CRXDSA_CRXDSA_Msk (0xfffffffful << EMAC_CRXDSA_CRXDSA_Pos) /*!< EMAC CRXDSA: CRXDSA Mask */
<> 144:ef7eb2e8f9f7 13916
<> 144:ef7eb2e8f9f7 13917 #define EMAC_CRXBSA_CRXBSA_Pos (0) /*!< EMAC CRXBSA: CRXBSA Position */
<> 144:ef7eb2e8f9f7 13918 #define EMAC_CRXBSA_CRXBSA_Msk (0xfffffffful << EMAC_CRXBSA_CRXBSA_Pos) /*!< EMAC CRXBSA: CRXBSA Mask */
<> 144:ef7eb2e8f9f7 13919
<> 144:ef7eb2e8f9f7 13920 #define EMAC_TSCTL_TSEN_Pos (0) /*!< EMAC TSCTL: TSEN Position */
<> 144:ef7eb2e8f9f7 13921 #define EMAC_TSCTL_TSEN_Msk (0x1ul << EMAC_TSCTL_TSEN_Pos) /*!< EMAC TSCTL: TSEN Mask */
<> 144:ef7eb2e8f9f7 13922
<> 144:ef7eb2e8f9f7 13923 #define EMAC_TSCTL_TSIEN_Pos (1) /*!< EMAC TSCTL: TSIEN Position */
<> 144:ef7eb2e8f9f7 13924 #define EMAC_TSCTL_TSIEN_Msk (0x1ul << EMAC_TSCTL_TSIEN_Pos) /*!< EMAC TSCTL: TSIEN Mask */
<> 144:ef7eb2e8f9f7 13925
<> 144:ef7eb2e8f9f7 13926 #define EMAC_TSCTL_TSMODE_Pos (2) /*!< EMAC TSCTL: TSMODE Position */
<> 144:ef7eb2e8f9f7 13927 #define EMAC_TSCTL_TSMODE_Msk (0x1ul << EMAC_TSCTL_TSMODE_Pos) /*!< EMAC TSCTL: TSMODE Mask */
<> 144:ef7eb2e8f9f7 13928
<> 144:ef7eb2e8f9f7 13929 #define EMAC_TSCTL_TSUPDATE_Pos (3) /*!< EMAC TSCTL: TSUPDATE Position */
<> 144:ef7eb2e8f9f7 13930 #define EMAC_TSCTL_TSUPDATE_Msk (0x1ul << EMAC_TSCTL_TSUPDATE_Pos) /*!< EMAC TSCTL: TSUPDATE Mask */
<> 144:ef7eb2e8f9f7 13931
<> 144:ef7eb2e8f9f7 13932 #define EMAC_TSCTL_TSALMEN_Pos (5) /*!< EMAC TSCTL: TSALMEN Position */
<> 144:ef7eb2e8f9f7 13933 #define EMAC_TSCTL_TSALMEN_Msk (0x1ul << EMAC_TSCTL_TSALMEN_Pos) /*!< EMAC TSCTL: TSALMEN Mask */
<> 144:ef7eb2e8f9f7 13934
<> 144:ef7eb2e8f9f7 13935 #define EMAC_TSSEC_SEC_Pos (0) /*!< EMAC TSSEC: SEC Position */
<> 144:ef7eb2e8f9f7 13936 #define EMAC_TSSEC_SEC_Msk (0xfffffffful << EMAC_TSSEC_SEC_Pos) /*!< EMAC TSSEC: SEC Mask */
<> 144:ef7eb2e8f9f7 13937
<> 144:ef7eb2e8f9f7 13938 #define EMAC_TSSUBSEC_SUBSEC_Pos (0) /*!< EMAC TSSUBSEC: SUBSEC Position */
<> 144:ef7eb2e8f9f7 13939 #define EMAC_TSSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_TSSUBSEC_SUBSEC_Pos) /*!< EMAC TSSUBSEC: SUBSEC Mask */
<> 144:ef7eb2e8f9f7 13940
<> 144:ef7eb2e8f9f7 13941 #define EMAC_TSINC_CNTINC_Pos (0) /*!< EMAC TSINC: CNTINC Position */
<> 144:ef7eb2e8f9f7 13942 #define EMAC_TSINC_CNTINC_Msk (0xfful << EMAC_TSINC_CNTINC_Pos) /*!< EMAC TSINC: CNTINC Mask */
<> 144:ef7eb2e8f9f7 13943
<> 144:ef7eb2e8f9f7 13944 #define EMAC_TSADDEND_ADDEND_Pos (0) /*!< EMAC TSADDEND: ADDEND Position */
<> 144:ef7eb2e8f9f7 13945 #define EMAC_TSADDEND_ADDEND_Msk (0xfffffffful << EMAC_TSADDEND_ADDEND_Pos) /*!< EMAC TSADDEND: ADDEND Mask */
<> 144:ef7eb2e8f9f7 13946
<> 144:ef7eb2e8f9f7 13947 #define EMAC_UPDSEC_SEC_Pos (0) /*!< EMAC UPDSEC: SEC Position */
<> 144:ef7eb2e8f9f7 13948 #define EMAC_UPDSEC_SEC_Msk (0xfffffffful << EMAC_UPDSEC_SEC_Pos) /*!< EMAC UPDSEC: SEC Mask */
<> 144:ef7eb2e8f9f7 13949
<> 144:ef7eb2e8f9f7 13950 #define EMAC_UPDSUBSEC_SUBSEC_Pos (0) /*!< EMAC UPDSUBSEC: SUBSEC Position */
<> 144:ef7eb2e8f9f7 13951 #define EMAC_UPDSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_UPDSUBSEC_SUBSEC_Pos) /*!< EMAC UPDSUBSEC: SUBSEC Mask */
<> 144:ef7eb2e8f9f7 13952
<> 144:ef7eb2e8f9f7 13953 #define EMAC_ALMSEC_SEC_Pos (0) /*!< EMAC ALMSEC: SEC Position */
<> 144:ef7eb2e8f9f7 13954 #define EMAC_ALMSEC_SEC_Msk (0xfffffffful << EMAC_ALMSEC_SEC_Pos) /*!< EMAC ALMSEC: SEC Mask */
<> 144:ef7eb2e8f9f7 13955
<> 144:ef7eb2e8f9f7 13956 #define EMAC_ALMSUBSEC_SUBSEC_Pos (0) /*!< EMAC ALMSUBSEC: SUBSEC Position */
<> 144:ef7eb2e8f9f7 13957 #define EMAC_ALMSUBSEC_SUBSEC_Msk (0xfffffffful << EMAC_ALMSUBSEC_SUBSEC_Pos) /*!< EMAC ALMSUBSEC: SUBSEC Mask */
<> 144:ef7eb2e8f9f7 13958
<> 144:ef7eb2e8f9f7 13959 /**@}*/ /* EMAC_CONST */
<> 144:ef7eb2e8f9f7 13960 /**@}*/ /* end of EMAC register group */
<> 144:ef7eb2e8f9f7 13961
<> 144:ef7eb2e8f9f7 13962
<> 144:ef7eb2e8f9f7 13963 /*---------------------- Enhanced PWM Generator -------------------------*/
<> 144:ef7eb2e8f9f7 13964 /**
<> 144:ef7eb2e8f9f7 13965 @addtogroup EPWM Enhanced PWM Generator(EPWM)
<> 144:ef7eb2e8f9f7 13966 Memory Mapped Structure for EPWM Controller
<> 144:ef7eb2e8f9f7 13967 @{ */
<> 144:ef7eb2e8f9f7 13968
<> 144:ef7eb2e8f9f7 13969 typedef struct {
<> 144:ef7eb2e8f9f7 13970
<> 144:ef7eb2e8f9f7 13971
<> 144:ef7eb2e8f9f7 13972 /**
<> 144:ef7eb2e8f9f7 13973 * CTL
<> 144:ef7eb2e8f9f7 13974 * ===================================================================================================
<> 144:ef7eb2e8f9f7 13975 * Offset: 0x00 PWM Control Register
<> 144:ef7eb2e8f9f7 13976 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 13977 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 13978 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 13979 * |[0:1] |MODE |PWM Mode Selection
<> 144:ef7eb2e8f9f7 13980 * | | |00 = Independent mode.
<> 144:ef7eb2e8f9f7 13981 * | | |01 = Pair/Complementary mode.
<> 144:ef7eb2e8f9f7 13982 * | | |10 = Synchronized mode.
<> 144:ef7eb2e8f9f7 13983 * | | |11 = Reserved.
<> 144:ef7eb2e8f9f7 13984 * |[2:3] |CLKDIV |PWM Clock Pre-Divider Selection
<> 144:ef7eb2e8f9f7 13985 * | | |00 = PWM clock = EPWMx_CLK.
<> 144:ef7eb2e8f9f7 13986 * | | |01 = PWM clock = EPWMx_CLK/2.
<> 144:ef7eb2e8f9f7 13987 * | | |10 = PWM clock = EPWMx_CLK/4.
<> 144:ef7eb2e8f9f7 13988 * | | |11 = PWM clock = EPWMx_CLK/16.
<> 144:ef7eb2e8f9f7 13989 * |[4] |PWMIEN |PWM Interrupt Enable Control
<> 144:ef7eb2e8f9f7 13990 * | | |0 = Disabling flag PIF to trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 13991 * | | |1 = Enabling flag PIF can trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 13992 * |[5] |BRKIEN |Brake0 And Brak1 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 13993 * | | |0 = Disabling flags BFK0 and BFK1 to trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 13994 * | | |1 = Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 13995 * |[6] |LOAD |Re-Load PWM Period Registers (EPWM_PERIOD) And PWM Duty Registers (PWM0~3) Control
<> 144:ef7eb2e8f9f7 13996 * | | |0 = No action if written with 0.
<> 144:ef7eb2e8f9f7 13997 * | | |The value of PWM period register (EPWM_PERIOD) and PWM duty registers (PWMn_CH0~PWMn_CH3) are not loaded to PWM counter and Comparator registers.
<> 144:ef7eb2e8f9f7 13998 * | | |1 = Hardware will update the value of PWM period register (EPWM_PERIOD) and PWM duty registers (PWMn_CH0~PWMn_CH3) to PWM Counter and Comparator register at the time of PWM Counter matches PERIOD in edge and central aligned modes or at the time of PWM Counter down counts with underflow in central aligned mode.
<> 144:ef7eb2e8f9f7 13999 * | | |Note1: n=0-1 for PWM unit0-1.
<> 144:ef7eb2e8f9f7 14000 * | | |Note2: This bit is software write, hardware clear and always read zero.
<> 144:ef7eb2e8f9f7 14001 * |[7] |CNTEN |Start CNTEN Control
<> 144:ef7eb2e8f9f7 14002 * | | |0 = The PWM stops running.
<> 144:ef7eb2e8f9f7 14003 * | | |1 = The PWM counter starts running.
<> 144:ef7eb2e8f9f7 14004 * |[8] |INTTYPE |PWM Interrupt Type Selection
<> 144:ef7eb2e8f9f7 14005 * | | |0 = PIF will be set if PWM counter underflow.
<> 144:ef7eb2e8f9f7 14006 * | | |1 = PIF will be set if PWM counter matches EPWM_PERIOD register.
<> 144:ef7eb2e8f9f7 14007 * | | |Note: This bit is effective when PWM in central align mode only.
<> 144:ef7eb2e8f9f7 14008 * |[9] |PINV |Inverse PWM Comparator Output
<> 144:ef7eb2e8f9f7 14009 * | | |When PINV is set to high the PWM comparator output signals will be inversed, therefore the PWM Duty (in percentage) is changed to (1-Duty) before PINV is set to high.
<> 144:ef7eb2e8f9f7 14010 * | | |0 = Not inverse PWM comparator output.
<> 144:ef7eb2e8f9f7 14011 * | | |1 = Inverse PWM comparator output.
<> 144:ef7eb2e8f9f7 14012 * |[11] |CNTCLR |Clear PWM Counter Control
<> 144:ef7eb2e8f9f7 14013 * | | |1 = Clear 16-bit PWM counter to 000H.
<> 144:ef7eb2e8f9f7 14014 * | | |Note: It is automatically cleared by hardware.
<> 144:ef7eb2e8f9f7 14015 * |[12] |CNTTYPE |PWM Aligned Type Selection
<> 144:ef7eb2e8f9f7 14016 * | | |0 = Edge-aligned type.
<> 144:ef7eb2e8f9f7 14017 * | | |1 = Centre-aligned type.
<> 144:ef7eb2e8f9f7 14018 * |[13] |GROUPEN |Group Bit
<> 144:ef7eb2e8f9f7 14019 * | | |0 = The signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 are independent.
<> 144:ef7eb2e8f9f7 14020 * | | |1 = Unify the signals timing of EPWM_CMPDAT0, EPWM_CMPDAT2 and EPWM_CMPDAT4 in the same phase which is controlled by EPWM_CMPDAT0.
<> 144:ef7eb2e8f9f7 14021 * |[14] |BRKP0INV |Inverse BKP0 State
<> 144:ef7eb2e8f9f7 14022 * | | |0 = The state of pin BKPx0 is passed to the negative edge detector.
<> 144:ef7eb2e8f9f7 14023 * | | |1 = The inversed state of pin BKPx0 is passed to the negative edge detector.
<> 144:ef7eb2e8f9f7 14024 * |[15] |BRKP1INV |Inverse BKP1 State
<> 144:ef7eb2e8f9f7 14025 * | | |0 = The state of pin BKPx1 is passed to the negative edge detector.
<> 144:ef7eb2e8f9f7 14026 * | | |1 = The inversed state of pin BKPx1 is passed to the negative edge detector.
<> 144:ef7eb2e8f9f7 14027 * |[16] |BRKP0EN |BKPx0 Pin Trigger Brake Function0 Enable Control
<> 144:ef7eb2e8f9f7 14028 * | | |0 = PWMx Brake Function 0 Disabled.
<> 144:ef7eb2e8f9f7 14029 * | | |1 = PWMx Brake Function 0 Enabled.
<> 144:ef7eb2e8f9f7 14030 * | | |Note: x=0~1 for PWM unit0~1.
<> 144:ef7eb2e8f9f7 14031 * |[17] |BRKP1EN |BKPx1 Pin Trigger Brake Function Enable Control
<> 144:ef7eb2e8f9f7 14032 * | | |0 = PWMx Brake Function 1 Disabled.
<> 144:ef7eb2e8f9f7 14033 * | | |1 = PWMx Brake Function 1 Enabled.
<> 144:ef7eb2e8f9f7 14034 * | | |Note: x=0~1 for PWM unit0~1.
<> 144:ef7eb2e8f9f7 14035 * |[18:19] |BRK1SEL |Brake Function 1 Source Selection
<> 144:ef7eb2e8f9f7 14036 * | | |00 = From external pin BKPx1 (x=0~1 for unit0~1).
<> 144:ef7eb2e8f9f7 14037 * | | |01 = From analog comparator 0 output (CPO0).
<> 144:ef7eb2e8f9f7 14038 * | | |10 = From analog comparator 1 output (CPO1).
<> 144:ef7eb2e8f9f7 14039 * | | |11 = From analog comparator 2 output (CPO2).
<> 144:ef7eb2e8f9f7 14040 * |[20:21] |BRK0NFSEL |Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection
<> 144:ef7eb2e8f9f7 14041 * | | |00 = Filter clock = HCLK.
<> 144:ef7eb2e8f9f7 14042 * | | |01 = Filter clock = HCLK/2.
<> 144:ef7eb2e8f9f7 14043 * | | |10 = Filter clock = HCLK/4.
<> 144:ef7eb2e8f9f7 14044 * | | |11 = Filter clock = HCLK/16.
<> 144:ef7eb2e8f9f7 14045 * |[22:23] |BRK1NFSEL |Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection
<> 144:ef7eb2e8f9f7 14046 * | | |00 = Filter clock = HCLK.
<> 144:ef7eb2e8f9f7 14047 * | | |01 =Filter clock = HCLK/2.
<> 144:ef7eb2e8f9f7 14048 * | | |10 = Filter clock = HCLK/4.
<> 144:ef7eb2e8f9f7 14049 * | | |11 = Filter clock = HCLK/16.
<> 144:ef7eb2e8f9f7 14050 * |[24] |CPO0BKEN |CPO0 Digital Output As Brake0 Source Enable Control
<> 144:ef7eb2e8f9f7 14051 * | | |1 = CPO0 as one brake source in Brake 0 Enabled.
<> 144:ef7eb2e8f9f7 14052 * | | |0 = CPO0 as one brake source in Brake 0 Disabled.
<> 144:ef7eb2e8f9f7 14053 * |[25] |CPO1BKEN |CPO1 Digital Output As Brake 0 Source Enable Control
<> 144:ef7eb2e8f9f7 14054 * | | |0 = CPO1 as one brake source in Brake 0 Disabled.
<> 144:ef7eb2e8f9f7 14055 * | | |1 = CPO1 as one brake source in Brake 0 Enabled.
<> 144:ef7eb2e8f9f7 14056 * |[26] |CPO2BKEN |CPO2 Digital Output As Brake 0 Source Enable Control
<> 144:ef7eb2e8f9f7 14057 * | | |0 = CPO2 as one brake source in Brake 0 Disabled.
<> 144:ef7eb2e8f9f7 14058 * | | |1 = CPO2 as one brake source in Brake 0 Enabled.
<> 144:ef7eb2e8f9f7 14059 * |[27] |LVDBKEN |Low-Level Detection Trigger PWM Brake Function 1 Enable Control
<> 144:ef7eb2e8f9f7 14060 * | | |0 = Brake Function 1 triggered by Low-level detection Disabled.
<> 144:ef7eb2e8f9f7 14061 * | | |1 = Brake Function 1 triggered by Low-level detection Enabled.
<> 144:ef7eb2e8f9f7 14062 * |[28] |BRK0NFDIS |PWM Brake 0 Noise Filter Disable Control
<> 144:ef7eb2e8f9f7 14063 * | | |0 = Noise filter of PWM Brake 0 Enabled.
<> 144:ef7eb2e8f9f7 14064 * | | |1 = Noise filter of PWM Brake 0 Disabled.
<> 144:ef7eb2e8f9f7 14065 * |[29] |BRK1NFDIS |PWM Brake 1 Noise Filter Disable Control
<> 144:ef7eb2e8f9f7 14066 * | | |0 = Noise filter of PWM Brake 1 Enabled.
<> 144:ef7eb2e8f9f7 14067 * | | |1 = Noise filter of PWM Brake 1 Disabled.
<> 144:ef7eb2e8f9f7 14068 * |[31] |CTRLD |Center Reload Mode Enable Control
<> 144:ef7eb2e8f9f7 14069 * | | |0 = EPWM reload duty register at the period point of PWM counter.
<> 144:ef7eb2e8f9f7 14070 * | | |1 = EPWM reload duty register at the center point of PWM counter.
<> 144:ef7eb2e8f9f7 14071 * | | |This bit only work when EPWM operation at center aligned mode.
<> 144:ef7eb2e8f9f7 14072 */
<> 144:ef7eb2e8f9f7 14073 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 14074
<> 144:ef7eb2e8f9f7 14075 /**
<> 144:ef7eb2e8f9f7 14076 * STATUS
<> 144:ef7eb2e8f9f7 14077 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14078 * Offset: 0x04 PWM Status Register
<> 144:ef7eb2e8f9f7 14079 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14080 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14081 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14082 * |[0] |BRKIF0 |PWM Brake0 Flag
<> 144:ef7eb2e8f9f7 14083 * | | |0 = PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one.
<> 144:ef7eb2e8f9f7 14084 * | | |1 = When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high.
<> 144:ef7eb2e8f9f7 14085 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14086 * |[1] |BRKIF1 |PWM Brake1 Flag
<> 144:ef7eb2e8f9f7 14087 * | | |0 = PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one.
<> 144:ef7eb2e8f9f7 14088 * | | |1 = When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high.
<> 144:ef7eb2e8f9f7 14089 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14090 * |[2] |PIF |PWM Period Flag
<> 144:ef7eb2e8f9f7 14091 * | | |0 = PWM Counter has not up counted to the value of PERIOD or down counted with underflow.
<> 144:ef7eb2e8f9f7 14092 * | | |1 = Hardware will set this flag to high at the time of PWM Counter matches PERIOD in edge and Centre aligned modes or at the time of PWM Counter down counts with underflow in Centre aligned mode.
<> 144:ef7eb2e8f9f7 14093 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14094 * |[4] |EIF0 |PWMx0 Edge Flag
<> 144:ef7eb2e8f9f7 14095 * | | |0 = The PWMx0 doesn't toggle.
<> 144:ef7eb2e8f9f7 14096 * | | |1 = Hardware will set this flag to high at the time of PWMx0 rising or falling.
<> 144:ef7eb2e8f9f7 14097 * | | |If EINTTYPE0 = 0, this bit is set when PWMx0 falling is detected.
<> 144:ef7eb2e8f9f7 14098 * | | |If EINTTYPE0 = 1, this bit is set when PWMx0 rising is detected.
<> 144:ef7eb2e8f9f7 14099 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14100 * |[5] |EIF2 |PWMx2 Edge Flag
<> 144:ef7eb2e8f9f7 14101 * | | |0 = The PWMx2 doesn't toggle.
<> 144:ef7eb2e8f9f7 14102 * | | |1 = Hardware will set this flag to high at the time of PWMx2 rising or falling.
<> 144:ef7eb2e8f9f7 14103 * | | |If EINTTYPE2 = 0, this bit is set when PWMx2 falling is detected.
<> 144:ef7eb2e8f9f7 14104 * | | |If EINTTYPE2 = 1, this bit is set when PWMx2 rising is detected.
<> 144:ef7eb2e8f9f7 14105 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14106 * |[6] |EIF4 |PWMx4 Edge Flag
<> 144:ef7eb2e8f9f7 14107 * | | |0 = The PWMx4 doesn't toggle.
<> 144:ef7eb2e8f9f7 14108 * | | |1 = Hardware will set this flag to high at the time of PWMx4 rising or falling.
<> 144:ef7eb2e8f9f7 14109 * | | |If EINTTYPE4 = 0, this bit is set when PWMx4 falling is detected.
<> 144:ef7eb2e8f9f7 14110 * | | |If EINTTYPE4 = 1, this bit is set when PWMx4 rising is detected.
<> 144:ef7eb2e8f9f7 14111 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14112 * |[8] |BRK0LOCK |PWM Brake0 Locked
<> 144:ef7eb2e8f9f7 14113 * | | |0 = Brake 0 state is released.
<> 144:ef7eb2e8f9f7 14114 * | | |1 = When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked.
<> 144:ef7eb2e8f9f7 14115 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14116 * |[24] |BRK0STS |Brake 0 Status (Read Only)
<> 144:ef7eb2e8f9f7 14117 * | | |0 = PWM had been out of Brake 0 state.
<> 144:ef7eb2e8f9f7 14118 * | | |1 = PWM is in Brake 0 state.
<> 144:ef7eb2e8f9f7 14119 * |[25] |BRK1STS |Brake 1 Status (Read Only)
<> 144:ef7eb2e8f9f7 14120 * | | |0 = PWM had been out of Brake 1 state.
<> 144:ef7eb2e8f9f7 14121 * | | |1 = PWM is in Brake 1 state.
<> 144:ef7eb2e8f9f7 14122 */
<> 144:ef7eb2e8f9f7 14123 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 14124
<> 144:ef7eb2e8f9f7 14125 /**
<> 144:ef7eb2e8f9f7 14126 * PERIOD
<> 144:ef7eb2e8f9f7 14127 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14128 * Offset: 0x08 PWM Period Register
<> 144:ef7eb2e8f9f7 14129 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14130 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14131 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14132 * |[0:15] |PERIOD |PWM Period Register
<> 144:ef7eb2e8f9f7 14133 * | | |Edge aligned:
<> 144:ef7eb2e8f9f7 14134 * | | |Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14135 * | | |Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14136 * | | |Centre aligned:
<> 144:ef7eb2e8f9f7 14137 * | | |Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14138 * | | |Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14139 */
<> 144:ef7eb2e8f9f7 14140 __IO uint32_t PERIOD;
<> 144:ef7eb2e8f9f7 14141
<> 144:ef7eb2e8f9f7 14142 /**
<> 144:ef7eb2e8f9f7 14143 * CMPDAT0
<> 144:ef7eb2e8f9f7 14144 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14145 * Offset: 0x0C EPWM_CMPDAT0 Duty Register
<> 144:ef7eb2e8f9f7 14146 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14147 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14148 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14149 * |[0:15] |CMP |PWM Duty Register
<> 144:ef7eb2e8f9f7 14150 * | | |Edge aligned:
<> 144:ef7eb2e8f9f7 14151 * | | |Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14152 * | | |Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14153 * | | |Centre aligned:
<> 144:ef7eb2e8f9f7 14154 * | | |Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14155 * | | |Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14156 */
<> 144:ef7eb2e8f9f7 14157 __IO uint32_t CMPDAT0;
<> 144:ef7eb2e8f9f7 14158
<> 144:ef7eb2e8f9f7 14159 /**
<> 144:ef7eb2e8f9f7 14160 * CMPDAT2
<> 144:ef7eb2e8f9f7 14161 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14162 * Offset: 0x10 EPWM_CMPDAT2 Duty Register
<> 144:ef7eb2e8f9f7 14163 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14164 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14165 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14166 * |[0:15] |CMP |PWM Duty Register
<> 144:ef7eb2e8f9f7 14167 * | | |Edge aligned:
<> 144:ef7eb2e8f9f7 14168 * | | |Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14169 * | | |Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14170 * | | |Centre aligned:
<> 144:ef7eb2e8f9f7 14171 * | | |Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14172 * | | |Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14173 */
<> 144:ef7eb2e8f9f7 14174 __IO uint32_t CMPDAT2;
<> 144:ef7eb2e8f9f7 14175
<> 144:ef7eb2e8f9f7 14176 /**
<> 144:ef7eb2e8f9f7 14177 * CMPDAT4
<> 144:ef7eb2e8f9f7 14178 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14179 * Offset: 0x14 EPWM_CMPDAT4 Duty Register
<> 144:ef7eb2e8f9f7 14180 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14181 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14182 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14183 * |[0:15] |CMP |PWM Duty Register
<> 144:ef7eb2e8f9f7 14184 * | | |Edge aligned:
<> 144:ef7eb2e8f9f7 14185 * | | |Period = (PERIOD + 1)* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14186 * | | |Duty = (Duty +1 )* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14187 * | | |Centre aligned:
<> 144:ef7eb2e8f9f7 14188 * | | |Period = (PERIOD * 2)* EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14189 * | | |Duty = (Duty *2 + 1) * EPWMx_CLK period * pre-scalar.
<> 144:ef7eb2e8f9f7 14190 */
<> 144:ef7eb2e8f9f7 14191 __IO uint32_t CMPDAT4;
<> 144:ef7eb2e8f9f7 14192
<> 144:ef7eb2e8f9f7 14193 /**
<> 144:ef7eb2e8f9f7 14194 * MSKEN
<> 144:ef7eb2e8f9f7 14195 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14196 * Offset: 0x18 PWM Mask Mode Enable Control Register
<> 144:ef7eb2e8f9f7 14197 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14198 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14199 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14200 * |[0:5] |MSKEN |PWM Mask Enable Control
<> 144:ef7eb2e8f9f7 14201 * | | |The PWM generator signal will be masked when this bit is enabled.
<> 144:ef7eb2e8f9f7 14202 * | | |The corresponding PWMn channel will be output with PMD.n data.
<> 144:ef7eb2e8f9f7 14203 * | | |0 = PWM generator signal is output to next stage.
<> 144:ef7eb2e8f9f7 14204 * | | |1 = PWM generator signal is masked and PMD.n is output to next stage.
<> 144:ef7eb2e8f9f7 14205 * | | |Note: n = 0~5.
<> 144:ef7eb2e8f9f7 14206 */
<> 144:ef7eb2e8f9f7 14207 __IO uint32_t MSKEN;
<> 144:ef7eb2e8f9f7 14208
<> 144:ef7eb2e8f9f7 14209 /**
<> 144:ef7eb2e8f9f7 14210 * MSK
<> 144:ef7eb2e8f9f7 14211 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14212 * Offset: 0x1C PWM Mask Mode Data Register
<> 144:ef7eb2e8f9f7 14213 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14214 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14215 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14216 * |[0:5] |MSKDAT |PWM Mask Data Bit
<> 144:ef7eb2e8f9f7 14217 * | | |This data bit control the state of PWMn output pin, if the corresponding PME.n = 1.
<> 144:ef7eb2e8f9f7 14218 * | | |0 = Output logic low to PWMn.
<> 144:ef7eb2e8f9f7 14219 * | | |1 = Output logic high to PWMn.
<> 144:ef7eb2e8f9f7 14220 * | | |Note: n = 0~5.
<> 144:ef7eb2e8f9f7 14221 */
<> 144:ef7eb2e8f9f7 14222 __IO uint32_t MSK;
<> 144:ef7eb2e8f9f7 14223
<> 144:ef7eb2e8f9f7 14224 /**
<> 144:ef7eb2e8f9f7 14225 * ASYMCMP0
<> 144:ef7eb2e8f9f7 14226 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14227 * Offset: 0x20 Asymmetric EPWM_CMPDAT0 Duty Register
<> 144:ef7eb2e8f9f7 14228 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14229 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14230 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14231 * |[0:15] |CMP |Asymmetric PWM Duty Register
<> 144:ef7eb2e8f9f7 14232 * | | |When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
<> 144:ef7eb2e8f9f7 14233 */
<> 144:ef7eb2e8f9f7 14234 __IO uint32_t ASYMCMP0;
<> 144:ef7eb2e8f9f7 14235
<> 144:ef7eb2e8f9f7 14236 /**
<> 144:ef7eb2e8f9f7 14237 * ASYMCMP2
<> 144:ef7eb2e8f9f7 14238 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14239 * Offset: 0x24 Asymmetric EPWM_CMPDAT2 Duty Register
<> 144:ef7eb2e8f9f7 14240 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14241 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14242 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14243 * |[0:15] |CMP |Asymmetric PWM Duty Register
<> 144:ef7eb2e8f9f7 14244 * | | |When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
<> 144:ef7eb2e8f9f7 14245 */
<> 144:ef7eb2e8f9f7 14246 __IO uint32_t ASYMCMP2;
<> 144:ef7eb2e8f9f7 14247
<> 144:ef7eb2e8f9f7 14248 /**
<> 144:ef7eb2e8f9f7 14249 * ASYMCMP4
<> 144:ef7eb2e8f9f7 14250 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14251 * Offset: 0x28 Asymmetric EPWM_CMPDAT4 Duty Register
<> 144:ef7eb2e8f9f7 14252 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14253 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14254 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14255 * |[0:15] |CMP |Asymmetric PWM Duty Register
<> 144:ef7eb2e8f9f7 14256 * | | |When the asymmetric PWM function is enabled, this 16-bit field determines the second time compared value after PWM counter has matched with PWM_Duty in the first half PWM cycle.
<> 144:ef7eb2e8f9f7 14257 */
<> 144:ef7eb2e8f9f7 14258 __IO uint32_t ASYMCMP4;
<> 144:ef7eb2e8f9f7 14259
<> 144:ef7eb2e8f9f7 14260 /**
<> 144:ef7eb2e8f9f7 14261 * DTCTL
<> 144:ef7eb2e8f9f7 14262 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14263 * Offset: 0x2C PWM Dead-time Control Register
<> 144:ef7eb2e8f9f7 14264 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14265 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14266 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14267 * |[0:10] |DTCNT |Dead-Time Counter
<> 144:ef7eb2e8f9f7 14268 * | | |The dead-time can be calculated from the following formula:
<> 144:ef7eb2e8f9f7 14269 * | | |Dead-time = EPWMx_CLK period * (DTCNT.[10:0]+1).
<> 144:ef7eb2e8f9f7 14270 * |[16] |DTEN0 |Dead-Time Insertion Enable Control For PWMx Pair (PWM0, PWM1)
<> 144:ef7eb2e8f9f7 14271 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
<> 144:ef7eb2e8f9f7 14272 * | | |If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 144:ef7eb2e8f9f7 14273 * | | |0 = Dead-time insertion Disabled on the pin pair (PWM0, PWM1).
<> 144:ef7eb2e8f9f7 14274 * | | |1 = Dead-time insertion Enabled on the pin pair (PWM0, PWM1).
<> 144:ef7eb2e8f9f7 14275 * | | |Note: x=0~1 for PWM unit0~1.
<> 144:ef7eb2e8f9f7 14276 * |[17] |DTEN2 |Dead-Time Insertion Enable Control For PWMx Pair (PWM2, PWM3)
<> 144:ef7eb2e8f9f7 14277 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
<> 144:ef7eb2e8f9f7 14278 * | | |If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 144:ef7eb2e8f9f7 14279 * | | |0 = Dead-time insertion Disabled on the pin pair (PWM2, PWM3).
<> 144:ef7eb2e8f9f7 14280 * | | |1 = Dead-time insertion Enabled on the pin pair (PWM2, PWM3).
<> 144:ef7eb2e8f9f7 14281 * | | |Note: x=0~1 for PWM unit0~1.
<> 144:ef7eb2e8f9f7 14282 * |[18] |DTEN4 |Dead-Time Insertion Enable Control For PWMx Pair (PWM4, PWM5)
<> 144:ef7eb2e8f9f7 14283 * | | |Dead-time insertion is only active when this pair of complementary PWM is enabled.
<> 144:ef7eb2e8f9f7 14284 * | | |If dead-time insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 144:ef7eb2e8f9f7 14285 * | | |0 = Dead-time insertion Disabled on the pin pair (PWM4, PWM5).
<> 144:ef7eb2e8f9f7 14286 * | | |1 = Dead-time insertion Enabled on the pin pair (PWM4, PWM5).
<> 144:ef7eb2e8f9f7 14287 * | | |Note: x=0~1 for PWM unit0~1.
<> 144:ef7eb2e8f9f7 14288 */
<> 144:ef7eb2e8f9f7 14289 __IO uint32_t DTCTL;
<> 144:ef7eb2e8f9f7 14290
<> 144:ef7eb2e8f9f7 14291 /**
<> 144:ef7eb2e8f9f7 14292 * BRKOUT
<> 144:ef7eb2e8f9f7 14293 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14294 * Offset: 0x30 PWM Brake Output
<> 144:ef7eb2e8f9f7 14295 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14296 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14297 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14298 * |[0:5] |BRKOUT |PWM Brake Output
<> 144:ef7eb2e8f9f7 14299 * | | |When PWM Brake is asserted, the PWM0~5 output state before polarity control will follow PWM1 bit0~5 setting, respectively.
<> 144:ef7eb2e8f9f7 14300 * | | |0 = The PWMn output before polarity control is low when Brake is asserted.
<> 144:ef7eb2e8f9f7 14301 * | | |1 = The PWMn output before polarity control is high when Brake is asserted.
<> 144:ef7eb2e8f9f7 14302 * | | |Note: n = 0~5.
<> 144:ef7eb2e8f9f7 14303 */
<> 144:ef7eb2e8f9f7 14304 __IO uint32_t BRKOUT;
<> 144:ef7eb2e8f9f7 14305
<> 144:ef7eb2e8f9f7 14306 /**
<> 144:ef7eb2e8f9f7 14307 * NPCTL
<> 144:ef7eb2e8f9f7 14308 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14309 * Offset: 0x34 PWM Negative Polarity Control
<> 144:ef7eb2e8f9f7 14310 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14311 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14312 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14313 * |[0:5] |NEGPOLAR |PWM Negative Polarity Control
<> 144:ef7eb2e8f9f7 14314 * | | |The register bit controls polarity/active state of real PWM output.
<> 144:ef7eb2e8f9f7 14315 * | | |0 = PWMn output is active high.
<> 144:ef7eb2e8f9f7 14316 * | | |1 = PWMn output is active low.
<> 144:ef7eb2e8f9f7 14317 * | | |Note: n = 0~5.
<> 144:ef7eb2e8f9f7 14318 */
<> 144:ef7eb2e8f9f7 14319 __IO uint32_t NPCTL;
<> 144:ef7eb2e8f9f7 14320
<> 144:ef7eb2e8f9f7 14321 /**
<> 144:ef7eb2e8f9f7 14322 * ASYMCTL
<> 144:ef7eb2e8f9f7 14323 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14324 * Offset: 0x38 Asymmetric PWM Control Register
<> 144:ef7eb2e8f9f7 14325 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14326 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14327 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14328 * |[0] |ASYMEN |Asymmetric PWM Enable Control
<> 144:ef7eb2e8f9f7 14329 * | | |0 = Asymmetric PWM function Disabled.
<> 144:ef7eb2e8f9f7 14330 * | | |1 = Asymmetric PWM function Enabled.
<> 144:ef7eb2e8f9f7 14331 * | | |Note: This control bit is only valid when PWM module is set in Centre-aligned mode.
<> 144:ef7eb2e8f9f7 14332 * |[8:9] |ASYMMODE0 |Asymmetric PWMx0 Reload Mode Setting
<> 144:ef7eb2e8f9f7 14333 * | | |00 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14334 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle
<> 144:ef7eb2e8f9f7 14335 * | | |3.
<> 144:ef7eb2e8f9f7 14336 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
<> 144:ef7eb2e8f9f7 14337 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle.
<> 144:ef7eb2e8f9f7 14338 * | | |01 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14339 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle
<> 144:ef7eb2e8f9f7 14340 * | | |3.
<> 144:ef7eb2e8f9f7 14341 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
<> 144:ef7eb2e8f9f7 14342 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in up-counting cycle.
<> 144:ef7eb2e8f9f7 14343 * | | | 5. PWMx0 must be less than ASPWMx0
<> 144:ef7eb2e8f9f7 14344 * | | |10 = 1. PWM compare register 0 is reload PWM_Duty (PWMx0[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14345 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle
<> 144:ef7eb2e8f9f7 14346 * | | |3.
<> 144:ef7eb2e8f9f7 14347 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx0[15:00]).
<> 144:ef7eb2e8f9f7 14348 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 0 in down-counting cycle.
<> 144:ef7eb2e8f9f7 14349 * | | | 5. PWMx0 must be greater than ASPWMx0.
<> 144:ef7eb2e8f9f7 14350 * | | |11 = Reserved.
<> 144:ef7eb2e8f9f7 14351 * | | |Note1: x=0~1 for PWM unit 0~1.
<> 144:ef7eb2e8f9f7 14352 * | | |Note2: This bit field is available only when ASYMEN=1.
<> 144:ef7eb2e8f9f7 14353 * | | |Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
<> 144:ef7eb2e8f9f7 14354 * |[16:17] |ASYMMODE2 |Asymmetric PWMx2 Reload Mode Setting
<> 144:ef7eb2e8f9f7 14355 * | | |00 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14356 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle
<> 144:ef7eb2e8f9f7 14357 * | | |3.
<> 144:ef7eb2e8f9f7 14358 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 2 is reloaded with CMP (ASPWMx2[15:00]).
<> 144:ef7eb2e8f9f7 14359 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle.
<> 144:ef7eb2e8f9f7 14360 * | | |01 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14361 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle
<> 144:ef7eb2e8f9f7 14362 * | | |3.
<> 144:ef7eb2e8f9f7 14363 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register2 is reloaded with CMP (ASPWMx2[15:00]).
<> 144:ef7eb2e8f9f7 14364 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in up-counting cycle.
<> 144:ef7eb2e8f9f7 14365 * | | | 5. PWMx2 must be less than ASPWMx2
<> 144:ef7eb2e8f9f7 14366 * | | |10 = 1. PWM compare register 2 is reload PWM_Duty (PWMx2[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14367 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle
<> 144:ef7eb2e8f9f7 14368 * | | |3.
<> 144:ef7eb2e8f9f7 14369 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 2 is reloaded with CMP (ASPWMx2[15:00]).
<> 144:ef7eb2e8f9f7 14370 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 2 in down-counting cycle.
<> 144:ef7eb2e8f9f7 14371 * | | | 5. PWMx2 must be greater than ASPWMx2.
<> 144:ef7eb2e8f9f7 14372 * | | |11 = Reserved.
<> 144:ef7eb2e8f9f7 14373 * | | |Note1: x=0~1 for PWM unit 0~1.
<> 144:ef7eb2e8f9f7 14374 * | | |Note2: This bit field is available only when ASYMEN=1.
<> 144:ef7eb2e8f9f7 14375 * | | |Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
<> 144:ef7eb2e8f9f7 14376 * |[24:25] |ASYMMODE4 |Asymmetric PWMx4 Reload Mode Setting
<> 144:ef7eb2e8f9f7 14377 * | | |00 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14378 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle
<> 144:ef7eb2e8f9f7 14379 * | | |3.
<> 144:ef7eb2e8f9f7 14380 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 4 is reloaded with CMP (ASPWMx4[15:00]).
<> 144:ef7eb2e8f9f7 14381 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle.
<> 144:ef7eb2e8f9f7 14382 * | | |01 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14383 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle
<> 144:ef7eb2e8f9f7 14384 * | | |3.
<> 144:ef7eb2e8f9f7 14385 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 0 is reloaded with CMP (ASPWMx4[15:00]).
<> 144:ef7eb2e8f9f7 14386 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in up-counting cycle.
<> 144:ef7eb2e8f9f7 14387 * | | | 5. PWMx4 must be less than ASPWMx4.
<> 144:ef7eb2e8f9f7 14388 * | | |10 = 1. PWM compare register 4 is reload PWM_Duty (PWMx4[15:0]) at PWM cycle start.
<> 144:ef7eb2e8f9f7 14389 * | | | 2. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle
<> 144:ef7eb2e8f9f7 14390 * | | |3.
<> 144:ef7eb2e8f9f7 14391 * | | |PWM compare output toggles at compare match, in the meanwhile, PWM compare register 4 is reloaded with CMP (ASPWMx4[15:00]).
<> 144:ef7eb2e8f9f7 14392 * | | | 4. PWM module compares the PWM counter (PWMCNT) with PWM compare register 4 in down-counting cycle.
<> 144:ef7eb2e8f9f7 14393 * | | | 5. PWMx4 must be greater than ASPWMx4.
<> 144:ef7eb2e8f9f7 14394 * | | |11= Reserved.
<> 144:ef7eb2e8f9f7 14395 * | | |Note1: x=0~1 for PWM unit 0~1.
<> 144:ef7eb2e8f9f7 14396 * | | |Note2: This bit field is available only when ASYMEN=1.
<> 144:ef7eb2e8f9f7 14397 * | | |Note3: The setting will be effected at the condition of LOAD=1 and from the start of next PWM cycle.
<> 144:ef7eb2e8f9f7 14398 */
<> 144:ef7eb2e8f9f7 14399 __IO uint32_t ASYMCTL;
<> 144:ef7eb2e8f9f7 14400
<> 144:ef7eb2e8f9f7 14401 /**
<> 144:ef7eb2e8f9f7 14402 * PERIODCNT
<> 144:ef7eb2e8f9f7 14403 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14404 * Offset: 0x3C PIF Compared Counter
<> 144:ef7eb2e8f9f7 14405 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14406 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14407 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14408 * |[0:3] |PERIODCNT |PIF Compared Counter
<> 144:ef7eb2e8f9f7 14409 * | | |The register sets the count number which defines how many times of PWM period occurs to set bit PIF to request the PWM period interrupt.
<> 144:ef7eb2e8f9f7 14410 * | | |PIF will be set in every (1 + PERIODCNT[3:0]) times of PWM period or center point defined by INTTYPE when EPWM_CTL [8] occurred.
<> 144:ef7eb2e8f9f7 14411 */
<> 144:ef7eb2e8f9f7 14412 __IO uint32_t PERIODCNT;
<> 144:ef7eb2e8f9f7 14413
<> 144:ef7eb2e8f9f7 14414 /**
<> 144:ef7eb2e8f9f7 14415 * EINTCTL
<> 144:ef7eb2e8f9f7 14416 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14417 * Offset: 0x40 PWM Edge Interrupt Control Register
<> 144:ef7eb2e8f9f7 14418 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14419 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14420 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14421 * |[0] |EDGEIEN0 |PWMx0 Edge Interrupt Enable Control
<> 144:ef7eb2e8f9f7 14422 * | | |0 = Disabling flag EIF0 to trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 14423 * | | |1 = Enabling flag EIF0 can trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 14424 * |[1] |EDGEIEN2 |PWMx2 Edge Interrupt Enable Control
<> 144:ef7eb2e8f9f7 14425 * | | |0 = Disabling flag EIF2 can trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 14426 * | | |1 = Enabling flag EIF2 can trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 14427 * |[2] |EDGEIEN4 |PWMx4 Edge Interrupt Enable Control
<> 144:ef7eb2e8f9f7 14428 * | | |0 = Disable flag EIF4 to trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 14429 * | | |1 = Enabling flag EIF4 can trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 14430 * |[8] |EINTTYPE0 |PWMx0 Edge Interrupt Type
<> 144:ef7eb2e8f9f7 14431 * | | |0 = EIF0 will be set if falling edge is detected at PWMx0.
<> 144:ef7eb2e8f9f7 14432 * | | |1 = EIF0 will be set if rising edge is detected at PWMx0.
<> 144:ef7eb2e8f9f7 14433 * |[9] |EINTTYPE2 |PWMx2 Edge Interrupt Type
<> 144:ef7eb2e8f9f7 14434 * | | |0 = EIF2 will be set if falling edge is detected at PWMx2.
<> 144:ef7eb2e8f9f7 14435 * | | |1 = EIF2 will be set if rising edge is detected at PWMx2.
<> 144:ef7eb2e8f9f7 14436 * |[10] |EINTTYPE4 |PWMx4 Edge Interrupt Type
<> 144:ef7eb2e8f9f7 14437 * | | |0 = EIF4 will be set if falling edge is detected at PWMx4.
<> 144:ef7eb2e8f9f7 14438 * | | |1 = EIF4 will be set if rising edge is detected at PWMx4.
<> 144:ef7eb2e8f9f7 14439 */
<> 144:ef7eb2e8f9f7 14440 __IO uint32_t EINTCTL;
<> 144:ef7eb2e8f9f7 14441
<> 144:ef7eb2e8f9f7 14442 /**
<> 144:ef7eb2e8f9f7 14443 * OUTEN0
<> 144:ef7eb2e8f9f7 14444 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14445 * Offset: 0x44 PWM Output Enable Control Register
<> 144:ef7eb2e8f9f7 14446 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14447 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14448 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14449 * |[0] |EVENOUTEN |PWM Even Ports Output Enable Control
<> 144:ef7eb2e8f9f7 14450 * | | |0 = PWM even ports output Disabled (PWM even ports at tri-state).
<> 144:ef7eb2e8f9f7 14451 * | | |1 = PWM even ports output Enabled.
<> 144:ef7eb2e8f9f7 14452 * |[1] |ODDOUTEN |PWM Odd Ports Output Enable Control
<> 144:ef7eb2e8f9f7 14453 * | | |0 = PWM odd ports output Disabled (PWM even ports at tri-state).
<> 144:ef7eb2e8f9f7 14454 * | | |1 = PWM odd ports output Enabled.
<> 144:ef7eb2e8f9f7 14455 */
<> 144:ef7eb2e8f9f7 14456 __IO uint32_t OUTEN0;
<> 144:ef7eb2e8f9f7 14457
<> 144:ef7eb2e8f9f7 14458 } EPWM_T;
<> 144:ef7eb2e8f9f7 14459
<> 144:ef7eb2e8f9f7 14460 /**
<> 144:ef7eb2e8f9f7 14461 @addtogroup EPWM_CONST EPWM Bit Field Definition
<> 144:ef7eb2e8f9f7 14462 Constant Definitions for EPWM Controller
<> 144:ef7eb2e8f9f7 14463 @{ */
<> 144:ef7eb2e8f9f7 14464
<> 144:ef7eb2e8f9f7 14465 #define EPWM_CTL_MODE_Pos (0) /*!< EPWM CTL: MODE Position */
<> 144:ef7eb2e8f9f7 14466 #define EPWM_CTL_MODE_Msk (0x3ul << EPWM_CTL_MODE_Pos) /*!< EPWM CTL: MODE Mask */
<> 144:ef7eb2e8f9f7 14467
<> 144:ef7eb2e8f9f7 14468 #define EPWM_CTL_CLKDIV_Pos (2) /*!< EPWM CTL: CLKDIV Position */
<> 144:ef7eb2e8f9f7 14469 #define EPWM_CTL_CLKDIV_Msk (0x3ul << EPWM_CTL_CLKDIV_Pos) /*!< EPWM CTL: CLKDIV Mask */
<> 144:ef7eb2e8f9f7 14470
<> 144:ef7eb2e8f9f7 14471 #define EPWM_CTL_PWMIEN_Pos (4) /*!< EPWM CTL: PWMIEN Position */
<> 144:ef7eb2e8f9f7 14472 #define EPWM_CTL_PWMIEN_Msk (0x1ul << EPWM_CTL_PWMIEN_Pos) /*!< EPWM CTL: PWMIEN Mask */
<> 144:ef7eb2e8f9f7 14473
<> 144:ef7eb2e8f9f7 14474 #define EPWM_CTL_BRKIEN_Pos (5) /*!< EPWM CTL: BRKIEN Position */
<> 144:ef7eb2e8f9f7 14475 #define EPWM_CTL_BRKIEN_Msk (0x1ul << EPWM_CTL_BRKIEN_Pos) /*!< EPWM CTL: BRKIEN Mask */
<> 144:ef7eb2e8f9f7 14476
<> 144:ef7eb2e8f9f7 14477 #define EPWM_CTL_LOAD_Pos (6) /*!< EPWM CTL: LOAD Position */
<> 144:ef7eb2e8f9f7 14478 #define EPWM_CTL_LOAD_Msk (0x1ul << EPWM_CTL_LOAD_Pos) /*!< EPWM CTL: LOAD Mask */
<> 144:ef7eb2e8f9f7 14479
<> 144:ef7eb2e8f9f7 14480 #define EPWM_CTL_CNTEN_Pos (7) /*!< EPWM CTL: CNTEN Position */
<> 144:ef7eb2e8f9f7 14481 #define EPWM_CTL_CNTEN_Msk (0x1ul << EPWM_CTL_CNTEN_Pos) /*!< EPWM CTL: CNTEN Mask */
<> 144:ef7eb2e8f9f7 14482
<> 144:ef7eb2e8f9f7 14483 #define EPWM_CTL_INTTYPE_Pos (8) /*!< EPWM CTL: INTTYPE Position */
<> 144:ef7eb2e8f9f7 14484 #define EPWM_CTL_INTTYPE_Msk (0x1ul << EPWM_CTL_INTTYPE_Pos) /*!< EPWM CTL: INTTYPE Mask */
<> 144:ef7eb2e8f9f7 14485
<> 144:ef7eb2e8f9f7 14486 #define EPWM_CTL_PINV_Pos (9) /*!< EPWM CTL: PINV Position */
<> 144:ef7eb2e8f9f7 14487 #define EPWM_CTL_PINV_Msk (0x1ul << EPWM_CTL_PINV_Pos) /*!< EPWM CTL: PINV Mask */
<> 144:ef7eb2e8f9f7 14488
<> 144:ef7eb2e8f9f7 14489 #define EPWM_CTL_CNTCLR_Pos (11) /*!< EPWM CTL: CNTCLR Position */
<> 144:ef7eb2e8f9f7 14490 #define EPWM_CTL_CNTCLR_Msk (0x1ul << EPWM_CTL_CNTCLR_Pos) /*!< EPWM CTL: CNTCLR Mask */
<> 144:ef7eb2e8f9f7 14491
<> 144:ef7eb2e8f9f7 14492 #define EPWM_CTL_CNTTYPE_Pos (12) /*!< EPWM CTL: CNTTYPE Position */
<> 144:ef7eb2e8f9f7 14493 #define EPWM_CTL_CNTTYPE_Msk (0x1ul << EPWM_CTL_CNTTYPE_Pos) /*!< EPWM CTL: CNTTYPE Mask */
<> 144:ef7eb2e8f9f7 14494
<> 144:ef7eb2e8f9f7 14495 #define EPWM_CTL_GROUPEN_Pos (13) /*!< EPWM CTL: GROUPEN Position */
<> 144:ef7eb2e8f9f7 14496 #define EPWM_CTL_GROUPEN_Msk (0x1ul << EPWM_CTL_GROUPEN_Pos) /*!< EPWM CTL: GROUPEN Mask */
<> 144:ef7eb2e8f9f7 14497
<> 144:ef7eb2e8f9f7 14498 #define EPWM_CTL_BRKP0INV_Pos (14) /*!< EPWM CTL: BRKP0INV Position */
<> 144:ef7eb2e8f9f7 14499 #define EPWM_CTL_BRKP0INV_Msk (0x1ul << EPWM_CTL_BRKP0INV_Pos) /*!< EPWM CTL: BRKP0INV Mask */
<> 144:ef7eb2e8f9f7 14500
<> 144:ef7eb2e8f9f7 14501 #define EPWM_CTL_BRKP1INV_Pos (15) /*!< EPWM CTL: BRKP1INV Position */
<> 144:ef7eb2e8f9f7 14502 #define EPWM_CTL_BRKP1INV_Msk (0x1ul << EPWM_CTL_BRKP1INV_Pos) /*!< EPWM CTL: BRKP1INV Mask */
<> 144:ef7eb2e8f9f7 14503
<> 144:ef7eb2e8f9f7 14504 #define EPWM_CTL_BRKP0EN_Pos (16) /*!< EPWM CTL: BRKP0EN Position */
<> 144:ef7eb2e8f9f7 14505 #define EPWM_CTL_BRKP0EN_Msk (0x1ul << EPWM_CTL_BRKP0EN_Pos) /*!< EPWM CTL: BRKP0EN Mask */
<> 144:ef7eb2e8f9f7 14506
<> 144:ef7eb2e8f9f7 14507 #define EPWM_CTL_BRKP1EN_Pos (17) /*!< EPWM CTL: BRKP1EN Position */
<> 144:ef7eb2e8f9f7 14508 #define EPWM_CTL_BRKP1EN_Msk (0x1ul << EPWM_CTL_BRKP1EN_Pos) /*!< EPWM CTL: BRKP1EN Mask */
<> 144:ef7eb2e8f9f7 14509
<> 144:ef7eb2e8f9f7 14510 #define EPWM_CTL_BRK1SEL_Pos (18) /*!< EPWM CTL: BRK1SEL Position */
<> 144:ef7eb2e8f9f7 14511 #define EPWM_CTL_BRK1SEL_Msk (0x3ul << EPWM_CTL_BRK1SEL_Pos) /*!< EPWM CTL: BRK1SEL Mask */
<> 144:ef7eb2e8f9f7 14512
<> 144:ef7eb2e8f9f7 14513 #define EPWM_CTL_BRK0NFSEL_Pos (20) /*!< EPWM CTL: BRK0NFSEL Position */
<> 144:ef7eb2e8f9f7 14514 #define EPWM_CTL_BRK0NFSEL_Msk (0x3ul << EPWM_CTL_BRK0NFSEL_Pos) /*!< EPWM CTL: BRK0NFSEL Mask */
<> 144:ef7eb2e8f9f7 14515
<> 144:ef7eb2e8f9f7 14516 #define EPWM_CTL_BRK1NFSEL_Pos (22) /*!< EPWM CTL: BRK1NFSEL Position */
<> 144:ef7eb2e8f9f7 14517 #define EPWM_CTL_BRK1NFSEL_Msk (0x3ul << EPWM_CTL_BRK1NFSEL_Pos) /*!< EPWM CTL: BRK1NFSEL Mask */
<> 144:ef7eb2e8f9f7 14518
<> 144:ef7eb2e8f9f7 14519 #define EPWM_CTL_CPO0BKEN_Pos (24) /*!< EPWM CTL: CPO0BKEN Position */
<> 144:ef7eb2e8f9f7 14520 #define EPWM_CTL_CPO0BKEN_Msk (0x1ul << EPWM_CTL_CPO0BKEN_Pos) /*!< EPWM CTL: CPO0BKEN Mask */
<> 144:ef7eb2e8f9f7 14521
<> 144:ef7eb2e8f9f7 14522 #define EPWM_CTL_CPO1BKEN_Pos (25) /*!< EPWM CTL: CPO1BKEN Position */
<> 144:ef7eb2e8f9f7 14523 #define EPWM_CTL_CPO1BKEN_Msk (0x1ul << EPWM_CTL_CPO1BKEN_Pos) /*!< EPWM CTL: CPO1BKEN Mask */
<> 144:ef7eb2e8f9f7 14524
<> 144:ef7eb2e8f9f7 14525 #define EPWM_CTL_CPO2BKEN_Pos (26) /*!< EPWM CTL: CPO2BKEN Position */
<> 144:ef7eb2e8f9f7 14526 #define EPWM_CTL_CPO2BKEN_Msk (0x1ul << EPWM_CTL_CPO2BKEN_Pos) /*!< EPWM CTL: CPO2BKEN Mask */
<> 144:ef7eb2e8f9f7 14527
<> 144:ef7eb2e8f9f7 14528 #define EPWM_CTL_LVDBKEN_Pos (27) /*!< EPWM CTL: LVDBKEN Position */
<> 144:ef7eb2e8f9f7 14529 #define EPWM_CTL_LVDBKEN_Msk (0x1ul << EPWM_CTL_LVDBKEN_Pos) /*!< EPWM CTL: LVDBKEN Mask */
<> 144:ef7eb2e8f9f7 14530
<> 144:ef7eb2e8f9f7 14531 #define EPWM_CTL_BRK0NFDIS_Pos (28) /*!< EPWM CTL: BRK0NFDIS Position */
<> 144:ef7eb2e8f9f7 14532 #define EPWM_CTL_BRK0NFDIS_Msk (0x1ul << EPWM_CTL_BRK0NFDIS_Pos) /*!< EPWM CTL: BRK0NFDIS Mask */
<> 144:ef7eb2e8f9f7 14533
<> 144:ef7eb2e8f9f7 14534 #define EPWM_CTL_BRK1NFDIS_Pos (29) /*!< EPWM CTL: BRK1NFDIS Position */
<> 144:ef7eb2e8f9f7 14535 #define EPWM_CTL_BRK1NFDIS_Msk (0x1ul << EPWM_CTL_BRK1NFDIS_Pos) /*!< EPWM CTL: BRK1NFDIS Mask */
<> 144:ef7eb2e8f9f7 14536
<> 144:ef7eb2e8f9f7 14537 #define EPWM_CTL_CTRLD_Pos (31) /*!< EPWM CTL: CTRLD Position */
<> 144:ef7eb2e8f9f7 14538 #define EPWM_CTL_CTRLD_Msk (0x1ul << EPWM_CTL_CTRLD_Pos) /*!< EPWM CTL: CTRLD Mask */
<> 144:ef7eb2e8f9f7 14539
<> 144:ef7eb2e8f9f7 14540 #define EPWM_STATUS_BRKIF0_Pos (0) /*!< EPWM STATUS: BRKIF0 Position */
<> 144:ef7eb2e8f9f7 14541 #define EPWM_STATUS_BRKIF0_Msk (0x1ul << EPWM_STATUS_BRKIF0_Pos) /*!< EPWM STATUS: BRKIF0 Mask */
<> 144:ef7eb2e8f9f7 14542
<> 144:ef7eb2e8f9f7 14543 #define EPWM_STATUS_BRKIF1_Pos (1) /*!< EPWM STATUS: BRKIF1 Position */
<> 144:ef7eb2e8f9f7 14544 #define EPWM_STATUS_BRKIF1_Msk (0x1ul << EPWM_STATUS_BRKIF1_Pos) /*!< EPWM STATUS: BRKIF1 Mask */
<> 144:ef7eb2e8f9f7 14545
<> 144:ef7eb2e8f9f7 14546 #define EPWM_STATUS_PIF_Pos (2) /*!< EPWM STATUS: PIF Position */
<> 144:ef7eb2e8f9f7 14547 #define EPWM_STATUS_PIF_Msk (0x1ul << EPWM_STATUS_PIF_Pos) /*!< EPWM STATUS: PIF Mask */
<> 144:ef7eb2e8f9f7 14548
<> 144:ef7eb2e8f9f7 14549 #define EPWM_STATUS_EIF0_Pos (4) /*!< EPWM STATUS: EIF0 Position */
<> 144:ef7eb2e8f9f7 14550 #define EPWM_STATUS_EIF0_Msk (0x1ul << EPWM_STATUS_EIF0_Pos) /*!< EPWM STATUS: EIF0 Mask */
<> 144:ef7eb2e8f9f7 14551
<> 144:ef7eb2e8f9f7 14552 #define EPWM_STATUS_EIF2_Pos (5) /*!< EPWM STATUS: EIF2 Position */
<> 144:ef7eb2e8f9f7 14553 #define EPWM_STATUS_EIF2_Msk (0x1ul << EPWM_STATUS_EIF2_Pos) /*!< EPWM STATUS: EIF2 Mask */
<> 144:ef7eb2e8f9f7 14554
<> 144:ef7eb2e8f9f7 14555 #define EPWM_STATUS_EIF4_Pos (6) /*!< EPWM STATUS: EIF4 Position */
<> 144:ef7eb2e8f9f7 14556 #define EPWM_STATUS_EIF4_Msk (0x1ul << EPWM_STATUS_EIF4_Pos) /*!< EPWM STATUS: EIF4 Mask */
<> 144:ef7eb2e8f9f7 14557
<> 144:ef7eb2e8f9f7 14558 #define EPWM_STATUS_BRK0LOCK_Pos (8) /*!< EPWM STATUS: BRK0LOCK Position */
<> 144:ef7eb2e8f9f7 14559 #define EPWM_STATUS_BRK0LOCK_Msk (0x1ul << EPWM_STATUS_BRK0LOCK_Pos) /*!< EPWM STATUS: BRK0LOCK Mask */
<> 144:ef7eb2e8f9f7 14560
<> 144:ef7eb2e8f9f7 14561 #define EPWM_STATUS_BRK0STS_Pos (24) /*!< EPWM STATUS: BRK0STS Position */
<> 144:ef7eb2e8f9f7 14562 #define EPWM_STATUS_BRK0STS_Msk (0x1ul << EPWM_STATUS_BRK0STS_Pos) /*!< EPWM STATUS: BRK0STS Mask */
<> 144:ef7eb2e8f9f7 14563
<> 144:ef7eb2e8f9f7 14564 #define EPWM_STATUS_BRK1STS_Pos (25) /*!< EPWM STATUS: BRK1STS Position */
<> 144:ef7eb2e8f9f7 14565 #define EPWM_STATUS_BRK1STS_Msk (0x1ul << EPWM_STATUS_BRK1STS_Pos) /*!< EPWM STATUS: BRK1STS Mask */
<> 144:ef7eb2e8f9f7 14566
<> 144:ef7eb2e8f9f7 14567 #define EPWM_PERIOD_PERIOD_Pos (0) /*!< EPWM PERIOD: PERIOD Position */
<> 144:ef7eb2e8f9f7 14568 #define EPWM_PERIOD_PERIOD_Msk (0xfffful << EPWM_PERIOD_PERIOD_Pos) /*!< EPWM PERIOD: PERIOD Mask */
<> 144:ef7eb2e8f9f7 14569
<> 144:ef7eb2e8f9f7 14570 #define EPWM_CMPDAT0_CMP_Pos (0) /*!< EPWM CMPDAT0: CMP Position */
<> 144:ef7eb2e8f9f7 14571 #define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) /*!< EPWM CMPDAT0: CMP Mask */
<> 144:ef7eb2e8f9f7 14572
<> 144:ef7eb2e8f9f7 14573 #define EPWM_CMPDAT2_CMP_Pos (0) /*!< EPWM CMPDAT2: CMP Position */
<> 144:ef7eb2e8f9f7 14574 #define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) /*!< EPWM CMPDAT2: CMP Mask */
<> 144:ef7eb2e8f9f7 14575
<> 144:ef7eb2e8f9f7 14576 #define EPWM_CMPDAT4_CMP_Pos (0) /*!< EPWM CMPDAT4: CMP Position */
<> 144:ef7eb2e8f9f7 14577 #define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) /*!< EPWM CMPDAT4: CMP Mask */
<> 144:ef7eb2e8f9f7 14578
<> 144:ef7eb2e8f9f7 14579 #define EPWM_MSKEN_MSKEN_Pos (0) /*!< EPWM MSKEN: MSKEN Position */
<> 144:ef7eb2e8f9f7 14580 #define EPWM_MSKEN_MSKEN_Msk (0x3ful << EPWM_MSKEN_MSKEN_Pos) /*!< EPWM MSKEN: MSKEN Mask */
<> 144:ef7eb2e8f9f7 14581
<> 144:ef7eb2e8f9f7 14582 #define EPWM_MSK_MSKDAT_Pos (0) /*!< EPWM MSK: MSKDAT Position */
<> 144:ef7eb2e8f9f7 14583 #define EPWM_MSK_MSKDAT_Msk (0x3ful << EPWM_MSK_MSKDAT_Pos) /*!< EPWM MSK: MSKDAT Mask */
<> 144:ef7eb2e8f9f7 14584
<> 144:ef7eb2e8f9f7 14585 #define EPWM_ASYMCMP0_CMP_Pos (0) /*!< EPWM ASYMCMP0: CMP Position */
<> 144:ef7eb2e8f9f7 14586 #define EPWM_ASYMCMP0_CMP_Msk (0xfffful << EPWM_ASYMCMP0_CMP_Pos) /*!< EPWM ASYMCMP0: CMP Mask */
<> 144:ef7eb2e8f9f7 14587
<> 144:ef7eb2e8f9f7 14588 #define EPWM_ASYMCMP2_CMP_Pos (0) /*!< EPWM ASYMCMP2: CMP Position */
<> 144:ef7eb2e8f9f7 14589 #define EPWM_ASYMCMP2_CMP_Msk (0xfffful << EPWM_ASYMCMP2_CMP_Pos) /*!< EPWM ASYMCMP2: CMP Mask */
<> 144:ef7eb2e8f9f7 14590
<> 144:ef7eb2e8f9f7 14591 #define EPWM_ASYMCMP4_CMP_Pos (0) /*!< EPWM ASYMCMP4: CMP Position */
<> 144:ef7eb2e8f9f7 14592 #define EPWM_ASYMCMP4_CMP_Msk (0xfffful << EPWM_ASYMCMP4_CMP_Pos) /*!< EPWM ASYMCMP4: CMP Mask */
<> 144:ef7eb2e8f9f7 14593
<> 144:ef7eb2e8f9f7 14594 #define EPWM_DTCTL_DTCNT_Pos (0) /*!< EPWM DTCTL: DTCNT Position */
<> 144:ef7eb2e8f9f7 14595 #define EPWM_DTCTL_DTCNT_Msk (0x7fful << EPWM_DTCTL_DTCNT_Pos) /*!< EPWM DTCTL: DTCNT Mask */
<> 144:ef7eb2e8f9f7 14596
<> 144:ef7eb2e8f9f7 14597 #define EPWM_DTCTL_DTEN0_Pos (16) /*!< EPWM DTCTL: DTEN0 Position */
<> 144:ef7eb2e8f9f7 14598 #define EPWM_DTCTL_DTEN0_Msk (0x1ul << EPWM_DTCTL_DTEN0_Pos) /*!< EPWM DTCTL: DTEN0 Mask */
<> 144:ef7eb2e8f9f7 14599
<> 144:ef7eb2e8f9f7 14600 #define EPWM_DTCTL_DTEN2_Pos (17) /*!< EPWM DTCTL: DTEN2 Position */
<> 144:ef7eb2e8f9f7 14601 #define EPWM_DTCTL_DTEN2_Msk (0x1ul << EPWM_DTCTL_DTEN2_Pos) /*!< EPWM DTCTL: DTEN2 Mask */
<> 144:ef7eb2e8f9f7 14602
<> 144:ef7eb2e8f9f7 14603 #define EPWM_DTCTL_DTEN4_Pos (18) /*!< EPWM DTCTL: DTEN4 Position */
<> 144:ef7eb2e8f9f7 14604 #define EPWM_DTCTL_DTEN4_Msk (0x1ul << EPWM_DTCTL_DTEN4_Pos) /*!< EPWM DTCTL: DTEN4 Mask */
<> 144:ef7eb2e8f9f7 14605
<> 144:ef7eb2e8f9f7 14606 #define EPWM_BRKOUT_BRKOUT_Pos (0) /*!< EPWM BRKOUT: BRKOUT Position */
<> 144:ef7eb2e8f9f7 14607 #define EPWM_BRKOUT_BRKOUT_Msk (0x3ful << EPWM_BRKOUT_BRKOUT_Pos) /*!< EPWM BRKOUT: BRKOUT Mask */
<> 144:ef7eb2e8f9f7 14608
<> 144:ef7eb2e8f9f7 14609 #define EPWM_NPCTL_NEGPOLAR_Pos (0) /*!< EPWM NPCTL: NEGPOLAR Position */
<> 144:ef7eb2e8f9f7 14610 #define EPWM_NPCTL_NEGPOLAR_Msk (0x3ful << EPWM_NPCTL_NEGPOLAR_Pos) /*!< EPWM NPCTL: NEGPOLAR Mask */
<> 144:ef7eb2e8f9f7 14611
<> 144:ef7eb2e8f9f7 14612 #define EPWM_ASYMCTL_ASYMEN_Pos (0) /*!< EPWM ASYMCTL: ASYMEN Position */
<> 144:ef7eb2e8f9f7 14613 #define EPWM_ASYMCTL_ASYMEN_Msk (0x1ul << EPWM_ASYMCTL_ASYMEN_Pos) /*!< EPWM ASYMCTL: ASYMEN Mask */
<> 144:ef7eb2e8f9f7 14614
<> 144:ef7eb2e8f9f7 14615 #define EPWM_ASYMCTL_ASYMMODE0_Pos (8) /*!< EPWM ASYMCTL: ASYMMODE0 Position */
<> 144:ef7eb2e8f9f7 14616 #define EPWM_ASYMCTL_ASYMMODE0_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE0_Pos) /*!< EPWM ASYMCTL: ASYMMODE0 Mask */
<> 144:ef7eb2e8f9f7 14617
<> 144:ef7eb2e8f9f7 14618 #define EPWM_ASYMCTL_ASYMMODE2_Pos (16) /*!< EPWM ASYMCTL: ASYMMODE2 Position */
<> 144:ef7eb2e8f9f7 14619 #define EPWM_ASYMCTL_ASYMMODE2_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE2_Pos) /*!< EPWM ASYMCTL: ASYMMODE2 Mask */
<> 144:ef7eb2e8f9f7 14620
<> 144:ef7eb2e8f9f7 14621 #define EPWM_ASYMCTL_ASYMMODE4_Pos (24) /*!< EPWM ASYMCTL: ASYMMODE4 Position */
<> 144:ef7eb2e8f9f7 14622 #define EPWM_ASYMCTL_ASYMMODE4_Msk (0x3ul << EPWM_ASYMCTL_ASYMMODE4_Pos) /*!< EPWM ASYMCTL: ASYMMODE4 Mask */
<> 144:ef7eb2e8f9f7 14623
<> 144:ef7eb2e8f9f7 14624 #define EPWM_PERIODCNT_PERIODCNT_Pos (0) /*!< EPWM PERIODCNT: PERIODCNT Position */
<> 144:ef7eb2e8f9f7 14625 #define EPWM_PERIODCNT_PERIODCNT_Msk (0xful << EPWM_PERIODCNT_PERIODCNT_Pos) /*!< EPWM PERIODCNT: PERIODCNT Mask */
<> 144:ef7eb2e8f9f7 14626
<> 144:ef7eb2e8f9f7 14627 #define EPWM_EINTCTL_EDGEIEN0_Pos (0) /*!< EPWM EINTCTL: EDGEIEN0 Position */
<> 144:ef7eb2e8f9f7 14628 #define EPWM_EINTCTL_EDGEIEN0_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN0_Pos) /*!< EPWM EINTCTL: EDGEIEN0 Mask */
<> 144:ef7eb2e8f9f7 14629
<> 144:ef7eb2e8f9f7 14630 #define EPWM_EINTCTL_EDGEIEN2_Pos (1) /*!< EPWM EINTCTL: EDGEIEN2 Position */
<> 144:ef7eb2e8f9f7 14631 #define EPWM_EINTCTL_EDGEIEN2_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN2_Pos) /*!< EPWM EINTCTL: EDGEIEN2 Mask */
<> 144:ef7eb2e8f9f7 14632
<> 144:ef7eb2e8f9f7 14633 #define EPWM_EINTCTL_EDGEIEN4_Pos (2) /*!< EPWM EINTCTL: EDGEIEN4 Position */
<> 144:ef7eb2e8f9f7 14634 #define EPWM_EINTCTL_EDGEIEN4_Msk (0x1ul << EPWM_EINTCTL_EDGEIEN4_Pos) /*!< EPWM EINTCTL: EDGEIEN4 Mask */
<> 144:ef7eb2e8f9f7 14635
<> 144:ef7eb2e8f9f7 14636 #define EPWM_EINTCTL_EINTTYPE0_Pos (8) /*!< EPWM EINTCTL: EINTTYPE0 Position */
<> 144:ef7eb2e8f9f7 14637 #define EPWM_EINTCTL_EINTTYPE0_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE0_Pos) /*!< EPWM EINTCTL: EINTTYPE0 Mask */
<> 144:ef7eb2e8f9f7 14638
<> 144:ef7eb2e8f9f7 14639 #define EPWM_EINTCTL_EINTTYPE2_Pos (9) /*!< EPWM EINTCTL: EINTTYPE2 Position */
<> 144:ef7eb2e8f9f7 14640 #define EPWM_EINTCTL_EINTTYPE2_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE2_Pos) /*!< EPWM EINTCTL: EINTTYPE2 Mask */
<> 144:ef7eb2e8f9f7 14641
<> 144:ef7eb2e8f9f7 14642 #define EPWM_EINTCTL_EINTTYPE4_Pos (10) /*!< EPWM EINTCTL: EINTTYPE4 Position */
<> 144:ef7eb2e8f9f7 14643 #define EPWM_EINTCTL_EINTTYPE4_Msk (0x1ul << EPWM_EINTCTL_EINTTYPE4_Pos) /*!< EPWM EINTCTL: EINTTYPE4 Mask */
<> 144:ef7eb2e8f9f7 14644
<> 144:ef7eb2e8f9f7 14645 #define EPWM_OUTEN0_EVENOUTEN_Pos (0) /*!< EPWM OUTEN0: EVENOUTEN Position */
<> 144:ef7eb2e8f9f7 14646 #define EPWM_OUTEN0_EVENOUTEN_Msk (0x1ul << EPWM_OUTEN0_EVENOUTEN_Pos) /*!< EPWM OUTEN0: EVENOUTEN Mask */
<> 144:ef7eb2e8f9f7 14647
<> 144:ef7eb2e8f9f7 14648 #define EPWM_OUTEN0_ODDOUTEN_Pos (1) /*!< EPWM OUTEN0: ODDOUTEN Position */
<> 144:ef7eb2e8f9f7 14649 #define EPWM_OUTEN0_ODDOUTEN_Msk (0x1ul << EPWM_OUTEN0_ODDOUTEN_Pos) /*!< EPWM OUTEN0: ODDOUTEN Mask */
<> 144:ef7eb2e8f9f7 14650
<> 144:ef7eb2e8f9f7 14651 /**@}*/ /* EPWM_CONST */
<> 144:ef7eb2e8f9f7 14652 /**@}*/ /* end of EPWM register group */
<> 144:ef7eb2e8f9f7 14653
<> 144:ef7eb2e8f9f7 14654
<> 144:ef7eb2e8f9f7 14655 /*---------------------- Flash Memory Controller -------------------------*/
<> 144:ef7eb2e8f9f7 14656 /**
<> 144:ef7eb2e8f9f7 14657 @addtogroup FMC Flash Memory Controller(FMC)
<> 144:ef7eb2e8f9f7 14658 Memory Mapped Structure for FMC Controller
<> 144:ef7eb2e8f9f7 14659 @{ */
<> 144:ef7eb2e8f9f7 14660
<> 144:ef7eb2e8f9f7 14661 typedef struct {
<> 144:ef7eb2e8f9f7 14662 /**
<> 144:ef7eb2e8f9f7 14663 * ISPCTL
<> 144:ef7eb2e8f9f7 14664 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14665 * Offset: 0x00 ISP Control Register
<> 144:ef7eb2e8f9f7 14666 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14667 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14668 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14669 * |[0] |ISPEN |ISP Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 14670 * | | |ISP function enable bit. Set this bit to enable ISP function.
<> 144:ef7eb2e8f9f7 14671 * | | |0 = ISP function Disabled.
<> 144:ef7eb2e8f9f7 14672 * | | |1 = ISP function Enabled.
<> 144:ef7eb2e8f9f7 14673 * |[1] |BS |Boot Select (Write Protect)
<> 144:ef7eb2e8f9f7 14674 * | | |Set/clear this bit to select next booting from LDROM/APROM, respectively.
<> 144:ef7eb2e8f9f7 14675 * | | |This bit also functions as chip booting status flag, which can be used to check where chip booted from.
<> 144:ef7eb2e8f9f7 14676 * | | |This bit is initiated with the inversed value of CBS in Config0 after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened.
<> 144:ef7eb2e8f9f7 14677 * | | |0 = Boot from APROM.
<> 144:ef7eb2e8f9f7 14678 * | | |1 = Boot from LDROM.
<> 144:ef7eb2e8f9f7 14679 * |[3] |APUEN |APROM Update Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 14680 * | | |0 = APROM cannot be updated when the chip runs in APROM.
<> 144:ef7eb2e8f9f7 14681 * | | |1 = APROM can be updated when the chip runs in APROM.
<> 144:ef7eb2e8f9f7 14682 * |[4] |CFGUEN |Config-Bits Update By ISP (Write Protect) Enable Control
<> 144:ef7eb2e8f9f7 14683 * | | |0 = ISP Disabled to update config-bits.
<> 144:ef7eb2e8f9f7 14684 * | | |1 = ISP Enabled to update config-bits at KEYMATCH flag active (bit7 of ISPSTS).
<> 144:ef7eb2e8f9f7 14685 * | | |Note: This bit is fixed to 0 in Secure mode.
<> 144:ef7eb2e8f9f7 14686 * |[5] |LDUEN |LDROM Update Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 14687 * | | |LDROM update enable bit.
<> 144:ef7eb2e8f9f7 14688 * | | |0 = LDROM cannot be updated.
<> 144:ef7eb2e8f9f7 14689 * | | |1 = LDROM can be updated at KEYMATCH flag active (bit7 of ISPSTS).
<> 144:ef7eb2e8f9f7 14690 * | | |Note: This bit is fixed to 0 in Secure mode.
<> 144:ef7eb2e8f9f7 14691 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
<> 144:ef7eb2e8f9f7 14692 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
<> 144:ef7eb2e8f9f7 14693 * | | |(1) APROM writes to itself if APUEN is set to 0.
<> 144:ef7eb2e8f9f7 14694 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
<> 144:ef7eb2e8f9f7 14695 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
<> 144:ef7eb2e8f9f7 14696 * | | |(4) Destination address is illegal, such as over an available range.
<> 144:ef7eb2e8f9f7 14697 * | | |Note: This bit needs to be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14698 */
<> 144:ef7eb2e8f9f7 14699 __IO uint32_t ISPCTL;
<> 144:ef7eb2e8f9f7 14700
<> 144:ef7eb2e8f9f7 14701 /**
<> 144:ef7eb2e8f9f7 14702 * ISPADDR
<> 144:ef7eb2e8f9f7 14703 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14704 * Offset: 0x04 ISP Address Register
<> 144:ef7eb2e8f9f7 14705 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14706 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14707 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14708 * |[0:31] |ISPADR |ISP Address
<> 144:ef7eb2e8f9f7 14709 * | | |The NUC442/NUC472 series is equipped with an embedded flash and supports word program only.
<> 144:ef7eb2e8f9f7 14710 * | | |ISPADR[1:0] must be kept 00b for ISP operation.
<> 144:ef7eb2e8f9f7 14711 */
<> 144:ef7eb2e8f9f7 14712 __IO uint32_t ISPADDR;
<> 144:ef7eb2e8f9f7 14713
<> 144:ef7eb2e8f9f7 14714 /**
<> 144:ef7eb2e8f9f7 14715 * ISPDAT
<> 144:ef7eb2e8f9f7 14716 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14717 * Offset: 0x08 ISP Data Register
<> 144:ef7eb2e8f9f7 14718 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14719 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14720 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14721 * |[0:31] |ISPDAT |ISP Data
<> 144:ef7eb2e8f9f7 14722 * | | |Write data to this register before ISP program operation.
<> 144:ef7eb2e8f9f7 14723 * | | |Read data from this register after ISP read operation.
<> 144:ef7eb2e8f9f7 14724 */
<> 144:ef7eb2e8f9f7 14725 __IO uint32_t ISPDAT;
<> 144:ef7eb2e8f9f7 14726
<> 144:ef7eb2e8f9f7 14727 /**
<> 144:ef7eb2e8f9f7 14728 * ISPCMD
<> 144:ef7eb2e8f9f7 14729 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14730 * Offset: 0x0C ISP Command Register
<> 144:ef7eb2e8f9f7 14731 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14732 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14733 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14734 * |[0:5] |CMD |ISP Command
<> 144:ef7eb2e8f9f7 14735 * | | |Please check the table below for ISP commands.
<> 144:ef7eb2e8f9f7 14736 */
<> 144:ef7eb2e8f9f7 14737 __IO uint32_t ISPCMD;
<> 144:ef7eb2e8f9f7 14738
<> 144:ef7eb2e8f9f7 14739 /**
<> 144:ef7eb2e8f9f7 14740 * ISPTRG
<> 144:ef7eb2e8f9f7 14741 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14742 * Offset: 0x10 ISP Trigger Register
<> 144:ef7eb2e8f9f7 14743 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14744 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14745 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14746 * |[0] |ISPGO |ISP Start Trigger
<> 144:ef7eb2e8f9f7 14747 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished.
<> 144:ef7eb2e8f9f7 14748 * | | |0 = ISP operation is finished.
<> 144:ef7eb2e8f9f7 14749 * | | |1 = ISP is progressed.
<> 144:ef7eb2e8f9f7 14750 * | | |This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 14751 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 14752 */
<> 144:ef7eb2e8f9f7 14753 __IO uint32_t ISPTRG;
<> 144:ef7eb2e8f9f7 14754
<> 144:ef7eb2e8f9f7 14755 /**
<> 144:ef7eb2e8f9f7 14756 * DFBA
<> 144:ef7eb2e8f9f7 14757 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14758 * Offset: 0x14 Data Flash Base Address
<> 144:ef7eb2e8f9f7 14759 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14760 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14761 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14762 * |[0:31] |DFBA |Data Flash Base Address
<> 144:ef7eb2e8f9f7 14763 * | | |This register indicates data flash start address. It is a read only register.
<> 144:ef7eb2e8f9f7 14764 * | | |The data flash is shared with APROM and data flash size is defined by user configuration and the content of this register is loaded from Config1.
<> 144:ef7eb2e8f9f7 14765 */
<> 144:ef7eb2e8f9f7 14766 __I uint32_t DFBA;
<> 144:ef7eb2e8f9f7 14767
<> 144:ef7eb2e8f9f7 14768 /**
<> 144:ef7eb2e8f9f7 14769 * FTCTL
<> 144:ef7eb2e8f9f7 14770 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14771 * Offset: 0x18 Flash Access Time Control Register
<> 144:ef7eb2e8f9f7 14772 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14773 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14774 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14775 * |[4:6] |FOM |Frequency Optimization Mode (Write Protect)
<> 144:ef7eb2e8f9f7 14776 * | | |When chip operation frequency is lower, chip can work more efficiently by setting FOM bits
<> 144:ef7eb2e8f9f7 14777 * | | |FOM[2:0]
<> 144:ef7eb2e8f9f7 14778 * | | |Optimized Frequency (OF)
<> 144:ef7eb2e8f9f7 14779 * | | |001
<> 144:ef7eb2e8f9f7 14780 * | | |0 MHz < OF <= 24 MHz
<> 144:ef7eb2e8f9f7 14781 * | | |010
<> 144:ef7eb2e8f9f7 14782 * | | |24 MHz < OF <= 48 MHz
<> 144:ef7eb2e8f9f7 14783 * | | |011
<> 144:ef7eb2e8f9f7 14784 * | | |48 MHz < OF <= 72 MHz
<> 144:ef7eb2e8f9f7 14785 * | | |others
<> 144:ef7eb2e8f9f7 14786 * | | |Reserved
<> 144:ef7eb2e8f9f7 14787 */
<> 144:ef7eb2e8f9f7 14788 __IO uint32_t FTCTL;
<> 144:ef7eb2e8f9f7 14789 uint32_t RESERVE0[9];
<> 144:ef7eb2e8f9f7 14790
<> 144:ef7eb2e8f9f7 14791 /**
<> 144:ef7eb2e8f9f7 14792 * ISPSTS
<> 144:ef7eb2e8f9f7 14793 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14794 * Offset: 0x40 Flash Access Time Control Register
<> 144:ef7eb2e8f9f7 14795 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14796 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14797 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14798 * |[0] |ISPBUSY |ISP busy flag
<> 144:ef7eb2e8f9f7 14799 * | | |0 = ISP operation is finished.
<> 144:ef7eb2e8f9f7 14800 * | | |1 = ISP is progressed.
<> 144:ef7eb2e8f9f7 14801 * |[2:1] |CBS |Chip boot selection mode
<> 144:ef7eb2e8f9f7 14802 * | | |This CBS field is just a copy of User-Configuration Config0 CBS[7:6].
<> 144:ef7eb2e8f9f7 14803 * |[6] |ISPFF |ISP Fail Flag (Write Protect)
<> 144:ef7eb2e8f9f7 14804 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
<> 144:ef7eb2e8f9f7 14805 * | | |(1) APROM writes to itself if APUEN is set to 0.
<> 144:ef7eb2e8f9f7 14806 * | | |(2) LDROM writes to itself if LDUEN is set to 0.
<> 144:ef7eb2e8f9f7 14807 * | | |(3) CONFIG is erased/programmed if CFGUEN is set to 0.
<> 144:ef7eb2e8f9f7 14808 * | | |(4) Destination address is illegal, such as over an available range.
<> 144:ef7eb2e8f9f7 14809 * | | |Note: This bit needs to be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 14810 * |[20:9] |VECMAP |Vector Page Mapping Address (Read Only)
<> 144:ef7eb2e8f9f7 14811 * | | |The current flash address space 0x0000_0000~0x0000_07FF is mapping to
<> 144:ef7eb2e8f9f7 14812 * | | |address {VECMAP[11:2], 11¡¦h000} ~ {VECMAP[11:2], 11¡¦h7FF}
<> 144:ef7eb2e8f9f7 14813 * | | |VECMAP[1:0] is needed to set 0.
<> 144:ef7eb2e8f9f7 14814 * |[26] |CFGCRCF |User-Configuration CRC Check Flag (Read Only)
<> 144:ef7eb2e8f9f7 14815 * | | |This bit is set by hardware when detecting CONFIG CRC checksum is error
<> 144:ef7eb2e8f9f7 14816 * | | |0 = CONFIG CRC checksum is OK.
<> 144:ef7eb2e8f9f7 14817 * | | |1 = CONFIG CRC checksum error and force chip into LOCK mode.
<> 144:ef7eb2e8f9f7 14818 */
<> 144:ef7eb2e8f9f7 14819 __IO uint32_t ISPSTS;
<> 144:ef7eb2e8f9f7 14820
<> 144:ef7eb2e8f9f7 14821 /**
<> 144:ef7eb2e8f9f7 14822 * FBWP
<> 144:ef7eb2e8f9f7 14823 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14824 * Offset: 0x44 Flash Block Write Protect Control Register
<> 144:ef7eb2e8f9f7 14825 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14826 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14827 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14828 * |[0:31] |BWP |Flash Block Write Protect Control
<> 144:ef7eb2e8f9f7 14829 * | | |If BWP.N bit is set to 0, the APROM memory relative region cannot program and erase by ISP. (N=0~31).
<> 144:ef7eb2e8f9f7 14830 * | | |Bit Block Protect Region
<> 144:ef7eb2e8f9f7 14831 * | | |BWP0 0x00_0000 ~ 0x00_3FFF
<> 144:ef7eb2e8f9f7 14832 * | | |BWP1 0x00_4000 ~ 0x00_7FFF
<> 144:ef7eb2e8f9f7 14833 * | | |BWP2 0x00_8000 ~ 0x00_BFFF
<> 144:ef7eb2e8f9f7 14834 * | | |BWP3 0x00_C000 ~ 0x00_FFFF
<> 144:ef7eb2e8f9f7 14835 * | | |BWP4 0x01_0000 ~ 0x01_3FFF
<> 144:ef7eb2e8f9f7 14836 * | | |BWP5 0x01_4000 ~ 0x01_7FFF
<> 144:ef7eb2e8f9f7 14837 * | | |BWP6 0x01_8000 ~ 0x01_BFFF
<> 144:ef7eb2e8f9f7 14838 * | | |BWP7 0x01_C000 ~ 0x01_FFFF
<> 144:ef7eb2e8f9f7 14839 * | | |BWP8 0x02_0000 ~ 0x02_3FFF
<> 144:ef7eb2e8f9f7 14840 * | | |BWP9 0x02_4000 ~ 0x02_7FFF
<> 144:ef7eb2e8f9f7 14841 * | | |BWP10 0x02_8000 ~ 0x02_BFFF
<> 144:ef7eb2e8f9f7 14842 * | | |BWP11 0x02_C000 ~ 0x02_FFFF
<> 144:ef7eb2e8f9f7 14843 * | | |BWP12 0x03_0000 ~ 0x03_3FFF
<> 144:ef7eb2e8f9f7 14844 * | | |BWP13 0x03_4000 ~ 0x03_7FFF
<> 144:ef7eb2e8f9f7 14845 * | | |BWP14 0x03_8000 ~ 0x03_BFFF
<> 144:ef7eb2e8f9f7 14846 * | | |BWP15 0x03_C000 ~ 0x03_FFFF
<> 144:ef7eb2e8f9f7 14847 * | | |BWP16 0x04_0000 ~ 0x04_3FFF
<> 144:ef7eb2e8f9f7 14848 * | | |BWP17 0x04_4000 ~ 0x04_7FFF
<> 144:ef7eb2e8f9f7 14849 * | | |BWP18 0x04_8000 ~ 0x04_BFFF
<> 144:ef7eb2e8f9f7 14850 * | | |BWP19 0x04_C000 ~ 0x04_FFFF
<> 144:ef7eb2e8f9f7 14851 * | | |BWP20 0x05_0000 ~ 0x05_3FFF
<> 144:ef7eb2e8f9f7 14852 * | | |BWP21 0x05_4000 ~ 0x05_7FFF
<> 144:ef7eb2e8f9f7 14853 * | | |BWP22 0x05_8000 ~ 0x05_BFFF
<> 144:ef7eb2e8f9f7 14854 * | | |BWP23 0x05_C000 ~ 0x05_FFFF
<> 144:ef7eb2e8f9f7 14855 * | | |BWP24 0x06_0000 ~ 0x06_3FFF
<> 144:ef7eb2e8f9f7 14856 * | | |BWP25 0x06_4000 ~ 0x06_7FFF
<> 144:ef7eb2e8f9f7 14857 * | | |BWP26 0x06_8000 ~ 0x06_BFFF
<> 144:ef7eb2e8f9f7 14858 * | | |BWP27 0x06_C000 ~ 0x06_FFFF
<> 144:ef7eb2e8f9f7 14859 * | | |BWP28 0x07_0000 ~ 0x07_3FFF
<> 144:ef7eb2e8f9f7 14860 * | | |BWP29 0x07_4000 ~ 0x07_7FFF
<> 144:ef7eb2e8f9f7 14861 * | | |BWP30 0x07_8000 ~ 0x07_BFFF
<> 144:ef7eb2e8f9f7 14862 * | | |BWP31 0x07_C000 ~ 0x07_FFFF
<> 144:ef7eb2e8f9f7 14863 * | | |This register is loaded from Config2 when chip is power on.
<> 144:ef7eb2e8f9f7 14864 * | | |It is read only, except the correct Super Key is matched.
<> 144:ef7eb2e8f9f7 14865 * | | |This register is also a protected bit which means programming this bit needs to write "59h", "16h", "88h" to address GCR_BA+0x100 to disable register protection.
<> 144:ef7eb2e8f9f7 14866 * | | |Refer to the register REGWRPROT at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 14867 */
<> 144:ef7eb2e8f9f7 14868 __IO uint32_t FBWP;
<> 144:ef7eb2e8f9f7 14869 uint32_t RESERVE1[14];
<> 144:ef7eb2e8f9f7 14870
<> 144:ef7eb2e8f9f7 14871 /**
<> 144:ef7eb2e8f9f7 14872 * MPDAT0
<> 144:ef7eb2e8f9f7 14873 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14874 * Offset: 0x80 ISP Data 0 Register
<> 144:ef7eb2e8f9f7 14875 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14876 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14877 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14878 * |[0:31] |ISPDAT0 |ISP Data 0
<> 144:ef7eb2e8f9f7 14879 * | | |This register is the first 32-bit data for 32b/64b/multi-word program,
<> 144:ef7eb2e8f9f7 14880 * | | |and it is also the mirror of FMC_ISPDAT register, both registers keep the same data.
<> 144:ef7eb2e8f9f7 14881 */
<> 144:ef7eb2e8f9f7 14882 __IO uint32_t MPDAT0;
<> 144:ef7eb2e8f9f7 14883
<> 144:ef7eb2e8f9f7 14884 /**
<> 144:ef7eb2e8f9f7 14885 * MPDAT1
<> 144:ef7eb2e8f9f7 14886 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14887 * Offset: 0x84 ISP Data 1 Register
<> 144:ef7eb2e8f9f7 14888 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14889 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14890 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14891 * |[0:31] |ISPDAT1 |ISP Data 1
<> 144:ef7eb2e8f9f7 14892 * | | |This register is the second 32-bit data for 32b/64b/multi-word program.
<> 144:ef7eb2e8f9f7 14893 */
<> 144:ef7eb2e8f9f7 14894 __IO uint32_t MPDAT1;
<> 144:ef7eb2e8f9f7 14895
<> 144:ef7eb2e8f9f7 14896 /**
<> 144:ef7eb2e8f9f7 14897 * MPDAT2
<> 144:ef7eb2e8f9f7 14898 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14899 * Offset: 0x88 ISP Data 2 Register
<> 144:ef7eb2e8f9f7 14900 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14901 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14902 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14903 * |[0:31] |ISPDAT2 |ISP Data 2
<> 144:ef7eb2e8f9f7 14904 * | | |This register is the third 32-bit data for 32b/64b/multi-word program.
<> 144:ef7eb2e8f9f7 14905 */
<> 144:ef7eb2e8f9f7 14906 __IO uint32_t MPDAT2;
<> 144:ef7eb2e8f9f7 14907
<> 144:ef7eb2e8f9f7 14908 /**
<> 144:ef7eb2e8f9f7 14909 * MPDAT3
<> 144:ef7eb2e8f9f7 14910 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14911 * Offset: 0x8C ISP Data 1 Register
<> 144:ef7eb2e8f9f7 14912 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14913 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14914 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14915 * |[0:31] |ISPDAT3 |ISP Data 3
<> 144:ef7eb2e8f9f7 14916 * | | |This register is the fourth 32-bit data for 32b/64b/multi-word program.
<> 144:ef7eb2e8f9f7 14917 */
<> 144:ef7eb2e8f9f7 14918 __IO uint32_t MPDAT3;
<> 144:ef7eb2e8f9f7 14919
<> 144:ef7eb2e8f9f7 14920 uint32_t RESERVE2[12];
<> 144:ef7eb2e8f9f7 14921
<> 144:ef7eb2e8f9f7 14922 /**
<> 144:ef7eb2e8f9f7 14923 * MPSTS
<> 144:ef7eb2e8f9f7 14924 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14925 * Offset: 0xC0 ISP Multi-Word Program Status Register
<> 144:ef7eb2e8f9f7 14926 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14927 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14928 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14929 * |[0] |MPBUSY |ISP Multi-Word Program Busy Flag (Read Only)
<> 144:ef7eb2e8f9f7 14930 * | | |0 = ISP Multi-Word Program operation is aborted or finished.
<> 144:ef7eb2e8f9f7 14931 * | | |1 = ISP Multi-Word Program operation is progressed.
<> 144:ef7eb2e8f9f7 14932 * |[2] |ISPFF |ISP Fail Flag (Read Only)
<> 144:ef7eb2e8f9f7 14933 * | | |This CBS field is just a copy of User-Configuration Config0 CBS[7:6].
<> 144:ef7eb2e8f9f7 14934 * |[4] |D0 |ISP DATA 0 Flag (Read Only)
<> 144:ef7eb2e8f9f7 14935 * | | |This bit is set when FMC_MPDAT0 is written and auto-clear to 0
<> 144:ef7eb2e8f9f7 14936 * | | |when the FMC_MPDAT0 is programmed to flash complete.
<> 144:ef7eb2e8f9f7 14937 * | | |0 = FMC_MPDAT0 register is empty, or program to flash complete.
<> 144:ef7eb2e8f9f7 14938 * | | |1 = FMC_MPDAT0 register has been written, and not programmed to flash yet.
<> 144:ef7eb2e8f9f7 14939 * |[5] |D1 |ISP DATA 1 Flag (Read Only)
<> 144:ef7eb2e8f9f7 14940 * | | |This bit is set when FMC_MPDAT1 is written and auto-clear to 0
<> 144:ef7eb2e8f9f7 14941 * | | |when the FMC_MPDAT1 is programmed to flash complete.
<> 144:ef7eb2e8f9f7 14942 * | | |0 = FMC_MPDAT1 register is empty, or program to flash complete.
<> 144:ef7eb2e8f9f7 14943 * | | |1 = FMC_MPDAT1 register has been written, and not programmed to flash yet.
<> 144:ef7eb2e8f9f7 14944 * |[6] |D2 |ISP DATA 2 Flag (Read Only)
<> 144:ef7eb2e8f9f7 14945 * | | |This bit is set when FMC_MPDAT2 is written and auto-clear to 0
<> 144:ef7eb2e8f9f7 14946 * | | |when the FMC_MPDAT2 is programmed to flash complete.
<> 144:ef7eb2e8f9f7 14947 * | | |0 = FMC_MPDAT2 register is empty, or program to flash complete.
<> 144:ef7eb2e8f9f7 14948 * | | |1 = FMC_MPDAT2 register has been written, and not programmed to flash yet.
<> 144:ef7eb2e8f9f7 14949 * |[7] |D3 |ISP DATA 3 Flag (Read Only)
<> 144:ef7eb2e8f9f7 14950 * | | |This bit is set when FMC_MPDAT3 is written and auto-clear to 0
<> 144:ef7eb2e8f9f7 14951 * | | |when the FMC_MPDAT3 is programmed to flash complete.
<> 144:ef7eb2e8f9f7 14952 * | | |0 = FMC_MPDAT3 register is empty, or program to flash complete.
<> 144:ef7eb2e8f9f7 14953 * | | |1 = FMC_MPDAT3 register has been written, and not programmed to flash yet.
<> 144:ef7eb2e8f9f7 14954 */
<> 144:ef7eb2e8f9f7 14955 __IO uint32_t MPSTS;
<> 144:ef7eb2e8f9f7 14956
<> 144:ef7eb2e8f9f7 14957 /**
<> 144:ef7eb2e8f9f7 14958 * MPADDR
<> 144:ef7eb2e8f9f7 14959 * ===================================================================================================
<> 144:ef7eb2e8f9f7 14960 * Offset: 0xC4 ISP Multi-Word Program Address Status Register
<> 144:ef7eb2e8f9f7 14961 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 14962 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 14963 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 14964 * |[0:31] |MPADDR |ISP Multi-Word Program Address Status
<> 144:ef7eb2e8f9f7 14965 * | | |MPADDR is the address of ISP Multi-Word Program operation when
<> 144:ef7eb2e8f9f7 14966 * | | |MPBUSY flag is 1. MPADDR will keep the final address when
<> 144:ef7eb2e8f9f7 14967 * | | |Multi-Word Program is aborted or finished.
<> 144:ef7eb2e8f9f7 14968 */
<> 144:ef7eb2e8f9f7 14969 __IO uint32_t MPADDR;
<> 144:ef7eb2e8f9f7 14970
<> 144:ef7eb2e8f9f7 14971 } FMC_T;
<> 144:ef7eb2e8f9f7 14972
<> 144:ef7eb2e8f9f7 14973
<> 144:ef7eb2e8f9f7 14974 /**
<> 144:ef7eb2e8f9f7 14975 @addtogroup FMC_CONST FMC Bit Field Definition
<> 144:ef7eb2e8f9f7 14976 Constant Definitions for FMC Controller
<> 144:ef7eb2e8f9f7 14977 @{ */
<> 144:ef7eb2e8f9f7 14978
<> 144:ef7eb2e8f9f7 14979 #define FMC_ISPCTL_ISPEN_Pos (0) /*!< FMC ISPCTL: ISPEN Position */
<> 144:ef7eb2e8f9f7 14980 #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) /*!< FMC ISPCTL: ISPEN Mask */
<> 144:ef7eb2e8f9f7 14981
<> 144:ef7eb2e8f9f7 14982 #define FMC_ISPCTL_BS_Pos (1) /*!< FMC ISPCTL: BS Position */
<> 144:ef7eb2e8f9f7 14983 #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) /*!< FMC ISPCTL: BS Mask */
<> 144:ef7eb2e8f9f7 14984
<> 144:ef7eb2e8f9f7 14985 #define FMC_ISPCTL_APUEN_Pos (3) /*!< FMC ISPCTL: APUEN Position */
<> 144:ef7eb2e8f9f7 14986 #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) /*!< FMC ISPCTL: APUEN Mask */
<> 144:ef7eb2e8f9f7 14987
<> 144:ef7eb2e8f9f7 14988 #define FMC_ISPCTL_CFGUEN_Pos (4) /*!< FMC ISPCTL: CFGUEN Position */
<> 144:ef7eb2e8f9f7 14989 #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) /*!< FMC ISPCTL: CFGUEN Mask */
<> 144:ef7eb2e8f9f7 14990
<> 144:ef7eb2e8f9f7 14991 #define FMC_ISPCTL_LDUEN_Pos (5) /*!< FMC ISPCTL: LDUEN Position */
<> 144:ef7eb2e8f9f7 14992 #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) /*!< FMC ISPCTL: LDUEN Mask */
<> 144:ef7eb2e8f9f7 14993
<> 144:ef7eb2e8f9f7 14994 #define FMC_ISPCTL_ISPFF_Pos (6) /*!< FMC ISPCTL: ISPFF Position */
<> 144:ef7eb2e8f9f7 14995 #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) /*!< FMC ISPCTL: ISPFF Mask */
<> 144:ef7eb2e8f9f7 14996
<> 144:ef7eb2e8f9f7 14997 #define FMC_ISPADDR_ISPADDR_Pos (0) /*!< FMC ISPADDR: ISPADDR Position */
<> 144:ef7eb2e8f9f7 14998 #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) /*!< FMC ISPADDR: ISPADDR Mask */
<> 144:ef7eb2e8f9f7 14999
<> 144:ef7eb2e8f9f7 15000 #define FMC_ISPDAT_ISPDAT_Pos (0) /*!< FMC ISPDAT: ISPDAT Position */
<> 144:ef7eb2e8f9f7 15001 #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC ISPDAT: ISPDAT Mask */
<> 144:ef7eb2e8f9f7 15002
<> 144:ef7eb2e8f9f7 15003 #define FMC_ISPCMD_CMD_Pos (0) /*!< FMC ISPCMD: CMD Position */
<> 144:ef7eb2e8f9f7 15004 #define FMC_ISPCMD_CMD_Msk (0x3ful << FMC_ISPCMD_CMD_Pos) /*!< FMC ISPCMD: CMD Mask */
<> 144:ef7eb2e8f9f7 15005
<> 144:ef7eb2e8f9f7 15006 #define FMC_ISPTRG_ISPGO_Pos (0) /*!< FMC ISPTRG: ISPGO Position */
<> 144:ef7eb2e8f9f7 15007 #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC ISPTRG: ISPGO Mask */
<> 144:ef7eb2e8f9f7 15008
<> 144:ef7eb2e8f9f7 15009 #define FMC_DFBA_DFBA_Pos (0) /*!< FMC DFBA: DFBA Position */
<> 144:ef7eb2e8f9f7 15010 #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) /*!< FMC DFBA: DFBA Mask */
<> 144:ef7eb2e8f9f7 15011
<> 144:ef7eb2e8f9f7 15012 #define FMC_FTCTL_FOM_Pos (4) /*!< FMC FTCTL: FOM Position */
<> 144:ef7eb2e8f9f7 15013 #define FMC_FTCTL_FOM_Msk (0x7ul << FMC_FTCTL_FOM_Pos) /*!< FMC FTCTL: FOM Mask */
<> 144:ef7eb2e8f9f7 15014
<> 144:ef7eb2e8f9f7 15015 #define FMC_ISPSTS_ISPBUSY_Pos (0) /*!< FMC ISPSTS: ISPBUSY Position */
<> 144:ef7eb2e8f9f7 15016 #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) /*!< FMC ISPSTS: ISPBUSY Mask */
<> 144:ef7eb2e8f9f7 15017
<> 144:ef7eb2e8f9f7 15018 #define FMC_ISPSTS_CBS_Pos (1) /*!< FMC ISPSTS: CBS Position */
<> 144:ef7eb2e8f9f7 15019 #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) /*!< FMC ISPSTS: CBS Mask */
<> 144:ef7eb2e8f9f7 15020
<> 144:ef7eb2e8f9f7 15021 #define FMC_ISPSTS_ISPFF_Pos (6) /*!< FMC ISPSTS: ISPFF Position */
<> 144:ef7eb2e8f9f7 15022 #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) /*!< FMC ISPSTS: ISPFF Mask */
<> 144:ef7eb2e8f9f7 15023
<> 144:ef7eb2e8f9f7 15024 #define FMC_ISPSTS_VECMAP_Pos (9) /*!< FMC ISPSTS: VECMAP Position */
<> 144:ef7eb2e8f9f7 15025 #define FMC_ISPSTS_VECMAP_Msk (0xffful << FMC_ISPSTS_VECMAP_Pos) /*!< FMC ISPSTS: VECMAP Mask */
<> 144:ef7eb2e8f9f7 15026
<> 144:ef7eb2e8f9f7 15027 #define FMC_ISPSTS_CFGCRCF_Pos (26) /*!< FMC ISPSTS: CFGCRCF Position */
<> 144:ef7eb2e8f9f7 15028 #define FMC_ISPSTS_CFGCRCF_Msk (0x1ul << FMC_ISPSTS_CFGCRCF_Pos) /*!< FMC ISPSTS: CFGCRCF Mask */
<> 144:ef7eb2e8f9f7 15029
<> 144:ef7eb2e8f9f7 15030 #define FMC_FBWP_BWP_Pos (0) /*!< FMC FBWP: BWP Position */
<> 144:ef7eb2e8f9f7 15031 #define FMC_FBWP_BWP_Msk (0xfffffffful << FMC_FBWP_BWP_Pos) /*!< FMC FBWP: BWP Mask */
<> 144:ef7eb2e8f9f7 15032
<> 144:ef7eb2e8f9f7 15033 #define FMC_MPDAT0_ISPDAT0_Pos (0) /*!< FMC MPDAT0: ISPDAT0 Position */
<> 144:ef7eb2e8f9f7 15034 #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) /*!< FMC MPDAT0: ISPDAT0 Mask */
<> 144:ef7eb2e8f9f7 15035
<> 144:ef7eb2e8f9f7 15036 #define FMC_MPDAT1_ISPDAT1_Pos (0) /*!< FMC MPDAT1: ISPDAT1 Position */
<> 144:ef7eb2e8f9f7 15037 #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) /*!< FMC MPDAT1: ISPDAT1 Mask */
<> 144:ef7eb2e8f9f7 15038
<> 144:ef7eb2e8f9f7 15039 #define FMC_MPDAT2_ISPDAT2_Pos (0) /*!< FMC MPDAT2: ISPDAT2 Position */
<> 144:ef7eb2e8f9f7 15040 #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) /*!< FMC MPDAT2: ISPDAT2 Mask */
<> 144:ef7eb2e8f9f7 15041
<> 144:ef7eb2e8f9f7 15042 #define FMC_MPDAT3_ISPDAT3_Pos (0) /*!< FMC MPDAT3: ISPDAT3 Position */
<> 144:ef7eb2e8f9f7 15043 #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) /*!< FMC MPDAT3: ISPDAT3 Mask */
<> 144:ef7eb2e8f9f7 15044
<> 144:ef7eb2e8f9f7 15045 #define FMC_MPSTS_MPBUSY_Pos (0) /*!< FMC MPSTS: WMPBUSY Position */
<> 144:ef7eb2e8f9f7 15046 #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) /*!< FMC MPSTS: MPBUSY Mask */
<> 144:ef7eb2e8f9f7 15047
<> 144:ef7eb2e8f9f7 15048 #define FMC_MPSTS_ISPFF_Pos (2) /*!< FMC MPSTS: ISPFF Position */
<> 144:ef7eb2e8f9f7 15049 #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) /*!< FMC MPSTS: ISPFF Mask */
<> 144:ef7eb2e8f9f7 15050
<> 144:ef7eb2e8f9f7 15051 #define FMC_MPSTS_D0_Pos (4) /*!< FMC MPSTS: D0 Position */
<> 144:ef7eb2e8f9f7 15052 #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) /*!< FMC MPSTS: D0 Mask */
<> 144:ef7eb2e8f9f7 15053
<> 144:ef7eb2e8f9f7 15054 #define FMC_MPSTS_D1_Pos (5) /*!< FMC MPSTS: D1 Position */
<> 144:ef7eb2e8f9f7 15055 #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) /*!< FMC MPSTS: D1 Mask */
<> 144:ef7eb2e8f9f7 15056
<> 144:ef7eb2e8f9f7 15057 #define FMC_MPSTS_D2_Pos (6) /*!< FMC MPSTS: D2 Position */
<> 144:ef7eb2e8f9f7 15058 #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) /*!< FMC MPSTS: D2 Mask */
<> 144:ef7eb2e8f9f7 15059
<> 144:ef7eb2e8f9f7 15060 #define FMC_MPSTS_D3_Pos (7) /*!< FMC MPSTS: D3 Position */
<> 144:ef7eb2e8f9f7 15061 #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) /*!< FMC MPSTS: D3 Mask */
<> 144:ef7eb2e8f9f7 15062
<> 144:ef7eb2e8f9f7 15063 #define FMC_MPADDR_MPADDR_Pos (0) /*!< FMC MPADDR: MPADDR Position */
<> 144:ef7eb2e8f9f7 15064 #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) /*!< FMC MPADDR: MPADDR Mask */
<> 144:ef7eb2e8f9f7 15065
<> 144:ef7eb2e8f9f7 15066 /**@}*/ /* FMC_CONST */
<> 144:ef7eb2e8f9f7 15067 /**@}*/ /* end of FMC register group */
<> 144:ef7eb2e8f9f7 15068
<> 144:ef7eb2e8f9f7 15069
<> 144:ef7eb2e8f9f7 15070 /*---------------------- General Purpose Input/Output Controller -------------------------*/
<> 144:ef7eb2e8f9f7 15071 /**
<> 144:ef7eb2e8f9f7 15072 @addtogroup GPIO General Purpose Input/Output Controller(GPIO)
<> 144:ef7eb2e8f9f7 15073 Memory Mapped Structure for GPIO Controller
<> 144:ef7eb2e8f9f7 15074 @{ */
<> 144:ef7eb2e8f9f7 15075
<> 144:ef7eb2e8f9f7 15076 typedef struct {
<> 144:ef7eb2e8f9f7 15077
<> 144:ef7eb2e8f9f7 15078
<> 144:ef7eb2e8f9f7 15079 /**
<> 144:ef7eb2e8f9f7 15080 * Px_MODE
<> 144:ef7eb2e8f9f7 15081 * ===================================================================================================
<> 144:ef7eb2e8f9f7 15082 * Offset: 0x00 Px I/O Mode Control
<> 144:ef7eb2e8f9f7 15083 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15084 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 15085 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 15086 * |[0:1] |MODE0 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15087 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15088 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15089 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15090 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15091 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15092 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15093 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15094 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15095 * |[2:3] |MODE1 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15096 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15097 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15098 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15099 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15100 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15101 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15102 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15103 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15104 * |[4:5] |MODE2 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15105 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15106 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15107 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15108 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15109 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15110 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15111 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15112 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15113 * |[6:7] |MODE3 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15114 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15115 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15116 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15117 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15118 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15119 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15120 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15121 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15122 * |[8:9] |MODE4 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15123 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15124 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15125 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15126 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15127 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15128 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15129 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15130 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15131 * |[10:11] |MODE5 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15132 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15133 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15134 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15135 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15136 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15137 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15138 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15139 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15140 * |[12:13] |MODE6 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15141 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15142 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15143 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15144 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15145 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15146 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15147 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15148 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15149 * |[14:15] |MODE7 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15150 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15151 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15152 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15153 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15154 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15155 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15156 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15157 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15158 * |[16:17] |MODE8 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15159 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15160 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15161 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15162 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15163 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15164 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15165 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15166 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15167 * |[18:19] |MODE9 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15168 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15169 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15170 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15171 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15172 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15173 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15174 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15175 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15176 * |[20:21] |MODE10 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15177 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15178 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15179 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15180 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15181 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15182 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15183 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15184 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15185 * |[22:23] |MODE11 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15186 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15187 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15188 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15189 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15190 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15191 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15192 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15193 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15194 * |[24:25] |MODE12 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15195 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15196 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15197 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15198 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15199 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15200 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15201 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15202 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15203 * |[26:27] |MODE13 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15204 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15205 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15206 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15207 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15208 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15209 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15210 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15211 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15212 * |[28:29] |MODE14 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15213 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15214 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15215 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15216 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15217 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15218 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15219 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15220 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15221 * |[30:31] |MODE15 |Port N Bit M I/O Mode Control
<> 144:ef7eb2e8f9f7 15222 * | | |Determine the I/O mode of port n bit m.
<> 144:ef7eb2e8f9f7 15223 * | | |00 = INPUT only mode.
<> 144:ef7eb2e8f9f7 15224 * | | |01 = OUTPUT mode.
<> 144:ef7eb2e8f9f7 15225 * | | |10 = Open-drain mode.
<> 144:ef7eb2e8f9f7 15226 * | | |11 = Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15227 * | | |Reset value:
<> 144:ef7eb2e8f9f7 15228 * | | |0xFFFF_FFFF when ( cfg_io =1'b0).
<> 144:ef7eb2e8f9f7 15229 * | | |0x0000_00000 when ( cfg_io =1'b1).
<> 144:ef7eb2e8f9f7 15230 */
<> 144:ef7eb2e8f9f7 15231 __IO uint32_t MODE;
<> 144:ef7eb2e8f9f7 15232
<> 144:ef7eb2e8f9f7 15233 /**
<> 144:ef7eb2e8f9f7 15234 * Px_DINOFF
<> 144:ef7eb2e8f9f7 15235 * ===================================================================================================
<> 144:ef7eb2e8f9f7 15236 * Offset: 0x04 Px Digital Input Path Disable Control
<> 144:ef7eb2e8f9f7 15237 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15238 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 15239 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 15240 * |[16] |DINOFF0 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15241 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15242 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15243 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15244 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15245 * |[17] |DINOFF1 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15246 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15247 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15248 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15249 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15250 * |[18] |DINOFF2 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15251 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15252 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15253 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15254 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15255 * |[19] |DINOFF3 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15256 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15257 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15258 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15259 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15260 * |[20] |DINOFF4 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15261 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15262 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15263 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15264 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15265 * |[21] |DINOFF5 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15266 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15267 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15268 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15269 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15270 * |[22] |DINOFF6 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15271 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15272 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15273 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15274 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15275 * |[23] |DINOFF7 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15276 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15277 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15278 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15279 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15280 * |[24] |DINOFF8 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15281 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15282 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15283 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15284 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15285 * |[25] |DINOFF9 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15286 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15287 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15288 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15289 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15290 * |[26] |DINOFF10 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15291 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15292 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15293 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15294 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15295 * |[27] |DINOFF11 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15296 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15297 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15298 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15299 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15300 * |[28] |DINOFF12 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15301 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15302 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15303 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15304 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15305 * |[29] |DINOFF13 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15306 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15307 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15308 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15309 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15310 * |[30] |DINOFF14 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15311 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15312 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15313 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15314 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15315 * |[31] |DINOFF15 |Port N Bit M Off Digital Input Path
<> 144:ef7eb2e8f9f7 15316 * | | |Each of these bits is used to turn off the digital input path of port n bit m pin.
<> 144:ef7eb2e8f9f7 15317 * | | |If input is analog signal, users can turn off digital input path to avoid input current leakage.
<> 144:ef7eb2e8f9f7 15318 * | | |0 = Digital input path Enabled.
<> 144:ef7eb2e8f9f7 15319 * | | |1 = Digital input path Disabled (Digital input is tied to low).
<> 144:ef7eb2e8f9f7 15320 */
<> 144:ef7eb2e8f9f7 15321 __IO uint32_t DINOFF;
<> 144:ef7eb2e8f9f7 15322
<> 144:ef7eb2e8f9f7 15323 /**
<> 144:ef7eb2e8f9f7 15324 * Px_DOUT
<> 144:ef7eb2e8f9f7 15325 * ===================================================================================================
<> 144:ef7eb2e8f9f7 15326 * Offset: 0x08 Px Data Output Value
<> 144:ef7eb2e8f9f7 15327 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15328 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 15329 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 15330 * |[0] |DOUT0 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15331 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15332 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15333 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15334 * |[1] |DOUT1 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15335 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15336 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15337 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15338 * |[2] |DOUT2 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15339 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15340 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15341 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15342 * |[3] |DOUT3 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15343 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15344 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15345 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15346 * |[4] |DOUT4 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15347 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15348 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15349 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15350 * |[5] |DOUT5 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15351 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15352 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15353 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15354 * |[6] |DOUT6 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15355 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15356 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15357 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15358 * |[7] |DOUT7 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15359 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15360 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15361 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15362 * |[8] |DOUT8 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15363 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15364 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15365 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15366 * |[9] |DOUT9 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15367 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15368 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15369 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15370 * |[10] |DOUT10 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15371 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15372 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15373 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15374 * |[11] |DOUT11 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15375 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15376 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15377 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15378 * |[12] |DOUT12 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15379 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15380 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15381 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15382 * |[13] |DOUT13 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15383 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15384 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15385 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15386 * |[14] |DOUT14 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15387 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15388 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15389 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15390 * |[15] |DOUT15 |Port N Bit M Output
<> 144:ef7eb2e8f9f7 15391 * | | |Each of these bits control the status of port n bit m when this pin is configures as output, open-drain, or Quasi-bidirectional mode.
<> 144:ef7eb2e8f9f7 15392 * | | |0 = Drive port n bit m high low.
<> 144:ef7eb2e8f9f7 15393 * | | |1 = Drive port n bit m high level.
<> 144:ef7eb2e8f9f7 15394 */
<> 144:ef7eb2e8f9f7 15395 __IO uint32_t DOUT;
<> 144:ef7eb2e8f9f7 15396
<> 144:ef7eb2e8f9f7 15397 /**
<> 144:ef7eb2e8f9f7 15398 * Px_DATMSK
<> 144:ef7eb2e8f9f7 15399 * ===================================================================================================
<> 144:ef7eb2e8f9f7 15400 * Offset: 0x0C Px Data Output Write Mask
<> 144:ef7eb2e8f9f7 15401 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15402 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 15403 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 15404 * |[0] |DATMSK0 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15405 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15406 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15407 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15408 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15409 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15410 * |[1] |DATMSK1 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15411 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15412 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15413 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15414 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15415 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15416 * |[2] |DATMSK2 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15417 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15418 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15419 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15420 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15421 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15422 * |[3] |DATMSK3 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15423 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15424 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15425 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15426 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15427 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15428 * |[4] |DATMSK4 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15429 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15430 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15431 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15432 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15433 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15434 * |[5] |DATMSK5 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15435 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15436 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15437 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15438 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15439 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15440 * |[6] |DATMSK6 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15441 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15442 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15443 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15444 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15445 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15446 * |[7] |DATMSK7 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15447 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15448 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15449 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15450 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15451 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15452 * |[8] |DATMSK8 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15453 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15454 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15455 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15456 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15457 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15458 * |[9] |DATMSK9 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15459 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15460 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15461 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15462 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15463 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15464 * |[10] |DATMSK10 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15465 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15466 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15467 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15468 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15469 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15470 * |[11] |DATMSK11 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15471 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15472 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15473 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15474 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15475 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15476 * |[12] |DATMSK12 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15477 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15478 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15479 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15480 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15481 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15482 * |[13] |DATMSK13 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15483 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15484 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15485 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15486 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15487 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15488 * |[14] |DATMSK14 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15489 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15490 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15491 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15492 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15493 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15494 * |[15] |DATMSK15 |Port N Bit M Data Output Write Mask
<> 144:ef7eb2e8f9f7 15495 * | | |These bits are used to protect the corresponding register of Px_DOUT[m].
<> 144:ef7eb2e8f9f7 15496 * | | |When set the DATMSK [m] to 1, the writing to Px_DOUT[m] bit is ignored.
<> 144:ef7eb2e8f9f7 15497 * | | |The write to port pin latch is masked.
<> 144:ef7eb2e8f9f7 15498 * | | |0 = Px_DOUT[m] bit writing is valid.
<> 144:ef7eb2e8f9f7 15499 * | | |1 = Px_DOUT[m] bit writing is ignored.
<> 144:ef7eb2e8f9f7 15500 */
<> 144:ef7eb2e8f9f7 15501 __IO uint32_t DATMSK;
<> 144:ef7eb2e8f9f7 15502
<> 144:ef7eb2e8f9f7 15503 /**
<> 144:ef7eb2e8f9f7 15504 * Px_PIN
<> 144:ef7eb2e8f9f7 15505 * ===================================================================================================
<> 144:ef7eb2e8f9f7 15506 * Offset: 0x10 Px Pin Value
<> 144:ef7eb2e8f9f7 15507 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15508 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 15509 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 15510 * |[0] |PIN0 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15511 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15512 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15513 * |[1] |PIN1 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15514 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15515 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15516 * |[2] |PIN2 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15517 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15518 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15519 * |[3] |PIN3 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15520 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15521 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15522 * |[4] |PIN4 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15523 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15524 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15525 * |[5] |PIN5 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15526 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15527 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15528 * |[6] |PIN6 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15529 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15530 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15531 * |[7] |PIN7 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15532 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15533 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15534 * |[8] |PIN8 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15535 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15536 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15537 * |[9] |PIN9 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15538 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15539 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15540 * |[10] |PIN10 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15541 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15542 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15543 * |[11] |PIN11 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15544 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15545 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15546 * |[12] |PIN12 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15547 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15548 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15549 * |[13] |PIN13 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15550 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15551 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15552 * |[14] |PIN14 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15553 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15554 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15555 * |[15] |PIN15 |Port N Bit M Pin Value
<> 144:ef7eb2e8f9f7 15556 * | | |Each bit of the register reflects the actual status of the respective port pin.
<> 144:ef7eb2e8f9f7 15557 * | | |If bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
<> 144:ef7eb2e8f9f7 15558 */
<> 144:ef7eb2e8f9f7 15559 __I uint32_t PIN;
<> 144:ef7eb2e8f9f7 15560
<> 144:ef7eb2e8f9f7 15561 /**
<> 144:ef7eb2e8f9f7 15562 * Px_DBEN
<> 144:ef7eb2e8f9f7 15563 * ===================================================================================================
<> 144:ef7eb2e8f9f7 15564 * Offset: 0x14 Px De-Bounce Enable Control
<> 144:ef7eb2e8f9f7 15565 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15566 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 15567 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 15568 * |[0] |DBEN0 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15569 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15570 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15571 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15572 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15573 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15574 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15575 * |[1] |DBEN1 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15576 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15577 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15578 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15579 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15580 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15581 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15582 * |[2] |DBEN2 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15583 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15584 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15585 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15586 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15587 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15588 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15589 * |[3] |DBEN3 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15590 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15591 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15592 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15593 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15594 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15595 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15596 * |[4] |DBEN4 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15597 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15598 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15599 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15600 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15601 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15602 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15603 * |[5] |DBEN5 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15604 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15605 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15606 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15607 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15608 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15609 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15610 * |[6] |DBEN6 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15611 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15612 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15613 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15614 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15615 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15616 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15617 * |[7] |DBEN7 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15618 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15619 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15620 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15621 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15622 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15623 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15624 * |[8] |DBEN8 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15625 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15626 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15627 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15628 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15629 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15630 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15631 * |[9] |DBEN9 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15632 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15633 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15634 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15635 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15636 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15637 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15638 * |[10] |DBEN10 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15639 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15640 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15641 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15642 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15643 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15644 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15645 * |[11] |DBEN11 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15646 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15647 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15648 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15649 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15650 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15651 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15652 * |[12] |DBEN12 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15653 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15654 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15655 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15656 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15657 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15658 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15659 * |[13] |DBEN13 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15660 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15661 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15662 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15663 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15664 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15665 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15666 * |[14] |DBEN14 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15667 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15668 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15669 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15670 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15671 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15672 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15673 * |[15] |DBEN15 |Port N Bit M Input De-Bounce Enable
<> 144:ef7eb2e8f9f7 15674 * | | |DBEN[m] is used to enable the de-bounce function for each corresponding bit.
<> 144:ef7eb2e8f9f7 15675 * | | |DBEN[m] is valid for "edge-triggered" interrupt only and is ignored for "level triggered" interrupt.
<> 144:ef7eb2e8f9f7 15676 * | | |If the input signal pulse width can't be sampled by continuous two de-bounce sample cycle The input signal transition is seen as the signal bounce and will not trigger the interrupt.
<> 144:ef7eb2e8f9f7 15677 * | | |The de-bounce clock is controlled by GPIO_DBCTL register.
<> 144:ef7eb2e8f9f7 15678 * | | |0 = Port n bit m input de-bounce Disabled.
<> 144:ef7eb2e8f9f7 15679 * | | |1 = Port n bit m input de-bounce Enabled.
<> 144:ef7eb2e8f9f7 15680 */
<> 144:ef7eb2e8f9f7 15681 __IO uint32_t DBEN;
<> 144:ef7eb2e8f9f7 15682
<> 144:ef7eb2e8f9f7 15683 /**
<> 144:ef7eb2e8f9f7 15684 * Px_INTTYPE
<> 144:ef7eb2e8f9f7 15685 * ===================================================================================================
<> 144:ef7eb2e8f9f7 15686 * Offset: 0x18 Px Interrupt Trigger Type Register
<> 144:ef7eb2e8f9f7 15687 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15688 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 15689 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 15690 * |[0] |TYPE0 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15691 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15692 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15693 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15694 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15695 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15696 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15697 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15698 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15699 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15700 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15701 * |[1] |TYPE1 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15702 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15703 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15704 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15705 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15706 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15707 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15708 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15709 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15710 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15711 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15712 * |[2] |TYPE2 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15713 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15714 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15715 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15716 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15717 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15718 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15719 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15720 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15721 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15722 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15723 * |[3] |TYPE3 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15724 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15725 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15726 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15727 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15728 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15729 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15730 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15731 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15732 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15733 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15734 * |[4] |TYPE4 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15735 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15736 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15737 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15738 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15739 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15740 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15741 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15742 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15743 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15744 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15745 * |[5] |TYPE5 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15746 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15747 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15748 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15749 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15750 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15751 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15752 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15753 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15754 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15755 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15756 * |[6] |TYPE6 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15757 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15758 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15759 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15760 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15761 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15762 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15763 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15764 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15765 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15766 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15767 * |[7] |TYPE7 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15768 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15769 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15770 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15771 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15772 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15773 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15774 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15775 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15776 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15777 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15778 * |[8] |TYPE8 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15779 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15780 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15781 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15782 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15783 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15784 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15785 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15786 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15787 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15788 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15789 * |[9] |TYPE9 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15790 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15791 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15792 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15793 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15794 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15795 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15796 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15797 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15798 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15799 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15800 * |[10] |TYPE10 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15801 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15802 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15803 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15804 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15805 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15806 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15807 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15808 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15809 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15810 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15811 * |[11] |TYPE11 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15812 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15813 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15814 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15815 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15816 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15817 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15818 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15819 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15820 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15821 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15822 * |[12] |TYPE12 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15823 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15824 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15825 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15826 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15827 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15828 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15829 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15830 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15831 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15832 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15833 * |[13] |TYPE13 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15834 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15835 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15836 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15837 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15838 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15839 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15840 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15841 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15842 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15843 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15844 * |[14] |TYPE14 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15845 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15846 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15847 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15848 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15849 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15850 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15851 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15852 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15853 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15854 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15855 * |[15] |TYPE15 |Port N Bit M Edge Or Level Triggered Interrupt Control
<> 144:ef7eb2e8f9f7 15856 * | | |TYPE[m] decides the pin interrupt triggered by level or edge.
<> 144:ef7eb2e8f9f7 15857 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
<> 144:ef7eb2e8f9f7 15858 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK.
<> 144:ef7eb2e8f9f7 15859 * | | |clock and generates the interrupt.
<> 144:ef7eb2e8f9f7 15860 * | | |0 = Edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15861 * | | |1 = Level triggered interrupt.
<> 144:ef7eb2e8f9f7 15862 * | | |Note1: If pin is set as the level trigger interrupt, only one level can be set on the registers Px_INTEN.
<> 144:ef7eb2e8f9f7 15863 * | | |If set both the level to trigger interrupt, the setting is ignored and no interrupt will occur.
<> 144:ef7eb2e8f9f7 15864 * | | |Note2: The de-bounce function is valid for edge triggered interrupt.
<> 144:ef7eb2e8f9f7 15865 * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
<> 144:ef7eb2e8f9f7 15866 */
<> 144:ef7eb2e8f9f7 15867 __IO uint32_t INTTYPE;
<> 144:ef7eb2e8f9f7 15868
<> 144:ef7eb2e8f9f7 15869 /**
<> 144:ef7eb2e8f9f7 15870 * Px_INTEN
<> 144:ef7eb2e8f9f7 15871 * ===================================================================================================
<> 144:ef7eb2e8f9f7 15872 * Offset: 0x1C Px Interrupt Enable
<> 144:ef7eb2e8f9f7 15873 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 15874 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 15875 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 15876 * |[0] |FLIEN0 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15877 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15878 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15879 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15880 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15881 * |[1] |FLIEN1 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15882 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15883 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15884 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15885 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15886 * |[2] |FLIEN2 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15887 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15888 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15889 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15890 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15891 * |[3] |FLIEN3 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15892 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15893 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15894 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15895 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15896 * |[4] |FLIEN4 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15897 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15898 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15899 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15900 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15901 * |[5] |FLIEN5 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15902 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15903 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15904 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15905 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15906 * |[6] |FLIEN6 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15907 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15908 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15909 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15910 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15911 * |[7] |FLIEN7 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15912 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15913 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15914 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15915 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15916 * |[8] |FLIEN8 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15917 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15918 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15919 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15920 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15921 * |[9] |FLIEN9 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15922 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15923 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15924 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15925 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15926 * |[10] |FLIEN10 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15927 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15928 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15929 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15930 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15931 * |[11] |FLIEN11 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15932 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15933 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15934 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15935 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15936 * |[12] |FLIEN12 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15937 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15938 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15939 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15940 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15941 * |[13] |FLIEN13 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15942 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15943 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15944 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15945 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15946 * |[14] |FLIEN14 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15947 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15948 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15949 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15950 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15951 * |[15] |FLIEN15 |Port N Bit M Interrupt Enable For Falling Edge Or Low Level Input
<> 144:ef7eb2e8f9f7 15952 * | | |FLIEN[n] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15953 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15954 * | | |0 = Port n bit m low-level or falling edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15955 * | | |1 = Port n bit m low-level or falling edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15956 * |[16] |RHIEN0 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15957 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15958 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15959 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15960 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15961 * |[17] |RHIEN1 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15962 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15963 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15964 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15965 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15966 * |[18] |RHIEN2 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15967 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15968 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15969 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15970 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15971 * |[19] |RHIEN3 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15972 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15973 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15974 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15975 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15976 * |[20] |RHIEN4 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15977 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15978 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15979 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15980 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15981 * |[21] |RHIEN5 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15982 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15983 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15984 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15985 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15986 * |[22] |RHIEN6 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15987 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15988 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15989 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15990 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15991 * |[23] |RHIEN7 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15992 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15993 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15994 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 15995 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 15996 * |[24] |RHIEN8 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 15997 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 15998 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 15999 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 16000 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 16001 * |[25] |RHIEN9 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 16002 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 16003 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 16004 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 16005 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 16006 * |[26] |RHIEN10 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 16007 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 16008 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 16009 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 16010 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 16011 * |[27] |RHIEN11 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 16012 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 16013 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 16014 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 16015 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 16016 * |[28] |RHIEN12 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 16017 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 16018 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 16019 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 16020 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 16021 * |[29] |RHIEN13 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 16022 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 16023 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 16024 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 16025 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 16026 * |[30] |RHIEN14 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 16027 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 16028 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 16029 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 16030 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 16031 * |[31] |RHIEN15 |Port N Bit M Interrupt Enable For Rising Edge Or High Level Input
<> 144:ef7eb2e8f9f7 16032 * | | |RHIEN[m] enables the interrupt for each of the corresponding input of Port n.
<> 144:ef7eb2e8f9f7 16033 * | | |Setting this bit to 1 also enables the pin wake-up function.
<> 144:ef7eb2e8f9f7 16034 * | | |0 = Port n bit m high-level or rising edge interrupt Disabled.
<> 144:ef7eb2e8f9f7 16035 * | | |1 = Port n bit m high-level or rising edge interrupt Enabled.
<> 144:ef7eb2e8f9f7 16036 */
<> 144:ef7eb2e8f9f7 16037 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 16038
<> 144:ef7eb2e8f9f7 16039 /**
<> 144:ef7eb2e8f9f7 16040 * Px_INTSRC
<> 144:ef7eb2e8f9f7 16041 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16042 * Offset: 0x20 Px Interrupt Source Flag
<> 144:ef7eb2e8f9f7 16043 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16044 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16045 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16046 * |[0] |INTSRC0 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16047 * | | |Read:
<> 144:ef7eb2e8f9f7 16048 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16049 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16050 * | | |Write:
<> 144:ef7eb2e8f9f7 16051 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16052 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16053 * |[1] |INTSRC1 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16054 * | | |Read:
<> 144:ef7eb2e8f9f7 16055 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16056 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16057 * | | |Write:
<> 144:ef7eb2e8f9f7 16058 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16059 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16060 * |[2] |INTSRC2 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16061 * | | |Read:
<> 144:ef7eb2e8f9f7 16062 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16063 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16064 * | | |Write:
<> 144:ef7eb2e8f9f7 16065 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16066 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16067 * |[3] |INTSRC3 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16068 * | | |Read:
<> 144:ef7eb2e8f9f7 16069 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16070 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16071 * | | |Write:
<> 144:ef7eb2e8f9f7 16072 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16073 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16074 * |[4] |INTSRC4 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16075 * | | |Read:
<> 144:ef7eb2e8f9f7 16076 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16077 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16078 * | | |Write:
<> 144:ef7eb2e8f9f7 16079 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16080 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16081 * |[5] |INTSRC5 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16082 * | | |Read:
<> 144:ef7eb2e8f9f7 16083 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16084 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16085 * | | |Write:
<> 144:ef7eb2e8f9f7 16086 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16087 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16088 * |[6] |INTSRC6 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16089 * | | |Read:
<> 144:ef7eb2e8f9f7 16090 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16091 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16092 * | | |Write:
<> 144:ef7eb2e8f9f7 16093 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16094 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16095 * |[7] |INTSRC7 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16096 * | | |Read:
<> 144:ef7eb2e8f9f7 16097 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16098 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16099 * | | |Write:
<> 144:ef7eb2e8f9f7 16100 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16101 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16102 * |[8] |INTSRC8 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16103 * | | |Read:
<> 144:ef7eb2e8f9f7 16104 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16105 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16106 * | | |Write:
<> 144:ef7eb2e8f9f7 16107 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16108 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16109 * |[9] |INTSRC9 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16110 * | | |Read:
<> 144:ef7eb2e8f9f7 16111 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16112 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16113 * | | |Write:
<> 144:ef7eb2e8f9f7 16114 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16115 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16116 * |[10] |INTSRC10 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16117 * | | |Read:
<> 144:ef7eb2e8f9f7 16118 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16119 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16120 * | | |Write:
<> 144:ef7eb2e8f9f7 16121 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16122 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16123 * |[11] |INTSRC11 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16124 * | | |Read:
<> 144:ef7eb2e8f9f7 16125 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16126 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16127 * | | |Write:
<> 144:ef7eb2e8f9f7 16128 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16129 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16130 * |[12] |INTSRC12 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16131 * | | |Read:
<> 144:ef7eb2e8f9f7 16132 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16133 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16134 * | | |Write:
<> 144:ef7eb2e8f9f7 16135 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16136 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16137 * |[13] |INTSRC13 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16138 * | | |Read:
<> 144:ef7eb2e8f9f7 16139 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16140 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16141 * | | |Write:
<> 144:ef7eb2e8f9f7 16142 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16143 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16144 * |[14] |INTSRC14 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16145 * | | |Read:
<> 144:ef7eb2e8f9f7 16146 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16147 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16148 * | | |Write:
<> 144:ef7eb2e8f9f7 16149 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16150 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16151 * |[15] |INTSRC15 |Port N Bit M Interrupt Trigger Source Indicator
<> 144:ef7eb2e8f9f7 16152 * | | |Read:
<> 144:ef7eb2e8f9f7 16153 * | | |0 = No interrupt at Port n.
<> 144:ef7eb2e8f9f7 16154 * | | |1 = Port n bit m generate an interrupt.
<> 144:ef7eb2e8f9f7 16155 * | | |Write:
<> 144:ef7eb2e8f9f7 16156 * | | |0= No effect.
<> 144:ef7eb2e8f9f7 16157 * | | |1= Clear the correspond pending interrupt.
<> 144:ef7eb2e8f9f7 16158 */
<> 144:ef7eb2e8f9f7 16159 __IO uint32_t INTSRC;
<> 144:ef7eb2e8f9f7 16160
<> 144:ef7eb2e8f9f7 16161 /**
<> 144:ef7eb2e8f9f7 16162 * Px_SMTEN
<> 144:ef7eb2e8f9f7 16163 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16164 * Offset: 0x24 Px Input Schmitt Trigger Enable
<> 144:ef7eb2e8f9f7 16165 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16166 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16167 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16168 * |[0] |SMTEN0 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16169 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16170 * |[1] |SMTEN1 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16171 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16172 * |[2] |SMTEN2 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16173 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16174 * |[3] |SMTEN3 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16175 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16176 * |[4] |SMTEN4 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16177 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16178 * |[5] |SMTEN5 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16179 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16180 * |[6] |SMTEN6 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16181 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16182 * |[7] |SMTEN7 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16183 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16184 * |[8] |SMTEN8 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16185 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16186 * |[9] |SMTEN9 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16187 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16188 * |[10] |SMTEN10 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16189 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16190 * |[11] |SMTEN11 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16191 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16192 * |[12] |SMTEN12 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16193 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16194 * |[13] |SMTEN13 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16195 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16196 * |[14] |SMTEN14 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16197 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16198 * |[15] |SMTEN15 |0 = P I/O input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 16199 * | | |1 = P I/O input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 16200 */
<> 144:ef7eb2e8f9f7 16201 __IO uint32_t SMTEN;
<> 144:ef7eb2e8f9f7 16202
<> 144:ef7eb2e8f9f7 16203 /**
<> 144:ef7eb2e8f9f7 16204 * Px_SLEWCTL
<> 144:ef7eb2e8f9f7 16205 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16206 * Offset: 0x28 Px High Slew Rate Control
<> 144:ef7eb2e8f9f7 16207 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16208 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16209 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16210 * |[0] |HSREN0 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16211 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16212 * |[1] |HSREN1 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16213 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16214 * |[2] |HSREN2 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16215 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16216 * |[3] |HSREN3 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16217 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16218 * |[4] |HSREN4 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16219 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16220 * |[5] |HSREN5 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16221 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16222 * |[6] |HSREN6 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16223 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16224 * |[7] |HSREN7 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16225 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16226 * |[8] |HSREN8 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16227 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16228 * |[9] |HSREN9 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16229 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16230 * |[10] |HSREN10 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16231 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16232 * |[11] |HSREN11 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16233 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16234 * |[12] |HSREN12 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16235 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16236 * |[13] |HSREN13 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16237 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16238 * |[14] |HSREN14 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16239 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16240 * |[15] |HSREN15 |0 = P I/O output with basic slew rate.
<> 144:ef7eb2e8f9f7 16241 * | | |1 = P I/O output with higher slew rate.
<> 144:ef7eb2e8f9f7 16242 */
<> 144:ef7eb2e8f9f7 16243 __IO uint32_t SLEWCTL;
<> 144:ef7eb2e8f9f7 16244
<> 144:ef7eb2e8f9f7 16245 } GPIO_T;
<> 144:ef7eb2e8f9f7 16246
<> 144:ef7eb2e8f9f7 16247
<> 144:ef7eb2e8f9f7 16248 typedef struct {
<> 144:ef7eb2e8f9f7 16249
<> 144:ef7eb2e8f9f7 16250 /**
<> 144:ef7eb2e8f9f7 16251 * GPIO_DBCTL
<> 144:ef7eb2e8f9f7 16252 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16253 * Offset: 0x000 Interrupt De-bounce Control
<> 144:ef7eb2e8f9f7 16254 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16255 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16256 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16257 * |[0:3] |DBCLKSEL |De-Bounce Sampling Cycle Selection
<> 144:ef7eb2e8f9f7 16258 * | | |0000 = Sample interrupt input once per 1 clocks.
<> 144:ef7eb2e8f9f7 16259 * | | |0001 = Sample interrupt input once per 2 clocks.
<> 144:ef7eb2e8f9f7 16260 * | | |0010 = Sample interrupt input once per 4 clocks.
<> 144:ef7eb2e8f9f7 16261 * | | |0011 = Sample interrupt input once per 8 clocks.
<> 144:ef7eb2e8f9f7 16262 * | | |0100 = Sample interrupt input once per 16 clocks.
<> 144:ef7eb2e8f9f7 16263 * | | |0101 = Sample interrupt input once per 32 clocks.
<> 144:ef7eb2e8f9f7 16264 * | | |0110 = Sample interrupt input once per 64 clocks.
<> 144:ef7eb2e8f9f7 16265 * | | |0111 = Sample interrupt input once per 128 clocks.
<> 144:ef7eb2e8f9f7 16266 * | | |1000 = Sample interrupt input once per 256 clocks.
<> 144:ef7eb2e8f9f7 16267 * | | |1001 = Sample interrupt input once per 2*256 clocks.
<> 144:ef7eb2e8f9f7 16268 * | | |1010 = Sample interrupt input once per 4*256 clocks.
<> 144:ef7eb2e8f9f7 16269 * | | |1011 = Sample interrupt input once per 8*256 clocks.
<> 144:ef7eb2e8f9f7 16270 * | | |1100 = Sample interrupt input once per 16*256 clocks.
<> 144:ef7eb2e8f9f7 16271 * | | |1101 = Sample interrupt input once per 32*256 clocks.
<> 144:ef7eb2e8f9f7 16272 * | | |1110 = Sample interrupt input once per 64*256 clocks.
<> 144:ef7eb2e8f9f7 16273 * | | |1111 = Sample interrupt input once per 128*256 clocks.
<> 144:ef7eb2e8f9f7 16274 * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
<> 144:ef7eb2e8f9f7 16275 * | | |0 = De-bounce counter clock source is the HCLK.
<> 144:ef7eb2e8f9f7 16276 * | | |1 = De-bounce counter clock source is the internal 10 kHz clock.
<> 144:ef7eb2e8f9f7 16277 * |[5] |ICLKON |Interrupt Clock On Mode
<> 144:ef7eb2e8f9f7 16278 * | | |Setting this bit to 0 will disable the interrupt generate circuit clock if the pin[n] interrupt is disabled.
<> 144:ef7eb2e8f9f7 16279 * | | |0 = Disable the clock if the all port interrupts are disabled.
<> 144:ef7eb2e8f9f7 16280 * | | |1 = Interrupt generated circuit clock always Enabled.
<> 144:ef7eb2e8f9f7 16281 */
<> 144:ef7eb2e8f9f7 16282 __IO uint32_t DBCTL;
<> 144:ef7eb2e8f9f7 16283
<> 144:ef7eb2e8f9f7 16284 } GPIO_DB_T;
<> 144:ef7eb2e8f9f7 16285
<> 144:ef7eb2e8f9f7 16286 /**
<> 144:ef7eb2e8f9f7 16287 @addtogroup GPIO_CONST GPIO Bit Field Definition
<> 144:ef7eb2e8f9f7 16288 Constant Definitions for GPIO Controller
<> 144:ef7eb2e8f9f7 16289 @{ */
<> 144:ef7eb2e8f9f7 16290
<> 144:ef7eb2e8f9f7 16291 #define GPIO_MODE_MODE0_Pos (0) /*!< GPIO MODE: MODE0 Position */
<> 144:ef7eb2e8f9f7 16292 #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) /*!< GPIO MODE: MODE0 Mask */
<> 144:ef7eb2e8f9f7 16293
<> 144:ef7eb2e8f9f7 16294 #define GPIO_MODE_MODE1_Pos (2) /*!< GPIO MODE: MODE1 Position */
<> 144:ef7eb2e8f9f7 16295 #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) /*!< GPIO MODE: MODE1 Mask */
<> 144:ef7eb2e8f9f7 16296
<> 144:ef7eb2e8f9f7 16297 #define GPIO_MODE_MODE2_Pos (4) /*!< GPIO MODE: MODE2 Position */
<> 144:ef7eb2e8f9f7 16298 #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) /*!< GPIO MODE: MODE2 Mask */
<> 144:ef7eb2e8f9f7 16299
<> 144:ef7eb2e8f9f7 16300 #define GPIO_MODE_MODE3_Pos (6) /*!< GPIO MODE: MODE3 Position */
<> 144:ef7eb2e8f9f7 16301 #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) /*!< GPIO MODE: MODE3 Mask */
<> 144:ef7eb2e8f9f7 16302
<> 144:ef7eb2e8f9f7 16303 #define GPIO_MODE_MODE4_Pos (8) /*!< GPIO MODE: MODE4 Position */
<> 144:ef7eb2e8f9f7 16304 #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) /*!< GPIO MODE: MODE4 Mask */
<> 144:ef7eb2e8f9f7 16305
<> 144:ef7eb2e8f9f7 16306 #define GPIO_MODE_MODE5_Pos (10) /*!< GPIO MODE: MODE5 Position */
<> 144:ef7eb2e8f9f7 16307 #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) /*!< GPIO MODE: MODE5 Mask */
<> 144:ef7eb2e8f9f7 16308
<> 144:ef7eb2e8f9f7 16309 #define GPIO_MODE_MODE6_Pos (12) /*!< GPIO MODE: MODE6 Position */
<> 144:ef7eb2e8f9f7 16310 #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) /*!< GPIO MODE: MODE6 Mask */
<> 144:ef7eb2e8f9f7 16311
<> 144:ef7eb2e8f9f7 16312 #define GPIO_MODE_MODE7_Pos (14) /*!< GPIO MODE: MODE7 Position */
<> 144:ef7eb2e8f9f7 16313 #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) /*!< GPIO MODE: MODE7 Mask */
<> 144:ef7eb2e8f9f7 16314
<> 144:ef7eb2e8f9f7 16315 #define GPIO_MODE_MODE8_Pos (16) /*!< GPIO MODE: MODE8 Position */
<> 144:ef7eb2e8f9f7 16316 #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) /*!< GPIO MODE: MODE8 Mask */
<> 144:ef7eb2e8f9f7 16317
<> 144:ef7eb2e8f9f7 16318 #define GPIO_MODE_MODE9_Pos (18) /*!< GPIO MODE: MODE9 Position */
<> 144:ef7eb2e8f9f7 16319 #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) /*!< GPIO MODE: MODE9 Mask */
<> 144:ef7eb2e8f9f7 16320
<> 144:ef7eb2e8f9f7 16321 #define GPIO_MODE_MODE10_Pos (20) /*!< GPIO MODE: MODE10 Position */
<> 144:ef7eb2e8f9f7 16322 #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) /*!< GPIO MODE: MODE10 Mask */
<> 144:ef7eb2e8f9f7 16323
<> 144:ef7eb2e8f9f7 16324 #define GPIO_MODE_MODE11_Pos (22) /*!< GPIO MODE: MODE11 Position */
<> 144:ef7eb2e8f9f7 16325 #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) /*!< GPIO MODE: MODE11 Mask */
<> 144:ef7eb2e8f9f7 16326
<> 144:ef7eb2e8f9f7 16327 #define GPIO_MODE_MODE12_Pos (24) /*!< GPIO MODE: MODE12 Position */
<> 144:ef7eb2e8f9f7 16328 #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) /*!< GPIO MODE: MODE12 Mask */
<> 144:ef7eb2e8f9f7 16329
<> 144:ef7eb2e8f9f7 16330 #define GPIO_MODE_MODE13_Pos (26) /*!< GPIO MODE: MODE13 Position */
<> 144:ef7eb2e8f9f7 16331 #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) /*!< GPIO MODE: MODE13 Mask */
<> 144:ef7eb2e8f9f7 16332
<> 144:ef7eb2e8f9f7 16333 #define GPIO_MODE_MODE14_Pos (28) /*!< GPIO MODE: MODE14 Position */
<> 144:ef7eb2e8f9f7 16334 #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) /*!< GPIO MODE: MODE14 Mask */
<> 144:ef7eb2e8f9f7 16335
<> 144:ef7eb2e8f9f7 16336 #define GPIO_MODE_MODE15_Pos (30) /*!< GPIO MODE: MODE15 Position */
<> 144:ef7eb2e8f9f7 16337 #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) /*!< GPIO MODE: MODE15 Mask */
<> 144:ef7eb2e8f9f7 16338
<> 144:ef7eb2e8f9f7 16339 #define GPIO_DINOFF_DINOFF0_Pos (16) /*!< GPIO DINOFF: DINOFF0 Position */
<> 144:ef7eb2e8f9f7 16340 #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) /*!< GPIO DINOFF: DINOFF0 Mask */
<> 144:ef7eb2e8f9f7 16341
<> 144:ef7eb2e8f9f7 16342 #define GPIO_DINOFF_DINOFF1_Pos (17) /*!< GPIO DINOFF: DINOFF1 Position */
<> 144:ef7eb2e8f9f7 16343 #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) /*!< GPIO DINOFF: DINOFF1 Mask */
<> 144:ef7eb2e8f9f7 16344
<> 144:ef7eb2e8f9f7 16345 #define GPIO_DINOFF_DINOFF2_Pos (18) /*!< GPIO DINOFF: DINOFF2 Position */
<> 144:ef7eb2e8f9f7 16346 #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) /*!< GPIO DINOFF: DINOFF2 Mask */
<> 144:ef7eb2e8f9f7 16347
<> 144:ef7eb2e8f9f7 16348 #define GPIO_DINOFF_DINOFF3_Pos (19) /*!< GPIO DINOFF: DINOFF3 Position */
<> 144:ef7eb2e8f9f7 16349 #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) /*!< GPIO DINOFF: DINOFF3 Mask */
<> 144:ef7eb2e8f9f7 16350
<> 144:ef7eb2e8f9f7 16351 #define GPIO_DINOFF_DINOFF4_Pos (20) /*!< GPIO DINOFF: DINOFF4 Position */
<> 144:ef7eb2e8f9f7 16352 #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) /*!< GPIO DINOFF: DINOFF4 Mask */
<> 144:ef7eb2e8f9f7 16353
<> 144:ef7eb2e8f9f7 16354 #define GPIO_DINOFF_DINOFF5_Pos (21) /*!< GPIO DINOFF: DINOFF5 Position */
<> 144:ef7eb2e8f9f7 16355 #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) /*!< GPIO DINOFF: DINOFF5 Mask */
<> 144:ef7eb2e8f9f7 16356
<> 144:ef7eb2e8f9f7 16357 #define GPIO_DINOFF_DINOFF6_Pos (22) /*!< GPIO DINOFF: DINOFF6 Position */
<> 144:ef7eb2e8f9f7 16358 #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) /*!< GPIO DINOFF: DINOFF6 Mask */
<> 144:ef7eb2e8f9f7 16359
<> 144:ef7eb2e8f9f7 16360 #define GPIO_DINOFF_DINOFF7_Pos (23) /*!< GPIO DINOFF: DINOFF7 Position */
<> 144:ef7eb2e8f9f7 16361 #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) /*!< GPIO DINOFF: DINOFF7 Mask */
<> 144:ef7eb2e8f9f7 16362
<> 144:ef7eb2e8f9f7 16363 #define GPIO_DINOFF_DINOFF8_Pos (24) /*!< GPIO DINOFF: DINOFF8 Position */
<> 144:ef7eb2e8f9f7 16364 #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) /*!< GPIO DINOFF: DINOFF8 Mask */
<> 144:ef7eb2e8f9f7 16365
<> 144:ef7eb2e8f9f7 16366 #define GPIO_DINOFF_DINOFF9_Pos (25) /*!< GPIO DINOFF: DINOFF9 Position */
<> 144:ef7eb2e8f9f7 16367 #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) /*!< GPIO DINOFF: DINOFF9 Mask */
<> 144:ef7eb2e8f9f7 16368
<> 144:ef7eb2e8f9f7 16369 #define GPIO_DINOFF_DINOFF10_Pos (26) /*!< GPIO DINOFF: DINOFF10 Position */
<> 144:ef7eb2e8f9f7 16370 #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) /*!< GPIO DINOFF: DINOFF10 Mask */
<> 144:ef7eb2e8f9f7 16371
<> 144:ef7eb2e8f9f7 16372 #define GPIO_DINOFF_DINOFF11_Pos (27) /*!< GPIO DINOFF: DINOFF11 Position */
<> 144:ef7eb2e8f9f7 16373 #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) /*!< GPIO DINOFF: DINOFF11 Mask */
<> 144:ef7eb2e8f9f7 16374
<> 144:ef7eb2e8f9f7 16375 #define GPIO_DINOFF_DINOFF12_Pos (28) /*!< GPIO DINOFF: DINOFF12 Position */
<> 144:ef7eb2e8f9f7 16376 #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) /*!< GPIO DINOFF: DINOFF12 Mask */
<> 144:ef7eb2e8f9f7 16377
<> 144:ef7eb2e8f9f7 16378 #define GPIO_DINOFF_DINOFF13_Pos (29) /*!< GPIO DINOFF: DINOFF13 Position */
<> 144:ef7eb2e8f9f7 16379 #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) /*!< GPIO DINOFF: DINOFF13 Mask */
<> 144:ef7eb2e8f9f7 16380
<> 144:ef7eb2e8f9f7 16381 #define GPIO_DINOFF_DINOFF14_Pos (30) /*!< GPIO DINOFF: DINOFF14 Position */
<> 144:ef7eb2e8f9f7 16382 #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) /*!< GPIO DINOFF: DINOFF14 Mask */
<> 144:ef7eb2e8f9f7 16383
<> 144:ef7eb2e8f9f7 16384 #define GPIO_DINOFF_DINOFF15_Pos (31) /*!< GPIO DINOFF: DINOFF15 Position */
<> 144:ef7eb2e8f9f7 16385 #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) /*!< GPIO DINOFF: DINOFF15 Mask */
<> 144:ef7eb2e8f9f7 16386
<> 144:ef7eb2e8f9f7 16387 #define GPIO_DOUT_DOUT0_Pos (0) /*!< GPIO DOUT: DOUT0 Position */
<> 144:ef7eb2e8f9f7 16388 #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) /*!< GPIO DOUT: DOUT0 Mask */
<> 144:ef7eb2e8f9f7 16389
<> 144:ef7eb2e8f9f7 16390 #define GPIO_DOUT_DOUT1_Pos (1) /*!< GPIO DOUT: DOUT1 Position */
<> 144:ef7eb2e8f9f7 16391 #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) /*!< GPIO DOUT: DOUT1 Mask */
<> 144:ef7eb2e8f9f7 16392
<> 144:ef7eb2e8f9f7 16393 #define GPIO_DOUT_DOUT2_Pos (2) /*!< GPIO DOUT: DOUT2 Position */
<> 144:ef7eb2e8f9f7 16394 #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) /*!< GPIO DOUT: DOUT2 Mask */
<> 144:ef7eb2e8f9f7 16395
<> 144:ef7eb2e8f9f7 16396 #define GPIO_DOUT_DOUT3_Pos (3) /*!< GPIO DOUT: DOUT3 Position */
<> 144:ef7eb2e8f9f7 16397 #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) /*!< GPIO DOUT: DOUT3 Mask */
<> 144:ef7eb2e8f9f7 16398
<> 144:ef7eb2e8f9f7 16399 #define GPIO_DOUT_DOUT4_Pos (4) /*!< GPIO DOUT: DOUT4 Position */
<> 144:ef7eb2e8f9f7 16400 #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) /*!< GPIO DOUT: DOUT4 Mask */
<> 144:ef7eb2e8f9f7 16401
<> 144:ef7eb2e8f9f7 16402 #define GPIO_DOUT_DOUT5_Pos (5) /*!< GPIO DOUT: DOUT5 Position */
<> 144:ef7eb2e8f9f7 16403 #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) /*!< GPIO DOUT: DOUT5 Mask */
<> 144:ef7eb2e8f9f7 16404
<> 144:ef7eb2e8f9f7 16405 #define GPIO_DOUT_DOUT6_Pos (6) /*!< GPIO DOUT: DOUT6 Position */
<> 144:ef7eb2e8f9f7 16406 #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) /*!< GPIO DOUT: DOUT6 Mask */
<> 144:ef7eb2e8f9f7 16407
<> 144:ef7eb2e8f9f7 16408 #define GPIO_DOUT_DOUT7_Pos (7) /*!< GPIO DOUT: DOUT7 Position */
<> 144:ef7eb2e8f9f7 16409 #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) /*!< GPIO DOUT: DOUT7 Mask */
<> 144:ef7eb2e8f9f7 16410
<> 144:ef7eb2e8f9f7 16411 #define GPIO_DOUT_DOUT8_Pos (8) /*!< GPIO DOUT: DOUT8 Position */
<> 144:ef7eb2e8f9f7 16412 #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) /*!< GPIO DOUT: DOUT8 Mask */
<> 144:ef7eb2e8f9f7 16413
<> 144:ef7eb2e8f9f7 16414 #define GPIO_DOUT_DOUT9_Pos (9) /*!< GPIO DOUT: DOUT9 Position */
<> 144:ef7eb2e8f9f7 16415 #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) /*!< GPIO DOUT: DOUT9 Mask */
<> 144:ef7eb2e8f9f7 16416
<> 144:ef7eb2e8f9f7 16417 #define GPIO_DOUT_DOUT10_Pos (10) /*!< GPIO DOUT: DOUT10 Position */
<> 144:ef7eb2e8f9f7 16418 #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) /*!< GPIO DOUT: DOUT10 Mask */
<> 144:ef7eb2e8f9f7 16419
<> 144:ef7eb2e8f9f7 16420 #define GPIO_DOUT_DOUT11_Pos (11) /*!< GPIO DOUT: DOUT11 Position */
<> 144:ef7eb2e8f9f7 16421 #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) /*!< GPIO DOUT: DOUT11 Mask */
<> 144:ef7eb2e8f9f7 16422
<> 144:ef7eb2e8f9f7 16423 #define GPIO_DOUT_DOUT12_Pos (12) /*!< GPIO DOUT: DOUT12 Position */
<> 144:ef7eb2e8f9f7 16424 #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) /*!< GPIO DOUT: DOUT12 Mask */
<> 144:ef7eb2e8f9f7 16425
<> 144:ef7eb2e8f9f7 16426 #define GPIO_DOUT_DOUT13_Pos (13) /*!< GPIO DOUT: DOUT13 Position */
<> 144:ef7eb2e8f9f7 16427 #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) /*!< GPIO DOUT: DOUT13 Mask */
<> 144:ef7eb2e8f9f7 16428
<> 144:ef7eb2e8f9f7 16429 #define GPIO_DOUT_DOUT14_Pos (14) /*!< GPIO DOUT: DOUT14 Position */
<> 144:ef7eb2e8f9f7 16430 #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) /*!< GPIO DOUT: DOUT14 Mask */
<> 144:ef7eb2e8f9f7 16431
<> 144:ef7eb2e8f9f7 16432 #define GPIO_DOUT_DOUT15_Pos (15) /*!< GPIO DOUT: DOUT15 Position */
<> 144:ef7eb2e8f9f7 16433 #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) /*!< GPIO DOUT: DOUT15 Mask */
<> 144:ef7eb2e8f9f7 16434
<> 144:ef7eb2e8f9f7 16435 #define GPIO_DATMSK_DATMSK0_Pos (0) /*!< GPIO DATMSK: DATMSK0 Position */
<> 144:ef7eb2e8f9f7 16436 #define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) /*!< GPIO DATMSK: DATMSK0 Mask */
<> 144:ef7eb2e8f9f7 16437
<> 144:ef7eb2e8f9f7 16438 #define GPIO_DATMSK_DATMSK1_Pos (1) /*!< GPIO DATMSK: DATMSK1 Position */
<> 144:ef7eb2e8f9f7 16439 #define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) /*!< GPIO DATMSK: DATMSK1 Mask */
<> 144:ef7eb2e8f9f7 16440
<> 144:ef7eb2e8f9f7 16441 #define GPIO_DATMSK_DATMSK2_Pos (2) /*!< GPIO DATMSK: DATMSK2 Position */
<> 144:ef7eb2e8f9f7 16442 #define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) /*!< GPIO DATMSK: DATMSK2 Mask */
<> 144:ef7eb2e8f9f7 16443
<> 144:ef7eb2e8f9f7 16444 #define GPIO_DATMSK_DATMSK3_Pos (3) /*!< GPIO DATMSK: DATMSK3 Position */
<> 144:ef7eb2e8f9f7 16445 #define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) /*!< GPIO DATMSK: DATMSK3 Mask */
<> 144:ef7eb2e8f9f7 16446
<> 144:ef7eb2e8f9f7 16447 #define GPIO_DATMSK_DATMSK4_Pos (4) /*!< GPIO DATMSK: DATMSK4 Position */
<> 144:ef7eb2e8f9f7 16448 #define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) /*!< GPIO DATMSK: DATMSK4 Mask */
<> 144:ef7eb2e8f9f7 16449
<> 144:ef7eb2e8f9f7 16450 #define GPIO_DATMSK_DATMSK5_Pos (5) /*!< GPIO DATMSK: DATMSK5 Position */
<> 144:ef7eb2e8f9f7 16451 #define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) /*!< GPIO DATMSK: DATMSK5 Mask */
<> 144:ef7eb2e8f9f7 16452
<> 144:ef7eb2e8f9f7 16453 #define GPIO_DATMSK_DATMSK6_Pos (6) /*!< GPIO DATMSK: DATMSK6 Position */
<> 144:ef7eb2e8f9f7 16454 #define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) /*!< GPIO DATMSK: DATMSK6 Mask */
<> 144:ef7eb2e8f9f7 16455
<> 144:ef7eb2e8f9f7 16456 #define GPIO_DATMSK_DATMSK7_Pos (7) /*!< GPIO DATMSK: DATMSK7 Position */
<> 144:ef7eb2e8f9f7 16457 #define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) /*!< GPIO DATMSK: DATMSK7 Mask */
<> 144:ef7eb2e8f9f7 16458
<> 144:ef7eb2e8f9f7 16459 #define GPIO_DATMSK_DATMSK8_Pos (8) /*!< GPIO DATMSK: DATMSK8 Position */
<> 144:ef7eb2e8f9f7 16460 #define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) /*!< GPIO DATMSK: DATMSK8 Mask */
<> 144:ef7eb2e8f9f7 16461
<> 144:ef7eb2e8f9f7 16462 #define GPIO_DATMSK_DATMSK9_Pos (9) /*!< GPIO DATMSK: DATMSK9 Position */
<> 144:ef7eb2e8f9f7 16463 #define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) /*!< GPIO DATMSK: DATMSK9 Mask */
<> 144:ef7eb2e8f9f7 16464
<> 144:ef7eb2e8f9f7 16465 #define GPIO_DATMSK_DATMSK10_Pos (10) /*!< GPIO DATMSK: DATMSK10 Position */
<> 144:ef7eb2e8f9f7 16466 #define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) /*!< GPIO DATMSK: DATMSK10 Mask */
<> 144:ef7eb2e8f9f7 16467
<> 144:ef7eb2e8f9f7 16468 #define GPIO_DATMSK_DATMSK11_Pos (11) /*!< GPIO DATMSK: DATMSK11 Position */
<> 144:ef7eb2e8f9f7 16469 #define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) /*!< GPIO DATMSK: DATMSK11 Mask */
<> 144:ef7eb2e8f9f7 16470
<> 144:ef7eb2e8f9f7 16471 #define GPIO_DATMSK_DATMSK12_Pos (12) /*!< GPIO DATMSK: DATMSK12 Position */
<> 144:ef7eb2e8f9f7 16472 #define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) /*!< GPIO DATMSK: DATMSK12 Mask */
<> 144:ef7eb2e8f9f7 16473
<> 144:ef7eb2e8f9f7 16474 #define GPIO_DATMSK_DATMSK13_Pos (13) /*!< GPIO DATMSK: DATMSK13 Position */
<> 144:ef7eb2e8f9f7 16475 #define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) /*!< GPIO DATMSK: DATMSK13 Mask */
<> 144:ef7eb2e8f9f7 16476
<> 144:ef7eb2e8f9f7 16477 #define GPIO_DATMSK_DATMSK14_Pos (14) /*!< GPIO DATMSK: DATMSK14 Position */
<> 144:ef7eb2e8f9f7 16478 #define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) /*!< GPIO DATMSK: DATMSK14 Mask */
<> 144:ef7eb2e8f9f7 16479
<> 144:ef7eb2e8f9f7 16480 #define GPIO_DATMSK_DATMSK15_Pos (15) /*!< GPIO DATMSK: DATMSK15 Position */
<> 144:ef7eb2e8f9f7 16481 #define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) /*!< GPIO DATMSK: DATMSK15 Mask */
<> 144:ef7eb2e8f9f7 16482
<> 144:ef7eb2e8f9f7 16483 #define GPIO_PIN_PIN0_Pos (0) /*!< GPIO PIN: PIN0 Position */
<> 144:ef7eb2e8f9f7 16484 #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) /*!< GPIO PIN: PIN0 Mask */
<> 144:ef7eb2e8f9f7 16485
<> 144:ef7eb2e8f9f7 16486 #define GPIO_PIN_PIN1_Pos (1) /*!< GPIO PIN: PIN1 Position */
<> 144:ef7eb2e8f9f7 16487 #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) /*!< GPIO PIN: PIN1 Mask */
<> 144:ef7eb2e8f9f7 16488
<> 144:ef7eb2e8f9f7 16489 #define GPIO_PIN_PIN2_Pos (2) /*!< GPIO PIN: PIN2 Position */
<> 144:ef7eb2e8f9f7 16490 #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) /*!< GPIO PIN: PIN2 Mask */
<> 144:ef7eb2e8f9f7 16491
<> 144:ef7eb2e8f9f7 16492 #define GPIO_PIN_PIN3_Pos (3) /*!< GPIO PIN: PIN3 Position */
<> 144:ef7eb2e8f9f7 16493 #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) /*!< GPIO PIN: PIN3 Mask */
<> 144:ef7eb2e8f9f7 16494
<> 144:ef7eb2e8f9f7 16495 #define GPIO_PIN_PIN4_Pos (4) /*!< GPIO PIN: PIN4 Position */
<> 144:ef7eb2e8f9f7 16496 #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) /*!< GPIO PIN: PIN4 Mask */
<> 144:ef7eb2e8f9f7 16497
<> 144:ef7eb2e8f9f7 16498 #define GPIO_PIN_PIN5_Pos (5) /*!< GPIO PIN: PIN5 Position */
<> 144:ef7eb2e8f9f7 16499 #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) /*!< GPIO PIN: PIN5 Mask */
<> 144:ef7eb2e8f9f7 16500
<> 144:ef7eb2e8f9f7 16501 #define GPIO_PIN_PIN6_Pos (6) /*!< GPIO PIN: PIN6 Position */
<> 144:ef7eb2e8f9f7 16502 #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) /*!< GPIO PIN: PIN6 Mask */
<> 144:ef7eb2e8f9f7 16503
<> 144:ef7eb2e8f9f7 16504 #define GPIO_PIN_PIN7_Pos (7) /*!< GPIO PIN: PIN7 Position */
<> 144:ef7eb2e8f9f7 16505 #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) /*!< GPIO PIN: PIN7 Mask */
<> 144:ef7eb2e8f9f7 16506
<> 144:ef7eb2e8f9f7 16507 #define GPIO_PIN_PIN8_Pos (8) /*!< GPIO PIN: PIN8 Position */
<> 144:ef7eb2e8f9f7 16508 #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) /*!< GPIO PIN: PIN8 Mask */
<> 144:ef7eb2e8f9f7 16509
<> 144:ef7eb2e8f9f7 16510 #define GPIO_PIN_PIN9_Pos (9) /*!< GPIO PIN: PIN9 Position */
<> 144:ef7eb2e8f9f7 16511 #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) /*!< GPIO PIN: PIN9 Mask */
<> 144:ef7eb2e8f9f7 16512
<> 144:ef7eb2e8f9f7 16513 #define GPIO_PIN_PIN10_Pos (10) /*!< GPIO PIN: PIN10 Position */
<> 144:ef7eb2e8f9f7 16514 #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) /*!< GPIO PIN: PIN10 Mask */
<> 144:ef7eb2e8f9f7 16515
<> 144:ef7eb2e8f9f7 16516 #define GPIO_PIN_PIN11_Pos (11) /*!< GPIO PIN: PIN11 Position */
<> 144:ef7eb2e8f9f7 16517 #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) /*!< GPIO PIN: PIN11 Mask */
<> 144:ef7eb2e8f9f7 16518
<> 144:ef7eb2e8f9f7 16519 #define GPIO_PIN_PIN12_Pos (12) /*!< GPIO PIN: PIN12 Position */
<> 144:ef7eb2e8f9f7 16520 #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) /*!< GPIO PIN: PIN12 Mask */
<> 144:ef7eb2e8f9f7 16521
<> 144:ef7eb2e8f9f7 16522 #define GPIO_PIN_PIN13_Pos (13) /*!< GPIO PIN: PIN13 Position */
<> 144:ef7eb2e8f9f7 16523 #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) /*!< GPIO PIN: PIN13 Mask */
<> 144:ef7eb2e8f9f7 16524
<> 144:ef7eb2e8f9f7 16525 #define GPIO_PIN_PIN14_Pos (14) /*!< GPIO PIN: PIN14 Position */
<> 144:ef7eb2e8f9f7 16526 #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) /*!< GPIO PIN: PIN14 Mask */
<> 144:ef7eb2e8f9f7 16527
<> 144:ef7eb2e8f9f7 16528 #define GPIO_PIN_PIN15_Pos (15) /*!< GPIO PIN: PIN15 Position */
<> 144:ef7eb2e8f9f7 16529 #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) /*!< GPIO PIN: PIN15 Mask */
<> 144:ef7eb2e8f9f7 16530
<> 144:ef7eb2e8f9f7 16531 #define GPIO_DBEN_DBEN0_Pos (0) /*!< GPIO DBEN: DBEN0 Position */
<> 144:ef7eb2e8f9f7 16532 #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) /*!< GPIO DBEN: DBEN0 Mask */
<> 144:ef7eb2e8f9f7 16533
<> 144:ef7eb2e8f9f7 16534 #define GPIO_DBEN_DBEN1_Pos (1) /*!< GPIO DBEN: DBEN1 Position */
<> 144:ef7eb2e8f9f7 16535 #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) /*!< GPIO DBEN: DBEN1 Mask */
<> 144:ef7eb2e8f9f7 16536
<> 144:ef7eb2e8f9f7 16537 #define GPIO_DBEN_DBEN2_Pos (2) /*!< GPIO DBEN: DBEN2 Position */
<> 144:ef7eb2e8f9f7 16538 #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) /*!< GPIO DBEN: DBEN2 Mask */
<> 144:ef7eb2e8f9f7 16539
<> 144:ef7eb2e8f9f7 16540 #define GPIO_DBEN_DBEN3_Pos (3) /*!< GPIO DBEN: DBEN3 Position */
<> 144:ef7eb2e8f9f7 16541 #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) /*!< GPIO DBEN: DBEN3 Mask */
<> 144:ef7eb2e8f9f7 16542
<> 144:ef7eb2e8f9f7 16543 #define GPIO_DBEN_DBEN4_Pos (4) /*!< GPIO DBEN: DBEN4 Position */
<> 144:ef7eb2e8f9f7 16544 #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) /*!< GPIO DBEN: DBEN4 Mask */
<> 144:ef7eb2e8f9f7 16545
<> 144:ef7eb2e8f9f7 16546 #define GPIO_DBEN_DBEN5_Pos (5) /*!< GPIO DBEN: DBEN5 Position */
<> 144:ef7eb2e8f9f7 16547 #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) /*!< GPIO DBEN: DBEN5 Mask */
<> 144:ef7eb2e8f9f7 16548
<> 144:ef7eb2e8f9f7 16549 #define GPIO_DBEN_DBEN6_Pos (6) /*!< GPIO DBEN: DBEN6 Position */
<> 144:ef7eb2e8f9f7 16550 #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) /*!< GPIO DBEN: DBEN6 Mask */
<> 144:ef7eb2e8f9f7 16551
<> 144:ef7eb2e8f9f7 16552 #define GPIO_DBEN_DBEN7_Pos (7) /*!< GPIO DBEN: DBEN7 Position */
<> 144:ef7eb2e8f9f7 16553 #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) /*!< GPIO DBEN: DBEN7 Mask */
<> 144:ef7eb2e8f9f7 16554
<> 144:ef7eb2e8f9f7 16555 #define GPIO_DBEN_DBEN8_Pos (8) /*!< GPIO DBEN: DBEN8 Position */
<> 144:ef7eb2e8f9f7 16556 #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) /*!< GPIO DBEN: DBEN8 Mask */
<> 144:ef7eb2e8f9f7 16557
<> 144:ef7eb2e8f9f7 16558 #define GPIO_DBEN_DBEN9_Pos (9) /*!< GPIO DBEN: DBEN9 Position */
<> 144:ef7eb2e8f9f7 16559 #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) /*!< GPIO DBEN: DBEN9 Mask */
<> 144:ef7eb2e8f9f7 16560
<> 144:ef7eb2e8f9f7 16561 #define GPIO_DBEN_DBEN10_Pos (10) /*!< GPIO DBEN: DBEN10 Position */
<> 144:ef7eb2e8f9f7 16562 #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) /*!< GPIO DBEN: DBEN10 Mask */
<> 144:ef7eb2e8f9f7 16563
<> 144:ef7eb2e8f9f7 16564 #define GPIO_DBEN_DBEN11_Pos (11) /*!< GPIO DBEN: DBEN11 Position */
<> 144:ef7eb2e8f9f7 16565 #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) /*!< GPIO DBEN: DBEN11 Mask */
<> 144:ef7eb2e8f9f7 16566
<> 144:ef7eb2e8f9f7 16567 #define GPIO_DBEN_DBEN12_Pos (12) /*!< GPIO DBEN: DBEN12 Position */
<> 144:ef7eb2e8f9f7 16568 #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) /*!< GPIO DBEN: DBEN12 Mask */
<> 144:ef7eb2e8f9f7 16569
<> 144:ef7eb2e8f9f7 16570 #define GPIO_DBEN_DBEN13_Pos (13) /*!< GPIO DBEN: DBEN13 Position */
<> 144:ef7eb2e8f9f7 16571 #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) /*!< GPIO DBEN: DBEN13 Mask */
<> 144:ef7eb2e8f9f7 16572
<> 144:ef7eb2e8f9f7 16573 #define GPIO_DBEN_DBEN14_Pos (14) /*!< GPIO DBEN: DBEN14 Position */
<> 144:ef7eb2e8f9f7 16574 #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) /*!< GPIO DBEN: DBEN14 Mask */
<> 144:ef7eb2e8f9f7 16575
<> 144:ef7eb2e8f9f7 16576 #define GPIO_DBEN_DBEN15_Pos (15) /*!< GPIO DBEN: DBEN15 Position */
<> 144:ef7eb2e8f9f7 16577 #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) /*!< GPIO DBEN: DBEN15 Mask */
<> 144:ef7eb2e8f9f7 16578
<> 144:ef7eb2e8f9f7 16579 #define GPIO_INTTYPE_TYPE0_Pos (0) /*!< GPIO INTTYPE: TYPE0 Position */
<> 144:ef7eb2e8f9f7 16580 #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) /*!< GPIO INTTYPE: TYPE0 Mask */
<> 144:ef7eb2e8f9f7 16581
<> 144:ef7eb2e8f9f7 16582 #define GPIO_INTTYPE_TYPE1_Pos (1) /*!< GPIO INTTYPE: TYPE1 Position */
<> 144:ef7eb2e8f9f7 16583 #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) /*!< GPIO INTTYPE: TYPE1 Mask */
<> 144:ef7eb2e8f9f7 16584
<> 144:ef7eb2e8f9f7 16585 #define GPIO_INTTYPE_TYPE2_Pos (2) /*!< GPIO INTTYPE: TYPE2 Position */
<> 144:ef7eb2e8f9f7 16586 #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) /*!< GPIO INTTYPE: TYPE2 Mask */
<> 144:ef7eb2e8f9f7 16587
<> 144:ef7eb2e8f9f7 16588 #define GPIO_INTTYPE_TYPE3_Pos (3) /*!< GPIO INTTYPE: TYPE3 Position */
<> 144:ef7eb2e8f9f7 16589 #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) /*!< GPIO INTTYPE: TYPE3 Mask */
<> 144:ef7eb2e8f9f7 16590
<> 144:ef7eb2e8f9f7 16591 #define GPIO_INTTYPE_TYPE4_Pos (4) /*!< GPIO INTTYPE: TYPE4 Position */
<> 144:ef7eb2e8f9f7 16592 #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) /*!< GPIO INTTYPE: TYPE4 Mask */
<> 144:ef7eb2e8f9f7 16593
<> 144:ef7eb2e8f9f7 16594 #define GPIO_INTTYPE_TYPE5_Pos (5) /*!< GPIO INTTYPE: TYPE5 Position */
<> 144:ef7eb2e8f9f7 16595 #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) /*!< GPIO INTTYPE: TYPE5 Mask */
<> 144:ef7eb2e8f9f7 16596
<> 144:ef7eb2e8f9f7 16597 #define GPIO_INTTYPE_TYPE6_Pos (6) /*!< GPIO INTTYPE: TYPE6 Position */
<> 144:ef7eb2e8f9f7 16598 #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) /*!< GPIO INTTYPE: TYPE6 Mask */
<> 144:ef7eb2e8f9f7 16599
<> 144:ef7eb2e8f9f7 16600 #define GPIO_INTTYPE_TYPE7_Pos (7) /*!< GPIO INTTYPE: TYPE7 Position */
<> 144:ef7eb2e8f9f7 16601 #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) /*!< GPIO INTTYPE: TYPE7 Mask */
<> 144:ef7eb2e8f9f7 16602
<> 144:ef7eb2e8f9f7 16603 #define GPIO_INTTYPE_TYPE8_Pos (8) /*!< GPIO INTTYPE: TYPE8 Position */
<> 144:ef7eb2e8f9f7 16604 #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) /*!< GPIO INTTYPE: TYPE8 Mask */
<> 144:ef7eb2e8f9f7 16605
<> 144:ef7eb2e8f9f7 16606 #define GPIO_INTTYPE_TYPE9_Pos (9) /*!< GPIO INTTYPE: TYPE9 Position */
<> 144:ef7eb2e8f9f7 16607 #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) /*!< GPIO INTTYPE: TYPE9 Mask */
<> 144:ef7eb2e8f9f7 16608
<> 144:ef7eb2e8f9f7 16609 #define GPIO_INTTYPE_TYPE10_Pos (10) /*!< GPIO INTTYPE: TYPE10 Position */
<> 144:ef7eb2e8f9f7 16610 #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) /*!< GPIO INTTYPE: TYPE10 Mask */
<> 144:ef7eb2e8f9f7 16611
<> 144:ef7eb2e8f9f7 16612 #define GPIO_INTTYPE_TYPE11_Pos (11) /*!< GPIO INTTYPE: TYPE11 Position */
<> 144:ef7eb2e8f9f7 16613 #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) /*!< GPIO INTTYPE: TYPE11 Mask */
<> 144:ef7eb2e8f9f7 16614
<> 144:ef7eb2e8f9f7 16615 #define GPIO_INTTYPE_TYPE12_Pos (12) /*!< GPIO INTTYPE: TYPE12 Position */
<> 144:ef7eb2e8f9f7 16616 #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) /*!< GPIO INTTYPE: TYPE12 Mask */
<> 144:ef7eb2e8f9f7 16617
<> 144:ef7eb2e8f9f7 16618 #define GPIO_INTTYPE_TYPE13_Pos (13) /*!< GPIO INTTYPE: TYPE13 Position */
<> 144:ef7eb2e8f9f7 16619 #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) /*!< GPIO INTTYPE: TYPE13 Mask */
<> 144:ef7eb2e8f9f7 16620
<> 144:ef7eb2e8f9f7 16621 #define GPIO_INTTYPE_TYPE14_Pos (14) /*!< GPIO INTTYPE: TYPE14 Position */
<> 144:ef7eb2e8f9f7 16622 #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) /*!< GPIO INTTYPE: TYPE14 Mask */
<> 144:ef7eb2e8f9f7 16623
<> 144:ef7eb2e8f9f7 16624 #define GPIO_INTTYPE_TYPE15_Pos (15) /*!< GPIO INTTYPE: TYPE15 Position */
<> 144:ef7eb2e8f9f7 16625 #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) /*!< GPIO INTTYPE: TYPE15 Mask */
<> 144:ef7eb2e8f9f7 16626
<> 144:ef7eb2e8f9f7 16627 #define GPIO_INTEN_FLIEN0_Pos (0) /*!< GPIO INTEN: FLIEN0 Position */
<> 144:ef7eb2e8f9f7 16628 #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) /*!< GPIO INTEN: FLIEN0 Mask */
<> 144:ef7eb2e8f9f7 16629
<> 144:ef7eb2e8f9f7 16630 #define GPIO_INTEN_FLIEN1_Pos (1) /*!< GPIO INTEN: FLIEN1 Position */
<> 144:ef7eb2e8f9f7 16631 #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) /*!< GPIO INTEN: FLIEN1 Mask */
<> 144:ef7eb2e8f9f7 16632
<> 144:ef7eb2e8f9f7 16633 #define GPIO_INTEN_FLIEN2_Pos (2) /*!< GPIO INTEN: FLIEN2 Position */
<> 144:ef7eb2e8f9f7 16634 #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) /*!< GPIO INTEN: FLIEN2 Mask */
<> 144:ef7eb2e8f9f7 16635
<> 144:ef7eb2e8f9f7 16636 #define GPIO_INTEN_FLIEN3_Pos (3) /*!< GPIO INTEN: FLIEN3 Position */
<> 144:ef7eb2e8f9f7 16637 #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) /*!< GPIO INTEN: FLIEN3 Mask */
<> 144:ef7eb2e8f9f7 16638
<> 144:ef7eb2e8f9f7 16639 #define GPIO_INTEN_FLIEN4_Pos (4) /*!< GPIO INTEN: FLIEN4 Position */
<> 144:ef7eb2e8f9f7 16640 #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) /*!< GPIO INTEN: FLIEN4 Mask */
<> 144:ef7eb2e8f9f7 16641
<> 144:ef7eb2e8f9f7 16642 #define GPIO_INTEN_FLIEN5_Pos (5) /*!< GPIO INTEN: FLIEN5 Position */
<> 144:ef7eb2e8f9f7 16643 #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) /*!< GPIO INTEN: FLIEN5 Mask */
<> 144:ef7eb2e8f9f7 16644
<> 144:ef7eb2e8f9f7 16645 #define GPIO_INTEN_FLIEN6_Pos (6) /*!< GPIO INTEN: FLIEN6 Position */
<> 144:ef7eb2e8f9f7 16646 #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) /*!< GPIO INTEN: FLIEN6 Mask */
<> 144:ef7eb2e8f9f7 16647
<> 144:ef7eb2e8f9f7 16648 #define GPIO_INTEN_FLIEN7_Pos (7) /*!< GPIO INTEN: FLIEN7 Position */
<> 144:ef7eb2e8f9f7 16649 #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) /*!< GPIO INTEN: FLIEN7 Mask */
<> 144:ef7eb2e8f9f7 16650
<> 144:ef7eb2e8f9f7 16651 #define GPIO_INTEN_FLIEN8_Pos (8) /*!< GPIO INTEN: FLIEN8 Position */
<> 144:ef7eb2e8f9f7 16652 #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) /*!< GPIO INTEN: FLIEN8 Mask */
<> 144:ef7eb2e8f9f7 16653
<> 144:ef7eb2e8f9f7 16654 #define GPIO_INTEN_FLIEN9_Pos (9) /*!< GPIO INTEN: FLIEN9 Position */
<> 144:ef7eb2e8f9f7 16655 #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) /*!< GPIO INTEN: FLIEN9 Mask */
<> 144:ef7eb2e8f9f7 16656
<> 144:ef7eb2e8f9f7 16657 #define GPIO_INTEN_FLIEN10_Pos (10) /*!< GPIO INTEN: FLIEN10 Position */
<> 144:ef7eb2e8f9f7 16658 #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) /*!< GPIO INTEN: FLIEN10 Mask */
<> 144:ef7eb2e8f9f7 16659
<> 144:ef7eb2e8f9f7 16660 #define GPIO_INTEN_FLIEN11_Pos (11) /*!< GPIO INTEN: FLIEN11 Position */
<> 144:ef7eb2e8f9f7 16661 #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) /*!< GPIO INTEN: FLIEN11 Mask */
<> 144:ef7eb2e8f9f7 16662
<> 144:ef7eb2e8f9f7 16663 #define GPIO_INTEN_FLIEN12_Pos (12) /*!< GPIO INTEN: FLIEN12 Position */
<> 144:ef7eb2e8f9f7 16664 #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) /*!< GPIO INTEN: FLIEN12 Mask */
<> 144:ef7eb2e8f9f7 16665
<> 144:ef7eb2e8f9f7 16666 #define GPIO_INTEN_FLIEN13_Pos (13) /*!< GPIO INTEN: FLIEN13 Position */
<> 144:ef7eb2e8f9f7 16667 #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) /*!< GPIO INTEN: FLIEN13 Mask */
<> 144:ef7eb2e8f9f7 16668
<> 144:ef7eb2e8f9f7 16669 #define GPIO_INTEN_FLIEN14_Pos (14) /*!< GPIO INTEN: FLIEN14 Position */
<> 144:ef7eb2e8f9f7 16670 #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) /*!< GPIO INTEN: FLIEN14 Mask */
<> 144:ef7eb2e8f9f7 16671
<> 144:ef7eb2e8f9f7 16672 #define GPIO_INTEN_FLIEN15_Pos (15) /*!< GPIO INTEN: FLIEN15 Position */
<> 144:ef7eb2e8f9f7 16673 #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) /*!< GPIO INTEN: FLIEN15 Mask */
<> 144:ef7eb2e8f9f7 16674
<> 144:ef7eb2e8f9f7 16675 #define GPIO_INTEN_RHIEN0_Pos (16) /*!< GPIO INTEN: RHIEN0 Position */
<> 144:ef7eb2e8f9f7 16676 #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) /*!< GPIO INTEN: RHIEN0 Mask */
<> 144:ef7eb2e8f9f7 16677
<> 144:ef7eb2e8f9f7 16678 #define GPIO_INTEN_RHIEN1_Pos (17) /*!< GPIO INTEN: RHIEN1 Position */
<> 144:ef7eb2e8f9f7 16679 #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) /*!< GPIO INTEN: RHIEN1 Mask */
<> 144:ef7eb2e8f9f7 16680
<> 144:ef7eb2e8f9f7 16681 #define GPIO_INTEN_RHIEN2_Pos (18) /*!< GPIO INTEN: RHIEN2 Position */
<> 144:ef7eb2e8f9f7 16682 #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) /*!< GPIO INTEN: RHIEN2 Mask */
<> 144:ef7eb2e8f9f7 16683
<> 144:ef7eb2e8f9f7 16684 #define GPIO_INTEN_RHIEN3_Pos (19) /*!< GPIO INTEN: RHIEN3 Position */
<> 144:ef7eb2e8f9f7 16685 #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) /*!< GPIO INTEN: RHIEN3 Mask */
<> 144:ef7eb2e8f9f7 16686
<> 144:ef7eb2e8f9f7 16687 #define GPIO_INTEN_RHIEN4_Pos (20) /*!< GPIO INTEN: RHIEN4 Position */
<> 144:ef7eb2e8f9f7 16688 #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) /*!< GPIO INTEN: RHIEN4 Mask */
<> 144:ef7eb2e8f9f7 16689
<> 144:ef7eb2e8f9f7 16690 #define GPIO_INTEN_RHIEN5_Pos (21) /*!< GPIO INTEN: RHIEN5 Position */
<> 144:ef7eb2e8f9f7 16691 #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) /*!< GPIO INTEN: RHIEN5 Mask */
<> 144:ef7eb2e8f9f7 16692
<> 144:ef7eb2e8f9f7 16693 #define GPIO_INTEN_RHIEN6_Pos (22) /*!< GPIO INTEN: RHIEN6 Position */
<> 144:ef7eb2e8f9f7 16694 #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) /*!< GPIO INTEN: RHIEN6 Mask */
<> 144:ef7eb2e8f9f7 16695
<> 144:ef7eb2e8f9f7 16696 #define GPIO_INTEN_RHIEN7_Pos (23) /*!< GPIO INTEN: RHIEN7 Position */
<> 144:ef7eb2e8f9f7 16697 #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) /*!< GPIO INTEN: RHIEN7 Mask */
<> 144:ef7eb2e8f9f7 16698
<> 144:ef7eb2e8f9f7 16699 #define GPIO_INTEN_RHIEN8_Pos (24) /*!< GPIO INTEN: RHIEN8 Position */
<> 144:ef7eb2e8f9f7 16700 #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) /*!< GPIO INTEN: RHIEN8 Mask */
<> 144:ef7eb2e8f9f7 16701
<> 144:ef7eb2e8f9f7 16702 #define GPIO_INTEN_RHIEN9_Pos (25) /*!< GPIO INTEN: RHIEN9 Position */
<> 144:ef7eb2e8f9f7 16703 #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) /*!< GPIO INTEN: RHIEN9 Mask */
<> 144:ef7eb2e8f9f7 16704
<> 144:ef7eb2e8f9f7 16705 #define GPIO_INTEN_RHIEN10_Pos (26) /*!< GPIO INTEN: RHIEN10 Position */
<> 144:ef7eb2e8f9f7 16706 #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) /*!< GPIO INTEN: RHIEN10 Mask */
<> 144:ef7eb2e8f9f7 16707
<> 144:ef7eb2e8f9f7 16708 #define GPIO_INTEN_RHIEN11_Pos (27) /*!< GPIO INTEN: RHIEN11 Position */
<> 144:ef7eb2e8f9f7 16709 #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) /*!< GPIO INTEN: RHIEN11 Mask */
<> 144:ef7eb2e8f9f7 16710
<> 144:ef7eb2e8f9f7 16711 #define GPIO_INTEN_RHIEN12_Pos (28) /*!< GPIO INTEN: RHIEN12 Position */
<> 144:ef7eb2e8f9f7 16712 #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) /*!< GPIO INTEN: RHIEN12 Mask */
<> 144:ef7eb2e8f9f7 16713
<> 144:ef7eb2e8f9f7 16714 #define GPIO_INTEN_RHIEN13_Pos (29) /*!< GPIO INTEN: RHIEN13 Position */
<> 144:ef7eb2e8f9f7 16715 #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) /*!< GPIO INTEN: RHIEN13 Mask */
<> 144:ef7eb2e8f9f7 16716
<> 144:ef7eb2e8f9f7 16717 #define GPIO_INTEN_RHIEN14_Pos (30) /*!< GPIO INTEN: RHIEN14 Position */
<> 144:ef7eb2e8f9f7 16718 #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) /*!< GPIO INTEN: RHIEN14 Mask */
<> 144:ef7eb2e8f9f7 16719
<> 144:ef7eb2e8f9f7 16720 #define GPIO_INTEN_RHIEN15_Pos (31) /*!< GPIO INTEN: RHIEN15 Position */
<> 144:ef7eb2e8f9f7 16721 #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) /*!< GPIO INTEN: RHIEN15 Mask */
<> 144:ef7eb2e8f9f7 16722
<> 144:ef7eb2e8f9f7 16723 #define GPIO_INTSRC_INTSRC0_Pos (0) /*!< GPIO INTSRC: INTSRC0 Position */
<> 144:ef7eb2e8f9f7 16724 #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) /*!< GPIO INTSRC: INTSRC0 Mask */
<> 144:ef7eb2e8f9f7 16725
<> 144:ef7eb2e8f9f7 16726 #define GPIO_INTSRC_INTSRC1_Pos (1) /*!< GPIO INTSRC: INTSRC1 Position */
<> 144:ef7eb2e8f9f7 16727 #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) /*!< GPIO INTSRC: INTSRC1 Mask */
<> 144:ef7eb2e8f9f7 16728
<> 144:ef7eb2e8f9f7 16729 #define GPIO_INTSRC_INTSRC2_Pos (2) /*!< GPIO INTSRC: INTSRC2 Position */
<> 144:ef7eb2e8f9f7 16730 #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) /*!< GPIO INTSRC: INTSRC2 Mask */
<> 144:ef7eb2e8f9f7 16731
<> 144:ef7eb2e8f9f7 16732 #define GPIO_INTSRC_INTSRC3_Pos (3) /*!< GPIO INTSRC: INTSRC3 Position */
<> 144:ef7eb2e8f9f7 16733 #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) /*!< GPIO INTSRC: INTSRC3 Mask */
<> 144:ef7eb2e8f9f7 16734
<> 144:ef7eb2e8f9f7 16735 #define GPIO_INTSRC_INTSRC4_Pos (4) /*!< GPIO INTSRC: INTSRC4 Position */
<> 144:ef7eb2e8f9f7 16736 #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) /*!< GPIO INTSRC: INTSRC4 Mask */
<> 144:ef7eb2e8f9f7 16737
<> 144:ef7eb2e8f9f7 16738 #define GPIO_INTSRC_INTSRC5_Pos (5) /*!< GPIO INTSRC: INTSRC5 Position */
<> 144:ef7eb2e8f9f7 16739 #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) /*!< GPIO INTSRC: INTSRC5 Mask */
<> 144:ef7eb2e8f9f7 16740
<> 144:ef7eb2e8f9f7 16741 #define GPIO_INTSRC_INTSRC6_Pos (6) /*!< GPIO INTSRC: INTSRC6 Position */
<> 144:ef7eb2e8f9f7 16742 #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) /*!< GPIO INTSRC: INTSRC6 Mask */
<> 144:ef7eb2e8f9f7 16743
<> 144:ef7eb2e8f9f7 16744 #define GPIO_INTSRC_INTSRC7_Pos (7) /*!< GPIO INTSRC: INTSRC7 Position */
<> 144:ef7eb2e8f9f7 16745 #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) /*!< GPIO INTSRC: INTSRC7 Mask */
<> 144:ef7eb2e8f9f7 16746
<> 144:ef7eb2e8f9f7 16747 #define GPIO_INTSRC_INTSRC8_Pos (8) /*!< GPIO INTSRC: INTSRC8 Position */
<> 144:ef7eb2e8f9f7 16748 #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) /*!< GPIO INTSRC: INTSRC8 Mask */
<> 144:ef7eb2e8f9f7 16749
<> 144:ef7eb2e8f9f7 16750 #define GPIO_INTSRC_INTSRC9_Pos (9) /*!< GPIO INTSRC: INTSRC9 Position */
<> 144:ef7eb2e8f9f7 16751 #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) /*!< GPIO INTSRC: INTSRC9 Mask */
<> 144:ef7eb2e8f9f7 16752
<> 144:ef7eb2e8f9f7 16753 #define GPIO_INTSRC_INTSRC10_Pos (10) /*!< GPIO INTSRC: INTSRC10 Position */
<> 144:ef7eb2e8f9f7 16754 #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) /*!< GPIO INTSRC: INTSRC10 Mask */
<> 144:ef7eb2e8f9f7 16755
<> 144:ef7eb2e8f9f7 16756 #define GPIO_INTSRC_INTSRC11_Pos (11) /*!< GPIO INTSRC: INTSRC11 Position */
<> 144:ef7eb2e8f9f7 16757 #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) /*!< GPIO INTSRC: INTSRC11 Mask */
<> 144:ef7eb2e8f9f7 16758
<> 144:ef7eb2e8f9f7 16759 #define GPIO_INTSRC_INTSRC12_Pos (12) /*!< GPIO INTSRC: INTSRC12 Position */
<> 144:ef7eb2e8f9f7 16760 #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) /*!< GPIO INTSRC: INTSRC12 Mask */
<> 144:ef7eb2e8f9f7 16761
<> 144:ef7eb2e8f9f7 16762 #define GPIO_INTSRC_INTSRC13_Pos (13) /*!< GPIO INTSRC: INTSRC13 Position */
<> 144:ef7eb2e8f9f7 16763 #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) /*!< GPIO INTSRC: INTSRC13 Mask */
<> 144:ef7eb2e8f9f7 16764
<> 144:ef7eb2e8f9f7 16765 #define GPIO_INTSRC_INTSRC14_Pos (14) /*!< GPIO INTSRC: INTSRC14 Position */
<> 144:ef7eb2e8f9f7 16766 #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) /*!< GPIO INTSRC: INTSRC14 Mask */
<> 144:ef7eb2e8f9f7 16767
<> 144:ef7eb2e8f9f7 16768 #define GPIO_INTSRC_INTSRC15_Pos (15) /*!< GPIO INTSRC: INTSRC15 Position */
<> 144:ef7eb2e8f9f7 16769 #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) /*!< GPIO INTSRC: INTSRC15 Mask */
<> 144:ef7eb2e8f9f7 16770
<> 144:ef7eb2e8f9f7 16771 #define GPIO_SMTEN_SMTEN0_Pos (0) /*!< GPIO SMTEN: SMTEN0 Position */
<> 144:ef7eb2e8f9f7 16772 #define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) /*!< GPIO SMTEN: SMTEN0 Mask */
<> 144:ef7eb2e8f9f7 16773
<> 144:ef7eb2e8f9f7 16774 #define GPIO_SMTEN_SMTEN1_Pos (1) /*!< GPIO SMTEN: SMTEN1 Position */
<> 144:ef7eb2e8f9f7 16775 #define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) /*!< GPIO SMTEN: SMTEN1 Mask */
<> 144:ef7eb2e8f9f7 16776
<> 144:ef7eb2e8f9f7 16777 #define GPIO_SMTEN_SMTEN2_Pos (2) /*!< GPIO SMTEN: SMTEN2 Position */
<> 144:ef7eb2e8f9f7 16778 #define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) /*!< GPIO SMTEN: SMTEN2 Mask */
<> 144:ef7eb2e8f9f7 16779
<> 144:ef7eb2e8f9f7 16780 #define GPIO_SMTEN_SMTEN3_Pos (3) /*!< GPIO SMTEN: SMTEN3 Position */
<> 144:ef7eb2e8f9f7 16781 #define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) /*!< GPIO SMTEN: SMTEN3 Mask */
<> 144:ef7eb2e8f9f7 16782
<> 144:ef7eb2e8f9f7 16783 #define GPIO_SMTEN_SMTEN4_Pos (4) /*!< GPIO SMTEN: SMTEN4 Position */
<> 144:ef7eb2e8f9f7 16784 #define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) /*!< GPIO SMTEN: SMTEN4 Mask */
<> 144:ef7eb2e8f9f7 16785
<> 144:ef7eb2e8f9f7 16786 #define GPIO_SMTEN_SMTEN5_Pos (5) /*!< GPIO SMTEN: SMTEN5 Position */
<> 144:ef7eb2e8f9f7 16787 #define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) /*!< GPIO SMTEN: SMTEN5 Mask */
<> 144:ef7eb2e8f9f7 16788
<> 144:ef7eb2e8f9f7 16789 #define GPIO_SMTEN_SMTEN6_Pos (6) /*!< GPIO SMTEN: SMTEN6 Position */
<> 144:ef7eb2e8f9f7 16790 #define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) /*!< GPIO SMTEN: SMTEN6 Mask */
<> 144:ef7eb2e8f9f7 16791
<> 144:ef7eb2e8f9f7 16792 #define GPIO_SMTEN_SMTEN7_Pos (7) /*!< GPIO SMTEN: SMTEN7 Position */
<> 144:ef7eb2e8f9f7 16793 #define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) /*!< GPIO SMTEN: SMTEN7 Mask */
<> 144:ef7eb2e8f9f7 16794
<> 144:ef7eb2e8f9f7 16795 #define GPIO_SMTEN_SMTEN8_Pos (8) /*!< GPIO SMTEN: SMTEN8 Position */
<> 144:ef7eb2e8f9f7 16796 #define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) /*!< GPIO SMTEN: SMTEN8 Mask */
<> 144:ef7eb2e8f9f7 16797
<> 144:ef7eb2e8f9f7 16798 #define GPIO_SMTEN_SMTEN9_Pos (9) /*!< GPIO SMTEN: SMTEN9 Position */
<> 144:ef7eb2e8f9f7 16799 #define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) /*!< GPIO SMTEN: SMTEN9 Mask */
<> 144:ef7eb2e8f9f7 16800
<> 144:ef7eb2e8f9f7 16801 #define GPIO_SMTEN_SMTEN10_Pos (10) /*!< GPIO SMTEN: SMTEN10 Position */
<> 144:ef7eb2e8f9f7 16802 #define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) /*!< GPIO SMTEN: SMTEN10 Mask */
<> 144:ef7eb2e8f9f7 16803
<> 144:ef7eb2e8f9f7 16804 #define GPIO_SMTEN_SMTEN11_Pos (11) /*!< GPIO SMTEN: SMTEN11 Position */
<> 144:ef7eb2e8f9f7 16805 #define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) /*!< GPIO SMTEN: SMTEN11 Mask */
<> 144:ef7eb2e8f9f7 16806
<> 144:ef7eb2e8f9f7 16807 #define GPIO_SMTEN_SMTEN12_Pos (12) /*!< GPIO SMTEN: SMTEN12 Position */
<> 144:ef7eb2e8f9f7 16808 #define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) /*!< GPIO SMTEN: SMTEN12 Mask */
<> 144:ef7eb2e8f9f7 16809
<> 144:ef7eb2e8f9f7 16810 #define GPIO_SMTEN_SMTEN13_Pos (13) /*!< GPIO SMTEN: SMTEN13 Position */
<> 144:ef7eb2e8f9f7 16811 #define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) /*!< GPIO SMTEN: SMTEN13 Mask */
<> 144:ef7eb2e8f9f7 16812
<> 144:ef7eb2e8f9f7 16813 #define GPIO_SMTEN_SMTEN14_Pos (14) /*!< GPIO SMTEN: SMTEN14 Position */
<> 144:ef7eb2e8f9f7 16814 #define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) /*!< GPIO SMTEN: SMTEN14 Mask */
<> 144:ef7eb2e8f9f7 16815
<> 144:ef7eb2e8f9f7 16816 #define GPIO_SMTEN_SMTEN15_Pos (15) /*!< GPIO SMTEN: SMTEN15 Position */
<> 144:ef7eb2e8f9f7 16817 #define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) /*!< GPIO SMTEN: SMTEN15 Mask */
<> 144:ef7eb2e8f9f7 16818
<> 144:ef7eb2e8f9f7 16819 #define GPIO_SLEWCTL_HSREN0_Pos (0) /*!< GPIO SLEWCTL: HSREN0 Position */
<> 144:ef7eb2e8f9f7 16820 #define GPIO_SLEWCTL_HSREN0_Msk (0x1ul << GPIO_SLEWCTL_HSREN0_Pos) /*!< GPIO SLEWCTL: HSREN0 Mask */
<> 144:ef7eb2e8f9f7 16821
<> 144:ef7eb2e8f9f7 16822 #define GPIO_SLEWCTL_HSREN1_Pos (1) /*!< GPIO SLEWCTL: HSREN1 Position */
<> 144:ef7eb2e8f9f7 16823 #define GPIO_SLEWCTL_HSREN1_Msk (0x1ul << GPIO_SLEWCTL_HSREN1_Pos) /*!< GPIO SLEWCTL: HSREN1 Mask */
<> 144:ef7eb2e8f9f7 16824
<> 144:ef7eb2e8f9f7 16825 #define GPIO_SLEWCTL_HSREN2_Pos (2) /*!< GPIO SLEWCTL: HSREN2 Position */
<> 144:ef7eb2e8f9f7 16826 #define GPIO_SLEWCTL_HSREN2_Msk (0x1ul << GPIO_SLEWCTL_HSREN2_Pos) /*!< GPIO SLEWCTL: HSREN2 Mask */
<> 144:ef7eb2e8f9f7 16827
<> 144:ef7eb2e8f9f7 16828 #define GPIO_SLEWCTL_HSREN3_Pos (3) /*!< GPIO SLEWCTL: HSREN3 Position */
<> 144:ef7eb2e8f9f7 16829 #define GPIO_SLEWCTL_HSREN3_Msk (0x1ul << GPIO_SLEWCTL_HSREN3_Pos) /*!< GPIO SLEWCTL: HSREN3 Mask */
<> 144:ef7eb2e8f9f7 16830
<> 144:ef7eb2e8f9f7 16831 #define GPIO_SLEWCTL_HSREN4_Pos (4) /*!< GPIO SLEWCTL: HSREN4 Position */
<> 144:ef7eb2e8f9f7 16832 #define GPIO_SLEWCTL_HSREN4_Msk (0x1ul << GPIO_SLEWCTL_HSREN4_Pos) /*!< GPIO SLEWCTL: HSREN4 Mask */
<> 144:ef7eb2e8f9f7 16833
<> 144:ef7eb2e8f9f7 16834 #define GPIO_SLEWCTL_HSREN5_Pos (5) /*!< GPIO SLEWCTL: HSREN5 Position */
<> 144:ef7eb2e8f9f7 16835 #define GPIO_SLEWCTL_HSREN5_Msk (0x1ul << GPIO_SLEWCTL_HSREN5_Pos) /*!< GPIO SLEWCTL: HSREN5 Mask */
<> 144:ef7eb2e8f9f7 16836
<> 144:ef7eb2e8f9f7 16837 #define GPIO_SLEWCTL_HSREN6_Pos (6) /*!< GPIO SLEWCTL: HSREN6 Position */
<> 144:ef7eb2e8f9f7 16838 #define GPIO_SLEWCTL_HSREN6_Msk (0x1ul << GPIO_SLEWCTL_HSREN6_Pos) /*!< GPIO SLEWCTL: HSREN6 Mask */
<> 144:ef7eb2e8f9f7 16839
<> 144:ef7eb2e8f9f7 16840 #define GPIO_SLEWCTL_HSREN7_Pos (7) /*!< GPIO SLEWCTL: HSREN7 Position */
<> 144:ef7eb2e8f9f7 16841 #define GPIO_SLEWCTL_HSREN7_Msk (0x1ul << GPIO_SLEWCTL_HSREN7_Pos) /*!< GPIO SLEWCTL: HSREN7 Mask */
<> 144:ef7eb2e8f9f7 16842
<> 144:ef7eb2e8f9f7 16843 #define GPIO_SLEWCTL_HSREN8_Pos (8) /*!< GPIO SLEWCTL: HSREN8 Position */
<> 144:ef7eb2e8f9f7 16844 #define GPIO_SLEWCTL_HSREN8_Msk (0x1ul << GPIO_SLEWCTL_HSREN8_Pos) /*!< GPIO SLEWCTL: HSREN8 Mask */
<> 144:ef7eb2e8f9f7 16845
<> 144:ef7eb2e8f9f7 16846 #define GPIO_SLEWCTL_HSREN9_Pos (9) /*!< GPIO SLEWCTL: HSREN9 Position */
<> 144:ef7eb2e8f9f7 16847 #define GPIO_SLEWCTL_HSREN9_Msk (0x1ul << GPIO_SLEWCTL_HSREN9_Pos) /*!< GPIO SLEWCTL: HSREN9 Mask */
<> 144:ef7eb2e8f9f7 16848
<> 144:ef7eb2e8f9f7 16849 #define GPIO_SLEWCTL_HSREN10_Pos (10) /*!< GPIO SLEWCTL: HSREN10 Position */
<> 144:ef7eb2e8f9f7 16850 #define GPIO_SLEWCTL_HSREN10_Msk (0x1ul << GPIO_SLEWCTL_HSREN10_Pos) /*!< GPIO SLEWCTL: HSREN10 Mask */
<> 144:ef7eb2e8f9f7 16851
<> 144:ef7eb2e8f9f7 16852 #define GPIO_SLEWCTL_HSREN11_Pos (11) /*!< GPIO SLEWCTL: HSREN11 Position */
<> 144:ef7eb2e8f9f7 16853 #define GPIO_SLEWCTL_HSREN11_Msk (0x1ul << GPIO_SLEWCTL_HSREN11_Pos) /*!< GPIO SLEWCTL: HSREN11 Mask */
<> 144:ef7eb2e8f9f7 16854
<> 144:ef7eb2e8f9f7 16855 #define GPIO_SLEWCTL_HSREN12_Pos (12) /*!< GPIO SLEWCTL: HSREN12 Position */
<> 144:ef7eb2e8f9f7 16856 #define GPIO_SLEWCTL_HSREN12_Msk (0x1ul << GPIO_SLEWCTL_HSREN12_Pos) /*!< GPIO SLEWCTL: HSREN12 Mask */
<> 144:ef7eb2e8f9f7 16857
<> 144:ef7eb2e8f9f7 16858 #define GPIO_SLEWCTL_HSREN13_Pos (13) /*!< GPIO SLEWCTL: HSREN13 Position */
<> 144:ef7eb2e8f9f7 16859 #define GPIO_SLEWCTL_HSREN13_Msk (0x1ul << GPIO_SLEWCTL_HSREN13_Pos) /*!< GPIO SLEWCTL: HSREN13 Mask */
<> 144:ef7eb2e8f9f7 16860
<> 144:ef7eb2e8f9f7 16861 #define GPIO_SLEWCTL_HSREN14_Pos (14) /*!< GPIO SLEWCTL: HSREN14 Position */
<> 144:ef7eb2e8f9f7 16862 #define GPIO_SLEWCTL_HSREN14_Msk (0x1ul << GPIO_SLEWCTL_HSREN14_Pos) /*!< GPIO SLEWCTL: HSREN14 Mask */
<> 144:ef7eb2e8f9f7 16863
<> 144:ef7eb2e8f9f7 16864 #define GPIO_SLEWCTL_HSREN15_Pos (15) /*!< GPIO SLEWCTL: HSREN15 Position */
<> 144:ef7eb2e8f9f7 16865 #define GPIO_SLEWCTL_HSREN15_Msk (0x1ul << GPIO_SLEWCTL_HSREN15_Pos) /*!< GPIO SLEWCTL: HSREN15 Mask */
<> 144:ef7eb2e8f9f7 16866
<> 144:ef7eb2e8f9f7 16867 #define GPIO_DBCTL_DBCLKSEL_Pos (0) /*!< GPIO DBCTL: DBCLKSEL Position */
<> 144:ef7eb2e8f9f7 16868 #define GPIO_DBCTL_DBCLKSEL_Msk (0xful << GPIO_DBCTL_DBCLKSEL_Pos) /*!< GPIO DBCTL: DBCLKSEL Mask */
<> 144:ef7eb2e8f9f7 16869
<> 144:ef7eb2e8f9f7 16870 #define GPIO_DBCTL_DBCLKSRC_Pos (4) /*!< GPIO DBCTL: DBCLKSRC Position */
<> 144:ef7eb2e8f9f7 16871 #define GPIO_DBCTL_DBCLKSRC_Msk (0x1ul << GPIO_DBCTL_DBCLKSRC_Pos) /*!< GPIO DBCTL: DBCLKSRC Mask */
<> 144:ef7eb2e8f9f7 16872
<> 144:ef7eb2e8f9f7 16873 #define GPIO_DBCTL_ICLKON_Pos (5) /*!< GPIO DBCTL: ICLKON Position */
<> 144:ef7eb2e8f9f7 16874 #define GPIO_DBCTL_ICLKON_Msk (0x1ul << GPIO_DBCTL_ICLKON_Pos) /*!< GPIO DBCTL: ICLKON Mask */
<> 144:ef7eb2e8f9f7 16875
<> 144:ef7eb2e8f9f7 16876 /**@}*/ /* GPIO_CONST */
<> 144:ef7eb2e8f9f7 16877 /**@}*/ /* end of GPIO register group */
<> 144:ef7eb2e8f9f7 16878
<> 144:ef7eb2e8f9f7 16879
<> 144:ef7eb2e8f9f7 16880 /*---------------------- Inter-IC Bus Controller -------------------------*/
<> 144:ef7eb2e8f9f7 16881 /**
<> 144:ef7eb2e8f9f7 16882 @addtogroup I2C Inter-IC Bus Controller(I2C)
<> 144:ef7eb2e8f9f7 16883 Memory Mapped Structure for I2C Controller
<> 144:ef7eb2e8f9f7 16884 @{ */
<> 144:ef7eb2e8f9f7 16885
<> 144:ef7eb2e8f9f7 16886 typedef struct {
<> 144:ef7eb2e8f9f7 16887
<> 144:ef7eb2e8f9f7 16888
<> 144:ef7eb2e8f9f7 16889 /**
<> 144:ef7eb2e8f9f7 16890 * CTL
<> 144:ef7eb2e8f9f7 16891 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16892 * Offset: 0x00 I2C Control Register
<> 144:ef7eb2e8f9f7 16893 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16894 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16895 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16896 * |[2] |AA |Assert Acknowledge Control
<> 144:ef7eb2e8f9f7 16897 * | | |When AA =1 prior to address or data received, an acknowledged (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
<> 144:ef7eb2e8f9f7 16898 * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line.
<> 144:ef7eb2e8f9f7 16899 * |[3] |SI |I2C Interrupt Flag
<> 144:ef7eb2e8f9f7 16900 * | | |When a new I2C state is present in the I2C_STATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested.
<> 144:ef7eb2e8f9f7 16901 * | | |SI must be cleared by software.
<> 144:ef7eb2e8f9f7 16902 * | | |Clear SI by writing 1 to this bit.
<> 144:ef7eb2e8f9f7 16903 * |[4] |STO |I2C STOP Control
<> 144:ef7eb2e8f9f7 16904 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically.
<> 144:ef7eb2e8f9f7 16905 * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode.
<> 144:ef7eb2e8f9f7 16906 * | | |This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
<> 144:ef7eb2e8f9f7 16907 * |[5] |STA |I2C START Control
<> 144:ef7eb2e8f9f7 16908 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
<> 144:ef7eb2e8f9f7 16909 * |[6] |I2CEN |I2C Controller Enable Control
<> 144:ef7eb2e8f9f7 16910 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 16911 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 16912 * | | |Set to enable I2C serial function controller.
<> 144:ef7eb2e8f9f7 16913 * | | |When ENS1=1 the I2C serial function enables.
<> 144:ef7eb2e8f9f7 16914 * | | |The multi-function pin function of SDA and SCL must set to I2C function first.
<> 144:ef7eb2e8f9f7 16915 * |[7] |INTEN |I2C Interrupt Enable Control
<> 144:ef7eb2e8f9f7 16916 * | | |0 = I2C interrupt Disabled.
<> 144:ef7eb2e8f9f7 16917 * | | |1 = I2C interrupt Enabled.
<> 144:ef7eb2e8f9f7 16918 */
<> 144:ef7eb2e8f9f7 16919 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 16920
<> 144:ef7eb2e8f9f7 16921 /**
<> 144:ef7eb2e8f9f7 16922 * ADDR0
<> 144:ef7eb2e8f9f7 16923 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16924 * Offset: 0x04 I2C Slave Address Register0
<> 144:ef7eb2e8f9f7 16925 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16926 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16927 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16928 * |[0] |GC |General Call Function
<> 144:ef7eb2e8f9f7 16929 * | | |0 = General Call Function Disabled.
<> 144:ef7eb2e8f9f7 16930 * | | |1 = General Call Function Enabled.
<> 144:ef7eb2e8f9f7 16931 * |[1:7] |ADDR |I2C Address Bits
<> 144:ef7eb2e8f9f7 16932 * | | |The content of this register is irrelevant when I2C is in Master mode.
<> 144:ef7eb2e8f9f7 16933 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
<> 144:ef7eb2e8f9f7 16934 * | | |The I2C hardware will react if either of the address is matched.
<> 144:ef7eb2e8f9f7 16935 */
<> 144:ef7eb2e8f9f7 16936 __IO uint32_t ADDR0;
<> 144:ef7eb2e8f9f7 16937
<> 144:ef7eb2e8f9f7 16938 /**
<> 144:ef7eb2e8f9f7 16939 * DAT
<> 144:ef7eb2e8f9f7 16940 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16941 * Offset: 0x08 I2C Data Register
<> 144:ef7eb2e8f9f7 16942 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16943 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16944 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16945 * |[0:7] |DAT |I2C Data Bits
<> 144:ef7eb2e8f9f7 16946 * | | |Bit [7:0] is located with the 8-bit transferred data of I2C serial port.
<> 144:ef7eb2e8f9f7 16947 */
<> 144:ef7eb2e8f9f7 16948 __IO uint32_t DAT;
<> 144:ef7eb2e8f9f7 16949
<> 144:ef7eb2e8f9f7 16950 /**
<> 144:ef7eb2e8f9f7 16951 * STATUS
<> 144:ef7eb2e8f9f7 16952 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16953 * Offset: 0x0C I2C Status Register
<> 144:ef7eb2e8f9f7 16954 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16955 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16956 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16957 * |[0:7] |STATUS |I2C Status Bits
<> 144:ef7eb2e8f9f7 16958 * | | |The status register of I2C:
<> 144:ef7eb2e8f9f7 16959 * | | |The three least significant bits are always 0.
<> 144:ef7eb2e8f9f7 16960 * | | |The five most significant bits contain the status code.
<> 144:ef7eb2e8f9f7 16961 * | | |Refer to section 6.15.5.4 for detail description.
<> 144:ef7eb2e8f9f7 16962 */
<> 144:ef7eb2e8f9f7 16963 __I uint32_t STATUS;
<> 144:ef7eb2e8f9f7 16964
<> 144:ef7eb2e8f9f7 16965 /**
<> 144:ef7eb2e8f9f7 16966 * CLKDIV
<> 144:ef7eb2e8f9f7 16967 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16968 * Offset: 0x10 I2C Clock Divided Register
<> 144:ef7eb2e8f9f7 16969 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16970 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16971 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16972 * |[0:7] |DIVIDER |I2C Clock Divided Bits
<> 144:ef7eb2e8f9f7 16973 * | | |The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4x (I2CLK+1)).
<> 144:ef7eb2e8f9f7 16974 * | | |Note: The minimum value of I2CLK is 4.
<> 144:ef7eb2e8f9f7 16975 */
<> 144:ef7eb2e8f9f7 16976 __IO uint32_t CLKDIV;
<> 144:ef7eb2e8f9f7 16977
<> 144:ef7eb2e8f9f7 16978 /**
<> 144:ef7eb2e8f9f7 16979 * TOCTL
<> 144:ef7eb2e8f9f7 16980 * ===================================================================================================
<> 144:ef7eb2e8f9f7 16981 * Offset: 0x14 I2C Time-out Control Register
<> 144:ef7eb2e8f9f7 16982 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 16983 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 16984 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 16985 * |[0] |TOIF |Time-Out Flag
<> 144:ef7eb2e8f9f7 16986 * | | |This bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI (I2CON[7])) is set to 1.
<> 144:ef7eb2e8f9f7 16987 * | | |Note: Write 1 to clear this bit.
<> 144:ef7eb2e8f9f7 16988 * |[1] |TOCDIV4 |Time-Out Counter Input Clock Divided By 4
<> 144:ef7eb2e8f9f7 16989 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 16990 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 16991 * | | |When Enabled, The time-out period is extend 4 times.
<> 144:ef7eb2e8f9f7 16992 * |[2] |TOCEN |Time-Out Counter Enable Control
<> 144:ef7eb2e8f9f7 16993 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 16994 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 16995 * | | |When Enabled, the 14-bit time-out counter will start counting when SI (I2CON[3]) is clear.
<> 144:ef7eb2e8f9f7 16996 * | | |Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
<> 144:ef7eb2e8f9f7 16997 */
<> 144:ef7eb2e8f9f7 16998 __IO uint32_t TOCTL;
<> 144:ef7eb2e8f9f7 16999
<> 144:ef7eb2e8f9f7 17000 /**
<> 144:ef7eb2e8f9f7 17001 * ADDR1
<> 144:ef7eb2e8f9f7 17002 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17003 * Offset: 0x18 I2C Slave Address Register1
<> 144:ef7eb2e8f9f7 17004 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17005 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17006 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17007 * |[0] |GC |General Call Function
<> 144:ef7eb2e8f9f7 17008 * | | |0 = General Call Function Disabled.
<> 144:ef7eb2e8f9f7 17009 * | | |1 = General Call Function Enabled.
<> 144:ef7eb2e8f9f7 17010 * |[1:7] |ADDR |I2C Address Bits
<> 144:ef7eb2e8f9f7 17011 * | | |The content of this register is irrelevant when I2C is in Master mode.
<> 144:ef7eb2e8f9f7 17012 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
<> 144:ef7eb2e8f9f7 17013 * | | |The I2C hardware will react if either of the address is matched.
<> 144:ef7eb2e8f9f7 17014 */
<> 144:ef7eb2e8f9f7 17015 __IO uint32_t ADDR1;
<> 144:ef7eb2e8f9f7 17016
<> 144:ef7eb2e8f9f7 17017 /**
<> 144:ef7eb2e8f9f7 17018 * ADDR2
<> 144:ef7eb2e8f9f7 17019 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17020 * Offset: 0x1C I2C Slave Address Register2
<> 144:ef7eb2e8f9f7 17021 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17022 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17023 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17024 * |[0] |GC |General Call Function
<> 144:ef7eb2e8f9f7 17025 * | | |0 = General Call Function Disabled.
<> 144:ef7eb2e8f9f7 17026 * | | |1 = General Call Function Enabled.
<> 144:ef7eb2e8f9f7 17027 * |[1:7] |ADDR |I2C Address Bits
<> 144:ef7eb2e8f9f7 17028 * | | |The content of this register is irrelevant when I2C is in Master mode.
<> 144:ef7eb2e8f9f7 17029 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
<> 144:ef7eb2e8f9f7 17030 * | | |The I2C hardware will react if either of the address is matched.
<> 144:ef7eb2e8f9f7 17031 */
<> 144:ef7eb2e8f9f7 17032 __IO uint32_t ADDR2;
<> 144:ef7eb2e8f9f7 17033
<> 144:ef7eb2e8f9f7 17034 /**
<> 144:ef7eb2e8f9f7 17035 * ADDR3
<> 144:ef7eb2e8f9f7 17036 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17037 * Offset: 0x20 I2C Slave Address Register3
<> 144:ef7eb2e8f9f7 17038 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17039 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17040 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17041 * |[0] |GC |General Call Function
<> 144:ef7eb2e8f9f7 17042 * | | |0 = General Call Function Disabled.
<> 144:ef7eb2e8f9f7 17043 * | | |1 = General Call Function Enabled.
<> 144:ef7eb2e8f9f7 17044 * |[1:7] |ADDR |I2C Address Bits
<> 144:ef7eb2e8f9f7 17045 * | | |The content of this register is irrelevant when I2C is in Master mode.
<> 144:ef7eb2e8f9f7 17046 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
<> 144:ef7eb2e8f9f7 17047 * | | |The I2C hardware will react if either of the address is matched.
<> 144:ef7eb2e8f9f7 17048 */
<> 144:ef7eb2e8f9f7 17049 __IO uint32_t ADDR3;
<> 144:ef7eb2e8f9f7 17050
<> 144:ef7eb2e8f9f7 17051 /**
<> 144:ef7eb2e8f9f7 17052 * ADDRMSK0
<> 144:ef7eb2e8f9f7 17053 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17054 * Offset: 0x24 I2C Slave Address Mask Register0
<> 144:ef7eb2e8f9f7 17055 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17056 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17057 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17058 * |[1:7] |ADDRMSK |I2C Address Mask Bits
<> 144:ef7eb2e8f9f7 17059 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
<> 144:ef7eb2e8f9f7 17060 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
<> 144:ef7eb2e8f9f7 17061 * | | |I2C bus controllers support multiple address recognition with four address mask register.
<> 144:ef7eb2e8f9f7 17062 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
<> 144:ef7eb2e8f9f7 17063 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
<> 144:ef7eb2e8f9f7 17064 */
<> 144:ef7eb2e8f9f7 17065 __IO uint32_t ADDRMSK0;
<> 144:ef7eb2e8f9f7 17066
<> 144:ef7eb2e8f9f7 17067 /**
<> 144:ef7eb2e8f9f7 17068 * ADDRMSK1
<> 144:ef7eb2e8f9f7 17069 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17070 * Offset: 0x28 I2C Slave Address Mask Register1
<> 144:ef7eb2e8f9f7 17071 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17072 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17073 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17074 * |[1:7] |ADDRMSK |I2C Address Mask Bits
<> 144:ef7eb2e8f9f7 17075 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
<> 144:ef7eb2e8f9f7 17076 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
<> 144:ef7eb2e8f9f7 17077 * | | |I2C bus controllers support multiple address recognition with four address mask register.
<> 144:ef7eb2e8f9f7 17078 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
<> 144:ef7eb2e8f9f7 17079 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
<> 144:ef7eb2e8f9f7 17080 */
<> 144:ef7eb2e8f9f7 17081 __IO uint32_t ADDRMSK1;
<> 144:ef7eb2e8f9f7 17082
<> 144:ef7eb2e8f9f7 17083 /**
<> 144:ef7eb2e8f9f7 17084 * ADDRMSK2
<> 144:ef7eb2e8f9f7 17085 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17086 * Offset: 0x2C I2C Slave Address Mask Register2
<> 144:ef7eb2e8f9f7 17087 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17088 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17089 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17090 * |[1:7] |ADDRMSK |I2C Address Mask Bits
<> 144:ef7eb2e8f9f7 17091 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
<> 144:ef7eb2e8f9f7 17092 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
<> 144:ef7eb2e8f9f7 17093 * | | |I2C bus controllers support multiple address recognition with four address mask register.
<> 144:ef7eb2e8f9f7 17094 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
<> 144:ef7eb2e8f9f7 17095 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
<> 144:ef7eb2e8f9f7 17096 */
<> 144:ef7eb2e8f9f7 17097 __IO uint32_t ADDRMSK2;
<> 144:ef7eb2e8f9f7 17098
<> 144:ef7eb2e8f9f7 17099 /**
<> 144:ef7eb2e8f9f7 17100 * ADDRMSK3
<> 144:ef7eb2e8f9f7 17101 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17102 * Offset: 0x30 I2C Slave Address Mask Register3
<> 144:ef7eb2e8f9f7 17103 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17104 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17105 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17106 * |[1:7] |ADDRMSK |I2C Address Mask Bits
<> 144:ef7eb2e8f9f7 17107 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
<> 144:ef7eb2e8f9f7 17108 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
<> 144:ef7eb2e8f9f7 17109 * | | |I2C bus controllers support multiple address recognition with four address mask register.
<> 144:ef7eb2e8f9f7 17110 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
<> 144:ef7eb2e8f9f7 17111 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
<> 144:ef7eb2e8f9f7 17112 */
<> 144:ef7eb2e8f9f7 17113 __IO uint32_t ADDRMSK3;
<> 144:ef7eb2e8f9f7 17114 uint32_t RESERVE0[2];
<> 144:ef7eb2e8f9f7 17115
<> 144:ef7eb2e8f9f7 17116
<> 144:ef7eb2e8f9f7 17117 /**
<> 144:ef7eb2e8f9f7 17118 * WKCTL
<> 144:ef7eb2e8f9f7 17119 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17120 * Offset: 0x3C I2C Wake-up Control Register
<> 144:ef7eb2e8f9f7 17121 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17122 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17123 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17124 * |[0] |WKEN |I2C Wake-Up Enable Control
<> 144:ef7eb2e8f9f7 17125 * | | |0 = I2C wake-up function Disabled.
<> 144:ef7eb2e8f9f7 17126 * | | |1 = I2C wake-up function Enabled.
<> 144:ef7eb2e8f9f7 17127 */
<> 144:ef7eb2e8f9f7 17128 __IO uint32_t WKCTL;
<> 144:ef7eb2e8f9f7 17129
<> 144:ef7eb2e8f9f7 17130 /**
<> 144:ef7eb2e8f9f7 17131 * WKSTS
<> 144:ef7eb2e8f9f7 17132 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17133 * Offset: 0x40 I2C Wake-up Status Register
<> 144:ef7eb2e8f9f7 17134 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17135 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17136 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17137 * |[0] |WKIF |I2C Wake-Up Flag
<> 144:ef7eb2e8f9f7 17138 * | | |0 = No wake up occurred.
<> 144:ef7eb2e8f9f7 17139 * | | |1 = Wake up from Power-down mode.
<> 144:ef7eb2e8f9f7 17140 * | | |Note: Software can write 1 to clear this bit.
<> 144:ef7eb2e8f9f7 17141 */
<> 144:ef7eb2e8f9f7 17142 __IO uint32_t WKSTS;
<> 144:ef7eb2e8f9f7 17143
<> 144:ef7eb2e8f9f7 17144 } I2C_T;
<> 144:ef7eb2e8f9f7 17145
<> 144:ef7eb2e8f9f7 17146 /**
<> 144:ef7eb2e8f9f7 17147 @addtogroup I2C_CONST I2C Bit Field Definition
<> 144:ef7eb2e8f9f7 17148 Constant Definitions for I2C Controller
<> 144:ef7eb2e8f9f7 17149 @{ */
<> 144:ef7eb2e8f9f7 17150
<> 144:ef7eb2e8f9f7 17151 #define I2C_CTL_AA_Pos (2) /*!< I2C CTL: AA Position */
<> 144:ef7eb2e8f9f7 17152 #define I2C_CTL_AA_Msk (0x1ul << I2C_CTL_AA_Pos) /*!< I2C CTL: AA Mask */
<> 144:ef7eb2e8f9f7 17153
<> 144:ef7eb2e8f9f7 17154 #define I2C_CTL_SI_Pos (3) /*!< I2C CTL: SI Position */
<> 144:ef7eb2e8f9f7 17155 #define I2C_CTL_SI_Msk (0x1ul << I2C_CTL_SI_Pos) /*!< I2C CTL: SI Mask */
<> 144:ef7eb2e8f9f7 17156
<> 144:ef7eb2e8f9f7 17157 #define I2C_CTL_STO_Pos (4) /*!< I2C CTL: STO Position */
<> 144:ef7eb2e8f9f7 17158 #define I2C_CTL_STO_Msk (0x1ul << I2C_CTL_STO_Pos) /*!< I2C CTL: STO Mask */
<> 144:ef7eb2e8f9f7 17159
<> 144:ef7eb2e8f9f7 17160 #define I2C_CTL_STA_Pos (5) /*!< I2C CTL: STA Position */
<> 144:ef7eb2e8f9f7 17161 #define I2C_CTL_STA_Msk (0x1ul << I2C_CTL_STA_Pos) /*!< I2C CTL: STA Mask */
<> 144:ef7eb2e8f9f7 17162
<> 144:ef7eb2e8f9f7 17163 #define I2C_CTL_I2CEN_Pos (6) /*!< I2C CTL: I2CEN Position */
<> 144:ef7eb2e8f9f7 17164 #define I2C_CTL_I2CEN_Msk (0x1ul << I2C_CTL_I2CEN_Pos) /*!< I2C CTL: I2CEN Mask */
<> 144:ef7eb2e8f9f7 17165
<> 144:ef7eb2e8f9f7 17166 #define I2C_CTL_INTEN_Pos (7) /*!< I2C CTL: INTEN Position */
<> 144:ef7eb2e8f9f7 17167 #define I2C_CTL_INTEN_Msk (0x1ul << I2C_CTL_INTEN_Pos) /*!< I2C CTL: INTEN Mask */
<> 144:ef7eb2e8f9f7 17168
<> 144:ef7eb2e8f9f7 17169 #define I2C_ADDR0_GC_Pos (0) /*!< I2C ADDR0: GC Position */
<> 144:ef7eb2e8f9f7 17170 #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) /*!< I2C ADDR0: GC Mask */
<> 144:ef7eb2e8f9f7 17171
<> 144:ef7eb2e8f9f7 17172 #define I2C_ADDR0_ADDR_Pos (1) /*!< I2C ADDR0: ADDR Position */
<> 144:ef7eb2e8f9f7 17173 #define I2C_ADDR0_ADDR_Msk (0x7ful << I2C_ADDR0_ADDR_Pos) /*!< I2C ADDR0: ADDR Mask */
<> 144:ef7eb2e8f9f7 17174
<> 144:ef7eb2e8f9f7 17175 #define I2C_DAT_DAT_Pos (0) /*!< I2C DAT: DAT Position */
<> 144:ef7eb2e8f9f7 17176 #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) /*!< I2C DAT: DAT Mask */
<> 144:ef7eb2e8f9f7 17177
<> 144:ef7eb2e8f9f7 17178 #define I2C_STATUS_STATUS_Pos (0) /*!< I2C STATUS: STATUS Position */
<> 144:ef7eb2e8f9f7 17179 #define I2C_STATUS_STATUS_Msk (0xfful << I2C_STATUS_STATUS_Pos) /*!< I2C STATUS: STATUS Mask */
<> 144:ef7eb2e8f9f7 17180
<> 144:ef7eb2e8f9f7 17181 #define I2C_CLKDIV_DIVIDER_Pos (0) /*!< I2C CLKDIV: DIVIDER Position */
<> 144:ef7eb2e8f9f7 17182 #define I2C_CLKDIV_DIVIDER_Msk (0xfful << I2C_CLKDIV_DIVIDER_Pos) /*!< I2C CLKDIV: DIVIDER Mask */
<> 144:ef7eb2e8f9f7 17183
<> 144:ef7eb2e8f9f7 17184 #define I2C_TOCTL_TOIF_Pos (0) /*!< I2C TOCTL: TOIF Position */
<> 144:ef7eb2e8f9f7 17185 #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) /*!< I2C TOCTL: TOIF Mask */
<> 144:ef7eb2e8f9f7 17186
<> 144:ef7eb2e8f9f7 17187 #define I2C_TOCTL_TOCDIV4_Pos (1) /*!< I2C TOCTL: TOCDIV4 Position */
<> 144:ef7eb2e8f9f7 17188 #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) /*!< I2C TOCTL: TOCDIV4 Mask */
<> 144:ef7eb2e8f9f7 17189
<> 144:ef7eb2e8f9f7 17190 #define I2C_TOCTL_TOCEN_Pos (2) /*!< I2C TOCTL: TOCEN Position */
<> 144:ef7eb2e8f9f7 17191 #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) /*!< I2C TOCTL: TOCEN Mask */
<> 144:ef7eb2e8f9f7 17192
<> 144:ef7eb2e8f9f7 17193 #define I2C_ADDR1_GC_Pos (0) /*!< I2C ADDR1: GC Position */
<> 144:ef7eb2e8f9f7 17194 #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) /*!< I2C ADDR1: GC Mask */
<> 144:ef7eb2e8f9f7 17195
<> 144:ef7eb2e8f9f7 17196 #define I2C_ADDR1_ADDR_Pos (1) /*!< I2C ADDR1: ADDR Position */
<> 144:ef7eb2e8f9f7 17197 #define I2C_ADDR1_ADDR_Msk (0x7ful << I2C_ADDR1_ADDR_Pos) /*!< I2C ADDR1: ADDR Mask */
<> 144:ef7eb2e8f9f7 17198
<> 144:ef7eb2e8f9f7 17199 #define I2C_ADDR2_GC_Pos (0) /*!< I2C ADDR2: GC Position */
<> 144:ef7eb2e8f9f7 17200 #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) /*!< I2C ADDR2: GC Mask */
<> 144:ef7eb2e8f9f7 17201
<> 144:ef7eb2e8f9f7 17202 #define I2C_ADDR2_ADDR_Pos (1) /*!< I2C ADDR2: ADDR Position */
<> 144:ef7eb2e8f9f7 17203 #define I2C_ADDR2_ADDR_Msk (0x7ful << I2C_ADDR2_ADDR_Pos) /*!< I2C ADDR2: ADDR Mask */
<> 144:ef7eb2e8f9f7 17204
<> 144:ef7eb2e8f9f7 17205 #define I2C_ADDR3_GC_Pos (0) /*!< I2C ADDR3: GC Position */
<> 144:ef7eb2e8f9f7 17206 #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) /*!< I2C ADDR3: GC Mask */
<> 144:ef7eb2e8f9f7 17207
<> 144:ef7eb2e8f9f7 17208 #define I2C_ADDR3_ADDR_Pos (1) /*!< I2C ADDR3: ADDR Position */
<> 144:ef7eb2e8f9f7 17209 #define I2C_ADDR3_ADDR_Msk (0x7ful << I2C_ADDR3_ADDR_Pos) /*!< I2C ADDR3: ADDR Mask */
<> 144:ef7eb2e8f9f7 17210
<> 144:ef7eb2e8f9f7 17211 #define I2C_ADDRMSK0_ADDRMSK_Pos (1) /*!< I2C ADDRMSK0: ADDRMSK Position */
<> 144:ef7eb2e8f9f7 17212 #define I2C_ADDRMSK0_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK0_ADDRMSK_Pos) /*!< I2C ADDRMSK0: ADDRMSK Mask */
<> 144:ef7eb2e8f9f7 17213
<> 144:ef7eb2e8f9f7 17214 #define I2C_ADDRMSK1_ADDRMSK_Pos (1) /*!< I2C ADDRMSK1: ADDRMSK Position */
<> 144:ef7eb2e8f9f7 17215 #define I2C_ADDRMSK1_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK1_ADDRMSK_Pos) /*!< I2C ADDRMSK1: ADDRMSK Mask */
<> 144:ef7eb2e8f9f7 17216
<> 144:ef7eb2e8f9f7 17217 #define I2C_ADDRMSK2_ADDRMSK_Pos (1) /*!< I2C ADDRMSK2: ADDRMSK Position */
<> 144:ef7eb2e8f9f7 17218 #define I2C_ADDRMSK2_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK2_ADDRMSK_Pos) /*!< I2C ADDRMSK2: ADDRMSK Mask */
<> 144:ef7eb2e8f9f7 17219
<> 144:ef7eb2e8f9f7 17220 #define I2C_ADDRMSK3_ADDRMSK_Pos (1) /*!< I2C ADDRMSK3: ADDRMSK Position */
<> 144:ef7eb2e8f9f7 17221 #define I2C_ADDRMSK3_ADDRMSK_Msk (0x7ful << I2C_ADDRMSK3_ADDRMSK_Pos) /*!< I2C ADDRMSK3: ADDRMSK Mask */
<> 144:ef7eb2e8f9f7 17222
<> 144:ef7eb2e8f9f7 17223 #define I2C_WKCTL_WKEN_Pos (0) /*!< I2C WKCTL: WKEN Position */
<> 144:ef7eb2e8f9f7 17224 #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) /*!< I2C WKCTL: WKEN Mask */
<> 144:ef7eb2e8f9f7 17225
<> 144:ef7eb2e8f9f7 17226 #define I2C_WKSTS_WKIF_Pos (0) /*!< I2C WKSTS: WKIF Position */
<> 144:ef7eb2e8f9f7 17227 #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) /*!< I2C WKSTS: WKIF Mask */
<> 144:ef7eb2e8f9f7 17228
<> 144:ef7eb2e8f9f7 17229 /**@}*/ /* I2C_CONST */
<> 144:ef7eb2e8f9f7 17230 /**@}*/ /* end of I2C register group */
<> 144:ef7eb2e8f9f7 17231
<> 144:ef7eb2e8f9f7 17232
<> 144:ef7eb2e8f9f7 17233 /*---------------------- I2S Interface Controller -------------------------*/
<> 144:ef7eb2e8f9f7 17234 /**
<> 144:ef7eb2e8f9f7 17235 @addtogroup I2S I2S Interface Controller(I2S)
<> 144:ef7eb2e8f9f7 17236 Memory Mapped Structure for I2S Controller
<> 144:ef7eb2e8f9f7 17237 @{ */
<> 144:ef7eb2e8f9f7 17238
<> 144:ef7eb2e8f9f7 17239 typedef struct {
<> 144:ef7eb2e8f9f7 17240
<> 144:ef7eb2e8f9f7 17241
<> 144:ef7eb2e8f9f7 17242 /**
<> 144:ef7eb2e8f9f7 17243 * CTL
<> 144:ef7eb2e8f9f7 17244 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17245 * Offset: 0x00 I2S Control Register
<> 144:ef7eb2e8f9f7 17246 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17247 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17248 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17249 * |[0] |I2SEN |I2S Controller Enable Control
<> 144:ef7eb2e8f9f7 17250 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 17251 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 17252 * |[1] |TXEN |Transmit Enable Control
<> 144:ef7eb2e8f9f7 17253 * | | |0 = Data transmission Disabled.
<> 144:ef7eb2e8f9f7 17254 * | | |1 = Data transmission Enabled.
<> 144:ef7eb2e8f9f7 17255 * |[2] |RXEN |Receive Enable Control
<> 144:ef7eb2e8f9f7 17256 * | | |0 = Data receiving Disabled.
<> 144:ef7eb2e8f9f7 17257 * | | |1 = Data receiving Enabled.
<> 144:ef7eb2e8f9f7 17258 * |[3] |MUTE |Transmit Mute Enable Control
<> 144:ef7eb2e8f9f7 17259 * | | |0 = Transmit data is shifted from buffer.
<> 144:ef7eb2e8f9f7 17260 * | | |1 = Transmit zero data.
<> 144:ef7eb2e8f9f7 17261 * |[4:5] |WDWIDTH |Word Width
<> 144:ef7eb2e8f9f7 17262 * | | |00 = data is 8-bit.
<> 144:ef7eb2e8f9f7 17263 * | | |01 = data is 16-bit.
<> 144:ef7eb2e8f9f7 17264 * | | |10 = data is 24-bit.
<> 144:ef7eb2e8f9f7 17265 * | | |11 = data is 32-bit.
<> 144:ef7eb2e8f9f7 17266 * |[6] |MONO |Monaural Data Control
<> 144:ef7eb2e8f9f7 17267 * | | |0 = Data is stereo format.
<> 144:ef7eb2e8f9f7 17268 * | | |1 = Data is monaural format.
<> 144:ef7eb2e8f9f7 17269 * | | |Note: when chip records data, only right channel data will be saved if monaural format is select.
<> 144:ef7eb2e8f9f7 17270 * |[7] |FORMAT |Data Format Selection
<> 144:ef7eb2e8f9f7 17271 * | | |If PCM=0,
<> 144:ef7eb2e8f9f7 17272 * | | |0 = I2S data format.
<> 144:ef7eb2e8f9f7 17273 * | | |1 = MSB justified data format.
<> 144:ef7eb2e8f9f7 17274 * | | |If PCM=1,
<> 144:ef7eb2e8f9f7 17275 * | | |0 = PCM mode A.
<> 144:ef7eb2e8f9f7 17276 * | | |1 = PCM mode B.
<> 144:ef7eb2e8f9f7 17277 * |[8] |SLAVE |Slave Mode Enable Control
<> 144:ef7eb2e8f9f7 17278 * | | |0 = Master mode.
<> 144:ef7eb2e8f9f7 17279 * | | |1 = Slave mode.
<> 144:ef7eb2e8f9f7 17280 * | | |Note: I2S can operate as master or slave.
<> 144:ef7eb2e8f9f7 17281 * | | |For Master mode, I2S_BCLK and I2S_LRCLK pins are output mode and send bit clock from NuMicro(TM)
<> 144:ef7eb2e8f9f7 17282 * | | |NUC442/NUC472 series to Audio CODEC chip.
<> 144:ef7eb2e8f9f7 17283 * | | |In Slave mode, I2S_BCLK and I2S_LRCLK pins are input mode and I2S_BCLK and I2S_LRCLK signals are received from outer Audio CODEC chip.
<> 144:ef7eb2e8f9f7 17284 * |[9:11] |TXTH |Transmit FIFO Threshold Level
<> 144:ef7eb2e8f9f7 17285 * | | |000 = 0 word data in transmit FIFO.
<> 144:ef7eb2e8f9f7 17286 * | | |001 = 1 word data in transmit FIFO.
<> 144:ef7eb2e8f9f7 17287 * | | |010 = 2 words data in transmit FIFO.
<> 144:ef7eb2e8f9f7 17288 * | | |011 = 3 words data in transmit FIFO.
<> 144:ef7eb2e8f9f7 17289 * | | |100 = 4 words data in transmit FIFO.
<> 144:ef7eb2e8f9f7 17290 * | | |101 = 5 words data in transmit FIFO.
<> 144:ef7eb2e8f9f7 17291 * | | |110 = 6 words data in transmit FIFO.
<> 144:ef7eb2e8f9f7 17292 * | | |111 = 7 words data in transmit FIFO.
<> 144:ef7eb2e8f9f7 17293 * | | |Note: If remain data word(s) in transmit FIFO is the same or less than threshold level then TXTHF flag is set.
<> 144:ef7eb2e8f9f7 17294 * |[12:14] |RXTH |Receive FIFO Threshold Level
<> 144:ef7eb2e8f9f7 17295 * | | |000 = 1 word data in receive FIFO.
<> 144:ef7eb2e8f9f7 17296 * | | |001 = 2 word data in receive FIFO.
<> 144:ef7eb2e8f9f7 17297 * | | |010 = 3 word data in receive FIFO.
<> 144:ef7eb2e8f9f7 17298 * | | |011 = 4 word data in receive FIFO.
<> 144:ef7eb2e8f9f7 17299 * | | |100 = 5 word data in receive FIFO.
<> 144:ef7eb2e8f9f7 17300 * | | |101 = 6 word data in receive FIFO.
<> 144:ef7eb2e8f9f7 17301 * | | |110 = 7 word data in receive FIFO.
<> 144:ef7eb2e8f9f7 17302 * | | |111 = 8 word data in receive FIFO.
<> 144:ef7eb2e8f9f7 17303 * | | |Note: When received data word(s) in buffer is equal to or higher than threshold level then RXTHF flag is set.
<> 144:ef7eb2e8f9f7 17304 * |[15] |MCLKEN |Master Clock Enable Control
<> 144:ef7eb2e8f9f7 17305 * | | |0 = Master clock Disabled.
<> 144:ef7eb2e8f9f7 17306 * | | |1 = Master clock Enabled.
<> 144:ef7eb2e8f9f7 17307 * | | |Note: If the external crystal clock in NuMicro(TM) NUC442/NUC472 series is frequency 2*N*256fs, software can program MCLK_DIV(I2S_CLK[5:0]) to get 256fs clock to audio codec chip.
<> 144:ef7eb2e8f9f7 17308 * |[16] |RZCEN |Right Channel Zero-Cross Detection Enable Control
<> 144:ef7eb2e8f9f7 17309 * | | |0 = Right channel zero-cross detect Disabled.
<> 144:ef7eb2e8f9f7 17310 * | | |1 = Right channel zero-cross detect Enabled.
<> 144:ef7eb2e8f9f7 17311 * | | |Note1: If this bit is set to 1, when right channel data sign bit change or next shift data bits are all zero then RZCF(I2S_STATUS[22]) flag is set to 1.
<> 144:ef7eb2e8f9f7 17312 * | | |Note2: If RZCF Flag is set to 1, the right channel will be mute.
<> 144:ef7eb2e8f9f7 17313 * |[17] |LZCEN |Left Channel Zero-Cross Detect Enable Control
<> 144:ef7eb2e8f9f7 17314 * | | |0 = Left channel zero-cross detect Disabled.
<> 144:ef7eb2e8f9f7 17315 * | | |1 = Left channel zero-cross detect Enabled.
<> 144:ef7eb2e8f9f7 17316 * | | |Note1: If this bit is set to 1, when left channel data sign bit change or next shift data bits are all zero then LZCF(I2S_STATUS[23]) flag is set to 1.
<> 144:ef7eb2e8f9f7 17317 * | | |Note2: If LZCF Flag is set to 1, the left channel will be mute.
<> 144:ef7eb2e8f9f7 17318 * |[18] |TXCLR |Clear Transmit FIFO
<> 144:ef7eb2e8f9f7 17319 * | | |0 = No Effect.
<> 144:ef7eb2e8f9f7 17320 * | | |1 = Clear TX FIFO.
<> 144:ef7eb2e8f9f7 17321 * | | |Note1: Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TXCNT(I2S_STATUS[31:28]) returns 0 and transmit FIFO becomes empty but data in transmit FIFO is not changed.
<> 144:ef7eb2e8f9f7 17322 * | | |Note2: This bit is clear by hardware automatically, read it return zero.
<> 144:ef7eb2e8f9f7 17323 * |[19] |RXCLR |Clear Receive FIFO
<> 144:ef7eb2e8f9f7 17324 * | | |0 = No Effect.
<> 144:ef7eb2e8f9f7 17325 * | | |1 = Clear RX FIFO.
<> 144:ef7eb2e8f9f7 17326 * | | |Note1: Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RXCNT (I2S_STATUS[27:24]) returns 0 and receive FIFO becomes empty.
<> 144:ef7eb2e8f9f7 17327 * | | |Note2: This bit is cleared by hardware automatically, read it return zero.
<> 144:ef7eb2e8f9f7 17328 * |[20] |TXPDMAEN |Transmit DMA Enable Control
<> 144:ef7eb2e8f9f7 17329 * | | |0 = TX DMA Disabled.
<> 144:ef7eb2e8f9f7 17330 * | | |1 = TX DMA Enabled.
<> 144:ef7eb2e8f9f7 17331 * | | |Note: When TX DMA is enables, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
<> 144:ef7eb2e8f9f7 17332 * |[21] |RXPDMAEN |Receive DMA Enable Control
<> 144:ef7eb2e8f9f7 17333 * | | |0 = RX DMA Disabled.
<> 144:ef7eb2e8f9f7 17334 * | | |1 = RX DMA Enabled.
<> 144:ef7eb2e8f9f7 17335 * | | |Note: When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
<> 144:ef7eb2e8f9f7 17336 * |[23] |RXLCH |Receive Left Channel Enable Control
<> 144:ef7eb2e8f9f7 17337 * | | |0 = Receives right channel data when monaural format is selected.
<> 144:ef7eb2e8f9f7 17338 * | | |1 = Receives left channel data when monaural format is selected.
<> 144:ef7eb2e8f9f7 17339 * | | |Note: When monaural format is selected (MONO = 1), I2S will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1.
<> 144:ef7eb2e8f9f7 17340 * |[24] |PCMEN |PCM Interface Enable Control
<> 144:ef7eb2e8f9f7 17341 * | | |0 = I2S Interface.
<> 144:ef7eb2e8f9f7 17342 * | | |1 = PCM Interface.
<> 144:ef7eb2e8f9f7 17343 */
<> 144:ef7eb2e8f9f7 17344 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 17345
<> 144:ef7eb2e8f9f7 17346 /**
<> 144:ef7eb2e8f9f7 17347 * CLKDIV
<> 144:ef7eb2e8f9f7 17348 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17349 * Offset: 0x04 I2S Clock Divider Register
<> 144:ef7eb2e8f9f7 17350 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17351 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17352 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17353 * |[0:5] |MCLKDIV |Master Clock Divider
<> 144:ef7eb2e8f9f7 17354 * | | |If chip external crystal frequency is (2xMCLKDIV)*256fs then software can program these bits to generate 256fs clock frequency to audio codec chip.
<> 144:ef7eb2e8f9f7 17355 * | | |If MCLKDIV is set to 0, MCLK is the same as external clock input.
<> 144:ef7eb2e8f9f7 17356 * | | |For example, sampling rate is 24 kHz and chip external crystal clock is 12.288 MHz, set MCLKDIV = 1.
<> 144:ef7eb2e8f9f7 17357 * | | |F_MCLK = F_I2SCLK/(2x(MCLKDIV)) (When MCLKDIV is >= 1 ).
<> 144:ef7eb2e8f9f7 17358 * | | |F_MCLK = F_I2SCLK (When MCLKDIV is set to 0 ).
<> 144:ef7eb2e8f9f7 17359 * | | |Note: F_MCLK is the frequency of MCLK, and F_i2SCLK is the frequency of the I2S_CLK
<> 144:ef7eb2e8f9f7 17360 * |[8:16] |BCLKDIV |Bit Clock Divider
<> 144:ef7eb2e8f9f7 17361 * | | |If I2S operates in Master mode, bit clock is provided by the NuMicro(TM) NUC442/NUC472 series.
<> 144:ef7eb2e8f9f7 17362 * | | |Software can program these bits to generate sampling rate clock frequency.
<> 144:ef7eb2e8f9f7 17363 * | | |F_BCLK= F_I2SCLK / (2*(BCLKDIV + 1)).
<> 144:ef7eb2e8f9f7 17364 * | | |Note: F_BCLK is the frequency of BCLK and F_I2SCLK is the frequency of I2S_CLK
<> 144:ef7eb2e8f9f7 17365 */
<> 144:ef7eb2e8f9f7 17366 __IO uint32_t CLKDIV;
<> 144:ef7eb2e8f9f7 17367
<> 144:ef7eb2e8f9f7 17368 /**
<> 144:ef7eb2e8f9f7 17369 * IEN
<> 144:ef7eb2e8f9f7 17370 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17371 * Offset: 0x08 I2S Interrupt Enable Register
<> 144:ef7eb2e8f9f7 17372 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17373 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17374 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17375 * |[0] |RXUDIEN |Receive FIFO Underflow Interrupt E Enable Control
<> 144:ef7eb2e8f9f7 17376 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17377 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17378 * | | |Note: If software reads receive FIFO when it is empty then RXUDIF(I2S_STATUS[8]) flag is set to 1.
<> 144:ef7eb2e8f9f7 17379 * |[1] |RXOVIEN |Receive FIFO Overflow Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17380 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17381 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17382 * | | |Note: Interrupt occurs if this bit is set to 1 and RXOVIEN(I2S_STATUS[9]) flag is set to 1
<> 144:ef7eb2e8f9f7 17383 * |[2] |RXTHIEN |Receive FIFO Threshold Level Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17384 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17385 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17386 * | | |Note: When data word in receive FIFO is equal or higher than RXTH(I2S_CTL[14:12]) and the RXTHF bit is set to 1.
<> 144:ef7eb2e8f9f7 17387 * | | |If RXTHIEN bit is enabled, interrupt occur.
<> 144:ef7eb2e8f9f7 17388 * |[8] |TXUDIEN |Transmit FIFO Underflow Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17389 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17390 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17391 * | | |Note: Interrupt occur if this bit is set to 1 and TXUDIEN(I2S_STATUS[16]) flag is set to 1.
<> 144:ef7eb2e8f9f7 17392 * |[9] |TXOVIEN |Transmit FIFO Overflow Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17393 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17394 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17395 * | | |Note: Interrupt occurs if this bit is set to 1 and TXOVIEN(I2S_STATUS[17]) flag is set to 1
<> 144:ef7eb2e8f9f7 17396 * |[10] |TXTHIEN |Transmit FIFO Threshold Level Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17397 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17398 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17399 * | | |Note: Interrupt occurs if this bit is set to 1 and data words in transmit FIFO is less than TXTH(I2S_CTL[11:9]).
<> 144:ef7eb2e8f9f7 17400 * |[11] |RZCIEN |Right Channel Zero-Cross Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17401 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17402 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17403 * | | |Note: Interrupt occurs if this bit is set to 1 and right channel zero-cross
<> 144:ef7eb2e8f9f7 17404 * |[12] |LZCIEN |Left Channel Zero-Cross Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17405 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17406 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17407 * | | |Note: Interrupt occurs if this bit is set to 1 and left channel zero-cross
<> 144:ef7eb2e8f9f7 17408 */
<> 144:ef7eb2e8f9f7 17409 __IO uint32_t IEN;
<> 144:ef7eb2e8f9f7 17410
<> 144:ef7eb2e8f9f7 17411 /**
<> 144:ef7eb2e8f9f7 17412 * STATUS
<> 144:ef7eb2e8f9f7 17413 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17414 * Offset: 0x0C I2S Status Register
<> 144:ef7eb2e8f9f7 17415 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17416 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17417 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17418 * |[0] |I2SIF |I2S Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 17419 * | | |0 = No I2S interrupt.
<> 144:ef7eb2e8f9f7 17420 * | | |1 = I2S interrupt.
<> 144:ef7eb2e8f9f7 17421 * | | |Note: It is wire-OR of TXIF and RXIF bits.
<> 144:ef7eb2e8f9f7 17422 * |[1] |RXIF |I2S Receive Interrupt (Read Only)
<> 144:ef7eb2e8f9f7 17423 * | | |0 = No receive interrupt.
<> 144:ef7eb2e8f9f7 17424 * | | |1 = Receive interrupt.
<> 144:ef7eb2e8f9f7 17425 * |[2] |TXIF |I2S Transmit Interrupt (Read Only)
<> 144:ef7eb2e8f9f7 17426 * | | |0 = No transmit interrupt.
<> 144:ef7eb2e8f9f7 17427 * | | |1 = Transmit interrupt.
<> 144:ef7eb2e8f9f7 17428 * |[3] |RIGHT |Right Channel (Read Only)
<> 144:ef7eb2e8f9f7 17429 * | | |0 = Left channel.
<> 144:ef7eb2e8f9f7 17430 * | | |1 = Right channel.
<> 144:ef7eb2e8f9f7 17431 * | | |Note: This bit indicate current transmit data is belong to right channel
<> 144:ef7eb2e8f9f7 17432 * |[8] |RXUDIF |Receive FIFO Underflow Flag
<> 144:ef7eb2e8f9f7 17433 * | | |0 = No underflow occur.
<> 144:ef7eb2e8f9f7 17434 * | | |1 = Underflow occur.
<> 144:ef7eb2e8f9f7 17435 * | | |Note1: When receive FIFO is empty, and software reads the receive FIFO again.
<> 144:ef7eb2e8f9f7 17436 * | | |This bit will be set to 1, and it indicates underflow situation occurs.
<> 144:ef7eb2e8f9f7 17437 * | | |Note2: Write 1 to clear this bit to zero
<> 144:ef7eb2e8f9f7 17438 * |[9] |RXOVIF |Receive FIFO Overflow Flag
<> 144:ef7eb2e8f9f7 17439 * | | |0 = No overflow occur.
<> 144:ef7eb2e8f9f7 17440 * | | |1 = Overflow occur.
<> 144:ef7eb2e8f9f7 17441 * | | |Note1: When receive FIFO is full and receive hardware attempt write to data into receive FIFO then this bit is set to 1, data in 1st buffer is overwrote.
<> 144:ef7eb2e8f9f7 17442 * | | |Note2: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 17443 * |[10] |RXTHIF |Receive FIFO Threshold Flag (Read Only)
<> 144:ef7eb2e8f9f7 17444 * | | |0 = Data word(s) in FIFO is lower than threshold level.
<> 144:ef7eb2e8f9f7 17445 * | | |1 = Data word(s) in FIFO is equal or higher than threshold level.
<> 144:ef7eb2e8f9f7 17446 * | | |Note: When data word(s) in receive FIFO is equal or higher than threshold value set in RXTH(I2S_CTL[14:12]) the RXTHIF bit becomes to 1.
<> 144:ef7eb2e8f9f7 17447 * | | |It keeps at 1 till RXCNT less than RXTH after software read RXFIFO register.
<> 144:ef7eb2e8f9f7 17448 * |[11] |RXFULL |Receive FIFO Full (Read Only)
<> 144:ef7eb2e8f9f7 17449 * | | |0 = Not full.
<> 144:ef7eb2e8f9f7 17450 * | | |1 = Full.
<> 144:ef7eb2e8f9f7 17451 * | | |Note: This bit reflects data words number in receive FIFO is 8.
<> 144:ef7eb2e8f9f7 17452 * |[12] |RXEMPTY |Receive FIFO Empty (Read Only)
<> 144:ef7eb2e8f9f7 17453 * | | |0 = Not empty.
<> 144:ef7eb2e8f9f7 17454 * | | |1 = Empty.
<> 144:ef7eb2e8f9f7 17455 * | | |Note: This bit reflects data words number in receive FIFO is zero
<> 144:ef7eb2e8f9f7 17456 * |[16] |TXUDIF |Transmit FIFO Underflow Flag
<> 144:ef7eb2e8f9f7 17457 * | | |0 = No underflow.
<> 144:ef7eb2e8f9f7 17458 * | | |1 = Underflow.
<> 144:ef7eb2e8f9f7 17459 * | | |Note1: When transmit FIFO is empty and shift logic hardware read data from data FIFO causes this set to 1.
<> 144:ef7eb2e8f9f7 17460 * | | |Note2: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 17461 * |[17] |TXOVIF |Transmit FIFO Overflow Flag
<> 144:ef7eb2e8f9f7 17462 * | | |0 = No overflow.
<> 144:ef7eb2e8f9f7 17463 * | | |1 = Overflow.
<> 144:ef7eb2e8f9f7 17464 * | | |Note1: Write data to transmit FIFO when it is full and this bit set to 1
<> 144:ef7eb2e8f9f7 17465 * | | |Note2: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 17466 * |[18] |TXTHIF |Transmit FIFO Threshold Flag (Read Only)
<> 144:ef7eb2e8f9f7 17467 * | | |0 = Data word(s) in FIFO is higher than threshold level.
<> 144:ef7eb2e8f9f7 17468 * | | |1 = Data word(s) in FIFO is equal or lower than threshold level.
<> 144:ef7eb2e8f9f7 17469 * | | |Note: When data word(s) in transmit FIFO is equal or lower than threshold value set in TXTH(I2S_CTL[11:9]) the TXTHIF bit becomes to 1.
<> 144:ef7eb2e8f9f7 17470 * | | |It keeps at 1 till TXCNT is higher than TXTH after software write TXFIFO register.
<> 144:ef7eb2e8f9f7 17471 * |[19] |TXFULL |Transmit FIFO Full (Read Only)
<> 144:ef7eb2e8f9f7 17472 * | | |This bit reflect data word number in transmit FIFO is 8
<> 144:ef7eb2e8f9f7 17473 * | | |0 = Not full.
<> 144:ef7eb2e8f9f7 17474 * | | |1 = Full.
<> 144:ef7eb2e8f9f7 17475 * |[20] |TXEMPTY |Transmit FIFO Empty (Read Only)
<> 144:ef7eb2e8f9f7 17476 * | | |This bit reflect data word number in transmit FIFO is zero
<> 144:ef7eb2e8f9f7 17477 * | | |0 = Not empty.
<> 144:ef7eb2e8f9f7 17478 * | | |1 = Empty.
<> 144:ef7eb2e8f9f7 17479 * |[21] |TXBUSY |Transmit Busy (Read Only)
<> 144:ef7eb2e8f9f7 17480 * | | |0 = Transmit shift buffer is empty.
<> 144:ef7eb2e8f9f7 17481 * | | |1 = Transmit shift buffer is busy.
<> 144:ef7eb2e8f9f7 17482 * | | |Note: This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out.
<> 144:ef7eb2e8f9f7 17483 * | | |And set to 1 when 1st data is load to shift buffer.
<> 144:ef7eb2e8f9f7 17484 * |[22] |RZCIF |Right Channel Zero-Cross Flag
<> 144:ef7eb2e8f9f7 17485 * | | |It indicates right channel next sample data sign bit is changed or all data bits are zero.
<> 144:ef7eb2e8f9f7 17486 * | | |0 = No zero-cross.
<> 144:ef7eb2e8f9f7 17487 * | | |1 = Right channel zero-cross is detected.
<> 144:ef7eb2e8f9f7 17488 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 17489 * |[23] |LZCIF |Left Channel Zero-Cross Flag
<> 144:ef7eb2e8f9f7 17490 * | | |It indicates left channel next sample data sign bit is changed or all data bits are zero.
<> 144:ef7eb2e8f9f7 17491 * | | |0 = No zero-cross.
<> 144:ef7eb2e8f9f7 17492 * | | |1 = Left channel zero-cross is detected.
<> 144:ef7eb2e8f9f7 17493 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 17494 * |[24:27] |RXCNT |Receive FIFO Level (Read Only)
<> 144:ef7eb2e8f9f7 17495 * | | |These bits indicate word number in receive FIFO
<> 144:ef7eb2e8f9f7 17496 * | | |0000 = No data.
<> 144:ef7eb2e8f9f7 17497 * | | |0001 = 1 word in receive FIFO.
<> 144:ef7eb2e8f9f7 17498 * | | |....
<> 144:ef7eb2e8f9f7 17499 * | | |1000 = 8 words in receive FIFO.
<> 144:ef7eb2e8f9f7 17500 * |[28:31] |TXCNT |Transmit FIFO Level (Read Only)
<> 144:ef7eb2e8f9f7 17501 * | | |These bits indicate word number in transmit FIFO
<> 144:ef7eb2e8f9f7 17502 * | | |0000 = No data.
<> 144:ef7eb2e8f9f7 17503 * | | |0001 = 1 word in transmit FIFO.
<> 144:ef7eb2e8f9f7 17504 * | | |....
<> 144:ef7eb2e8f9f7 17505 * | | |1000 = 8 words in transmit FIFO.
<> 144:ef7eb2e8f9f7 17506 */
<> 144:ef7eb2e8f9f7 17507 __I uint32_t STATUS;
<> 144:ef7eb2e8f9f7 17508
<> 144:ef7eb2e8f9f7 17509 /**
<> 144:ef7eb2e8f9f7 17510 * TX
<> 144:ef7eb2e8f9f7 17511 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17512 * Offset: 0x10 I2S Transmit FIFO Register
<> 144:ef7eb2e8f9f7 17513 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17514 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17515 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17516 * |[0:31] |TX |Transmit FIFO Bits
<> 144:ef7eb2e8f9f7 17517 * | | |I2S contains 8 words (8x32 bit) data buffer for data transmit.
<> 144:ef7eb2e8f9f7 17518 * | | |Write data to this register to prepare data for transmit.
<> 144:ef7eb2e8f9f7 17519 * | | |The remaining word number is indicated by TXCNT(I2S_STATUS[31:28]).
<> 144:ef7eb2e8f9f7 17520 */
<> 144:ef7eb2e8f9f7 17521 __O uint32_t TX;
<> 144:ef7eb2e8f9f7 17522
<> 144:ef7eb2e8f9f7 17523 /**
<> 144:ef7eb2e8f9f7 17524 * RX
<> 144:ef7eb2e8f9f7 17525 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17526 * Offset: 0x14 I2S Receive FIFO Register
<> 144:ef7eb2e8f9f7 17527 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17528 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17529 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17530 * |[0:31] |RX |Receive FIFO Bits
<> 144:ef7eb2e8f9f7 17531 * | | |I2S contains 8 words (8x32 bit) data buffer for data receive.
<> 144:ef7eb2e8f9f7 17532 * | | |Read this register to get data in FIFO.
<> 144:ef7eb2e8f9f7 17533 * | | |The remaining data word number is indicated by RXCNT(I2S_STATUS[27:24]).
<> 144:ef7eb2e8f9f7 17534 */
<> 144:ef7eb2e8f9f7 17535 __I uint32_t RX;
<> 144:ef7eb2e8f9f7 17536
<> 144:ef7eb2e8f9f7 17537 } I2S_T;
<> 144:ef7eb2e8f9f7 17538
<> 144:ef7eb2e8f9f7 17539 /**
<> 144:ef7eb2e8f9f7 17540 @addtogroup I2S_CONST I2S Bit Field Definition
<> 144:ef7eb2e8f9f7 17541 Constant Definitions for I2S Controller
<> 144:ef7eb2e8f9f7 17542 @{ */
<> 144:ef7eb2e8f9f7 17543
<> 144:ef7eb2e8f9f7 17544 #define I2S_CTL_I2SEN_Pos (0) /*!< I2S CTL: I2SEN Position */
<> 144:ef7eb2e8f9f7 17545 #define I2S_CTL_I2SEN_Msk (0x1ul << I2S_CTL_I2SEN_Pos) /*!< I2S CTL: I2SEN Mask */
<> 144:ef7eb2e8f9f7 17546
<> 144:ef7eb2e8f9f7 17547 #define I2S_CTL_TXEN_Pos (1) /*!< I2S CTL: TXEN Position */
<> 144:ef7eb2e8f9f7 17548 #define I2S_CTL_TXEN_Msk (0x1ul << I2S_CTL_TXEN_Pos) /*!< I2S CTL: TXEN Mask */
<> 144:ef7eb2e8f9f7 17549
<> 144:ef7eb2e8f9f7 17550 #define I2S_CTL_RXEN_Pos (2) /*!< I2S CTL: RXEN Position */
<> 144:ef7eb2e8f9f7 17551 #define I2S_CTL_RXEN_Msk (0x1ul << I2S_CTL_RXEN_Pos) /*!< I2S CTL: RXEN Mask */
<> 144:ef7eb2e8f9f7 17552
<> 144:ef7eb2e8f9f7 17553 #define I2S_CTL_MUTE_Pos (3) /*!< I2S CTL: MUTE Position */
<> 144:ef7eb2e8f9f7 17554 #define I2S_CTL_MUTE_Msk (0x1ul << I2S_CTL_MUTE_Pos) /*!< I2S CTL: MUTE Mask */
<> 144:ef7eb2e8f9f7 17555
<> 144:ef7eb2e8f9f7 17556 #define I2S_CTL_WDWIDTH_Pos (4) /*!< I2S CTL: WDWIDTH Position */
<> 144:ef7eb2e8f9f7 17557 #define I2S_CTL_WDWIDTH_Msk (0x3ul << I2S_CTL_WDWIDTH_Pos) /*!< I2S CTL: WDWIDTH Mask */
<> 144:ef7eb2e8f9f7 17558
<> 144:ef7eb2e8f9f7 17559 #define I2S_CTL_MONO_Pos (6) /*!< I2S CTL: MONO Position */
<> 144:ef7eb2e8f9f7 17560 #define I2S_CTL_MONO_Msk (0x1ul << I2S_CTL_MONO_Pos) /*!< I2S CTL: MONO Mask */
<> 144:ef7eb2e8f9f7 17561
<> 144:ef7eb2e8f9f7 17562 #define I2S_CTL_FORMAT_Pos (7) /*!< I2S CTL: FORMAT Position */
<> 144:ef7eb2e8f9f7 17563 #define I2S_CTL_FORMAT_Msk (0x1ul << I2S_CTL_FORMAT_Pos) /*!< I2S CTL: FORMAT Mask */
<> 144:ef7eb2e8f9f7 17564
<> 144:ef7eb2e8f9f7 17565 #define I2S_CTL_SLAVE_Pos (8) /*!< I2S CTL: SLAVE Position */
<> 144:ef7eb2e8f9f7 17566 #define I2S_CTL_SLAVE_Msk (0x1ul << I2S_CTL_SLAVE_Pos) /*!< I2S CTL: SLAVE Mask */
<> 144:ef7eb2e8f9f7 17567
<> 144:ef7eb2e8f9f7 17568 #define I2S_CTL_TXTH_Pos (9) /*!< I2S CTL: TXTH Position */
<> 144:ef7eb2e8f9f7 17569 #define I2S_CTL_TXTH_Msk (0x7ul << I2S_CTL_TXTH_Pos) /*!< I2S CTL: TXTH Mask */
<> 144:ef7eb2e8f9f7 17570
<> 144:ef7eb2e8f9f7 17571 #define I2S_CTL_RXTH_Pos (12) /*!< I2S CTL: RXTH Position */
<> 144:ef7eb2e8f9f7 17572 #define I2S_CTL_RXTH_Msk (0x7ul << I2S_CTL_RXTH_Pos) /*!< I2S CTL: RXTH Mask */
<> 144:ef7eb2e8f9f7 17573
<> 144:ef7eb2e8f9f7 17574 #define I2S_CTL_MCLKEN_Pos (15) /*!< I2S CTL: MCLKEN Position */
<> 144:ef7eb2e8f9f7 17575 #define I2S_CTL_MCLKEN_Msk (0x1ul << I2S_CTL_MCLKEN_Pos) /*!< I2S CTL: MCLKEN Mask */
<> 144:ef7eb2e8f9f7 17576
<> 144:ef7eb2e8f9f7 17577 #define I2S_CTL_RZCEN_Pos (16) /*!< I2S CTL: RZCEN Position */
<> 144:ef7eb2e8f9f7 17578 #define I2S_CTL_RZCEN_Msk (0x1ul << I2S_CTL_RZCEN_Pos) /*!< I2S CTL: RZCEN Mask */
<> 144:ef7eb2e8f9f7 17579
<> 144:ef7eb2e8f9f7 17580 #define I2S_CTL_LZCEN_Pos (17) /*!< I2S CTL: LZCEN Position */
<> 144:ef7eb2e8f9f7 17581 #define I2S_CTL_LZCEN_Msk (0x1ul << I2S_CTL_LZCEN_Pos) /*!< I2S CTL: LZCEN Mask */
<> 144:ef7eb2e8f9f7 17582
<> 144:ef7eb2e8f9f7 17583 #define I2S_CTL_TXCLR_Pos (18) /*!< I2S CTL: TXCLR Position */
<> 144:ef7eb2e8f9f7 17584 #define I2S_CTL_TXCLR_Msk (0x1ul << I2S_CTL_TXCLR_Pos) /*!< I2S CTL: TXCLR Mask */
<> 144:ef7eb2e8f9f7 17585
<> 144:ef7eb2e8f9f7 17586 #define I2S_CTL_RXCLR_Pos (19) /*!< I2S CTL: RXCLR Position */
<> 144:ef7eb2e8f9f7 17587 #define I2S_CTL_RXCLR_Msk (0x1ul << I2S_CTL_RXCLR_Pos) /*!< I2S CTL: RXCLR Mask */
<> 144:ef7eb2e8f9f7 17588
<> 144:ef7eb2e8f9f7 17589 #define I2S_CTL_TXPDMAEN_Pos (20) /*!< I2S CTL: TXPDMAEN Position */
<> 144:ef7eb2e8f9f7 17590 #define I2S_CTL_TXPDMAEN_Msk (0x1ul << I2S_CTL_TXPDMAEN_Pos) /*!< I2S CTL: TXPDMAEN Mask */
<> 144:ef7eb2e8f9f7 17591
<> 144:ef7eb2e8f9f7 17592 #define I2S_CTL_RXPDMAEN_Pos (21) /*!< I2S CTL: RXPDMAEN Position */
<> 144:ef7eb2e8f9f7 17593 #define I2S_CTL_RXPDMAEN_Msk (0x1ul << I2S_CTL_RXPDMAEN_Pos) /*!< I2S CTL: RXPDMAEN Mask */
<> 144:ef7eb2e8f9f7 17594
<> 144:ef7eb2e8f9f7 17595 #define I2S_CTL_RXLCH_Pos (23) /*!< I2S CTL: RXLCH Position */
<> 144:ef7eb2e8f9f7 17596 #define I2S_CTL_RXLCH_Msk (0x1ul << I2S_CTL_RXLCH_Pos) /*!< I2S CTL: RXLCH Mask */
<> 144:ef7eb2e8f9f7 17597
<> 144:ef7eb2e8f9f7 17598 #define I2S_CTL_PCMEN_Pos (24) /*!< I2S CTL: PCMEN Position */
<> 144:ef7eb2e8f9f7 17599 #define I2S_CTL_PCMEN_Msk (0x1ul << I2S_CTL_PCMEN_Pos) /*!< I2S CTL: PCMEN Mask */
<> 144:ef7eb2e8f9f7 17600
<> 144:ef7eb2e8f9f7 17601 #define I2S_CLKDIV_MCLKDIV_Pos (0) /*!< I2S CLKDIV: MCLKDIV Position */
<> 144:ef7eb2e8f9f7 17602 #define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) /*!< I2S CLKDIV: MCLKDIV Mask */
<> 144:ef7eb2e8f9f7 17603
<> 144:ef7eb2e8f9f7 17604 #define I2S_CLKDIV_BCLKDIV_Pos (8) /*!< I2S CLKDIV: BCLKDIV Position */
<> 144:ef7eb2e8f9f7 17605 #define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) /*!< I2S CLKDIV: BCLKDIV Mask */
<> 144:ef7eb2e8f9f7 17606
<> 144:ef7eb2e8f9f7 17607 #define I2S_IEN_RXUDIEN_Pos (0) /*!< I2S IEN: RXUDIEN Position */
<> 144:ef7eb2e8f9f7 17608 #define I2S_IEN_RXUDIEN_Msk (0x1ul << I2S_IEN_RXUDIEN_Pos) /*!< I2S IEN: RXUDIEN Mask */
<> 144:ef7eb2e8f9f7 17609
<> 144:ef7eb2e8f9f7 17610 #define I2S_IEN_RXOVIEN_Pos (1) /*!< I2S IEN: RXOVIEN Position */
<> 144:ef7eb2e8f9f7 17611 #define I2S_IEN_RXOVIEN_Msk (0x1ul << I2S_IEN_RXOVIEN_Pos) /*!< I2S IEN: RXOVIEN Mask */
<> 144:ef7eb2e8f9f7 17612
<> 144:ef7eb2e8f9f7 17613 #define I2S_IEN_RXTHIEN_Pos (2) /*!< I2S IEN: RXTHIEN Position */
<> 144:ef7eb2e8f9f7 17614 #define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) /*!< I2S IEN: RXTHIEN Mask */
<> 144:ef7eb2e8f9f7 17615
<> 144:ef7eb2e8f9f7 17616 #define I2S_IEN_TXUDIEN_Pos (8) /*!< I2S IEN: TXUDIEN Position */
<> 144:ef7eb2e8f9f7 17617 #define I2S_IEN_TXUDIEN_Msk (0x1ul << I2S_IEN_TXUDIEN_Pos) /*!< I2S IEN: TXUDIEN Mask */
<> 144:ef7eb2e8f9f7 17618
<> 144:ef7eb2e8f9f7 17619 #define I2S_IEN_TXOVIEN_Pos (9) /*!< I2S IEN: TXOVIEN Position */
<> 144:ef7eb2e8f9f7 17620 #define I2S_IEN_TXOVIEN_Msk (0x1ul << I2S_IEN_TXOVIEN_Pos) /*!< I2S IEN: TXOVIEN Mask */
<> 144:ef7eb2e8f9f7 17621
<> 144:ef7eb2e8f9f7 17622 #define I2S_IEN_TXTHIEN_Pos (10) /*!< I2S IEN: TXTHIEN Position */
<> 144:ef7eb2e8f9f7 17623 #define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) /*!< I2S IEN: TXTHIEN Mask */
<> 144:ef7eb2e8f9f7 17624
<> 144:ef7eb2e8f9f7 17625 #define I2S_IEN_RZCIEN_Pos (11) /*!< I2S IEN: RZCIEN Position */
<> 144:ef7eb2e8f9f7 17626 #define I2S_IEN_RZCIEN_Msk (0x1ul << I2S_IEN_RZCIEN_Pos) /*!< I2S IEN: RZCIEN Mask */
<> 144:ef7eb2e8f9f7 17627
<> 144:ef7eb2e8f9f7 17628 #define I2S_IEN_LZCIEN_Pos (12) /*!< I2S IEN: LZCIEN Position */
<> 144:ef7eb2e8f9f7 17629 #define I2S_IEN_LZCIEN_Msk (0x1ul << I2S_IEN_LZCIEN_Pos) /*!< I2S IEN: LZCIEN Mask */
<> 144:ef7eb2e8f9f7 17630
<> 144:ef7eb2e8f9f7 17631 #define I2S_STATUS_I2SIF_Pos (0) /*!< I2S STATUS: I2SIF Position */
<> 144:ef7eb2e8f9f7 17632 #define I2S_STATUS_I2SIF_Msk (0x1ul << I2S_STATUS_I2SIF_Pos) /*!< I2S STATUS: I2SIF Mask */
<> 144:ef7eb2e8f9f7 17633
<> 144:ef7eb2e8f9f7 17634 #define I2S_STATUS_RXIF_Pos (1) /*!< I2S STATUS: RXIF Position */
<> 144:ef7eb2e8f9f7 17635 #define I2S_STATUS_RXIF_Msk (0x1ul << I2S_STATUS_RXIF_Pos) /*!< I2S STATUS: RXIF Mask */
<> 144:ef7eb2e8f9f7 17636
<> 144:ef7eb2e8f9f7 17637 #define I2S_STATUS_TXIF_Pos (2) /*!< I2S STATUS: TXIF Position */
<> 144:ef7eb2e8f9f7 17638 #define I2S_STATUS_TXIF_Msk (0x1ul << I2S_STATUS_TXIF_Pos) /*!< I2S STATUS: TXIF Mask */
<> 144:ef7eb2e8f9f7 17639
<> 144:ef7eb2e8f9f7 17640 #define I2S_STATUS_RIGHT_Pos (3) /*!< I2S STATUS: RIGHT Position */
<> 144:ef7eb2e8f9f7 17641 #define I2S_STATUS_RIGHT_Msk (0x1ul << I2S_STATUS_RIGHT_Pos) /*!< I2S STATUS: RIGHT Mask */
<> 144:ef7eb2e8f9f7 17642
<> 144:ef7eb2e8f9f7 17643 #define I2S_STATUS_RXUDIF_Pos (8) /*!< I2S STATUS: RXUDIF Position */
<> 144:ef7eb2e8f9f7 17644 #define I2S_STATUS_RXUDIF_Msk (0x1ul << I2S_STATUS_RXUDIF_Pos) /*!< I2S STATUS: RXUDIF Mask */
<> 144:ef7eb2e8f9f7 17645
<> 144:ef7eb2e8f9f7 17646 #define I2S_STATUS_RXOVIF_Pos (9) /*!< I2S STATUS: RXOVIF Position */
<> 144:ef7eb2e8f9f7 17647 #define I2S_STATUS_RXOVIF_Msk (0x1ul << I2S_STATUS_RXOVIF_Pos) /*!< I2S STATUS: RXOVIF Mask */
<> 144:ef7eb2e8f9f7 17648
<> 144:ef7eb2e8f9f7 17649 #define I2S_STATUS_RXTHIF_Pos (10) /*!< I2S STATUS: RXTHIF Position */
<> 144:ef7eb2e8f9f7 17650 #define I2S_STATUS_RXTHIF_Msk (0x1ul << I2S_STATUS_RXTHIF_Pos) /*!< I2S STATUS: RXTHIF Mask */
<> 144:ef7eb2e8f9f7 17651
<> 144:ef7eb2e8f9f7 17652 #define I2S_STATUS_RXFULL_Pos (11) /*!< I2S STATUS: RXFULL Position */
<> 144:ef7eb2e8f9f7 17653 #define I2S_STATUS_RXFULL_Msk (0x1ul << I2S_STATUS_RXFULL_Pos) /*!< I2S STATUS: RXFULL Mask */
<> 144:ef7eb2e8f9f7 17654
<> 144:ef7eb2e8f9f7 17655 #define I2S_STATUS_RXEMPTY_Pos (12) /*!< I2S STATUS: RXEMPTY Position */
<> 144:ef7eb2e8f9f7 17656 #define I2S_STATUS_RXEMPTY_Msk (0x1ul << I2S_STATUS_RXEMPTY_Pos) /*!< I2S STATUS: RXEMPTY Mask */
<> 144:ef7eb2e8f9f7 17657
<> 144:ef7eb2e8f9f7 17658 #define I2S_STATUS_TXUDIF_Pos (16) /*!< I2S STATUS: TXUDIF Position */
<> 144:ef7eb2e8f9f7 17659 #define I2S_STATUS_TXUDIF_Msk (0x1ul << I2S_STATUS_TXUDIF_Pos) /*!< I2S STATUS: TXUDIF Mask */
<> 144:ef7eb2e8f9f7 17660
<> 144:ef7eb2e8f9f7 17661 #define I2S_STATUS_TXOVIF_Pos (17) /*!< I2S STATUS: TXOVIF Position */
<> 144:ef7eb2e8f9f7 17662 #define I2S_STATUS_TXOVIF_Msk (0x1ul << I2S_STATUS_TXOVIF_Pos) /*!< I2S STATUS: TXOVIF Mask */
<> 144:ef7eb2e8f9f7 17663
<> 144:ef7eb2e8f9f7 17664 #define I2S_STATUS_TXTHIF_Pos (18) /*!< I2S STATUS: TXTHIF Position */
<> 144:ef7eb2e8f9f7 17665 #define I2S_STATUS_TXTHIF_Msk (0x1ul << I2S_STATUS_TXTHIF_Pos) /*!< I2S STATUS: TXTHIF Mask */
<> 144:ef7eb2e8f9f7 17666
<> 144:ef7eb2e8f9f7 17667 #define I2S_STATUS_TXFULL_Pos (19) /*!< I2S STATUS: TXFULL Position */
<> 144:ef7eb2e8f9f7 17668 #define I2S_STATUS_TXFULL_Msk (0x1ul << I2S_STATUS_TXFULL_Pos) /*!< I2S STATUS: TXFULL Mask */
<> 144:ef7eb2e8f9f7 17669
<> 144:ef7eb2e8f9f7 17670 #define I2S_STATUS_TXEMPTY_Pos (20) /*!< I2S STATUS: TXEMPTY Position */
<> 144:ef7eb2e8f9f7 17671 #define I2S_STATUS_TXEMPTY_Msk (0x1ul << I2S_STATUS_TXEMPTY_Pos) /*!< I2S STATUS: TXEMPTY Mask */
<> 144:ef7eb2e8f9f7 17672
<> 144:ef7eb2e8f9f7 17673 #define I2S_STATUS_TXBUSY_Pos (21) /*!< I2S STATUS: TXBUSY Position */
<> 144:ef7eb2e8f9f7 17674 #define I2S_STATUS_TXBUSY_Msk (0x1ul << I2S_STATUS_TXBUSY_Pos) /*!< I2S STATUS: TXBUSY Mask */
<> 144:ef7eb2e8f9f7 17675
<> 144:ef7eb2e8f9f7 17676 #define I2S_STATUS_RZCIF_Pos (22) /*!< I2S STATUS: RZCIF Position */
<> 144:ef7eb2e8f9f7 17677 #define I2S_STATUS_RZCIF_Msk (0x1ul << I2S_STATUS_RZCIF_Pos) /*!< I2S STATUS: RZCIF Mask */
<> 144:ef7eb2e8f9f7 17678
<> 144:ef7eb2e8f9f7 17679 #define I2S_STATUS_LZCIF_Pos (23) /*!< I2S STATUS: LZCIF Position */
<> 144:ef7eb2e8f9f7 17680 #define I2S_STATUS_LZCIF_Msk (0x1ul << I2S_STATUS_LZCIF_Pos) /*!< I2S STATUS: LZCIF Mask */
<> 144:ef7eb2e8f9f7 17681
<> 144:ef7eb2e8f9f7 17682 #define I2S_STATUS_RXCNT_Pos (24) /*!< I2S STATUS: RXCNT Position */
<> 144:ef7eb2e8f9f7 17683 #define I2S_STATUS_RXCNT_Msk (0xful << I2S_STATUS_RXCNT_Pos) /*!< I2S STATUS: RXCNT Mask */
<> 144:ef7eb2e8f9f7 17684
<> 144:ef7eb2e8f9f7 17685 #define I2S_STATUS_TXCNT_Pos (28) /*!< I2S STATUS: TXCNT Position */
<> 144:ef7eb2e8f9f7 17686 #define I2S_STATUS_TXCNT_Msk (0xful << I2S_STATUS_TXCNT_Pos) /*!< I2S STATUS: TXCNT Mask */
<> 144:ef7eb2e8f9f7 17687
<> 144:ef7eb2e8f9f7 17688 #define I2S_TX_TX_Pos (0) /*!< I2S TX: TX Position */
<> 144:ef7eb2e8f9f7 17689 #define I2S_TX_TX_Msk (0xfffffffful << I2S_TX_TX_Pos) /*!< I2S TX: TX Mask */
<> 144:ef7eb2e8f9f7 17690
<> 144:ef7eb2e8f9f7 17691 #define I2S_RX_RX_Pos (0) /*!< I2S RX: RX Position */
<> 144:ef7eb2e8f9f7 17692 #define I2S_RX_RX_Msk (0xfffffffful << I2S_RX_RX_Pos) /*!< I2S RX: RX Mask */
<> 144:ef7eb2e8f9f7 17693
<> 144:ef7eb2e8f9f7 17694 /**@}*/ /* I2S_CONST */
<> 144:ef7eb2e8f9f7 17695 /**@}*/ /* end of I2S register group */
<> 144:ef7eb2e8f9f7 17696
<> 144:ef7eb2e8f9f7 17697
<> 144:ef7eb2e8f9f7 17698 /*---------------------- OP Amplifier -------------------------*/
<> 144:ef7eb2e8f9f7 17699 /**
<> 144:ef7eb2e8f9f7 17700 @addtogroup OPA OP Amplifier(OPA)
<> 144:ef7eb2e8f9f7 17701 Memory Mapped Structure for OPA Controller
<> 144:ef7eb2e8f9f7 17702 @{ */
<> 144:ef7eb2e8f9f7 17703
<> 144:ef7eb2e8f9f7 17704 typedef struct {
<> 144:ef7eb2e8f9f7 17705
<> 144:ef7eb2e8f9f7 17706
<> 144:ef7eb2e8f9f7 17707 /**
<> 144:ef7eb2e8f9f7 17708 * CTL
<> 144:ef7eb2e8f9f7 17709 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17710 * Offset: 0x00 OP Amplifier Control Register
<> 144:ef7eb2e8f9f7 17711 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17712 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17713 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17714 * |[0] |OPEN0 |OP Amplifier 0 Enable Control
<> 144:ef7eb2e8f9f7 17715 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 17716 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 17717 * | | |Note: OP Amplifier 0 output needs wait stable 20us[MS1] after OPEN0 is first set.
<> 144:ef7eb2e8f9f7 17718 * | | |[MS1]alpha test
<> 144:ef7eb2e8f9f7 17719 * |[1] |OPEN1 |OP Amplifier 1 Enable Control
<> 144:ef7eb2e8f9f7 17720 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 17721 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 17722 * | | |Note: OP Amplifier 1 output needs wait stable 20us[MS1] after OPEN1 is first set.
<> 144:ef7eb2e8f9f7 17723 * | | |[MS1]alpha test
<> 144:ef7eb2e8f9f7 17724 * |[4] |OPSMTEN0 |OP Amplifier 0 Schmitt Trigger Non-Inverting Buffer Enable Control
<> 144:ef7eb2e8f9f7 17725 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 17726 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 17727 * |[5] |OPSMTEN1 |OP Amplifier 1 Schmitt Trigger Non-Inverting Buffer Enable Control
<> 144:ef7eb2e8f9f7 17728 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 17729 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 17730 * |[8] |OPAIE0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17731 * | | |0 = OP Amplifier 0 digital output interrupt function Disabled.
<> 144:ef7eb2e8f9f7 17732 * | | |1 = OP Amplifier 0 digital output interrupt function Enabled.
<> 144:ef7eb2e8f9f7 17733 * | | |The OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE0 is set to 1, a comparator interrupt request is generated.
<> 144:ef7eb2e8f9f7 17734 * |[9] |OPAIE1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17735 * | | |0 = OP Amplifier 1 digital output interrupt function Disabled.
<> 144:ef7eb2e8f9f7 17736 * | | |1 = OP Amplifier 1 digital output interrupt function Enabled.
<> 144:ef7eb2e8f9f7 17737 * | | |OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state, in the meanwhile, if OPAIE1 is set to 1, a comparator interrupt request is generated.
<> 144:ef7eb2e8f9f7 17738 */
<> 144:ef7eb2e8f9f7 17739 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 17740
<> 144:ef7eb2e8f9f7 17741 /**
<> 144:ef7eb2e8f9f7 17742 * STATUS
<> 144:ef7eb2e8f9f7 17743 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17744 * Offset: 0x04 OP Amplifier Status Register
<> 144:ef7eb2e8f9f7 17745 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17746 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17747 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17748 * |[0] |OPDO0 |OP Amplifier 0 Digital Output
<> 144:ef7eb2e8f9f7 17749 * | | |Synchronized to the APB clock to allow reading by software.
<> 144:ef7eb2e8f9f7 17750 * | | |Cleared when the Schmitt trigger buffer is disabled (OPSMTEN0 = 0).
<> 144:ef7eb2e8f9f7 17751 * |[1] |OPDO1 |OP Amplifier 1 Digital Output
<> 144:ef7eb2e8f9f7 17752 * | | |Synchronized to the APB clock to allow reading by software.
<> 144:ef7eb2e8f9f7 17753 * | | |Cleared when the Schmitt trigger buffer is disabled (OPSMTEN1 = 0).
<> 144:ef7eb2e8f9f7 17754 * |[4] |OPDF0 |OP Amplifier 0 Schmitt Trigger Digital Output Interrupt Flag
<> 144:ef7eb2e8f9f7 17755 * | | |OPDF0 interrupt flag is set by hardware whenever the OP amplifier 0 Schmitt trigger non-inverting buffer digital output changes state.
<> 144:ef7eb2e8f9f7 17756 * | | |This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 17757 * |[5] |OPDF1 |OP Amplifier 1 Schmitt Trigger Digital Output Interrupt Flag
<> 144:ef7eb2e8f9f7 17758 * | | |OPDF1 interrupt flag is set by hardware whenever the OP amplifier 1 Schmitt trigger non-inverting buffer digital output changes state.
<> 144:ef7eb2e8f9f7 17759 * | | |This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 17760 */
<> 144:ef7eb2e8f9f7 17761 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 17762
<> 144:ef7eb2e8f9f7 17763 } OPA_T;
<> 144:ef7eb2e8f9f7 17764
<> 144:ef7eb2e8f9f7 17765 /**
<> 144:ef7eb2e8f9f7 17766 @addtogroup OPA_CONST OPA Bit Field Definition
<> 144:ef7eb2e8f9f7 17767 Constant Definitions for OPA Controller
<> 144:ef7eb2e8f9f7 17768 @{ */
<> 144:ef7eb2e8f9f7 17769
<> 144:ef7eb2e8f9f7 17770 #define OPA_CTL_OPEN0_Pos (0) /*!< OPA CTL: OPEN0 Position */
<> 144:ef7eb2e8f9f7 17771 #define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) /*!< OPA CTL: OPEN0 Mask */
<> 144:ef7eb2e8f9f7 17772
<> 144:ef7eb2e8f9f7 17773 #define OPA_CTL_OPEN1_Pos (1) /*!< OPA CTL: OPEN1 Position */
<> 144:ef7eb2e8f9f7 17774 #define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) /*!< OPA CTL: OPEN1 Mask */
<> 144:ef7eb2e8f9f7 17775
<> 144:ef7eb2e8f9f7 17776 #define OPA_CTL_OPSMTEN0_Pos (4) /*!< OPA CTL: OPSMTEN0 Position */
<> 144:ef7eb2e8f9f7 17777 #define OPA_CTL_OPSMTEN0_Msk (0x1ul << OPA_CTL_OPSMTEN0_Pos) /*!< OPA CTL: OPSMTEN0 Mask */
<> 144:ef7eb2e8f9f7 17778
<> 144:ef7eb2e8f9f7 17779 #define OPA_CTL_OPSMTEN1_Pos (5) /*!< OPA CTL: OPSMTEN1 Position */
<> 144:ef7eb2e8f9f7 17780 #define OPA_CTL_OPSMTEN1_Msk (0x1ul << OPA_CTL_OPSMTEN1_Pos) /*!< OPA CTL: OPSMTEN1 Mask */
<> 144:ef7eb2e8f9f7 17781
<> 144:ef7eb2e8f9f7 17782 #define OPA_CTL_OPAIE0_Pos (8) /*!< OPA CTL: OPAIE0 Position */
<> 144:ef7eb2e8f9f7 17783 #define OPA_CTL_OPAIE0_Msk (0x1ul << OPA_CTL_OPAIE0_Pos) /*!< OPA CTL: OPAIE0 Mask */
<> 144:ef7eb2e8f9f7 17784
<> 144:ef7eb2e8f9f7 17785 #define OPA_CTL_OPAIE1_Pos (9) /*!< OPA CTL: OPAIE1 Position */
<> 144:ef7eb2e8f9f7 17786 #define OPA_CTL_OPAIE1_Msk (0x1ul << OPA_CTL_OPAIE1_Pos) /*!< OPA CTL: OPAIE1 Mask */
<> 144:ef7eb2e8f9f7 17787
<> 144:ef7eb2e8f9f7 17788 #define OPA_STATUS_OPDO0_Pos (0) /*!< OPA STATUS: OPDO0 Position */
<> 144:ef7eb2e8f9f7 17789 #define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) /*!< OPA STATUS: OPDO0 Mask */
<> 144:ef7eb2e8f9f7 17790
<> 144:ef7eb2e8f9f7 17791 #define OPA_STATUS_OPDO1_Pos (1) /*!< OPA STATUS: OPDO1 Position */
<> 144:ef7eb2e8f9f7 17792 #define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) /*!< OPA STATUS: OPDO1 Mask */
<> 144:ef7eb2e8f9f7 17793
<> 144:ef7eb2e8f9f7 17794 #define OPA_STATUS_OPDF0_Pos (4) /*!< OPA STATUS: OPDF0 Position */
<> 144:ef7eb2e8f9f7 17795 #define OPA_STATUS_OPDF0_Msk (0x1ul << OPA_STATUS_OPDF0_Pos) /*!< OPA STATUS: OPDF0 Mask */
<> 144:ef7eb2e8f9f7 17796
<> 144:ef7eb2e8f9f7 17797 #define OPA_STATUS_OPDF1_Pos (5) /*!< OPA STATUS: OPDF1 Position */
<> 144:ef7eb2e8f9f7 17798 #define OPA_STATUS_OPDF1_Msk (0x1ul << OPA_STATUS_OPDF1_Pos) /*!< OPA STATUS: OPDF1 Mask */
<> 144:ef7eb2e8f9f7 17799
<> 144:ef7eb2e8f9f7 17800 /**@}*/ /* OPA_CONST */
<> 144:ef7eb2e8f9f7 17801 /**@}*/ /* end of OPA register group */
<> 144:ef7eb2e8f9f7 17802
<> 144:ef7eb2e8f9f7 17803
<> 144:ef7eb2e8f9f7 17804 /*---------------------- USB On-The-Go Controller -------------------------*/
<> 144:ef7eb2e8f9f7 17805 /**
<> 144:ef7eb2e8f9f7 17806 @addtogroup OTG USB On-The-Go Controller(OTG)
<> 144:ef7eb2e8f9f7 17807 Memory Mapped Structure for OTG Controller
<> 144:ef7eb2e8f9f7 17808 @{ */
<> 144:ef7eb2e8f9f7 17809
<> 144:ef7eb2e8f9f7 17810 typedef struct {
<> 144:ef7eb2e8f9f7 17811
<> 144:ef7eb2e8f9f7 17812
<> 144:ef7eb2e8f9f7 17813 /**
<> 144:ef7eb2e8f9f7 17814 * CTL
<> 144:ef7eb2e8f9f7 17815 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17816 * Offset: 0x00 OTG Control Register
<> 144:ef7eb2e8f9f7 17817 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17818 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17819 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17820 * |[0] |VBUSDROP |Drop The VUSB Bus
<> 144:ef7eb2e8f9f7 17821 * | | |If user application running on this OTG A-device wants to conserve power consumption, set this bit to high When set this bit to TRUE, BUSREQ shall be cleared as well.
<> 144:ef7eb2e8f9f7 17822 * | | |0 = Did Not drop the VBUS and keep going on USB data transfers.
<> 144:ef7eb2e8f9f7 17823 * | | |1 = Drop the VBUS to conserve power consumption.
<> 144:ef7eb2e8f9f7 17824 * |[1] |BUSREQ |OTG A-Device Bus Request
<> 144:ef7eb2e8f9f7 17825 * | | |If user application of an OTG A-device wants to do data transfers via USB bus, set this bit to high Otherwise if user application won't use the bus any more, set this bit to low.
<> 144:ef7eb2e8f9f7 17826 * | | |This bit will be automatically cleared if VBUSDROP bit is set to TRUE.
<> 144:ef7eb2e8f9f7 17827 * |[2] |HNPREQEN |OTG B-Device HNP Enable/Request
<> 144:ef7eb2e8f9f7 17828 * | | |Set this bit to TRUE after the OTG A-device successfully sends a SetFeature(b_hnp_enable) command to the OTG B-device This bit will be cleared automatically when a bus reset or SESS_VLD goes from TRUE to FALSE.
<> 144:ef7eb2e8f9f7 17829 * |[4] |OTGEN |OTG Function Enable Control
<> 144:ef7eb2e8f9f7 17830 * | | |If USB is configured as OTG device, this bit must set high.
<> 144:ef7eb2e8f9f7 17831 * | | |0= OTG function Disabled.
<> 144:ef7eb2e8f9f7 17832 * | | |1 = OTG function Enabled.
<> 144:ef7eb2e8f9f7 17833 * |[7] |PDEVCKON |Force OTG PHY Output Clock To USB Device
<> 144:ef7eb2e8f9f7 17834 * | | |If software configures OTG controller as OTG device and OTG device as A-device, OTG controller will output OTG PHY clock (30 MHz) to USB device only when OTG device as A-peripheral.
<> 144:ef7eb2e8f9f7 17835 * | | |If software needs to configure USB device before role change (from A-Host to A-Peripheral), software can set this bit high to output OTG PHY clock to USB device.
<> 144:ef7eb2e8f9f7 17836 * | | |0= USB device clock is available only when OTG device as a peripheral.
<> 144:ef7eb2e8f9f7 17837 * | | |1 = Force output OTG PHY clock to USB device.
<> 144:ef7eb2e8f9f7 17838 * |[8] |WKEN |OTG Wake-Up Enable Control
<> 144:ef7eb2e8f9f7 17839 * | | |0= OTG ID pin status change wake-up Disabled.
<> 144:ef7eb2e8f9f7 17840 * | | |1 = OTG ID pin status change wake-up Enabled.
<> 144:ef7eb2e8f9f7 17841 */
<> 144:ef7eb2e8f9f7 17842 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 17843
<> 144:ef7eb2e8f9f7 17844 /**
<> 144:ef7eb2e8f9f7 17845 * PHYCTL
<> 144:ef7eb2e8f9f7 17846 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17847 * Offset: 0x04 OTG PHY Control Register
<> 144:ef7eb2e8f9f7 17848 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17849 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17850 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17851 * |[0] |SWPDEN |Software Control Pull-Down On Data Lines Enable Control
<> 144:ef7eb2e8f9f7 17852 * | | |0 = Pull-down resistors on data lines is controlled by OTG control logic.
<> 144:ef7eb2e8f9f7 17853 * | | |1 = Pull-down resistors on data lines is controlled by software.
<> 144:ef7eb2e8f9f7 17854 * | | |Note: Software must set this bit high before controlling DPPDEN and DMPDEN.
<> 144:ef7eb2e8f9f7 17855 * |[1] |DPPDEN |D+ Pull-Down Enable Control Set SWPDEN to TRUE before using this function
<> 144:ef7eb2e8f9f7 17856 * | | |0 = 15 kOhm resistor pull-down on D+ pin Disabled.
<> 144:ef7eb2e8f9f7 17857 * | | |1 = 15 kOhm resistor pull-down on D+ pin Enabled.
<> 144:ef7eb2e8f9f7 17858 * |[2] |DMPDEN |D- Pull-Down Enable Control Set SWPDEN to TRUE before using this function
<> 144:ef7eb2e8f9f7 17859 * | | |0 = 15 kOhm resistor pull-down on D- pin Disabled.
<> 144:ef7eb2e8f9f7 17860 * | | |1 = 15 kOhm resistor pull-down on D- pin Enabled.
<> 144:ef7eb2e8f9f7 17861 * |[5] |VBSTSPOL |Off-Chip USB VBUS Power Status Polarity
<> 144:ef7eb2e8f9f7 17862 * | | |The polarity of off-chip USB VBUS LDO valid depends on the selected component.
<> 144:ef7eb2e8f9f7 17863 * | | |This bit provides the inversed option of off-chip USB VBUS LDO valid.
<> 144:ef7eb2e8f9f7 17864 * | | |0 = The polarity of off-chip USB VBUS LDO valid not inversed.
<> 144:ef7eb2e8f9f7 17865 * | | |1 = The polarity of off-chip USB VBUS LDO valid inversed.
<> 144:ef7eb2e8f9f7 17866 * |[6] |VBENPOL |Off-Chip USB VBUS Power Enable Polarity
<> 144:ef7eb2e8f9f7 17867 * | | |The OTG controller will enable off-chip USB VBUS LDO to provide VBUS power when need.
<> 144:ef7eb2e8f9f7 17868 * | | |The polarity of enabling off-chip BSU VBUS LDO (high active or low active) depends on the selected component.
<> 144:ef7eb2e8f9f7 17869 * | | |This bit provides the inverse option of off-chip USB VBUS LDO enable.
<> 144:ef7eb2e8f9f7 17870 * | | |0 = The polarity of enabling off-chip USB VBUS LDO from the OTG controller not inversed.
<> 144:ef7eb2e8f9f7 17871 * | | |1 = The polarity of enabling off-chip USB VBUS LDO from the OTG controller inversed.
<> 144:ef7eb2e8f9f7 17872 * |[7] |IDDETEN |ID Detection Enable
<> 144:ef7eb2e8f9f7 17873 * | | |0 = Sampling on ID pin Enabled.
<> 144:ef7eb2e8f9f7 17874 * | | |1 = Sampling on ID pin Disabled.
<> 144:ef7eb2e8f9f7 17875 * |[8] |PHYCLK |PHY Input Clock Selection
<> 144:ef7eb2e8f9f7 17876 * | | |0 = PHY input clock is12 MHz.
<> 144:ef7eb2e8f9f7 17877 * | | |1 = PHY input clock is 24 MHz.
<> 144:ef7eb2e8f9f7 17878 * |[9] |OTGPHYEN |OTG PHY Enable Control When Device Configured As OTG-Device
<> 144:ef7eb2e8f9f7 17879 * | | |When device is configured as OTG-device, hardware will not enable OTG PHY automatically.
<> 144:ef7eb2e8f9f7 17880 * | | |Software can set OTG_EN to enable OTG PHY.
<> 144:ef7eb2e8f9f7 17881 * | | |0 = OTG PHY Disabled.
<> 144:ef7eb2e8f9f7 17882 * | | |1 = OTG PHY Enabled.
<> 144:ef7eb2e8f9f7 17883 */
<> 144:ef7eb2e8f9f7 17884 __IO uint32_t PHYCTL;
<> 144:ef7eb2e8f9f7 17885
<> 144:ef7eb2e8f9f7 17886 /**
<> 144:ef7eb2e8f9f7 17887 * INTEN
<> 144:ef7eb2e8f9f7 17888 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17889 * Offset: 0x08 OTG Interrupt Enable Register
<> 144:ef7eb2e8f9f7 17890 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17891 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17892 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17893 * |[0] |ROLECHGIEN|Role(Host Or Peripheral) Changed Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17894 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17895 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17896 * |[1] |VBEIEN |VBUS Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17897 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17898 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17899 * | | |Note: VBUS error means going to a_vbus_err state. Please refer to A-device state diagram in OTG spec.
<> 144:ef7eb2e8f9f7 17900 * |[2] |SRPFIEN |SRP Fail Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17901 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17902 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17903 * |[3] |HNPFIEN |HNP Fail Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17904 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17905 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17906 * |[4] |GOIDLEIEN |OTG Device Goes IDLE State Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17907 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17908 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17909 * | | |Note: Going to idle state means going to a_idle or b_idle state.
<> 144:ef7eb2e8f9f7 17910 * | | |Please refer to A-device state diagram and B-device state diagram in OTG spec.
<> 144:ef7eb2e8f9f7 17911 * |[5] |IDCHGIEN |IDSTS Changed Interrupt Enable
<> 144:ef7eb2e8f9f7 17912 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17913 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17914 * |[6] |PDEVIEN |Act As Peripheral Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17915 * | | |0 = This device as a peripheral interrupt Disabled.
<> 144:ef7eb2e8f9f7 17916 * | | |1 = This device as a peripheral interrupt Enabled.
<> 144:ef7eb2e8f9f7 17917 * |[7] |HOSTIEN |Act As Host Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17918 * | | |0= This device as a host interrupt Disabled.
<> 144:ef7eb2e8f9f7 17919 * | | |1 = This device as a host interrupt Enabled.
<> 144:ef7eb2e8f9f7 17920 * |[8] |BVLDCHGIEN|B-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17921 * | | |0 =Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17922 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17923 * |[9] |AVLDCHGIEN|A-Device Session Valid Status Change (From High To Low Or From Low To High) Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17924 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17925 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17926 * |[10] |VBCHGIEN |VBVALID Status Changed Interrupt Enable
<> 144:ef7eb2e8f9f7 17927 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17928 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17929 * |[11] |SECHGIEN |SESSEND Status Changed Interrupt Enable Control 0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17930 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17931 * |[13] |SRPDETIEN |SRP Detected Interrupt Enable Control
<> 144:ef7eb2e8f9f7 17932 * | | |0 = Interrupt Disabled.
<> 144:ef7eb2e8f9f7 17933 * | | |1 = Interrupt Enabled.
<> 144:ef7eb2e8f9f7 17934 */
<> 144:ef7eb2e8f9f7 17935 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 17936
<> 144:ef7eb2e8f9f7 17937 /**
<> 144:ef7eb2e8f9f7 17938 * INTSTS
<> 144:ef7eb2e8f9f7 17939 * ===================================================================================================
<> 144:ef7eb2e8f9f7 17940 * Offset: 0x0C OTG Interrupt Status Register
<> 144:ef7eb2e8f9f7 17941 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 17942 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 17943 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 17944 * |[0] |ROLECHGIF |OTG Role Change Interrupt Status
<> 144:ef7eb2e8f9f7 17945 * | | |This flag is set when the role of an OTG device changed from a host to a peripheral, or changed from a peripheral to a host
<> 144:ef7eb2e8f9f7 17946 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17947 * |[1] |VBEIF |VBUS Error Interrupt Status
<> 144:ef7eb2e8f9f7 17948 * | | |This flag will be set in one of two conditions
<> 144:ef7eb2e8f9f7 17949 * | | |l One case is that voltage on VBUS cannot reach a minimum valid threshold 4.4V within a maximum time of 100ms after OTG A device starting to drive.
<> 144:ef7eb2e8f9f7 17950 * | | |l The other case is that the supplied VBUS drops below a minimum valid threshold due to the overcurrent condition.
<> 144:ef7eb2e8f9f7 17951 * | | |Note: Write 1 to clear this flag and recover from the VBUS error state.
<> 144:ef7eb2e8f9f7 17952 * |[2] |SRPFIF |SRP Fail Interrupt Status
<> 144:ef7eb2e8f9f7 17953 * | | |After initiating SRP, an OTG B-device will wait at least TB_SRP_FAIL min, defined in OTG specification, for the OTG A-device respond This flag is set when the OTG B-device didn't get the response from the remote A-device to turn VBUS on and generate a bus reset.
<> 144:ef7eb2e8f9f7 17954 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17955 * |[3] |HNPFIF |HNP Fail Interrupt Status
<> 144:ef7eb2e8f9f7 17956 * | | |When A-device has granted B-device to be host and USB bus in SE0 state, this bit will be set in specified interval (b_ase0_brst_tmr, defined in OTG spec.
<> 144:ef7eb2e8f9f7 17957 * | | |specification), A-device does not signal connect signal.
<> 144:ef7eb2e8f9f7 17958 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17959 * |[4] |GOIDLEIF |OTG Device Goes IDLE Interrupt Status
<> 144:ef7eb2e8f9f7 17960 * | | |Flag is set if the OTG device transfers from non-idle state to idle state.
<> 144:ef7eb2e8f9f7 17961 * | | |The OTG device will be neither a host nor a peripheral.
<> 144:ef7eb2e8f9f7 17962 * | | |0 = OTG device does not go back to idle state(a_idle or b_idle).
<> 144:ef7eb2e8f9f7 17963 * | | |1 = OTG device go back to idle state(a_idle or b_idle).
<> 144:ef7eb2e8f9f7 17964 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17965 * |[5] |IDCHGIF |ID State Change Interrupt Status
<> 144:ef7eb2e8f9f7 17966 * | | |0 = IDSTS not toggled.
<> 144:ef7eb2e8f9f7 17967 * | | |1 = IDSTS from high to low or from low to high.
<> 144:ef7eb2e8f9f7 17968 * | | |Note1: OTG_CTL[BUSREQ] will be cleared when IDDIG is high.
<> 144:ef7eb2e8f9f7 17969 * | | |Note2: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17970 * |[6] |PDEVIF |Act As Peripheral Interrupt Status
<> 144:ef7eb2e8f9f7 17971 * | | |0= This device does not act as a peripheral.
<> 144:ef7eb2e8f9f7 17972 * | | |1 = This device acts as a peripheral.
<> 144:ef7eb2e8f9f7 17973 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17974 * |[7] |HOSTIF |Act As Host Interrupt Status
<> 144:ef7eb2e8f9f7 17975 * | | |0= This device does not act as a host.
<> 144:ef7eb2e8f9f7 17976 * | | |1 = This device acts as a host.
<> 144:ef7eb2e8f9f7 17977 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17978 * |[8] |BVLDCHGIF |B-Device Session Valid State Change Interrupt Status
<> 144:ef7eb2e8f9f7 17979 * | | |0 = BVLD not toggled.
<> 144:ef7eb2e8f9f7 17980 * | | |1 = BVLD from high to low or low to high.
<> 144:ef7eb2e8f9f7 17981 * | | |Note: Write 1 to clear this status.
<> 144:ef7eb2e8f9f7 17982 * |[9] |AVLDCHGIF |A-Device Session Valid State Change Interrupt Status
<> 144:ef7eb2e8f9f7 17983 * | | |0 = AVLD not toggled.
<> 144:ef7eb2e8f9f7 17984 * | | |1 = AVLD from high to low or low to high.
<> 144:ef7eb2e8f9f7 17985 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17986 * |[10] |VBCHGIF |VBVALID State Change Interrupt Status
<> 144:ef7eb2e8f9f7 17987 * | | |0 = VBUS_VLD not toggled.
<> 144:ef7eb2e8f9f7 17988 * | | |1 = VBUSVLD from high to low or from low to high.
<> 144:ef7eb2e8f9f7 17989 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17990 * |[11] |SECHGIF |SESSEND State Change Interrupt Status
<> 144:ef7eb2e8f9f7 17991 * | | |0 = Session end not toggled.
<> 144:ef7eb2e8f9f7 17992 * | | |1 = SESSEND from high to low or from low to high.
<> 144:ef7eb2e8f9f7 17993 * | | |Note: Write 1 to clear this flag.
<> 144:ef7eb2e8f9f7 17994 * |[13] |SRPDETIF |SRP Detected Interrupt Status
<> 144:ef7eb2e8f9f7 17995 * | | |0 = SRP not detected.
<> 144:ef7eb2e8f9f7 17996 * | | |1 = SRP detected.
<> 144:ef7eb2e8f9f7 17997 * | | |Note: Write 1 to clear this status.
<> 144:ef7eb2e8f9f7 17998 */
<> 144:ef7eb2e8f9f7 17999 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 18000
<> 144:ef7eb2e8f9f7 18001 /**
<> 144:ef7eb2e8f9f7 18002 * STATUS
<> 144:ef7eb2e8f9f7 18003 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18004 * Offset: 0x10 Functional Status Register
<> 144:ef7eb2e8f9f7 18005 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18006 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18007 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18008 * |[0] |OVERCUR |Over current Condition
<> 144:ef7eb2e8f9f7 18009 * | | |The voltage on VBUS cannot reach a minimum VBUS valid threshold, 4.4V minimum, within a maximum time of 100ms after OTG A device starting to drive
<> 144:ef7eb2e8f9f7 18010 * | | |0 = OTG A-device drives VBUS successfully.
<> 144:ef7eb2e8f9f7 18011 * | | |1 = Over current condition occurred.
<> 144:ef7eb2e8f9f7 18012 * |[1] |IDSTS |ID Pin State Of Mini-B/Micro-Plug
<> 144:ef7eb2e8f9f7 18013 * | | |0 = Mini-A/Micro-A plug is attached.
<> 144:ef7eb2e8f9f7 18014 * | | |1 = Mini-B/Micro-B plug is attached.
<> 144:ef7eb2e8f9f7 18015 * |[2] |SESSEND |Session End Status
<> 144:ef7eb2e8f9f7 18016 * | | |0 = VBUS > 0.8V.
<> 144:ef7eb2e8f9f7 18017 * | | |1 = VBUS < 0.2V.
<> 144:ef7eb2e8f9f7 18018 * |[3] |BVLID |B-Device Session Valid Status
<> 144:ef7eb2e8f9f7 18019 * | | |0 = VBUS < 0.8V.
<> 144:ef7eb2e8f9f7 18020 * | | |1 = VBUS > 4V.
<> 144:ef7eb2e8f9f7 18021 * |[4] |AVLD |A-Device Session Valid Status
<> 144:ef7eb2e8f9f7 18022 * | | |0 = VBUS < 0.8V.
<> 144:ef7eb2e8f9f7 18023 * | | |1 = VBUS > 2V.
<> 144:ef7eb2e8f9f7 18024 * |[5] |VBUSVLD |VBUS Valid Status
<> 144:ef7eb2e8f9f7 18025 * | | |0 = VBUS < 4.4V.
<> 144:ef7eb2e8f9f7 18026 * | | |1 = VBUS > 4.75V.
<> 144:ef7eb2e8f9f7 18027 */
<> 144:ef7eb2e8f9f7 18028 __I uint32_t STATUS;
<> 144:ef7eb2e8f9f7 18029
<> 144:ef7eb2e8f9f7 18030 } OTG_T;
<> 144:ef7eb2e8f9f7 18031
<> 144:ef7eb2e8f9f7 18032 /**
<> 144:ef7eb2e8f9f7 18033 @addtogroup OTG_CONST OTG Bit Field Definition
<> 144:ef7eb2e8f9f7 18034 Constant Definitions for OTG Controller
<> 144:ef7eb2e8f9f7 18035 @{ */
<> 144:ef7eb2e8f9f7 18036
<> 144:ef7eb2e8f9f7 18037 #define OTG_CTL_VBUSDROP_Pos (0) /*!< OTG CTL: VBUSDROP Position */
<> 144:ef7eb2e8f9f7 18038 #define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) /*!< OTG CTL: VBUSDROP Mask */
<> 144:ef7eb2e8f9f7 18039
<> 144:ef7eb2e8f9f7 18040 #define OTG_CTL_BUSREQ_Pos (1) /*!< OTG CTL: BUSREQ Position */
<> 144:ef7eb2e8f9f7 18041 #define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) /*!< OTG CTL: BUSREQ Mask */
<> 144:ef7eb2e8f9f7 18042
<> 144:ef7eb2e8f9f7 18043 #define OTG_CTL_HNPREQEN_Pos (2) /*!< OTG CTL: HNPREQEN Position */
<> 144:ef7eb2e8f9f7 18044 #define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) /*!< OTG CTL: HNPREQEN Mask */
<> 144:ef7eb2e8f9f7 18045
<> 144:ef7eb2e8f9f7 18046 #define OTG_CTL_OTGEN_Pos (4) /*!< OTG CTL: OTGEN Position */
<> 144:ef7eb2e8f9f7 18047 #define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) /*!< OTG CTL: OTGEN Mask */
<> 144:ef7eb2e8f9f7 18048
<> 144:ef7eb2e8f9f7 18049 #define OTG_CTL_PDEVCKON_Pos (7) /*!< OTG CTL: PDEVCKON Position */
<> 144:ef7eb2e8f9f7 18050 #define OTG_CTL_PDEVCKON_Msk (0x1ul << OTG_CTL_PDEVCKON_Pos) /*!< OTG CTL: PDEVCKON Mask */
<> 144:ef7eb2e8f9f7 18051
<> 144:ef7eb2e8f9f7 18052 #define OTG_CTL_WKEN_Pos (8) /*!< OTG CTL: WKEN Position */
<> 144:ef7eb2e8f9f7 18053 #define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) /*!< OTG CTL: WKEN Mask */
<> 144:ef7eb2e8f9f7 18054
<> 144:ef7eb2e8f9f7 18055 #define OTG_PHYCTL_SWPDEN_Pos (0) /*!< OTG PHYCTL: SWPDEN Position */
<> 144:ef7eb2e8f9f7 18056 #define OTG_PHYCTL_SWPDEN_Msk (0x1ul << OTG_PHYCTL_SWPDEN_Pos) /*!< OTG PHYCTL: SWPDEN Mask */
<> 144:ef7eb2e8f9f7 18057
<> 144:ef7eb2e8f9f7 18058 #define OTG_PHYCTL_DPPDEN_Pos (1) /*!< OTG PHYCTL: DPPDEN Position */
<> 144:ef7eb2e8f9f7 18059 #define OTG_PHYCTL_DPPDEN_Msk (0x1ul << OTG_PHYCTL_DPPDEN_Pos) /*!< OTG PHYCTL: DPPDEN Mask */
<> 144:ef7eb2e8f9f7 18060
<> 144:ef7eb2e8f9f7 18061 #define OTG_PHYCTL_DMPDEN_Pos (2) /*!< OTG PHYCTL: DMPDEN Position */
<> 144:ef7eb2e8f9f7 18062 #define OTG_PHYCTL_DMPDEN_Msk (0x1ul << OTG_PHYCTL_DMPDEN_Pos) /*!< OTG PHYCTL: DMPDEN Mask */
<> 144:ef7eb2e8f9f7 18063
<> 144:ef7eb2e8f9f7 18064 #define OTG_PHYCTL_VBSTSPOL_Pos (5) /*!< OTG PHYCTL: VBSTSPOL Position */
<> 144:ef7eb2e8f9f7 18065 #define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) /*!< OTG PHYCTL: VBSTSPOL Mask */
<> 144:ef7eb2e8f9f7 18066
<> 144:ef7eb2e8f9f7 18067 #define OTG_PHYCTL_VBENPOL_Pos (6) /*!< OTG PHYCTL: VBUSPOL Position */
<> 144:ef7eb2e8f9f7 18068 #define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) /*!< OTG PHYCTL: VBUSPOL Mask */
<> 144:ef7eb2e8f9f7 18069
<> 144:ef7eb2e8f9f7 18070 #define OTG_PHYCTL_IDDETEN_Pos (7) /*!< OTG PHYCTL: IDDETEN Position */
<> 144:ef7eb2e8f9f7 18071 #define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) /*!< OTG PHYCTL: IDDETEN Mask */
<> 144:ef7eb2e8f9f7 18072
<> 144:ef7eb2e8f9f7 18073 #define OTG_PHYCTL_PHYCLK_Pos (8) /*!< OTG PHYCTL: PHYCLK Position */
<> 144:ef7eb2e8f9f7 18074 #define OTG_PHYCTL_PHYCLK_Msk (0x1ul << OTG_PHYCTL_PHYCLK_Pos) /*!< OTG PHYCTL: PHYCLK Mask */
<> 144:ef7eb2e8f9f7 18075
<> 144:ef7eb2e8f9f7 18076 #define OTG_PHYCTL_OTGPHYEN_Pos (9) /*!< OTG PHYCTL: OTGPHYEN Position */
<> 144:ef7eb2e8f9f7 18077 #define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) /*!< OTG PHYCTL: OTGPHYEN Mask */
<> 144:ef7eb2e8f9f7 18078
<> 144:ef7eb2e8f9f7 18079 #define OTG_INTEN_ROLECHGIEN_Pos (0) /*!< OTG INTEN: ROLECHGIEN Position */
<> 144:ef7eb2e8f9f7 18080 #define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) /*!< OTG INTEN: ROLECHGIEN Mask */
<> 144:ef7eb2e8f9f7 18081
<> 144:ef7eb2e8f9f7 18082 #define OTG_INTEN_VBEIEN_Pos (1) /*!< OTG INTEN: VBEIEN Position */
<> 144:ef7eb2e8f9f7 18083 #define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) /*!< OTG INTEN: VBEIEN Mask */
<> 144:ef7eb2e8f9f7 18084
<> 144:ef7eb2e8f9f7 18085 #define OTG_INTEN_SRPFIEN_Pos (2) /*!< OTG INTEN: SRPFIEN Position */
<> 144:ef7eb2e8f9f7 18086 #define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) /*!< OTG INTEN: SRPFIEN Mask */
<> 144:ef7eb2e8f9f7 18087
<> 144:ef7eb2e8f9f7 18088 #define OTG_INTEN_HNPFIEN_Pos (3) /*!< OTG INTEN: HNPFIEN Position */
<> 144:ef7eb2e8f9f7 18089 #define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) /*!< OTG INTEN: HNPFIEN Mask */
<> 144:ef7eb2e8f9f7 18090
<> 144:ef7eb2e8f9f7 18091 #define OTG_INTEN_GOIDLEIEN_Pos (4) /*!< OTG INTEN: GOIDLEIEN Position */
<> 144:ef7eb2e8f9f7 18092 #define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) /*!< OTG INTEN: GOIDLEIEN Mask */
<> 144:ef7eb2e8f9f7 18093
<> 144:ef7eb2e8f9f7 18094 #define OTG_INTEN_IDCHGIEN_Pos (5) /*!< OTG INTEN: IDCHGIEN Position */
<> 144:ef7eb2e8f9f7 18095 #define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) /*!< OTG INTEN: IDCHGIEN Mask */
<> 144:ef7eb2e8f9f7 18096
<> 144:ef7eb2e8f9f7 18097 #define OTG_INTEN_PDEVIEN_Pos (6) /*!< OTG INTEN: PDEVIEN Position */
<> 144:ef7eb2e8f9f7 18098 #define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) /*!< OTG INTEN: PDEVIEN Mask */
<> 144:ef7eb2e8f9f7 18099
<> 144:ef7eb2e8f9f7 18100 #define OTG_INTEN_HOSTIEN_Pos (7) /*!< OTG INTEN: HOSTIEN Position */
<> 144:ef7eb2e8f9f7 18101 #define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) /*!< OTG INTEN: HOSTIEN Mask */
<> 144:ef7eb2e8f9f7 18102
<> 144:ef7eb2e8f9f7 18103 #define OTG_INTEN_BVLDCHGIEN_Pos (8) /*!< OTG INTEN: BVLDCHGIEN Position */
<> 144:ef7eb2e8f9f7 18104 #define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) /*!< OTG INTEN: BVLDCHGIEN Mask */
<> 144:ef7eb2e8f9f7 18105
<> 144:ef7eb2e8f9f7 18106 #define OTG_INTEN_AVLDCHGIEN_Pos (9) /*!< OTG INTEN: AVLDCHGIEN Position */
<> 144:ef7eb2e8f9f7 18107 #define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) /*!< OTG INTEN: AVLDCHGIEN Mask */
<> 144:ef7eb2e8f9f7 18108
<> 144:ef7eb2e8f9f7 18109 #define OTG_INTEN_VBCHGIEN_Pos (10) /*!< OTG INTEN: VBCHGIEN Position */
<> 144:ef7eb2e8f9f7 18110 #define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) /*!< OTG INTEN: VBCHGIEN Mask */
<> 144:ef7eb2e8f9f7 18111
<> 144:ef7eb2e8f9f7 18112 #define OTG_INTEN_SECHGIEN_Pos (11) /*!< OTG INTEN: SECHGIEN Position */
<> 144:ef7eb2e8f9f7 18113 #define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) /*!< OTG INTEN: SECHGIEN Mask */
<> 144:ef7eb2e8f9f7 18114
<> 144:ef7eb2e8f9f7 18115 #define OTG_INTEN_SRPDETIEN_Pos (13) /*!< OTG INTEN: SRPDETIEN Position */
<> 144:ef7eb2e8f9f7 18116 #define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) /*!< OTG INTEN: SRPDETIEN Mask */
<> 144:ef7eb2e8f9f7 18117
<> 144:ef7eb2e8f9f7 18118 #define OTG_INTSTS_ROLECHGIF_Pos (0) /*!< OTG INTSTS: ROLECHGIF Position */
<> 144:ef7eb2e8f9f7 18119 #define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) /*!< OTG INTSTS: ROLECHGIF Mask */
<> 144:ef7eb2e8f9f7 18120
<> 144:ef7eb2e8f9f7 18121 #define OTG_INTSTS_VBEIF_Pos (1) /*!< OTG INTSTS: VBEIF Position */
<> 144:ef7eb2e8f9f7 18122 #define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) /*!< OTG INTSTS: VBEIF Mask */
<> 144:ef7eb2e8f9f7 18123
<> 144:ef7eb2e8f9f7 18124 #define OTG_INTSTS_SRPFIF_Pos (2) /*!< OTG INTSTS: SRPFIF Position */
<> 144:ef7eb2e8f9f7 18125 #define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) /*!< OTG INTSTS: SRPFIF Mask */
<> 144:ef7eb2e8f9f7 18126
<> 144:ef7eb2e8f9f7 18127 #define OTG_INTSTS_HNPFIF_Pos (3) /*!< OTG INTSTS: HNPFIF Position */
<> 144:ef7eb2e8f9f7 18128 #define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) /*!< OTG INTSTS: HNPFIF Mask */
<> 144:ef7eb2e8f9f7 18129
<> 144:ef7eb2e8f9f7 18130 #define OTG_INTSTS_GOIDLEIF_Pos (4) /*!< OTG INTSTS: GOIDLEIF Position */
<> 144:ef7eb2e8f9f7 18131 #define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) /*!< OTG INTSTS: GOIDLEIF Mask */
<> 144:ef7eb2e8f9f7 18132
<> 144:ef7eb2e8f9f7 18133 #define OTG_INTSTS_IDCHGIF_Pos (5) /*!< OTG INTSTS: IDCHGIF Position */
<> 144:ef7eb2e8f9f7 18134 #define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) /*!< OTG INTSTS: IDCHGIF Mask */
<> 144:ef7eb2e8f9f7 18135
<> 144:ef7eb2e8f9f7 18136 #define OTG_INTSTS_PDEVIF_Pos (6) /*!< OTG INTSTS: PDEVIF Position */
<> 144:ef7eb2e8f9f7 18137 #define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) /*!< OTG INTSTS: PDEVIF Mask */
<> 144:ef7eb2e8f9f7 18138
<> 144:ef7eb2e8f9f7 18139 #define OTG_INTSTS_HOSTIF_Pos (7) /*!< OTG INTSTS: HOSTIF Position */
<> 144:ef7eb2e8f9f7 18140 #define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) /*!< OTG INTSTS: HOSTIF Mask */
<> 144:ef7eb2e8f9f7 18141
<> 144:ef7eb2e8f9f7 18142 #define OTG_INTSTS_BVLDCHGIF_Pos (8) /*!< OTG INTSTS: BVLDCHGIF Position */
<> 144:ef7eb2e8f9f7 18143 #define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) /*!< OTG INTSTS: BVLDCHGIF Mask */
<> 144:ef7eb2e8f9f7 18144
<> 144:ef7eb2e8f9f7 18145 #define OTG_INTSTS_AVLDCHGIF_Pos (9) /*!< OTG INTSTS: AVLDCHGIF Position */
<> 144:ef7eb2e8f9f7 18146 #define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) /*!< OTG INTSTS: AVLDCHGIF Mask */
<> 144:ef7eb2e8f9f7 18147
<> 144:ef7eb2e8f9f7 18148 #define OTG_INTSTS_VBCHGIF_Pos (10) /*!< OTG INTSTS: VBCHGIF Position */
<> 144:ef7eb2e8f9f7 18149 #define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) /*!< OTG INTSTS: VBCHGIF Mask */
<> 144:ef7eb2e8f9f7 18150
<> 144:ef7eb2e8f9f7 18151 #define OTG_INTSTS_SECHGIF_Pos (11) /*!< OTG INTSTS: SECHGIF Position */
<> 144:ef7eb2e8f9f7 18152 #define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) /*!< OTG INTSTS: SECHGIF Mask */
<> 144:ef7eb2e8f9f7 18153
<> 144:ef7eb2e8f9f7 18154 #define OTG_INTSTS_SRPDETIF_Pos (13) /*!< OTG INTSTS: SRPDETIF Position */
<> 144:ef7eb2e8f9f7 18155 #define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) /*!< OTG INTSTS: SRPDETIF Mask */
<> 144:ef7eb2e8f9f7 18156
<> 144:ef7eb2e8f9f7 18157 #define OTG_STATUS_OVERCUR_Pos (0) /*!< OTG STATUS: OVERCUR Position */
<> 144:ef7eb2e8f9f7 18158 #define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) /*!< OTG STATUS: OVERCUR Mask */
<> 144:ef7eb2e8f9f7 18159
<> 144:ef7eb2e8f9f7 18160 #define OTG_STATUS_IDSTS_Pos (1) /*!< OTG STATUS: IDSTS Position */
<> 144:ef7eb2e8f9f7 18161 #define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) /*!< OTG STATUS: IDSTS Mask */
<> 144:ef7eb2e8f9f7 18162
<> 144:ef7eb2e8f9f7 18163 #define OTG_STATUS_SESSEND_Pos (2) /*!< OTG STATUS: SESSEND Position */
<> 144:ef7eb2e8f9f7 18164 #define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) /*!< OTG STATUS: SESSEND Mask */
<> 144:ef7eb2e8f9f7 18165
<> 144:ef7eb2e8f9f7 18166 #define OTG_STATUS_BVLD_Pos (3) /*!< OTG STATUS: BVLD Position */
<> 144:ef7eb2e8f9f7 18167 #define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) /*!< OTG STATUS: BVLD Mask */
<> 144:ef7eb2e8f9f7 18168
<> 144:ef7eb2e8f9f7 18169 #define OTG_STATUS_AVLD_Pos (4) /*!< OTG STATUS: AVLD Position */
<> 144:ef7eb2e8f9f7 18170 #define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) /*!< OTG STATUS: AVLD Mask */
<> 144:ef7eb2e8f9f7 18171
<> 144:ef7eb2e8f9f7 18172 #define OTG_STATUS_VBUSVLD_Pos (5) /*!< OTG STATUS: VBUSVLD Position */
<> 144:ef7eb2e8f9f7 18173 #define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) /*!< OTG STATUS: VBUSVLD Mask */
<> 144:ef7eb2e8f9f7 18174
<> 144:ef7eb2e8f9f7 18175 /**@}*/ /* OTG_CONST */
<> 144:ef7eb2e8f9f7 18176 /**@}*/ /* end of OTG register group */
<> 144:ef7eb2e8f9f7 18177
<> 144:ef7eb2e8f9f7 18178
<> 144:ef7eb2e8f9f7 18179 /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
<> 144:ef7eb2e8f9f7 18180 /**
<> 144:ef7eb2e8f9f7 18181 @addtogroup PDMA Peripheral Direct Memory Access Controller(PDMA)
<> 144:ef7eb2e8f9f7 18182 Memory Mapped Structure for PDMA Controller
<> 144:ef7eb2e8f9f7 18183 @{ */
<> 144:ef7eb2e8f9f7 18184
<> 144:ef7eb2e8f9f7 18185 typedef struct {
<> 144:ef7eb2e8f9f7 18186
<> 144:ef7eb2e8f9f7 18187 /**
<> 144:ef7eb2e8f9f7 18188 * DSCTx_CTL
<> 144:ef7eb2e8f9f7 18189 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18190 * Offset: 0x00 Descriptor Table Control Register of PDMA Channel x
<> 144:ef7eb2e8f9f7 18191 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18192 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18193 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18194 * |[0:1] |OPMODE |PDMA Operation Mode Selection
<> 144:ef7eb2e8f9f7 18195 * | | |00 = Stop Mode.
<> 144:ef7eb2e8f9f7 18196 * | | |Channel is stopped or this table is complete, when PDMA finish channel table task, OPMODE will be cleared to stop mode automatically.
<> 144:ef7eb2e8f9f7 18197 * | | |01 = Basic Mode.
<> 144:ef7eb2e8f9f7 18198 * | | |The descriptor table only has one task.
<> 144:ef7eb2e8f9f7 18199 * | | |When this task is finished, the PDMA_INTSTS[x] will be asserted.
<> 144:ef7eb2e8f9f7 18200 * | | |10 = Scatter-Gather Mode.
<> 144:ef7eb2e8f9f7 18201 * | | |When operating in this mode, user must give the next descriptor table address in EMBTA_NTAAR register; PDMA will ignore this task, and then load the next task to execute.
<> 144:ef7eb2e8f9f7 18202 * | | |Note: Before filling transfer task in the descriptor table, user must check if the descriptor table is complete.
<> 144:ef7eb2e8f9f7 18203 * |[2] |TXTYPE |Request Type
<> 144:ef7eb2e8f9f7 18204 * | | |0 = Burst request type.
<> 144:ef7eb2e8f9f7 18205 * | | |1 = Single request type.
<> 144:ef7eb2e8f9f7 18206 * |[4:6] |BURSIZE |Burst Size
<> 144:ef7eb2e8f9f7 18207 * | | |This field is used for peripheral to determine the burst size or used for determine the re-arbitration size.
<> 144:ef7eb2e8f9f7 18208 * | | |But if in Single Request Type, this field is not useful and only 1 transfer item been transmitted for each transfer.
<> 144:ef7eb2e8f9f7 18209 * | | |000 = 128 transfers.
<> 144:ef7eb2e8f9f7 18210 * | | |001 = 64 transfers.
<> 144:ef7eb2e8f9f7 18211 * | | |010 = 32 transfers.
<> 144:ef7eb2e8f9f7 18212 * | | |011 = 16 transfers.
<> 144:ef7eb2e8f9f7 18213 * | | |100 = 8 transfers.
<> 144:ef7eb2e8f9f7 18214 * | | |101 = 4 transfers.
<> 144:ef7eb2e8f9f7 18215 * | | |110 = 2 transfers.
<> 144:ef7eb2e8f9f7 18216 * | | |111 = 1 transfers.
<> 144:ef7eb2e8f9f7 18217 * |[7] |TBINTDIS |Table Interrupt Disable Control
<> 144:ef7eb2e8f9f7 18218 * | | |This field can be used to decide whether to enable table interrupt or not.
<> 144:ef7eb2e8f9f7 18219 * | | |When with transfer done flag, this bit is only used for scatter-gather mode.
<> 144:ef7eb2e8f9f7 18220 * | | |If the TBINTDIS bit is enabled when PDMA finishes this task, there will no any interrupt generated.
<> 144:ef7eb2e8f9f7 18221 * | | |However, with the table empty flag, this bit is also useful.
<> 144:ef7eb2e8f9f7 18222 * | | |If it is set to '1', the TEMPTYF will not be set when this situation has happened.
<> 144:ef7eb2e8f9f7 18223 * | | |0 = Table interrupt Enabled.
<> 144:ef7eb2e8f9f7 18224 * | | |1 = Table interrupt Disabled.
<> 144:ef7eb2e8f9f7 18225 * |[8:9] |SAINC |Source Address Increment
<> 144:ef7eb2e8f9f7 18226 * | | |This field is used to set the source address increment size
<> 144:ef7eb2e8f9f7 18227 * | | |11 = No Increment (Fixed Address.).
<> 144:ef7eb2e8f9f7 18228 * | | |Other = Increment and size is depended on TXWIDTH selection.
<> 144:ef7eb2e8f9f7 18229 * |[10:11] |DAINC |Destination Address Increment
<> 144:ef7eb2e8f9f7 18230 * | | |This field is used to set the destination address increment size
<> 144:ef7eb2e8f9f7 18231 * | | |11 = No Increment (Fixed Address.).
<> 144:ef7eb2e8f9f7 18232 * | | |Other = Increment and size is depended on TXWIDTH selection.
<> 144:ef7eb2e8f9f7 18233 * |[12:13] |TXWIDTH |Transfer Width Selection
<> 144:ef7eb2e8f9f7 18234 * | | |This field is used for transfer width.
<> 144:ef7eb2e8f9f7 18235 * | | |00 = 8 bits for every transfer item.
<> 144:ef7eb2e8f9f7 18236 * | | |01 = 16 bits for every transfer item.
<> 144:ef7eb2e8f9f7 18237 * | | |10 = 32 bits for every transfer item.
<> 144:ef7eb2e8f9f7 18238 * | | |11 = Reserved.
<> 144:ef7eb2e8f9f7 18239 * | | |Note: The PDMA transfer source address (EMBTA_ENDSAR) and PDMA transfer destination address (EMBTA_ENDDAR) should be alignment under the TXWIDTH selection
<> 144:ef7eb2e8f9f7 18240 * |[16:29] |TXCNT |Transfer Count
<> 144:ef7eb2e8f9f7 18241 * | | |The TXCNT represents the required number of PDMA transfer, the real transfer count is (TXCNT + 1); The maximum transfer count is 16384 , every transfer may be byte, half-word or word that is dependent on TXWIDTH field.
<> 144:ef7eb2e8f9f7 18242 * | | |Note: When PDMA finish each transfer item, this field will be decrease imminently
<> 144:ef7eb2e8f9f7 18243 */
<> 144:ef7eb2e8f9f7 18244 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 18245
<> 144:ef7eb2e8f9f7 18246 /**
<> 144:ef7eb2e8f9f7 18247 * DSCTx_ENDSA
<> 144:ef7eb2e8f9f7 18248 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18249 * Offset: 0x04 End Source Address Register of PDMA Channel x
<> 144:ef7eb2e8f9f7 18250 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18251 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18252 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18253 * |[0:31] |ENDSA |PDMA Transfer Ending Source Address Bits
<> 144:ef7eb2e8f9f7 18254 * | | |This field indicates a 32-bit ending source address of PDMA.
<> 144:ef7eb2e8f9f7 18255 * | | |Note: If the source start address is 0x2000_0000, the transfer count is 0x100 and the source address increment is word, this field must be filled 0x2000_0400.
<> 144:ef7eb2e8f9f7 18256 * | | |The equation is "0x2000_0400 = 0x2000_0000 + 0x100*4(word)".
<> 144:ef7eb2e8f9f7 18257 */
<> 144:ef7eb2e8f9f7 18258 __IO uint32_t ENDSA;
<> 144:ef7eb2e8f9f7 18259
<> 144:ef7eb2e8f9f7 18260 /**
<> 144:ef7eb2e8f9f7 18261 * DSCTx_ENDDA
<> 144:ef7eb2e8f9f7 18262 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18263 * Offset: 0x08 End Destination Address Register of PDMA Channel x
<> 144:ef7eb2e8f9f7 18264 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18265 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18266 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18267 * |[0:31] |ENDDA |PDMA Transfer Ending Destination Address Bits
<> 144:ef7eb2e8f9f7 18268 * | | |This field indicates a 32-bit ending destination address of PDMA.
<> 144:ef7eb2e8f9f7 18269 * | | |Note: If the destination start address is 0x2000_0000, the transfer count is 0x100 and the destination address increment is word, this field must be filled 0x2000_0400.
<> 144:ef7eb2e8f9f7 18270 * | | |The equation is "0x2000_0400 = 0x2000_0000 + 0x100*4(word)".
<> 144:ef7eb2e8f9f7 18271 */
<> 144:ef7eb2e8f9f7 18272 __IO uint32_t ENDDA;
<> 144:ef7eb2e8f9f7 18273
<> 144:ef7eb2e8f9f7 18274 /**
<> 144:ef7eb2e8f9f7 18275 * DSCTx_NEXT
<> 144:ef7eb2e8f9f7 18276 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18277 * Offset: 0x0C Scatter-Gather Descriptor Table Offset Address of PDMA Channel x
<> 144:ef7eb2e8f9f7 18278 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18279 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18280 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18281 * |[2:15] |NEXT |PDMA Next Description Table Offset Address Bits
<> 144:ef7eb2e8f9f7 18282 * | | |This field indicates the offset of next descriptor table address in system memory.
<> 144:ef7eb2e8f9f7 18283 * | | |Note1: The next descriptor table address must be word boundary.
<> 144:ef7eb2e8f9f7 18284 * | | |Note2: The system memory based address is 0x2000_0000 (PDMA_ETADDR), if the next descriptor table is 0x2000_0100, that this field must fill 0x0100.
<> 144:ef7eb2e8f9f7 18285 * | | |Note3: Before filled transfer task in the description table, user must check if the descriptor table is complete.
<> 144:ef7eb2e8f9f7 18286 */
<> 144:ef7eb2e8f9f7 18287 __IO uint32_t NEXT;
<> 144:ef7eb2e8f9f7 18288
<> 144:ef7eb2e8f9f7 18289 } DSCT_T;
<> 144:ef7eb2e8f9f7 18290
<> 144:ef7eb2e8f9f7 18291 typedef struct {
<> 144:ef7eb2e8f9f7 18292 DSCT_T DSCT[16];
<> 144:ef7eb2e8f9f7 18293 uint32_t RESERVE0[192];
<> 144:ef7eb2e8f9f7 18294
<> 144:ef7eb2e8f9f7 18295 /**
<> 144:ef7eb2e8f9f7 18296 * CHCTL
<> 144:ef7eb2e8f9f7 18297 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18298 * Offset: 0x400 PDMA Channel Control Register
<> 144:ef7eb2e8f9f7 18299 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18300 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18301 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18302 * |[0:15] |CHEN |PDMA Channel Enable Control Bit[X]
<> 144:ef7eb2e8f9f7 18303 * | | |Set this bit to 1 to enable PDMA[x] operation.
<> 144:ef7eb2e8f9f7 18304 * | | |0 = PDMA channel [x] Disabled.
<> 144:ef7eb2e8f9f7 18305 * | | |1 = PDMA channel [x] Enabled.
<> 144:ef7eb2e8f9f7 18306 * | | |Note1: If software stops each PDMA transfer by setting PDMA_STOP register, this bit will be cleared automatically after finishing current transfer.
<> 144:ef7eb2e8f9f7 18307 * | | |Note2: Software reset (writing 0xFFFF_FFF to PDMA_STOP register) will clear this bit.
<> 144:ef7eb2e8f9f7 18308 * | | |Note3: If each channel is not set as enabled, each channel cannot be active.
<> 144:ef7eb2e8f9f7 18309 */
<> 144:ef7eb2e8f9f7 18310 __IO uint32_t CHCTL;
<> 144:ef7eb2e8f9f7 18311
<> 144:ef7eb2e8f9f7 18312 /**
<> 144:ef7eb2e8f9f7 18313 * STOP
<> 144:ef7eb2e8f9f7 18314 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18315 * Offset: 0x404 PDMA Stop Transfer Register
<> 144:ef7eb2e8f9f7 18316 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18317 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18318 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18319 * |[0:15] |STOP |PDMA Stop Transfer Bit [X]
<> 144:ef7eb2e8f9f7 18320 * | | |User can stop the PDMA transfer by software reset (writing all '1' to PDMA_STOP register) or by PDMA_STOP register.
<> 144:ef7eb2e8f9f7 18321 * | | |The difference between software reset and PDMA_STOP register is when software set software reset, the operation will be stopped imminently that include the on-going transfer and the channel enable bit and request active flag will be cleared to '0'.
<> 144:ef7eb2e8f9f7 18322 * | | |When software set PDMA_STOP bit, the operation will finish the on-going transfer channel and then clear the channel enable bit and request active flag.
<> 144:ef7eb2e8f9f7 18323 * | | |Software can poll channel enable bit to know if the on-going transfer is finished.
<> 144:ef7eb2e8f9f7 18324 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 18325 * | | |1 = Stop PDMA transfer[x].
<> 144:ef7eb2e8f9f7 18326 * | | |Note1: This field is Write-Only
<> 144:ef7eb2e8f9f7 18327 * | | |Note2: Setting all PDMA_STOP bit to "1" will generate software reset to reset internal state machine (the embedded table will not be reset).
<> 144:ef7eb2e8f9f7 18328 */
<> 144:ef7eb2e8f9f7 18329 __O uint32_t STOP;
<> 144:ef7eb2e8f9f7 18330
<> 144:ef7eb2e8f9f7 18331 /**
<> 144:ef7eb2e8f9f7 18332 * SWREQ
<> 144:ef7eb2e8f9f7 18333 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18334 * Offset: 0x408 PDMA Software Request Register
<> 144:ef7eb2e8f9f7 18335 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18336 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18337 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18338 * |[0:11] |SWREQ |PDMA Software Request Bit [X]
<> 144:ef7eb2e8f9f7 18339 * | | |Set this bit to 1 to generate a software request to PDMA [x].
<> 144:ef7eb2e8f9f7 18340 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 18341 * | | |1 = Generate a software request.
<> 144:ef7eb2e8f9f7 18342 * | | |Note1: This field is Write-Only.
<> 144:ef7eb2e8f9f7 18343 * | | |Software can indicate which channel is on active by reading PDMA_TRGSTS register.
<> 144:ef7eb2e8f9f7 18344 * | | |Active flag may be triggered by software request or peripheral request.
<> 144:ef7eb2e8f9f7 18345 * | | |Note2: If user does not enable each PDMA channel, the software request will be ignored.
<> 144:ef7eb2e8f9f7 18346 */
<> 144:ef7eb2e8f9f7 18347 __O uint32_t SWREQ;
<> 144:ef7eb2e8f9f7 18348
<> 144:ef7eb2e8f9f7 18349 /**
<> 144:ef7eb2e8f9f7 18350 * TRGSTS
<> 144:ef7eb2e8f9f7 18351 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18352 * Offset: 0x40C PDMA Request Active Flag Register
<> 144:ef7eb2e8f9f7 18353 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18354 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18355 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18356 * |[0:15] |REQSTS |PDMA Request Active Flag [X]
<> 144:ef7eb2e8f9f7 18357 * | | |This flag indicates whether channel[x] have a request or not.
<> 144:ef7eb2e8f9f7 18358 * | | |0 = Have no requests.
<> 144:ef7eb2e8f9f7 18359 * | | |1 = Have a request.
<> 144:ef7eb2e8f9f7 18360 * | | |Note1: The request may come from software request (SWREQ) or peripheral request.
<> 144:ef7eb2e8f9f7 18361 * | | |Note2: When PDMA finishes channel transfer, this bit will be cleared automatically
<> 144:ef7eb2e8f9f7 18362 * | | |Note3: Software reset (setting PDMA_STOP to 0xFFFF_FFFF) will clear this bit.
<> 144:ef7eb2e8f9f7 18363 */
<> 144:ef7eb2e8f9f7 18364 __I uint32_t TRGSTS;
<> 144:ef7eb2e8f9f7 18365
<> 144:ef7eb2e8f9f7 18366 /**
<> 144:ef7eb2e8f9f7 18367 * PRISET
<> 144:ef7eb2e8f9f7 18368 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18369 * Offset: 0x410 PDMA Fixed Priority Setting Register
<> 144:ef7eb2e8f9f7 18370 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18371 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18372 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18373 * |[0:15] |FPRISET |PDMA Fixed Priority Setting Bit[X]
<> 144:ef7eb2e8f9f7 18374 * | | |Set this bit to 1 to enable fix priority level.
<> 144:ef7eb2e8f9f7 18375 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 18376 * | | |1 = Set PDMA channel [x] be fixed priority channel.
<> 144:ef7eb2e8f9f7 18377 * | | |The PDMA channel priority is shown in the following table.
<> 144:ef7eb2e8f9f7 18378 */
<> 144:ef7eb2e8f9f7 18379 __IO uint32_t PRISET;
<> 144:ef7eb2e8f9f7 18380
<> 144:ef7eb2e8f9f7 18381 /**
<> 144:ef7eb2e8f9f7 18382 * PRICLR
<> 144:ef7eb2e8f9f7 18383 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18384 * Offset: 0x414 PDMA Fixed Priority Clear Register
<> 144:ef7eb2e8f9f7 18385 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18386 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18387 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18388 * |[0:15] |FPRICLR |PDMA Fix Priority Clear Bit [X]
<> 144:ef7eb2e8f9f7 18389 * | | |Set this bit to 1 to clear fixed priority level.
<> 144:ef7eb2e8f9f7 18390 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 18391 * | | |1 = Set PDMA channel [x] to be round-robin priority channel.
<> 144:ef7eb2e8f9f7 18392 * | | |Note: This field is Write-Only, and software can indicate the channel priority by reading PDMA_FPIOSEL register.
<> 144:ef7eb2e8f9f7 18393 */
<> 144:ef7eb2e8f9f7 18394 __O uint32_t PRICLR;
<> 144:ef7eb2e8f9f7 18395
<> 144:ef7eb2e8f9f7 18396 /**
<> 144:ef7eb2e8f9f7 18397 * INTEN
<> 144:ef7eb2e8f9f7 18398 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18399 * Offset: 0x418 PDMA Interrupt Enable Control Register
<> 144:ef7eb2e8f9f7 18400 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18401 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18402 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18403 * |[0:15] |INTEN |PDMA Interrupt Enable Control Register [X]
<> 144:ef7eb2e8f9f7 18404 * | | |This field is used for enabling PDMA channel[x] interrupt.
<> 144:ef7eb2e8f9f7 18405 * | | |0 = PDMA channel [x] interrupt Disabled.
<> 144:ef7eb2e8f9f7 18406 * | | |1 = PDMA channel [x] interrupt Enabled.
<> 144:ef7eb2e8f9f7 18407 */
<> 144:ef7eb2e8f9f7 18408 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 18409
<> 144:ef7eb2e8f9f7 18410 /**
<> 144:ef7eb2e8f9f7 18411 * INTSTS
<> 144:ef7eb2e8f9f7 18412 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18413 * Offset: 0x41C PDMA Interrupt Status Register
<> 144:ef7eb2e8f9f7 18414 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18415 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18416 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18417 * |[0] |ABTIF |PDMA Read/Write Target Abort Interrupt Status Flag
<> 144:ef7eb2e8f9f7 18418 * | | |This bit indicates that PDMA has target abort error; Software can read PDMA_TABORTF register to find which channel has target abort error.
<> 144:ef7eb2e8f9f7 18419 * | | |0 = No bus ERROR response received.
<> 144:ef7eb2e8f9f7 18420 * | | |1 = Bus ERROR response received.
<> 144:ef7eb2e8f9f7 18421 * | | |Note: This field is read only.
<> 144:ef7eb2e8f9f7 18422 * |[1] |TDIF |Transfer Done Interrupt Status Flag
<> 144:ef7eb2e8f9f7 18423 * | | |This bit indicates that PDMA has finished transmission; Software can read PDMA_TDSTS register to indicate which channel finished transfer.
<> 144:ef7eb2e8f9f7 18424 * | | |0 = Not finished yet.
<> 144:ef7eb2e8f9f7 18425 * | | |1 = PDMA channel has finished transmission.
<> 144:ef7eb2e8f9f7 18426 * | | |Note: This field is Read only.
<> 144:ef7eb2e8f9f7 18427 * |[2] |TEIF |Table Empty Interrupt Status Flag
<> 144:ef7eb2e8f9f7 18428 * | | |This bit indicates that PDMA has finished each table transmission and the operation is Stop mode.
<> 144:ef7eb2e8f9f7 18429 * | | |Software can read TEIF register to indicate which channel finished transfer.
<> 144:ef7eb2e8f9f7 18430 * | | |0 = Not finished yet.
<> 144:ef7eb2e8f9f7 18431 * | | |1 = PDMA channel has finished and the operation is Stop mode.
<> 144:ef7eb2e8f9f7 18432 * | | |Note: This field is Read only.
<> 144:ef7eb2e8f9f7 18433 * |[8:23] |REQTOFX |Time-Out Status Flag For Each Channel
<> 144:ef7eb2e8f9f7 18434 * | | |This flag indicates that PDMA has waited peripheral request for a period defined by TIMECNTX
<> 144:ef7eb2e8f9f7 18435 * | | |0 = No time-out flag.
<> 144:ef7eb2e8f9f7 18436 * | | |1 = Time-out flag.
<> 144:ef7eb2e8f9f7 18437 * | | |Note: This field is Read only, but software can write 1 to clear it.
<> 144:ef7eb2e8f9f7 18438 */
<> 144:ef7eb2e8f9f7 18439 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 18440
<> 144:ef7eb2e8f9f7 18441 /**
<> 144:ef7eb2e8f9f7 18442 * ABTSTS
<> 144:ef7eb2e8f9f7 18443 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18444 * Offset: 0x420 PDMA Read/Write Target Abort Flag Register
<> 144:ef7eb2e8f9f7 18445 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18446 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18447 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18448 * |[0:15] |ABTIF |PDMA Read/Write Target Abort Interrupt Status Flag
<> 144:ef7eb2e8f9f7 18449 * | | |This bit indicates which PDMA has target abort error
<> 144:ef7eb2e8f9f7 18450 * | | |0 = No bus ERROR response received.
<> 144:ef7eb2e8f9f7 18451 * | | |1 = Bus ERROR response received.
<> 144:ef7eb2e8f9f7 18452 * | | |Note: This field is read only, but software can write 1 to clear it.
<> 144:ef7eb2e8f9f7 18453 */
<> 144:ef7eb2e8f9f7 18454 __IO uint32_t ABTSTS;
<> 144:ef7eb2e8f9f7 18455
<> 144:ef7eb2e8f9f7 18456 /**
<> 144:ef7eb2e8f9f7 18457 * TDSTS
<> 144:ef7eb2e8f9f7 18458 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18459 * Offset: 0x424 PDMA Transfer Done Flag Register
<> 144:ef7eb2e8f9f7 18460 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18461 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18462 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18463 * |[0:15] |TDIF |Transfer Done Flag [X]
<> 144:ef7eb2e8f9f7 18464 * | | |This bit indicates which PDMA channel has finished transmission.
<> 144:ef7eb2e8f9f7 18465 * | | |0 = Not finished yet.
<> 144:ef7eb2e8f9f7 18466 * | | |1 = PDMA channel has finished transmission.
<> 144:ef7eb2e8f9f7 18467 * | | |Note: This field is read only, but software can write 1 to clear.
<> 144:ef7eb2e8f9f7 18468 */
<> 144:ef7eb2e8f9f7 18469 __IO uint32_t TDSTS;
<> 144:ef7eb2e8f9f7 18470
<> 144:ef7eb2e8f9f7 18471 /**
<> 144:ef7eb2e8f9f7 18472 * SCATSTS
<> 144:ef7eb2e8f9f7 18473 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18474 * Offset: 0x428 PDMA Scatter-Gather Transfer Done Flag Register
<> 144:ef7eb2e8f9f7 18475 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18476 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18477 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18478 * |[0:15] |TEMPTYF |Table Empty Flag Bit [X]
<> 144:ef7eb2e8f9f7 18479 * | | |This bit indicates which PDMA channel table has finished transmission and the operation mode is Stop mode
<> 144:ef7eb2e8f9f7 18480 * | | |0 = Not finished or not in Stop mode.
<> 144:ef7eb2e8f9f7 18481 * | | |1 = PDMA channel has finished transmission and the operation is Stop mode.
<> 144:ef7eb2e8f9f7 18482 * | | |Note: This field is read only, but software can write 1 to clear.
<> 144:ef7eb2e8f9f7 18483 */
<> 144:ef7eb2e8f9f7 18484 __IO uint32_t SCATSTS;
<> 144:ef7eb2e8f9f7 18485
<> 144:ef7eb2e8f9f7 18486 /**
<> 144:ef7eb2e8f9f7 18487 * TACTSTS
<> 144:ef7eb2e8f9f7 18488 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18489 * Offset: 0x42C PDMA Transfer on Active Flag Register
<> 144:ef7eb2e8f9f7 18490 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18491 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18492 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18493 * |[0:15] |TXACTF |Transfer On Active Flag Bit [X]
<> 144:ef7eb2e8f9f7 18494 * | | |This bit indicates which PDMA channel is on active.
<> 144:ef7eb2e8f9f7 18495 * | | |0 = PDMA channel is not finished.
<> 144:ef7eb2e8f9f7 18496 * | | |1 = PDMA channel is on active.
<> 144:ef7eb2e8f9f7 18497 */
<> 144:ef7eb2e8f9f7 18498 __I uint32_t TACTSTS;
<> 144:ef7eb2e8f9f7 18499 uint32_t RESERVE1[3];
<> 144:ef7eb2e8f9f7 18500
<> 144:ef7eb2e8f9f7 18501
<> 144:ef7eb2e8f9f7 18502 /**
<> 144:ef7eb2e8f9f7 18503 * SCATBA
<> 144:ef7eb2e8f9f7 18504 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18505 * Offset: 0x43C PDMA Scatter-Gather Descriptor Table Base Address Register
<> 144:ef7eb2e8f9f7 18506 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18507 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18508 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18509 * |[16:31] |SCATBA |PDMA Scatter-Gather Descriptor Table Base Address Bits
<> 144:ef7eb2e8f9f7 18510 * | | |In Scatter-Gather mode, this is the base address for calculating the next link - list address.
<> 144:ef7eb2e8f9f7 18511 * | | |The next link address equation is.
<> 144:ef7eb2e8f9f7 18512 * | | |Next Link Address = { SCATBA[15:0], EMBTA_NTAAR[15:2], 2'b00}.
<> 144:ef7eb2e8f9f7 18513 * | | |Note: Only useful in Scatter-Gather mode.
<> 144:ef7eb2e8f9f7 18514 */
<> 144:ef7eb2e8f9f7 18515 __IO uint32_t SCATBA;
<> 144:ef7eb2e8f9f7 18516
<> 144:ef7eb2e8f9f7 18517 /**
<> 144:ef7eb2e8f9f7 18518 * TOC0_1
<> 144:ef7eb2e8f9f7 18519 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18520 * Offset: 0x440 PDMA Time-out Period Counter Ch1 and Ch0 Register
<> 144:ef7eb2e8f9f7 18521 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18522 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18523 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18524 * |[0:15] |TOC0 |Time-Out Period Counter For Channel 0
<> 144:ef7eb2e8f9f7 18525 * | | |This controls the period of time-out function for channel 0.
<> 144:ef7eb2e8f9f7 18526 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18527 * |[16:31] |TOC1 |Time-Out Period Counter For Channel 1
<> 144:ef7eb2e8f9f7 18528 * | | |This controls the period of time-out function for channel 1.
<> 144:ef7eb2e8f9f7 18529 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18530 */
<> 144:ef7eb2e8f9f7 18531 __IO uint32_t TOC0_1;
<> 144:ef7eb2e8f9f7 18532
<> 144:ef7eb2e8f9f7 18533 /**
<> 144:ef7eb2e8f9f7 18534 * TOC2_3
<> 144:ef7eb2e8f9f7 18535 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18536 * Offset: 0x444 PDMA Time-out Period Counter Ch3 and Ch2 Register
<> 144:ef7eb2e8f9f7 18537 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18538 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18539 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18540 * |[0:15] |TOC2 |Time-Out Period Counter For Channel 2
<> 144:ef7eb2e8f9f7 18541 * | | |This controls the period of time-out function for channel 2.
<> 144:ef7eb2e8f9f7 18542 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18543 * |[16:31] |TOC3 |Time-Out Period Counter For Channel 3
<> 144:ef7eb2e8f9f7 18544 * | | |This controls the period of time-out function for channel 3.
<> 144:ef7eb2e8f9f7 18545 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18546 */
<> 144:ef7eb2e8f9f7 18547 __IO uint32_t TOC2_3;
<> 144:ef7eb2e8f9f7 18548
<> 144:ef7eb2e8f9f7 18549 /**
<> 144:ef7eb2e8f9f7 18550 * TOC4_5
<> 144:ef7eb2e8f9f7 18551 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18552 * Offset: 0x448 PDMA Time-out Period Counter Ch5 and Ch4 Register
<> 144:ef7eb2e8f9f7 18553 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18554 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18555 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18556 * |[0:15] |TOC4 |Time-Out Period Counter For Channel 4
<> 144:ef7eb2e8f9f7 18557 * | | |This controls the period of time-out function for channel 4.
<> 144:ef7eb2e8f9f7 18558 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18559 * |[16:31] |TOC5 |Time-Out Period Counter For Channel 5
<> 144:ef7eb2e8f9f7 18560 * | | |This controls the period of time-out function for channel 5.
<> 144:ef7eb2e8f9f7 18561 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18562 */
<> 144:ef7eb2e8f9f7 18563 __IO uint32_t TOC4_5;
<> 144:ef7eb2e8f9f7 18564
<> 144:ef7eb2e8f9f7 18565 /**
<> 144:ef7eb2e8f9f7 18566 * TOC6_7
<> 144:ef7eb2e8f9f7 18567 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18568 * Offset: 0x44C PDMA Time-out Period Counter Ch7 and Ch6 Register
<> 144:ef7eb2e8f9f7 18569 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18570 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18571 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18572 * |[0:15] |TOC6 |Time-Out Period Counter For Channel 6
<> 144:ef7eb2e8f9f7 18573 * | | |This controls the period of time-out function for channel 6.
<> 144:ef7eb2e8f9f7 18574 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18575 * |[16:31] |TOC7 |Time-Out Period Counter For Channel 7
<> 144:ef7eb2e8f9f7 18576 * | | |This controls the period of time-out function for channel 7.
<> 144:ef7eb2e8f9f7 18577 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18578 */
<> 144:ef7eb2e8f9f7 18579 __IO uint32_t TOC6_7;
<> 144:ef7eb2e8f9f7 18580
<> 144:ef7eb2e8f9f7 18581 /**
<> 144:ef7eb2e8f9f7 18582 * TOC8_9
<> 144:ef7eb2e8f9f7 18583 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18584 * Offset: 0x450 PDMA Time-out Period Counter Ch9 and Ch8 Register
<> 144:ef7eb2e8f9f7 18585 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18586 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18587 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18588 * |[0:15] |TOC8 |Time-Out Period Counter For Channel 8
<> 144:ef7eb2e8f9f7 18589 * | | |This controls the period of time-out function for channel 8.
<> 144:ef7eb2e8f9f7 18590 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18591 * |[16:31] |TOC9 |Time-Out Period Counter For Channel 9
<> 144:ef7eb2e8f9f7 18592 * | | |This controls the period of time-out function for channel 9.
<> 144:ef7eb2e8f9f7 18593 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18594 */
<> 144:ef7eb2e8f9f7 18595 __IO uint32_t TOC8_9;
<> 144:ef7eb2e8f9f7 18596
<> 144:ef7eb2e8f9f7 18597 /**
<> 144:ef7eb2e8f9f7 18598 * TOC10_11
<> 144:ef7eb2e8f9f7 18599 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18600 * Offset: 0x454 PDMA Time-out Period Counter Ch11 and Ch10 Register
<> 144:ef7eb2e8f9f7 18601 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18602 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18603 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18604 * |[0:15] |TOC10 |Time-Out Period Counter For Channel 10
<> 144:ef7eb2e8f9f7 18605 * | | |This controls the period of time-out function for channel 10.
<> 144:ef7eb2e8f9f7 18606 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18607 * |[16:31] |TOC11 |Time-Out Period Counter For Channel 11
<> 144:ef7eb2e8f9f7 18608 * | | |This controls the period of time-out function for channel 11.
<> 144:ef7eb2e8f9f7 18609 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18610 */
<> 144:ef7eb2e8f9f7 18611 __IO uint32_t TOC10_11;
<> 144:ef7eb2e8f9f7 18612
<> 144:ef7eb2e8f9f7 18613 /**
<> 144:ef7eb2e8f9f7 18614 * TOC12_13
<> 144:ef7eb2e8f9f7 18615 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18616 * Offset: 0x458 PDMA Time-out Period Counter Ch13 and Ch12 Register
<> 144:ef7eb2e8f9f7 18617 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18618 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18619 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18620 * |[0:15] |TOC12 |Time-Out Period Counter For Channel 12
<> 144:ef7eb2e8f9f7 18621 * | | |This controls the period of time-out function for channel 12.
<> 144:ef7eb2e8f9f7 18622 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18623 * |[16:31] |TOC13 |Time-Out Period Counter For Channel 13
<> 144:ef7eb2e8f9f7 18624 * | | |This controls the period of time-out function for channel 13.
<> 144:ef7eb2e8f9f7 18625 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18626 */
<> 144:ef7eb2e8f9f7 18627 __IO uint32_t TOC12_13;
<> 144:ef7eb2e8f9f7 18628
<> 144:ef7eb2e8f9f7 18629 /**
<> 144:ef7eb2e8f9f7 18630 * TOC14_15
<> 144:ef7eb2e8f9f7 18631 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18632 * Offset: 0x45C PDMA Time-out Period Counter Ch15 and Ch14 Register
<> 144:ef7eb2e8f9f7 18633 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18634 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18635 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18636 * |[0:15] |TOC14 |Time-Out Period Counter For Channel 14
<> 144:ef7eb2e8f9f7 18637 * | | |This control the period of time-out function for channel 14.
<> 144:ef7eb2e8f9f7 18638 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18639 * |[16:31] |TOC15 |Time-Out Period Counter For Channel 15
<> 144:ef7eb2e8f9f7 18640 * | | |This control the period of time-out function for channel 15.
<> 144:ef7eb2e8f9f7 18641 * | | |The calculation unit is based on 10 kHz clock.
<> 144:ef7eb2e8f9f7 18642 */
<> 144:ef7eb2e8f9f7 18643 __IO uint32_t TOC14_15;
<> 144:ef7eb2e8f9f7 18644 uint32_t RESERVE2[8];
<> 144:ef7eb2e8f9f7 18645
<> 144:ef7eb2e8f9f7 18646
<> 144:ef7eb2e8f9f7 18647 /**
<> 144:ef7eb2e8f9f7 18648 * REQSEL0_3
<> 144:ef7eb2e8f9f7 18649 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18650 * Offset: 0x480 PDMA Source Module Select Register 0
<> 144:ef7eb2e8f9f7 18651 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18652 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18653 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18654 * |[0:4] |REQSRC0 |Channel 0 Selection
<> 144:ef7eb2e8f9f7 18655 * | | |This filed defines which peripheral is connected to PDMA channel 0.
<> 144:ef7eb2e8f9f7 18656 * | | |Software can configure the peripheral by setting REQSRC0.
<> 144:ef7eb2e8f9f7 18657 * | | |00000 = Connect to SPI0_TX.
<> 144:ef7eb2e8f9f7 18658 * | | |00001 = Connect to SPI1_TX.
<> 144:ef7eb2e8f9f7 18659 * | | |00010 = Connect to SPI2_TX.
<> 144:ef7eb2e8f9f7 18660 * | | |00011 = Connect to SPI3_TX.
<> 144:ef7eb2e8f9f7 18661 * | | |00100 = Connect to UART0_TX.
<> 144:ef7eb2e8f9f7 18662 * | | |00101 = Connect to UART1_TX.
<> 144:ef7eb2e8f9f7 18663 * | | |00110 = Connect to UART2_TX.
<> 144:ef7eb2e8f9f7 18664 * | | |00111 = Connect to UART3_TX.
<> 144:ef7eb2e8f9f7 18665 * | | |01000 = Connect to UART4_TX.
<> 144:ef7eb2e8f9f7 18666 * | | |01001 = Connect to UART5_TX.
<> 144:ef7eb2e8f9f7 18667 * | | |01010 = Reserved.
<> 144:ef7eb2e8f9f7 18668 * | | |01011 = Connect to I2S_TX.
<> 144:ef7eb2e8f9f7 18669 * | | |01100 = Connect to I2S1_TX.
<> 144:ef7eb2e8f9f7 18670 * | | |01101 = Connect to SPI0_RX.
<> 144:ef7eb2e8f9f7 18671 * | | |01110 = Connect to SPI1_RX.
<> 144:ef7eb2e8f9f7 18672 * | | |01111 = Connect to SPI2_RX.
<> 144:ef7eb2e8f9f7 18673 * | | |10000 = Connect to SPI3_RX.
<> 144:ef7eb2e8f9f7 18674 * | | |10001 = Connect to UART0_RX.
<> 144:ef7eb2e8f9f7 18675 * | | |10010 = Connect to UART1_RX.
<> 144:ef7eb2e8f9f7 18676 * | | |10011 = Connect to UART2_RX.
<> 144:ef7eb2e8f9f7 18677 * | | |10100 = Connect to UART3_RX.
<> 144:ef7eb2e8f9f7 18678 * | | |10101 = Connect to UART4_RX.
<> 144:ef7eb2e8f9f7 18679 * | | |10110 = Connect to UART5_RX.
<> 144:ef7eb2e8f9f7 18680 * | | |10111 = Reserved.
<> 144:ef7eb2e8f9f7 18681 * | | |11000 = Connect to ADC.
<> 144:ef7eb2e8f9f7 18682 * | | |11001 = Connect to I2S_RX.
<> 144:ef7eb2e8f9f7 18683 * | | |11010 = Connect to I2S1_RX.
<> 144:ef7eb2e8f9f7 18684 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 18685 * |[8:12] |REQSRC1 |Channel 1 Selection
<> 144:ef7eb2e8f9f7 18686 * | | |This filed defines which peripheral is connected to PDMA channel 1.
<> 144:ef7eb2e8f9f7 18687 * | | |Software can configure the peripheral setting by REQSRC1.
<> 144:ef7eb2e8f9f7 18688 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18689 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18690 * |[16:20] |REQSRC2 |Channel 2 Selection
<> 144:ef7eb2e8f9f7 18691 * | | |This filed defines which peripheral is connected to PDMA channel 2.
<> 144:ef7eb2e8f9f7 18692 * | | |Software can configure the peripheral setting by REQSRC2.
<> 144:ef7eb2e8f9f7 18693 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18694 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18695 * |[24:28] |REQSRC3 |Channel 3 Selection
<> 144:ef7eb2e8f9f7 18696 * | | |This filed defines which peripheral is connected to PDMA channel 3.
<> 144:ef7eb2e8f9f7 18697 * | | |Software can configure the peripheral setting by REQSRC3.
<> 144:ef7eb2e8f9f7 18698 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18699 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18700 */
<> 144:ef7eb2e8f9f7 18701 __IO uint32_t REQSEL0_3;
<> 144:ef7eb2e8f9f7 18702
<> 144:ef7eb2e8f9f7 18703 /**
<> 144:ef7eb2e8f9f7 18704 * REQSEL4_7
<> 144:ef7eb2e8f9f7 18705 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18706 * Offset: 0x484 PDMA Source Module Select Register 1
<> 144:ef7eb2e8f9f7 18707 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18708 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18709 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18710 * |[0:4] |REQSRC4 |Channel 0 Selection
<> 144:ef7eb2e8f9f7 18711 * | | |This filed defines which peripheral is connected to PDMA channel 4.
<> 144:ef7eb2e8f9f7 18712 * | | |Software can configure the peripheral setting by REQSRC4.
<> 144:ef7eb2e8f9f7 18713 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18714 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18715 * |[8:12] |REQSRC5 |Channel 1 Selection
<> 144:ef7eb2e8f9f7 18716 * | | |This filed defines which peripheral is connected to PDMA channel 5.
<> 144:ef7eb2e8f9f7 18717 * | | |Software can configure the peripheral setting by REQSRC5.
<> 144:ef7eb2e8f9f7 18718 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18719 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18720 * |[16:20] |REQSRC6 |Channel 6 Selection
<> 144:ef7eb2e8f9f7 18721 * | | |This filed defines which peripheral is connected to PDMA channel 6.
<> 144:ef7eb2e8f9f7 18722 * | | |Software can configure the peripheral setting by REQSRC6.
<> 144:ef7eb2e8f9f7 18723 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18724 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18725 * |[24:28] |REQSRC7 |Channel 7 Selection
<> 144:ef7eb2e8f9f7 18726 * | | |This filed defines which peripheral is connected to PDMA channel 7.
<> 144:ef7eb2e8f9f7 18727 * | | |Software can configure the peripheral setting by REQSRC7.
<> 144:ef7eb2e8f9f7 18728 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18729 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18730 */
<> 144:ef7eb2e8f9f7 18731 __IO uint32_t REQSEL4_7;
<> 144:ef7eb2e8f9f7 18732
<> 144:ef7eb2e8f9f7 18733 /**
<> 144:ef7eb2e8f9f7 18734 * REQSEL8_11
<> 144:ef7eb2e8f9f7 18735 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18736 * Offset: 0x488 PDMA Source Module Select Register 2
<> 144:ef7eb2e8f9f7 18737 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18738 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18739 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18740 * |[0:4] |REQSRC8 |Channel 8 Selection
<> 144:ef7eb2e8f9f7 18741 * | | |This filed defines which peripheral is connected to PDMA channel 8.
<> 144:ef7eb2e8f9f7 18742 * | | |Software can configure the peripheral setting by REQSRC8.
<> 144:ef7eb2e8f9f7 18743 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18744 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18745 * |[8:12] |REQSRC9 |Channel 9 Selection
<> 144:ef7eb2e8f9f7 18746 * | | |This filed defines which peripheral is connected to PDMA channel 9.
<> 144:ef7eb2e8f9f7 18747 * | | |Software can configure the peripheral setting by REQSRC9.
<> 144:ef7eb2e8f9f7 18748 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18749 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18750 * |[16:20] |REQSRC10 |Channel 10 Selection
<> 144:ef7eb2e8f9f7 18751 * | | |This filed defines which peripheral is connected to PDMA channel 10.
<> 144:ef7eb2e8f9f7 18752 * | | |Software can configure the peripheral setting by REQSRC10.
<> 144:ef7eb2e8f9f7 18753 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18754 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18755 * |[24:28] |REQSRC11 |Channel 11 Selection
<> 144:ef7eb2e8f9f7 18756 * | | |This filed defines which peripheral is connected to PDMA channel 11.
<> 144:ef7eb2e8f9f7 18757 * | | |Software can configure the peripheral setting by REQSRC11.
<> 144:ef7eb2e8f9f7 18758 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18759 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18760 */
<> 144:ef7eb2e8f9f7 18761 __IO uint32_t REQSEL8_11;
<> 144:ef7eb2e8f9f7 18762
<> 144:ef7eb2e8f9f7 18763 /**
<> 144:ef7eb2e8f9f7 18764 * REQSEL12_15
<> 144:ef7eb2e8f9f7 18765 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18766 * Offset: 0x48C PDMA Source Module Select Register 3
<> 144:ef7eb2e8f9f7 18767 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18768 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18769 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18770 * |[0:4] |REQSRC12 |Channel 12 Selection
<> 144:ef7eb2e8f9f7 18771 * | | |This filed defines which peripheral is connected to PDMA channel 12.
<> 144:ef7eb2e8f9f7 18772 * | | |Software can configure the peripheral setting by REQSRC12.
<> 144:ef7eb2e8f9f7 18773 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18774 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18775 * |[8:12] |REQSRC13 |Channel 13 Selection
<> 144:ef7eb2e8f9f7 18776 * | | |This filed defines which peripheral is connected to PDMA channel 13.
<> 144:ef7eb2e8f9f7 18777 * | | |Software can configure the peripheral setting by REQSRC13.
<> 144:ef7eb2e8f9f7 18778 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18779 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18780 * |[16:20] |REQSRC14 |Channel 14 Selection
<> 144:ef7eb2e8f9f7 18781 * | | |This filed defines which peripheral is connected to PDMA channel 14.
<> 144:ef7eb2e8f9f7 18782 * | | |Software can configure the peripheral setting by REQSRC14.
<> 144:ef7eb2e8f9f7 18783 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18784 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18785 * |[24:28] |REQSRC15 |Channel 15 Selection
<> 144:ef7eb2e8f9f7 18786 * | | |This filed defines which peripheral is connected to PDMA channel 15.
<> 144:ef7eb2e8f9f7 18787 * | | |Software can configure the peripheral setting by REQSRC15.
<> 144:ef7eb2e8f9f7 18788 * | | |The channel configuration is the same as REQSRC0 field.
<> 144:ef7eb2e8f9f7 18789 * | | |Please refer to the explanation of REQSRC0.
<> 144:ef7eb2e8f9f7 18790 */
<> 144:ef7eb2e8f9f7 18791 __IO uint32_t REQSEL12_15;
<> 144:ef7eb2e8f9f7 18792
<> 144:ef7eb2e8f9f7 18793 } PDMA_T;
<> 144:ef7eb2e8f9f7 18794
<> 144:ef7eb2e8f9f7 18795 /**
<> 144:ef7eb2e8f9f7 18796 @addtogroup PDMA_CONST PDMA Bit Field Definition
<> 144:ef7eb2e8f9f7 18797 Constant Definitions for PDMA Controller
<> 144:ef7eb2e8f9f7 18798 @{ */
<> 144:ef7eb2e8f9f7 18799
<> 144:ef7eb2e8f9f7 18800 #define PDMA_DSCT_CTL_OPMODE_Pos (0) /*!< PDMA DSCT_CTL: OPMODE Position */
<> 144:ef7eb2e8f9f7 18801 #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) /*!< PDMA DSCT_CTL: OPMODE Mask */
<> 144:ef7eb2e8f9f7 18802
<> 144:ef7eb2e8f9f7 18803 #define PDMA_DSCT_CTL_TXTYPE_Pos (2) /*!< PDMA DSCT_CTL: TXTYPE Position */
<> 144:ef7eb2e8f9f7 18804 #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) /*!< PDMA DSCT_CTL: TXTYPE Mask */
<> 144:ef7eb2e8f9f7 18805
<> 144:ef7eb2e8f9f7 18806 #define PDMA_DSCT_CTL_BURSIZE_Pos (4) /*!< PDMA DSCT_CTL: BURSIZE Position */
<> 144:ef7eb2e8f9f7 18807 #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) /*!< PDMA DSCT_CTL: BURSIZE Mask */
<> 144:ef7eb2e8f9f7 18808
<> 144:ef7eb2e8f9f7 18809 #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) /*!< PDMA DSCT_CTL: TBINTDIS Position */
<> 144:ef7eb2e8f9f7 18810 #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) /*!< PDMA DSCT_CTL: TBINTDIS Mask */
<> 144:ef7eb2e8f9f7 18811
<> 144:ef7eb2e8f9f7 18812 #define PDMA_DSCT_CTL_SAINC_Pos (8) /*!< PDMA DSCT_CTL: SAINC Position */
<> 144:ef7eb2e8f9f7 18813 #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) /*!< PDMA DSCT_CTL: SAINC Mask */
<> 144:ef7eb2e8f9f7 18814
<> 144:ef7eb2e8f9f7 18815 #define PDMA_DSCT_CTL_DAINC_Pos (10) /*!< PDMA DSCT_CTL: DAINC Position */
<> 144:ef7eb2e8f9f7 18816 #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) /*!< PDMA DSCT_CTL: DAINC Mask */
<> 144:ef7eb2e8f9f7 18817
<> 144:ef7eb2e8f9f7 18818 #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) /*!< PDMA DSCT_CTL: TXWIDTH Position */
<> 144:ef7eb2e8f9f7 18819 #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) /*!< PDMA DSCT_CTL: TXWIDTH Mask */
<> 144:ef7eb2e8f9f7 18820
<> 144:ef7eb2e8f9f7 18821 #define PDMA_DSCT_CTL_TXCNT_Pos (16) /*!< PDMA DSCT_CTL: TXCNT Position */
<> 144:ef7eb2e8f9f7 18822 #define PDMA_DSCT_CTL_TXCNT_Msk (0x3ffful << PDMA_DSCT_CTL_TXCNT_Pos) /*!< PDMA DSCT_CTL: TXCNT Mask */
<> 144:ef7eb2e8f9f7 18823
<> 144:ef7eb2e8f9f7 18824 #define PDMA_DSCT_ENDSA_ENDSA_Pos (0) /*!< PDMA DSCT_ENDSA: ENDSA Position */
<> 144:ef7eb2e8f9f7 18825 #define PDMA_DSCT_ENDSA_ENDSA_Msk (0xfffffffful << PDMA_DSCT_ENDSA_ENDSA_Pos) /*!< PDMA DSCT_ENDSA: ENDSA Mask */
<> 144:ef7eb2e8f9f7 18826
<> 144:ef7eb2e8f9f7 18827 #define PDMA_DSCT_ENDDA_ENDDA_Pos (0) /*!< PDMA DSCT_ENDDA: ENDDA Position */
<> 144:ef7eb2e8f9f7 18828 #define PDMA_DSCT_ENDDA_ENDDA_Msk (0xfffffffful << PDMA_DSCT_ENDDA_ENDDA_Pos) /*!< PDMA DSCT_ENDDA: ENDDA Mask */
<> 144:ef7eb2e8f9f7 18829
<> 144:ef7eb2e8f9f7 18830 #define PDMA_DSCT_NEXT_NEXT_Pos (2) /*!< PDMA DSCT_NEXT: NEXT Position */
<> 144:ef7eb2e8f9f7 18831 #define PDMA_DSCT_NEXT_NEXT_Msk (0x3ffful << PDMA_DSCT_NEXT_NEXT_Pos) /*!< PDMA DSCT_NEXT: NEXT Mask */
<> 144:ef7eb2e8f9f7 18832
<> 144:ef7eb2e8f9f7 18833 #define PDMA_CHCTL_CHEN_Pos (0) /*!< PDMA CHCTL: CHEN Position */
<> 144:ef7eb2e8f9f7 18834 #define PDMA_CHCTL_CHEN_Msk (0xfffful << PDMA_CHCTL_CHEN_Pos) /*!< PDMA CHCTL: CHEN Mask */
<> 144:ef7eb2e8f9f7 18835
<> 144:ef7eb2e8f9f7 18836 #define PDMA_STOP_STOP_Pos (0) /*!< PDMA STOP: STOP Position */
<> 144:ef7eb2e8f9f7 18837 #define PDMA_STOP_STOP_Msk (0xfffful << PDMA_STOP_STOP_Pos) /*!< PDMA STOP: STOP Mask */
<> 144:ef7eb2e8f9f7 18838
<> 144:ef7eb2e8f9f7 18839 #define PDMA_SWREQ_SWREQ_Pos (0) /*!< PDMA SWREQ: SWREQ Position */
<> 144:ef7eb2e8f9f7 18840 #define PDMA_SWREQ_SWREQ_Msk (0xffful << PDMA_SWREQ_SWREQ_Pos) /*!< PDMA SWREQ: SWREQ Mask */
<> 144:ef7eb2e8f9f7 18841
<> 144:ef7eb2e8f9f7 18842 #define PDMA_TRGSTS_REQSTS_Pos (0) /*!< PDMA TRGSTS: REQSTS Position */
<> 144:ef7eb2e8f9f7 18843 #define PDMA_TRGSTS_REQSTS_Msk (0xfffful << PDMA_TRGSTS_REQSTS_Pos) /*!< PDMA TRGSTS: REQSTS Mask */
<> 144:ef7eb2e8f9f7 18844
<> 144:ef7eb2e8f9f7 18845 #define PDMA_PRISET_FPRISET_Pos (0) /*!< PDMA PRISET: FPRISET Position */
<> 144:ef7eb2e8f9f7 18846 #define PDMA_PRISET_FPRISET_Msk (0xfffful << PDMA_PRISET_FPRISET_Pos) /*!< PDMA PRISET: FPRISET Mask */
<> 144:ef7eb2e8f9f7 18847
<> 144:ef7eb2e8f9f7 18848 #define PDMA_PRICLR_FPRICLR_Pos (0) /*!< PDMA PRICLR: FPRICLR Position */
<> 144:ef7eb2e8f9f7 18849 #define PDMA_PRICLR_FPRICLR_Msk (0xfffful << PDMA_PRICLR_FPRICLR_Pos) /*!< PDMA PRICLR: FPRICLR Mask */
<> 144:ef7eb2e8f9f7 18850
<> 144:ef7eb2e8f9f7 18851 #define PDMA_INTEN_INTEN_Pos (0) /*!< PDMA INTEN: INTEN Position */
<> 144:ef7eb2e8f9f7 18852 #define PDMA_INTEN_INTEN_Msk (0xfffful << PDMA_INTEN_INTEN_Pos) /*!< PDMA INTEN: INTEN Mask */
<> 144:ef7eb2e8f9f7 18853
<> 144:ef7eb2e8f9f7 18854 #define PDMA_INTSTS_ABTIF_Pos (0) /*!< PDMA INTSTS: ABTIF Position */
<> 144:ef7eb2e8f9f7 18855 #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) /*!< PDMA INTSTS: ABTIF Mask */
<> 144:ef7eb2e8f9f7 18856
<> 144:ef7eb2e8f9f7 18857 #define PDMA_INTSTS_TDIF_Pos (1) /*!< PDMA INTSTS: TDIF Position */
<> 144:ef7eb2e8f9f7 18858 #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) /*!< PDMA INTSTS: TDIF Mask */
<> 144:ef7eb2e8f9f7 18859
<> 144:ef7eb2e8f9f7 18860 #define PDMA_INTSTS_TEIF_Pos (2) /*!< PDMA INTSTS: TEIF Position */
<> 144:ef7eb2e8f9f7 18861 #define PDMA_INTSTS_TEIF_Msk (0x1ul << PDMA_INTSTS_TEIF_Pos) /*!< PDMA INTSTS: TEIF Mask */
<> 144:ef7eb2e8f9f7 18862
<> 144:ef7eb2e8f9f7 18863 #define PDMA_INTSTS_REQTOFX_Pos (8) /*!< PDMA INTSTS: REQTOFX Position */
<> 144:ef7eb2e8f9f7 18864 #define PDMA_INTSTS_REQTOFX_Msk (0xfffful << PDMA_INTSTS_REQTOFX_Pos) /*!< PDMA INTSTS: REQTOFX Mask */
<> 144:ef7eb2e8f9f7 18865
<> 144:ef7eb2e8f9f7 18866 #define PDMA_ABTSTS_ABTIF_Pos (0) /*!< PDMA ABTSTS: ABTIF Position */
<> 144:ef7eb2e8f9f7 18867 #define PDMA_ABTSTS_ABTIF_Msk (0xfffful << PDMA_ABTSTS_ABTIF_Pos) /*!< PDMA ABTSTS: ABTIF Mask */
<> 144:ef7eb2e8f9f7 18868
<> 144:ef7eb2e8f9f7 18869 #define PDMA_TDSTS_TDIF_Pos (0) /*!< PDMA TDSTS: TDIF Position */
<> 144:ef7eb2e8f9f7 18870 #define PDMA_TDSTS_TDIF_Msk (0xfffful << PDMA_TDSTS_TDIF_Pos) /*!< PDMA TDSTS: TDIF Mask */
<> 144:ef7eb2e8f9f7 18871
<> 144:ef7eb2e8f9f7 18872 #define PDMA_SCATSTS_TEMPTYF_Pos (0) /*!< PDMA SCATSTS: TEMPTYF Position */
<> 144:ef7eb2e8f9f7 18873 #define PDMA_SCATSTS_TEMPTYF_Msk (0xfffful << PDMA_SCATSTS_TEMPTYF_Pos) /*!< PDMA SCATSTS: TEMPTYF Mask */
<> 144:ef7eb2e8f9f7 18874
<> 144:ef7eb2e8f9f7 18875 #define PDMA_TACTSTS_TXACTF_Pos (0) /*!< PDMA TACTSTS: TXACTF Position */
<> 144:ef7eb2e8f9f7 18876 #define PDMA_TACTSTS_TXACTF_Msk (0xfffful << PDMA_TACTSTS_TXACTF_Pos) /*!< PDMA TACTSTS: TXACTF Mask */
<> 144:ef7eb2e8f9f7 18877
<> 144:ef7eb2e8f9f7 18878 #define PDMA_SCATBA_SCATBA_Pos (16) /*!< PDMA SCATBA: SCATBA Position */
<> 144:ef7eb2e8f9f7 18879 #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) /*!< PDMA SCATBA: SCATBA Mask */
<> 144:ef7eb2e8f9f7 18880
<> 144:ef7eb2e8f9f7 18881 #define PDMA_TOC0_1_TOC0_Pos (0) /*!< PDMA TOC0_1: TOC0 Position */
<> 144:ef7eb2e8f9f7 18882 #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) /*!< PDMA TOC0_1: TOC0 Mask */
<> 144:ef7eb2e8f9f7 18883
<> 144:ef7eb2e8f9f7 18884 #define PDMA_TOC0_1_TOC1_Pos (16) /*!< PDMA TOC0_1: TOC1 Position */
<> 144:ef7eb2e8f9f7 18885 #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) /*!< PDMA TOC0_1: TOC1 Mask */
<> 144:ef7eb2e8f9f7 18886
<> 144:ef7eb2e8f9f7 18887 #define PDMA_TOC2_3_TOC2_Pos (0) /*!< PDMA TOC2_3: TOC2 Position */
<> 144:ef7eb2e8f9f7 18888 #define PDMA_TOC2_3_TOC2_Msk (0xfffful << PDMA_TOC2_3_TOC2_Pos) /*!< PDMA TOC2_3: TOC2 Mask */
<> 144:ef7eb2e8f9f7 18889
<> 144:ef7eb2e8f9f7 18890 #define PDMA_TOC2_3_TOC3_Pos (16) /*!< PDMA TOC2_3: TOC3 Position */
<> 144:ef7eb2e8f9f7 18891 #define PDMA_TOC2_3_TOC3_Msk (0xfffful << PDMA_TOC2_3_TOC3_Pos) /*!< PDMA TOC2_3: TOC3 Mask */
<> 144:ef7eb2e8f9f7 18892
<> 144:ef7eb2e8f9f7 18893 #define PDMA_TOC4_5_TOC4_Pos (0) /*!< PDMA TOC4_5: TOC4 Position */
<> 144:ef7eb2e8f9f7 18894 #define PDMA_TOC4_5_TOC4_Msk (0xfffful << PDMA_TOC4_5_TOC4_Pos) /*!< PDMA TOC4_5: TOC4 Mask */
<> 144:ef7eb2e8f9f7 18895
<> 144:ef7eb2e8f9f7 18896 #define PDMA_TOC4_5_TOC5_Pos (16) /*!< PDMA TOC4_5: TOC5 Position */
<> 144:ef7eb2e8f9f7 18897 #define PDMA_TOC4_5_TOC5_Msk (0xfffful << PDMA_TOC4_5_TOC5_Pos) /*!< PDMA TOC4_5: TOC5 Mask */
<> 144:ef7eb2e8f9f7 18898
<> 144:ef7eb2e8f9f7 18899 #define PDMA_TOC6_7_TOC6_Pos (0) /*!< PDMA TOC6_7: TOC6 Position */
<> 144:ef7eb2e8f9f7 18900 #define PDMA_TOC6_7_TOC6_Msk (0xfffful << PDMA_TOC6_7_TOC6_Pos) /*!< PDMA TOC6_7: TOC6 Mask */
<> 144:ef7eb2e8f9f7 18901
<> 144:ef7eb2e8f9f7 18902 #define PDMA_TOC6_7_TOC7_Pos (16) /*!< PDMA TOC6_7: TOC7 Position */
<> 144:ef7eb2e8f9f7 18903 #define PDMA_TOC6_7_TOC7_Msk (0xfffful << PDMA_TOC6_7_TOC7_Pos) /*!< PDMA TOC6_7: TOC7 Mask */
<> 144:ef7eb2e8f9f7 18904
<> 144:ef7eb2e8f9f7 18905 #define PDMA_TOC8_9_TOC8_Pos (0) /*!< PDMA TOC8_9: TOC8 Position */
<> 144:ef7eb2e8f9f7 18906 #define PDMA_TOC8_9_TOC8_Msk (0xfffful << PDMA_TOC8_9_TOC8_Pos) /*!< PDMA TOC8_9: TOC8 Mask */
<> 144:ef7eb2e8f9f7 18907
<> 144:ef7eb2e8f9f7 18908 #define PDMA_TOC8_9_TOC9_Pos (16) /*!< PDMA TOC8_9: TOC9 Position */
<> 144:ef7eb2e8f9f7 18909 #define PDMA_TOC8_9_TOC9_Msk (0xfffful << PDMA_TOC8_9_TOC9_Pos) /*!< PDMA TOC8_9: TOC9 Mask */
<> 144:ef7eb2e8f9f7 18910
<> 144:ef7eb2e8f9f7 18911 #define PDMA_TOC10_11_TOC10_Pos (0) /*!< PDMA TOC10_11: TOC10 Position */
<> 144:ef7eb2e8f9f7 18912 #define PDMA_TOC10_11_TOC10_Msk (0xfffful << PDMA_TOC10_11_TOC10_Pos) /*!< PDMA TOC10_11: TOC10 Mask */
<> 144:ef7eb2e8f9f7 18913
<> 144:ef7eb2e8f9f7 18914 #define PDMA_TOC10_11_TOC11_Pos (16) /*!< PDMA TOC10_11: TOC11 Position */
<> 144:ef7eb2e8f9f7 18915 #define PDMA_TOC10_11_TOC11_Msk (0xfffful << PDMA_TOC10_11_TOC11_Pos) /*!< PDMA TOC10_11: TOC11 Mask */
<> 144:ef7eb2e8f9f7 18916
<> 144:ef7eb2e8f9f7 18917 #define PDMA_TOC12_13_TOC12_Pos (0) /*!< PDMA TOC12_13: TOC12 Position */
<> 144:ef7eb2e8f9f7 18918 #define PDMA_TOC12_13_TOC12_Msk (0xfffful << PDMA_TOC12_13_TOC12_Pos) /*!< PDMA TOC12_13: TOC12 Mask */
<> 144:ef7eb2e8f9f7 18919
<> 144:ef7eb2e8f9f7 18920 #define PDMA_TOC12_13_TOC13_Pos (16) /*!< PDMA TOC12_13: TOC13 Position */
<> 144:ef7eb2e8f9f7 18921 #define PDMA_TOC12_13_TOC13_Msk (0xfffful << PDMA_TOC12_13_TOC13_Pos) /*!< PDMA TOC12_13: TOC13 Mask */
<> 144:ef7eb2e8f9f7 18922
<> 144:ef7eb2e8f9f7 18923 #define PDMA_TOC14_15_TOC14_Pos (0) /*!< PDMA TOC14_15: TOC14 Position */
<> 144:ef7eb2e8f9f7 18924 #define PDMA_TOC14_15_TOC14_Msk (0xfffful << PDMA_TOC14_15_TOC14_Pos) /*!< PDMA TOC14_15: TOC14 Mask */
<> 144:ef7eb2e8f9f7 18925
<> 144:ef7eb2e8f9f7 18926 #define PDMA_TOC14_15_TOC15_Pos (16) /*!< PDMA TOC14_15: TOC15 Position */
<> 144:ef7eb2e8f9f7 18927 #define PDMA_TOC14_15_TOC15_Msk (0xfffful << PDMA_TOC14_15_TOC15_Pos) /*!< PDMA TOC14_15: TOC15 Mask */
<> 144:ef7eb2e8f9f7 18928
<> 144:ef7eb2e8f9f7 18929 #define PDMA_REQSEL0_3_REQSRC0_Pos (0) /*!< PDMA REQSEL0_3: REQSRC0 Position */
<> 144:ef7eb2e8f9f7 18930 #define PDMA_REQSEL0_3_REQSRC0_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC0_Pos) /*!< PDMA REQSEL0_3: REQSRC0 Mask */
<> 144:ef7eb2e8f9f7 18931
<> 144:ef7eb2e8f9f7 18932 #define PDMA_REQSEL0_3_REQSRC1_Pos (8) /*!< PDMA REQSEL0_3: REQSRC1 Position */
<> 144:ef7eb2e8f9f7 18933 #define PDMA_REQSEL0_3_REQSRC1_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC1_Pos) /*!< PDMA REQSEL0_3: REQSRC1 Mask */
<> 144:ef7eb2e8f9f7 18934
<> 144:ef7eb2e8f9f7 18935 #define PDMA_REQSEL0_3_REQSRC2_Pos (16) /*!< PDMA REQSEL0_3: REQSRC2 Position */
<> 144:ef7eb2e8f9f7 18936 #define PDMA_REQSEL0_3_REQSRC2_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC2_Pos) /*!< PDMA REQSEL0_3: REQSRC2 Mask */
<> 144:ef7eb2e8f9f7 18937
<> 144:ef7eb2e8f9f7 18938 #define PDMA_REQSEL0_3_REQSRC3_Pos (24) /*!< PDMA REQSEL0_3: REQSRC3 Position */
<> 144:ef7eb2e8f9f7 18939 #define PDMA_REQSEL0_3_REQSRC3_Msk (0x1ful << PDMA_REQSEL0_3_REQSRC3_Pos) /*!< PDMA REQSEL0_3: REQSRC3 Mask */
<> 144:ef7eb2e8f9f7 18940
<> 144:ef7eb2e8f9f7 18941 #define PDMA_REQSEL4_7_REQSRC4_Pos (0) /*!< PDMA REQSEL4_7: REQSRC4 Position */
<> 144:ef7eb2e8f9f7 18942 #define PDMA_REQSEL4_7_REQSRC4_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC4_Pos) /*!< PDMA REQSEL4_7: REQSRC4 Mask */
<> 144:ef7eb2e8f9f7 18943
<> 144:ef7eb2e8f9f7 18944 #define PDMA_REQSEL4_7_REQSRC5_Pos (8) /*!< PDMA REQSEL4_7: REQSRC5 Position */
<> 144:ef7eb2e8f9f7 18945 #define PDMA_REQSEL4_7_REQSRC5_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC5_Pos) /*!< PDMA REQSEL4_7: REQSRC5 Mask */
<> 144:ef7eb2e8f9f7 18946
<> 144:ef7eb2e8f9f7 18947 #define PDMA_REQSEL4_7_REQSRC6_Pos (16) /*!< PDMA REQSEL4_7: REQSRC6 Position */
<> 144:ef7eb2e8f9f7 18948 #define PDMA_REQSEL4_7_REQSRC6_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC6_Pos) /*!< PDMA REQSEL4_7: REQSRC6 Mask */
<> 144:ef7eb2e8f9f7 18949
<> 144:ef7eb2e8f9f7 18950 #define PDMA_REQSEL4_7_REQSRC7_Pos (24) /*!< PDMA REQSEL4_7: REQSRC7 Position */
<> 144:ef7eb2e8f9f7 18951 #define PDMA_REQSEL4_7_REQSRC7_Msk (0x1ful << PDMA_REQSEL4_7_REQSRC7_Pos) /*!< PDMA REQSEL4_7: REQSRC7 Mask */
<> 144:ef7eb2e8f9f7 18952
<> 144:ef7eb2e8f9f7 18953 #define PDMA_REQSEL8_11_REQSRC8_Pos (0) /*!< PDMA REQSEL8_11: REQSRC8 Position */
<> 144:ef7eb2e8f9f7 18954 #define PDMA_REQSEL8_11_REQSRC8_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC8_Pos) /*!< PDMA REQSEL8_11: REQSRC8 Mask */
<> 144:ef7eb2e8f9f7 18955
<> 144:ef7eb2e8f9f7 18956 #define PDMA_REQSEL8_11_REQSRC9_Pos (8) /*!< PDMA REQSEL8_11: REQSRC9 Position */
<> 144:ef7eb2e8f9f7 18957 #define PDMA_REQSEL8_11_REQSRC9_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC9_Pos) /*!< PDMA REQSEL8_11: REQSRC9 Mask */
<> 144:ef7eb2e8f9f7 18958
<> 144:ef7eb2e8f9f7 18959 #define PDMA_REQSEL8_11_REQSRC10_Pos (16) /*!< PDMA REQSEL8_11: REQSRC10 Position */
<> 144:ef7eb2e8f9f7 18960 #define PDMA_REQSEL8_11_REQSRC10_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC10_Pos) /*!< PDMA REQSEL8_11: REQSRC10 Mask */
<> 144:ef7eb2e8f9f7 18961
<> 144:ef7eb2e8f9f7 18962 #define PDMA_REQSEL8_11_REQSRC11_Pos (24) /*!< PDMA REQSEL8_11: REQSRC11 Position */
<> 144:ef7eb2e8f9f7 18963 #define PDMA_REQSEL8_11_REQSRC11_Msk (0x1ful << PDMA_REQSEL8_11_REQSRC11_Pos) /*!< PDMA REQSEL8_11: REQSRC11 Mask */
<> 144:ef7eb2e8f9f7 18964
<> 144:ef7eb2e8f9f7 18965 #define PDMA_REQSEL12_15_REQSRC12_Pos (0) /*!< PDMA REQSEL12_15: REQSRC12 Position */
<> 144:ef7eb2e8f9f7 18966 #define PDMA_REQSEL12_15_REQSRC12_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC12_Pos) /*!< PDMA REQSEL12_15: REQSRC12 Mask */
<> 144:ef7eb2e8f9f7 18967
<> 144:ef7eb2e8f9f7 18968 #define PDMA_REQSEL12_15_REQSRC13_Pos (8) /*!< PDMA REQSEL12_15: REQSRC13 Position */
<> 144:ef7eb2e8f9f7 18969 #define PDMA_REQSEL12_15_REQSRC13_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC13_Pos) /*!< PDMA REQSEL12_15: REQSRC13 Mask */
<> 144:ef7eb2e8f9f7 18970
<> 144:ef7eb2e8f9f7 18971 #define PDMA_REQSEL12_15_REQSRC14_Pos (16) /*!< PDMA REQSEL12_15: REQSRC14 Position */
<> 144:ef7eb2e8f9f7 18972 #define PDMA_REQSEL12_15_REQSRC14_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC14_Pos) /*!< PDMA REQSEL12_15: REQSRC14 Mask */
<> 144:ef7eb2e8f9f7 18973
<> 144:ef7eb2e8f9f7 18974 #define PDMA_REQSEL12_15_REQSRC15_Pos (24) /*!< PDMA REQSEL12_15: REQSRC15 Position */
<> 144:ef7eb2e8f9f7 18975 #define PDMA_REQSEL12_15_REQSRC15_Msk (0x1ful << PDMA_REQSEL12_15_REQSRC15_Pos) /*!< PDMA REQSEL12_15: REQSRC15 Mask */
<> 144:ef7eb2e8f9f7 18976
<> 144:ef7eb2e8f9f7 18977 /**@}*/ /* PDMA_CONST */
<> 144:ef7eb2e8f9f7 18978 /**@}*/ /* end of PDMA register group */
<> 144:ef7eb2e8f9f7 18979
<> 144:ef7eb2e8f9f7 18980
<> 144:ef7eb2e8f9f7 18981 /*---------------------- PS/2 Device Controller -------------------------*/
<> 144:ef7eb2e8f9f7 18982 /**
<> 144:ef7eb2e8f9f7 18983 @addtogroup PS2 PS/2 Device Controller(PS2)
<> 144:ef7eb2e8f9f7 18984 Memory Mapped Structure for PS2 Controller
<> 144:ef7eb2e8f9f7 18985 @{ */
<> 144:ef7eb2e8f9f7 18986
<> 144:ef7eb2e8f9f7 18987 typedef struct {
<> 144:ef7eb2e8f9f7 18988
<> 144:ef7eb2e8f9f7 18989
<> 144:ef7eb2e8f9f7 18990 /**
<> 144:ef7eb2e8f9f7 18991 * CTL
<> 144:ef7eb2e8f9f7 18992 * ===================================================================================================
<> 144:ef7eb2e8f9f7 18993 * Offset: 0x00 PS/2 Control Register
<> 144:ef7eb2e8f9f7 18994 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 18995 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 18996 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 18997 * |[0] |PS2EN |PS/2 Device Enable Control
<> 144:ef7eb2e8f9f7 18998 * | | |Enable PS/2 device controller.
<> 144:ef7eb2e8f9f7 18999 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 19000 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 19001 * |[1] |TXIEN |Transmit Interrupt Enable Control
<> 144:ef7eb2e8f9f7 19002 * | | |0 = Data transmit complete interrupt Disabled.
<> 144:ef7eb2e8f9f7 19003 * | | |1 = Data transmit complete interrupt Enabled.
<> 144:ef7eb2e8f9f7 19004 * |[2] |RXIEN |Receive Interrupt Enable Control
<> 144:ef7eb2e8f9f7 19005 * | | |0 = Data receive complete interrupt Disabled.
<> 144:ef7eb2e8f9f7 19006 * | | |1 = Data receive complete interrupt Enabled.
<> 144:ef7eb2e8f9f7 19007 * |[3:6] |TXFDEPTH |Transmit Data FIFO Depth
<> 144:ef7eb2e8f9f7 19008 * | | |There is 16-byte buffer for data transmit.
<> 144:ef7eb2e8f9f7 19009 * | | |Software can define the FIFO depth from 1 to 16 bytes depending on the application.
<> 144:ef7eb2e8f9f7 19010 * | | |0 = 1 byte.
<> 144:ef7eb2e8f9f7 19011 * | | |1 = 2 bytes.
<> 144:ef7eb2e8f9f7 19012 * | | |...
<> 144:ef7eb2e8f9f7 19013 * | | |14 = 15 bytes.
<> 144:ef7eb2e8f9f7 19014 * | | |15 = 16 bytes.
<> 144:ef7eb2e8f9f7 19015 * |[7] |ACK |Acknowledge Enable Control
<> 144:ef7eb2e8f9f7 19016 * | | |0 = Always sends acknowledge to host at 12th clock for host to device communication.
<> 144:ef7eb2e8f9f7 19017 * | | |1 = If parity error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock.
<> 144:ef7eb2e8f9f7 19018 * |[8] |CLRFIFO |Clear TX FIFO
<> 144:ef7eb2e8f9f7 19019 * | | |Write 1 to this bit to terminate device to host transmission.
<> 144:ef7eb2e8f9f7 19020 * | | |The TXEMPTY(PS2_STATUS[7]) bit will be set to 1 and pointer BYTEIDEX(PS2_STATUS[11:8]) is reset to 0 regardless there is residue data in buffer or not.
<> 144:ef7eb2e8f9f7 19021 * | | |The buffer content is not been cleared.
<> 144:ef7eb2e8f9f7 19022 * | | |0 = Not active.
<> 144:ef7eb2e8f9f7 19023 * | | |1 = Clear FIFO.
<> 144:ef7eb2e8f9f7 19024 * |[9] |OVERRIDE |Software Override PS/2 CLK/DATA Pin State
<> 144:ef7eb2e8f9f7 19025 * | | |0 = CLKSTAT and DATSTAT pins are controlled by internal state machine.
<> 144:ef7eb2e8f9f7 19026 * | | |1 = CLKSTAT and DATSTAT pins are controlled by software.
<> 144:ef7eb2e8f9f7 19027 * |[10] |FPS2CLK |Force CLKSTAT Line
<> 144:ef7eb2e8f9f7 19028 * | | |It forces CLKSTAT line high or low regardless of the internal state of the device controller if OVERRIDE is set to high.
<> 144:ef7eb2e8f9f7 19029 * | | |0 = Force CLKSTAT line low.
<> 144:ef7eb2e8f9f7 19030 * | | |1 = Force CLKSTAT line high.
<> 144:ef7eb2e8f9f7 19031 * |[11] |FPS2DAT |Force DATSTAT Line
<> 144:ef7eb2e8f9f7 19032 * | | |It forces DATSTAT high or low regardless of the internal state of the device controller if OVERRIDE is set to high.
<> 144:ef7eb2e8f9f7 19033 * | | |0 = Force DATSTAT low.
<> 144:ef7eb2e8f9f7 19034 * | | |1 = Force DATSTAT high.
<> 144:ef7eb2e8f9f7 19035 */
<> 144:ef7eb2e8f9f7 19036 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 19037
<> 144:ef7eb2e8f9f7 19038 /**
<> 144:ef7eb2e8f9f7 19039 * TXDAT0
<> 144:ef7eb2e8f9f7 19040 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19041 * Offset: 0x04 PS/2 Transmit DATA Register 0
<> 144:ef7eb2e8f9f7 19042 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19043 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19044 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19045 * |[0:31] |DAT |Transmit Data
<> 144:ef7eb2e8f9f7 19046 * | | |Write data to this register starts device to host communication if bus is in IDLE state.
<> 144:ef7eb2e8f9f7 19047 * | | |Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
<> 144:ef7eb2e8f9f7 19048 */
<> 144:ef7eb2e8f9f7 19049 __IO uint32_t TXDAT0;
<> 144:ef7eb2e8f9f7 19050
<> 144:ef7eb2e8f9f7 19051 /**
<> 144:ef7eb2e8f9f7 19052 * TXDAT1
<> 144:ef7eb2e8f9f7 19053 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19054 * Offset: 0x08 PS/2 Transmit DATA Register 1
<> 144:ef7eb2e8f9f7 19055 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19056 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19057 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19058 * |[0:31] |DAT |Transmit Data
<> 144:ef7eb2e8f9f7 19059 * | | |Write data to this register starts device to host communication if bus is in IDLE state.
<> 144:ef7eb2e8f9f7 19060 * | | |Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
<> 144:ef7eb2e8f9f7 19061 */
<> 144:ef7eb2e8f9f7 19062 __IO uint32_t TXDAT1;
<> 144:ef7eb2e8f9f7 19063
<> 144:ef7eb2e8f9f7 19064 /**
<> 144:ef7eb2e8f9f7 19065 * TXDAT2
<> 144:ef7eb2e8f9f7 19066 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19067 * Offset: 0x0C PS/2 Transmit DATA Register 2
<> 144:ef7eb2e8f9f7 19068 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19069 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19070 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19071 * |[0:31] |DAT |Transmit Data
<> 144:ef7eb2e8f9f7 19072 * | | |Write data to this register starts device to host communication if bus is in IDLE state.
<> 144:ef7eb2e8f9f7 19073 * | | |Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
<> 144:ef7eb2e8f9f7 19074 */
<> 144:ef7eb2e8f9f7 19075 __IO uint32_t TXDAT2;
<> 144:ef7eb2e8f9f7 19076
<> 144:ef7eb2e8f9f7 19077 /**
<> 144:ef7eb2e8f9f7 19078 * TXDAT3
<> 144:ef7eb2e8f9f7 19079 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19080 * Offset: 0x10 PS/2 Transmit DATA Register 3
<> 144:ef7eb2e8f9f7 19081 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19082 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19083 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19084 * |[0:31] |DAT |Transmit Data
<> 144:ef7eb2e8f9f7 19085 * | | |Write data to this register starts device to host communication if bus is in IDLE state.
<> 144:ef7eb2e8f9f7 19086 * | | |Software must enable PS2EN(PS2_CTL[0]) before writing data to TX buffer.
<> 144:ef7eb2e8f9f7 19087 */
<> 144:ef7eb2e8f9f7 19088 __IO uint32_t TXDAT3;
<> 144:ef7eb2e8f9f7 19089
<> 144:ef7eb2e8f9f7 19090 /**
<> 144:ef7eb2e8f9f7 19091 * RXDAT
<> 144:ef7eb2e8f9f7 19092 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19093 * Offset: 0x14 PS/2 Receive DATA Register
<> 144:ef7eb2e8f9f7 19094 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19095 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19096 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19097 * |[0:7] |DAT |Received Data
<> 144:ef7eb2e8f9f7 19098 * | | |For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2_RXDAT register.
<> 144:ef7eb2e8f9f7 19099 * | | |CPU must read this register before next byte reception complete; otherwise, the data will be overwritten and RXOV(PS2_STATUS[6]) bit will be set to 1.
<> 144:ef7eb2e8f9f7 19100 */
<> 144:ef7eb2e8f9f7 19101 __I uint32_t RXDAT;
<> 144:ef7eb2e8f9f7 19102
<> 144:ef7eb2e8f9f7 19103 /**
<> 144:ef7eb2e8f9f7 19104 * STATUS
<> 144:ef7eb2e8f9f7 19105 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19106 * Offset: 0x18 PS/2 Status Register
<> 144:ef7eb2e8f9f7 19107 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19108 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19109 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19110 * |[0] |CLKSTAT |CLK Pin State
<> 144:ef7eb2e8f9f7 19111 * | | |This bit reflects the status of the CLKSTAT line after synchronizing.
<> 144:ef7eb2e8f9f7 19112 * |[1] |DATSTAT |DATA Pin State
<> 144:ef7eb2e8f9f7 19113 * | | |This bit reflects the status of the DATSTAT line after synchronizing and sampling.
<> 144:ef7eb2e8f9f7 19114 * |[2] |FRAMEERR |Frame Error
<> 144:ef7eb2e8f9f7 19115 * | | |For host to device communication, if STOP bit (logic 1) is not received it is a frame error.
<> 144:ef7eb2e8f9f7 19116 * | | |If frame error occurs, DATA line may keep at low state after 12th clock.
<> 144:ef7eb2e8f9f7 19117 * | | |At this moment, software overrides CLKSTAT to send clock till DATSTAT release to high state.
<> 144:ef7eb2e8f9f7 19118 * | | |After that, device sends a "Resend" command to host.
<> 144:ef7eb2e8f9f7 19119 * | | |0 = No frame error.
<> 144:ef7eb2e8f9f7 19120 * | | |1 = Frame error occurred .
<> 144:ef7eb2e8f9f7 19121 * | | |Note: Write 1 to clear this bit.
<> 144:ef7eb2e8f9f7 19122 * |[3] |RXPARITY |Received Parity
<> 144:ef7eb2e8f9f7 19123 * | | |This bit reflects the parity bit for the last received data byte (odd parity).
<> 144:ef7eb2e8f9f7 19124 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 19125 * |[4] |RXBUSY |Receive Busy
<> 144:ef7eb2e8f9f7 19126 * | | |This bit indicates that the PS/2 device is currently receiving data.
<> 144:ef7eb2e8f9f7 19127 * | | |0 = Idle.
<> 144:ef7eb2e8f9f7 19128 * | | |1 = Currently receiving data.
<> 144:ef7eb2e8f9f7 19129 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 19130 * |[5] |TXBUSY |Transmit Busy
<> 144:ef7eb2e8f9f7 19131 * | | |This bit indicates that the PS/2 device is currently sending data.
<> 144:ef7eb2e8f9f7 19132 * | | |0 = Idle.
<> 144:ef7eb2e8f9f7 19133 * | | |1 = Currently sending data.
<> 144:ef7eb2e8f9f7 19134 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 19135 * |[6] |RXOV |RX Buffer Overwrite
<> 144:ef7eb2e8f9f7 19136 * | | |0 = No overwrite.
<> 144:ef7eb2e8f9f7 19137 * | | |1 = Data in PS2_RXDAT register is overwritten by new received data.
<> 144:ef7eb2e8f9f7 19138 * | | |Note: Write 1 to clear this bit.
<> 144:ef7eb2e8f9f7 19139 * |[7] |TXEMPTY |TX FIFO Empty
<> 144:ef7eb2e8f9f7 19140 * | | |When software writes any data to PS2_TXDAT0-3 the TXEMPTY bit is cleared to 0 immediately if PS2EN is enabled.
<> 144:ef7eb2e8f9f7 19141 * | | |When transmitted data byte number is equal to FIFODEPTH then TXEMPTY bit is set to 1.
<> 144:ef7eb2e8f9f7 19142 * | | |0 = There is data to be transmitted.
<> 144:ef7eb2e8f9f7 19143 * | | |1 = FIFO is empty.
<> 144:ef7eb2e8f9f7 19144 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 19145 * |[8:11] |BYTEIDX |Byte Index
<> 144:ef7eb2e8f9f7 19146 * | | |It indicates which data byte in transmit data shift register.
<> 144:ef7eb2e8f9f7 19147 * | | |When all data in FIFO is transmitted and it will be cleared to 0.
<> 144:ef7eb2e8f9f7 19148 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 19149 * | | |BYTEIDX DATA Transmit
<> 144:ef7eb2e8f9f7 19150 * | | |0000 TXDATA0[7:0]
<> 144:ef7eb2e8f9f7 19151 * | | |0001 TXDATA0[15:8]
<> 144:ef7eb2e8f9f7 19152 * | | |0010 TXDATA0[23:16]
<> 144:ef7eb2e8f9f7 19153 * | | |0011 TXDATA0[31:24]
<> 144:ef7eb2e8f9f7 19154 * | | |0100 TXDATA1[7:0]
<> 144:ef7eb2e8f9f7 19155 * | | |0101 TXDATA1[15:8]
<> 144:ef7eb2e8f9f7 19156 * | | |0110 TXDATA1[23:16]
<> 144:ef7eb2e8f9f7 19157 * | | |0111 TXDATA1[31:24]
<> 144:ef7eb2e8f9f7 19158 * | | |1000 TXDATA2[7:0]
<> 144:ef7eb2e8f9f7 19159 * | | |1001 TXDATA2[15:8]
<> 144:ef7eb2e8f9f7 19160 * | | |1010 TXDATA2[23:16]
<> 144:ef7eb2e8f9f7 19161 * | | |1011 TXDATA2[31:24]
<> 144:ef7eb2e8f9f7 19162 * | | |1100 TXDATA3[7:0]
<> 144:ef7eb2e8f9f7 19163 * | | |1101 TXDATA3[15:8]
<> 144:ef7eb2e8f9f7 19164 * | | |1110 TXDATA3[23:16]
<> 144:ef7eb2e8f9f7 19165 * | | |1111 TXDATA3[31:24]
<> 144:ef7eb2e8f9f7 19166 */
<> 144:ef7eb2e8f9f7 19167 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 19168
<> 144:ef7eb2e8f9f7 19169 /**
<> 144:ef7eb2e8f9f7 19170 * INTSTS
<> 144:ef7eb2e8f9f7 19171 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19172 * Offset: 0x1C PS/2 Interrupt Status Register
<> 144:ef7eb2e8f9f7 19173 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19174 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19175 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19176 * |[0] |RXIF |Receive Interrupt
<> 144:ef7eb2e8f9f7 19177 * | | |This bit is set to 1 when acknowledge bit is sent for Host to device communication.
<> 144:ef7eb2e8f9f7 19178 * | | |Interrupt occurs if RXIEN(PS2_CTL[2]) bit is set to 1.
<> 144:ef7eb2e8f9f7 19179 * | | |0 = No interrupt.
<> 144:ef7eb2e8f9f7 19180 * | | |1 = Receive interrupt occurred.
<> 144:ef7eb2e8f9f7 19181 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 19182 * |[1] |TXIF |Transmit Interrupt
<> 144:ef7eb2e8f9f7 19183 * | | |This bit is set to 1 after STOP bit is transmitted. Interrupt occurs if TXIEN(PS2_CTL[1]) bit is set
<> 144:ef7eb2e8f9f7 19184 * | | |to 1.
<> 144:ef7eb2e8f9f7 19185 * | | |0 = No interrupt.
<> 144:ef7eb2e8f9f7 19186 * | | |1 = Transmit interrupt occurred.
<> 144:ef7eb2e8f9f7 19187 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 19188 */
<> 144:ef7eb2e8f9f7 19189 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 19190
<> 144:ef7eb2e8f9f7 19191 } PS2_T;
<> 144:ef7eb2e8f9f7 19192
<> 144:ef7eb2e8f9f7 19193 /**
<> 144:ef7eb2e8f9f7 19194 @addtogroup PS2_CONST PS2 Bit Field Definition
<> 144:ef7eb2e8f9f7 19195 Constant Definitions for PS2 Controller
<> 144:ef7eb2e8f9f7 19196 @{ */
<> 144:ef7eb2e8f9f7 19197
<> 144:ef7eb2e8f9f7 19198 #define PS2_CTL_PS2EN_Pos (0) /*!< PS2 CTL: PS2EN Position */
<> 144:ef7eb2e8f9f7 19199 #define PS2_CTL_PS2EN_Msk (0x1ul << PS2_CTL_PS2EN_Pos) /*!< PS2 CTL: PS2EN Mask */
<> 144:ef7eb2e8f9f7 19200
<> 144:ef7eb2e8f9f7 19201 #define PS2_CTL_TXIEN_Pos (1) /*!< PS2 CTL: TXIEN Position */
<> 144:ef7eb2e8f9f7 19202 #define PS2_CTL_TXIEN_Msk (0x1ul << PS2_CTL_TXIEN_Pos) /*!< PS2 CTL: TXIEN Mask */
<> 144:ef7eb2e8f9f7 19203
<> 144:ef7eb2e8f9f7 19204 #define PS2_CTL_RXIEN_Pos (2) /*!< PS2 CTL: RXIEN Position */
<> 144:ef7eb2e8f9f7 19205 #define PS2_CTL_RXIEN_Msk (0x1ul << PS2_CTL_RXIEN_Pos) /*!< PS2 CTL: RXIEN Mask */
<> 144:ef7eb2e8f9f7 19206
<> 144:ef7eb2e8f9f7 19207 #define PS2_CTL_TXFDEPTH_Pos (3) /*!< PS2 CTL: TXFDEPTH Position */
<> 144:ef7eb2e8f9f7 19208 #define PS2_CTL_TXFDEPTH_Msk (0xful << PS2_CTL_TXFDEPTH_Pos) /*!< PS2 CTL: TXFDEPTH Mask */
<> 144:ef7eb2e8f9f7 19209
<> 144:ef7eb2e8f9f7 19210 #define PS2_CTL_ACK_Pos (7) /*!< PS2 CTL: ACK Position */
<> 144:ef7eb2e8f9f7 19211 #define PS2_CTL_ACK_Msk (0x1ul << PS2_CTL_ACK_Pos) /*!< PS2 CTL: ACK Mask */
<> 144:ef7eb2e8f9f7 19212
<> 144:ef7eb2e8f9f7 19213 #define PS2_CTL_CLRFIFO_Pos (8) /*!< PS2 CTL: CLRFIFO Position */
<> 144:ef7eb2e8f9f7 19214 #define PS2_CTL_CLRFIFO_Msk (0x1ul << PS2_CTL_CLRFIFO_Pos) /*!< PS2 CTL: CLRFIFO Mask */
<> 144:ef7eb2e8f9f7 19215
<> 144:ef7eb2e8f9f7 19216 #define PS2_CTL_OVERRIDE_Pos (9) /*!< PS2 CTL: OVERRIDE Position */
<> 144:ef7eb2e8f9f7 19217 #define PS2_CTL_OVERRIDE_Msk (0x1ul << PS2_CTL_OVERRIDE_Pos) /*!< PS2 CTL: OVERRIDE Mask */
<> 144:ef7eb2e8f9f7 19218
<> 144:ef7eb2e8f9f7 19219 #define PS2_CTL_FPS2CLK_Pos (10) /*!< PS2 CTL: FPS2CLK Position */
<> 144:ef7eb2e8f9f7 19220 #define PS2_CTL_FPS2CLK_Msk (0x1ul << PS2_CTL_FPS2CLK_Pos) /*!< PS2 CTL: FPS2CLK Mask */
<> 144:ef7eb2e8f9f7 19221
<> 144:ef7eb2e8f9f7 19222 #define PS2_CTL_FPS2DAT_Pos (11) /*!< PS2 CTL: FPS2DAT Position */
<> 144:ef7eb2e8f9f7 19223 #define PS2_CTL_FPS2DAT_Msk (0x1ul << PS2_CTL_FPS2DAT_Pos) /*!< PS2 CTL: FPS2DAT Mask */
<> 144:ef7eb2e8f9f7 19224
<> 144:ef7eb2e8f9f7 19225 #define PS2_TXDAT0_DAT_Pos (0) /*!< PS2 TXDAT0: DAT Position */
<> 144:ef7eb2e8f9f7 19226 #define PS2_TXDAT0_DAT_Msk (0xfffffffful << PS2_TXDAT0_DAT_Pos) /*!< PS2 TXDAT0: DAT Mask */
<> 144:ef7eb2e8f9f7 19227
<> 144:ef7eb2e8f9f7 19228 #define PS2_TXDAT1_DAT_Pos (0) /*!< PS2 TXDAT1: DAT Position */
<> 144:ef7eb2e8f9f7 19229 #define PS2_TXDAT1_DAT_Msk (0xfffffffful << PS2_TXDAT1_DAT_Pos) /*!< PS2 TXDAT1: DAT Mask */
<> 144:ef7eb2e8f9f7 19230
<> 144:ef7eb2e8f9f7 19231 #define PS2_TXDAT2_DAT_Pos (0) /*!< PS2 TXDAT2: DAT Position */
<> 144:ef7eb2e8f9f7 19232 #define PS2_TXDAT2_DAT_Msk (0xfffffffful << PS2_TXDAT2_DAT_Pos) /*!< PS2 TXDAT2: DAT Mask */
<> 144:ef7eb2e8f9f7 19233
<> 144:ef7eb2e8f9f7 19234 #define PS2_TXDAT3_DAT_Pos (0) /*!< PS2 TXDAT3: DAT Position */
<> 144:ef7eb2e8f9f7 19235 #define PS2_TXDAT3_DAT_Msk (0xfffffffful << PS2_TXDAT3_DAT_Pos) /*!< PS2 TXDAT3: DAT Mask */
<> 144:ef7eb2e8f9f7 19236
<> 144:ef7eb2e8f9f7 19237 #define PS2_RXDAT_DAT_Pos (0) /*!< PS2 RXDAT: DAT Position */
<> 144:ef7eb2e8f9f7 19238 #define PS2_RXDAT_DAT_Msk (0xfful << PS2_RXDAT_DAT_Pos) /*!< PS2 RXDAT: DAT Mask */
<> 144:ef7eb2e8f9f7 19239
<> 144:ef7eb2e8f9f7 19240 #define PS2_STATUS_CLKSTAT_Pos (0) /*!< PS2 STATUS: CLKSTAT Position */
<> 144:ef7eb2e8f9f7 19241 #define PS2_STATUS_CLKSTAT_Msk (0x1ul << PS2_STATUS_CLKSTAT_Pos) /*!< PS2 STATUS: CLKSTAT Mask */
<> 144:ef7eb2e8f9f7 19242
<> 144:ef7eb2e8f9f7 19243 #define PS2_STATUS_DATSTAT_Pos (1) /*!< PS2 STATUS: DATSTAT Position */
<> 144:ef7eb2e8f9f7 19244 #define PS2_STATUS_DATSTAT_Msk (0x1ul << PS2_STATUS_DATSTAT_Pos) /*!< PS2 STATUS: DATSTAT Mask */
<> 144:ef7eb2e8f9f7 19245
<> 144:ef7eb2e8f9f7 19246 #define PS2_STATUS_FRAMEERR_Pos (2) /*!< PS2 STATUS: FRAMEERR Position */
<> 144:ef7eb2e8f9f7 19247 #define PS2_STATUS_FRAMEERR_Msk (0x1ul << PS2_STATUS_FRAMEERR_Pos) /*!< PS2 STATUS: FRAMEERR Mask */
<> 144:ef7eb2e8f9f7 19248
<> 144:ef7eb2e8f9f7 19249 #define PS2_STATUS_RXPARITY_Pos (3) /*!< PS2 STATUS: RXPARITY Position */
<> 144:ef7eb2e8f9f7 19250 #define PS2_STATUS_RXPARITY_Msk (0x1ul << PS2_STATUS_RXPARITY_Pos) /*!< PS2 STATUS: RXPARITY Mask */
<> 144:ef7eb2e8f9f7 19251
<> 144:ef7eb2e8f9f7 19252 #define PS2_STATUS_RXBUSY_Pos (4) /*!< PS2 STATUS: RXBUSY Position */
<> 144:ef7eb2e8f9f7 19253 #define PS2_STATUS_RXBUSY_Msk (0x1ul << PS2_STATUS_RXBUSY_Pos) /*!< PS2 STATUS: RXBUSY Mask */
<> 144:ef7eb2e8f9f7 19254
<> 144:ef7eb2e8f9f7 19255 #define PS2_STATUS_TXBUSY_Pos (5) /*!< PS2 STATUS: TXBUSY Position */
<> 144:ef7eb2e8f9f7 19256 #define PS2_STATUS_TXBUSY_Msk (0x1ul << PS2_STATUS_TXBUSY_Pos) /*!< PS2 STATUS: TXBUSY Mask */
<> 144:ef7eb2e8f9f7 19257
<> 144:ef7eb2e8f9f7 19258 #define PS2_STATUS_RXOV_Pos (6) /*!< PS2 STATUS: RXOV Position */
<> 144:ef7eb2e8f9f7 19259 #define PS2_STATUS_RXOV_Msk (0x1ul << PS2_STATUS_RXOV_Pos) /*!< PS2 STATUS: RXOV Mask */
<> 144:ef7eb2e8f9f7 19260
<> 144:ef7eb2e8f9f7 19261 #define PS2_STATUS_TXEMPTY_Pos (7) /*!< PS2 STATUS: TXEMPTY Position */
<> 144:ef7eb2e8f9f7 19262 #define PS2_STATUS_TXEMPTY_Msk (0x1ul << PS2_STATUS_TXEMPTY_Pos) /*!< PS2 STATUS: TXEMPTY Mask */
<> 144:ef7eb2e8f9f7 19263
<> 144:ef7eb2e8f9f7 19264 #define PS2_STATUS_BYTEIDX_Pos (8) /*!< PS2 STATUS: BYTEIDX Position */
<> 144:ef7eb2e8f9f7 19265 #define PS2_STATUS_BYTEIDX_Msk (0xful << PS2_STATUS_BYTEIDX_Pos) /*!< PS2 STATUS: BYTEIDX Mask */
<> 144:ef7eb2e8f9f7 19266
<> 144:ef7eb2e8f9f7 19267 #define PS2_INTSTS_RXIF_Pos (0) /*!< PS2 INTSTS: RXIF Position */
<> 144:ef7eb2e8f9f7 19268 #define PS2_INTSTS_RXIF_Msk (0x1ul << PS2_INTSTS_RXIF_Pos) /*!< PS2 INTSTS: RXIF Mask */
<> 144:ef7eb2e8f9f7 19269
<> 144:ef7eb2e8f9f7 19270 #define PS2_INTSTS_TXIF_Pos (1) /*!< PS2 INTSTS: TXIF Position */
<> 144:ef7eb2e8f9f7 19271 #define PS2_INTSTS_TXIF_Msk (0x1ul << PS2_INTSTS_TXIF_Pos) /*!< PS2 INTSTS: TXIF Mask */
<> 144:ef7eb2e8f9f7 19272
<> 144:ef7eb2e8f9f7 19273 /**@}*/ /* PS2_CONST */
<> 144:ef7eb2e8f9f7 19274 /**@}*/ /* end of PS2 register group */
<> 144:ef7eb2e8f9f7 19275
<> 144:ef7eb2e8f9f7 19276
<> 144:ef7eb2e8f9f7 19277 /*---------------------- Pulse Width Modulation Controller -------------------------*/
<> 144:ef7eb2e8f9f7 19278 /**
<> 144:ef7eb2e8f9f7 19279 @addtogroup PWM Pulse Width Modulation Controller(PWM)
<> 144:ef7eb2e8f9f7 19280 Memory Mapped Structure for PWM Controller
<> 144:ef7eb2e8f9f7 19281 @{ */
<> 144:ef7eb2e8f9f7 19282
<> 144:ef7eb2e8f9f7 19283 typedef struct {
<> 144:ef7eb2e8f9f7 19284
<> 144:ef7eb2e8f9f7 19285
<> 144:ef7eb2e8f9f7 19286 /**
<> 144:ef7eb2e8f9f7 19287 * CLKPSC
<> 144:ef7eb2e8f9f7 19288 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19289 * Offset: 0x00 PWM Clock Prescale Register
<> 144:ef7eb2e8f9f7 19290 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19291 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19292 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19293 * |[0:7] |CLKPSC01 |PWM Counter Base-Clock Prescale For PWM Pair Of Channel 0 And Channel 1
<> 144:ef7eb2e8f9f7 19294 * | | |The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
<> 144:ef7eb2e8f9f7 19295 * | | |Each PWM pair share one PWM counter base-clock prescaler.
<> 144:ef7eb2e8f9f7 19296 * | | |The base-clock of PWM counter is divided by (CLKPSC01 + 1).
<> 144:ef7eb2e8f9f7 19297 * | | |If the value of CLKPSC01 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
<> 144:ef7eb2e8f9f7 19298 * |[8:15] |CLKPSC23 |PWM Counter Base-Clock Prescale For PWM Pair Of Channel 2 And Channel 3
<> 144:ef7eb2e8f9f7 19299 * | | |The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
<> 144:ef7eb2e8f9f7 19300 * | | |Each PWM pair share one PWM counter base-clock prescaler.
<> 144:ef7eb2e8f9f7 19301 * | | |The base-clock of PWM counter is divided by (CLKPSC23 + 1).
<> 144:ef7eb2e8f9f7 19302 * | | |If the value of CLKPSC23 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
<> 144:ef7eb2e8f9f7 19303 * |[16:23] |CLKPSC45 |PWM Counter Base-Clock Prescale For PWM Pair Of Channel 4 And Channel 5
<> 144:ef7eb2e8f9f7 19304 * | | |The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
<> 144:ef7eb2e8f9f7 19305 * | | |Each PWM pair share one PWM counter base-clock prescaler.
<> 144:ef7eb2e8f9f7 19306 * | | |The base-clock of PWM counter is divided by (CLKPSC45 + 1).
<> 144:ef7eb2e8f9f7 19307 * | | |If the value of CLKPSC45 is zero, the base-clock prescaler will stop output clock and corresponding PWM counter will also stop.
<> 144:ef7eb2e8f9f7 19308 */
<> 144:ef7eb2e8f9f7 19309 __IO uint32_t CLKPSC;
<> 144:ef7eb2e8f9f7 19310
<> 144:ef7eb2e8f9f7 19311 /**
<> 144:ef7eb2e8f9f7 19312 * CLKDIV
<> 144:ef7eb2e8f9f7 19313 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19314 * Offset: 0x04 PWM Clock Divide Register
<> 144:ef7eb2e8f9f7 19315 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19316 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19317 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19318 * |[0:2] |CLKDIV0 |PWM Counter Base-Clock Divide For PWMx_CH0
<> 144:ef7eb2e8f9f7 19319 * | | |(Table is the same as CLKDIV5)
<> 144:ef7eb2e8f9f7 19320 * |[4:6] |CLKDIV1 |PWM Counter Base-Clock Divide For PWMx_CH1
<> 144:ef7eb2e8f9f7 19321 * | | |(Table is the same as CLKDIV5)
<> 144:ef7eb2e8f9f7 19322 * |[8:10] |CLKDIV2 |PWM Counter Base-Clock Divide For PWMx_CH2
<> 144:ef7eb2e8f9f7 19323 * | | |(Table is the same as CLKDIV5)
<> 144:ef7eb2e8f9f7 19324 * |[12:14] |CLKDIV3 |PWM Counter Base-Clock Divide For PWMx_CH3
<> 144:ef7eb2e8f9f7 19325 * | | |(Table is the same as CLKDIV5)
<> 144:ef7eb2e8f9f7 19326 * |[16:18] |CLKDIV4 |PWM Counter Base-Clock Divide For PWMx_CH4
<> 144:ef7eb2e8f9f7 19327 * | | |(Table is the same as CLKDIV5)
<> 144:ef7eb2e8f9f7 19328 * |[20:22] |CLKDIV5 |PWM Counter Base-Clock Divide For PWMx_CH5
<> 144:ef7eb2e8f9f7 19329 * | | |The base-clock of PWM counter is decided by clock pre-scalar and clock divider.
<> 144:ef7eb2e8f9f7 19330 * | | |Each PWM counter has independent clock divider control register and the divided value is listed in the table below:.
<> 144:ef7eb2e8f9f7 19331 * | | |000 = 2.
<> 144:ef7eb2e8f9f7 19332 * | | |001 = 4.
<> 144:ef7eb2e8f9f7 19333 * | | |010 = 8.
<> 144:ef7eb2e8f9f7 19334 * | | |011 = 16.
<> 144:ef7eb2e8f9f7 19335 * | | |100 = 1.
<> 144:ef7eb2e8f9f7 19336 */
<> 144:ef7eb2e8f9f7 19337 __IO uint32_t CLKDIV;
<> 144:ef7eb2e8f9f7 19338
<> 144:ef7eb2e8f9f7 19339 /**
<> 144:ef7eb2e8f9f7 19340 * CTL
<> 144:ef7eb2e8f9f7 19341 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19342 * Offset: 0x08 PWM Control Register
<> 144:ef7eb2e8f9f7 19343 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19344 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19345 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19346 * |[0:5] |CMPINV |PWM Comparator Output Inverter Enable Control
<> 144:ef7eb2e8f9f7 19347 * | | |When CMPINV is set to high, the PWM comparator output signals will be inversed,
<> 144:ef7eb2e8f9f7 19348 * | | |0 = Comparator output inverter Disabled.
<> 144:ef7eb2e8f9f7 19349 * | | |1 = Comparator output inverter Enabled.
<> 144:ef7eb2e8f9f7 19350 * | | |Note: Each bit control corresponding PWM channel
<> 144:ef7eb2e8f9f7 19351 * |[6] |OUTMODE |PWM Output Mode
<> 144:ef7eb2e8f9f7 19352 * | | |The register controls the output mode of PWM
<> 144:ef7eb2e8f9f7 19353 * | | |0 = PWM output at independent mode.
<> 144:ef7eb2e8f9f7 19354 * | | |1 = PWM output at complementary mode.
<> 144:ef7eb2e8f9f7 19355 * |[7] |GROUPEN |Group Mode Enable Control
<> 144:ef7eb2e8f9f7 19356 * | | |0 = The signals timing of each PWM channel are independent.
<> 144:ef7eb2e8f9f7 19357 * | | |1 = Unify the signals timing of PWM0, PWM2 and PWM4 in the same phase which is controlled by PWM0 and unify the signals timing of PWM1, PWM3 and PWM5 in the same phase which is controlled by PWM1.
<> 144:ef7eb2e8f9f7 19358 * |[8:13] |PINV |PWM Output Polar Inverse Enable Control
<> 144:ef7eb2e8f9f7 19359 * | | |The register controls polarity state of PWM output
<> 144:ef7eb2e8f9f7 19360 * | | |0 = PWM output polar inverse Disabled.
<> 144:ef7eb2e8f9f7 19361 * | | |1 = PWM output polar inverse Enabled.
<> 144:ef7eb2e8f9f7 19362 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19363 * |[15] |SYNCEN |Synchronous Mode Enable Control
<> 144:ef7eb2e8f9f7 19364 * | | |0 = The signals timing of each PWM channel are independent.
<> 144:ef7eb2e8f9f7 19365 * | | |1 = Unify the signals timing of PWM0 and PWM1 in the same phase which is controlled by PWM0 and so as another two PWM pair.
<> 144:ef7eb2e8f9f7 19366 * | | |Note: If Group and Synchronous mode are enabled simultaneously, the Synchronous mode will be inactive.
<> 144:ef7eb2e8f9f7 19367 * |[16:21] |CNTMODE |PWM Counter Operation Mode
<> 144:ef7eb2e8f9f7 19368 * | | |0 = PWM counter working as One-shot mode.
<> 144:ef7eb2e8f9f7 19369 * | | |1 = PWM counter working as Auto-reload mode.
<> 144:ef7eb2e8f9f7 19370 * | | |Note: Each bit control corresponding PWM channel
<> 144:ef7eb2e8f9f7 19371 * | | |Note: If there is a transition at this bit, it will cause PWM_PERIODn and PWM_CMPDATn be cleared.
<> 144:ef7eb2e8f9f7 19372 * |[24:29] |CNTTYPE |PWM Counter Operation Aligned Type
<> 144:ef7eb2e8f9f7 19373 * | | |0 = PWM counter operating as Edge-aligned type.
<> 144:ef7eb2e8f9f7 19374 * | | |1 = PWM counter operating as Center-aligned type.
<> 144:ef7eb2e8f9f7 19375 * | | |Note: Each bit control corresponding PWM channel
<> 144:ef7eb2e8f9f7 19376 * |[31] |DBGTRIOFF |ICE Debug Mode Acknowledge Disable Control (Write Protect)
<> 144:ef7eb2e8f9f7 19377 * | | |0 = ICE debug mode acknowledgement effects PWM output.
<> 144:ef7eb2e8f9f7 19378 * | | |PWM pin will be forced as tri-state while ICE debug mode acknowledged.
<> 144:ef7eb2e8f9f7 19379 * | | |1 = ICE debug mode acknowledgement disabled.
<> 144:ef7eb2e8f9f7 19380 * | | |PWM pin will keep output no matter ICE debug mode acknowledged or not.
<> 144:ef7eb2e8f9f7 19381 */
<> 144:ef7eb2e8f9f7 19382 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 19383
<> 144:ef7eb2e8f9f7 19384 /**
<> 144:ef7eb2e8f9f7 19385 * CNTEN
<> 144:ef7eb2e8f9f7 19386 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19387 * Offset: 0x0C PWM Counter Enable Control Register
<> 144:ef7eb2e8f9f7 19388 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19389 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19390 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19391 * |[0:5] |CNTEN |PWM Counter Enable Control
<> 144:ef7eb2e8f9f7 19392 * | | |0 = PWM Counter Stop Running.
<> 144:ef7eb2e8f9f7 19393 * | | |1 = PWM Counter Start Running.
<> 144:ef7eb2e8f9f7 19394 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19395 */
<> 144:ef7eb2e8f9f7 19396 __IO uint32_t CNTEN;
<> 144:ef7eb2e8f9f7 19397
<> 144:ef7eb2e8f9f7 19398 /**
<> 144:ef7eb2e8f9f7 19399 * PERIOD
<> 144:ef7eb2e8f9f7 19400 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19401 * Offset: 0x10 ~ 0x24 PWM Counter Register
<> 144:ef7eb2e8f9f7 19402 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19403 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19404 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19405 * |[0:15] |PERIOD |PWM Period Register
<> 144:ef7eb2e8f9f7 19406 * | | |PERIOD determines the PWM period.
<> 144:ef7eb2e8f9f7 19407 * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(PERIOD+1)]; where xy, could be 01, 23 or 45, depends on selected PWM channel.
<> 144:ef7eb2e8f9f7 19408 * | | |For Edge-aligned mode:
<> 144:ef7eb2e8f9f7 19409 * | | |l Duty ratio = (CMP+1)/(PERIOD+1).
<> 144:ef7eb2e8f9f7 19410 * | | |l CMP >= PERIOD: PWM output is always high.
<> 144:ef7eb2e8f9f7 19411 * | | |l CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
<> 144:ef7eb2e8f9f7 19412 * | | |l CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
<> 144:ef7eb2e8f9f7 19413 * | | |For Center-aligned mode:
<> 144:ef7eb2e8f9f7 19414 * | | |l Duty ratio = [(2 x CMP) + 1]/[2 x (PERIOD+1)].
<> 144:ef7eb2e8f9f7 19415 * | | |l CMP > PERIOD: PWM output is always high.
<> 144:ef7eb2e8f9f7 19416 * | | |l CMP <= PERIOD: PWM low width = 2 x (PERIOD-CMP) + 1 unit; PWM high width = (2 x CMP) + 1 unit.
<> 144:ef7eb2e8f9f7 19417 * | | |l CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit.
<> 144:ef7eb2e8f9f7 19418 * | | |(Unit = one PWM clock cycle).
<> 144:ef7eb2e8f9f7 19419 * | | |Note1: Any write to PERIOD will take effect in next PWM cycle.
<> 144:ef7eb2e8f9f7 19420 * | | |Note2: When PWM operating at center-aligned type, PERIOD value should be set between 0x0000 to 0xFFFE.
<> 144:ef7eb2e8f9f7 19421 * | | |If PERIOD equal to 0xFFFF, the PWM will work unpredictable.
<> 144:ef7eb2e8f9f7 19422 * | | |Note3: When PERIOD value is set to 0, PWM output is always high.
<> 144:ef7eb2e8f9f7 19423 */
<> 144:ef7eb2e8f9f7 19424 __IO uint32_t PERIOD[6];
<> 144:ef7eb2e8f9f7 19425
<> 144:ef7eb2e8f9f7 19426 /**
<> 144:ef7eb2e8f9f7 19427 * CMPDAT
<> 144:ef7eb2e8f9f7 19428 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19429 * Offset: 0x28 ~0x3C PWM Comparator Register
<> 144:ef7eb2e8f9f7 19430 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19431 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19432 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19433 * |[0:15] |CMP |PWM Duty Register
<> 144:ef7eb2e8f9f7 19434 * | | |CMP determines the PWM duty.
<> 144:ef7eb2e8f9f7 19435 * | | |PWM frequency = PWMxy_CLK/[(prescale+1)*(clock divider)*(PERIOD+1)]; where xy, could be 01, 23 or, 45, depends on selected PWM channel.
<> 144:ef7eb2e8f9f7 19436 * | | |For Edge-aligned mode:
<> 144:ef7eb2e8f9f7 19437 * | | |l Duty ratio = (CMP+1)/(PERIOD+1).
<> 144:ef7eb2e8f9f7 19438 * | | |l CMP >= PERIOD: PWM output is always high.
<> 144:ef7eb2e8f9f7 19439 * | | |l CMP < PERIOD: PWM low width = (PERIOD-CMP) unit; PWM high width = (CMP+1) unit.
<> 144:ef7eb2e8f9f7 19440 * | | |l CMP = 0: PWM low width = (PERIOD) unit; PWM high width = 1 unit.
<> 144:ef7eb2e8f9f7 19441 * | | |For Center-aligned mode:
<> 144:ef7eb2e8f9f7 19442 * | | |l Duty ratio = [(2 x CMP) + 1]/[2 x (PERIOD+1)].
<> 144:ef7eb2e8f9f7 19443 * | | |l CMP > PERIOD: PWM output is always high.
<> 144:ef7eb2e8f9f7 19444 * | | |l CMP <= PERIOD: PWM low width = 2 x (PERIOD-CMP) + 1 unit; PWM high width = (2 x CMP) + 1 unit.
<> 144:ef7eb2e8f9f7 19445 * | | |l CMP = 0: PWM low width = 2 x PERIOD + 1 unit; PWM high width = 1 unit.
<> 144:ef7eb2e8f9f7 19446 * | | |(Unit = one PWM clock cycle).
<> 144:ef7eb2e8f9f7 19447 * | | |Note: Any write to CMP will take effect in next PWM cycle.
<> 144:ef7eb2e8f9f7 19448 */
<> 144:ef7eb2e8f9f7 19449 __IO uint32_t CMPDAT[6];
<> 144:ef7eb2e8f9f7 19450
<> 144:ef7eb2e8f9f7 19451 /**
<> 144:ef7eb2e8f9f7 19452 * CNT
<> 144:ef7eb2e8f9f7 19453 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19454 * Offset: 0x40 ~ 0x54 PWM Data Register
<> 144:ef7eb2e8f9f7 19455 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19456 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19457 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19458 * |[0:15] |CNT |PWM Data Register
<> 144:ef7eb2e8f9f7 19459 * | | |User can monitor CNT to know the current value in 16-bit down counter.
<> 144:ef7eb2e8f9f7 19460 * | | |Note: It is recommended that read this register when PWM engine clock is source from system clock, otherwise a transition value of PWM counter may be read.
<> 144:ef7eb2e8f9f7 19461 */
<> 144:ef7eb2e8f9f7 19462 __I uint32_t CNT[6];
<> 144:ef7eb2e8f9f7 19463
<> 144:ef7eb2e8f9f7 19464 /**
<> 144:ef7eb2e8f9f7 19465 * MSKEN
<> 144:ef7eb2e8f9f7 19466 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19467 * Offset: 0x58 PWM Mask Control Register
<> 144:ef7eb2e8f9f7 19468 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19469 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19470 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19471 * |[0:5] |MSKEN |PWM Mask Enable Control
<> 144:ef7eb2e8f9f7 19472 * | | |The PWM output signal will be masked when this bit is enabled.
<> 144:ef7eb2e8f9f7 19473 * | | |The corresponding PWMn channel will be output with MSKDAT data.
<> 144:ef7eb2e8f9f7 19474 * | | |0 = PWM output signal is non-masked.
<> 144:ef7eb2e8f9f7 19475 * | | |1 = PWM output signal is masked and output with MSKDAT data.
<> 144:ef7eb2e8f9f7 19476 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19477 */
<> 144:ef7eb2e8f9f7 19478 __IO uint32_t MSKEN;
<> 144:ef7eb2e8f9f7 19479
<> 144:ef7eb2e8f9f7 19480 /**
<> 144:ef7eb2e8f9f7 19481 * MSK
<> 144:ef7eb2e8f9f7 19482 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19483 * Offset: 0x5C PWM Mask Data Register
<> 144:ef7eb2e8f9f7 19484 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19485 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19486 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19487 * |[0:5] |MSKDAT |PWM Mask Data Bit:
<> 144:ef7eb2e8f9f7 19488 * | | |This data bit control the state of PWMn output pin, if corresponding mask function is enabled.
<> 144:ef7eb2e8f9f7 19489 * | | |0 = Output logic low to PWMn.
<> 144:ef7eb2e8f9f7 19490 * | | |1 = Output logic high to PWMn.
<> 144:ef7eb2e8f9f7 19491 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19492 */
<> 144:ef7eb2e8f9f7 19493 __IO uint32_t MSK;
<> 144:ef7eb2e8f9f7 19494
<> 144:ef7eb2e8f9f7 19495 /**
<> 144:ef7eb2e8f9f7 19496 * DTCTL
<> 144:ef7eb2e8f9f7 19497 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19498 * Offset: 0x60 PWM Dead-zone Control Register
<> 144:ef7eb2e8f9f7 19499 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19500 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19501 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19502 * |[0:7] |DTCNT01 |Dead-Zone Interval For PWM Pair Of Channel 0 And Channel 1
<> 144:ef7eb2e8f9f7 19503 * | | |These 8-bit determine the Dead-zone length.
<> 144:ef7eb2e8f9f7 19504 * | | |The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
<> 144:ef7eb2e8f9f7 19505 * |[8:15] |DTCNT23 |Dead-Zone Interval For PWM Pair Of Channel 2 And Channel 3
<> 144:ef7eb2e8f9f7 19506 * | | |These 8-bit determine the Dead-zone length.
<> 144:ef7eb2e8f9f7 19507 * | | |The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
<> 144:ef7eb2e8f9f7 19508 * |[16:23] |DTCNT45 |Dead-Zone Interval For PWM Pair Of Channel 4 And Channel 5
<> 144:ef7eb2e8f9f7 19509 * | | |These 8-bit determine the Dead-zone length.
<> 144:ef7eb2e8f9f7 19510 * | | |The unit time of Dead-zone length is received from corresponding PWM_CLKDIV.
<> 144:ef7eb2e8f9f7 19511 * |[24:25] |DTDIV |Dead-Zone Generator Divider
<> 144:ef7eb2e8f9f7 19512 * | | |00 = Dead-zone clock equal to PWM base clock divide 1.
<> 144:ef7eb2e8f9f7 19513 * | | |01 = Dead-zone clock equal to PWM base clock divide 2.
<> 144:ef7eb2e8f9f7 19514 * | | |10 = Dead-zone clock equal to PWM base clock divide 4.
<> 144:ef7eb2e8f9f7 19515 * | | |11 = Dead-zone clock equal to PWM base clock divide 8.
<> 144:ef7eb2e8f9f7 19516 * |[28] |DTEN01 |Dead-Zone Enable Control For PWM Pair Of Channel 0 And Channel 1
<> 144:ef7eb2e8f9f7 19517 * | | |Dead-zone insertion is only active when this pair of complementary PWM is enabled.
<> 144:ef7eb2e8f9f7 19518 * | | |If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 144:ef7eb2e8f9f7 19519 * | | |0 = Dead-zone insertion Disabled.
<> 144:ef7eb2e8f9f7 19520 * | | |1 = Dead-zone insertion Enabled.
<> 144:ef7eb2e8f9f7 19521 * |[29] |DTEN23 |Dead-Zone Enable Control For PWM Pair Of Channel 2 And Channel 3
<> 144:ef7eb2e8f9f7 19522 * | | |Dead-zone insertion is only active when this pair of complementary PWM is enabled.
<> 144:ef7eb2e8f9f7 19523 * | | |If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 144:ef7eb2e8f9f7 19524 * | | |0 = Dead-zone insertion Disabled.
<> 144:ef7eb2e8f9f7 19525 * | | |1 = Dead-zone insertion Enabled.
<> 144:ef7eb2e8f9f7 19526 * |[30] |DTEN45 |Dead-Zone Enable Control For PWM Pair Of Channel 4 And Channel 5
<> 144:ef7eb2e8f9f7 19527 * | | |Dead-zone insertion is only active when this pair of complementary PWM is enabled.
<> 144:ef7eb2e8f9f7 19528 * | | |If Dead-zone insertion is inactive, the outputs of pin pair are complementary without any delay.
<> 144:ef7eb2e8f9f7 19529 * | | |0 = Dead-zone insertion Disabled.
<> 144:ef7eb2e8f9f7 19530 * | | |1 = Dead-zone insertion Enabled.
<> 144:ef7eb2e8f9f7 19531 */
<> 144:ef7eb2e8f9f7 19532 __IO uint32_t DTCTL;
<> 144:ef7eb2e8f9f7 19533
<> 144:ef7eb2e8f9f7 19534 /**
<> 144:ef7eb2e8f9f7 19535 * TRGADCTL
<> 144:ef7eb2e8f9f7 19536 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19537 * Offset: 0x64 PWM Trigger Control Register
<> 144:ef7eb2e8f9f7 19538 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19539 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19540 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19541 * |[0:5] |PTRGEN |PWM Period Point Trigger Enable Control
<> 144:ef7eb2e8f9f7 19542 * | | |0 = PWM period point trigger ADC function Disabled.
<> 144:ef7eb2e8f9f7 19543 * | | |1 = PWM period point trigger ADC function Enabled.
<> 144:ef7eb2e8f9f7 19544 * | | |PWM can trigger ADC to start conversion when PWM counter down count to zero if this bit is set to1.
<> 144:ef7eb2e8f9f7 19545 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19546 * |[8:13] |CTRGEN |PWM Center Point Trigger Enable Control
<> 144:ef7eb2e8f9f7 19547 * | | |0 = PWM center point trigger ADC function Disabled.
<> 144:ef7eb2e8f9f7 19548 * | | |1 = PWM center point trigger ADC function Enabled.
<> 144:ef7eb2e8f9f7 19549 * | | |PWM can trigger ADC to start conversion when PWM counter up count to (PERIODn+1) if this bit is set to1.
<> 144:ef7eb2e8f9f7 19550 * | | |Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
<> 144:ef7eb2e8f9f7 19551 * | | |Note2: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19552 * |[16:21] |FTRGEN |PWM Falling Edge Point Trigger Enable Control
<> 144:ef7eb2e8f9f7 19553 * | | |0 = PWM falling edge point trigger ADC function Disabled.
<> 144:ef7eb2e8f9f7 19554 * | | |1 = PWM falling edge point trigger ADC function Enabled.
<> 144:ef7eb2e8f9f7 19555 * | | |PWM can trigger ADC to start conversion when PWM output pin falling edge is detected if this bit is set to1.
<> 144:ef7eb2e8f9f7 19556 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19557 * |[24:29] |RTRGEN |PWM Rising Edge Point Trigger Enable Control
<> 144:ef7eb2e8f9f7 19558 * | | |0 = PWM rising edge point trigger ADC function Disabled.
<> 144:ef7eb2e8f9f7 19559 * | | |1 = PWM rising edge point trigger ADC function Enabled.
<> 144:ef7eb2e8f9f7 19560 * | | |PWM can trigger ADC to start conversion when PWM output pin rising edge is detected if this bit is set to1.
<> 144:ef7eb2e8f9f7 19561 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19562 */
<> 144:ef7eb2e8f9f7 19563 __IO uint32_t TRGADCTL;
<> 144:ef7eb2e8f9f7 19564
<> 144:ef7eb2e8f9f7 19565 /**
<> 144:ef7eb2e8f9f7 19566 * TRGADCSTS
<> 144:ef7eb2e8f9f7 19567 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19568 * Offset: 0x68 PWM Trigger ADC Status Register
<> 144:ef7eb2e8f9f7 19569 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19570 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19571 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19572 * |[0:5] |PTRGF |PWM Period Point Trigger Flag
<> 144:ef7eb2e8f9f7 19573 * | | |This bit is set to 1 by hardware when PWM counter down count to zero if corresponding PTRGEN bit is 1.
<> 144:ef7eb2e8f9f7 19574 * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
<> 144:ef7eb2e8f9f7 19575 * | | |Note1: Write 1 to clear this bit.
<> 144:ef7eb2e8f9f7 19576 * | | |Note2: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19577 * |[8:13] |CTRGF |PWM Center Point Trigger Flag
<> 144:ef7eb2e8f9f7 19578 * | | |This bit is set to 1 by hardware when PWM counter up counts to (PERIODn+1) if the corresponding CTRGEN bit is 1.
<> 144:ef7eb2e8f9f7 19579 * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
<> 144:ef7eb2e8f9f7 19580 * | | |Note1: Write 1 to clear this bit.
<> 144:ef7eb2e8f9f7 19581 * | | |Note2: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19582 * |[16:21] |FTRGF |PWM Falling Edge Point Trigger Indicator
<> 144:ef7eb2e8f9f7 19583 * | | |This bit is set to 1 by hardware when PWM output pin falling edge is detected if corresponding FETRGEN bit is 1.
<> 144:ef7eb2e8f9f7 19584 * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
<> 144:ef7eb2e8f9f7 19585 * | | |Note1: Write 1 to clear this bit.
<> 144:ef7eb2e8f9f7 19586 * | | |Note2: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19587 * |[24:29] |RTRGF |PWM Rising Edge Point Trigger Indicator
<> 144:ef7eb2e8f9f7 19588 * | | |This bit is set to 1 by hardware when PWM output pin rising edge is detected if corresponding RETRGEN bit is 1.
<> 144:ef7eb2e8f9f7 19589 * | | |After this bit is set to 1, ADC will start conversion if ADC triggered source is selected by PWM.
<> 144:ef7eb2e8f9f7 19590 * | | |Note1: Write 1 to clear this bit.
<> 144:ef7eb2e8f9f7 19591 * | | |Note2: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19592 */
<> 144:ef7eb2e8f9f7 19593 __IO uint32_t TRGADCSTS;
<> 144:ef7eb2e8f9f7 19594
<> 144:ef7eb2e8f9f7 19595 /**
<> 144:ef7eb2e8f9f7 19596 * BRKCTL
<> 144:ef7eb2e8f9f7 19597 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19598 * Offset: 0x6C PWM Brake Control Register
<> 144:ef7eb2e8f9f7 19599 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19600 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19601 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19602 * |[0] |BRKP0EN |Brake0 Function Enable Control
<> 144:ef7eb2e8f9f7 19603 * | | |0 = Brake0 detect function Disabled.
<> 144:ef7eb2e8f9f7 19604 * | | |1 = Brake0 detect function Enabled.
<> 144:ef7eb2e8f9f7 19605 * |[1] |BRK0NFDIS |PWM Brake 0 Noise Filter Disable Control
<> 144:ef7eb2e8f9f7 19606 * | | |0 = Noise filter of PWM Brake 0 Enabled.
<> 144:ef7eb2e8f9f7 19607 * | | |1 = Noise filter of PWM Brake 0 Disabled.
<> 144:ef7eb2e8f9f7 19608 * |[2] |BRK0INV |Inverse BKP0 State
<> 144:ef7eb2e8f9f7 19609 * | | |0 = The state of pin BKPx0 is passed to the negative edge detector.
<> 144:ef7eb2e8f9f7 19610 * | | |1 = The inversed state of pin BKPx0 is passed to the negative edge detector.
<> 144:ef7eb2e8f9f7 19611 * |[6:7] |BRK0NFSEL |Brake 0 (BKPx0 Pin) Edge Detector Filter Clock Selection
<> 144:ef7eb2e8f9f7 19612 * | | |00 = Filter clock = HCLK.
<> 144:ef7eb2e8f9f7 19613 * | | |01 = Filter clock = HCLK/2.
<> 144:ef7eb2e8f9f7 19614 * | | |10 = Filter clock = HCLK/4.
<> 144:ef7eb2e8f9f7 19615 * | | |11 = Filter clock = HCLK/16.
<> 144:ef7eb2e8f9f7 19616 * |[8] |BRKP1EN |Brake1 Function Enable Control
<> 144:ef7eb2e8f9f7 19617 * | | |0 = Brake1 function Disabled.
<> 144:ef7eb2e8f9f7 19618 * | | |1 = Brake1 function Enabled.
<> 144:ef7eb2e8f9f7 19619 * |[9] |BRK1NFDIS |PWM Brake 1 Noise Filter Disable Control
<> 144:ef7eb2e8f9f7 19620 * | | |0 = Noise filter of PWM Brake 1 Enabled.
<> 144:ef7eb2e8f9f7 19621 * | | |1 = Noise filter of PWM Brake 1 Disabled.
<> 144:ef7eb2e8f9f7 19622 * |[10] |BRK1INV |Inverse BKP1 State
<> 144:ef7eb2e8f9f7 19623 * | | |0 = The state of pin BKPx1 is passed to the negative edge detector.
<> 144:ef7eb2e8f9f7 19624 * | | |1 = The inversed state of pin BKPx1 is passed to the negative edge detector.
<> 144:ef7eb2e8f9f7 19625 * |[12:13] |BK1SEL |Brake Function 1 Source Selection
<> 144:ef7eb2e8f9f7 19626 * | | |00 = From external pin BKP1.
<> 144:ef7eb2e8f9f7 19627 * | | |01 = From analog comparator 0 output (CPO0).
<> 144:ef7eb2e8f9f7 19628 * | | |10 = From analog comparator 1 output (CPO1).
<> 144:ef7eb2e8f9f7 19629 * | | |11 = Reserved.
<> 144:ef7eb2e8f9f7 19630 * |[14:15] |BRK1NFSEL |Brake 1 (BKPx1 Pin) Edge Detector Filter Clock Selection
<> 144:ef7eb2e8f9f7 19631 * | | |00 = Filter clock = HCLK.
<> 144:ef7eb2e8f9f7 19632 * | | |01 = Filter clock = HCLK/2.
<> 144:ef7eb2e8f9f7 19633 * | | |10 = Filter clock = HCLK/4.
<> 144:ef7eb2e8f9f7 19634 * | | |11 = Filter clock = HCLK/16.
<> 144:ef7eb2e8f9f7 19635 * |[16] |CPO0BKEN |CPO0 Digital Output As Brake0 Source Enable Control
<> 144:ef7eb2e8f9f7 19636 * | | |0 = CPO0 as one brake source in Brake 0 Disabled.
<> 144:ef7eb2e8f9f7 19637 * | | |1 = CPO0 as one brake source in Brake 0 Enabled.
<> 144:ef7eb2e8f9f7 19638 * |[17] |CPO1BKEN |CPO1 Digital Output As Brake 0 Source Enable Control
<> 144:ef7eb2e8f9f7 19639 * | | |0 = CPO1 as one brake source in Brake 0 Disabled.
<> 144:ef7eb2e8f9f7 19640 * | | |1 = CPO1 as one brake source in Brake 0 Enabled.
<> 144:ef7eb2e8f9f7 19641 * |[18] |CPO2BKEN |CPO2 Digital Output As Brake 0 Source Enable Control
<> 144:ef7eb2e8f9f7 19642 * | | |0 = CPO2 as one brake source in Brake 0 Disabled.
<> 144:ef7eb2e8f9f7 19643 * | | |1 = CPO2 as one brake source in Brake 0 Enabled.
<> 144:ef7eb2e8f9f7 19644 * |[19] |LVDBKEN |Low-Level Detection Trigger PWM Brake Function 1 Enable Control
<> 144:ef7eb2e8f9f7 19645 * | | |0 = Brake Function 1 triggered by Low-level detection Disabled.
<> 144:ef7eb2e8f9f7 19646 * | | |1 = Brake Function 1 triggered by Low-level detection Enabled.
<> 144:ef7eb2e8f9f7 19647 * |[24:29] |BKOD |PWM Brake Output Data Register
<> 144:ef7eb2e8f9f7 19648 * | | |0 = PWM output low when fault brake conditions asserted.
<> 144:ef7eb2e8f9f7 19649 * | | |1 = PWM output high when fault brake conditions asserted.
<> 144:ef7eb2e8f9f7 19650 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19651 */
<> 144:ef7eb2e8f9f7 19652 __IO uint32_t BRKCTL;
<> 144:ef7eb2e8f9f7 19653
<> 144:ef7eb2e8f9f7 19654 /**
<> 144:ef7eb2e8f9f7 19655 * INTCTL
<> 144:ef7eb2e8f9f7 19656 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19657 * Offset: 0x70 PWM Interrupt Control Register
<> 144:ef7eb2e8f9f7 19658 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19659 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19660 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19661 * |[0:5] |PINTTYPE |PWM Period Interrupt Type Selection
<> 144:ef7eb2e8f9f7 19662 * | | |0 = PIF[n] will be set if PWM counter underflow.
<> 144:ef7eb2e8f9f7 19663 * | | |1 = PIF[n] will be set if PWM counter matches PWM_PERIODn register.
<> 144:ef7eb2e8f9f7 19664 * | | |Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
<> 144:ef7eb2e8f9f7 19665 * | | |Note2: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19666 * |[8:13] |DINTTYPE |PWM Duty Interrupt Type Selection
<> 144:ef7eb2e8f9f7 19667 * | | |0 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during down counting.
<> 144:ef7eb2e8f9f7 19668 * | | |1 = DIF[n] will be set if PWM counter matches PWM_CMPDATn register during up counting.
<> 144:ef7eb2e8f9f7 19669 * | | |Note1: This bit should keep at 0 when PWM counter operating in Edge-aligned type.
<> 144:ef7eb2e8f9f7 19670 * | | |Note2: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19671 */
<> 144:ef7eb2e8f9f7 19672 __IO uint32_t INTCTL;
<> 144:ef7eb2e8f9f7 19673
<> 144:ef7eb2e8f9f7 19674 /**
<> 144:ef7eb2e8f9f7 19675 * INTEN
<> 144:ef7eb2e8f9f7 19676 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19677 * Offset: 0x74 PWM Interrupt Enable Control Register
<> 144:ef7eb2e8f9f7 19678 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19679 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19680 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19681 * |[0:5] |PIEN |PWM Period Interrupt Enable Control
<> 144:ef7eb2e8f9f7 19682 * | | |0 = Period interrupt Disabled.
<> 144:ef7eb2e8f9f7 19683 * | | |1 = Period interrupt Enabled.
<> 144:ef7eb2e8f9f7 19684 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19685 * |[6] |BRKIEN |Brake0 And Brak1 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 19686 * | | |0 = Disabling flags BFK0 and BFK1 to trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 19687 * | | |1 = Enabling flags BRKIF0 and BRKIF1 can trigger PWM interrupt.
<> 144:ef7eb2e8f9f7 19688 * |[8:13] |DIEN |PWM Duty Interrupt Enable Control
<> 144:ef7eb2e8f9f7 19689 * | | |0 = Duty interrupt Disabled.
<> 144:ef7eb2e8f9f7 19690 * | | |1 = Duty interrupt Enabled.
<> 144:ef7eb2e8f9f7 19691 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19692 * |[16:21] |RLIEN |Rising Latch Interrupt Enable Control
<> 144:ef7eb2e8f9f7 19693 * | | |0 = Rising latch interrupt Disabled.
<> 144:ef7eb2e8f9f7 19694 * | | |1 = Rising latch interrupt Enabled.
<> 144:ef7eb2e8f9f7 19695 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19696 * |[24:29] |FLIEN |Falling Latch Interrupt Enable Control
<> 144:ef7eb2e8f9f7 19697 * | | |0 = Falling latch interrupt Disabled.
<> 144:ef7eb2e8f9f7 19698 * | | |1 = Falling latch interrupt Enabled.
<> 144:ef7eb2e8f9f7 19699 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19700 */
<> 144:ef7eb2e8f9f7 19701 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 19702
<> 144:ef7eb2e8f9f7 19703 /**
<> 144:ef7eb2e8f9f7 19704 * INTSTS
<> 144:ef7eb2e8f9f7 19705 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19706 * Offset: 0x78 PWM Interrupt Flag Register
<> 144:ef7eb2e8f9f7 19707 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19708 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19709 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19710 * |[0:5] |PIF |PWM Period Interrupt Flag
<> 144:ef7eb2e8f9f7 19711 * | | |This bit is set by hardware when PWM counter reaches the requirement condition of interrupt (depending on PINTTYPE (PWM_INTCTL[n]) ).
<> 144:ef7eb2e8f9f7 19712 * | | |Software can write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 19713 * |[6] |BRKIF0 |PWM Brake0 Flag
<> 144:ef7eb2e8f9f7 19714 * | | |0 = PWM Brake 0 is able to poll falling signal at BKP0 and has not recognized any one.
<> 144:ef7eb2e8f9f7 19715 * | | |1 = When PWM Brake 0 detects a falling signal at BKP0, this flag will be set to high.
<> 144:ef7eb2e8f9f7 19716 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 19717 * |[7] |BRKIF1 |PWM Brake1 Flag
<> 144:ef7eb2e8f9f7 19718 * | | |0 = PWM Brake 1 is able to poll falling signal at BKP1 and has not recognized any one.
<> 144:ef7eb2e8f9f7 19719 * | | |1 = When PWM Brake 1 detects a falling signal at pin BKP1, this flag will be set to high.
<> 144:ef7eb2e8f9f7 19720 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 19721 * |[8:13] |DIF |PWM Duty Interrupt Flag
<> 144:ef7eb2e8f9f7 19722 * | | |Flag is set by hardware when channel 0 PWM counter down count and reaches CMP0.
<> 144:ef7eb2e8f9f7 19723 * | | |Software can clear this bit by writing 1 to it.
<> 144:ef7eb2e8f9f7 19724 * | | |Note: If CMP is equal to PERIOD, this flag is not working in edge-aligned type selection.
<> 144:ef7eb2e8f9f7 19725 * |[14] |BRKLK0 |PWM Brake0 Locked
<> 144:ef7eb2e8f9f7 19726 * | | |0 = Brake 0 state is released.
<> 144:ef7eb2e8f9f7 19727 * | | |1 = When PWM Brake detects a falling signal at BKP0, this flag will be set to high to indicate the Brake0 state is locked.
<> 144:ef7eb2e8f9f7 19728 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 19729 * |[16:21] |CRLIF |Capture Rising Latch Interrupt Flag
<> 144:ef7eb2e8f9f7 19730 * | | |0 = No capture rising latch condition happened.
<> 144:ef7eb2e8f9f7 19731 * | | |1 = Capture rising latch condition happened, this flag will be set to high.
<> 144:ef7eb2e8f9f7 19732 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 19733 * |[22] |BRKSTS0 |Brake 0 Status (Read Only)
<> 144:ef7eb2e8f9f7 19734 * | | |0 = PWM had been out of Brake 0 state.
<> 144:ef7eb2e8f9f7 19735 * | | |1 = PWM is in Brake 0 state.
<> 144:ef7eb2e8f9f7 19736 * |[23] |BRKSTS1 |Brake 1 Status (Read Only)
<> 144:ef7eb2e8f9f7 19737 * | | |0 = PWM had been out of Brake 1 state.
<> 144:ef7eb2e8f9f7 19738 * | | |1 = PWM is in Brake 1 state.
<> 144:ef7eb2e8f9f7 19739 * |[24:29] |CFLIF |Capture Falling Latch Interrupt Flag
<> 144:ef7eb2e8f9f7 19740 * | | |0 = No capture falling latch condition happened.
<> 144:ef7eb2e8f9f7 19741 * | | |1 = Capture falling latch condition happened, this flag will be set to high.
<> 144:ef7eb2e8f9f7 19742 * | | |Note: This bit must be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 19743 */
<> 144:ef7eb2e8f9f7 19744 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 19745
<> 144:ef7eb2e8f9f7 19746 /**
<> 144:ef7eb2e8f9f7 19747 * POEN
<> 144:ef7eb2e8f9f7 19748 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19749 * Offset: 0x7C PWM Output Enable Control Register
<> 144:ef7eb2e8f9f7 19750 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19751 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19752 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19753 * |[0:5] |POEN |PWM Pin Output Enable Control
<> 144:ef7eb2e8f9f7 19754 * | | |0 = PWM pin at tri-state.
<> 144:ef7eb2e8f9f7 19755 * | | |1 = PWM pin in output mode.
<> 144:ef7eb2e8f9f7 19756 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19757 */
<> 144:ef7eb2e8f9f7 19758 __IO uint32_t POEN;
<> 144:ef7eb2e8f9f7 19759
<> 144:ef7eb2e8f9f7 19760 /**
<> 144:ef7eb2e8f9f7 19761 * CAPCTL
<> 144:ef7eb2e8f9f7 19762 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19763 * Offset: 0x80 PWM Capture Control Register
<> 144:ef7eb2e8f9f7 19764 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19765 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19766 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19767 * |[0:5] |CAPEN |Capture Function Enable Control
<> 144:ef7eb2e8f9f7 19768 * | | |0 = Capture function Disabled. RCAPDAT and FCAPDAT will not be updated.
<> 144:ef7eb2e8f9f7 19769 * | | |1 = Capture function Enabled.
<> 144:ef7eb2e8f9f7 19770 * | | |Capture latched the PWM counter value and saved to RCAPDAT (Rising latch) and FCAPDAT (Falling latch).
<> 144:ef7eb2e8f9f7 19771 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19772 * |[8:13] |CAPINV |Capture Inverter Enable Control
<> 144:ef7eb2e8f9f7 19773 * | | |0 = Capture source inverter Disabled.
<> 144:ef7eb2e8f9f7 19774 * | | |1 = Capture source inverter Enabled. Reverse the input signal from GPIO
<> 144:ef7eb2e8f9f7 19775 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19776 * |[16:21] |RCRLDEN |Rising Latch Reload Enable Control
<> 144:ef7eb2e8f9f7 19777 * | | |0 = Rising latch reload counter Enabled.
<> 144:ef7eb2e8f9f7 19778 * | | |1 = Rising latch reload counter Enabled.
<> 144:ef7eb2e8f9f7 19779 * |[24:29] |FCRLDEN |Falling Latch Reload Enable Control
<> 144:ef7eb2e8f9f7 19780 * | | |0 = Falling latch reload counter Disabled.
<> 144:ef7eb2e8f9f7 19781 * | | |1 = Falling latch
<> 144:ef7eb2e8f9f7 19782 * | | |reload counter Enabled.
<> 144:ef7eb2e8f9f7 19783 */
<> 144:ef7eb2e8f9f7 19784 __IO uint32_t CAPCTL;
<> 144:ef7eb2e8f9f7 19785
<> 144:ef7eb2e8f9f7 19786 /**
<> 144:ef7eb2e8f9f7 19787 * CAPINEN
<> 144:ef7eb2e8f9f7 19788 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19789 * Offset: 0x84 PWM Capture Input Enable Control Register
<> 144:ef7eb2e8f9f7 19790 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19791 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19792 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19793 * |[0:5] |CAPINEN |Capture Input Enable Control
<> 144:ef7eb2e8f9f7 19794 * | | |0 = PWM Channel capture input path Disabled.
<> 144:ef7eb2e8f9f7 19795 * | | |The input of PWM channel capture function is always regarded as 0.
<> 144:ef7eb2e8f9f7 19796 * | | |1 = PWM Channel capture input path Enabled.
<> 144:ef7eb2e8f9f7 19797 * | | |The input of PWM channel capture function comes from correlative multifunction pin.
<> 144:ef7eb2e8f9f7 19798 * | | |Note: Each bit controls the corresponding PWM channel.
<> 144:ef7eb2e8f9f7 19799 */
<> 144:ef7eb2e8f9f7 19800 __IO uint32_t CAPINEN;
<> 144:ef7eb2e8f9f7 19801
<> 144:ef7eb2e8f9f7 19802 /**
<> 144:ef7eb2e8f9f7 19803 * CAPSTS
<> 144:ef7eb2e8f9f7 19804 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19805 * Offset: 0x88 PWM Capture Status Register
<> 144:ef7eb2e8f9f7 19806 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19807 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19808 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19809 * |[0:5] |CRIFOV |Rising Latch Interrupt Flag Overrun Status
<> 144:ef7eb2e8f9f7 19810 * | | |This flag indicates if rising latch happened when the corresponding CRLIF is 1
<> 144:ef7eb2e8f9f7 19811 * | | |Note: This bit will be cleared automatically when user clear corresponding CRLIF.
<> 144:ef7eb2e8f9f7 19812 * |[8:13] |FLIFOV |Falling Latch Interrupt Flag Overrun Status
<> 144:ef7eb2e8f9f7 19813 * | | |This flag indicates if falling latch happened when the corresponding CFLIF is 1
<> 144:ef7eb2e8f9f7 19814 * | | |Note: This bit will be cleared automatically when user clear corresponding CFLIF.
<> 144:ef7eb2e8f9f7 19815 */
<> 144:ef7eb2e8f9f7 19816 __I uint32_t CAPSTS;
<> 144:ef7eb2e8f9f7 19817 uint32_t RESERVE0[1];
<> 144:ef7eb2e8f9f7 19818
<> 144:ef7eb2e8f9f7 19819
<> 144:ef7eb2e8f9f7 19820 /**
<> 144:ef7eb2e8f9f7 19821 * RCAPDAT0
<> 144:ef7eb2e8f9f7 19822 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19823 * Offset: 0x90 PWM Capture Rising Latch Register 0
<> 144:ef7eb2e8f9f7 19824 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19825 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19826 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19827 * |[0:15] |RCAPDAT |Capture Rising Latch Register
<> 144:ef7eb2e8f9f7 19828 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
<> 144:ef7eb2e8f9f7 19829 */
<> 144:ef7eb2e8f9f7 19830 __I uint32_t RCAPDAT0;
<> 144:ef7eb2e8f9f7 19831
<> 144:ef7eb2e8f9f7 19832 /**
<> 144:ef7eb2e8f9f7 19833 * FCAPDAT0
<> 144:ef7eb2e8f9f7 19834 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19835 * Offset: 0x94 PWM Capture Falling Latch Register 0
<> 144:ef7eb2e8f9f7 19836 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19837 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19838 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19839 * |[0:15] |FCAPDAT |Capture Falling Latch Register
<> 144:ef7eb2e8f9f7 19840 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
<> 144:ef7eb2e8f9f7 19841 */
<> 144:ef7eb2e8f9f7 19842 __I uint32_t FCAPDAT0;
<> 144:ef7eb2e8f9f7 19843
<> 144:ef7eb2e8f9f7 19844 /**
<> 144:ef7eb2e8f9f7 19845 * RCAPDAT1
<> 144:ef7eb2e8f9f7 19846 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19847 * Offset: 0x98 PWM Capture Rising Latch Register 1
<> 144:ef7eb2e8f9f7 19848 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19849 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19850 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19851 * |[0:15] |RCAPDAT |Capture Rising Latch Register
<> 144:ef7eb2e8f9f7 19852 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
<> 144:ef7eb2e8f9f7 19853 */
<> 144:ef7eb2e8f9f7 19854 __I uint32_t RCAPDAT1;
<> 144:ef7eb2e8f9f7 19855
<> 144:ef7eb2e8f9f7 19856 /**
<> 144:ef7eb2e8f9f7 19857 * FCAPDAT1
<> 144:ef7eb2e8f9f7 19858 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19859 * Offset: 0x9C PWM Capture Falling Latch Register 1
<> 144:ef7eb2e8f9f7 19860 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19861 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19862 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19863 * |[0:15] |FCAPDAT |Capture Falling Latch Register
<> 144:ef7eb2e8f9f7 19864 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
<> 144:ef7eb2e8f9f7 19865 */
<> 144:ef7eb2e8f9f7 19866 __I uint32_t FCAPDAT1;
<> 144:ef7eb2e8f9f7 19867
<> 144:ef7eb2e8f9f7 19868 /**
<> 144:ef7eb2e8f9f7 19869 * RCAPDAT2
<> 144:ef7eb2e8f9f7 19870 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19871 * Offset: 0xA0 PWM Capture Rising Latch Register 2
<> 144:ef7eb2e8f9f7 19872 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19873 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19874 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19875 * |[0:15] |RCAPDAT |Capture Rising Latch Register
<> 144:ef7eb2e8f9f7 19876 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
<> 144:ef7eb2e8f9f7 19877 */
<> 144:ef7eb2e8f9f7 19878 __I uint32_t RCAPDAT2;
<> 144:ef7eb2e8f9f7 19879
<> 144:ef7eb2e8f9f7 19880 /**
<> 144:ef7eb2e8f9f7 19881 * FCAPDAT2
<> 144:ef7eb2e8f9f7 19882 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19883 * Offset: 0xA4 PWM Capture Falling Latch Register 2
<> 144:ef7eb2e8f9f7 19884 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19885 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19886 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19887 * |[0:15] |FCAPDAT |Capture Falling Latch Register
<> 144:ef7eb2e8f9f7 19888 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
<> 144:ef7eb2e8f9f7 19889 */
<> 144:ef7eb2e8f9f7 19890 __I uint32_t FCAPDAT2;
<> 144:ef7eb2e8f9f7 19891
<> 144:ef7eb2e8f9f7 19892 /**
<> 144:ef7eb2e8f9f7 19893 * RCAPDAT3
<> 144:ef7eb2e8f9f7 19894 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19895 * Offset: 0xA8 PWM Capture Rising Latch Register 3
<> 144:ef7eb2e8f9f7 19896 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19897 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19898 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19899 * |[0:15] |RCAPDAT |Capture Rising Latch Register
<> 144:ef7eb2e8f9f7 19900 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
<> 144:ef7eb2e8f9f7 19901 */
<> 144:ef7eb2e8f9f7 19902 __I uint32_t RCAPDAT3;
<> 144:ef7eb2e8f9f7 19903
<> 144:ef7eb2e8f9f7 19904 /**
<> 144:ef7eb2e8f9f7 19905 * FCAPDAT3
<> 144:ef7eb2e8f9f7 19906 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19907 * Offset: 0xAC PWM Capture Falling Latch Register 3
<> 144:ef7eb2e8f9f7 19908 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19909 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19910 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19911 * |[0:15] |FCAPDAT |Capture Falling Latch Register
<> 144:ef7eb2e8f9f7 19912 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
<> 144:ef7eb2e8f9f7 19913 */
<> 144:ef7eb2e8f9f7 19914 __I uint32_t FCAPDAT3;
<> 144:ef7eb2e8f9f7 19915
<> 144:ef7eb2e8f9f7 19916 /**
<> 144:ef7eb2e8f9f7 19917 * RCAPDAT4
<> 144:ef7eb2e8f9f7 19918 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19919 * Offset: 0xB0 PWM Capture Rising Latch Register 4
<> 144:ef7eb2e8f9f7 19920 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19921 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19922 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19923 * |[0:15] |RCAPDAT |Capture Rising Latch Register
<> 144:ef7eb2e8f9f7 19924 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
<> 144:ef7eb2e8f9f7 19925 */
<> 144:ef7eb2e8f9f7 19926 __I uint32_t RCAPDAT4;
<> 144:ef7eb2e8f9f7 19927
<> 144:ef7eb2e8f9f7 19928 /**
<> 144:ef7eb2e8f9f7 19929 * FCAPDAT4
<> 144:ef7eb2e8f9f7 19930 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19931 * Offset: 0xB4 PWM Capture Falling Latch Register 4
<> 144:ef7eb2e8f9f7 19932 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19933 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19934 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19935 * |[0:15] |FCAPDAT |Capture Falling Latch Register
<> 144:ef7eb2e8f9f7 19936 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
<> 144:ef7eb2e8f9f7 19937 */
<> 144:ef7eb2e8f9f7 19938 __I uint32_t FCAPDAT4;
<> 144:ef7eb2e8f9f7 19939
<> 144:ef7eb2e8f9f7 19940 /**
<> 144:ef7eb2e8f9f7 19941 * RCAPDAT5
<> 144:ef7eb2e8f9f7 19942 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19943 * Offset: 0xB8 PWM Capture Rising Latch Register 5
<> 144:ef7eb2e8f9f7 19944 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19945 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19946 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19947 * |[0:15] |RCAPDAT |Capture Rising Latch Register
<> 144:ef7eb2e8f9f7 19948 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has rising transition.
<> 144:ef7eb2e8f9f7 19949 */
<> 144:ef7eb2e8f9f7 19950 __I uint32_t RCAPDAT5;
<> 144:ef7eb2e8f9f7 19951
<> 144:ef7eb2e8f9f7 19952 /**
<> 144:ef7eb2e8f9f7 19953 * FCAPDAT5
<> 144:ef7eb2e8f9f7 19954 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19955 * Offset: 0xBC PWM Capture Falling Latch Register 5
<> 144:ef7eb2e8f9f7 19956 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19957 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19958 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19959 * |[0:15] |FCAPDAT |Capture Falling Latch Register
<> 144:ef7eb2e8f9f7 19960 * | | |Latch the PWM counter when Channel 0/1/2/3/4/5 has Falling transition.
<> 144:ef7eb2e8f9f7 19961 */
<> 144:ef7eb2e8f9f7 19962 __I uint32_t FCAPDAT5;
<> 144:ef7eb2e8f9f7 19963 uint32_t RESERVE1[8];
<> 144:ef7eb2e8f9f7 19964
<> 144:ef7eb2e8f9f7 19965
<> 144:ef7eb2e8f9f7 19966 /**
<> 144:ef7eb2e8f9f7 19967 * SBS0
<> 144:ef7eb2e8f9f7 19968 * ===================================================================================================
<> 144:ef7eb2e8f9f7 19969 * Offset: 0xE0 PWM0 Synchronous Busy Status Register
<> 144:ef7eb2e8f9f7 19970 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 19971 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 19972 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 19973 * |[0] |SYNCBUSY |PWM Synchronous Busy
<> 144:ef7eb2e8f9f7 19974 * | | |When software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 counter operation mode CNTMOD (CONR[16]), PWM will have a busy time to update these values completely because PWM clock may be different from system clock domain.
<> 144:ef7eb2e8f9f7 19975 * | | |Software needs to check this busy status before writes PWM_PERIOD0/PWM_CMPDAT0/ PWM_CLKPSC or switch PWM0 counter operation mode to make sure previous setting has been update completely.
<> 144:ef7eb2e8f9f7 19976 * | | |This bit will be set when software writes PWM_PERIOD0/PWM_CMPDAT0/PWM_CLKPSC or switch PWM0 operation mode CNTMOD (CONR[16]) and will be cleared by hardware automatically when PWM update these value completely.
<> 144:ef7eb2e8f9f7 19977 */
<> 144:ef7eb2e8f9f7 19978 __I uint32_t SBS[6];
<> 144:ef7eb2e8f9f7 19979
<> 144:ef7eb2e8f9f7 19980 } PWM_T;
<> 144:ef7eb2e8f9f7 19981
<> 144:ef7eb2e8f9f7 19982 /**
<> 144:ef7eb2e8f9f7 19983 @addtogroup PWM_CONST PWM Bit Field Definition
<> 144:ef7eb2e8f9f7 19984 Constant Definitions for PWM Controller
<> 144:ef7eb2e8f9f7 19985 @{ */
<> 144:ef7eb2e8f9f7 19986
<> 144:ef7eb2e8f9f7 19987 #define PWM_CLKPSC_CLKPSC01_Pos (0) /*!< PWM CLKPSC: CLKPSC01 Position */
<> 144:ef7eb2e8f9f7 19988 #define PWM_CLKPSC_CLKPSC01_Msk (0xfful << PWM_CLKPSC_CLKPSC01_Pos) /*!< PWM CLKPSC: CLKPSC01 Mask */
<> 144:ef7eb2e8f9f7 19989
<> 144:ef7eb2e8f9f7 19990 #define PWM_CLKPSC_CLKPSC23_Pos (8) /*!< PWM CLKPSC: CLKPSC23 Position */
<> 144:ef7eb2e8f9f7 19991 #define PWM_CLKPSC_CLKPSC23_Msk (0xfful << PWM_CLKPSC_CLKPSC23_Pos) /*!< PWM CLKPSC: CLKPSC23 Mask */
<> 144:ef7eb2e8f9f7 19992
<> 144:ef7eb2e8f9f7 19993 #define PWM_CLKPSC_CLKPSC45_Pos (16) /*!< PWM CLKPSC: CLKPSC45 Position */
<> 144:ef7eb2e8f9f7 19994 #define PWM_CLKPSC_CLKPSC45_Msk (0xfful << PWM_CLKPSC_CLKPSC45_Pos) /*!< PWM CLKPSC: CLKPSC45 Mask */
<> 144:ef7eb2e8f9f7 19995
<> 144:ef7eb2e8f9f7 19996 #define PWM_CLKDIV_CLKDIV0_Pos (0) /*!< PWM CLKDIV: CLKDIV0 Position */
<> 144:ef7eb2e8f9f7 19997 #define PWM_CLKDIV_CLKDIV0_Msk (0x7ul << PWM_CLKDIV_CLKDIV0_Pos) /*!< PWM CLKDIV: CLKDIV0 Mask */
<> 144:ef7eb2e8f9f7 19998
<> 144:ef7eb2e8f9f7 19999 #define PWM_CLKDIV_CLKDIV1_Pos (4) /*!< PWM CLKDIV: CLKDIV1 Position */
<> 144:ef7eb2e8f9f7 20000 #define PWM_CLKDIV_CLKDIV1_Msk (0x7ul << PWM_CLKDIV_CLKDIV1_Pos) /*!< PWM CLKDIV: CLKDIV1 Mask */
<> 144:ef7eb2e8f9f7 20001
<> 144:ef7eb2e8f9f7 20002 #define PWM_CLKDIV_CLKDIV2_Pos (8) /*!< PWM CLKDIV: CLKDIV2 Position */
<> 144:ef7eb2e8f9f7 20003 #define PWM_CLKDIV_CLKDIV2_Msk (0x7ul << PWM_CLKDIV_CLKDIV2_Pos) /*!< PWM CLKDIV: CLKDIV2 Mask */
<> 144:ef7eb2e8f9f7 20004
<> 144:ef7eb2e8f9f7 20005 #define PWM_CLKDIV_CLKDIV3_Pos (12) /*!< PWM CLKDIV: CLKDIV3 Position */
<> 144:ef7eb2e8f9f7 20006 #define PWM_CLKDIV_CLKDIV3_Msk (0x7ul << PWM_CLKDIV_CLKDIV3_Pos) /*!< PWM CLKDIV: CLKDIV3 Mask */
<> 144:ef7eb2e8f9f7 20007
<> 144:ef7eb2e8f9f7 20008 #define PWM_CLKDIV_CLKDIV4_Pos (16) /*!< PWM CLKDIV: CLKDIV4 Position */
<> 144:ef7eb2e8f9f7 20009 #define PWM_CLKDIV_CLKDIV4_Msk (0x7ul << PWM_CLKDIV_CLKDIV4_Pos) /*!< PWM CLKDIV: CLKDIV4 Mask */
<> 144:ef7eb2e8f9f7 20010
<> 144:ef7eb2e8f9f7 20011 #define PWM_CLKDIV_CLKDIV5_Pos (20) /*!< PWM CLKDIV: CLKDIV5 Position */
<> 144:ef7eb2e8f9f7 20012 #define PWM_CLKDIV_CLKDIV5_Msk (0x7ul << PWM_CLKDIV_CLKDIV5_Pos) /*!< PWM CLKDIV: CLKDIV5 Mask */
<> 144:ef7eb2e8f9f7 20013
<> 144:ef7eb2e8f9f7 20014 #define PWM_CTL_CMPINV_Pos (0) /*!< PWM CTL: CMPINV Position */
<> 144:ef7eb2e8f9f7 20015 #define PWM_CTL_CMPINV_Msk (0x3ful << PWM_CTL_CMPINV_Pos) /*!< PWM CTL: CMPINV Mask */
<> 144:ef7eb2e8f9f7 20016
<> 144:ef7eb2e8f9f7 20017 #define PWM_CTL_OUTMODE_Pos (6) /*!< PWM CTL: OUTMODE Position */
<> 144:ef7eb2e8f9f7 20018 #define PWM_CTL_OUTMODE_Msk (0x1ul << PWM_CTL_OUTMODE_Pos) /*!< PWM CTL: OUTMODE Mask */
<> 144:ef7eb2e8f9f7 20019
<> 144:ef7eb2e8f9f7 20020 #define PWM_CTL_GROUPEN_Pos (7) /*!< PWM CTL: GROUPEN Position */
<> 144:ef7eb2e8f9f7 20021 #define PWM_CTL_GROUPEN_Msk (0x1ul << PWM_CTL_GROUPEN_Pos) /*!< PWM CTL: GROUPEN Mask */
<> 144:ef7eb2e8f9f7 20022
<> 144:ef7eb2e8f9f7 20023 #define PWM_CTL_PINV_Pos (8) /*!< PWM CTL: PINV Position */
<> 144:ef7eb2e8f9f7 20024 #define PWM_CTL_PINV_Msk (0x3ful << PWM_CTL_PINV_Pos) /*!< PWM CTL: PINV Mask */
<> 144:ef7eb2e8f9f7 20025
<> 144:ef7eb2e8f9f7 20026 #define PWM_CTL_SYNCEN_Pos (15) /*!< PWM CTL: SYNCEN Position */
<> 144:ef7eb2e8f9f7 20027 #define PWM_CTL_SYNCEN_Msk (0x1ul << PWM_CTL_SYNCEN_Pos) /*!< PWM CTL: SYNCEN Mask */
<> 144:ef7eb2e8f9f7 20028
<> 144:ef7eb2e8f9f7 20029 #define PWM_CTL_CNTMODE_Pos (16) /*!< PWM CTL: CNTMODE Position */
<> 144:ef7eb2e8f9f7 20030 #define PWM_CTL_CNTMODE_Msk (0x3ful << PWM_CTL_CNTMODE_Pos) /*!< PWM CTL: CNTMODE Mask */
<> 144:ef7eb2e8f9f7 20031
<> 144:ef7eb2e8f9f7 20032 #define PWM_CTL_CNTTYPE_Pos (24) /*!< PWM CTL: CNTTYPE Position */
<> 144:ef7eb2e8f9f7 20033 #define PWM_CTL_CNTTYPE_Msk (0x3ful << PWM_CTL_CNTTYPE_Pos) /*!< PWM CTL: CNTTYPE Mask */
<> 144:ef7eb2e8f9f7 20034
<> 144:ef7eb2e8f9f7 20035 #define PWM_CTL_DBGTRIOFF_Pos (31) /*!< PWM CTL: DBGTRIOFF Position */
<> 144:ef7eb2e8f9f7 20036 #define PWM_CTL_DBGTRIOFF_Msk (0x1ul << PWM_CTL_DBGTRIOFF_Pos) /*!< PWM CTL: DBGTRIOFF Mask */
<> 144:ef7eb2e8f9f7 20037
<> 144:ef7eb2e8f9f7 20038 #define PWM_CNTEN_CNTEN_Pos (0) /*!< PWM CNTEN: CNTEN Position */
<> 144:ef7eb2e8f9f7 20039 #define PWM_CNTEN_CNTEN_Msk (0x3ful << PWM_CNTEN_CNTEN_Pos) /*!< PWM CNTEN: CNTEN Mask */
<> 144:ef7eb2e8f9f7 20040
<> 144:ef7eb2e8f9f7 20041 #define PWM_PERIOD0_PERIOD_Pos (0) /*!< PWM PERIOD0: PERIOD Position */
<> 144:ef7eb2e8f9f7 20042 #define PWM_PERIOD0_PERIOD_Msk (0xfffful << PWM_PERIOD0_PERIOD_Pos) /*!< PWM PERIOD0: PERIOD Mask */
<> 144:ef7eb2e8f9f7 20043
<> 144:ef7eb2e8f9f7 20044 #define PWM_PERIOD1_PERIOD_Pos (0) /*!< PWM PERIOD1: PERIOD Position */
<> 144:ef7eb2e8f9f7 20045 #define PWM_PERIOD1_PERIOD_Msk (0xfffful << PWM_PERIOD1_PERIOD_Pos) /*!< PWM PERIOD1: PERIOD Mask */
<> 144:ef7eb2e8f9f7 20046
<> 144:ef7eb2e8f9f7 20047 #define PWM_PERIOD2_PERIOD_Pos (0) /*!< PWM PERIOD2: PERIOD Position */
<> 144:ef7eb2e8f9f7 20048 #define PWM_PERIOD2_PERIOD_Msk (0xfffful << PWM_PERIOD2_PERIOD_Pos) /*!< PWM PERIOD2: PERIOD Mask */
<> 144:ef7eb2e8f9f7 20049
<> 144:ef7eb2e8f9f7 20050 #define PWM_PERIOD3_PERIOD_Pos (0) /*!< PWM PERIOD3: PERIOD Position */
<> 144:ef7eb2e8f9f7 20051 #define PWM_PERIOD3_PERIOD_Msk (0xfffful << PWM_PERIOD3_PERIOD_Pos) /*!< PWM PERIOD3: PERIOD Mask */
<> 144:ef7eb2e8f9f7 20052
<> 144:ef7eb2e8f9f7 20053 #define PWM_PERIOD4_PERIOD_Pos (0) /*!< PWM PERIOD4: PERIOD Position */
<> 144:ef7eb2e8f9f7 20054 #define PWM_PERIOD4_PERIOD_Msk (0xfffful << PWM_PERIOD4_PERIOD_Pos) /*!< PWM PERIOD4: PERIOD Mask */
<> 144:ef7eb2e8f9f7 20055
<> 144:ef7eb2e8f9f7 20056 #define PWM_PERIOD5_PERIOD_Pos (0) /*!< PWM PERIOD5: PERIOD Position */
<> 144:ef7eb2e8f9f7 20057 #define PWM_PERIOD5_PERIOD_Msk (0xfffful << PWM_PERIOD5_PERIOD_Pos) /*!< PWM PERIOD5: PERIOD Mask */
<> 144:ef7eb2e8f9f7 20058
<> 144:ef7eb2e8f9f7 20059 #define PWM_CMPDAT0_CMP_Pos (0) /*!< PWM CMPDAT0: CMP Position */
<> 144:ef7eb2e8f9f7 20060 #define PWM_CMPDAT0_CMP_Msk (0xfffful << PWM_CMPDAT0_CMP_Pos) /*!< PWM CMPDAT0: CMP Mask */
<> 144:ef7eb2e8f9f7 20061
<> 144:ef7eb2e8f9f7 20062 #define PWM_CMPDAT1_CMP_Pos (0) /*!< PWM CMPDAT1: CMP Position */
<> 144:ef7eb2e8f9f7 20063 #define PWM_CMPDAT1_CMP_Msk (0xfffful << PWM_CMPDAT1_CMP_Pos) /*!< PWM CMPDAT1: CMP Mask */
<> 144:ef7eb2e8f9f7 20064
<> 144:ef7eb2e8f9f7 20065 #define PWM_CMPDAT2_CMP_Pos (0) /*!< PWM CMPDAT2: CMP Position */
<> 144:ef7eb2e8f9f7 20066 #define PWM_CMPDAT2_CMP_Msk (0xfffful << PWM_CMPDAT2_CMP_Pos) /*!< PWM CMPDAT2: CMP Mask */
<> 144:ef7eb2e8f9f7 20067
<> 144:ef7eb2e8f9f7 20068 #define PWM_CMPDAT3_CMP_Pos (0) /*!< PWM CMPDAT3: CMP Position */
<> 144:ef7eb2e8f9f7 20069 #define PWM_CMPDAT3_CMP_Msk (0xfffful << PWM_CMPDAT3_CMP_Pos) /*!< PWM CMPDAT3: CMP Mask */
<> 144:ef7eb2e8f9f7 20070
<> 144:ef7eb2e8f9f7 20071 #define PWM_CMPDAT4_CMP_Pos (0) /*!< PWM CMPDAT4: CMP Position */
<> 144:ef7eb2e8f9f7 20072 #define PWM_CMPDAT4_CMP_Msk (0xfffful << PWM_CMPDAT4_CMP_Pos) /*!< PWM CMPDAT4: CMP Mask */
<> 144:ef7eb2e8f9f7 20073
<> 144:ef7eb2e8f9f7 20074 #define PWM_CMPDAT5_CMP_Pos (0) /*!< PWM CMPDAT5: CMP Position */
<> 144:ef7eb2e8f9f7 20075 #define PWM_CMPDAT5_CMP_Msk (0xfffful << PWM_CMPDAT5_CMP_Pos) /*!< PWM CMPDAT5: CMP Mask */
<> 144:ef7eb2e8f9f7 20076
<> 144:ef7eb2e8f9f7 20077 #define PWM_CNT0_CNT_Pos (0) /*!< PWM CNT0: CNT Position */
<> 144:ef7eb2e8f9f7 20078 #define PWM_CNT0_CNT_Msk (0xfffful << PWM_CNT0_CNT_Pos) /*!< PWM CNT0: CNT Mask */
<> 144:ef7eb2e8f9f7 20079
<> 144:ef7eb2e8f9f7 20080 #define PWM_CNT1_CNT_Pos (0) /*!< PWM CNT1: CNT Position */
<> 144:ef7eb2e8f9f7 20081 #define PWM_CNT1_CNT_Msk (0xfffful << PWM_CNT1_CNT_Pos) /*!< PWM CNT1: CNT Mask */
<> 144:ef7eb2e8f9f7 20082
<> 144:ef7eb2e8f9f7 20083 #define PWM_CNT2_CNT_Pos (0) /*!< PWM CNT2: CNT Position */
<> 144:ef7eb2e8f9f7 20084 #define PWM_CNT2_CNT_Msk (0xfffful << PWM_CNT2_CNT_Pos) /*!< PWM CNT2: CNT Mask */
<> 144:ef7eb2e8f9f7 20085
<> 144:ef7eb2e8f9f7 20086 #define PWM_CNT3_CNT_Pos (0) /*!< PWM CNT3: CNT Position */
<> 144:ef7eb2e8f9f7 20087 #define PWM_CNT3_CNT_Msk (0xfffful << PWM_CNT3_CNT_Pos) /*!< PWM CNT3: CNT Mask */
<> 144:ef7eb2e8f9f7 20088
<> 144:ef7eb2e8f9f7 20089 #define PWM_CNT4_CNT_Pos (0) /*!< PWM CNT4: CNT Position */
<> 144:ef7eb2e8f9f7 20090 #define PWM_CNT4_CNT_Msk (0xfffful << PWM_CNT4_CNT_Pos) /*!< PWM CNT4: CNT Mask */
<> 144:ef7eb2e8f9f7 20091
<> 144:ef7eb2e8f9f7 20092 #define PWM_CNT5_CNT_Pos (0) /*!< PWM CNT5: CNT Position */
<> 144:ef7eb2e8f9f7 20093 #define PWM_CNT5_CNT_Msk (0xfffful << PWM_CNT5_CNT_Pos) /*!< PWM CNT5: CNT Mask */
<> 144:ef7eb2e8f9f7 20094
<> 144:ef7eb2e8f9f7 20095 #define PWM_MSKEN_MSKEN_Pos (0) /*!< PWM MSKEN: MSKEN Position */
<> 144:ef7eb2e8f9f7 20096 #define PWM_MSKEN_MSKEN_Msk (0x3ful << PWM_MSKEN_MSKEN_Pos) /*!< PWM MSKEN: MSKEN Mask */
<> 144:ef7eb2e8f9f7 20097
<> 144:ef7eb2e8f9f7 20098 #define PWM_MSK_MSKDAT_Pos (0) /*!< PWM MSK: MSKDAT Position */
<> 144:ef7eb2e8f9f7 20099 #define PWM_MSK_MSKDAT_Msk (0x3ful << PWM_MSK_MSKDAT_Pos) /*!< PWM MSK: MSKDAT Mask */
<> 144:ef7eb2e8f9f7 20100
<> 144:ef7eb2e8f9f7 20101 #define PWM_DTCTL_DTCNT01_Pos (0) /*!< PWM DTCTL: DTCNT01 Position */
<> 144:ef7eb2e8f9f7 20102 #define PWM_DTCTL_DTCNT01_Msk (0xfful << PWM_DTCTL_DTCNT01_Pos) /*!< PWM DTCTL: DTCNT01 Mask */
<> 144:ef7eb2e8f9f7 20103
<> 144:ef7eb2e8f9f7 20104 #define PWM_DTCTL_DTCNT23_Pos (8) /*!< PWM DTCTL: DTCNT23 Position */
<> 144:ef7eb2e8f9f7 20105 #define PWM_DTCTL_DTCNT23_Msk (0xfful << PWM_DTCTL_DTCNT23_Pos) /*!< PWM DTCTL: DTCNT23 Mask */
<> 144:ef7eb2e8f9f7 20106
<> 144:ef7eb2e8f9f7 20107 #define PWM_DTCTL_DTCNT45_Pos (16) /*!< PWM DTCTL: DTCNT45 Position */
<> 144:ef7eb2e8f9f7 20108 #define PWM_DTCTL_DTCNT45_Msk (0xfful << PWM_DTCTL_DTCNT45_Pos) /*!< PWM DTCTL: DTCNT45 Mask */
<> 144:ef7eb2e8f9f7 20109
<> 144:ef7eb2e8f9f7 20110 #define PWM_DTCTL_DTDIV_Pos (24) /*!< PWM DTCTL: DTDIV Position */
<> 144:ef7eb2e8f9f7 20111 #define PWM_DTCTL_DTDIV_Msk (0x3ul << PWM_DTCTL_DTDIV_Pos) /*!< PWM DTCTL: DTDIV Mask */
<> 144:ef7eb2e8f9f7 20112
<> 144:ef7eb2e8f9f7 20113 #define PWM_DTCTL_DTEN01_Pos (28) /*!< PWM DTCTL: DTEN01 Position */
<> 144:ef7eb2e8f9f7 20114 #define PWM_DTCTL_DTEN01_Msk (0x1ul << PWM_DTCTL_DTEN01_Pos) /*!< PWM DTCTL: DTEN01 Mask */
<> 144:ef7eb2e8f9f7 20115
<> 144:ef7eb2e8f9f7 20116 #define PWM_DTCTL_DTEN23_Pos (29) /*!< PWM DTCTL: DTEN23 Position */
<> 144:ef7eb2e8f9f7 20117 #define PWM_DTCTL_DTEN23_Msk (0x1ul << PWM_DTCTL_DTEN23_Pos) /*!< PWM DTCTL: DTEN23 Mask */
<> 144:ef7eb2e8f9f7 20118
<> 144:ef7eb2e8f9f7 20119 #define PWM_DTCTL_DTEN45_Pos (30) /*!< PWM DTCTL: DTEN45 Position */
<> 144:ef7eb2e8f9f7 20120 #define PWM_DTCTL_DTEN45_Msk (0x1ul << PWM_DTCTL_DTEN45_Pos) /*!< PWM DTCTL: DTEN45 Mask */
<> 144:ef7eb2e8f9f7 20121
<> 144:ef7eb2e8f9f7 20122 #define PWM_TRGADCTL_PTRGEN_Pos (0) /*!< PWM TRGADCTL: PTRGEN Position */
<> 144:ef7eb2e8f9f7 20123 #define PWM_TRGADCTL_PTRGEN_Msk (0x3ful << PWM_TRGADCTL_PTRGEN_Pos) /*!< PWM TRGADCTL: PTRGEN Mask */
<> 144:ef7eb2e8f9f7 20124
<> 144:ef7eb2e8f9f7 20125 #define PWM_TRGADCTL_CTRGEN_Pos (8) /*!< PWM TRGADCTL: CTRGEN Position */
<> 144:ef7eb2e8f9f7 20126 #define PWM_TRGADCTL_CTRGEN_Msk (0x3ful << PWM_TRGADCTL_CTRGEN_Pos) /*!< PWM TRGADCTL: CTRGEN Mask */
<> 144:ef7eb2e8f9f7 20127
<> 144:ef7eb2e8f9f7 20128 #define PWM_TRGADCTL_FTRGEN_Pos (16) /*!< PWM TRGADCTL: FTRGEN Position */
<> 144:ef7eb2e8f9f7 20129 #define PWM_TRGADCTL_FTRGEN_Msk (0x3ful << PWM_TRGADCTL_FTRGEN_Pos) /*!< PWM TRGADCTL: FTRGEN Mask */
<> 144:ef7eb2e8f9f7 20130
<> 144:ef7eb2e8f9f7 20131 #define PWM_TRGADCTL_RTRGEN_Pos (24) /*!< PWM TRGADCTL: RTRGEN Position */
<> 144:ef7eb2e8f9f7 20132 #define PWM_TRGADCTL_RTRGEN_Msk (0x3ful << PWM_TRGADCTL_RTRGEN_Pos) /*!< PWM TRGADCTL: RTRGEN Mask */
<> 144:ef7eb2e8f9f7 20133
<> 144:ef7eb2e8f9f7 20134 #define PWM_TRGADCSTS_PTRGF_Pos (0) /*!< PWM TRGADCSTS: PTRGF Position */
<> 144:ef7eb2e8f9f7 20135 #define PWM_TRGADCSTS_PTRGF_Msk (0x3ful << PWM_TRGADCSTS_PTRGF_Pos) /*!< PWM TRGADCSTS: PTRGF Mask */
<> 144:ef7eb2e8f9f7 20136
<> 144:ef7eb2e8f9f7 20137 #define PWM_TRGADCSTS_CTRGF_Pos (8) /*!< PWM TRGADCSTS: CTRGF Position */
<> 144:ef7eb2e8f9f7 20138 #define PWM_TRGADCSTS_CTRGF_Msk (0x3ful << PWM_TRGADCSTS_CTRGF_Pos) /*!< PWM TRGADCSTS: CTRGF Mask */
<> 144:ef7eb2e8f9f7 20139
<> 144:ef7eb2e8f9f7 20140 #define PWM_TRGADCSTS_FTRGF_Pos (16) /*!< PWM TRGADCSTS: FTRGF Position */
<> 144:ef7eb2e8f9f7 20141 #define PWM_TRGADCSTS_FTRGF_Msk (0x3ful << PWM_TRGADCSTS_FTRGF_Pos) /*!< PWM TRGADCSTS: FTRGF Mask */
<> 144:ef7eb2e8f9f7 20142
<> 144:ef7eb2e8f9f7 20143 #define PWM_TRGADCSTS_RTRGF_Pos (24) /*!< PWM TRGADCSTS: RTRGF Position */
<> 144:ef7eb2e8f9f7 20144 #define PWM_TRGADCSTS_RTRGF_Msk (0x3ful << PWM_TRGADCSTS_RTRGF_Pos) /*!< PWM TRGADCSTS: RTRGF Mask */
<> 144:ef7eb2e8f9f7 20145
<> 144:ef7eb2e8f9f7 20146 #define PWM_BRKCTL_BRK0EN_Pos (0) /*!< PWM BRKCTL: BRK0EN Position */
<> 144:ef7eb2e8f9f7 20147 #define PWM_BRKCTL_BRK0EN_Msk (0x1ul << PWM_BRKCTL_BRK0EN_Pos) /*!< PWM BRKCTL: BRK0EN Mask */
<> 144:ef7eb2e8f9f7 20148
<> 144:ef7eb2e8f9f7 20149 #define PWM_BRKCTL_BRK0NFDIS_Pos (1) /*!< PWM BRKCTL: BRK0NFDIS Position */
<> 144:ef7eb2e8f9f7 20150 #define PWM_BRKCTL_BRK0NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK0NFDIS_Pos) /*!< PWM BRKCTL: BRK0NFDIS Mask */
<> 144:ef7eb2e8f9f7 20151
<> 144:ef7eb2e8f9f7 20152 #define PWM_BRKCTL_BRK0INV_Pos (2) /*!< PWM BRKCTL: BRK0INV Position */
<> 144:ef7eb2e8f9f7 20153 #define PWM_BRKCTL_BRK0INV_Msk (0x1ul << PWM_BRKCTL_BRK0INV_Pos) /*!< PWM BRKCTL: BRK0INV Mask */
<> 144:ef7eb2e8f9f7 20154
<> 144:ef7eb2e8f9f7 20155 #define PWM_BRKCTL_BRK0NFSEL_Pos (6) /*!< PWM BRKCTL: BRK0NFSEL Position */
<> 144:ef7eb2e8f9f7 20156 #define PWM_BRKCTL_BRK0NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK0NFSEL_Pos) /*!< PWM BRKCTL: BRK0NFSEL Mask */
<> 144:ef7eb2e8f9f7 20157
<> 144:ef7eb2e8f9f7 20158 #define PWM_BRKCTL_BRK1EN_Pos (8) /*!< PWM BRKCTL: BRK1EN Position */
<> 144:ef7eb2e8f9f7 20159 #define PWM_BRKCTL_BRK1EN_Msk (0x1ul << PWM_BRKCTL_BRK1EN_Pos) /*!< PWM BRKCTL: BRK1EN Mask */
<> 144:ef7eb2e8f9f7 20160
<> 144:ef7eb2e8f9f7 20161 #define PWM_BRKCTL_BRK1NFDIS_Pos (9) /*!< PWM BRKCTL: BRK1NFDIS Position */
<> 144:ef7eb2e8f9f7 20162 #define PWM_BRKCTL_BRK1NFDIS_Msk (0x1ul << PWM_BRKCTL_BRK1NFDIS_Pos) /*!< PWM BRKCTL: BRK1NFDIS Mask */
<> 144:ef7eb2e8f9f7 20163
<> 144:ef7eb2e8f9f7 20164 #define PWM_BRKCTL_BRK1INV_Pos (10) /*!< PWM BRKCTL: BRK1INV Position */
<> 144:ef7eb2e8f9f7 20165 #define PWM_BRKCTL_BRK1INV_Msk (0x1ul << PWM_BRKCTL_BRK1INV_Pos) /*!< PWM BRKCTL: BRK1INV Mask */
<> 144:ef7eb2e8f9f7 20166
<> 144:ef7eb2e8f9f7 20167 #define PWM_BRKCTL_BK1SEL_Pos (12) /*!< PWM BRKCTL: BK1SEL Position */
<> 144:ef7eb2e8f9f7 20168 #define PWM_BRKCTL_BK1SEL_Msk (0x3ul << PWM_BRKCTL_BK1SEL_Pos) /*!< PWM BRKCTL: BK1SEL Mask */
<> 144:ef7eb2e8f9f7 20169
<> 144:ef7eb2e8f9f7 20170 #define PWM_BRKCTL_BRK1NFSEL_Pos (14) /*!< PWM BRKCTL: BRK1NFSEL Position */
<> 144:ef7eb2e8f9f7 20171 #define PWM_BRKCTL_BRK1NFSEL_Msk (0x3ul << PWM_BRKCTL_BRK1NFSEL_Pos) /*!< PWM BRKCTL: BRK1NFSEL Mask */
<> 144:ef7eb2e8f9f7 20172
<> 144:ef7eb2e8f9f7 20173 #define PWM_BRKCTL_CPO0BKEN_Pos (16) /*!< PWM BRKCTL: CPO0BKEN Position */
<> 144:ef7eb2e8f9f7 20174 #define PWM_BRKCTL_CPO0BKEN_Msk (0x1ul << PWM_BRKCTL_CPO0BKEN_Pos) /*!< PWM BRKCTL: CPO0BKEN Mask */
<> 144:ef7eb2e8f9f7 20175
<> 144:ef7eb2e8f9f7 20176 #define PWM_BRKCTL_CPO1BKEN_Pos (17) /*!< PWM BRKCTL: CPO1BKEN Position */
<> 144:ef7eb2e8f9f7 20177 #define PWM_BRKCTL_CPO1BKEN_Msk (0x1ul << PWM_BRKCTL_CPO1BKEN_Pos) /*!< PWM BRKCTL: CPO1BKEN Mask */
<> 144:ef7eb2e8f9f7 20178
<> 144:ef7eb2e8f9f7 20179 #define PWM_BRKCTL_CPO2BKEN_Pos (18) /*!< PWM BRKCTL: CPO2BKEN Position */
<> 144:ef7eb2e8f9f7 20180 #define PWM_BRKCTL_CPO2BKEN_Msk (0x1ul << PWM_BRKCTL_CPO2BKEN_Pos) /*!< PWM BRKCTL: CPO2BKEN Mask */
<> 144:ef7eb2e8f9f7 20181
<> 144:ef7eb2e8f9f7 20182 #define PWM_BRKCTL_LVDBKEN_Pos (19) /*!< PWM BRKCTL: LVDBKEN Position */
<> 144:ef7eb2e8f9f7 20183 #define PWM_BRKCTL_LVDBKEN_Msk (0x1ul << PWM_BRKCTL_LVDBKEN_Pos) /*!< PWM BRKCTL: LVDBKEN Mask */
<> 144:ef7eb2e8f9f7 20184
<> 144:ef7eb2e8f9f7 20185 #define PWM_BRKCTL_BKOD_Pos (24) /*!< PWM BRKCTL: BKOD Position */
<> 144:ef7eb2e8f9f7 20186 #define PWM_BRKCTL_BKOD_Msk (0x3ful << PWM_BRKCTL_BKOD_Pos) /*!< PWM BRKCTL: BKOD Mask */
<> 144:ef7eb2e8f9f7 20187
<> 144:ef7eb2e8f9f7 20188 #define PWM_INTCTL_PINTTYPE_Pos (0) /*!< PWM INTCTL: PINTTYPE Position */
<> 144:ef7eb2e8f9f7 20189 #define PWM_INTCTL_PINTTYPE_Msk (0x3ful << PWM_INTCTL_PINTTYPE_Pos) /*!< PWM INTCTL: PINTTYPE Mask */
<> 144:ef7eb2e8f9f7 20190
<> 144:ef7eb2e8f9f7 20191 #define PWM_INTCTL_DINTTYPE_Pos (8) /*!< PWM INTCTL: DINTTYPE Position */
<> 144:ef7eb2e8f9f7 20192 #define PWM_INTCTL_DINTTYPE_Msk (0x3ful << PWM_INTCTL_DINTTYPE_Pos) /*!< PWM INTCTL: DINTTYPE Mask */
<> 144:ef7eb2e8f9f7 20193
<> 144:ef7eb2e8f9f7 20194 #define PWM_INTEN_PIEN_Pos (0) /*!< PWM INTEN: PIEN Position */
<> 144:ef7eb2e8f9f7 20195 #define PWM_INTEN_PIEN_Msk (0x3ful << PWM_INTEN_PIEN_Pos) /*!< PWM INTEN: PIEN Mask */
<> 144:ef7eb2e8f9f7 20196
<> 144:ef7eb2e8f9f7 20197 #define PWM_INTEN_BRKIEN_Pos (6) /*!< PWM INTEN: BRKIEN Position */
<> 144:ef7eb2e8f9f7 20198 #define PWM_INTEN_BRKIEN_Msk (0x1ul << PWM_INTEN_BRKIEN_Pos) /*!< PWM INTEN: BRKIEN Mask */
<> 144:ef7eb2e8f9f7 20199
<> 144:ef7eb2e8f9f7 20200 #define PWM_INTEN_DIEN_Pos (8) /*!< PWM INTEN: DIEN Position */
<> 144:ef7eb2e8f9f7 20201 #define PWM_INTEN_DIEN_Msk (0x3ful << PWM_INTEN_DIEN_Pos) /*!< PWM INTEN: DIEN Mask */
<> 144:ef7eb2e8f9f7 20202
<> 144:ef7eb2e8f9f7 20203 #define PWM_INTEN_RLIEN_Pos (16) /*!< PWM INTEN: RLIEN Position */
<> 144:ef7eb2e8f9f7 20204 #define PWM_INTEN_RLIEN_Msk (0x3ful << PWM_INTEN_RLIEN_Pos) /*!< PWM INTEN: RLIEN Mask */
<> 144:ef7eb2e8f9f7 20205
<> 144:ef7eb2e8f9f7 20206 #define PWM_INTEN_FLIEN_Pos (24) /*!< PWM INTEN: FLIEN Position */
<> 144:ef7eb2e8f9f7 20207 #define PWM_INTEN_FLIEN_Msk (0x3ful << PWM_INTEN_FLIEN_Pos) /*!< PWM INTEN: FLIEN Mask */
<> 144:ef7eb2e8f9f7 20208
<> 144:ef7eb2e8f9f7 20209 #define PWM_INTSTS_PIF_Pos (0) /*!< PWM INTSTS: PIF Position */
<> 144:ef7eb2e8f9f7 20210 #define PWM_INTSTS_PIF_Msk (0x3ful << PWM_INTSTS_PIF_Pos) /*!< PWM INTSTS: PIF Mask */
<> 144:ef7eb2e8f9f7 20211
<> 144:ef7eb2e8f9f7 20212 #define PWM_INTSTS_BRKIF0_Pos (6) /*!< PWM INTSTS: BRKIF0 Position */
<> 144:ef7eb2e8f9f7 20213 #define PWM_INTSTS_BRKIF0_Msk (0x1ul << PWM_INTSTS_BRKIF0_Pos) /*!< PWM INTSTS: BRKIF0 Mask */
<> 144:ef7eb2e8f9f7 20214
<> 144:ef7eb2e8f9f7 20215 #define PWM_INTSTS_BRKIF1_Pos (7) /*!< PWM INTSTS: BRKIF1 Position */
<> 144:ef7eb2e8f9f7 20216 #define PWM_INTSTS_BRKIF1_Msk (0x1ul << PWM_INTSTS_BRKIF1_Pos) /*!< PWM INTSTS: BRKIF1 Mask */
<> 144:ef7eb2e8f9f7 20217
<> 144:ef7eb2e8f9f7 20218 #define PWM_INTSTS_DIF_Pos (8) /*!< PWM INTSTS: DIF Position */
<> 144:ef7eb2e8f9f7 20219 #define PWM_INTSTS_DIF_Msk (0x3ful << PWM_INTSTS_DIF_Pos) /*!< PWM INTSTS: DIF Mask */
<> 144:ef7eb2e8f9f7 20220
<> 144:ef7eb2e8f9f7 20221 #define PWM_INTSTS_BRKLK0_Pos (14) /*!< PWM INTSTS: BRKLK0 Position */
<> 144:ef7eb2e8f9f7 20222 #define PWM_INTSTS_BRKLK0_Msk (0x1ul << PWM_INTSTS_BRKLK0_Pos) /*!< PWM INTSTS: BRKLK0 Mask */
<> 144:ef7eb2e8f9f7 20223
<> 144:ef7eb2e8f9f7 20224 #define PWM_INTSTS_CRLIF_Pos (16) /*!< PWM INTSTS: CRLIF Position */
<> 144:ef7eb2e8f9f7 20225 #define PWM_INTSTS_CRLIF_Msk (0x3ful << PWM_INTSTS_CRLIF_Pos) /*!< PWM INTSTS: CRLIF Mask */
<> 144:ef7eb2e8f9f7 20226
<> 144:ef7eb2e8f9f7 20227 #define PWM_INTSTS_BRKSTS0_Pos (22) /*!< PWM INTSTS: BRKSTS0 Position */
<> 144:ef7eb2e8f9f7 20228 #define PWM_INTSTS_BRKSTS0_Msk (0x1ul << PWM_INTSTS_BRKSTS0_Pos) /*!< PWM INTSTS: BRKSTS0 Mask */
<> 144:ef7eb2e8f9f7 20229
<> 144:ef7eb2e8f9f7 20230 #define PWM_INTSTS_BRKSTS1_Pos (23) /*!< PWM INTSTS: BRKSTS1 Position */
<> 144:ef7eb2e8f9f7 20231 #define PWM_INTSTS_BRKSTS1_Msk (0x1ul << PWM_INTSTS_BRKSTS1_Pos) /*!< PWM INTSTS: BRKSTS1 Mask */
<> 144:ef7eb2e8f9f7 20232
<> 144:ef7eb2e8f9f7 20233 #define PWM_INTSTS_CFLIF_Pos (24) /*!< PWM INTSTS: CFLIF Position */
<> 144:ef7eb2e8f9f7 20234 #define PWM_INTSTS_CFLIF_Msk (0x3ful << PWM_INTSTS_CFLIF_Pos) /*!< PWM INTSTS: CFLIF Mask */
<> 144:ef7eb2e8f9f7 20235
<> 144:ef7eb2e8f9f7 20236 #define PWM_POEN_POEN_Pos (0) /*!< PWM POEN: POEN Position */
<> 144:ef7eb2e8f9f7 20237 #define PWM_POEN_POEN_Msk (0x3ful << PWM_POEN_POEN_Pos) /*!< PWM POEN: POEN Mask */
<> 144:ef7eb2e8f9f7 20238
<> 144:ef7eb2e8f9f7 20239 #define PWM_CAPCTL_CAPEN_Pos (0) /*!< PWM CAPCTL: CAPEN Position */
<> 144:ef7eb2e8f9f7 20240 #define PWM_CAPCTL_CAPEN_Msk (0x3ful << PWM_CAPCTL_CAPEN_Pos) /*!< PWM CAPCTL: CAPEN Mask */
<> 144:ef7eb2e8f9f7 20241
<> 144:ef7eb2e8f9f7 20242 #define PWM_CAPCTL_CAPINV_Pos (8) /*!< PWM CAPCTL: CAPINV Position */
<> 144:ef7eb2e8f9f7 20243 #define PWM_CAPCTL_CAPINV_Msk (0x3ful << PWM_CAPCTL_CAPINV_Pos) /*!< PWM CAPCTL: CAPINV Mask */
<> 144:ef7eb2e8f9f7 20244
<> 144:ef7eb2e8f9f7 20245 #define PWM_CAPCTL_RCRLDEN_Pos (16) /*!< PWM CAPCTL: RCRLDEN Position */
<> 144:ef7eb2e8f9f7 20246 #define PWM_CAPCTL_RCRLDEN_Msk (0x3ful << PWM_CAPCTL_RCRLDEN_Pos) /*!< PWM CAPCTL: RCRLDEN Mask */
<> 144:ef7eb2e8f9f7 20247
<> 144:ef7eb2e8f9f7 20248 #define PWM_CAPCTL_FCRLDEN_Pos (24) /*!< PWM CAPCTL: FCRLDEN Position */
<> 144:ef7eb2e8f9f7 20249 #define PWM_CAPCTL_FCRLDEN_Msk (0x3ful << PWM_CAPCTL_FCRLDEN_Pos) /*!< PWM CAPCTL: FCRLDEN Mask */
<> 144:ef7eb2e8f9f7 20250
<> 144:ef7eb2e8f9f7 20251 #define PWM_CAPINEN_CAPINEN_Pos (0) /*!< PWM CAPINEN: CAPINEN Position */
<> 144:ef7eb2e8f9f7 20252 #define PWM_CAPINEN_CAPINEN_Msk (0x3ful << PWM_CAPINEN_CAPINEN_Pos) /*!< PWM CAPINEN: CAPINEN Mask */
<> 144:ef7eb2e8f9f7 20253
<> 144:ef7eb2e8f9f7 20254 #define PWM_CAPSTS_CRIFOV_Pos (0) /*!< PWM CAPSTS: CRIFOV Position */
<> 144:ef7eb2e8f9f7 20255 #define PWM_CAPSTS_CRIFOV_Msk (0x3ful << PWM_CAPSTS_CRIFOV_Pos) /*!< PWM CAPSTS: CRIFOV Mask */
<> 144:ef7eb2e8f9f7 20256
<> 144:ef7eb2e8f9f7 20257 #define PWM_CAPSTS_FLIFOV_Pos (8) /*!< PWM CAPSTS: FLIFOV Position */
<> 144:ef7eb2e8f9f7 20258 #define PWM_CAPSTS_FLIFOV_Msk (0x3ful << PWM_CAPSTS_FLIFOV_Pos) /*!< PWM CAPSTS: FLIFOV Mask */
<> 144:ef7eb2e8f9f7 20259
<> 144:ef7eb2e8f9f7 20260 #define PWM_RCAPDAT0_RCAPDAT_Pos (0) /*!< PWM RCAPDAT0: RCAPDAT Position */
<> 144:ef7eb2e8f9f7 20261 #define PWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT0_RCAPDAT_Pos) /*!< PWM RCAPDAT0: RCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20262
<> 144:ef7eb2e8f9f7 20263 #define PWM_FCAPDAT0_FCAPDAT_Pos (0) /*!< PWM FCAPDAT0: FCAPDAT Position */
<> 144:ef7eb2e8f9f7 20264 #define PWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT0_FCAPDAT_Pos) /*!< PWM FCAPDAT0: FCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20265
<> 144:ef7eb2e8f9f7 20266 #define PWM_RCAPDAT1_RCAPDAT_Pos (0) /*!< PWM RCAPDAT1: RCAPDAT Position */
<> 144:ef7eb2e8f9f7 20267 #define PWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT1_RCAPDAT_Pos) /*!< PWM RCAPDAT1: RCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20268
<> 144:ef7eb2e8f9f7 20269 #define PWM_FCAPDAT1_FCAPDAT_Pos (0) /*!< PWM FCAPDAT1: FCAPDAT Position */
<> 144:ef7eb2e8f9f7 20270 #define PWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT1_FCAPDAT_Pos) /*!< PWM FCAPDAT1: FCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20271
<> 144:ef7eb2e8f9f7 20272 #define PWM_RCAPDAT2_RCAPDAT_Pos (0) /*!< PWM RCAPDAT2: RCAPDAT Position */
<> 144:ef7eb2e8f9f7 20273 #define PWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT2_RCAPDAT_Pos) /*!< PWM RCAPDAT2: RCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20274
<> 144:ef7eb2e8f9f7 20275 #define PWM_FCAPDAT2_FCAPDAT_Pos (0) /*!< PWM FCAPDAT2: FCAPDAT Position */
<> 144:ef7eb2e8f9f7 20276 #define PWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT2_FCAPDAT_Pos) /*!< PWM FCAPDAT2: FCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20277
<> 144:ef7eb2e8f9f7 20278 #define PWM_RCAPDAT3_RCAPDAT_Pos (0) /*!< PWM RCAPDAT3: RCAPDAT Position */
<> 144:ef7eb2e8f9f7 20279 #define PWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT3_RCAPDAT_Pos) /*!< PWM RCAPDAT3: RCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20280
<> 144:ef7eb2e8f9f7 20281 #define PWM_FCAPDAT3_FCAPDAT_Pos (0) /*!< PWM FCAPDAT3: FCAPDAT Position */
<> 144:ef7eb2e8f9f7 20282 #define PWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT3_FCAPDAT_Pos) /*!< PWM FCAPDAT3: FCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20283
<> 144:ef7eb2e8f9f7 20284 #define PWM_RCAPDAT4_RCAPDAT_Pos (0) /*!< PWM RCAPDAT4: RCAPDAT Position */
<> 144:ef7eb2e8f9f7 20285 #define PWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT4_RCAPDAT_Pos) /*!< PWM RCAPDAT4: RCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20286
<> 144:ef7eb2e8f9f7 20287 #define PWM_FCAPDAT4_FCAPDAT_Pos (0) /*!< PWM FCAPDAT4: FCAPDAT Position */
<> 144:ef7eb2e8f9f7 20288 #define PWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT4_FCAPDAT_Pos) /*!< PWM FCAPDAT4: FCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20289
<> 144:ef7eb2e8f9f7 20290 #define PWM_RCAPDAT5_RCAPDAT_Pos (0) /*!< PWM RCAPDAT5: RCAPDAT Position */
<> 144:ef7eb2e8f9f7 20291 #define PWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << PWM_RCAPDAT5_RCAPDAT_Pos) /*!< PWM RCAPDAT5: RCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20292
<> 144:ef7eb2e8f9f7 20293 #define PWM_FCAPDAT5_FCAPDAT_Pos (0) /*!< PWM FCAPDAT5: FCAPDAT Position */
<> 144:ef7eb2e8f9f7 20294 #define PWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << PWM_FCAPDAT5_FCAPDAT_Pos) /*!< PWM FCAPDAT5: FCAPDAT Mask */
<> 144:ef7eb2e8f9f7 20295
<> 144:ef7eb2e8f9f7 20296 #define PWM_SBS0_SYNCBUSY_Pos (0) /*!< PWM SBS0: SYNCBUSY Position */
<> 144:ef7eb2e8f9f7 20297 #define PWM_SBS0_SYNCBUSY_Msk (0x1ul << PWM_SBS0_SYNCBUSY_Pos) /*!< PWM SBS0: SYNCBUSY Mask */
<> 144:ef7eb2e8f9f7 20298
<> 144:ef7eb2e8f9f7 20299 #define PWM_SBS1_SYNCBUSY_Pos (0) /*!< PWM SBS1: SYNCBUSY Position */
<> 144:ef7eb2e8f9f7 20300 #define PWM_SBS1_SYNCBUSY_Msk (0x1ul << PWM_SBS1_SYNCBUSY_Pos) /*!< PWM SBS1: SYNCBUSY Mask */
<> 144:ef7eb2e8f9f7 20301
<> 144:ef7eb2e8f9f7 20302 #define PWM_SBS2_SYNCBUSY_Pos (0) /*!< PWM SBS2: SYNCBUSY Position */
<> 144:ef7eb2e8f9f7 20303 #define PWM_SBS2_SYNCBUSY_Msk (0x1ul << PWM_SBS2_SYNCBUSY_Pos) /*!< PWM SBS2: SYNCBUSY Mask */
<> 144:ef7eb2e8f9f7 20304
<> 144:ef7eb2e8f9f7 20305 #define PWM_SBS3_SYNCBUSY_Pos (0) /*!< PWM SBS3: SYNCBUSY Position */
<> 144:ef7eb2e8f9f7 20306 #define PWM_SBS3_SYNCBUSY_Msk (0x1ul << PWM_SBS3_SYNCBUSY_Pos) /*!< PWM SBS3: SYNCBUSY Mask */
<> 144:ef7eb2e8f9f7 20307
<> 144:ef7eb2e8f9f7 20308 #define PWM_SBS4_SYNCBUSY_Pos (0) /*!< PWM SBS4: SYNCBUSY Position */
<> 144:ef7eb2e8f9f7 20309 #define PWM_SBS4_SYNCBUSY_Msk (0x1ul << PWM_SBS4_SYNCBUSY_Pos) /*!< PWM SBS4: SYNCBUSY Mask */
<> 144:ef7eb2e8f9f7 20310
<> 144:ef7eb2e8f9f7 20311 #define PWM_SBS5_SYNCBUSY_Pos (0) /*!< PWM SBS5: SYNCBUSY Position */
<> 144:ef7eb2e8f9f7 20312 #define PWM_SBS5_SYNCBUSY_Msk (0x1ul << PWM_SBS5_SYNCBUSY_Pos) /*!< PWM SBS5: SYNCBUSY Mask */
<> 144:ef7eb2e8f9f7 20313
<> 144:ef7eb2e8f9f7 20314 /**@}*/ /* PWM_CONST */
<> 144:ef7eb2e8f9f7 20315 /**@}*/ /* end of PWM register group */
<> 144:ef7eb2e8f9f7 20316
<> 144:ef7eb2e8f9f7 20317
<> 144:ef7eb2e8f9f7 20318 /*---------------------- Quadrature Encoder Interface -------------------------*/
<> 144:ef7eb2e8f9f7 20319 /**
<> 144:ef7eb2e8f9f7 20320 @addtogroup QEI Quadrature Encoder Interface(QEI)
<> 144:ef7eb2e8f9f7 20321 Memory Mapped Structure for QEI Controller
<> 144:ef7eb2e8f9f7 20322 @{ */
<> 144:ef7eb2e8f9f7 20323
<> 144:ef7eb2e8f9f7 20324 typedef struct {
<> 144:ef7eb2e8f9f7 20325
<> 144:ef7eb2e8f9f7 20326
<> 144:ef7eb2e8f9f7 20327 /**
<> 144:ef7eb2e8f9f7 20328 * CNT
<> 144:ef7eb2e8f9f7 20329 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20330 * Offset: 0x00 QEI Pulse Counter
<> 144:ef7eb2e8f9f7 20331 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20332 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20333 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20334 * |[0:31] |VAL |Quadrature Encoder Pulse Counter
<> 144:ef7eb2e8f9f7 20335 * | | |A 32-bit up/down counter.
<> 144:ef7eb2e8f9f7 20336 * | | |When an effective phase pulse is detected, this counter is increased by one if the bit DIRF (QEI_STATUS[27]) is one or decreased by one if the bit DIRF is zero.
<> 144:ef7eb2e8f9f7 20337 * | | |This register performs an integrator which count value is proportional to the encoder position.
<> 144:ef7eb2e8f9f7 20338 * | | |The pulse counter may be initialized to a predetermined value by one of three events occurs:.
<> 144:ef7eb2e8f9f7 20339 * | | |1. Software written if QEIEN (QEI_CTR[29]) = 0.
<> 144:ef7eb2e8f9f7 20340 * | | |2. Compare-match event if QEIEN=1 and QEI is in compare-counting mode.
<> 144:ef7eb2e8f9f7 20341 * | | |3. Index signal change if QEIEN=1 and IDXRLDEN (QEI_CTR[27])=1.
<> 144:ef7eb2e8f9f7 20342 */
<> 144:ef7eb2e8f9f7 20343 __IO uint32_t CNT;
<> 144:ef7eb2e8f9f7 20344
<> 144:ef7eb2e8f9f7 20345 /**
<> 144:ef7eb2e8f9f7 20346 * CNTHOLD
<> 144:ef7eb2e8f9f7 20347 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20348 * Offset: 0x04 QEI Pulse Counter Hold Register
<> 144:ef7eb2e8f9f7 20349 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20350 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20351 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20352 * |[0:31] |VAL |Quadrature Encoder Pulse Counter Hold Register
<> 144:ef7eb2e8f9f7 20353 * | | |When bit HOLDCNT (QEIx_CTR[24]) goes from low to high, the QEI_CNT value is copied into QEI_CNTHOLD register.
<> 144:ef7eb2e8f9f7 20354 */
<> 144:ef7eb2e8f9f7 20355 __IO uint32_t CNTHOLD;
<> 144:ef7eb2e8f9f7 20356
<> 144:ef7eb2e8f9f7 20357 /**
<> 144:ef7eb2e8f9f7 20358 * CNTLATCH
<> 144:ef7eb2e8f9f7 20359 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20360 * Offset: 0x08 QEI Pulse Counter Index Latch Register
<> 144:ef7eb2e8f9f7 20361 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20362 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20363 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20364 * |[0:31] |VAL |Quadrature Encoder Pulse Counter Index Latch
<> 144:ef7eb2e8f9f7 20365 * | | |When the IDXF (QEI_STATUS[18]) bit is set, the QEI_CNT value is copied into QEI_CNTLATCH register.
<> 144:ef7eb2e8f9f7 20366 */
<> 144:ef7eb2e8f9f7 20367 __IO uint32_t CNTLATCH;
<> 144:ef7eb2e8f9f7 20368
<> 144:ef7eb2e8f9f7 20369 /**
<> 144:ef7eb2e8f9f7 20370 * CNTCMP
<> 144:ef7eb2e8f9f7 20371 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20372 * Offset: 0x0C QEI Pulse Counter Compare Register
<> 144:ef7eb2e8f9f7 20373 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20374 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20375 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20376 * |[0:31] |VAL |Quadrature Encoder Pulse Counter Compare
<> 144:ef7eb2e8f9f7 20377 * | | |if the QEI controller is in the compare-counting mode CMPENN (QEI_CTR[28]) =1, when the value of QEI_CNT matches the value of VAL the bit CMPF will be set.
<> 144:ef7eb2e8f9f7 20378 * | | |This register is software writable.
<> 144:ef7eb2e8f9f7 20379 */
<> 144:ef7eb2e8f9f7 20380 __IO uint32_t CNTCMP;
<> 144:ef7eb2e8f9f7 20381 uint32_t RESERVE0[1];
<> 144:ef7eb2e8f9f7 20382
<> 144:ef7eb2e8f9f7 20383
<> 144:ef7eb2e8f9f7 20384 /**
<> 144:ef7eb2e8f9f7 20385 * MAXCNT
<> 144:ef7eb2e8f9f7 20386 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20387 * Offset: 0x14 QEI Pre-set Maximum Count Register
<> 144:ef7eb2e8f9f7 20388 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20389 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20390 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20391 * |[0:31] |VAL |Quadrature Encoder Preset Maximum Count
<> 144:ef7eb2e8f9f7 20392 * | | |This register value determined by user stores the maximum value which may be the number of the quadrature encoder pulses in a revolution for the QEI controller compare-counting mode
<> 144:ef7eb2e8f9f7 20393 */
<> 144:ef7eb2e8f9f7 20394 __IO uint32_t CNTMAX;
<> 144:ef7eb2e8f9f7 20395
<> 144:ef7eb2e8f9f7 20396 /**
<> 144:ef7eb2e8f9f7 20397 * CTR
<> 144:ef7eb2e8f9f7 20398 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20399 * Offset: 0x18 QEI Controller Control Register
<> 144:ef7eb2e8f9f7 20400 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20401 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20402 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20403 * |[0:1] |NFCLKSEL |Noise Filter Clock Pre-Divide Selection
<> 144:ef7eb2e8f9f7 20404 * | | |To determine the sampling frequency of the Noise Filter clock .
<> 144:ef7eb2e8f9f7 20405 * | | |00 = QEI_CLK.
<> 144:ef7eb2e8f9f7 20406 * | | |01 = QEI_CLK/2.
<> 144:ef7eb2e8f9f7 20407 * | | |10 = QEI_CLK/4.
<> 144:ef7eb2e8f9f7 20408 * | | |11 = QEI_CLK/16.
<> 144:ef7eb2e8f9f7 20409 * |[3] |NFDIS |QEI Controller Input Noise Filter Disable Control
<> 144:ef7eb2e8f9f7 20410 * | | |0 = The noise filter of QEI controller Enabled.
<> 144:ef7eb2e8f9f7 20411 * | | |1 = The noise filter of QEI controller Disabled.
<> 144:ef7eb2e8f9f7 20412 * |[4] |CHAEN |QEA Input To QEI Controller Enable Control
<> 144:ef7eb2e8f9f7 20413 * | | |0 = QEA input to QEI Controller Disabled.
<> 144:ef7eb2e8f9f7 20414 * | | |1 = QEA input to QEI Controller Enabled.
<> 144:ef7eb2e8f9f7 20415 * |[5] |CHBEN |QEB Input To QEI Controller Enable Control
<> 144:ef7eb2e8f9f7 20416 * | | |0 = QEB input to QEI Controller Disabled.
<> 144:ef7eb2e8f9f7 20417 * | | |1 = QEB input to QEI Controller Enabled.
<> 144:ef7eb2e8f9f7 20418 * |[6] |IDXEN |IDX Input To QEI Controller Enable Control
<> 144:ef7eb2e8f9f7 20419 * | | |0 = IDX input to QEI Controller Disabled.
<> 144:ef7eb2e8f9f7 20420 * | | |1 = IDX input to QEI Controller Enabled.
<> 144:ef7eb2e8f9f7 20421 * |[8:9] |MODE |QEI Counting Mode Selection
<> 144:ef7eb2e8f9f7 20422 * | | |There are four quadrature encoder pulse counter operation modes.
<> 144:ef7eb2e8f9f7 20423 * | | |00 = X4 Free-counting Mode.
<> 144:ef7eb2e8f9f7 20424 * | | |01 = X2 Free-counting Mode.
<> 144:ef7eb2e8f9f7 20425 * | | |10 = X4 Compare-counting Mode.
<> 144:ef7eb2e8f9f7 20426 * | | |11 = X2 Compare-counting Mode.
<> 144:ef7eb2e8f9f7 20427 * |[12] |CHAINV |Inverse QEA Input Polarity
<> 144:ef7eb2e8f9f7 20428 * | | |0 = Not inverse QEA input polarity.
<> 144:ef7eb2e8f9f7 20429 * | | |1 = QEA input polarity is inversed to QEI controller.
<> 144:ef7eb2e8f9f7 20430 * |[13] |CHBINV |Inverse QEB Input Polarity
<> 144:ef7eb2e8f9f7 20431 * | | |0 = Not inverse QEB input polarity.
<> 144:ef7eb2e8f9f7 20432 * | | |1 = QEB input polarity is inversed to QEI controller.
<> 144:ef7eb2e8f9f7 20433 * |[14] |IDXINV |Inverse IDX Input Polarity
<> 144:ef7eb2e8f9f7 20434 * | | |0 = Not inverse IDX input polarity.
<> 144:ef7eb2e8f9f7 20435 * | | |1 = IDX input polarity is inversed to QEI controller.
<> 144:ef7eb2e8f9f7 20436 * |[16] |OVUNIEN |OVUNF Trigger QEI Interrupt Enable Control
<> 144:ef7eb2e8f9f7 20437 * | | |0 = OVUNF can trigger QEI controller interrupt Disabled.
<> 144:ef7eb2e8f9f7 20438 * | | |1 = OVUNF can trigger QEI controller interrupt Enabled.
<> 144:ef7eb2e8f9f7 20439 * |[17] |DIRIEN |DIRCHGF Trigger QEI Interrupt Enable Control
<> 144:ef7eb2e8f9f7 20440 * | | |0 = DIRCHGF can trigger QEI controller interrupt Disabled.
<> 144:ef7eb2e8f9f7 20441 * | | |1 = DIRCHGF can trigger QEI controller interrupt Enabled.
<> 144:ef7eb2e8f9f7 20442 * |[18] |CMPIEN |CMPF Trigger QEI Interrupt Enable Control
<> 144:ef7eb2e8f9f7 20443 * | | |0 = CMPF can trigger QEI controller interrupt Disabled.
<> 144:ef7eb2e8f9f7 20444 * | | |1 = CMPF can trigger QEI controller interrupt Enabled.
<> 144:ef7eb2e8f9f7 20445 * |[19] |IDXIEN |IDXF Trigger QEI Interrupt Enable Control
<> 144:ef7eb2e8f9f7 20446 * | | |0 = The IDXF can trigger QEI interrupt Disabled.
<> 144:ef7eb2e8f9f7 20447 * | | |1 = The IDXF can trigger QEI interrupt Enabled.
<> 144:ef7eb2e8f9f7 20448 * |[20] |HOLDTMR0 |Hold QEI_CNT By Timer 0
<> 144:ef7eb2e8f9f7 20449 * | | |0 = TIF (TISR0[0]) has no effect on HOLDCNT.
<> 144:ef7eb2e8f9f7 20450 * | | |1 = A rising edge of bit TIF (TISR0[0]) in timer 0 sets HOLDCNT to 1.
<> 144:ef7eb2e8f9f7 20451 * |[21] |HOLDTMR1 |Hold QEI_CNT By Timer 1
<> 144:ef7eb2e8f9f7 20452 * | | |0 = TIF (TISR1[0]) has no effect on HOLDCNT.
<> 144:ef7eb2e8f9f7 20453 * | | |1 = A rising edge of bit TIF (TISR1[0]) in timer 1 sets HOLDCNT to 1.
<> 144:ef7eb2e8f9f7 20454 * |[22] |HOLDTMR2 |Hold QEI_CNT By Timer 2
<> 144:ef7eb2e8f9f7 20455 * | | |0 = TIF (TISR2[0]) has no effect on HOLDCNT.
<> 144:ef7eb2e8f9f7 20456 * | | |1 = A rising edge of bit TIF (TISR2[0]) in timer 2 sets HOLDCNT to 1.
<> 144:ef7eb2e8f9f7 20457 * |[23] |HOLDTMR3 |Hold QEI_CNT By Timer 3
<> 144:ef7eb2e8f9f7 20458 * | | |0 = TIF (TISR3[0]) has no effect on HOLDCNT.
<> 144:ef7eb2e8f9f7 20459 * | | |1 = A rising edge of bit TIF (TISR3[0]) in timer 3 sets HOLDCNT to 1.
<> 144:ef7eb2e8f9f7 20460 * |[24] |HOLDCNT |Hold QEI_CNT Control
<> 144:ef7eb2e8f9f7 20461 * | | |When this bit is set from low to high, the QEI_CNT value is copied into QEI_CNTHOLD.
<> 144:ef7eb2e8f9f7 20462 * | | |This bit may be set by writing 1 to it or Timer0~Timer3 interrupt flag TIF (TISTRx[0]).
<> 144:ef7eb2e8f9f7 20463 * | | |0 = No operation.
<> 144:ef7eb2e8f9f7 20464 * | | |1 = QEI_CNT content is captured and stored in QEI_CNTHOLD.
<> 144:ef7eb2e8f9f7 20465 * | | |Note: This bit is automatically cleared after QEI_CNTHOLD holds QEI_CNT value.
<> 144:ef7eb2e8f9f7 20466 * |[25] |IDXLATEN |Index Latch QEI_CNT Enable Control
<> 144:ef7eb2e8f9f7 20467 * | | |If this bit is set to high, the QEI_CNT content will be latched into QEI_CNTLATCH at every rising on signal CHX.
<> 144:ef7eb2e8f9f7 20468 * | | |0 = The index signal latch QEI counter function Disabled.
<> 144:ef7eb2e8f9f7 20469 * | | |1 = The index signal latch QEI counter function Enabled.
<> 144:ef7eb2e8f9f7 20470 * |[27] |IDXRLDEN |Index Trigger QEI_CNT Reload Enable Control
<> 144:ef7eb2e8f9f7 20471 * | | |When this bit is high and a rising edge comes on signal CHX, the QEI_CNT will be reset to zero if the counter is in up-counting type (DIRF = 1); while the QEI_CNT will be reloaded with QEI_MAXCNT content if the counter is in down-counting type (DIRF = 0).
<> 144:ef7eb2e8f9f7 20472 * | | |0 = Reload function Disabled.
<> 144:ef7eb2e8f9f7 20473 * | | |1 = QEI_CNT re-initialized by Index signal Enabled.
<> 144:ef7eb2e8f9f7 20474 * |[28] |CMPENN |The Compare Function Enable Control
<> 144:ef7eb2e8f9f7 20475 * | | |The compare function in QEI controller is to compare the dynamic counting QEI_CNT with the compare register QEI_CNTCMP, if QEI_CNT value reaches QEI_CNTCMP, the flag CMPF will be set.
<> 144:ef7eb2e8f9f7 20476 * | | |0 = Compare function Disabled.
<> 144:ef7eb2e8f9f7 20477 * | | |1 = Compare function Enabled.
<> 144:ef7eb2e8f9f7 20478 * |[29] |QEIEN |Quadrature Encoder Interface Controller Enable Control
<> 144:ef7eb2e8f9f7 20479 * | | |0 = QEI controller function Disabled.
<> 144:ef7eb2e8f9f7 20480 * | | |1 = QEI controller function Enabled.
<> 144:ef7eb2e8f9f7 20481 */
<> 144:ef7eb2e8f9f7 20482 __IO uint32_t CTR;
<> 144:ef7eb2e8f9f7 20483 uint32_t RESERVE1[4];
<> 144:ef7eb2e8f9f7 20484
<> 144:ef7eb2e8f9f7 20485
<> 144:ef7eb2e8f9f7 20486 /**
<> 144:ef7eb2e8f9f7 20487 * STATUS
<> 144:ef7eb2e8f9f7 20488 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20489 * Offset: 0x2C QEI Controller Status Register
<> 144:ef7eb2e8f9f7 20490 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20491 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20492 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20493 * |[0] |IDXF |IDX Detected Flag
<> 144:ef7eb2e8f9f7 20494 * | | |When the QEI controller detects a rising edge on signal CHX it will set flag IDXF to high.
<> 144:ef7eb2e8f9f7 20495 * | | |0 = No rising edge detected on signal CHX.
<> 144:ef7eb2e8f9f7 20496 * | | |1 = A rising edge occurs on signal CHX.
<> 144:ef7eb2e8f9f7 20497 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 20498 * |[1] |CMPF |Compare-Match Flag
<> 144:ef7eb2e8f9f7 20499 * | | |If the QEI compare function is enabled, the flag is set by hardware while QEI counter up or down counts and reach to the QEI_CNTCMP value.
<> 144:ef7eb2e8f9f7 20500 * | | |0 = QEI counter does not match with QEI_CNTCMP value.
<> 144:ef7eb2e8f9f7 20501 * | | |1 = QEI counter counts to the same as QEI_CNTCMP value.
<> 144:ef7eb2e8f9f7 20502 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 20503 * |[2] |OVUNF |QEI Counter Overflow Or Underflow Flag
<> 144:ef7eb2e8f9f7 20504 * | | |Flag is set by hardware while QEI_CNT overflows from 0xFFFF_FFFF to zero in free-counting mode or from the QEI_MAXCNT value to zero in compare-counting mode.
<> 144:ef7eb2e8f9f7 20505 * | | |Similarly, the flag is set wile QEI counter underflows from zero to 0xFFFF_FFFF or QEI_MAXCNT.
<> 144:ef7eb2e8f9f7 20506 * | | |0 = No overflow or underflow occurs in QEI counter.
<> 144:ef7eb2e8f9f7 20507 * | | |1 = QEI counter occurs counting overflow or underflow.
<> 144:ef7eb2e8f9f7 20508 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 20509 * |[3] |DIRCHGF |Direction Change Flag
<> 144:ef7eb2e8f9f7 20510 * | | |Flag is set by hardware while QEI counter counting direction is changed.
<> 144:ef7eb2e8f9f7 20511 * | | |Software can clear this bit by writing 1 to it.
<> 144:ef7eb2e8f9f7 20512 * | | |0 = No change in QEI counter counting direction.
<> 144:ef7eb2e8f9f7 20513 * | | |1 = QEI counter counting direction is changed.
<> 144:ef7eb2e8f9f7 20514 * | | |Note: This bit is only cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 20515 * |[8] |DIRF |QEI Counter Counting Direction Indication
<> 144:ef7eb2e8f9f7 20516 * | | |0 = QEI Counter is in down-counting.
<> 144:ef7eb2e8f9f7 20517 * | | |1 = QEI Counter is in up-counting.
<> 144:ef7eb2e8f9f7 20518 * | | |Note: This bit is set/reset by hardware according to the phase detection between CHA and CHB.
<> 144:ef7eb2e8f9f7 20519 */
<> 144:ef7eb2e8f9f7 20520 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 20521
<> 144:ef7eb2e8f9f7 20522 } QEI_T;
<> 144:ef7eb2e8f9f7 20523
<> 144:ef7eb2e8f9f7 20524 /**
<> 144:ef7eb2e8f9f7 20525 @addtogroup QEI_CONST QEI Bit Field Definition
<> 144:ef7eb2e8f9f7 20526 Constant Definitions for QEI Controller
<> 144:ef7eb2e8f9f7 20527 @{ */
<> 144:ef7eb2e8f9f7 20528
<> 144:ef7eb2e8f9f7 20529 #define QEI_CNT_VAL_Pos (0) /*!< QEI CNT: VAL Position */
<> 144:ef7eb2e8f9f7 20530 #define QEI_CNT_VAL_Msk (0xfffffffful << QEI_CNT_VAL_Pos) /*!< QEI CNT: VAL Mask */
<> 144:ef7eb2e8f9f7 20531
<> 144:ef7eb2e8f9f7 20532 #define QEI_CNTHOLD_VAL_Pos (0) /*!< QEI CNTHOLD: VAL Position */
<> 144:ef7eb2e8f9f7 20533 #define QEI_CNTHOLD_VAL_Msk (0xfffffffful << QEI_CNTHOLD_VAL_Pos) /*!< QEI CNTHOLD: VAL Mask */
<> 144:ef7eb2e8f9f7 20534
<> 144:ef7eb2e8f9f7 20535 #define QEI_CNTLATCH_VAL_Pos (0) /*!< QEI CNTLATCH: VAL Position */
<> 144:ef7eb2e8f9f7 20536 #define QEI_CNTLATCH_VAL_Msk (0xfffffffful << QEI_CNTLATCH_VAL_Pos) /*!< QEI CNTLATCH: VAL Mask */
<> 144:ef7eb2e8f9f7 20537
<> 144:ef7eb2e8f9f7 20538 #define QEI_CNTCMP_VAL_Pos (0) /*!< QEI CNTCMP: VAL Position */
<> 144:ef7eb2e8f9f7 20539 #define QEI_CNTCMP_VAL_Msk (0xfffffffful << QEI_CNTCMP_VAL_Pos) /*!< QEI CNTCMP: VAL Mask */
<> 144:ef7eb2e8f9f7 20540
<> 144:ef7eb2e8f9f7 20541 #define QEI_CNTMAX_VAL_Pos (0) /*!< QEI CNTMAX: VAL Position */
<> 144:ef7eb2e8f9f7 20542 #define QEI_CNTMAX_VAL_Msk (0xfffffffful << QEI_CNTMAX_VAL_Pos) /*!< QEI CNTMAX: VAL Mask */
<> 144:ef7eb2e8f9f7 20543
<> 144:ef7eb2e8f9f7 20544 #define QEI_CTR_NFCLKSEL_Pos (0) /*!< QEI CTR: NFCLKSEL Position */
<> 144:ef7eb2e8f9f7 20545 #define QEI_CTR_NFCLKSEL_Msk (0x3ul << QEI_CTR_NFCLKSEL_Pos) /*!< QEI CTR: NFCLKSEL Mask */
<> 144:ef7eb2e8f9f7 20546
<> 144:ef7eb2e8f9f7 20547 #define QEI_CTR_NFDIS_Pos (3) /*!< QEI CTR: NFDIS Position */
<> 144:ef7eb2e8f9f7 20548 #define QEI_CTR_NFDIS_Msk (0x1ul << QEI_CTR_NFDIS_Pos) /*!< QEI CTR: NFDIS Mask */
<> 144:ef7eb2e8f9f7 20549
<> 144:ef7eb2e8f9f7 20550 #define QEI_CTR_CHAEN_Pos (4) /*!< QEI CTR: CHAEN Position */
<> 144:ef7eb2e8f9f7 20551 #define QEI_CTR_CHAEN_Msk (0x1ul << QEI_CTR_CHAEN_Pos) /*!< QEI CTR: CHAEN Mask */
<> 144:ef7eb2e8f9f7 20552
<> 144:ef7eb2e8f9f7 20553 #define QEI_CTR_CHBEN_Pos (5) /*!< QEI CTR: CHBEN Position */
<> 144:ef7eb2e8f9f7 20554 #define QEI_CTR_CHBEN_Msk (0x1ul << QEI_CTR_CHBEN_Pos) /*!< QEI CTR: CHBEN Mask */
<> 144:ef7eb2e8f9f7 20555
<> 144:ef7eb2e8f9f7 20556 #define QEI_CTR_IDXEN_Pos (6) /*!< QEI CTR: IDXEN Position */
<> 144:ef7eb2e8f9f7 20557 #define QEI_CTR_IDXEN_Msk (0x1ul << QEI_CTR_IDXEN_Pos) /*!< QEI CTR: IDXEN Mask */
<> 144:ef7eb2e8f9f7 20558
<> 144:ef7eb2e8f9f7 20559 #define QEI_CTR_MODE_Pos (8) /*!< QEI CTR: MODE Position */
<> 144:ef7eb2e8f9f7 20560 #define QEI_CTR_MODE_Msk (0x3ul << QEI_CTR_MODE_Pos) /*!< QEI CTR: MODE Mask */
<> 144:ef7eb2e8f9f7 20561
<> 144:ef7eb2e8f9f7 20562 #define QEI_CTR_CHAINV_Pos (12) /*!< QEI CTR: CHAINV Position */
<> 144:ef7eb2e8f9f7 20563 #define QEI_CTR_CHAINV_Msk (0x1ul << QEI_CTR_CHAINV_Pos) /*!< QEI CTR: CHAINV Mask */
<> 144:ef7eb2e8f9f7 20564
<> 144:ef7eb2e8f9f7 20565 #define QEI_CTR_CHBINV_Pos (13) /*!< QEI CTR: CHBINV Position */
<> 144:ef7eb2e8f9f7 20566 #define QEI_CTR_CHBINV_Msk (0x1ul << QEI_CTR_CHBINV_Pos) /*!< QEI CTR: CHBINV Mask */
<> 144:ef7eb2e8f9f7 20567
<> 144:ef7eb2e8f9f7 20568 #define QEI_CTR_IDXINV_Pos (14) /*!< QEI CTR: IDXINV Position */
<> 144:ef7eb2e8f9f7 20569 #define QEI_CTR_IDXINV_Msk (0x1ul << QEI_CTR_IDXINV_Pos) /*!< QEI CTR: IDXINV Mask */
<> 144:ef7eb2e8f9f7 20570
<> 144:ef7eb2e8f9f7 20571 #define QEI_CTR_OVUNIEN_Pos (16) /*!< QEI CTR: OVUNIEN Position */
<> 144:ef7eb2e8f9f7 20572 #define QEI_CTR_OVUNIEN_Msk (0x1ul << QEI_CTR_OVUNIEN_Pos) /*!< QEI CTR: OVUNIEN Mask */
<> 144:ef7eb2e8f9f7 20573
<> 144:ef7eb2e8f9f7 20574 #define QEI_CTR_DIRIEN_Pos (17) /*!< QEI CTR: DIRIEN Position */
<> 144:ef7eb2e8f9f7 20575 #define QEI_CTR_DIRIEN_Msk (0x1ul << QEI_CTR_DIRIEN_Pos) /*!< QEI CTR: DIRIEN Mask */
<> 144:ef7eb2e8f9f7 20576
<> 144:ef7eb2e8f9f7 20577 #define QEI_CTR_CMPIEN_Pos (18) /*!< QEI CTR: CMPIEN Position */
<> 144:ef7eb2e8f9f7 20578 #define QEI_CTR_CMPIEN_Msk (0x1ul << QEI_CTR_CMPIEN_Pos) /*!< QEI CTR: CMPIEN Mask */
<> 144:ef7eb2e8f9f7 20579
<> 144:ef7eb2e8f9f7 20580 #define QEI_CTR_IDXIEN_Pos (19) /*!< QEI CTR: IDXIEN Position */
<> 144:ef7eb2e8f9f7 20581 #define QEI_CTR_IDXIEN_Msk (0x1ul << QEI_CTR_IDXIEN_Pos) /*!< QEI CTR: IDXIEN Mask */
<> 144:ef7eb2e8f9f7 20582
<> 144:ef7eb2e8f9f7 20583 #define QEI_CTR_HOLDTMR0_Pos (20) /*!< QEI CTR: HOLDTMR0 Position */
<> 144:ef7eb2e8f9f7 20584 #define QEI_CTR_HOLDTMR0_Msk (0x1ul << QEI_CTR_HOLDTMR0_Pos) /*!< QEI CTR: HOLDTMR0 Mask */
<> 144:ef7eb2e8f9f7 20585
<> 144:ef7eb2e8f9f7 20586 #define QEI_CTR_HOLDTMR1_Pos (21) /*!< QEI CTR: HOLDTMR1 Position */
<> 144:ef7eb2e8f9f7 20587 #define QEI_CTR_HOLDTMR1_Msk (0x1ul << QEI_CTR_HOLDTMR1_Pos) /*!< QEI CTR: HOLDTMR1 Mask */
<> 144:ef7eb2e8f9f7 20588
<> 144:ef7eb2e8f9f7 20589 #define QEI_CTR_HOLDTMR2_Pos (22) /*!< QEI CTR: HOLDTMR2 Position */
<> 144:ef7eb2e8f9f7 20590 #define QEI_CTR_HOLDTMR2_Msk (0x1ul << QEI_CTR_HOLDTMR2_Pos) /*!< QEI CTR: HOLDTMR2 Mask */
<> 144:ef7eb2e8f9f7 20591
<> 144:ef7eb2e8f9f7 20592 #define QEI_CTR_HOLDTMR3_Pos (23) /*!< QEI CTR: HOLDTMR3 Position */
<> 144:ef7eb2e8f9f7 20593 #define QEI_CTR_HOLDTMR3_Msk (0x1ul << QEI_CTR_HOLDTMR3_Pos) /*!< QEI CTR: HOLDTMR3 Mask */
<> 144:ef7eb2e8f9f7 20594
<> 144:ef7eb2e8f9f7 20595 #define QEI_CTR_HOLDCNT_Pos (24) /*!< QEI CTR: HOLDCNT Position */
<> 144:ef7eb2e8f9f7 20596 #define QEI_CTR_HOLDCNT_Msk (0x1ul << QEI_CTR_HOLDCNT_Pos) /*!< QEI CTR: HOLDCNT Mask */
<> 144:ef7eb2e8f9f7 20597
<> 144:ef7eb2e8f9f7 20598 #define QEI_CTR_IDXLATEN_Pos (25) /*!< QEI CTR: IDXLATEN Position */
<> 144:ef7eb2e8f9f7 20599 #define QEI_CTR_IDXLATEN_Msk (0x1ul << QEI_CTR_IDXLATEN_Pos) /*!< QEI CTR: IDXLATEN Mask */
<> 144:ef7eb2e8f9f7 20600
<> 144:ef7eb2e8f9f7 20601 #define QEI_CTR_IDXRLDEN_Pos (27) /*!< QEI CTR: IDXRLDEN Position */
<> 144:ef7eb2e8f9f7 20602 #define QEI_CTR_IDXRLDEN_Msk (0x1ul << QEI_CTR_IDXRLDEN_Pos) /*!< QEI CTR: IDXRLDEN Mask */
<> 144:ef7eb2e8f9f7 20603
<> 144:ef7eb2e8f9f7 20604 #define QEI_CTR_CMPENN_Pos (28) /*!< QEI CTR: CMPENN Position */
<> 144:ef7eb2e8f9f7 20605 #define QEI_CTR_CMPENN_Msk (0x1ul << QEI_CTR_CMPENN_Pos) /*!< QEI CTR: CMPENN Mask */
<> 144:ef7eb2e8f9f7 20606
<> 144:ef7eb2e8f9f7 20607 #define QEI_CTR_QEIEN_Pos (29) /*!< QEI CTR: QEIEN Position */
<> 144:ef7eb2e8f9f7 20608 #define QEI_CTR_QEIEN_Msk (0x1ul << QEI_CTR_QEIEN_Pos) /*!< QEI CTR: QEIEN Mask */
<> 144:ef7eb2e8f9f7 20609
<> 144:ef7eb2e8f9f7 20610 #define QEI_STATUS_IDXF_Pos (0) /*!< QEI STATUS: IDXF Position */
<> 144:ef7eb2e8f9f7 20611 #define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) /*!< QEI STATUS: IDXF Mask */
<> 144:ef7eb2e8f9f7 20612
<> 144:ef7eb2e8f9f7 20613 #define QEI_STATUS_CMPF_Pos (1) /*!< QEI STATUS: CMPF Position */
<> 144:ef7eb2e8f9f7 20614 #define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) /*!< QEI STATUS: CMPF Mask */
<> 144:ef7eb2e8f9f7 20615
<> 144:ef7eb2e8f9f7 20616 #define QEI_STATUS_OVUNF_Pos (2) /*!< QEI STATUS: OVUNF Position */
<> 144:ef7eb2e8f9f7 20617 #define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) /*!< QEI STATUS: OVUNF Mask */
<> 144:ef7eb2e8f9f7 20618
<> 144:ef7eb2e8f9f7 20619 #define QEI_STATUS_DIRCHGF_Pos (3) /*!< QEI STATUS: DIRCHGF Position */
<> 144:ef7eb2e8f9f7 20620 #define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) /*!< QEI STATUS: DIRCHGF Mask */
<> 144:ef7eb2e8f9f7 20621
<> 144:ef7eb2e8f9f7 20622 #define QEI_STATUS_DIRF_Pos (8) /*!< QEI STATUS: DIRF Position */
<> 144:ef7eb2e8f9f7 20623 #define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) /*!< QEI STATUS: DIRF Mask */
<> 144:ef7eb2e8f9f7 20624
<> 144:ef7eb2e8f9f7 20625 /**@}*/ /* QEI_CONST */
<> 144:ef7eb2e8f9f7 20626 /**@}*/ /* end of QEI register group */
<> 144:ef7eb2e8f9f7 20627
<> 144:ef7eb2e8f9f7 20628
<> 144:ef7eb2e8f9f7 20629 /*---------------------- Real Time Clock Controller -------------------------*/
<> 144:ef7eb2e8f9f7 20630 /**
<> 144:ef7eb2e8f9f7 20631 @addtogroup RTC Real Time Clock Controller(RTC)
<> 144:ef7eb2e8f9f7 20632 Memory Mapped Structure for RTC Controller
<> 144:ef7eb2e8f9f7 20633 @{ */
<> 144:ef7eb2e8f9f7 20634
<> 144:ef7eb2e8f9f7 20635 typedef struct {
<> 144:ef7eb2e8f9f7 20636
<> 144:ef7eb2e8f9f7 20637 /**
<> 144:ef7eb2e8f9f7 20638 * INIT
<> 144:ef7eb2e8f9f7 20639 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20640 * Offset: 0x00 RTC Initiation Register
<> 144:ef7eb2e8f9f7 20641 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20642 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20643 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20644 * |[0] |INIT_Active|RTC Active Status (Read Only)
<> 144:ef7eb2e8f9f7 20645 * | | |0 = RTC is at reset state.
<> 144:ef7eb2e8f9f7 20646 * | | |1 = RTC is at normal active state.
<> 144:ef7eb2e8f9f7 20647 * |[1:31] |INIT |RTC Initiation
<> 144:ef7eb2e8f9f7 20648 * | | |When RTC block is powered on, RTC is at reset state.
<> 144:ef7eb2e8f9f7 20649 * | | |User has to write a number (0x a5eb1357) to INIT to make RTC leaving reset state.
<> 144:ef7eb2e8f9f7 20650 * | | |Once the INIT is written as 0xa5eb1357, the RTC will be in un-reset state permanently.
<> 144:ef7eb2e8f9f7 20651 * | | |The INIT is a write-only field and read value will be always "0".
<> 144:ef7eb2e8f9f7 20652 */
<> 144:ef7eb2e8f9f7 20653 __IO uint32_t INIT;
<> 144:ef7eb2e8f9f7 20654
<> 144:ef7eb2e8f9f7 20655 /**
<> 144:ef7eb2e8f9f7 20656 * RWEN
<> 144:ef7eb2e8f9f7 20657 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20658 * Offset: 0x04 RTC Access Enable Register
<> 144:ef7eb2e8f9f7 20659 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20660 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20661 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20662 * |[0:15] |RWEN |RTC Register Access Enable Password (Write Only)
<> 144:ef7eb2e8f9f7 20663 * | | |Writing 0xA965 to this register will enable RTC access and keep 1024 RTC clock.
<> 144:ef7eb2e8f9f7 20664 * |[16] |RWENF |RTC Register Access Enable Flag (Read Only)
<> 144:ef7eb2e8f9f7 20665 * | | |0 = RTC register read/write Disabled.
<> 144:ef7eb2e8f9f7 20666 * | | |1 = RTC register read/write Enabled.
<> 144:ef7eb2e8f9f7 20667 * | | |This bit will be set after RTC_RWEN[15:0] register is load a 0xA965, and be cleared automatically after 1024 RTC clock.
<> 144:ef7eb2e8f9f7 20668 */
<> 144:ef7eb2e8f9f7 20669 __O uint32_t RWEN;
<> 144:ef7eb2e8f9f7 20670
<> 144:ef7eb2e8f9f7 20671 /**
<> 144:ef7eb2e8f9f7 20672 * FREQADJ
<> 144:ef7eb2e8f9f7 20673 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20674 * Offset: 0x08 RTC Frequency Compensation Register
<> 144:ef7eb2e8f9f7 20675 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20676 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20677 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20678 * |[0:5] |FRACTION |Fraction Part
<> 144:ef7eb2e8f9f7 20679 * | | |Formula = (fraction part of detected value) x 60.
<> 144:ef7eb2e8f9f7 20680 * | | |Note: Digit in RTC_FREQADJ must be expressed as hexadecimal number.
<> 144:ef7eb2e8f9f7 20681 * |[8:11] |INTEGER |Integer Part
<> 144:ef7eb2e8f9f7 20682 */
<> 144:ef7eb2e8f9f7 20683 __IO uint32_t FREQADJ;
<> 144:ef7eb2e8f9f7 20684
<> 144:ef7eb2e8f9f7 20685 /**
<> 144:ef7eb2e8f9f7 20686 * TIME
<> 144:ef7eb2e8f9f7 20687 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20688 * Offset: 0x0C Time Loading Register
<> 144:ef7eb2e8f9f7 20689 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20690 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20691 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20692 * |[0:3] |SEC |1-Sec Time Digit (0~9)
<> 144:ef7eb2e8f9f7 20693 * |[4:6] |TENSEC |10-Sec Time Digit (0~5)
<> 144:ef7eb2e8f9f7 20694 * |[8:11] |MIN |1-Min Time Digit (0~9)
<> 144:ef7eb2e8f9f7 20695 * |[12:14] |TENMIN |10-Min Time Digit (0~5)
<> 144:ef7eb2e8f9f7 20696 * |[16:19] |HR |1-Hour Time Digit (0~9)
<> 144:ef7eb2e8f9f7 20697 * |[20:21] |TENHR |10-Hour Time Digit (0~2)
<> 144:ef7eb2e8f9f7 20698 */
<> 144:ef7eb2e8f9f7 20699 __IO uint32_t TIME;
<> 144:ef7eb2e8f9f7 20700
<> 144:ef7eb2e8f9f7 20701 /**
<> 144:ef7eb2e8f9f7 20702 * CAL
<> 144:ef7eb2e8f9f7 20703 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20704 * Offset: 0x10 Calendar Loading Register
<> 144:ef7eb2e8f9f7 20705 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20706 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20707 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20708 * |[0:3] |DAY |1-Day Calendar Digit (0~9)
<> 144:ef7eb2e8f9f7 20709 * |[4:5] |TENDAY |10-Day Calendar Digit (0~3)
<> 144:ef7eb2e8f9f7 20710 * |[8:11] |MON |1-Month Calendar Digit (0~9)
<> 144:ef7eb2e8f9f7 20711 * |[12] |TENMON |10-Month Calendar Digit (0~1)
<> 144:ef7eb2e8f9f7 20712 * |[16:19] |YEAR |1-Year Calendar Digit (0~9)
<> 144:ef7eb2e8f9f7 20713 * |[20:23] |TENYEAR |10-Year Calendar Digit (0~9)
<> 144:ef7eb2e8f9f7 20714 */
<> 144:ef7eb2e8f9f7 20715 __IO uint32_t CAL;
<> 144:ef7eb2e8f9f7 20716
<> 144:ef7eb2e8f9f7 20717 /**
<> 144:ef7eb2e8f9f7 20718 * CLKFMT
<> 144:ef7eb2e8f9f7 20719 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20720 * Offset: 0x14 Time Scale Selection Register
<> 144:ef7eb2e8f9f7 20721 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20722 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20723 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20724 * |[0] |24HEN |24-Hour / 12-Hour Time Scale Selection
<> 144:ef7eb2e8f9f7 20725 * | | |Indicates that RTC_TIME and RTC_TALM are in 24-hour time scale or 12-hour time scale
<> 144:ef7eb2e8f9f7 20726 * | | |0 = 12-hour time scale with AM and PM indication selected.
<> 144:ef7eb2e8f9f7 20727 * | | |1 = 24-hour time scale selected.
<> 144:ef7eb2e8f9f7 20728 */
<> 144:ef7eb2e8f9f7 20729 __IO uint32_t CLKFMT;
<> 144:ef7eb2e8f9f7 20730
<> 144:ef7eb2e8f9f7 20731 /**
<> 144:ef7eb2e8f9f7 20732 * WEEKDAY
<> 144:ef7eb2e8f9f7 20733 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20734 * Offset: 0x18 Day of the Week Register
<> 144:ef7eb2e8f9f7 20735 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20736 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20737 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20738 * |[0:2] |WEEKDAY |Day Of The Week Bits
<> 144:ef7eb2e8f9f7 20739 * | | |000 = Sunday.
<> 144:ef7eb2e8f9f7 20740 * | | |001 = Monday.
<> 144:ef7eb2e8f9f7 20741 * | | |010 = Tuesday.
<> 144:ef7eb2e8f9f7 20742 * | | |011 = Wednesday.
<> 144:ef7eb2e8f9f7 20743 * | | |100 = Thursday.
<> 144:ef7eb2e8f9f7 20744 * | | |101 = Friday.
<> 144:ef7eb2e8f9f7 20745 * | | |110 = Saturday.
<> 144:ef7eb2e8f9f7 20746 * | | |111 = Reserved
<> 144:ef7eb2e8f9f7 20747 */
<> 144:ef7eb2e8f9f7 20748 __IO uint32_t WEEKDAY;
<> 144:ef7eb2e8f9f7 20749
<> 144:ef7eb2e8f9f7 20750 /**
<> 144:ef7eb2e8f9f7 20751 * TALM
<> 144:ef7eb2e8f9f7 20752 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20753 * Offset: 0x1C Time Alarm Register
<> 144:ef7eb2e8f9f7 20754 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20755 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20756 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20757 * |[0:3] |SEC |1-Sec Time Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 20758 * |[4:6] |TENSEC |10-Sec Time Digit of Alarm Setting (0~5)
<> 144:ef7eb2e8f9f7 20759 * |[8:11] |MIN |1-Min Time Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 20760 * |[12:14] |TENMIN |10-Min Time Digit of Alarm Setting (0~5)
<> 144:ef7eb2e8f9f7 20761 * |[16:19] |HR |1-Hour Time Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 20762 * |[20:21] |TENHR |10-Hour Time Digit of Alarm Setting (0~2)
<> 144:ef7eb2e8f9f7 20763 */
<> 144:ef7eb2e8f9f7 20764 __IO uint32_t TALM;
<> 144:ef7eb2e8f9f7 20765
<> 144:ef7eb2e8f9f7 20766 /**
<> 144:ef7eb2e8f9f7 20767 * CALM
<> 144:ef7eb2e8f9f7 20768 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20769 * Offset: 0x20 Calendar Alarm Register
<> 144:ef7eb2e8f9f7 20770 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20771 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20772 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20773 * |[0:3] |DAY |1-Day Calendar Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 20774 * |[4:5] |TENDAY |10-Day Calendar Digit of Alarm Setting (0~3)
<> 144:ef7eb2e8f9f7 20775 * |[8:11] |MON |1-Month Calendar Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 20776 * |[12] |TENMON |10-Month Calendar Digit of Alarm Setting (0~1)
<> 144:ef7eb2e8f9f7 20777 * |[16:19] |YEAR |1-Year Calendar Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 20778 * |[20:23] |TENYEAR |10-Year Calendar Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 20779 */
<> 144:ef7eb2e8f9f7 20780 __IO uint32_t CALM;
<> 144:ef7eb2e8f9f7 20781
<> 144:ef7eb2e8f9f7 20782 /**
<> 144:ef7eb2e8f9f7 20783 * LEAPYEAR
<> 144:ef7eb2e8f9f7 20784 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20785 * Offset: 0x24 Leap Year Indication Register
<> 144:ef7eb2e8f9f7 20786 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20787 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20788 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20789 * |[0] |LEAPYEAR |Leap Year Indicator (Read Only)
<> 144:ef7eb2e8f9f7 20790 * | | |0 = This year is not a leap year.
<> 144:ef7eb2e8f9f7 20791 * | | |1 = This year is leap year.
<> 144:ef7eb2e8f9f7 20792 */
<> 144:ef7eb2e8f9f7 20793 __I uint32_t LEAPYEAR;
<> 144:ef7eb2e8f9f7 20794
<> 144:ef7eb2e8f9f7 20795 /**
<> 144:ef7eb2e8f9f7 20796 * INTEN
<> 144:ef7eb2e8f9f7 20797 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20798 * Offset: 0x28 RTC Interrupt Enable Register
<> 144:ef7eb2e8f9f7 20799 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20800 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20801 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20802 * |[0] |ALMIEN |Alarm Interrupt Enable Control
<> 144:ef7eb2e8f9f7 20803 * | | |0 = RTC Alarm Interrupt Disabled.
<> 144:ef7eb2e8f9f7 20804 * | | |1 = RTC Alarm Interrupt Enabled.
<> 144:ef7eb2e8f9f7 20805 * |[1] |TICKIEN |Time Tick Interrupt Enable Control
<> 144:ef7eb2e8f9f7 20806 * | | |0 = RTC Time Tick Interrupt Disabled.
<> 144:ef7eb2e8f9f7 20807 * | | |1 = RTC Time Tick Interrupt Enabled.
<> 144:ef7eb2e8f9f7 20808 */
<> 144:ef7eb2e8f9f7 20809 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 20810
<> 144:ef7eb2e8f9f7 20811 /**
<> 144:ef7eb2e8f9f7 20812 * INTSTS
<> 144:ef7eb2e8f9f7 20813 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20814 * Offset: 0x2C RTC Interrupt Indicator Register
<> 144:ef7eb2e8f9f7 20815 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20816 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20817 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20818 * |[0] |ALMIF |RTC Alarm Interrupt Flag
<> 144:ef7eb2e8f9f7 20819 * | | |When RTC real time counters RTC_TIME and RTC_CAL reach the alarm setting time registers RTC_TALM and RTC_CALM, this bit will be set to 1 and an interrupt will be generated if RTC Alarm Interrupt enabled (ALMIEN (RTC_INTEN(0)) is set to 1.
<> 144:ef7eb2e8f9f7 20820 * | | |Chip will also be waken up if RTC Alarm Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
<> 144:ef7eb2e8f9f7 20821 * | | |Note: This bit can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 20822 * |[1] |TICKIF |RTC Time Tick Interrupt Flag
<> 144:ef7eb2e8f9f7 20823 * | | |When RTC Time Tick happened, this bit will be set to 1 and an interrupt will be generated if RTC Tick Interrupt enabled (TICKIEN (RTC_INTEN[1])) is set to 1.
<> 144:ef7eb2e8f9f7 20824 * | | |Chip will also be waken up if RTC Tick Interrupt is enabled and this bit is set to 1 when chip is running at Power-down mode.
<> 144:ef7eb2e8f9f7 20825 * | | |Note: This bit can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 20826 */
<> 144:ef7eb2e8f9f7 20827 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 20828
<> 144:ef7eb2e8f9f7 20829 /**
<> 144:ef7eb2e8f9f7 20830 * TICK
<> 144:ef7eb2e8f9f7 20831 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20832 * Offset: 0x30 RTC Time Tick Register
<> 144:ef7eb2e8f9f7 20833 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20834 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20835 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20836 * |[0:2] |TICKSEL |Time Tick Bits
<> 144:ef7eb2e8f9f7 20837 * | | |The RTC time tick period for Periodic Time Tick Interrupt request.
<> 144:ef7eb2e8f9f7 20838 * | | |000 = Time tick is 1 second.
<> 144:ef7eb2e8f9f7 20839 * | | |001 = Time tick is 1/2 second.
<> 144:ef7eb2e8f9f7 20840 * | | |010 = Time tick is 1/4 second.
<> 144:ef7eb2e8f9f7 20841 * | | |011 = Time tick is 1/8 second.
<> 144:ef7eb2e8f9f7 20842 * | | |100 = Time tick is 1/16 second.
<> 144:ef7eb2e8f9f7 20843 * | | |101 = Time tick is 1/32 second.
<> 144:ef7eb2e8f9f7 20844 * | | |110 = Time tick is 1/64 second.
<> 144:ef7eb2e8f9f7 20845 * | | |111 = Time tick is 1/128 second.
<> 144:ef7eb2e8f9f7 20846 * | | |Note: These bits can be read back after the RTC register access enable bit RWENF (RTC_RWEN[16]) is active.
<> 144:ef7eb2e8f9f7 20847 */
<> 144:ef7eb2e8f9f7 20848 __IO uint32_t TICK;
<> 144:ef7eb2e8f9f7 20849 uint32_t RESERVE0[2];
<> 144:ef7eb2e8f9f7 20850
<> 144:ef7eb2e8f9f7 20851
<> 144:ef7eb2e8f9f7 20852 /**
<> 144:ef7eb2e8f9f7 20853 * SPRCTL
<> 144:ef7eb2e8f9f7 20854 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20855 * Offset: 0x3C RTC Spare Functional Control Register
<> 144:ef7eb2e8f9f7 20856 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20857 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20858 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20859 * |[2] |SPRRWEN |SPR Register Enable Control
<> 144:ef7eb2e8f9f7 20860 * | | |This bit controls the spare register to be enabled or not.
<> 144:ef7eb2e8f9f7 20861 * | | |0 = Spare register Disabled and RTC_SPR0 ~ RTC_SPR23 cannot be accessed.
<> 144:ef7eb2e8f9f7 20862 * | | |1 = Spare register Enabled and RTC_SPR0 ~ RTC_SPR23 can be accessed.
<> 144:ef7eb2e8f9f7 20863 * |[7] |SPRRWRDY |SPR Register Ready
<> 144:ef7eb2e8f9f7 20864 * | | |This bit indicates if the registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are ready to be accessed.
<> 144:ef7eb2e8f9f7 20865 * | | |After CPU writing registers RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23, polling this bit to check if these registers are updated done is necessary.
<> 144:ef7eb2e8f9f7 20866 * | | |This bit is read only and any write to it won't take any effect.
<> 144:ef7eb2e8f9f7 20867 * | | |0 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 updating is in progress.
<> 144:ef7eb2e8f9f7 20868 * | | |1 = RTC_SPRCTL, RTC_SPR0 ~ RTC_SPR23 are updated done and ready to be accessed.
<> 144:ef7eb2e8f9f7 20869 */
<> 144:ef7eb2e8f9f7 20870 __IO uint32_t SPRCTL;
<> 144:ef7eb2e8f9f7 20871
<> 144:ef7eb2e8f9f7 20872 /**
<> 144:ef7eb2e8f9f7 20873 * SPRx
<> 144:ef7eb2e8f9f7 20874 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20875 * Offset: 0x40 RTC Spare Register 0 ~ 23
<> 144:ef7eb2e8f9f7 20876 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20877 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20878 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20879 * |[0:31] |SPARE |SPARE Bits
<> 144:ef7eb2e8f9f7 20880 * | | |This field is used to store back-up information defined by software.
<> 144:ef7eb2e8f9f7 20881 * | | |This field will be cleared by hardware automatically once a snooper pin event is detected.
<> 144:ef7eb2e8f9f7 20882 * | | |Before storing back-up information in to SPARE register, software should write 0xA965 to RTC_RWEN to make sure register read/write enabled.
<> 144:ef7eb2e8f9f7 20883 */
<> 144:ef7eb2e8f9f7 20884 __IO uint32_t SPR[24];
<> 144:ef7eb2e8f9f7 20885 uint32_t RESERVE1[28];
<> 144:ef7eb2e8f9f7 20886
<> 144:ef7eb2e8f9f7 20887
<> 144:ef7eb2e8f9f7 20888 /**
<> 144:ef7eb2e8f9f7 20889 * TAMPCTL
<> 144:ef7eb2e8f9f7 20890 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20891 * Offset: 0x110 Tamper Control Register
<> 144:ef7eb2e8f9f7 20892 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20893 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20894 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20895 * |[0] |TIEN |Tamper Interrupt Enable Control
<> 144:ef7eb2e8f9f7 20896 * | | |0 = Tamper interrupt Disabled.
<> 144:ef7eb2e8f9f7 20897 * | | |1 = Tamper interrupt Enabled.
<> 144:ef7eb2e8f9f7 20898 * |[1] |DESTROYEN |Destroy Spare Register Enable Control
<> 144:ef7eb2e8f9f7 20899 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 20900 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 20901 * |[2] |TAMPEN0 |Tamper0 Detect Enable Control
<> 144:ef7eb2e8f9f7 20902 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 20903 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 20904 * |[3] |TAMPEN1 |Tamper1 Detect Enable Control
<> 144:ef7eb2e8f9f7 20905 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 20906 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 20907 * |[4] |TAMPDBEN0 |Tamper0 De-Bounce Enable Control
<> 144:ef7eb2e8f9f7 20908 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 20909 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 20910 * |[5] |TAMPDBEN1 |Tamper1 De-Bounce Enable Control
<> 144:ef7eb2e8f9f7 20911 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 20912 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 20913 * |[6] |TAMPLV0 |Tamper0 Level
<> 144:ef7eb2e8f9f7 20914 * | | |0 = Low.
<> 144:ef7eb2e8f9f7 20915 * | | |1 = High.
<> 144:ef7eb2e8f9f7 20916 * |[7] |TAMPLV1 |Tamper1 Level
<> 144:ef7eb2e8f9f7 20917 * | | |0 = Low.
<> 144:ef7eb2e8f9f7 20918 * | | |1 = High.
<> 144:ef7eb2e8f9f7 20919 */
<> 144:ef7eb2e8f9f7 20920 __IO uint32_t TAMPCTL;
<> 144:ef7eb2e8f9f7 20921
<> 144:ef7eb2e8f9f7 20922 /**
<> 144:ef7eb2e8f9f7 20923 * TAMPSTS
<> 144:ef7eb2e8f9f7 20924 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20925 * Offset: 0x114 Tamper Status Register
<> 144:ef7eb2e8f9f7 20926 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20927 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20928 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20929 * |[0] |TAMPSTS0 |Tamper0 Sense Flag
<> 144:ef7eb2e8f9f7 20930 * | | |0 = No invasion.
<> 144:ef7eb2e8f9f7 20931 * | | |1 = Tamper0 detect invasion.
<> 144:ef7eb2e8f9f7 20932 * | | |Note: Write 1 to clear it
<> 144:ef7eb2e8f9f7 20933 * |[1] |TAMPSTS1 |Tamper1 Sense Flag
<> 144:ef7eb2e8f9f7 20934 * | | |0 = No invasion.
<> 144:ef7eb2e8f9f7 20935 * | | |1 = Tamper1 detect invasion.
<> 144:ef7eb2e8f9f7 20936 * | | |Note: Write 1 to clear it
<> 144:ef7eb2e8f9f7 20937 */
<> 144:ef7eb2e8f9f7 20938 __IO uint32_t TAMPSTS;
<> 144:ef7eb2e8f9f7 20939 uint32_t RESERVE2[3];
<> 144:ef7eb2e8f9f7 20940
<> 144:ef7eb2e8f9f7 20941
<> 144:ef7eb2e8f9f7 20942 /**
<> 144:ef7eb2e8f9f7 20943 * TAMP0PCTL
<> 144:ef7eb2e8f9f7 20944 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20945 * Offset: 0x124 TAMPER0 Pin I/O Mode Control
<> 144:ef7eb2e8f9f7 20946 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20947 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20948 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20949 * |[0] |OUTLV |Output Level
<> 144:ef7eb2e8f9f7 20950 * | | |0 = Low.
<> 144:ef7eb2e8f9f7 20951 * | | |1 = High.
<> 144:ef7eb2e8f9f7 20952 * |[1] |OUTEN |Output Enable Control
<> 144:ef7eb2e8f9f7 20953 * | | |0 = Output Enabled.
<> 144:ef7eb2e8f9f7 20954 * | | |1 = Output Disabled.
<> 144:ef7eb2e8f9f7 20955 * |[2] |TRIEN |Tri-State
<> 144:ef7eb2e8f9f7 20956 * | | |0 = Tri-state Disabled.
<> 144:ef7eb2e8f9f7 20957 * | | |1 = Tri-state Enabled.
<> 144:ef7eb2e8f9f7 20958 * |[3] |TYPE |Type
<> 144:ef7eb2e8f9f7 20959 * | | |0 = Input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 20960 * | | |1 = Input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 20961 * |[4] |DINOFF |Off Digital
<> 144:ef7eb2e8f9f7 20962 * | | |0 = Off digital Disabled.
<> 144:ef7eb2e8f9f7 20963 * | | |1 = Off digital Enabled.
<> 144:ef7eb2e8f9f7 20964 */
<> 144:ef7eb2e8f9f7 20965 __IO uint32_t TAMP0PCTL;
<> 144:ef7eb2e8f9f7 20966
<> 144:ef7eb2e8f9f7 20967 /**
<> 144:ef7eb2e8f9f7 20968 * TAMP1PCTL
<> 144:ef7eb2e8f9f7 20969 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20970 * Offset: 0x128 TAMPER1 Pin I/O Mode Control
<> 144:ef7eb2e8f9f7 20971 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20972 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20973 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20974 * |[0] |OUTLV |Output Level
<> 144:ef7eb2e8f9f7 20975 * | | |0 = Low.
<> 144:ef7eb2e8f9f7 20976 * | | |1 = High.
<> 144:ef7eb2e8f9f7 20977 * |[1] |OUTEN |Output Enable Control
<> 144:ef7eb2e8f9f7 20978 * | | |0 = Output Enabled.
<> 144:ef7eb2e8f9f7 20979 * | | |1 = Output Disabled.
<> 144:ef7eb2e8f9f7 20980 * |[2] |TRIEN |Tri-State
<> 144:ef7eb2e8f9f7 20981 * | | |0 = Tri-state Disabled.
<> 144:ef7eb2e8f9f7 20982 * | | |1 = Tri-state Enabled.
<> 144:ef7eb2e8f9f7 20983 * |[3] |TYPE |Type
<> 144:ef7eb2e8f9f7 20984 * | | |0 = Input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 20985 * | | |1 = Input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 20986 * |[4] |DINOFF |Off Digital
<> 144:ef7eb2e8f9f7 20987 * | | |0 = Off digital Disabled.
<> 144:ef7eb2e8f9f7 20988 * | | |1 = Off digital Enabled.
<> 144:ef7eb2e8f9f7 20989 */
<> 144:ef7eb2e8f9f7 20990 __IO uint32_t TAMP1PCTL;
<> 144:ef7eb2e8f9f7 20991
<> 144:ef7eb2e8f9f7 20992 /**
<> 144:ef7eb2e8f9f7 20993 * LXTIPCTL
<> 144:ef7eb2e8f9f7 20994 * ===================================================================================================
<> 144:ef7eb2e8f9f7 20995 * Offset: 0x12C 32K Input Pin I/O Mode Control
<> 144:ef7eb2e8f9f7 20996 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 20997 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 20998 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 20999 * |[0] |OUTLV |Output Level
<> 144:ef7eb2e8f9f7 21000 * | | |0 = Low.
<> 144:ef7eb2e8f9f7 21001 * | | |1 = High.
<> 144:ef7eb2e8f9f7 21002 * |[1] |OUTEN |Output Enable Control
<> 144:ef7eb2e8f9f7 21003 * | | |0 = Output Enabled.
<> 144:ef7eb2e8f9f7 21004 * | | |1 = Output Disabled.
<> 144:ef7eb2e8f9f7 21005 * |[2] |TRIEN |Tri-State
<> 144:ef7eb2e8f9f7 21006 * | | |0 = Tri-state Disabled.
<> 144:ef7eb2e8f9f7 21007 * | | |1 = Tri-state Enabled.
<> 144:ef7eb2e8f9f7 21008 * |[3] |TYPE |Type
<> 144:ef7eb2e8f9f7 21009 * | | |0 = Input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 21010 * | | |1 = Input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 21011 * |[4] |DINOFF |Off Digital
<> 144:ef7eb2e8f9f7 21012 * | | |0 = Off digital Disabled.
<> 144:ef7eb2e8f9f7 21013 * | | |1 = Off digital Enabled.
<> 144:ef7eb2e8f9f7 21014 */
<> 144:ef7eb2e8f9f7 21015 __IO uint32_t LXTIPCTL;
<> 144:ef7eb2e8f9f7 21016
<> 144:ef7eb2e8f9f7 21017 /**
<> 144:ef7eb2e8f9f7 21018 * LXTOPCTL
<> 144:ef7eb2e8f9f7 21019 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21020 * Offset: 0x130 32K Output Pin I/O Mode Control
<> 144:ef7eb2e8f9f7 21021 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21022 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21023 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21024 * |[0] |OUTLV |Output Level
<> 144:ef7eb2e8f9f7 21025 * | | |0 = Low.
<> 144:ef7eb2e8f9f7 21026 * | | |1 = High.
<> 144:ef7eb2e8f9f7 21027 * |[1] |OUTEN |Output Enable Control
<> 144:ef7eb2e8f9f7 21028 * | | |0 = Output Enabled.
<> 144:ef7eb2e8f9f7 21029 * | | |1 = Output Disabled.
<> 144:ef7eb2e8f9f7 21030 * |[2] |TRIEN |Tri-State
<> 144:ef7eb2e8f9f7 21031 * | | |0 = Tri-state Disabled.
<> 144:ef7eb2e8f9f7 21032 * | | |1 = Tri-state Enabled.
<> 144:ef7eb2e8f9f7 21033 * |[3] |TYPE |Type
<> 144:ef7eb2e8f9f7 21034 * | | |0 = Input Schmitt Trigger function Disabled.
<> 144:ef7eb2e8f9f7 21035 * | | |1 = Input Schmitt Trigger function Enabled.
<> 144:ef7eb2e8f9f7 21036 * |[4] |DINOFF |Off Digital
<> 144:ef7eb2e8f9f7 21037 * | | |0 = Off digital Disabled.
<> 144:ef7eb2e8f9f7 21038 * | | |1 = Off digital Enabled.
<> 144:ef7eb2e8f9f7 21039 */
<> 144:ef7eb2e8f9f7 21040 __IO uint32_t LXTOPCTL;
<> 144:ef7eb2e8f9f7 21041 uint32_t RESERVE3[3];
<> 144:ef7eb2e8f9f7 21042
<> 144:ef7eb2e8f9f7 21043
<> 144:ef7eb2e8f9f7 21044 /**
<> 144:ef7eb2e8f9f7 21045 * TAMSK
<> 144:ef7eb2e8f9f7 21046 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21047 * Offset: 0x140 Time Alarm MASK Register
<> 144:ef7eb2e8f9f7 21048 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21049 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21050 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21051 * |[0] |MSEC |Mask 1-Sec Time Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 21052 * |[1] |MTENSEC |Mask 10-Sec Time Digit of Alarm Setting (0~5)
<> 144:ef7eb2e8f9f7 21053 * |[2] |MMIN |Mask 1-Min Time Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 21054 * |[3] |MTENMIN |Mask 10-Min Time Digit of Alarm Setting (0~5)
<> 144:ef7eb2e8f9f7 21055 * |[4] |MHR |Mask 1-Hour Time Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 21056 * |[5] |MTENHR |Mask 10-Hour Time Digit of Alarm Setting (0~2)
<> 144:ef7eb2e8f9f7 21057 */
<> 144:ef7eb2e8f9f7 21058 __IO uint32_t TAMSK;
<> 144:ef7eb2e8f9f7 21059
<> 144:ef7eb2e8f9f7 21060 /**
<> 144:ef7eb2e8f9f7 21061 * CAMSK
<> 144:ef7eb2e8f9f7 21062 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21063 * Offset: 0x144 Calendar Alarm MASK Register
<> 144:ef7eb2e8f9f7 21064 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21065 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21066 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21067 * |[0] |MDAY |Mask 1-Day Calendar Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 21068 * |[1] |MTENDAY |Mask 10-Day Calendar Digit of Alarm Setting (0~3)
<> 144:ef7eb2e8f9f7 21069 * |[2] |MMON |Mask 1-Month Calendar Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 21070 * |[3] |MTENMON |Mask 10-Month Calendar Digit of Alarm Setting (0~1)
<> 144:ef7eb2e8f9f7 21071 * |[4] |MYEAR |Mask 1-Year Calendar Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 21072 * |[5] |MTENYEAR |Mask 10-Year Calendar Digit of Alarm Setting (0~9)
<> 144:ef7eb2e8f9f7 21073 */
<> 144:ef7eb2e8f9f7 21074 __IO uint32_t CAMSK;
<> 144:ef7eb2e8f9f7 21075
<> 144:ef7eb2e8f9f7 21076 } RTC_T;
<> 144:ef7eb2e8f9f7 21077
<> 144:ef7eb2e8f9f7 21078 /**
<> 144:ef7eb2e8f9f7 21079 @addtogroup RTC_CONST RTC Bit Field Definition
<> 144:ef7eb2e8f9f7 21080 Constant Definitions for RTC Controller
<> 144:ef7eb2e8f9f7 21081 @{ */
<> 144:ef7eb2e8f9f7 21082
<> 144:ef7eb2e8f9f7 21083 #define RTC_INIT_INIT_Active_Pos (0) /*!< RTC INIT: INIT_Active Position */
<> 144:ef7eb2e8f9f7 21084 #define RTC_INIT_INIT_Active_Msk (0x1ul << RTC_INIT_INIT_Active_Pos) /*!< RTC INIT: INIT_Active Mask */
<> 144:ef7eb2e8f9f7 21085
<> 144:ef7eb2e8f9f7 21086 #define RTC_INIT_INIT_Pos (1) /*!< RTC INIT: INIT Position */
<> 144:ef7eb2e8f9f7 21087 #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) /*!< RTC INIT: INIT Mask */
<> 144:ef7eb2e8f9f7 21088
<> 144:ef7eb2e8f9f7 21089 #define RTC_RWEN_RWEN_Pos (0) /*!< RTC RWEN: RWEN Position */
<> 144:ef7eb2e8f9f7 21090 #define RTC_RWEN_RWEN_Msk (0xfffful << RTC_RWEN_RWEN_Pos) /*!< RTC RWEN: RWEN Mask */
<> 144:ef7eb2e8f9f7 21091
<> 144:ef7eb2e8f9f7 21092 #define RTC_RWEN_RWENF_Pos (16) /*!< RTC RWEN: RWENF Position */
<> 144:ef7eb2e8f9f7 21093 #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) /*!< RTC RWEN: RWENF Mask */
<> 144:ef7eb2e8f9f7 21094
<> 144:ef7eb2e8f9f7 21095 #define RTC_FREQADJ_FRACTION_Pos (0) /*!< RTC FREQADJ: FRACTION Position */
<> 144:ef7eb2e8f9f7 21096 #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) /*!< RTC FREQADJ: FRACTION Mask */
<> 144:ef7eb2e8f9f7 21097
<> 144:ef7eb2e8f9f7 21098 #define RTC_FREQADJ_INTEGER_Pos (8) /*!< RTC FREQADJ: INTEGER Position */
<> 144:ef7eb2e8f9f7 21099 #define RTC_FREQADJ_INTEGER_Msk (0xful << RTC_FREQADJ_INTEGER_Pos) /*!< RTC FREQADJ: INTEGER Mask */
<> 144:ef7eb2e8f9f7 21100
<> 144:ef7eb2e8f9f7 21101 #define RTC_TIME_SEC_Pos (0) /*!< RTC TIME: SEC Position */
<> 144:ef7eb2e8f9f7 21102 #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) /*!< RTC TIME: SEC Mask */
<> 144:ef7eb2e8f9f7 21103
<> 144:ef7eb2e8f9f7 21104 #define RTC_TIME_TENSEC_Pos (4) /*!< RTC TIME: TENSEC Position */
<> 144:ef7eb2e8f9f7 21105 #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) /*!< RTC TIME: TENSEC Mask */
<> 144:ef7eb2e8f9f7 21106
<> 144:ef7eb2e8f9f7 21107 #define RTC_TIME_MIN_Pos (8) /*!< RTC TIME: MIN Position */
<> 144:ef7eb2e8f9f7 21108 #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) /*!< RTC TIME: MIN Mask */
<> 144:ef7eb2e8f9f7 21109
<> 144:ef7eb2e8f9f7 21110 #define RTC_TIME_TENMIN_Pos (12) /*!< RTC TIME: TENMIN Position */
<> 144:ef7eb2e8f9f7 21111 #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) /*!< RTC TIME: TENMIN Mask */
<> 144:ef7eb2e8f9f7 21112
<> 144:ef7eb2e8f9f7 21113 #define RTC_TIME_HR_Pos (16) /*!< RTC TIME: HR Position */
<> 144:ef7eb2e8f9f7 21114 #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) /*!< RTC TIME: HR Mask */
<> 144:ef7eb2e8f9f7 21115
<> 144:ef7eb2e8f9f7 21116 #define RTC_TIME_TENHR_Pos (20) /*!< RTC TIME: TENHR Position */
<> 144:ef7eb2e8f9f7 21117 #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) /*!< RTC TIME: TENHR Mask */
<> 144:ef7eb2e8f9f7 21118
<> 144:ef7eb2e8f9f7 21119 #define RTC_CAL_DAY_Pos (0) /*!< RTC CAL: DAY Position */
<> 144:ef7eb2e8f9f7 21120 #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) /*!< RTC CAL: DAY Mask */
<> 144:ef7eb2e8f9f7 21121
<> 144:ef7eb2e8f9f7 21122 #define RTC_CAL_TENDAY_Pos (4) /*!< RTC CAL: TENDAY Position */
<> 144:ef7eb2e8f9f7 21123 #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) /*!< RTC CAL: TENDAY Mask */
<> 144:ef7eb2e8f9f7 21124
<> 144:ef7eb2e8f9f7 21125 #define RTC_CAL_MON_Pos (8) /*!< RTC CAL: MON Position */
<> 144:ef7eb2e8f9f7 21126 #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) /*!< RTC CAL: MON Mask */
<> 144:ef7eb2e8f9f7 21127
<> 144:ef7eb2e8f9f7 21128 #define RTC_CAL_TENMON_Pos (12) /*!< RTC CAL: TENMON Position */
<> 144:ef7eb2e8f9f7 21129 #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) /*!< RTC CAL: TENMON Mask */
<> 144:ef7eb2e8f9f7 21130
<> 144:ef7eb2e8f9f7 21131 #define RTC_CAL_YEAR_Pos (16) /*!< RTC CAL: YEAR Position */
<> 144:ef7eb2e8f9f7 21132 #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) /*!< RTC CAL: YEAR Mask */
<> 144:ef7eb2e8f9f7 21133
<> 144:ef7eb2e8f9f7 21134 #define RTC_CAL_TENYEAR_Pos (20) /*!< RTC CAL: TENYEAR Position */
<> 144:ef7eb2e8f9f7 21135 #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) /*!< RTC CAL: TENYEAR Mask */
<> 144:ef7eb2e8f9f7 21136
<> 144:ef7eb2e8f9f7 21137 #define RTC_CLKFMT_24HEN_Pos (0) /*!< RTC CLKFMT: 24HEN Position */
<> 144:ef7eb2e8f9f7 21138 #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) /*!< RTC CLKFMT: 24HEN Mask */
<> 144:ef7eb2e8f9f7 21139
<> 144:ef7eb2e8f9f7 21140 #define RTC_WEEKDAY_WEEKDAY_Pos (0) /*!< RTC WEEKDAY: WEEKDAY Position */
<> 144:ef7eb2e8f9f7 21141 #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) /*!< RTC WEEKDAY: WEEKDAY Mask */
<> 144:ef7eb2e8f9f7 21142
<> 144:ef7eb2e8f9f7 21143 #define RTC_TALM_SEC_Pos (0) /*!< RTC TALM: SEC Position */
<> 144:ef7eb2e8f9f7 21144 #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) /*!< RTC TALM: SEC Mask */
<> 144:ef7eb2e8f9f7 21145
<> 144:ef7eb2e8f9f7 21146 #define RTC_TALM_TENSEC_Pos (4) /*!< RTC TALM: TENSEC Position */
<> 144:ef7eb2e8f9f7 21147 #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) /*!< RTC TALM: TENSEC Mask */
<> 144:ef7eb2e8f9f7 21148
<> 144:ef7eb2e8f9f7 21149 #define RTC_TALM_MIN_Pos (8) /*!< RTC TALM: MIN Position */
<> 144:ef7eb2e8f9f7 21150 #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) /*!< RTC TALM: MIN Mask */
<> 144:ef7eb2e8f9f7 21151
<> 144:ef7eb2e8f9f7 21152 #define RTC_TALM_TENMIN_Pos (12) /*!< RTC TALM: TENMIN Position */
<> 144:ef7eb2e8f9f7 21153 #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) /*!< RTC TALM: TENMIN Mask */
<> 144:ef7eb2e8f9f7 21154
<> 144:ef7eb2e8f9f7 21155 #define RTC_TALM_HR_Pos (16) /*!< RTC TALM: HR Position */
<> 144:ef7eb2e8f9f7 21156 #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) /*!< RTC TALM: HR Mask */
<> 144:ef7eb2e8f9f7 21157
<> 144:ef7eb2e8f9f7 21158 #define RTC_TALM_TENHR_Pos (20) /*!< RTC TALM: TENHR Position */
<> 144:ef7eb2e8f9f7 21159 #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) /*!< RTC TALM: TENHR Mask */
<> 144:ef7eb2e8f9f7 21160
<> 144:ef7eb2e8f9f7 21161 #define RTC_CALM_DAY_Pos (0) /*!< RTC CALM: DAY Position */
<> 144:ef7eb2e8f9f7 21162 #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) /*!< RTC CALM: DAY Mask */
<> 144:ef7eb2e8f9f7 21163
<> 144:ef7eb2e8f9f7 21164 #define RTC_CALM_TENDAY_Pos (4) /*!< RTC CALM: TENDAY Position */
<> 144:ef7eb2e8f9f7 21165 #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) /*!< RTC CALM: TENDAY Mask */
<> 144:ef7eb2e8f9f7 21166
<> 144:ef7eb2e8f9f7 21167 #define RTC_CALM_MON_Pos (8) /*!< RTC CALM: MON Position */
<> 144:ef7eb2e8f9f7 21168 #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) /*!< RTC CALM: MON Mask */
<> 144:ef7eb2e8f9f7 21169
<> 144:ef7eb2e8f9f7 21170 #define RTC_CALM_TENMON_Pos (12) /*!< RTC CALM: TENMON Position */
<> 144:ef7eb2e8f9f7 21171 #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) /*!< RTC CALM: TENMON Mask */
<> 144:ef7eb2e8f9f7 21172
<> 144:ef7eb2e8f9f7 21173 #define RTC_CALM_YEAR_Pos (16) /*!< RTC CALM: YEAR Position */
<> 144:ef7eb2e8f9f7 21174 #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) /*!< RTC CALM: YEAR Mask */
<> 144:ef7eb2e8f9f7 21175
<> 144:ef7eb2e8f9f7 21176 #define RTC_CALM_TENYEAR_Pos (20) /*!< RTC CALM: TENYEAR Position */
<> 144:ef7eb2e8f9f7 21177 #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) /*!< RTC CALM: TENYEAR Mask */
<> 144:ef7eb2e8f9f7 21178
<> 144:ef7eb2e8f9f7 21179 #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) /*!< RTC LEAPYEAR: LEAPYEAR Position */
<> 144:ef7eb2e8f9f7 21180 #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) /*!< RTC LEAPYEAR: LEAPYEAR Mask */
<> 144:ef7eb2e8f9f7 21181
<> 144:ef7eb2e8f9f7 21182 #define RTC_INTEN_ALMIEN_Pos (0) /*!< RTC INTEN: ALMIEN Position */
<> 144:ef7eb2e8f9f7 21183 #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) /*!< RTC INTEN: ALMIEN Mask */
<> 144:ef7eb2e8f9f7 21184
<> 144:ef7eb2e8f9f7 21185 #define RTC_INTEN_TICKIEN_Pos (1) /*!< RTC INTEN: TICKIEN Position */
<> 144:ef7eb2e8f9f7 21186 #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) /*!< RTC INTEN: TICKIEN Mask */
<> 144:ef7eb2e8f9f7 21187
<> 144:ef7eb2e8f9f7 21188 #define RTC_INTSTS_ALMIF_Pos (0) /*!< RTC INTSTS: ALMIF Position */
<> 144:ef7eb2e8f9f7 21189 #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) /*!< RTC INTSTS: ALMIF Mask */
<> 144:ef7eb2e8f9f7 21190
<> 144:ef7eb2e8f9f7 21191 #define RTC_INTSTS_TICKIF_Pos (1) /*!< RTC INTSTS: TICKIF Position */
<> 144:ef7eb2e8f9f7 21192 #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) /*!< RTC INTSTS: TICKIF Mask */
<> 144:ef7eb2e8f9f7 21193
<> 144:ef7eb2e8f9f7 21194 #define RTC_TICK_TICKSEL_Pos (0) /*!< RTC TICK: TICKSEL Position */
<> 144:ef7eb2e8f9f7 21195 #define RTC_TICK_TICKSEL_Msk (0x7ul << RTC_TICK_TICKSEL_Pos) /*!< RTC TICK: TICKSEL Mask */
<> 144:ef7eb2e8f9f7 21196
<> 144:ef7eb2e8f9f7 21197 #define RTC_SPRCTL_SPRRWEN_Pos (2) /*!< RTC SPRCTL: SPRRWEN Position */
<> 144:ef7eb2e8f9f7 21198 #define RTC_SPRCTL_SPRRWEN_Msk (0x1ul << RTC_SPRCTL_SPRRWEN_Pos) /*!< RTC SPRCTL: SPRRWEN Mask */
<> 144:ef7eb2e8f9f7 21199
<> 144:ef7eb2e8f9f7 21200 #define RTC_SPRCTL_SPRRWRDY_Pos (7) /*!< RTC SPRCTL: SPRRWRDY Position */
<> 144:ef7eb2e8f9f7 21201 #define RTC_SPRCTL_SPRRWRDY_Msk (0x1ul << RTC_SPRCTL_SPRRWRDY_Pos) /*!< RTC SPRCTL: SPRRWRDY Mask */
<> 144:ef7eb2e8f9f7 21202
<> 144:ef7eb2e8f9f7 21203 #define RTC_TAMPCTL_TIEN_Pos (0) /*!< RTC TAMPCTL: TIEN Position */
<> 144:ef7eb2e8f9f7 21204 #define RTC_TAMPCTL_TIEN_Msk (0x1ul << RTC_TAMPCTL_TIEN_Pos) /*!< RTC TAMPCTL: TIEN Mask */
<> 144:ef7eb2e8f9f7 21205
<> 144:ef7eb2e8f9f7 21206 #define RTC_TAMPCTL_DESTROYEN_Pos (1) /*!< RTC TAMPCTL: DESTROYEN Position */
<> 144:ef7eb2e8f9f7 21207 #define RTC_TAMPCTL_DESTROYEN_Msk (0x1ul << RTC_TAMPCTL_DESTROYEN_Pos) /*!< RTC TAMPCTL: DESTROYEN Mask */
<> 144:ef7eb2e8f9f7 21208
<> 144:ef7eb2e8f9f7 21209 #define RTC_TAMPCTL_TAMPEN0_Pos (2) /*!< RTC TAMPCTL: TAMPEN0 Position */
<> 144:ef7eb2e8f9f7 21210 #define RTC_TAMPCTL_TAMPEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPEN0_Pos) /*!< RTC TAMPCTL: TAMPEN0 Mask */
<> 144:ef7eb2e8f9f7 21211
<> 144:ef7eb2e8f9f7 21212 #define RTC_TAMPCTL_TAMPEN1_Pos (3) /*!< RTC TAMPCTL: TAMPEN1 Position */
<> 144:ef7eb2e8f9f7 21213 #define RTC_TAMPCTL_TAMPEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPEN1_Pos) /*!< RTC TAMPCTL: TAMPEN1 Mask */
<> 144:ef7eb2e8f9f7 21214
<> 144:ef7eb2e8f9f7 21215 #define RTC_TAMPCTL_TAMPDBEN0_Pos (4) /*!< RTC TAMPCTL: TAMPDBEN0 Position */
<> 144:ef7eb2e8f9f7 21216 #define RTC_TAMPCTL_TAMPDBEN0_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN0_Pos) /*!< RTC TAMPCTL: TAMPDBEN0 Mask */
<> 144:ef7eb2e8f9f7 21217
<> 144:ef7eb2e8f9f7 21218 #define RTC_TAMPCTL_TAMPDBEN1_Pos (5) /*!< RTC TAMPCTL: TAMPDBEN1 Position */
<> 144:ef7eb2e8f9f7 21219 #define RTC_TAMPCTL_TAMPDBEN1_Msk (0x1ul << RTC_TAMPCTL_TAMPDBEN1_Pos) /*!< RTC TAMPCTL: TAMPDBEN1 Mask */
<> 144:ef7eb2e8f9f7 21220
<> 144:ef7eb2e8f9f7 21221 #define RTC_TAMPCTL_TAMPLV0_Pos (6) /*!< RTC TAMPCTL: TAMPLV0 Position */
<> 144:ef7eb2e8f9f7 21222 #define RTC_TAMPCTL_TAMPLV0_Msk (0x1ul << RTC_TAMPCTL_TAMPLV0_Pos) /*!< RTC TAMPCTL: TAMPLV0 Mask */
<> 144:ef7eb2e8f9f7 21223
<> 144:ef7eb2e8f9f7 21224 #define RTC_TAMPCTL_TAMPLV1_Pos (7) /*!< RTC TAMPCTL: TAMPLV1 Position */
<> 144:ef7eb2e8f9f7 21225 #define RTC_TAMPCTL_TAMPLV1_Msk (0x1ul << RTC_TAMPCTL_TAMPLV1_Pos) /*!< RTC TAMPCTL: TAMPLV1 Mask */
<> 144:ef7eb2e8f9f7 21226
<> 144:ef7eb2e8f9f7 21227 #define RTC_TAMPSTS_TAMPSTS0_Pos (0) /*!< RTC TAMPSTS: TAMPSTS0 Position */
<> 144:ef7eb2e8f9f7 21228 #define RTC_TAMPSTS_TAMPSTS0_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS0_Pos) /*!< RTC TAMPSTS: TAMPSTS0 Mask */
<> 144:ef7eb2e8f9f7 21229
<> 144:ef7eb2e8f9f7 21230 #define RTC_TAMPSTS_TAMPSTS1_Pos (1) /*!< RTC TAMPSTS: TAMPSTS1 Position */
<> 144:ef7eb2e8f9f7 21231 #define RTC_TAMPSTS_TAMPSTS1_Msk (0x1ul << RTC_TAMPSTS_TAMPSTS1_Pos) /*!< RTC TAMPSTS: TAMPSTS1 Mask */
<> 144:ef7eb2e8f9f7 21232
<> 144:ef7eb2e8f9f7 21233 #define RTC_TAMP0PCTL_OUTLV_Pos (0) /*!< RTC TAMP0PCTL: OUTLV Position */
<> 144:ef7eb2e8f9f7 21234 #define RTC_TAMP0PCTL_OUTLV_Msk (0x1ul << RTC_TAMP0PCTL_OUTLV_Pos) /*!< RTC TAMP0PCTL: OUTLV Mask */
<> 144:ef7eb2e8f9f7 21235
<> 144:ef7eb2e8f9f7 21236 #define RTC_TAMP0PCTL_OUTEN_Pos (1) /*!< RTC TAMP0PCTL: OUTEN Position */
<> 144:ef7eb2e8f9f7 21237 #define RTC_TAMP0PCTL_OUTEN_Msk (0x1ul << RTC_TAMP0PCTL_OUTEN_Pos) /*!< RTC TAMP0PCTL: OUTEN Mask */
<> 144:ef7eb2e8f9f7 21238
<> 144:ef7eb2e8f9f7 21239 #define RTC_TAMP0PCTL_TRIEN_Pos (2) /*!< RTC TAMP0PCTL: TRIEN Position */
<> 144:ef7eb2e8f9f7 21240 #define RTC_TAMP0PCTL_TRIEN_Msk (0x1ul << RTC_TAMP0PCTL_TRIEN_Pos) /*!< RTC TAMP0PCTL: TRIEN Mask */
<> 144:ef7eb2e8f9f7 21241
<> 144:ef7eb2e8f9f7 21242 #define RTC_TAMP0PCTL_TYPE_Pos (3) /*!< RTC TAMP0PCTL: TYPE Position */
<> 144:ef7eb2e8f9f7 21243 #define RTC_TAMP0PCTL_TYPE_Msk (0x1ul << RTC_TAMP0PCTL_TYPE_Pos) /*!< RTC TAMP0PCTL: TYPE Mask */
<> 144:ef7eb2e8f9f7 21244
<> 144:ef7eb2e8f9f7 21245 #define RTC_TAMP0PCTL_DINOFF_Pos (4) /*!< RTC TAMP0PCTL: DINOFF Position */
<> 144:ef7eb2e8f9f7 21246 #define RTC_TAMP0PCTL_DINOFF_Msk (0x1ul << RTC_TAMP0PCTL_DINOFF_Pos) /*!< RTC TAMP0PCTL: DINOFF Mask */
<> 144:ef7eb2e8f9f7 21247
<> 144:ef7eb2e8f9f7 21248 #define RTC_TAMP1PCTL_OUTLV_Pos (0) /*!< RTC TAMP1PCTL: OUTLV Position */
<> 144:ef7eb2e8f9f7 21249 #define RTC_TAMP1PCTL_OUTLV_Msk (0x1ul << RTC_TAMP1PCTL_OUTLV_Pos) /*!< RTC TAMP1PCTL: OUTLV Mask */
<> 144:ef7eb2e8f9f7 21250
<> 144:ef7eb2e8f9f7 21251 #define RTC_TAMP1PCTL_OUTEN_Pos (1) /*!< RTC TAMP1PCTL: OUTEN Position */
<> 144:ef7eb2e8f9f7 21252 #define RTC_TAMP1PCTL_OUTEN_Msk (0x1ul << RTC_TAMP1PCTL_OUTEN_Pos) /*!< RTC TAMP1PCTL: OUTEN Mask */
<> 144:ef7eb2e8f9f7 21253
<> 144:ef7eb2e8f9f7 21254 #define RTC_TAMP1PCTL_TRIEN_Pos (2) /*!< RTC TAMP1PCTL: TRIEN Position */
<> 144:ef7eb2e8f9f7 21255 #define RTC_TAMP1PCTL_TRIEN_Msk (0x1ul << RTC_TAMP1PCTL_TRIEN_Pos) /*!< RTC TAMP1PCTL: TRIEN Mask */
<> 144:ef7eb2e8f9f7 21256
<> 144:ef7eb2e8f9f7 21257 #define RTC_TAMP1PCTL_TYPE_Pos (3) /*!< RTC TAMP1PCTL: TYPE Position */
<> 144:ef7eb2e8f9f7 21258 #define RTC_TAMP1PCTL_TYPE_Msk (0x1ul << RTC_TAMP1PCTL_TYPE_Pos) /*!< RTC TAMP1PCTL: TYPE Mask */
<> 144:ef7eb2e8f9f7 21259
<> 144:ef7eb2e8f9f7 21260 #define RTC_TAMP1PCTL_DINOFF_Pos (4) /*!< RTC TAMP1PCTL: DINOFF Position */
<> 144:ef7eb2e8f9f7 21261 #define RTC_TAMP1PCTL_DINOFF_Msk (0x1ul << RTC_TAMP1PCTL_DINOFF_Pos) /*!< RTC TAMP1PCTL: DINOFF Mask */
<> 144:ef7eb2e8f9f7 21262
<> 144:ef7eb2e8f9f7 21263 #define RTC_LXTIPCTL_OUTLV_Pos (0) /*!< RTC LXTIPCTL: OUTLV Position */
<> 144:ef7eb2e8f9f7 21264 #define RTC_LXTIPCTL_OUTLV_Msk (0x1ul << RTC_LXTIPCTL_OUTLV_Pos) /*!< RTC LXTIPCTL: OUTLV Mask */
<> 144:ef7eb2e8f9f7 21265
<> 144:ef7eb2e8f9f7 21266 #define RTC_LXTIPCTL_OUTEN_Pos (1) /*!< RTC LXTIPCTL: OUTEN Position */
<> 144:ef7eb2e8f9f7 21267 #define RTC_LXTIPCTL_OUTEN_Msk (0x1ul << RTC_LXTIPCTL_OUTEN_Pos) /*!< RTC LXTIPCTL: OUTEN Mask */
<> 144:ef7eb2e8f9f7 21268
<> 144:ef7eb2e8f9f7 21269 #define RTC_LXTIPCTL_TRIEN_Pos (2) /*!< RTC LXTIPCTL: TRIEN Position */
<> 144:ef7eb2e8f9f7 21270 #define RTC_LXTIPCTL_TRIEN_Msk (0x1ul << RTC_LXTIPCTL_TRIEN_Pos) /*!< RTC LXTIPCTL: TRIEN Mask */
<> 144:ef7eb2e8f9f7 21271
<> 144:ef7eb2e8f9f7 21272 #define RTC_LXTIPCTL_TYPE_Pos (3) /*!< RTC LXTIPCTL: TYPE Position */
<> 144:ef7eb2e8f9f7 21273 #define RTC_LXTIPCTL_TYPE_Msk (0x1ul << RTC_LXTIPCTL_TYPE_Pos) /*!< RTC LXTIPCTL: TYPE Mask */
<> 144:ef7eb2e8f9f7 21274
<> 144:ef7eb2e8f9f7 21275 #define RTC_LXTIPCTL_DINOFF_Pos (4) /*!< RTC LXTIPCTL: DINOFF Position */
<> 144:ef7eb2e8f9f7 21276 #define RTC_LXTIPCTL_DINOFF_Msk (0x1ul << RTC_LXTIPCTL_DINOFF_Pos) /*!< RTC LXTIPCTL: DINOFF Mask */
<> 144:ef7eb2e8f9f7 21277
<> 144:ef7eb2e8f9f7 21278 #define RTC_LXTOPCTL_OUTLV_Pos (0) /*!< RTC LXTOPCTL: OUTLV Position */
<> 144:ef7eb2e8f9f7 21279 #define RTC_LXTOPCTL_OUTLV_Msk (0x1ul << RTC_LXTOPCTL_OUTLV_Pos) /*!< RTC LXTOPCTL: OUTLV Mask */
<> 144:ef7eb2e8f9f7 21280
<> 144:ef7eb2e8f9f7 21281 #define RTC_LXTOPCTL_OUTEN_Pos (1) /*!< RTC LXTOPCTL: OUTEN Position */
<> 144:ef7eb2e8f9f7 21282 #define RTC_LXTOPCTL_OUTEN_Msk (0x1ul << RTC_LXTOPCTL_OUTEN_Pos) /*!< RTC LXTOPCTL: OUTEN Mask */
<> 144:ef7eb2e8f9f7 21283
<> 144:ef7eb2e8f9f7 21284 #define RTC_LXTOPCTL_TRIEN_Pos (2) /*!< RTC LXTOPCTL: TRIEN Position */
<> 144:ef7eb2e8f9f7 21285 #define RTC_LXTOPCTL_TRIEN_Msk (0x1ul << RTC_LXTOPCTL_TRIEN_Pos) /*!< RTC LXTOPCTL: TRIEN Mask */
<> 144:ef7eb2e8f9f7 21286
<> 144:ef7eb2e8f9f7 21287 #define RTC_LXTOPCTL_TYPE_Pos (3) /*!< RTC LXTOPCTL: TYPE Position */
<> 144:ef7eb2e8f9f7 21288 #define RTC_LXTOPCTL_TYPE_Msk (0x1ul << RTC_LXTOPCTL_TYPE_Pos) /*!< RTC LXTOPCTL: TYPE Mask */
<> 144:ef7eb2e8f9f7 21289
<> 144:ef7eb2e8f9f7 21290 #define RTC_LXTOPCTL_DINOFF_Pos (4) /*!< RTC LXTOPCTL: DINOFF Position */
<> 144:ef7eb2e8f9f7 21291 #define RTC_LXTOPCTL_DINOFF_Msk (0x1ul << RTC_LXTOPCTL_DINOFF_Pos) /*!< RTC LXTOPCTL: DINOFF Mask */
<> 144:ef7eb2e8f9f7 21292
<> 144:ef7eb2e8f9f7 21293 #define RTC_TAMSK_MSEC_Pos (0) /*!< RTC TAMSK: MSEC Position */
<> 144:ef7eb2e8f9f7 21294 #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) /*!< RTC TAMSK: MSEC Mask */
<> 144:ef7eb2e8f9f7 21295
<> 144:ef7eb2e8f9f7 21296 #define RTC_TAMSK_MTENSEC_Pos (1) /*!< RTC TAMSK: MTENSEC Position */
<> 144:ef7eb2e8f9f7 21297 #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) /*!< RTC TAMSK: MTENSEC Mask */
<> 144:ef7eb2e8f9f7 21298
<> 144:ef7eb2e8f9f7 21299 #define RTC_TAMSK_MMIN_Pos (2) /*!< RTC TAMSK: MMIN Position */
<> 144:ef7eb2e8f9f7 21300 #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) /*!< RTC TAMSK: MMIN Mask */
<> 144:ef7eb2e8f9f7 21301
<> 144:ef7eb2e8f9f7 21302 #define RTC_TAMSK_MTENMIN_Pos (3) /*!< RTC TAMSK: MTENMIN Position */
<> 144:ef7eb2e8f9f7 21303 #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) /*!< RTC TAMSK: MTENMIN Mask */
<> 144:ef7eb2e8f9f7 21304
<> 144:ef7eb2e8f9f7 21305 #define RTC_TAMSK_MHR_Pos (4) /*!< RTC TAMSK: MHR Position */
<> 144:ef7eb2e8f9f7 21306 #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) /*!< RTC TAMSK: MHR Mask */
<> 144:ef7eb2e8f9f7 21307
<> 144:ef7eb2e8f9f7 21308 #define RTC_TAMSK_MTENHR_Pos (5) /*!< RTC TAMSK: MTENHR Position */
<> 144:ef7eb2e8f9f7 21309 #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) /*!< RTC TAMSK: MTENHR Mask */
<> 144:ef7eb2e8f9f7 21310
<> 144:ef7eb2e8f9f7 21311 #define RTC_CAMSK_MDAY_Pos (0) /*!< RTC CAMSK: MDAY Position */
<> 144:ef7eb2e8f9f7 21312 #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) /*!< RTC CAMSK: MDAY Mask */
<> 144:ef7eb2e8f9f7 21313
<> 144:ef7eb2e8f9f7 21314 #define RTC_CAMSK_MTENDAY_Pos (1) /*!< RTC CAMSK: MTENDAY Position */
<> 144:ef7eb2e8f9f7 21315 #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) /*!< RTC CAMSK: MTENDAY Mask */
<> 144:ef7eb2e8f9f7 21316
<> 144:ef7eb2e8f9f7 21317 #define RTC_CAMSK_MMON_Pos (2) /*!< RTC CAMSK: MMON Position */
<> 144:ef7eb2e8f9f7 21318 #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) /*!< RTC CAMSK: MMON Mask */
<> 144:ef7eb2e8f9f7 21319
<> 144:ef7eb2e8f9f7 21320 #define RTC_CAMSK_MTENMON_Pos (3) /*!< RTC CAMSK: MTENMON Position */
<> 144:ef7eb2e8f9f7 21321 #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) /*!< RTC CAMSK: MTENMON Mask */
<> 144:ef7eb2e8f9f7 21322
<> 144:ef7eb2e8f9f7 21323 #define RTC_CAMSK_MYEAR_Pos (4) /*!< RTC CAMSK: MYEAR Position */
<> 144:ef7eb2e8f9f7 21324 #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) /*!< RTC CAMSK: MYEAR Mask */
<> 144:ef7eb2e8f9f7 21325
<> 144:ef7eb2e8f9f7 21326 #define RTC_CAMSK_MTENYEAR_Pos (5) /*!< RTC CAMSK: MTENYEAR Position */
<> 144:ef7eb2e8f9f7 21327 #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) /*!< RTC CAMSK: MTENYEAR Mask */
<> 144:ef7eb2e8f9f7 21328
<> 144:ef7eb2e8f9f7 21329 /**@}*/ /* RTC_CONST */
<> 144:ef7eb2e8f9f7 21330 /**@}*/ /* end of RTC register group */
<> 144:ef7eb2e8f9f7 21331
<> 144:ef7eb2e8f9f7 21332
<> 144:ef7eb2e8f9f7 21333 /*---------------------- Smart Card Host Interface Controller -------------------------*/
<> 144:ef7eb2e8f9f7 21334 /**
<> 144:ef7eb2e8f9f7 21335 @addtogroup SC Smart Card Host Interface Controller(SC)
<> 144:ef7eb2e8f9f7 21336 Memory Mapped Structure for SC Controller
<> 144:ef7eb2e8f9f7 21337 @{ */
<> 144:ef7eb2e8f9f7 21338
<> 144:ef7eb2e8f9f7 21339 typedef struct {
<> 144:ef7eb2e8f9f7 21340
<> 144:ef7eb2e8f9f7 21341
<> 144:ef7eb2e8f9f7 21342 /**
<> 144:ef7eb2e8f9f7 21343 * DAT
<> 144:ef7eb2e8f9f7 21344 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21345 * Offset: 0x00 SC Receive and Transmit Buffer Register
<> 144:ef7eb2e8f9f7 21346 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21347 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21348 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21349 * |[0:7] |DAT |Receiving/ Transmit Buffer
<> 144:ef7eb2e8f9f7 21350 * | | |Write Operation:
<> 144:ef7eb2e8f9f7 21351 * | | |By writing data to DAT, the SC will send out an 8-bit data.
<> 144:ef7eb2e8f9f7 21352 * | | |Note: If SCEN(SC_CTL[0]) is not enabled, DAT cannot be programmed.
<> 144:ef7eb2e8f9f7 21353 * | | |Read Operation:
<> 144:ef7eb2e8f9f7 21354 * | | |By reading DAT, the SC will return an 8-bit received data.
<> 144:ef7eb2e8f9f7 21355 */
<> 144:ef7eb2e8f9f7 21356 __IO uint32_t DAT;
<> 144:ef7eb2e8f9f7 21357
<> 144:ef7eb2e8f9f7 21358 /**
<> 144:ef7eb2e8f9f7 21359 * CTL
<> 144:ef7eb2e8f9f7 21360 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21361 * Offset: 0x04 SC Control Register
<> 144:ef7eb2e8f9f7 21362 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21363 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21364 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21365 * |[0] |SCEN |SC Engine Enable Control
<> 144:ef7eb2e8f9f7 21366 * | | |Set this bit to 1 to enable SC operation.
<> 144:ef7eb2e8f9f7 21367 * | | |If this bit is cleared, SC will force all transition to IDLE state.
<> 144:ef7eb2e8f9f7 21368 * |[1] |RXOFF |RX Transition Disable Control
<> 144:ef7eb2e8f9f7 21369 * | | |0 = The receiver Enabled.
<> 144:ef7eb2e8f9f7 21370 * | | |1 = The receiver Disabled.
<> 144:ef7eb2e8f9f7 21371 * | | |Note: If AUTOCEN is enabled, this fields must be ignored.
<> 144:ef7eb2e8f9f7 21372 * |[2] |TXOFF |TX Transition Disable Control
<> 144:ef7eb2e8f9f7 21373 * | | |0 = The transceiver Enabled.
<> 144:ef7eb2e8f9f7 21374 * | | |1 = The transceiver Disabled.
<> 144:ef7eb2e8f9f7 21375 * |[3] |AUTOCEN |Auto Convention Enable Control
<> 144:ef7eb2e8f9f7 21376 * | | |0 = Auto-convention Disabled.
<> 144:ef7eb2e8f9f7 21377 * | | |1 = Auto-convention Enabled.
<> 144:ef7eb2e8f9f7 21378 * | | |When hardware receives TS in answer to reset state and the TS is direct convention, CONSEL(SC_CTL[5:4]) will be set to 00 automatically, otherwise if the TS is inverse convention, and CONSEL (SC_CTL[5:4]) will be set to 11.
<> 144:ef7eb2e8f9f7 21379 * | | |If software enables auto convention function, the setting step must be done before Answer to Reset state and the first data must be 3B or 3F.
<> 144:ef7eb2e8f9f7 21380 * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and change the CONSEL (SC_CTL[5:4]) bits automatically.
<> 144:ef7eb2e8f9f7 21381 * | | |If the first data is not 3B or 3F, hardware will generate an interrupt INT_ACON_ERR (if ACON_ERR IE (SC_INTEN[10]) = 1 to CPU.
<> 144:ef7eb2e8f9f7 21382 * |[4:5] |CONSEL |Convention Selection
<> 144:ef7eb2e8f9f7 21383 * | | |00 = Direct convention.
<> 144:ef7eb2e8f9f7 21384 * | | |01 = Reserved.
<> 144:ef7eb2e8f9f7 21385 * | | |10 = Reserved.
<> 144:ef7eb2e8f9f7 21386 * | | |11 = Inverse convention.
<> 144:ef7eb2e8f9f7 21387 * | | |Note: If AUTOCEN(SC_CTL[3]) enabled, this fields are ignored.
<> 144:ef7eb2e8f9f7 21388 * |[6:7] |RXTRGLV |Rx Buffer Trigger Level
<> 144:ef7eb2e8f9f7 21389 * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDA_IF will be set (if IER [RDAIENN] is enabled, an interrupt will be generated).
<> 144:ef7eb2e8f9f7 21390 * | | |00 = INTR_RDA Trigger Level with 01 Bytes.
<> 144:ef7eb2e8f9f7 21391 * | | |01 = INTR_RDA Trigger Level with 02 Bytes.
<> 144:ef7eb2e8f9f7 21392 * | | |10 = INTR_RDA Trigger Level with 03 Bytees.
<> 144:ef7eb2e8f9f7 21393 * | | |11 = Reserved.
<> 144:ef7eb2e8f9f7 21394 * |[8:12] |BGT |Block Guard Time (BGT)
<> 144:ef7eb2e8f9f7 21395 * | | |Block guard time means the minimum bit length between the leading edges of two consecutive characters between different transfer directions.
<> 144:ef7eb2e8f9f7 21396 * | | |This field indicates the counter for the bit length of block guard time.
<> 144:ef7eb2e8f9f7 21397 * | | |According to ISO7816-3, in T = 0 mode, software must fill 15 (real block guard time = 16.5) to this field; in T = 1 mode, software must fill 21 (real block guard time = 22.5) to it.
<> 144:ef7eb2e8f9f7 21398 * | | |In RX mode, software can enable SC_ALTCTL [RXBGTEN] to detect the first coming character timing.
<> 144:ef7eb2e8f9f7 21399 * | | |If the incoming data timing less than BGT, an interrupt will be generated.
<> 144:ef7eb2e8f9f7 21400 * | | |Note: The real block guard time is BGT + 1.
<> 144:ef7eb2e8f9f7 21401 * |[13:14] |TMRSEL |Timer Selection
<> 144:ef7eb2e8f9f7 21402 * | | |00 = All internal timer function Disabled.
<> 144:ef7eb2e8f9f7 21403 * | | |01 = Internal 24 bit timer Enabled.
<> 144:ef7eb2e8f9f7 21404 * | | |Software can configure it by setting SC_TMRCTL0 [23:0].
<> 144:ef7eb2e8f9f7 21405 * | | |SC_TMRCTL1 and SC_TMRCTL2 will be ignored in this mode.
<> 144:ef7eb2e8f9f7 21406 * | | |10 = internal 24 bit timer and 8 bit internal timer Enabled.
<> 144:ef7eb2e8f9f7 21407 * | | |Software can configure the 24 bit timer by setting SC_TMRCTL0 [23:0] and configure the 8 bit timer by setting SC_TMRCTL1[7:0].
<> 144:ef7eb2e8f9f7 21408 * | | |SC_TMRCTL2 will be ignored in this mode.
<> 144:ef7eb2e8f9f7 21409 * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled.
<> 144:ef7eb2e8f9f7 21410 * | | |Software can configure them by setting SC_TMRCTL0 [23:0], SC_TMRCTL1 [7:0] and SC_TMRCTL2 [7:0].
<> 144:ef7eb2e8f9f7 21411 * |[15] |NSB |Stop Bit Length
<> 144:ef7eb2e8f9f7 21412 * | | |This field indicates the length of stop bit.
<> 144:ef7eb2e8f9f7 21413 * | | |0 = The stop bit length is 2 ETU.
<> 144:ef7eb2e8f9f7 21414 * | | |1= The stop bit length is 1 ETU.
<> 144:ef7eb2e8f9f7 21415 * | | |Note: The default stop bit length is 2. SMC and UART adopts NSB to program the stop bit length
<> 144:ef7eb2e8f9f7 21416 * |[16:18] |RXRTY |RX Error Retry Count Number
<> 144:ef7eb2e8f9f7 21417 * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred
<> 144:ef7eb2e8f9f7 21418 * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number.
<> 144:ef7eb2e8f9f7 21419 * | | |Note2: This field cannot be changed when RXRTYEN enabled.
<> 144:ef7eb2e8f9f7 21420 * | | |The change flow is to disable RX_ETRTRY_EN first and then fill in new retry value.
<> 144:ef7eb2e8f9f7 21421 * |[19] |RXRTYEN |RX Error Retry Enable Control
<> 144:ef7eb2e8f9f7 21422 * | | |This bit enables receiver retry function when parity error has occurred.
<> 144:ef7eb2e8f9f7 21423 * | | |1 = RX error retry function Enabled.
<> 144:ef7eb2e8f9f7 21424 * | | |0 = RX error retry function Disabled.
<> 144:ef7eb2e8f9f7 21425 * | | |Note: Software must fill in the RXRTY value before enabling this bit.
<> 144:ef7eb2e8f9f7 21426 * |[20:22] |TXRTY |TX Error Retry Count Number
<> 144:ef7eb2e8f9f7 21427 * | | |This field indicates the maximum number of transmitter retries that are allowed when parity error has occurred.
<> 144:ef7eb2e8f9f7 21428 * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number.
<> 144:ef7eb2e8f9f7 21429 * | | |Note2: This field cannot be changed when TXRTYEN enabled.
<> 144:ef7eb2e8f9f7 21430 * | | |The change flow is to disable TX_ETRTRY_EN first and then fill in new retry value.
<> 144:ef7eb2e8f9f7 21431 * |[23] |TXRTYEN |TX Error Retry Enable Control
<> 144:ef7eb2e8f9f7 21432 * | | |This bit enables transmitter retry function when parity error has occurred.
<> 144:ef7eb2e8f9f7 21433 * | | |0 = TX error retry function Disabled.
<> 144:ef7eb2e8f9f7 21434 * | | |1 = TX error retry function Enabled.
<> 144:ef7eb2e8f9f7 21435 * |[24:25] |CDDBSEL |Card Detect De-Bounce Selection
<> 144:ef7eb2e8f9f7 21436 * | | |This field indicates the card detect de-bounce selection.
<> 144:ef7eb2e8f9f7 21437 * | | |00 = De-bounce sample card insert once per 384 (128 * 3) engine clocks and de-bounce sample card removal once per 128 engine clocks.
<> 144:ef7eb2e8f9f7 21438 * | | |01 = De-bounce sample card insert once per 192 (64 * 3) engine clocks and de-bounce sample card removal once per 64 engine clocks.
<> 144:ef7eb2e8f9f7 21439 * | | |10 = De-bounce sample card insert once per 96 (32 * 3) engine clocks and de-bounce sample card removal once per 32 engine clocks.
<> 144:ef7eb2e8f9f7 21440 * | | |11 = De-bounce sample card insert once per 48 (16 * 3) engine clocks and de-bounce sample card removal once per 16 engine clocks.
<> 144:ef7eb2e8f9f7 21441 * |[26] |CDLV |Card Detect Level
<> 144:ef7eb2e8f9f7 21442 * | | |0 = When hardware detects the card detect pin from high to low, it indicates a card is detected.
<> 144:ef7eb2e8f9f7 21443 * | | |1 = When hardware detects the card detect pin from low to high, it indicates a card is detected.
<> 144:ef7eb2e8f9f7 21444 * | | |Note: Software must select card detect level before Smart Card engine enabled.
<> 144:ef7eb2e8f9f7 21445 * |[30] |SYNC |SYNC Flag Indicator
<> 144:ef7eb2e8f9f7 21446 * | | |Due to synchronization, software should check this bit before writing a new value to RXRTY and TXRTY.
<> 144:ef7eb2e8f9f7 21447 * | | |0 = synchronizing is completion, user can write new data to SC_PINCTL register.
<> 144:ef7eb2e8f9f7 21448 * | | |1 = Last value is synchronizing.
<> 144:ef7eb2e8f9f7 21449 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 21450 */
<> 144:ef7eb2e8f9f7 21451 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 21452
<> 144:ef7eb2e8f9f7 21453 /**
<> 144:ef7eb2e8f9f7 21454 * ALTCTL
<> 144:ef7eb2e8f9f7 21455 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21456 * Offset: 0x08 SC Alternate Control Register
<> 144:ef7eb2e8f9f7 21457 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21458 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21459 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21460 * |[0] |TXRST |TX Software Reset
<> 144:ef7eb2e8f9f7 21461 * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared.
<> 144:ef7eb2e8f9f7 21462 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 21463 * | | |1 = Reset the TX internal state machine and pointers.
<> 144:ef7eb2e8f9f7 21464 * | | |Note: This bit will be auto cleared after reset is complete.
<> 144:ef7eb2e8f9f7 21465 * |[1] |RXRST |Rx Software Reset
<> 144:ef7eb2e8f9f7 21466 * | | |When RXRST is set, all the bytes in the receiver buffer and Rx internal state machine will be cleared.
<> 144:ef7eb2e8f9f7 21467 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 21468 * | | |1 = Reset the Rx internal state machine and pointers.
<> 144:ef7eb2e8f9f7 21469 * | | |Note: This bit will be auto cleared after reset is complete.
<> 144:ef7eb2e8f9f7 21470 * |[2] |DACTEN |Deactivation Sequence Generator Enable Control
<> 144:ef7eb2e8f9f7 21471 * | | |This bit enables SC controller to initiate the card by deactivation sequence
<> 144:ef7eb2e8f9f7 21472 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 21473 * | | |1 = Deactivation sequence generator Enabled.
<> 144:ef7eb2e8f9f7 21474 * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
<> 144:ef7eb2e8f9f7 21475 * | | |Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
<> 144:ef7eb2e8f9f7 21476 * | | |So don't fill this bit, TXRST, and RXRST at the same time.
<> 144:ef7eb2e8f9f7 21477 * | | |Note3: If SC_CTL [SCEN] not enabled, this filed cannot be programmed.
<> 144:ef7eb2e8f9f7 21478 * |[3] |ACTEN |Activation Sequence Generator Enable Control
<> 144:ef7eb2e8f9f7 21479 * | | |This bit enables SC controller to initiate the card by activation sequence
<> 144:ef7eb2e8f9f7 21480 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 21481 * | | |1 = Activation sequence generator Enabled.
<> 144:ef7eb2e8f9f7 21482 * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
<> 144:ef7eb2e8f9f7 21483 * | | |Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
<> 144:ef7eb2e8f9f7 21484 * | | |Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 144:ef7eb2e8f9f7 21485 * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Control
<> 144:ef7eb2e8f9f7 21486 * | | |This bit enables SC controller to initiate the card by warm reset sequence
<> 144:ef7eb2e8f9f7 21487 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 21488 * | | |1 = Warm reset sequence generator Enabled.
<> 144:ef7eb2e8f9f7 21489 * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the INITIF(SC_INTSTS[8]) will be set to 1.
<> 144:ef7eb2e8f9f7 21490 * | | |Note2: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST, and RXRST at the same time.
<> 144:ef7eb2e8f9f7 21491 * | | |Note3: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 144:ef7eb2e8f9f7 21492 * |[5] |CNTEN0 |Internal Timer0 Start Enable Control
<> 144:ef7eb2e8f9f7 21493 * | | |This bit enables Timer 0 to start counting.
<> 144:ef7eb2e8f9f7 21494 * | | |Software can fill 0 to stop it and set 1 to reload and count.
<> 144:ef7eb2e8f9f7 21495 * | | |0 = Stops counting.
<> 144:ef7eb2e8f9f7 21496 * | | |1 = Start counting.
<> 144:ef7eb2e8f9f7 21497 * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SC_CTL[14:13]) = 01.
<> 144:ef7eb2e8f9f7 21498 * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL0[26] = 0), this bit will be auto-cleared by hardware.
<> 144:ef7eb2e8f9f7 21499 * | | |Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
<> 144:ef7eb2e8f9f7 21500 * | | |So don't fill this bit, TXRST and RXRST at the same time.
<> 144:ef7eb2e8f9f7 21501 * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 144:ef7eb2e8f9f7 21502 * |[6] |CNTEN1 |Internal Timer1 Start Enable Control
<> 144:ef7eb2e8f9f7 21503 * | | |This bit enables Timer 1 to start counting.
<> 144:ef7eb2e8f9f7 21504 * | | |Software can fill 0 to stop it and set 1 to reload and count.
<> 144:ef7eb2e8f9f7 21505 * | | |0 = Stops counting.
<> 144:ef7eb2e8f9f7 21506 * | | |1 = Start counting.
<> 144:ef7eb2e8f9f7 21507 * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 10 or TMRSEL(SC_CTL[14:13]) = 11.
<> 144:ef7eb2e8f9f7 21508 * | | |Don't filled CNTEN1 when SC_CTL([TMRSEL] = 00 or SC_CTL[TMRSEL] = 01.
<> 144:ef7eb2e8f9f7 21509 * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL1[26] = 0), this bit will be auto-cleared by hardware.
<> 144:ef7eb2e8f9f7 21510 * | | |Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]), so don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
<> 144:ef7eb2e8f9f7 21511 * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 144:ef7eb2e8f9f7 21512 * |[7] |CNTEN2 |Internal Timer2 Start Enable Control
<> 144:ef7eb2e8f9f7 21513 * | | |This bit enables Timer 2 to start counting.
<> 144:ef7eb2e8f9f7 21514 * | | |Software can fill 0 to stop it and set 1 to reload and count.
<> 144:ef7eb2e8f9f7 21515 * | | |0 = Stops counting.
<> 144:ef7eb2e8f9f7 21516 * | | |1 = Start counting.
<> 144:ef7eb2e8f9f7 21517 * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SC_CTL[14:13]) = 11.
<> 144:ef7eb2e8f9f7 21518 * | | |Don't filled CNTEN2 when TMRSEL(SC_CTL[14:13]) = 00 or TMRSEL(SC_CTL[14:13]) = 01 or TMRSEL(SC_CTL[14:13]) = 10.
<> 144:ef7eb2e8f9f7 21519 * | | |Note2: If the operation mode is not in auto-reload mode (SC_TMRCTL2[26] = 0), this bit will be auto-cleared by hardware.
<> 144:ef7eb2e8f9f7 21520 * | | |Note3: This field will be cleared by TXRST(SC_ALTCTL[0]) and RXRST(SC_ALTCTL[1]).
<> 144:ef7eb2e8f9f7 21521 * | | |So don't fill this bit, TXRST(SC_ALTCTL[0]), and RXRST(SC_ALTCTL[1]) at the same time.
<> 144:ef7eb2e8f9f7 21522 * | | |Note4: If SCEN(SC_CTL[0]) is not enabled, this filed cannot be programmed.
<> 144:ef7eb2e8f9f7 21523 * |[8:9] |INITSEL |Initial Timing Selection
<> 144:ef7eb2e8f9f7 21524 * | | |This fields indicates the timing of hardware initial state (activation or warm-reset or deactivation).
<> 144:ef7eb2e8f9f7 21525 * | | |Unit: SC clock
<> 144:ef7eb2e8f9f7 21526 * | | |Activation: refer to SC Activation Sequence in Figure 5.19-4.
<> 144:ef7eb2e8f9f7 21527 * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 5.19-5
<> 144:ef7eb2e8f9f7 21528 * | | |Deactivation: refer to Deactivation Sequence in Figure 5.19-6
<> 144:ef7eb2e8f9f7 21529 * |[11] |ADACEN |Auto Deactivation When Card Removal
<> 144:ef7eb2e8f9f7 21530 * | | |0 = Auto deactivation Disabled when hardware detected the card removal.
<> 144:ef7eb2e8f9f7 21531 * | | |1 = Auto deactivation Enabled when hardware detected the card removal.
<> 144:ef7eb2e8f9f7 21532 * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence (if this bit is set).
<> 144:ef7eb2e8f9f7 21533 * | | |If this process completes, hardware will generate an interrupt INT_INIT to CPU.
<> 144:ef7eb2e8f9f7 21534 * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Control
<> 144:ef7eb2e8f9f7 21535 * | | |0 = Receiver block guard time function Disabled.
<> 144:ef7eb2e8f9f7 21536 * | | |1 = Receiver block guard time function Enabled.
<> 144:ef7eb2e8f9f7 21537 * |[13] |ACTSTS0 |Internal Timer0 Active State (Read Only)
<> 144:ef7eb2e8f9f7 21538 * | | |This bit indicates the timer counter status of timer0.
<> 144:ef7eb2e8f9f7 21539 * | | |0 = Timer0 is not active.
<> 144:ef7eb2e8f9f7 21540 * | | |1 = Timer0 is active.
<> 144:ef7eb2e8f9f7 21541 * |[14] |ACTSTS1 |Internal Timer1 Active State (Read Only)
<> 144:ef7eb2e8f9f7 21542 * | | |This bit indicates the timer counter status of timer1.
<> 144:ef7eb2e8f9f7 21543 * | | |0 = Timer1 is not active.
<> 144:ef7eb2e8f9f7 21544 * | | |1 = Timer1 is active.
<> 144:ef7eb2e8f9f7 21545 * |[15] |ACTSTS2 |Internal Timer2 Active State (Read Only)
<> 144:ef7eb2e8f9f7 21546 * | | |This bit indicates the timer counter status of timer2.
<> 144:ef7eb2e8f9f7 21547 * | | |0 = Timer2 is not active.
<> 144:ef7eb2e8f9f7 21548 * | | |1 = Timer2 is active.
<> 144:ef7eb2e8f9f7 21549 */
<> 144:ef7eb2e8f9f7 21550 __IO uint32_t ALTCTL;
<> 144:ef7eb2e8f9f7 21551
<> 144:ef7eb2e8f9f7 21552 /**
<> 144:ef7eb2e8f9f7 21553 * EGT
<> 144:ef7eb2e8f9f7 21554 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21555 * Offset: 0x0C SC Extend Guard Time Register
<> 144:ef7eb2e8f9f7 21556 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21557 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21558 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21559 * |[0:7] |EGT |Extended Guard Time
<> 144:ef7eb2e8f9f7 21560 * | | |This field indicates the extended guard timer value.
<> 144:ef7eb2e8f9f7 21561 * | | |Note: The counter is ETU base and the real extended guard time is EGT.
<> 144:ef7eb2e8f9f7 21562 */
<> 144:ef7eb2e8f9f7 21563 __IO uint32_t EGT;
<> 144:ef7eb2e8f9f7 21564
<> 144:ef7eb2e8f9f7 21565 /**
<> 144:ef7eb2e8f9f7 21566 * RXTOUT
<> 144:ef7eb2e8f9f7 21567 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21568 * Offset: 0x10 SC Receive Buffer Time-out Register
<> 144:ef7eb2e8f9f7 21569 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21570 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21571 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21572 * |[0:8] |RFTM |SC Receiver Buffer Time-Out (ETU Base)
<> 144:ef7eb2e8f9f7 21573 * | | |The time-out counter resets and starts counting whenever the RX buffer received a new data word.
<> 144:ef7eb2e8f9f7 21574 * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by reading SC_DAT buffer, a receiver time-out interrupt INT_RTMR will be generated(if RXTOIF(SC_INTEN[9]) = 1 ).
<> 144:ef7eb2e8f9f7 21575 * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5
<> 144:ef7eb2e8f9f7 21576 * | | |Note2: Fill all 0 to this field indicates to disable this function.
<> 144:ef7eb2e8f9f7 21577 */
<> 144:ef7eb2e8f9f7 21578 __IO uint32_t RXTOUT;
<> 144:ef7eb2e8f9f7 21579
<> 144:ef7eb2e8f9f7 21580 /**
<> 144:ef7eb2e8f9f7 21581 * ETUCTL
<> 144:ef7eb2e8f9f7 21582 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21583 * Offset: 0x14 SC ETU Control Register
<> 144:ef7eb2e8f9f7 21584 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21585 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21586 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21587 * |[0:11] |ETURDIV |ETU Rate Divider
<> 144:ef7eb2e8f9f7 21588 * | | |The field indicates the clock rate divider.
<> 144:ef7eb2e8f9f7 21589 * | | |The real ETU is ETURDIV + 1.
<> 144:ef7eb2e8f9f7 21590 * | | |Note: Software can configure this field, but this field must be greater than 0x004.
<> 144:ef7eb2e8f9f7 21591 * |[15] |CMPEN |Compensation Mode Enable Control
<> 144:ef7eb2e8f9f7 21592 * | | |This bit enables clock compensation function.
<> 144:ef7eb2e8f9f7 21593 * | | |When this bit enabled, hardware will alternate between n clock cycles and n-1 clock cycles, where n is the value to be written into the ETURDIV .
<> 144:ef7eb2e8f9f7 21594 * | | |0 = Compensation function Disabled.
<> 144:ef7eb2e8f9f7 21595 * | | |1 = Compensation function Enabled.
<> 144:ef7eb2e8f9f7 21596 */
<> 144:ef7eb2e8f9f7 21597 __IO uint32_t ETUCTL;
<> 144:ef7eb2e8f9f7 21598
<> 144:ef7eb2e8f9f7 21599 /**
<> 144:ef7eb2e8f9f7 21600 * INTEN
<> 144:ef7eb2e8f9f7 21601 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21602 * Offset: 0x18 SC Interrupt Enable Control Register
<> 144:ef7eb2e8f9f7 21603 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21604 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21605 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21606 * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21607 * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt enable.
<> 144:ef7eb2e8f9f7 21608 * | | |0 = Receive data reach trigger level interrupt Disabled.
<> 144:ef7eb2e8f9f7 21609 * | | |1 = Receive data reach trigger level interrupt Enabled.
<> 144:ef7eb2e8f9f7 21610 * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21611 * | | |This field is used for transmit buffer empty interrupt enable.
<> 144:ef7eb2e8f9f7 21612 * | | |0 = Transmit buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 21613 * | | |1 = Transmit buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 21614 * |[2] |TERRIEN |Transfer Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21615 * | | |This field is used for transfer error interrupt enable.
<> 144:ef7eb2e8f9f7 21616 * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5]), parity error PEF(SC_STATUS[4]), receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_STATUS[30].
<> 144:ef7eb2e8f9f7 21617 * | | |0 = Transfer error interrupt Disabled.
<> 144:ef7eb2e8f9f7 21618 * | | |1 = Transfer error interrupt Enabled.
<> 144:ef7eb2e8f9f7 21619 * |[3] |TMR0IEN |Timer0 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21620 * | | |This field is used to enable TMR0 interrupt enable.
<> 144:ef7eb2e8f9f7 21621 * | | |0 = Timer0 interrupt Disabled.
<> 144:ef7eb2e8f9f7 21622 * | | |1 = Timer0 interrupt Enabled.
<> 144:ef7eb2e8f9f7 21623 * |[4] |TMR1IEN |Timer1 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21624 * | | |This field is used to enable the TMR1 interrupt.
<> 144:ef7eb2e8f9f7 21625 * | | |0 = Timer1 interrupt Disabled.
<> 144:ef7eb2e8f9f7 21626 * | | |1 = Timer1 interrupt Enabled.
<> 144:ef7eb2e8f9f7 21627 * |[5] |TMR2IEN |Timer2 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21628 * | | |This field is used for TMR2 interrupt enable.
<> 144:ef7eb2e8f9f7 21629 * | | |0 = Timer2 interrupt Disabled.
<> 144:ef7eb2e8f9f7 21630 * | | |1 = Timer2 interrupt Enabled.
<> 144:ef7eb2e8f9f7 21631 * |[6] |BGTIEN |Block Guard Time Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21632 * | | |This field is used for block guard time interrupt enable.
<> 144:ef7eb2e8f9f7 21633 * | | |0 = Block guard time Disabled.
<> 144:ef7eb2e8f9f7 21634 * | | |1 = Block guard time Enabled.
<> 144:ef7eb2e8f9f7 21635 * |[7] |CDIEN |Card Detect Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21636 * | | |This field is used for card detect interrupt enable. The card detect status is CINSERT(SC_STATUS[12])
<> 144:ef7eb2e8f9f7 21637 * | | |0 = Card detect interrupt Disabled.
<> 144:ef7eb2e8f9f7 21638 * | | |1 = Card detect interrupt Enabled.
<> 144:ef7eb2e8f9f7 21639 * |[8] |INITIEN |Initial End Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21640 * | | |This field is used for activation (ACTEN(SC_ALTCTL[3] = 1)), deactivation (DACTEN SC_ALTCTL[2] = 1) and warm reset (SC_ALTCTL [WARSTEN]) sequence interrupt enable.
<> 144:ef7eb2e8f9f7 21641 * | | |0 = Initial end interrupt Disabled.
<> 144:ef7eb2e8f9f7 21642 * | | |1 = Initial end interrupt Enabled.
<> 144:ef7eb2e8f9f7 21643 * |[9] |RXTOIF |Receiver Buffer Time-Out Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21644 * | | |This field is used for receiver buffer time-out interrupt enable.
<> 144:ef7eb2e8f9f7 21645 * | | |0 = Receiver buffer time-out interrupt Disabled.
<> 144:ef7eb2e8f9f7 21646 * | | |1 = Receiver buffer time-out interrupt Enabled.
<> 144:ef7eb2e8f9f7 21647 * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 21648 * | | |This field is used for auto-convention error interrupt enable.
<> 144:ef7eb2e8f9f7 21649 * | | |0 = Auto-convention error interrupt Disabled.
<> 144:ef7eb2e8f9f7 21650 * | | |1 = Auto-convention error interrupt Enabled.
<> 144:ef7eb2e8f9f7 21651 */
<> 144:ef7eb2e8f9f7 21652 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 21653
<> 144:ef7eb2e8f9f7 21654 /**
<> 144:ef7eb2e8f9f7 21655 * INTSTS
<> 144:ef7eb2e8f9f7 21656 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21657 * Offset: 0x1C SC Interrupt Status Register
<> 144:ef7eb2e8f9f7 21658 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21659 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21660 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21661 * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21662 * | | |This field is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
<> 144:ef7eb2e8f9f7 21663 * | | |Note: This field is the status flag of received data reaching RXTRGLV (SC_CTL[7:6]).
<> 144:ef7eb2e8f9f7 21664 * | | |If software reads data from SC_DAT and receiver buffer data byte number is less than RXTRGLV (SC_CTL[7:6]), this bit will be cleared automatically.
<> 144:ef7eb2e8f9f7 21665 * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21666 * | | |This field is used for transmit buffer empty interrupt status flag.
<> 144:ef7eb2e8f9f7 21667 * | | |Note: This field is the status flag of transmit buffer empty state.
<> 144:ef7eb2e8f9f7 21668 * | | |If software wants to clear this bit, software must write data to SC_DAT bufferand then this bit will be cleared automatically.
<> 144:ef7eb2e8f9f7 21669 * |[2] |TERRIF |Transfer Error Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21670 * | | |This field is used for transfer error interrupt status flag.
<> 144:ef7eb2e8f9f7 21671 * | | |The transfer error states is at SC_STATUS register which includes receiver break error BEF(SC_STATUS[6]), frame error FEF(SC_STATUS[5], parity error PEF(SC_STATUS[4] and receiver buffer overflow error RXOV(SC_STATUS[0]), transmit buffer overflow error TXOVER(SC_STATUS[8]), receiver retry over limit error RXOVERR(SC_STATUS[22] and transmitter retry over limit error TXOVERR(SC_SC[30]).
<> 144:ef7eb2e8f9f7 21672 * | | |Note: This field is the status flag of BEF(SC_STATUS[6]), FEF(SC_STATUS[5], PEF(SC_STATUS[4], RXOV(SC_STATUS[0]), TXOVER(SC_STATUS[8]), RXOVERR(SC_STATUS[22] or TXOVERR(SC_SC[30]).
<> 144:ef7eb2e8f9f7 21673 * | | |So, if software wants to clear this bit, software must write 1 to each field.
<> 144:ef7eb2e8f9f7 21674 * |[3] |TMR0IF |Timer0 Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21675 * | | |This field is used for TMR0 interrupt status flag.
<> 144:ef7eb2e8f9f7 21676 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21677 * |[4] |TMR1IF |Timer1 Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21678 * | | |This field is used for TMR1 interrupt status flag.
<> 144:ef7eb2e8f9f7 21679 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21680 * |[5] |TMR2IF |Timer2 Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21681 * | | |This field is used for TMR2 interrupt status flag.
<> 144:ef7eb2e8f9f7 21682 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21683 * |[6] |BGTIF |Block Guard Time Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21684 * | | |This field is used for block guard time interrupt status flag.
<> 144:ef7eb2e8f9f7 21685 * | | |Note1: This bit is valid when RXBGTEN (SC_ALTCTL[12]) is enabled.
<> 144:ef7eb2e8f9f7 21686 * | | |Note2: This bit is read only, but it can be cleared by writing "1" to it.
<> 144:ef7eb2e8f9f7 21687 * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21688 * | | |This field is used for card detect interrupt status flag.
<> 144:ef7eb2e8f9f7 21689 * | | |The card detect status is CINSERT (SC_STATUS[12])] and CREMOVE(SC_STATUS[11]).
<> 144:ef7eb2e8f9f7 21690 * | | |Note: This field is the status flag of CINSERT SC_STATUS[12]) SC_PINCTL[CINSERT] or CREMOVE(SC_STATUS[11])].
<> 144:ef7eb2e8f9f7 21691 * | | |So if software wants to clear this bit, software must write 1 to this field.
<> 144:ef7eb2e8f9f7 21692 * |[8] |INITIF |Initial End Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21693 * | | |This field is used for activation (ACTEN(SC_ALTCTL[3])), deactivation (DACTEN (SC_ALTCTL[2])) and warm reset (WARSTEN (SC_ALTCTL[4])) sequence interrupt status flag.
<> 144:ef7eb2e8f9f7 21694 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21695 * |[9] |RBTOIF |Receiver Buffer Time-Out Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21696 * | | |This field is used for receiver buffer time-out interrupt status flag.
<> 144:ef7eb2e8f9f7 21697 * | | |Note: This field is the status flag of receiver buffer time-out state.
<> 144:ef7eb2e8f9f7 21698 * | | |If software wants to clear this bit, software must read all receiver buffer remaining data by reading SC_DAT buffer,.
<> 144:ef7eb2e8f9f7 21699 * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21700 * | | |This field indicates auto convention sequence error.
<> 144:ef7eb2e8f9f7 21701 * | | |If the received TS at ATR state is neither 3B nor 3F, this bit will be set.
<> 144:ef7eb2e8f9f7 21702 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21703 */
<> 144:ef7eb2e8f9f7 21704 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 21705
<> 144:ef7eb2e8f9f7 21706 /**
<> 144:ef7eb2e8f9f7 21707 * STATUS
<> 144:ef7eb2e8f9f7 21708 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21709 * Offset: 0x20 SC Status Register
<> 144:ef7eb2e8f9f7 21710 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21711 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21712 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21713 * |[0] |RXOV |RX Overflow Error Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21714 * | | |This bit is set when RX buffer overflow.
<> 144:ef7eb2e8f9f7 21715 * | | |If the number of received bytes is greater than Rx Buffer size (4 bytes), this bit will be set.
<> 144:ef7eb2e8f9f7 21716 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21717 * |[1] |RXEMPTY |Receiver Buffer Empty Status Flag(Read Only)
<> 144:ef7eb2e8f9f7 21718 * | | |This bit indicates RX buffer empty or not.
<> 144:ef7eb2e8f9f7 21719 * | | |When the last byte of Rx buffer has been read by CPU, hardware sets this bit high.
<> 144:ef7eb2e8f9f7 21720 * | | |It will be cleared when SC receives any new data.
<> 144:ef7eb2e8f9f7 21721 * |[2] |RXFULL |Receiver Buffer Full Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21722 * | | |This bit indicates RX buffer full or not.
<> 144:ef7eb2e8f9f7 21723 * | | |This bit is set when RX pointer is equal to 4, otherwise it is cleared by hardware.
<> 144:ef7eb2e8f9f7 21724 * |[4] |PEF |Receiver Parity Error Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21725 * | | |This bit is set to logic 1 whenever the received character does not have a valid
<> 144:ef7eb2e8f9f7 21726 * | | |"parity bit".
<> 144:ef7eb2e8f9f7 21727 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21728 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
<> 144:ef7eb2e8f9f7 21729 * |[5] |FEF |Receiver Frame Error Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21730 * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0).
<> 144:ef7eb2e8f9f7 21731 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21732 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
<> 144:ef7eb2e8f9f7 21733 * |[6] |BEF |Receiver Break Error Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21734 * | | |This bit is set to a logic 1 whenever the received data input (RX) held in the "spacing state" (logic 0) is longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits).
<> 144:ef7eb2e8f9f7 21735 * | | |.
<> 144:ef7eb2e8f9f7 21736 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21737 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN(SC_CTL[19]) , hardware will not set this flag.
<> 144:ef7eb2e8f9f7 21738 * |[8] |TXOV |TX Overflow Error Interrupt Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21739 * | | |If TX buffer is full, an additional write to SC_DAT will cause this bit be set to "1" by hardware.
<> 144:ef7eb2e8f9f7 21740 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21741 * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21742 * | | |This bit indicates TX buffer empty or not.
<> 144:ef7eb2e8f9f7 21743 * | | |When the last byte of TX buffer has been transferred to Transmitter Shift Register, hardware sets this bit high.
<> 144:ef7eb2e8f9f7 21744 * | | |It will be cleared when writing data into SC_DAT (TX buffer not empty).
<> 144:ef7eb2e8f9f7 21745 * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21746 * | | |This bit indicates TX buffer full or not.
<> 144:ef7eb2e8f9f7 21747 * | | |This bit is set when TX pointer is equal to 4, otherwise is cleared by hardware.
<> 144:ef7eb2e8f9f7 21748 * |[11] |CREMOVE |Card Detect Removal Status Of SC_CD Pin (Read Only)
<> 144:ef7eb2e8f9f7 21749 * | | |This bit is set whenever card has been removal.
<> 144:ef7eb2e8f9f7 21750 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 21751 * | | |1 = Card removed.
<> 144:ef7eb2e8f9f7 21752 * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
<> 144:ef7eb2e8f9f7 21753 * | | |Note2: Card detect engine will start after SCEN (SC_CTL[0])set.
<> 144:ef7eb2e8f9f7 21754 * |[12] |CINSERT |Card Detect Insert Status Of SC_CD Pin (Read Only)
<> 144:ef7eb2e8f9f7 21755 * | | |This bit is set whenever card has been inserted.
<> 144:ef7eb2e8f9f7 21756 * | | |0 = No effect.1 = Card insert.
<> 144:ef7eb2e8f9f7 21757 * | | |Note1: This bit is read only, but it can be cleared by writing "1" to it.
<> 144:ef7eb2e8f9f7 21758 * | | |Note2: The card detect engine will start after SCEN (SC_CTL[0]) set.
<> 144:ef7eb2e8f9f7 21759 * |[13] |CDPINSTS |Card Detect Status Of SC_CD Pin Status (Read Only)
<> 144:ef7eb2e8f9f7 21760 * | | |This bit is the pin status flag of SC_CD
<> 144:ef7eb2e8f9f7 21761 * | | |0 = The SC_CD pin state at low.
<> 144:ef7eb2e8f9f7 21762 * | | |1 = The SC_CD pin state at high.
<> 144:ef7eb2e8f9f7 21763 * |[16:17] |RXPOINT |Receiver Buffer Pointer Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21764 * | | |This field indicates the RX buffer pointer status flag.
<> 144:ef7eb2e8f9f7 21765 * | | |When SC receives one byte from external device, RXPOINT(SC_STATUS[17:16]) increases one.
<> 144:ef7eb2e8f9f7 21766 * | | |When one byte of RX buffer is read by CPU, RXPOINT(SC_STATUS[17:16]) decreases one.
<> 144:ef7eb2e8f9f7 21767 * |[21] |RXRERR |Receiver Retry Error (Read Only)
<> 144:ef7eb2e8f9f7 21768 * | | |This bit is set by hardware when RX has any error and retries transfer.
<> 144:ef7eb2e8f9f7 21769 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21770 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
<> 144:ef7eb2e8f9f7 21771 * | | |Note3: If CPU enables receiver retry function by setting RXRTYEN (SC_CTL[19]) , the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
<> 144:ef7eb2e8f9f7 21772 * |[22] |RXOVERR |Receiver Over Retry Error (Read Only)
<> 144:ef7eb2e8f9f7 21773 * | | |This bit is set by hardware when RX transfer error retry over retry number limit.
<> 144:ef7eb2e8f9f7 21774 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21775 * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SC_CTL[19]), the PEF(SC_STATUS[4]) flag will be ignored (hardware will not set PEF(SC_STATUS[4])).
<> 144:ef7eb2e8f9f7 21776 * |[23] |RXACT |Receiver In Active Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21777 * | | |This bit is set by hardware when RX transfer is in active.
<> 144:ef7eb2e8f9f7 21778 * | | |This bit is cleared automatically when RX transfer is finished.
<> 144:ef7eb2e8f9f7 21779 * |[24:25] |TXPOINT |Transmit Buffer Pointer Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21780 * | | |This field indicates the TX buffer pointer status flag.
<> 144:ef7eb2e8f9f7 21781 * | | |When CPU writes data into SC_DAT, TXPOINT increases one.
<> 144:ef7eb2e8f9f7 21782 * | | |When one byte of TX Buffer is transferred to transmitter shift register, TXPOINT decreases one.
<> 144:ef7eb2e8f9f7 21783 * |[29] |TXRERR |Transmitter Retry Error (Read Only)
<> 144:ef7eb2e8f9f7 21784 * | | |This bit is set by hardware when transmitter re-transmits.
<> 144:ef7eb2e8f9f7 21785 * | | |Note1: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21786 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU.
<> 144:ef7eb2e8f9f7 21787 * |[30] |TXOVERR |Transmitter Over Retry Error (Read Only)
<> 144:ef7eb2e8f9f7 21788 * | | |This bit is set by hardware when transmitter re-transmits over retry number limitation.
<> 144:ef7eb2e8f9f7 21789 * | | |Note: This bit is read only, but it can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 21790 * |[31] |TXACT |Transmit In Active Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 21791 * | | |0 = This bit is cleared automatically when TX transfer is finished or the last byte transmission has completed.
<> 144:ef7eb2e8f9f7 21792 * | | |1 = This bit is set by hardware when TX transfer is in active and the STOP bit of the last byte has been transmitted.
<> 144:ef7eb2e8f9f7 21793 */
<> 144:ef7eb2e8f9f7 21794 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 21795
<> 144:ef7eb2e8f9f7 21796 /**
<> 144:ef7eb2e8f9f7 21797 * PINCTL
<> 144:ef7eb2e8f9f7 21798 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21799 * Offset: 0x24 SC Pin Control State Register
<> 144:ef7eb2e8f9f7 21800 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21801 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21802 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21803 * |[0] |PWREN |SC_PWREN Pin Signal
<> 144:ef7eb2e8f9f7 21804 * | | |Software can set PWREN and PWRINV to decide SC_PWR pin is in high or low level.
<> 144:ef7eb2e8f9f7 21805 * | | |Write this field to drive SC_PWR pin
<> 144:ef7eb2e8f9f7 21806 * | | |Refer PWRINV description for programming SC_PWR pin voltage level.
<> 144:ef7eb2e8f9f7 21807 * | | |Read this field to get SC_PWR pin status.
<> 144:ef7eb2e8f9f7 21808 * | | |0 = SC_PWR pin status is low.
<> 144:ef7eb2e8f9f7 21809 * | | |1 = SC_PWR pin status is high.
<> 144:ef7eb2e8f9f7 21810 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 144:ef7eb2e8f9f7 21811 * | | |So don't fill this field when operating in these modes.
<> 144:ef7eb2e8f9f7 21812 * |[1] |SCRST |SCRST Pin Signal
<> 144:ef7eb2e8f9f7 21813 * | | |This bit is the pin status of SCRST but user can drive SCRST pin to high or low by setting this bit.
<> 144:ef7eb2e8f9f7 21814 * | | |Write this field to drive SCRST pin.
<> 144:ef7eb2e8f9f7 21815 * | | |0 = Drive SCRST pin to low.
<> 144:ef7eb2e8f9f7 21816 * | | |1 = Drive SCRST pin to high.
<> 144:ef7eb2e8f9f7 21817 * | | |Read this
<> 144:ef7eb2e8f9f7 21818 * | | |field to get SCRST pin status.
<> 144:ef7eb2e8f9f7 21819 * | | |0 = SCRST pin status is low.
<> 144:ef7eb2e8f9f7 21820 * | | |1 = SCRST pin status is high.
<> 144:ef7eb2e8f9f7 21821 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 144:ef7eb2e8f9f7 21822 * | | |So don't fill this field when operating in these modes.
<> 144:ef7eb2e8f9f7 21823 * |[6] |CLKKEEP |SC Clock Enable Control
<> 144:ef7eb2e8f9f7 21824 * | | |0 = SC clock generation Disabled.
<> 144:ef7eb2e8f9f7 21825 * | | |1 = SC clock always keeps free running.
<> 144:ef7eb2e8f9f7 21826 * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 144:ef7eb2e8f9f7 21827 * | | |So don't fill this field when operating in these modes.
<> 144:ef7eb2e8f9f7 21828 * |[9] |SCDOOUT |SC Data Output Pin
<> 144:ef7eb2e8f9f7 21829 * | | |This bit is the pin status of SCDOOUT but user can drive SCDOOUT pin to high or low by setting this bit.
<> 144:ef7eb2e8f9f7 21830 * | | |0 = Drive SCDOOUT pin to low.
<> 144:ef7eb2e8f9f7 21831 * | | |1 = Drive SCDOOUT pin to high.
<> 144:ef7eb2e8f9f7 21832 * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 144:ef7eb2e8f9f7 21833 * | | |So don't fill this field when SC is in these modes.
<> 144:ef7eb2e8f9f7 21834 * |[11] |PWRINV |SC_POW Pin Inverse
<> 144:ef7eb2e8f9f7 21835 * | | |This bit is used for inverse the SC_POW pin.
<> 144:ef7eb2e8f9f7 21836 * | | |There are four kinds of combination for SC_POW pin setting by PWRINV and PWREN(SC_PINCTL[0]).
<> 144:ef7eb2e8f9f7 21837 * | | |PWRINV is bit 1 and PWREN is bit 0 for SC_POW_Pin as high or low voltage selection.
<> 144:ef7eb2e8f9f7 21838 * | | |PWRINV is 0 and PWREN is 0, than SC_POW Pin output 0.
<> 144:ef7eb2e8f9f7 21839 * | | |PWRINV is 0 and PWREN is 1, than SC_POW Pin output 1.
<> 144:ef7eb2e8f9f7 21840 * | | |PWRINV is 1 and PWREN is 0, than SC_POW Pin output 1.
<> 144:ef7eb2e8f9f7 21841 * | | |PWRINV is 1 and PWREN is 1, than SC_POW Pin output 0.
<> 144:ef7eb2e8f9f7 21842 * | | |Note: Software must select PWRINV before Smart Card is enabled by SCEN (SC_CTL[0]).
<> 144:ef7eb2e8f9f7 21843 * |[16] |DATSTS |This bit is the pin status of SC_DAT
<> 144:ef7eb2e8f9f7 21844 * | | |0 = The SC_DAT pin is low.
<> 144:ef7eb2e8f9f7 21845 * | | |1 = The SC_DAT pin is high.
<> 144:ef7eb2e8f9f7 21846 * |[17] |PWRSTS |SC_PWR Pin Signal
<> 144:ef7eb2e8f9f7 21847 * | | |This bit is the pin status of SC_PWR
<> 144:ef7eb2e8f9f7 21848 * | | |0 = SC_PWR pin to low.
<> 144:ef7eb2e8f9f7 21849 * | | |1 = SC_PWR pin to high.
<> 144:ef7eb2e8f9f7 21850 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 144:ef7eb2e8f9f7 21851 * | | |This bit is not allowed to program when SC is operated at these modes.
<> 144:ef7eb2e8f9f7 21852 * |[18] |RSTSTS |SC_RST Pin Signals
<> 144:ef7eb2e8f9f7 21853 * | | |This bit is the pin status of SC_RST
<> 144:ef7eb2e8f9f7 21854 * | | |0 = SC_RST pin is low.
<> 144:ef7eb2e8f9f7 21855 * | | |1 = SC_RST pin is high.
<> 144:ef7eb2e8f9f7 21856 * | | |Note: When SC is operated at activation, warm reset or deactivation mode, this bit will be changed automatically.
<> 144:ef7eb2e8f9f7 21857 * | | |This bit is not allowed to program when SC is operated at these modes.
<> 144:ef7eb2e8f9f7 21858 * |[30] |SYNC |SYNC Flag Indicator
<> 144:ef7eb2e8f9f7 21859 * | | |Due to synchronization, software should check this bit when writing a new value to SC_PINCTL register.
<> 144:ef7eb2e8f9f7 21860 * | | |0 = Synchronizing is completion, user can write new data to SC_PINCTL register.
<> 144:ef7eb2e8f9f7 21861 * | | |1 = Last value is synchronizing.
<> 144:ef7eb2e8f9f7 21862 * | | |Note: This bit is read only.
<> 144:ef7eb2e8f9f7 21863 */
<> 144:ef7eb2e8f9f7 21864 __IO uint32_t PINCTL;
<> 144:ef7eb2e8f9f7 21865
<> 144:ef7eb2e8f9f7 21866 /**
<> 144:ef7eb2e8f9f7 21867 * TMRCTL0
<> 144:ef7eb2e8f9f7 21868 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21869 * Offset: 0x28 SC Internal Timer Control Register 0
<> 144:ef7eb2e8f9f7 21870 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21871 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21872 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21873 * |[0:23] |CNT |Timer 0 Counter Value (ETU Base)
<> 144:ef7eb2e8f9f7 21874 * | | |This field indicates the internal timer operation values.
<> 144:ef7eb2e8f9f7 21875 * |[24:27] |OPMODE |Timer 0 Operation Mode Selection
<> 144:ef7eb2e8f9f7 21876 * | | |This field indicates the internal 24-bit timer operation selection.
<> 144:ef7eb2e8f9f7 21877 * | | |Refer to 6.25.4.4 for programming Timer0.
<> 144:ef7eb2e8f9f7 21878 */
<> 144:ef7eb2e8f9f7 21879 __IO uint32_t TMRCTL0;
<> 144:ef7eb2e8f9f7 21880
<> 144:ef7eb2e8f9f7 21881 /**
<> 144:ef7eb2e8f9f7 21882 * TMRCTL1
<> 144:ef7eb2e8f9f7 21883 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21884 * Offset: 0x2C SC Internal Timer Control Register 1
<> 144:ef7eb2e8f9f7 21885 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21886 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21887 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21888 * |[0:7] |CNT |Timer 1 Counter Value (ETU Base)
<> 144:ef7eb2e8f9f7 21889 * | | |This field indicates the internal timer operation values.
<> 144:ef7eb2e8f9f7 21890 * |[24:27] |OPMODE |Timer 1 Operation Mode Selection
<> 144:ef7eb2e8f9f7 21891 * | | |This field indicates the internal 8-bit timer operation selection.
<> 144:ef7eb2e8f9f7 21892 * | | |Refer to 6.25.4.4 for programming Timer1.
<> 144:ef7eb2e8f9f7 21893 */
<> 144:ef7eb2e8f9f7 21894 __IO uint32_t TMRCTL1;
<> 144:ef7eb2e8f9f7 21895
<> 144:ef7eb2e8f9f7 21896 /**
<> 144:ef7eb2e8f9f7 21897 * TMRCTL2
<> 144:ef7eb2e8f9f7 21898 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21899 * Offset: 0x30 SC Internal Timer Control Register 2
<> 144:ef7eb2e8f9f7 21900 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21901 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21902 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21903 * |[0:7] |CNT |Timer 2 Counter Value (ETU Base)
<> 144:ef7eb2e8f9f7 21904 * | | |This field indicates the internal timer operation values.
<> 144:ef7eb2e8f9f7 21905 * |[24:27] |OPMODE |Timer 2 Operation Mode Selection
<> 144:ef7eb2e8f9f7 21906 * | | |This field indicates the internal 8-bit timer operation selection
<> 144:ef7eb2e8f9f7 21907 * | | |Refer to 6.25.4.4 for programming Timer2
<> 144:ef7eb2e8f9f7 21908 */
<> 144:ef7eb2e8f9f7 21909 __IO uint32_t TMRCTL2;
<> 144:ef7eb2e8f9f7 21910
<> 144:ef7eb2e8f9f7 21911 /**
<> 144:ef7eb2e8f9f7 21912 * UARTCTL
<> 144:ef7eb2e8f9f7 21913 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21914 * Offset: 0x34 SC UART Mode Control Register
<> 144:ef7eb2e8f9f7 21915 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21916 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21917 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21918 * |[0] |UARTEN |UART Mode Enable Control
<> 144:ef7eb2e8f9f7 21919 * | | |0 = Smart Card mode.
<> 144:ef7eb2e8f9f7 21920 * | | |1 = UART mode.
<> 144:ef7eb2e8f9f7 21921 * | | |Note1: When operating in UART mode, user must set CONSEL (SC_CTL[5:4]) = 00 and AUTOCEN(SC_CTL[3]) = 0.
<> 144:ef7eb2e8f9f7 21922 * | | |Note2: When operating in Smart Card mode, user must set SC_UARTCTL [7:0] = 00.
<> 144:ef7eb2e8f9f7 21923 * | | |Note3: When UART is enabled, hardware will generate a reset to resetFIFO and internal state machine.
<> 144:ef7eb2e8f9f7 21924 * |[4:5] |WLS |Data Length
<> 144:ef7eb2e8f9f7 21925 * | | |00 = Character Data Length is 8 bits.
<> 144:ef7eb2e8f9f7 21926 * | | |01 = Character Data Length is 7 bits.
<> 144:ef7eb2e8f9f7 21927 * | | |10 = Character Data length is 6 bits.
<> 144:ef7eb2e8f9f7 21928 * | | |11 = Character Data Length is 5 bits.
<> 144:ef7eb2e8f9f7 21929 * | | |Note: In smart card mode, this WLS must be '00'
<> 144:ef7eb2e8f9f7 21930 * |[6] |PBOFF |Parity Bit Disable Control
<> 144:ef7eb2e8f9f7 21931 * | | |0 = Parity bit is generated or checked between the "last data word bit" and "stop bit" of the serial data.
<> 144:ef7eb2e8f9f7 21932 * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer.
<> 144:ef7eb2e8f9f7 21933 * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit)
<> 144:ef7eb2e8f9f7 21934 * |[7] |OPE |Odd Parity Enable Control
<> 144:ef7eb2e8f9f7 21935 * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
<> 144:ef7eb2e8f9f7 21936 * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode.
<> 144:ef7eb2e8f9f7 21937 * | | |Note: This bit has effect only when PBOFF bit is '0'.
<> 144:ef7eb2e8f9f7 21938 */
<> 144:ef7eb2e8f9f7 21939 __IO uint32_t UARTCTL;
<> 144:ef7eb2e8f9f7 21940
<> 144:ef7eb2e8f9f7 21941 /**
<> 144:ef7eb2e8f9f7 21942 * TMRDAT0
<> 144:ef7eb2e8f9f7 21943 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21944 * Offset: 0x38 SC Timer 0 Current Data Register
<> 144:ef7eb2e8f9f7 21945 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21946 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21947 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21948 * |[0:23] |CNT0 |Timer0 Current Counter Value (Read Only)
<> 144:ef7eb2e8f9f7 21949 * | | |This field indicates the current count values of timer0.
<> 144:ef7eb2e8f9f7 21950 */
<> 144:ef7eb2e8f9f7 21951 __I uint32_t TMRDAT0;
<> 144:ef7eb2e8f9f7 21952
<> 144:ef7eb2e8f9f7 21953 /**
<> 144:ef7eb2e8f9f7 21954 * TMRDAT1_2
<> 144:ef7eb2e8f9f7 21955 * ===================================================================================================
<> 144:ef7eb2e8f9f7 21956 * Offset: 0x3C SC Timer 1 and 2 Current Data Register
<> 144:ef7eb2e8f9f7 21957 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 21958 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 21959 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 21960 * |[0:7] |CNT1 |Timer1 Current Counter Value (Read Only)
<> 144:ef7eb2e8f9f7 21961 * | | |This field indicates the current count values of timer1.
<> 144:ef7eb2e8f9f7 21962 * |[8:15] |CNT2 |Timer2 Current Counter Value (Read Only)
<> 144:ef7eb2e8f9f7 21963 * | | |This field indicates the current count values of timer2.
<> 144:ef7eb2e8f9f7 21964 */
<> 144:ef7eb2e8f9f7 21965 __I uint32_t TMRDAT1_2;
<> 144:ef7eb2e8f9f7 21966
<> 144:ef7eb2e8f9f7 21967 } SC_T;
<> 144:ef7eb2e8f9f7 21968
<> 144:ef7eb2e8f9f7 21969 /**
<> 144:ef7eb2e8f9f7 21970 @addtogroup SC_CONST SC Bit Field Definition
<> 144:ef7eb2e8f9f7 21971 Constant Definitions for SC Controller
<> 144:ef7eb2e8f9f7 21972 @{ */
<> 144:ef7eb2e8f9f7 21973
<> 144:ef7eb2e8f9f7 21974 #define SC_DAT_DAT_Pos (0) /*!< SC DAT: DAT Position */
<> 144:ef7eb2e8f9f7 21975 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC DAT: DAT Mask */
<> 144:ef7eb2e8f9f7 21976
<> 144:ef7eb2e8f9f7 21977 #define SC_CTL_SCEN_Pos (0) /*!< SC CTL: SCEN Position */
<> 144:ef7eb2e8f9f7 21978 #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC CTL: SCEN Mask */
<> 144:ef7eb2e8f9f7 21979
<> 144:ef7eb2e8f9f7 21980 #define SC_CTL_RXOFF_Pos (1) /*!< SC CTL: RXOFF Position */
<> 144:ef7eb2e8f9f7 21981 #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC CTL: RXOFF Mask */
<> 144:ef7eb2e8f9f7 21982
<> 144:ef7eb2e8f9f7 21983 #define SC_CTL_TXOFF_Pos (2) /*!< SC CTL: TXOFF Position */
<> 144:ef7eb2e8f9f7 21984 #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC CTL: TXOFF Mask */
<> 144:ef7eb2e8f9f7 21985
<> 144:ef7eb2e8f9f7 21986 #define SC_CTL_AUTOCEN_Pos (3) /*!< SC CTL: AUTOCEN Position */
<> 144:ef7eb2e8f9f7 21987 #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC CTL: AUTOCEN Mask */
<> 144:ef7eb2e8f9f7 21988
<> 144:ef7eb2e8f9f7 21989 #define SC_CTL_CONSEL_Pos (4) /*!< SC CTL: CONSEL Position */
<> 144:ef7eb2e8f9f7 21990 #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC CTL: CONSEL Mask */
<> 144:ef7eb2e8f9f7 21991
<> 144:ef7eb2e8f9f7 21992 #define SC_CTL_RXTRGLV_Pos (6) /*!< SC CTL: RXTRGLV Position */
<> 144:ef7eb2e8f9f7 21993 #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC CTL: RXTRGLV Mask */
<> 144:ef7eb2e8f9f7 21994
<> 144:ef7eb2e8f9f7 21995 #define SC_CTL_BGT_Pos (8) /*!< SC CTL: BGT Position */
<> 144:ef7eb2e8f9f7 21996 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC CTL: BGT Mask */
<> 144:ef7eb2e8f9f7 21997
<> 144:ef7eb2e8f9f7 21998 #define SC_CTL_TMRSEL_Pos (13) /*!< SC CTL: TMRSEL Position */
<> 144:ef7eb2e8f9f7 21999 #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC CTL: TMRSEL Mask */
<> 144:ef7eb2e8f9f7 22000
<> 144:ef7eb2e8f9f7 22001 #define SC_CTL_NSB_Pos (15) /*!< SC CTL: NSB Position */
<> 144:ef7eb2e8f9f7 22002 #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC CTL: NSB Mask */
<> 144:ef7eb2e8f9f7 22003
<> 144:ef7eb2e8f9f7 22004 #define SC_CTL_RXRTY_Pos (16) /*!< SC CTL: RXRTY Position */
<> 144:ef7eb2e8f9f7 22005 #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC CTL: RXRTY Mask */
<> 144:ef7eb2e8f9f7 22006
<> 144:ef7eb2e8f9f7 22007 #define SC_CTL_RXRTYEN_Pos (19) /*!< SC CTL: RXRTYEN Position */
<> 144:ef7eb2e8f9f7 22008 #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC CTL: RXRTYEN Mask */
<> 144:ef7eb2e8f9f7 22009
<> 144:ef7eb2e8f9f7 22010 #define SC_CTL_TXRTY_Pos (20) /*!< SC CTL: TXRTY Position */
<> 144:ef7eb2e8f9f7 22011 #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC CTL: TXRTY Mask */
<> 144:ef7eb2e8f9f7 22012
<> 144:ef7eb2e8f9f7 22013 #define SC_CTL_TXRTYEN_Pos (23) /*!< SC CTL: TXRTYEN Position */
<> 144:ef7eb2e8f9f7 22014 #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC CTL: TXRTYEN Mask */
<> 144:ef7eb2e8f9f7 22015
<> 144:ef7eb2e8f9f7 22016 #define SC_CTL_CDDBSEL_Pos (24) /*!< SC CTL: CDDBSEL Position */
<> 144:ef7eb2e8f9f7 22017 #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC CTL: CDDBSEL Mask */
<> 144:ef7eb2e8f9f7 22018
<> 144:ef7eb2e8f9f7 22019 #define SC_CTL_CDLV_Pos (26) /*!< SC CTL: CDLV Position */
<> 144:ef7eb2e8f9f7 22020 #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC CTL: CDLV Mask */
<> 144:ef7eb2e8f9f7 22021
<> 144:ef7eb2e8f9f7 22022 #define SC_CTL_SYNC_Pos (30) /*!< SC CTL: SYNC Position */
<> 144:ef7eb2e8f9f7 22023 #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC CTL: SYNC Mask */
<> 144:ef7eb2e8f9f7 22024
<> 144:ef7eb2e8f9f7 22025 #define SC_ALTCTL_TXRST_Pos (0) /*!< SC ALTCTL: TXRST Position */
<> 144:ef7eb2e8f9f7 22026 #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC ALTCTL: TXRST Mask */
<> 144:ef7eb2e8f9f7 22027
<> 144:ef7eb2e8f9f7 22028 #define SC_ALTCTL_RXRST_Pos (1) /*!< SC ALTCTL: RXRST Position */
<> 144:ef7eb2e8f9f7 22029 #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC ALTCTL: RXRST Mask */
<> 144:ef7eb2e8f9f7 22030
<> 144:ef7eb2e8f9f7 22031 #define SC_ALTCTL_DACTEN_Pos (2) /*!< SC ALTCTL: DACTEN Position */
<> 144:ef7eb2e8f9f7 22032 #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC ALTCTL: DACTEN Mask */
<> 144:ef7eb2e8f9f7 22033
<> 144:ef7eb2e8f9f7 22034 #define SC_ALTCTL_ACTEN_Pos (3) /*!< SC ALTCTL: ACTEN Position */
<> 144:ef7eb2e8f9f7 22035 #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC ALTCTL: ACTEN Mask */
<> 144:ef7eb2e8f9f7 22036
<> 144:ef7eb2e8f9f7 22037 #define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC ALTCTL: WARSTEN Position */
<> 144:ef7eb2e8f9f7 22038 #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC ALTCTL: WARSTEN Mask */
<> 144:ef7eb2e8f9f7 22039
<> 144:ef7eb2e8f9f7 22040 #define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC ALTCTL: CNTEN0 Position */
<> 144:ef7eb2e8f9f7 22041 #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC ALTCTL: CNTEN0 Mask */
<> 144:ef7eb2e8f9f7 22042
<> 144:ef7eb2e8f9f7 22043 #define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC ALTCTL: CNTEN1 Position */
<> 144:ef7eb2e8f9f7 22044 #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC ALTCTL: CNTEN1 Mask */
<> 144:ef7eb2e8f9f7 22045
<> 144:ef7eb2e8f9f7 22046 #define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC ALTCTL: CNTEN2 Position */
<> 144:ef7eb2e8f9f7 22047 #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC ALTCTL: CNTEN2 Mask */
<> 144:ef7eb2e8f9f7 22048
<> 144:ef7eb2e8f9f7 22049 #define SC_ALTCTL_INITSEL_Pos (8) /*!< SC ALTCTL: INITSEL Position */
<> 144:ef7eb2e8f9f7 22050 #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC ALTCTL: INITSEL Mask */
<> 144:ef7eb2e8f9f7 22051
<> 144:ef7eb2e8f9f7 22052 #define SC_ALTCTL_ADACEN_Pos (11) /*!< SC ALTCTL: ADACEN Position */
<> 144:ef7eb2e8f9f7 22053 #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC ALTCTL: ADACEN Mask */
<> 144:ef7eb2e8f9f7 22054
<> 144:ef7eb2e8f9f7 22055 #define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC ALTCTL: RXBGTEN Position */
<> 144:ef7eb2e8f9f7 22056 #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC ALTCTL: RXBGTEN Mask */
<> 144:ef7eb2e8f9f7 22057
<> 144:ef7eb2e8f9f7 22058 #define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC ALTCTL: ACTSTS0 Position */
<> 144:ef7eb2e8f9f7 22059 #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC ALTCTL: ACTSTS0 Mask */
<> 144:ef7eb2e8f9f7 22060
<> 144:ef7eb2e8f9f7 22061 #define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC ALTCTL: ACTSTS1 Position */
<> 144:ef7eb2e8f9f7 22062 #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC ALTCTL: ACTSTS1 Mask */
<> 144:ef7eb2e8f9f7 22063
<> 144:ef7eb2e8f9f7 22064 #define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC ALTCTL: ACTSTS2 Position */
<> 144:ef7eb2e8f9f7 22065 #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC ALTCTL: ACTSTS2 Mask */
<> 144:ef7eb2e8f9f7 22066
<> 144:ef7eb2e8f9f7 22067 #define SC_EGT_EGT_Pos (0) /*!< SC EGT: EGT Position */
<> 144:ef7eb2e8f9f7 22068 #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC EGT: EGT Mask */
<> 144:ef7eb2e8f9f7 22069
<> 144:ef7eb2e8f9f7 22070 #define SC_RXTOUT_RFTM_Pos (0) /*!< SC RXTOUT: RFTM Position */
<> 144:ef7eb2e8f9f7 22071 #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC RXTOUT: RFTM Mask */
<> 144:ef7eb2e8f9f7 22072
<> 144:ef7eb2e8f9f7 22073 #define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC ETUCTL: ETURDIV Position */
<> 144:ef7eb2e8f9f7 22074 #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC ETUCTL: ETURDIV Mask */
<> 144:ef7eb2e8f9f7 22075
<> 144:ef7eb2e8f9f7 22076 #define SC_ETUCTL_CMPEN_Pos (15) /*!< SC ETUCTL: CMPEN Position */
<> 144:ef7eb2e8f9f7 22077 #define SC_ETUCTL_CMPEN_Msk (0x1ul << SC_ETUCTL_CMPEN_Pos) /*!< SC ETUCTL: CMPEN Mask */
<> 144:ef7eb2e8f9f7 22078
<> 144:ef7eb2e8f9f7 22079 #define SC_INTEN_RDAIEN_Pos (0) /*!< SC INTEN: RDAIEN Position */
<> 144:ef7eb2e8f9f7 22080 #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC INTEN: RDAIEN Mask */
<> 144:ef7eb2e8f9f7 22081
<> 144:ef7eb2e8f9f7 22082 #define SC_INTEN_TBEIEN_Pos (1) /*!< SC INTEN: TBEIEN Position */
<> 144:ef7eb2e8f9f7 22083 #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC INTEN: TBEIEN Mask */
<> 144:ef7eb2e8f9f7 22084
<> 144:ef7eb2e8f9f7 22085 #define SC_INTEN_TERRIEN_Pos (2) /*!< SC INTEN: TERRIEN Position */
<> 144:ef7eb2e8f9f7 22086 #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC INTEN: TERRIEN Mask */
<> 144:ef7eb2e8f9f7 22087
<> 144:ef7eb2e8f9f7 22088 #define SC_INTEN_TMR0IEN_Pos (3) /*!< SC INTEN: TMR0IEN Position */
<> 144:ef7eb2e8f9f7 22089 #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC INTEN: TMR0IEN Mask */
<> 144:ef7eb2e8f9f7 22090
<> 144:ef7eb2e8f9f7 22091 #define SC_INTEN_TMR1IEN_Pos (4) /*!< SC INTEN: TMR1IEN Position */
<> 144:ef7eb2e8f9f7 22092 #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC INTEN: TMR1IEN Mask */
<> 144:ef7eb2e8f9f7 22093
<> 144:ef7eb2e8f9f7 22094 #define SC_INTEN_TMR2IEN_Pos (5) /*!< SC INTEN: TMR2IEN Position */
<> 144:ef7eb2e8f9f7 22095 #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC INTEN: TMR2IEN Mask */
<> 144:ef7eb2e8f9f7 22096
<> 144:ef7eb2e8f9f7 22097 #define SC_INTEN_BGTIEN_Pos (6) /*!< SC INTEN: BGTIEN Position */
<> 144:ef7eb2e8f9f7 22098 #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC INTEN: BGTIEN Mask */
<> 144:ef7eb2e8f9f7 22099
<> 144:ef7eb2e8f9f7 22100 #define SC_INTEN_CDIEN_Pos (7) /*!< SC INTEN: CDIEN Position */
<> 144:ef7eb2e8f9f7 22101 #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC INTEN: CDIEN Mask */
<> 144:ef7eb2e8f9f7 22102
<> 144:ef7eb2e8f9f7 22103 #define SC_INTEN_INITIEN_Pos (8) /*!< SC INTEN: INITIEN Position */
<> 144:ef7eb2e8f9f7 22104 #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC INTEN: INITIEN Mask */
<> 144:ef7eb2e8f9f7 22105
<> 144:ef7eb2e8f9f7 22106 #define SC_INTEN_RXTOIF_Pos (9) /*!< SC INTEN: RXTOIF Position */
<> 144:ef7eb2e8f9f7 22107 #define SC_INTEN_RXTOIF_Msk (0x1ul << SC_INTEN_RXTOIF_Pos) /*!< SC INTEN: RXTOIF Mask */
<> 144:ef7eb2e8f9f7 22108
<> 144:ef7eb2e8f9f7 22109 #define SC_INTEN_ACERRIEN_Pos (10) /*!< SC INTEN: ACERRIEN Position */
<> 144:ef7eb2e8f9f7 22110 #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC INTEN: ACERRIEN Mask */
<> 144:ef7eb2e8f9f7 22111
<> 144:ef7eb2e8f9f7 22112 #define SC_INTSTS_RDAIF_Pos (0) /*!< SC INTSTS: RDAIF Position */
<> 144:ef7eb2e8f9f7 22113 #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC INTSTS: RDAIF Mask */
<> 144:ef7eb2e8f9f7 22114
<> 144:ef7eb2e8f9f7 22115 #define SC_INTSTS_TBEIF_Pos (1) /*!< SC INTSTS: TBEIF Position */
<> 144:ef7eb2e8f9f7 22116 #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC INTSTS: TBEIF Mask */
<> 144:ef7eb2e8f9f7 22117
<> 144:ef7eb2e8f9f7 22118 #define SC_INTSTS_TERRIF_Pos (2) /*!< SC INTSTS: TERRIF Position */
<> 144:ef7eb2e8f9f7 22119 #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC INTSTS: TERRIF Mask */
<> 144:ef7eb2e8f9f7 22120
<> 144:ef7eb2e8f9f7 22121 #define SC_INTSTS_TMR0IF_Pos (3) /*!< SC INTSTS: TMR0IF Position */
<> 144:ef7eb2e8f9f7 22122 #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC INTSTS: TMR0IF Mask */
<> 144:ef7eb2e8f9f7 22123
<> 144:ef7eb2e8f9f7 22124 #define SC_INTSTS_TMR1IF_Pos (4) /*!< SC INTSTS: TMR1IF Position */
<> 144:ef7eb2e8f9f7 22125 #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC INTSTS: TMR1IF Mask */
<> 144:ef7eb2e8f9f7 22126
<> 144:ef7eb2e8f9f7 22127 #define SC_INTSTS_TMR2IF_Pos (5) /*!< SC INTSTS: TMR2IF Position */
<> 144:ef7eb2e8f9f7 22128 #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC INTSTS: TMR2IF Mask */
<> 144:ef7eb2e8f9f7 22129
<> 144:ef7eb2e8f9f7 22130 #define SC_INTSTS_BGTIF_Pos (6) /*!< SC INTSTS: BGTIF Position */
<> 144:ef7eb2e8f9f7 22131 #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC INTSTS: BGTIF Mask */
<> 144:ef7eb2e8f9f7 22132
<> 144:ef7eb2e8f9f7 22133 #define SC_INTSTS_CDIF_Pos (7) /*!< SC INTSTS: CDIF Position */
<> 144:ef7eb2e8f9f7 22134 #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC INTSTS: CDIF Mask */
<> 144:ef7eb2e8f9f7 22135
<> 144:ef7eb2e8f9f7 22136 #define SC_INTSTS_INITIF_Pos (8) /*!< SC INTSTS: INITIF Position */
<> 144:ef7eb2e8f9f7 22137 #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC INTSTS: INITIF Mask */
<> 144:ef7eb2e8f9f7 22138
<> 144:ef7eb2e8f9f7 22139 #define SC_INTSTS_RBTOIF_Pos (9) /*!< SC INTSTS: RBTOIF Position */
<> 144:ef7eb2e8f9f7 22140 #define SC_INTSTS_RBTOIF_Msk (0x1ul << SC_INTSTS_RBTOIF_Pos) /*!< SC INTSTS: RBTOIF Mask */
<> 144:ef7eb2e8f9f7 22141
<> 144:ef7eb2e8f9f7 22142 #define SC_INTSTS_ACERRIF_Pos (10) /*!< SC INTSTS: ACERRIF Position */
<> 144:ef7eb2e8f9f7 22143 #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC INTSTS: ACERRIF Mask */
<> 144:ef7eb2e8f9f7 22144
<> 144:ef7eb2e8f9f7 22145 #define SC_STATUS_RXOV_Pos (0) /*!< SC STATUS: RXOV Position */
<> 144:ef7eb2e8f9f7 22146 #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC STATUS: RXOV Mask */
<> 144:ef7eb2e8f9f7 22147
<> 144:ef7eb2e8f9f7 22148 #define SC_STATUS_RXEMPTY_Pos (1) /*!< SC STATUS: RXEMPTY Position */
<> 144:ef7eb2e8f9f7 22149 #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC STATUS: RXEMPTY Mask */
<> 144:ef7eb2e8f9f7 22150
<> 144:ef7eb2e8f9f7 22151 #define SC_STATUS_RXFULL_Pos (2) /*!< SC STATUS: RXFULL Position */
<> 144:ef7eb2e8f9f7 22152 #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC STATUS: RXFULL Mask */
<> 144:ef7eb2e8f9f7 22153
<> 144:ef7eb2e8f9f7 22154 #define SC_STATUS_PEF_Pos (4) /*!< SC STATUS: PEF Position */
<> 144:ef7eb2e8f9f7 22155 #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC STATUS: PEF Mask */
<> 144:ef7eb2e8f9f7 22156
<> 144:ef7eb2e8f9f7 22157 #define SC_STATUS_FEF_Pos (5) /*!< SC STATUS: FEF Position */
<> 144:ef7eb2e8f9f7 22158 #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC STATUS: FEF Mask */
<> 144:ef7eb2e8f9f7 22159
<> 144:ef7eb2e8f9f7 22160 #define SC_STATUS_BEF_Pos (6) /*!< SC STATUS: BEF Position */
<> 144:ef7eb2e8f9f7 22161 #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC STATUS: BEF Mask */
<> 144:ef7eb2e8f9f7 22162
<> 144:ef7eb2e8f9f7 22163 #define SC_STATUS_TXOV_Pos (8) /*!< SC STATUS: TXOV Position */
<> 144:ef7eb2e8f9f7 22164 #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC STATUS: TXOV Mask */
<> 144:ef7eb2e8f9f7 22165
<> 144:ef7eb2e8f9f7 22166 #define SC_STATUS_TXEMPTY_Pos (9) /*!< SC STATUS: TXEMPTY Position */
<> 144:ef7eb2e8f9f7 22167 #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC STATUS: TXEMPTY Mask */
<> 144:ef7eb2e8f9f7 22168
<> 144:ef7eb2e8f9f7 22169 #define SC_STATUS_TXFULL_Pos (10) /*!< SC STATUS: TXFULL Position */
<> 144:ef7eb2e8f9f7 22170 #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC STATUS: TXFULL Mask */
<> 144:ef7eb2e8f9f7 22171
<> 144:ef7eb2e8f9f7 22172 #define SC_STATUS_CREMOVE_Pos (11) /*!< SC STATUS: CREMOVE Position */
<> 144:ef7eb2e8f9f7 22173 #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC STATUS: CREMOVE Mask */
<> 144:ef7eb2e8f9f7 22174
<> 144:ef7eb2e8f9f7 22175 #define SC_STATUS_CINSERT_Pos (12) /*!< SC STATUS: CINSERT Position */
<> 144:ef7eb2e8f9f7 22176 #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC STATUS: CINSERT Mask */
<> 144:ef7eb2e8f9f7 22177
<> 144:ef7eb2e8f9f7 22178 #define SC_STATUS_CDPINSTS_Pos (13) /*!< SC STATUS: CDPINSTS Position */
<> 144:ef7eb2e8f9f7 22179 #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC STATUS: CDPINSTS Mask */
<> 144:ef7eb2e8f9f7 22180
<> 144:ef7eb2e8f9f7 22181 #define SC_STATUS_RXPOINT_Pos (16) /*!< SC STATUS: RXPOINT Position */
<> 144:ef7eb2e8f9f7 22182 #define SC_STATUS_RXPOINT_Msk (0x3ul << SC_STATUS_RXPOINT_Pos) /*!< SC STATUS: RXPOINT Mask */
<> 144:ef7eb2e8f9f7 22183
<> 144:ef7eb2e8f9f7 22184 #define SC_STATUS_RXRERR_Pos (21) /*!< SC STATUS: RXRERR Position */
<> 144:ef7eb2e8f9f7 22185 #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC STATUS: RXRERR Mask */
<> 144:ef7eb2e8f9f7 22186
<> 144:ef7eb2e8f9f7 22187 #define SC_STATUS_RXOVERR_Pos (22) /*!< SC STATUS: RXOVERR Position */
<> 144:ef7eb2e8f9f7 22188 #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC STATUS: RXOVERR Mask */
<> 144:ef7eb2e8f9f7 22189
<> 144:ef7eb2e8f9f7 22190 #define SC_STATUS_RXACT_Pos (23) /*!< SC STATUS: RXACT Position */
<> 144:ef7eb2e8f9f7 22191 #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC STATUS: RXACT Mask */
<> 144:ef7eb2e8f9f7 22192
<> 144:ef7eb2e8f9f7 22193 #define SC_STATUS_TXPOINT_Pos (24) /*!< SC STATUS: TXPOINT Position */
<> 144:ef7eb2e8f9f7 22194 #define SC_STATUS_TXPOINT_Msk (0x3ul << SC_STATUS_TXPOINT_Pos) /*!< SC STATUS: TXPOINT Mask */
<> 144:ef7eb2e8f9f7 22195
<> 144:ef7eb2e8f9f7 22196 #define SC_STATUS_TXRERR_Pos (29) /*!< SC STATUS: TXRERR Position */
<> 144:ef7eb2e8f9f7 22197 #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC STATUS: TXRERR Mask */
<> 144:ef7eb2e8f9f7 22198
<> 144:ef7eb2e8f9f7 22199 #define SC_STATUS_TXOVERR_Pos (30) /*!< SC STATUS: TXOVERR Position */
<> 144:ef7eb2e8f9f7 22200 #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC STATUS: TXOVERR Mask */
<> 144:ef7eb2e8f9f7 22201
<> 144:ef7eb2e8f9f7 22202 #define SC_STATUS_TXACT_Pos (31) /*!< SC STATUS: TXACT Position */
<> 144:ef7eb2e8f9f7 22203 #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC STATUS: TXACT Mask */
<> 144:ef7eb2e8f9f7 22204
<> 144:ef7eb2e8f9f7 22205 #define SC_PINCTL_PWREN_Pos (0) /*!< SC PINCTL: PWREN Position */
<> 144:ef7eb2e8f9f7 22206 #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC PINCTL: PWREN Mask */
<> 144:ef7eb2e8f9f7 22207
<> 144:ef7eb2e8f9f7 22208 #define SC_PINCTL_SCRST_Pos (1) /*!< SC PINCTL: SCRST Position */
<> 144:ef7eb2e8f9f7 22209 #define SC_PINCTL_SCRST_Msk (0x1ul << SC_PINCTL_SCRST_Pos) /*!< SC PINCTL: SCRST Mask */
<> 144:ef7eb2e8f9f7 22210
<> 144:ef7eb2e8f9f7 22211 #define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC PINCTL: CLKKEEP Position */
<> 144:ef7eb2e8f9f7 22212 #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC PINCTL: CLKKEEP Mask */
<> 144:ef7eb2e8f9f7 22213
<> 144:ef7eb2e8f9f7 22214 #define SC_PINCTL_SCDOUT_Pos (9) /*!< SC PINCTL: SCDOUT Position */
<> 144:ef7eb2e8f9f7 22215 #define SC_PINCTL_SCDOUT_Msk (0x1ul << SC_PINCTL_SCDOUT_Pos) /*!< SC PINCTL: SCDOUT Mask */
<> 144:ef7eb2e8f9f7 22216
<> 144:ef7eb2e8f9f7 22217 #define SC_PINCTL_PWRINV_Pos (11) /*!< SC PINCTL: PWRINV Position */
<> 144:ef7eb2e8f9f7 22218 #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC PINCTL: PWRINV Mask */
<> 144:ef7eb2e8f9f7 22219
<> 144:ef7eb2e8f9f7 22220 #define SC_PINCTL_DATSTS_Pos (16) /*!< SC PINCTL: DATSTS Position */
<> 144:ef7eb2e8f9f7 22221 #define SC_PINCTL_DATSTS_Msk (0x1ul << SC_PINCTL_DATSTS_Pos) /*!< SC PINCTL: DATSTS Mask */
<> 144:ef7eb2e8f9f7 22222
<> 144:ef7eb2e8f9f7 22223 #define SC_PINCTL_PWRSTS_Pos (17) /*!< SC PINCTL: PWRSTS Position */
<> 144:ef7eb2e8f9f7 22224 #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC PINCTL: PWRSTS Mask */
<> 144:ef7eb2e8f9f7 22225
<> 144:ef7eb2e8f9f7 22226 #define SC_PINCTL_RSTSTS_Pos (18) /*!< SC PINCTL: RSTSTS Position */
<> 144:ef7eb2e8f9f7 22227 #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC PINCTL: RSTSTS Mask */
<> 144:ef7eb2e8f9f7 22228
<> 144:ef7eb2e8f9f7 22229 #define SC_PINCTL_SYNC_Pos (30) /*!< SC PINCTL: SYNC Position */
<> 144:ef7eb2e8f9f7 22230 #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC PINCTL: SYNC Mask */
<> 144:ef7eb2e8f9f7 22231
<> 144:ef7eb2e8f9f7 22232 #define SC_TMRCTL0_CNT_Pos (0) /*!< SC TMRCTL0: CNT Position */
<> 144:ef7eb2e8f9f7 22233 #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC TMRCTL0: CNT Mask */
<> 144:ef7eb2e8f9f7 22234
<> 144:ef7eb2e8f9f7 22235 #define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC TMRCTL0: OPMODE Position */
<> 144:ef7eb2e8f9f7 22236 #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC TMRCTL0: OPMODE Mask */
<> 144:ef7eb2e8f9f7 22237
<> 144:ef7eb2e8f9f7 22238 #define SC_TMRCTL1_CNT_Pos (0) /*!< SC TMRCTL1: CNT Position */
<> 144:ef7eb2e8f9f7 22239 #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC TMRCTL1: CNT Mask */
<> 144:ef7eb2e8f9f7 22240
<> 144:ef7eb2e8f9f7 22241 #define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC TMRCTL1: OPMODE Position */
<> 144:ef7eb2e8f9f7 22242 #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC TMRCTL1: OPMODE Mask */
<> 144:ef7eb2e8f9f7 22243
<> 144:ef7eb2e8f9f7 22244 #define SC_TMRCTL2_CNT_Pos (0) /*!< SC TMRCTL2: CNT Position */
<> 144:ef7eb2e8f9f7 22245 #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC TMRCTL2: CNT Mask */
<> 144:ef7eb2e8f9f7 22246
<> 144:ef7eb2e8f9f7 22247 #define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC TMRCTL2: OPMODE Position */
<> 144:ef7eb2e8f9f7 22248 #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC TMRCTL2: OPMODE Mask */
<> 144:ef7eb2e8f9f7 22249
<> 144:ef7eb2e8f9f7 22250 #define SC_UARTCTL_UARTEN_Pos (0) /*!< SC UARTCTL: UARTEN Position */
<> 144:ef7eb2e8f9f7 22251 #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC UARTCTL: UARTEN Mask */
<> 144:ef7eb2e8f9f7 22252
<> 144:ef7eb2e8f9f7 22253 #define SC_UARTCTL_WLS_Pos (4) /*!< SC UARTCTL: WLS Position */
<> 144:ef7eb2e8f9f7 22254 #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC UARTCTL: WLS Mask */
<> 144:ef7eb2e8f9f7 22255
<> 144:ef7eb2e8f9f7 22256 #define SC_UARTCTL_PBOFF_Pos (6) /*!< SC UARTCTL: PBOFF Position */
<> 144:ef7eb2e8f9f7 22257 #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC UARTCTL: PBOFF Mask */
<> 144:ef7eb2e8f9f7 22258
<> 144:ef7eb2e8f9f7 22259 #define SC_UARTCTL_OPE_Pos (7) /*!< SC UARTCTL: OPE Position */
<> 144:ef7eb2e8f9f7 22260 #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC UARTCTL: OPE Mask */
<> 144:ef7eb2e8f9f7 22261
<> 144:ef7eb2e8f9f7 22262 #define SC_TMRDAT0_TDR0_Pos (0) /*!< SC TMRDAT0: TDR0 Position */
<> 144:ef7eb2e8f9f7 22263 #define SC_TMRDAT0_TDR0_Msk (0xfffffful << SC_TMRDAT0_TDR0_Pos) /*!< SC TMRDAT0: TDR0 Mask */
<> 144:ef7eb2e8f9f7 22264
<> 144:ef7eb2e8f9f7 22265 #define SC_TMRDAT1_2_TDR1_Pos (0) /*!< SC TMRDAT1_2: TDR1 Position */
<> 144:ef7eb2e8f9f7 22266 #define SC_TMRDAT1_2_TDR1_Msk (0xfful << SC_TMRDAT1_2_TDR1_Pos) /*!< SC TMRDAT1_2: TDR1 Mask */
<> 144:ef7eb2e8f9f7 22267
<> 144:ef7eb2e8f9f7 22268 #define SC_TMRDAT1_2_TDR2_Pos (8) /*!< SC TMRDAT1_2: TDR2 Position */
<> 144:ef7eb2e8f9f7 22269 #define SC_TMRDAT1_2_TDR2_Msk (0xfful << SC_TMRDAT1_2_TDR2_Pos) /*!< SC TMRDAT1_2: TDR2 Mask */
<> 144:ef7eb2e8f9f7 22270
<> 144:ef7eb2e8f9f7 22271 /**@}*/ /* SC_CONST */
<> 144:ef7eb2e8f9f7 22272 /**@}*/ /* end of SC register group */
<> 144:ef7eb2e8f9f7 22273
<> 144:ef7eb2e8f9f7 22274
<> 144:ef7eb2e8f9f7 22275 /*---------------------- SD Card Host Interface -------------------------*/
<> 144:ef7eb2e8f9f7 22276 /**
<> 144:ef7eb2e8f9f7 22277 @addtogroup SDH SD Card Host Interface(SDH)
<> 144:ef7eb2e8f9f7 22278 Memory Mapped Structure for SDH Controller
<> 144:ef7eb2e8f9f7 22279 @{ */
<> 144:ef7eb2e8f9f7 22280
<> 144:ef7eb2e8f9f7 22281 typedef struct {
<> 144:ef7eb2e8f9f7 22282
<> 144:ef7eb2e8f9f7 22283 /**
<> 144:ef7eb2e8f9f7 22284 * FBx
<> 144:ef7eb2e8f9f7 22285 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22286 * Offset: 0x00 ~ 0x7C Shared Buffer (FIFO) 0 ~ 31
<> 144:ef7eb2e8f9f7 22287 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22288 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22289 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22290 * |[0:31] |BUF |Shared Buffer
<> 144:ef7eb2e8f9f7 22291
<> 144:ef7eb2e8f9f7 22292 */
<> 144:ef7eb2e8f9f7 22293 uint32_t FB[32];
<> 144:ef7eb2e8f9f7 22294 uint32_t RESERVE0[224];
<> 144:ef7eb2e8f9f7 22295
<> 144:ef7eb2e8f9f7 22296
<> 144:ef7eb2e8f9f7 22297 /**
<> 144:ef7eb2e8f9f7 22298 * DMACTL
<> 144:ef7eb2e8f9f7 22299 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22300 * Offset: 0x400 DMA Control and Status Register
<> 144:ef7eb2e8f9f7 22301 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22302 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22303 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22304 * |[0] |DMAEN |DMA Engine Enable Control
<> 144:ef7eb2e8f9f7 22305 * | | |0 = DMA Disabled.
<> 144:ef7eb2e8f9f7 22306 * | | |1 = DMA Enabled.
<> 144:ef7eb2e8f9f7 22307 * | | |If this bit is cleared, DMA will ignore all requests from SD host and force bus master into IDLE state.
<> 144:ef7eb2e8f9f7 22308 * | | |Note: If target abort is occurred, DMAEN will be cleared.
<> 144:ef7eb2e8f9f7 22309 * |[1] |DMARST |Software Engine Reset
<> 144:ef7eb2e8f9f7 22310 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 22311 * | | |1 = Reset internal state machine and pointers.
<> 144:ef7eb2e8f9f7 22312 * | | |The contents of control register will not be cleared.
<> 144:ef7eb2e8f9f7 22313 * | | |This bit will auto be cleared after few clock cycles.
<> 144:ef7eb2e8f9f7 22314 * | | |Note: The software reset DMA related registers.
<> 144:ef7eb2e8f9f7 22315 * |[3] |SGEN |Scatter-Gather Function Enable Control
<> 144:ef7eb2e8f9f7 22316 * | | |0 = Scatter-gather function Disabled (DMA will treat the starting address in DMASAR as starting pointer of a single block memory).
<> 144:ef7eb2e8f9f7 22317 * | | |1 = Scatter-gather function Enabled (DMA will treat the starting address in DMASAR as a starting address of Physical Address Descriptor (PAD) table.
<> 144:ef7eb2e8f9f7 22318 * | | |The format of these Pads' will be described later).
<> 144:ef7eb2e8f9f7 22319 * |[9] |DMABUSY |DMA Transfer Is In Progress
<> 144:ef7eb2e8f9f7 22320 * | | |This bit indicates if SD Host is granted and doing DMA transfer or not.
<> 144:ef7eb2e8f9f7 22321 * | | |0 = DMA transfer is not in progress.
<> 144:ef7eb2e8f9f7 22322 * | | |1 = DMA transfer is in progress.
<> 144:ef7eb2e8f9f7 22323 */
<> 144:ef7eb2e8f9f7 22324 __IO uint32_t DMACTL;
<> 144:ef7eb2e8f9f7 22325 uint32_t RESERVE1[1];
<> 144:ef7eb2e8f9f7 22326
<> 144:ef7eb2e8f9f7 22327
<> 144:ef7eb2e8f9f7 22328 /**
<> 144:ef7eb2e8f9f7 22329 * DMASA
<> 144:ef7eb2e8f9f7 22330 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22331 * Offset: 0x408 DMA Transfer Starting Address Register
<> 144:ef7eb2e8f9f7 22332 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22333 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22334 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22335 * |[0] |ORDER |Determined To The PAD Table Fetching Is In Order Or Out Of Order
<> 144:ef7eb2e8f9f7 22336 * | | |0 = PAD table is fetched in order.
<> 144:ef7eb2e8f9f7 22337 * | | |1 = PAD table is fetched out of order.
<> 144:ef7eb2e8f9f7 22338 * | | |Note: the bit0 is valid in scatter-gather mode when SGEN = 1.
<> 144:ef7eb2e8f9f7 22339 * |[1:31] |DMASA |DMA Transfer Starting Address
<> 144:ef7eb2e8f9f7 22340 * | | |This field pads 0 as least significant bit indicates a 32-bit starting address of system memory (SRAM) for DMA to retrieve or fill in data.
<> 144:ef7eb2e8f9f7 22341 * | | |If DMA is not in normal mode, this field will be interpreted as a starting address of Physical Address Descriptor (PAD) table.
<> 144:ef7eb2e8f9f7 22342 */
<> 144:ef7eb2e8f9f7 22343 __IO uint32_t DMASA;
<> 144:ef7eb2e8f9f7 22344
<> 144:ef7eb2e8f9f7 22345 /**
<> 144:ef7eb2e8f9f7 22346 * DMABCNT
<> 144:ef7eb2e8f9f7 22347 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22348 * Offset: 0x40C DMA Transfer Byte Count Register
<> 144:ef7eb2e8f9f7 22349 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22350 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22351 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22352 * |[0:25] |BCNT |DMA Transfer Byte Count (Read Only)
<> 144:ef7eb2e8f9f7 22353 * | | |This field indicates the remained byte count of DMA transfer.
<> 144:ef7eb2e8f9f7 22354 * | | |The value of this field is valid only when DMA is busy; otherwise, it is 0.
<> 144:ef7eb2e8f9f7 22355 */
<> 144:ef7eb2e8f9f7 22356 __I uint32_t DMABCNT;
<> 144:ef7eb2e8f9f7 22357
<> 144:ef7eb2e8f9f7 22358 /**
<> 144:ef7eb2e8f9f7 22359 * DMAINTEN
<> 144:ef7eb2e8f9f7 22360 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22361 * Offset: 0x410 DMA Interrupt Enable Control Register
<> 144:ef7eb2e8f9f7 22362 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22363 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22364 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22365 * |[0] |ABORTIEN |DMA Read/Write Target Abort Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22366 * | | |0 = Target abort interrupt generation Disabled during DMA transfer.
<> 144:ef7eb2e8f9f7 22367 * | | |1 = Target abort interrupt generation Enabled during DMA transfer.
<> 144:ef7eb2e8f9f7 22368 * |[1] |WEOTIEN |Wrong EOT Encountered Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22369 * | | |0 = Interrupt generation Disabled when wrong EOT is encountered.
<> 144:ef7eb2e8f9f7 22370 * | | |1 = Interrupt generation Enabled when wrong EOT is encountered.
<> 144:ef7eb2e8f9f7 22371 */
<> 144:ef7eb2e8f9f7 22372 __IO uint32_t DMAINTEN;
<> 144:ef7eb2e8f9f7 22373
<> 144:ef7eb2e8f9f7 22374 /**
<> 144:ef7eb2e8f9f7 22375 * DMAINTSTS
<> 144:ef7eb2e8f9f7 22376 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22377 * Offset: 0x414 DMA Interrupt Status Register
<> 144:ef7eb2e8f9f7 22378 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22379 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22380 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22381 * |[0] |ABORTIF |DMA Read/Write Target Abort Interrupt Flag
<> 144:ef7eb2e8f9f7 22382 * | | |0 = No bus ERROR response received.
<> 144:ef7eb2e8f9f7 22383 * | | |1 = Bus ERROR response received.
<> 144:ef7eb2e8f9f7 22384 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22385 * |[1] |WEOTIF |Wrong EOT Encountered Interrupt Flag
<> 144:ef7eb2e8f9f7 22386 * | | |When DMA Scatter-Gather function is enabled, and EOT of the descriptor is encountered before DMA transfer finished (that means the total sector count of all PAD is less than the sector count of SD host), this bit will be set.
<> 144:ef7eb2e8f9f7 22387 * | | |0 = No EOT encountered before DMA transfer finished.
<> 144:ef7eb2e8f9f7 22388 * | | |1 = EOT encountered before DMA transfer finished.
<> 144:ef7eb2e8f9f7 22389 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22390 */
<> 144:ef7eb2e8f9f7 22391 __IO uint32_t DMAINTSTS;
<> 144:ef7eb2e8f9f7 22392 uint32_t RESERVE2[250];
<> 144:ef7eb2e8f9f7 22393
<> 144:ef7eb2e8f9f7 22394
<> 144:ef7eb2e8f9f7 22395 /**
<> 144:ef7eb2e8f9f7 22396 * GCTL
<> 144:ef7eb2e8f9f7 22397 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22398 * Offset: 0x800 Global Control and Status Register
<> 144:ef7eb2e8f9f7 22399 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22400 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22401 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22402 * |[0] |GCTLRST |Software Engine Reset
<> 144:ef7eb2e8f9f7 22403 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 22404 * | | |1 = Reset SD host.
<> 144:ef7eb2e8f9f7 22405 * | | |The contents of control register will not be cleared.
<> 144:ef7eb2e8f9f7 22406 * | | |This bit will auto cleared after reset complete.
<> 144:ef7eb2e8f9f7 22407 * |[1] |SDEN |Secure Digital Functionality Enable Control
<> 144:ef7eb2e8f9f7 22408 * | | |0 = SD functionality disabled.
<> 144:ef7eb2e8f9f7 22409 * | | |1 = SD functionality enabled.
<> 144:ef7eb2e8f9f7 22410 */
<> 144:ef7eb2e8f9f7 22411 __IO uint32_t GCTL;
<> 144:ef7eb2e8f9f7 22412
<> 144:ef7eb2e8f9f7 22413 /**
<> 144:ef7eb2e8f9f7 22414 * GINTEN
<> 144:ef7eb2e8f9f7 22415 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22416 * Offset: 0x804 Global Interrupt Control Register
<> 144:ef7eb2e8f9f7 22417 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22418 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22419 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22420 * |[0] |DTAIEN |DMA READ/WRITE Target Abort Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22421 * | | |0 = DMA READ/WRITE target abort interrupt generation disabled.
<> 144:ef7eb2e8f9f7 22422 * | | |1 = DMA READ/WRITE target abort interrupt generation enabled.
<> 144:ef7eb2e8f9f7 22423 */
<> 144:ef7eb2e8f9f7 22424 __IO uint32_t GINTEN;
<> 144:ef7eb2e8f9f7 22425
<> 144:ef7eb2e8f9f7 22426 /**
<> 144:ef7eb2e8f9f7 22427 * GINTSTS
<> 144:ef7eb2e8f9f7 22428 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22429 * Offset: 0x808 Global Interrupt Status Register
<> 144:ef7eb2e8f9f7 22430 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22431 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22432 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22433 * |[0] |DTAIF |DMA READ/WRITE Target Abort Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 22434 * | | |This bit indicates DMA received an ERROR response from internal AHB bus during DMA read/write operation.
<> 144:ef7eb2e8f9f7 22435 * | | |When Target Abort is occurred, please reset all engine.
<> 144:ef7eb2e8f9f7 22436 * | | |0 = No bus ERROR response received.
<> 144:ef7eb2e8f9f7 22437 * | | |1 = Bus ERROR response received.
<> 144:ef7eb2e8f9f7 22438 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22439 */
<> 144:ef7eb2e8f9f7 22440 __I uint32_t GINTSTS;
<> 144:ef7eb2e8f9f7 22441 uint32_t RESERVE3[5];
<> 144:ef7eb2e8f9f7 22442
<> 144:ef7eb2e8f9f7 22443
<> 144:ef7eb2e8f9f7 22444 /**
<> 144:ef7eb2e8f9f7 22445 * CTL
<> 144:ef7eb2e8f9f7 22446 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22447 * Offset: 0x820 SD Control and Status Register
<> 144:ef7eb2e8f9f7 22448 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22449 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22450 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22451 * |[0] |COEN |Command Output Enable Control
<> 144:ef7eb2e8f9f7 22452 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
<> 144:ef7eb2e8f9f7 22453 * | | |1 = Enabled, SD host will output a command to SD card.
<> 144:ef7eb2e8f9f7 22454 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
<> 144:ef7eb2e8f9f7 22455 * |[1] |RIEN |Response Input Enable Control
<> 144:ef7eb2e8f9f7 22456 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
<> 144:ef7eb2e8f9f7 22457 * | | |1 = Enabled, SD host will wait to receive a response from SD card.
<> 144:ef7eb2e8f9f7 22458 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
<> 144:ef7eb2e8f9f7 22459 * |[2] |DIEN |Data Input Enable Control
<> 144:ef7eb2e8f9f7 22460 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
<> 144:ef7eb2e8f9f7 22461 * | | |1 = Enabled, SD host will wait to receive block data and the CRC16 value from SD card.
<> 144:ef7eb2e8f9f7 22462 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
<> 144:ef7eb2e8f9f7 22463 * |[3] |DOEN |Data Output Enable Control
<> 144:ef7eb2e8f9f7 22464 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
<> 144:ef7eb2e8f9f7 22465 * | | |1 = Enabled, SD host will transfer block data and the CRC16 value to SD card.
<> 144:ef7eb2e8f9f7 22466 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
<> 144:ef7eb2e8f9f7 22467 * |[4] |R2EN |Response R2 Input Enable Control
<> 144:ef7eb2e8f9f7 22468 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
<> 144:ef7eb2e8f9f7 22469 * | | |1 = Enabled, SD host will wait to receive a response R2 from SD card and store the response data into DMC's flash buffer (exclude CRC7).
<> 144:ef7eb2e8f9f7 22470 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
<> 144:ef7eb2e8f9f7 22471 * |[5] |CLK74OEN |Initial 74 Clock Cycles Output Enable Control
<> 144:ef7eb2e8f9f7 22472 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
<> 144:ef7eb2e8f9f7 22473 * | | |1 = Enabled, SD host will output 74 clock cycles to SD card.
<> 144:ef7eb2e8f9f7 22474 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
<> 144:ef7eb2e8f9f7 22475 * |[6] |CLK8OEN |Generating 8 Clock Cycles Output Enable Control
<> 144:ef7eb2e8f9f7 22476 * | | |0 = No effect. (Please use DMARST (SDH_CTL [0]) to clear this bit.)
<> 144:ef7eb2e8f9f7 22477 * | | |1 = Enabled, SD host will output 8 clock cycles.
<> 144:ef7eb2e8f9f7 22478 * | | |Note: When operation is finished, this bit will be cleared automatically, so don't write 0 to this bit (the controller will be abnormal).
<> 144:ef7eb2e8f9f7 22479 * |[7] |CLKKEEP0 |SD Clock Enable Control For Port 0
<> 144:ef7eb2e8f9f7 22480 * | | |0 = SD host decided when to output clock and when to disable clock output automatically.
<> 144:ef7eb2e8f9f7 22481 * | | |1 = SD clock always keeps free running.
<> 144:ef7eb2e8f9f7 22482 * |[8:13] |CMDCODE |SD Command Code
<> 144:ef7eb2e8f9f7 22483 * | | |This register contains the SD command code (0x00 - 0x3F).
<> 144:ef7eb2e8f9f7 22484 * |[14] |CTLRST |Software Engine Reset
<> 144:ef7eb2e8f9f7 22485 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 22486 * | | |1 = Reset the internal state machine and counters.
<> 144:ef7eb2e8f9f7 22487 * | | |The contents of control register will not be cleared (but RIEN, DIEN, DOEN and R2_EN will be cleared).
<> 144:ef7eb2e8f9f7 22488 * | | |This bit will be auto cleared after few clock cycles.
<> 144:ef7eb2e8f9f7 22489 * |[15] |DBW |SD Data Bus Width (For 1-Bit / 4-Bit Selection)
<> 144:ef7eb2e8f9f7 22490 * | | |0 = Data bus width is 1-bit.
<> 144:ef7eb2e8f9f7 22491 * | | |1 = Data bus width is 4-bit.
<> 144:ef7eb2e8f9f7 22492 * |[16:23] |BLKCNT |Block Counts To Be Transferred Or Received
<> 144:ef7eb2e8f9f7 22493 * | | |This field contains the block counts for data-in and data-out transfer.
<> 144:ef7eb2e8f9f7 22494 * | | |For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, software can use this function to accelerate data transfer and improve performance.
<> 144:ef7eb2e8f9f7 22495 * | | |Don't fill 0x0 to this field.
<> 144:ef7eb2e8f9f7 22496 * | | |Note: For READ_MULTIPLE_BLOCK and WRITE_MULTIPLE_BLOCK command, the actual total length is BLKCNT * (BLKLEN +1).
<> 144:ef7eb2e8f9f7 22497 * |[24:27] |SDNWR |NWR Parameter For Block Write Operation
<> 144:ef7eb2e8f9f7 22498 * | | |This value indicates the NWR parameter for data block write operation in SD clock counts.
<> 144:ef7eb2e8f9f7 22499 * | | |The actual clock cycle will be SDNWR+1.
<> 144:ef7eb2e8f9f7 22500 * |[29:30] |SDPORT |SD Port Selection
<> 144:ef7eb2e8f9f7 22501 * | | |00 = Port 0 selected.
<> 144:ef7eb2e8f9f7 22502 * | | |01 = Port 1 selected.
<> 144:ef7eb2e8f9f7 22503 * | | |Other = Reserved.
<> 144:ef7eb2e8f9f7 22504 * |[31] |CLKKEEP1 |SD Clock Enable Control For Port 1
<> 144:ef7eb2e8f9f7 22505 * | | |0 = SD host decided when to output clock and when to disable clock output automatically.
<> 144:ef7eb2e8f9f7 22506 * | | |1 = SD clock always keeps free running.
<> 144:ef7eb2e8f9f7 22507 */
<> 144:ef7eb2e8f9f7 22508 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 22509
<> 144:ef7eb2e8f9f7 22510 /**
<> 144:ef7eb2e8f9f7 22511 * CMDARG
<> 144:ef7eb2e8f9f7 22512 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22513 * Offset: 0x824 SD Command Argument Register
<> 144:ef7eb2e8f9f7 22514 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22515 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22516 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22517 * |[0:31] |ARGUMENT |SD Command Argument
<> 144:ef7eb2e8f9f7 22518 * | | |This register contains a 32-bit value specifies the argument of SD command from host controller to SD card.
<> 144:ef7eb2e8f9f7 22519 * | | |Before trigger COEN (SDH_CTL [0]), software should fill argument in this field.
<> 144:ef7eb2e8f9f7 22520 */
<> 144:ef7eb2e8f9f7 22521 __IO uint32_t CMDARG;
<> 144:ef7eb2e8f9f7 22522
<> 144:ef7eb2e8f9f7 22523 /**
<> 144:ef7eb2e8f9f7 22524 * INTEN
<> 144:ef7eb2e8f9f7 22525 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22526 * Offset: 0x828 SD Interrupt Control Register
<> 144:ef7eb2e8f9f7 22527 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22528 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22529 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22530 * |[0] |BLKDIEN |Block Transfer Done Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22531 * | | |0 = SD host will not generate interrupt when data-in (out) transfer done.
<> 144:ef7eb2e8f9f7 22532 * | | |1 = SD host will generate interrupt when data-in (out) transfer done.
<> 144:ef7eb2e8f9f7 22533 * |[1] |CRCIEN |CRC7, CRC16 And CRC Status Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22534 * | | |0 = SD host will not generate interrupt when CRC7, CRC16 and CRC status is error.
<> 144:ef7eb2e8f9f7 22535 * | | |1 = SD host will generate interrupt when CRC7, CRC16 and CRC status is error.
<> 144:ef7eb2e8f9f7 22536 * |[8] |CDIEN0 |SD0 Card Detection Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22537 * | | |Enable/Disable interrupts generation of SD controller when card 0 is inserted or removed.
<> 144:ef7eb2e8f9f7 22538 * | | |0 = Disable.
<> 144:ef7eb2e8f9f7 22539 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 22540 * |[9] |CDIEN1 |SD1 Card Detection Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22541 * | | |Enable/Disable interrupts generation of SD controller when card 1 is inserted or removed.
<> 144:ef7eb2e8f9f7 22542 * | | |0 = Disable.
<> 144:ef7eb2e8f9f7 22543 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 22544 * |[12] |RTOIEN |Response Time-Out Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22545 * | | |Enable/Disable interrupts generation of SD controller when receiving response or R2 time-out.
<> 144:ef7eb2e8f9f7 22546 * | | |Time-out value is specified at TOUT register.
<> 144:ef7eb2e8f9f7 22547 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 22548 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 22549 * |[13] |DITOIEN |Data Input Time-Out Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22550 * | | |Enable/Disable interrupts generation of SD controller when data input time-out.
<> 144:ef7eb2e8f9f7 22551 * | | |Time-out value is specified at TOUT register.
<> 144:ef7eb2e8f9f7 22552 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 22553 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 22554 * |[14] |WKIEN |Wake-Up Signal Generating Enable Control
<> 144:ef7eb2e8f9f7 22555 * | | |Enable/Disable wake-up signal generating of SD host when current using SD card issues an interrupt (wake-up) via DAT [1] to host.
<> 144:ef7eb2e8f9f7 22556 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 22557 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 22558 * |[30] |CDSRC0 |SD0 Card Detect Source Selection
<> 144:ef7eb2e8f9f7 22559 * | | |0 = From SD0 card's DAT3 pin.
<> 144:ef7eb2e8f9f7 22560 * | | |Host need clock to got data on pin DAT3.
<> 144:ef7eb2e8f9f7 22561 * | | |Please make sure CLKKEEP0 (SDH_CTL[7]) is 1 in order to generate free running clock for DAT3 pin.
<> 144:ef7eb2e8f9f7 22562 * | | |1 = From GPIO pin.
<> 144:ef7eb2e8f9f7 22563 * |[31] |CDSRC1 |SD1 Card Detect Source Selection
<> 144:ef7eb2e8f9f7 22564 * | | |0 = From SD1 card's DAT3 pin.
<> 144:ef7eb2e8f9f7 22565 * | | |Host need clock to got data on pin DAT3.
<> 144:ef7eb2e8f9f7 22566 * | | |Please make sure CLKKEEP1 (SDH_CTL[31]) is 1 in order to generate free running clock for DAT3 pin.
<> 144:ef7eb2e8f9f7 22567 * | | |1 = From GPIO pin.
<> 144:ef7eb2e8f9f7 22568 */
<> 144:ef7eb2e8f9f7 22569 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 22570
<> 144:ef7eb2e8f9f7 22571 /**
<> 144:ef7eb2e8f9f7 22572 * INTSTS
<> 144:ef7eb2e8f9f7 22573 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22574 * Offset: 0x82C SD Interrupt Status Register
<> 144:ef7eb2e8f9f7 22575 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22576 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22577 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22578 * |[0] |BLKDIF |Block Transfer Done Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 22579 * | | |This bit indicates that SD host has finished all data-in or data-out block transfer.
<> 144:ef7eb2e8f9f7 22580 * | | |If there is a CRC16 error or incorrect CRC status during multiple block data transfer, the transfer will be broken and this bit will also be set.
<> 144:ef7eb2e8f9f7 22581 * | | |0 = Not finished yet.
<> 144:ef7eb2e8f9f7 22582 * | | |1 = Done.
<> 144:ef7eb2e8f9f7 22583 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22584 * |[1] |CRCIF |CRC7, CRC16 And CRC Status Error Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 22585 * | | |This bit indicates that SD host has occurred CRC error during response in, data-in or data-out (CRC status error) transfer.
<> 144:ef7eb2e8f9f7 22586 * | | |When CRC error is occurred, software should reset SD engine.
<> 144:ef7eb2e8f9f7 22587 * | | |Some response (ex.
<> 144:ef7eb2e8f9f7 22588 * | | |R3) doesn't have CRC7 information with it; SD host will still calculate CRC7, get CRC error and set this flag.
<> 144:ef7eb2e8f9f7 22589 * | | |In this condition, software should ignore CRC error and clears this bit manually.
<> 144:ef7eb2e8f9f7 22590 * | | |0 = No CRC error is occurred.
<> 144:ef7eb2e8f9f7 22591 * | | |1 = CRC error is occurred.
<> 144:ef7eb2e8f9f7 22592 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22593 * |[2] |CRC7 |CRC7 Check Status (Read Only)
<> 144:ef7eb2e8f9f7 22594 * | | |SD host will check CRC7 correctness during each response in.
<> 144:ef7eb2e8f9f7 22595 * | | |If that response does not contain CRC7 information (ex.
<> 144:ef7eb2e8f9f7 22596 * | | |R3), then software should turn off CRCIEN (SDH_INTEN[1]) and ignore this bit.
<> 144:ef7eb2e8f9f7 22597 * | | |0 = Fault.
<> 144:ef7eb2e8f9f7 22598 * | | |1 = OK.
<> 144:ef7eb2e8f9f7 22599 * |[3] |CRC16 |CRC16 Check Status Of Data-In Transfer (Read Only)
<> 144:ef7eb2e8f9f7 22600 * | | |SD host will check CRC16 correctness after data-in transfer.
<> 144:ef7eb2e8f9f7 22601 * | | |0 = Fault.
<> 144:ef7eb2e8f9f7 22602 * | | |1 = OK.
<> 144:ef7eb2e8f9f7 22603 * |[4:6] |CRCSTS |CRC Status Value Of Data-Out Transfer (Read Only)
<> 144:ef7eb2e8f9f7 22604 * | | |SD host will record CRC status of data-out transfer.
<> 144:ef7eb2e8f9f7 22605 * | | |Software could use this value to identify what type of error is during data-out transfer.
<> 144:ef7eb2e8f9f7 22606 * | | |010 = Positive CRC status.
<> 144:ef7eb2e8f9f7 22607 * | | |101 = Negative CRC status.
<> 144:ef7eb2e8f9f7 22608 * | | |111 = SD card programming error occurs.
<> 144:ef7eb2e8f9f7 22609 * |[7] |DAT0STS |DAT0 Pin Status Of Current Selected SD Port (Read Only)
<> 144:ef7eb2e8f9f7 22610 * | | |This bit is the DAT0 pin status of current selected SD port.
<> 144:ef7eb2e8f9f7 22611 * |[8] |CDIF0 |SD0 Card Detection Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 22612 * | | |This bit indicates that SD card 0 is inserted or removed.
<> 144:ef7eb2e8f9f7 22613 * | | |Only when CDIEN0 (SDH_INTEN[8]) is set to 1, this bit is active.
<> 144:ef7eb2e8f9f7 22614 * | | |0 = No card is inserted or removed.
<> 144:ef7eb2e8f9f7 22615 * | | |1 = There is a card inserted in or removed from SD0.
<> 144:ef7eb2e8f9f7 22616 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22617 * |[9] |CDIF1 |SD1 Card Detection Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 22618 * | | |This bit indicates that SD card 1 is inserted or removed.
<> 144:ef7eb2e8f9f7 22619 * | | |Only when CDIEN1 (SDH_INTEN[9]) is set to 1, this bit is active.
<> 144:ef7eb2e8f9f7 22620 * | | |0 = No card is inserted or removed.
<> 144:ef7eb2e8f9f7 22621 * | | |1 = There is a card inserted in or removed from SD1.
<> 144:ef7eb2e8f9f7 22622 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22623 * |[12] |RTOIF |Response Time-Out Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 22624 * | | |This bit indicates that SD host counts to time-out value when receiving response or R2 (waiting start bit).
<> 144:ef7eb2e8f9f7 22625 * | | |0 = Not time-out.
<> 144:ef7eb2e8f9f7 22626 * | | |1 = Response time-out.
<> 144:ef7eb2e8f9f7 22627 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22628 * |[13] |DITOIF |Data Input Time-Out Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 22629 * | | |This bit indicates that SD host counts to time-out value when receiving data (waiting start bit).
<> 144:ef7eb2e8f9f7 22630 * | | |0 = Not time-out.
<> 144:ef7eb2e8f9f7 22631 * | | |1 = Data input time-out.
<> 144:ef7eb2e8f9f7 22632 * | | |Note: This bit is read only, but can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 22633 * |[16] |CDSTS0 |Card Detect Status Of SD0 (Read Only)
<> 144:ef7eb2e8f9f7 22634 * | | |This bit indicates the card detect pin status of SD0, and is used for card detection.
<> 144:ef7eb2e8f9f7 22635 * | | |When there is a card inserted in or removed from SD0, software should check this bit to confirm if there is really a card insertion or removal.
<> 144:ef7eb2e8f9f7 22636 * | | |If CDSRC0 (SDH_INTEN[30]) = 0, to select DAT3 for card detection:.
<> 144:ef7eb2e8f9f7 22637 * | | |0 = Card removed.
<> 144:ef7eb2e8f9f7 22638 * | | |1 = Card inserted.
<> 144:ef7eb2e8f9f7 22639 * | | |If CDSRC0 (SDH_INTEN[30]) = 1, to select GPIO for card detection:.
<> 144:ef7eb2e8f9f7 22640 * | | |0 = Card inserted.
<> 144:ef7eb2e8f9f7 22641 * | | |1 = Card removed.
<> 144:ef7eb2e8f9f7 22642 * |[17] |CDSTS1 |Card Detect Status Of SD1 (Read Only)
<> 144:ef7eb2e8f9f7 22643 * | | |This bit indicates the card detect pin status of SD1, and is used for card detection.
<> 144:ef7eb2e8f9f7 22644 * | | |When there is a card inserted in or removed from SD1, software should check this bit to confirm if there is really a card insertion or removal.
<> 144:ef7eb2e8f9f7 22645 * | | |If CDSRC1 (SDH_INTEN[31]) = 0, to select DAT3 for card detection:.
<> 144:ef7eb2e8f9f7 22646 * | | |0 = Card removed.
<> 144:ef7eb2e8f9f7 22647 * | | |1 = Card inserted.
<> 144:ef7eb2e8f9f7 22648 * | | |If CDSRC1 (SDH_INTEN[31]) = 1, to select GPIO for card detection:.
<> 144:ef7eb2e8f9f7 22649 * | | |0 = Card inserted.
<> 144:ef7eb2e8f9f7 22650 * | | |1 = Card removed.
<> 144:ef7eb2e8f9f7 22651 * |[18] |DAT1STS |DAT1 Pin Status Of SD Port (Read Only)
<> 144:ef7eb2e8f9f7 22652 * | | |This bit indicates the DAT1 pin status of SD port.
<> 144:ef7eb2e8f9f7 22653 */
<> 144:ef7eb2e8f9f7 22654 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 22655
<> 144:ef7eb2e8f9f7 22656 /**
<> 144:ef7eb2e8f9f7 22657 * RESP0
<> 144:ef7eb2e8f9f7 22658 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22659 * Offset: 0x830 SD Receiving Response Token Register 0
<> 144:ef7eb2e8f9f7 22660 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22661 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22662 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22663 * |[0:31] |RESPTK0 |SD Receiving Response Token 0
<> 144:ef7eb2e8f9f7 22664 * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set.
<> 144:ef7eb2e8f9f7 22665 * | | |This field contains response bit 47-16 of the response token.
<> 144:ef7eb2e8f9f7 22666 */
<> 144:ef7eb2e8f9f7 22667 __I uint32_t RESP0;
<> 144:ef7eb2e8f9f7 22668
<> 144:ef7eb2e8f9f7 22669 /**
<> 144:ef7eb2e8f9f7 22670 * RESP1
<> 144:ef7eb2e8f9f7 22671 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22672 * Offset: 0x834 SD Receiving Response Token Register 1
<> 144:ef7eb2e8f9f7 22673 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22674 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22675 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22676 * |[0:7] |RESPTK1 |SD Receiving Response Token 1
<> 144:ef7eb2e8f9f7 22677 * | | |SD host controller will receive a response token for getting a reply from SD card when RIEN (SDH_CTL[1]) is set.
<> 144:ef7eb2e8f9f7 22678 * | | |This register contains the bit 15-8 of the response token.
<> 144:ef7eb2e8f9f7 22679 */
<> 144:ef7eb2e8f9f7 22680 __I uint32_t RESP1;
<> 144:ef7eb2e8f9f7 22681
<> 144:ef7eb2e8f9f7 22682 /**
<> 144:ef7eb2e8f9f7 22683 * BLEN
<> 144:ef7eb2e8f9f7 22684 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22685 * Offset: 0x838 SD Block Length Register
<> 144:ef7eb2e8f9f7 22686 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22687 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22688 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22689 * |[0:10] |BLKLEN |SD BLOCK LENGTH In Byte Unit
<> 144:ef7eb2e8f9f7 22690 * | | |An 11-bit value specifies the SD transfer byte count of a block.
<> 144:ef7eb2e8f9f7 22691 * | | |The actual byte count is equal to BLKLEN+1.
<> 144:ef7eb2e8f9f7 22692 * | | |Note: The default SD block length is 512 bytes
<> 144:ef7eb2e8f9f7 22693 */
<> 144:ef7eb2e8f9f7 22694 __IO uint32_t BLEN;
<> 144:ef7eb2e8f9f7 22695
<> 144:ef7eb2e8f9f7 22696 /**
<> 144:ef7eb2e8f9f7 22697 * TOUT
<> 144:ef7eb2e8f9f7 22698 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22699 * Offset: 0x83C SD Response/Data-in Time-out Register
<> 144:ef7eb2e8f9f7 22700 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22701 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22702 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22703 * |[0:23] |TOUT |SD Response/Data-In Time-Out Value
<> 144:ef7eb2e8f9f7 22704 * | | |A 24-bit value specifies the time-out counts of response and data input.
<> 144:ef7eb2e8f9f7 22705 * | | |SD host controller will wait start bit of response or data-in until this value reached.
<> 144:ef7eb2e8f9f7 22706 * | | |The time period depends on SD engine clock frequency.
<> 144:ef7eb2e8f9f7 22707 * | | |Do not write a small number into this field, or you may never get response or data due to time-out.
<> 144:ef7eb2e8f9f7 22708 * | | |Note: Filling 0x0 into this field will disable hardware time-out function.
<> 144:ef7eb2e8f9f7 22709 */
<> 144:ef7eb2e8f9f7 22710 __IO uint32_t TOUT;
<> 144:ef7eb2e8f9f7 22711
<> 144:ef7eb2e8f9f7 22712 } SDH_T;
<> 144:ef7eb2e8f9f7 22713
<> 144:ef7eb2e8f9f7 22714 /**
<> 144:ef7eb2e8f9f7 22715 @addtogroup SDH_CONST SDH Bit Field Definition
<> 144:ef7eb2e8f9f7 22716 Constant Definitions for SDH Controller
<> 144:ef7eb2e8f9f7 22717 @{ */
<> 144:ef7eb2e8f9f7 22718
<> 144:ef7eb2e8f9f7 22719 #define SDH_DMACTL_DMAEN_Pos (0) /*!< SDH DMACTL: DMAEN Position */
<> 144:ef7eb2e8f9f7 22720 #define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) /*!< SDH DMACTL: DMAEN Mask */
<> 144:ef7eb2e8f9f7 22721
<> 144:ef7eb2e8f9f7 22722 #define SDH_DMACTL_DMARST_Pos (1) /*!< SDH DMACTL: DMARST Position */
<> 144:ef7eb2e8f9f7 22723 #define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) /*!< SDH DMACTL: DMARST Mask */
<> 144:ef7eb2e8f9f7 22724
<> 144:ef7eb2e8f9f7 22725 #define SDH_DMACTL_SGEN_Pos (3) /*!< SDH DMACTL: SGEN Position */
<> 144:ef7eb2e8f9f7 22726 #define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) /*!< SDH DMACTL: SGEN Mask */
<> 144:ef7eb2e8f9f7 22727
<> 144:ef7eb2e8f9f7 22728 #define SDH_DMACTL_DMABUSY_Pos (9) /*!< SDH DMACTL: DMABUSY Position */
<> 144:ef7eb2e8f9f7 22729 #define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) /*!< SDH DMACTL: DMABUSY Mask */
<> 144:ef7eb2e8f9f7 22730
<> 144:ef7eb2e8f9f7 22731 #define SDH_DMASA_ORDER_Pos (0) /*!< SDH DMASA: ORDER Position */
<> 144:ef7eb2e8f9f7 22732 #define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) /*!< SDH DMASA: ORDER Mask */
<> 144:ef7eb2e8f9f7 22733
<> 144:ef7eb2e8f9f7 22734 #define SDH_DMASA_DMASA_Pos (1) /*!< SDH DMASA: DMASA Position */
<> 144:ef7eb2e8f9f7 22735 #define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) /*!< SDH DMASA: DMASA Mask */
<> 144:ef7eb2e8f9f7 22736
<> 144:ef7eb2e8f9f7 22737 #define SDH_DMABCNT_BCNT_Pos (0) /*!< SDH DMABCNT: BCNT Position */
<> 144:ef7eb2e8f9f7 22738 #define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) /*!< SDH DMABCNT: BCNT Mask */
<> 144:ef7eb2e8f9f7 22739
<> 144:ef7eb2e8f9f7 22740 #define SDH_DMAINTEN_ABORTIEN_Pos (0) /*!< SDH DMAINTEN: ABORTIEN Position */
<> 144:ef7eb2e8f9f7 22741 #define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) /*!< SDH DMAINTEN: ABORTIEN Mask */
<> 144:ef7eb2e8f9f7 22742
<> 144:ef7eb2e8f9f7 22743 #define SDH_DMAINTEN_WEOTIEN_Pos (1) /*!< SDH DMAINTEN: WEOTIEN Position */
<> 144:ef7eb2e8f9f7 22744 #define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) /*!< SDH DMAINTEN: WEOTIEN Mask */
<> 144:ef7eb2e8f9f7 22745
<> 144:ef7eb2e8f9f7 22746 #define SDH_DMAINTSTS_ABORTIF_Pos (0) /*!< SDH DMAINTSTS: ABORTIF Position */
<> 144:ef7eb2e8f9f7 22747 #define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) /*!< SDH DMAINTSTS: ABORTIF Mask */
<> 144:ef7eb2e8f9f7 22748
<> 144:ef7eb2e8f9f7 22749 #define SDH_DMAINTSTS_WEOTIF_Pos (1) /*!< SDH DMAINTSTS: WEOTIF Position */
<> 144:ef7eb2e8f9f7 22750 #define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) /*!< SDH DMAINTSTS: WEOTIF Mask */
<> 144:ef7eb2e8f9f7 22751
<> 144:ef7eb2e8f9f7 22752 #define SDH_GCTL_GCTLRST_Pos (0) /*!< SDH GCTL: GCTLRST Position */
<> 144:ef7eb2e8f9f7 22753 #define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) /*!< SDH GCTL: GCTLRST Mask */
<> 144:ef7eb2e8f9f7 22754
<> 144:ef7eb2e8f9f7 22755 #define SDH_GCTL_SDEN_Pos (1) /*!< SDH GCTL: SDEN Position */
<> 144:ef7eb2e8f9f7 22756 #define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) /*!< SDH GCTL: SDEN Mask */
<> 144:ef7eb2e8f9f7 22757
<> 144:ef7eb2e8f9f7 22758 #define SDH_GINTEN_DTAIEN_Pos (0) /*!< SDH GINTEN: DTAIEN Position */
<> 144:ef7eb2e8f9f7 22759 #define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) /*!< SDH GINTEN: DTAIEN Mask */
<> 144:ef7eb2e8f9f7 22760
<> 144:ef7eb2e8f9f7 22761 #define SDH_GINTSTS_DTAIF_Pos (0) /*!< SDH GINTSTS: DTAIF Position */
<> 144:ef7eb2e8f9f7 22762 #define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) /*!< SDH GINTSTS: DTAIF Mask */
<> 144:ef7eb2e8f9f7 22763
<> 144:ef7eb2e8f9f7 22764 #define SDH_CTL_COEN_Pos (0) /*!< SDH CTL: COEN Position */
<> 144:ef7eb2e8f9f7 22765 #define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) /*!< SDH CTL: COEN Mask */
<> 144:ef7eb2e8f9f7 22766
<> 144:ef7eb2e8f9f7 22767 #define SDH_CTL_RIEN_Pos (1) /*!< SDH CTL: RIEN Position */
<> 144:ef7eb2e8f9f7 22768 #define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) /*!< SDH CTL: RIEN Mask */
<> 144:ef7eb2e8f9f7 22769
<> 144:ef7eb2e8f9f7 22770 #define SDH_CTL_DIEN_Pos (2) /*!< SDH CTL: DIEN Position */
<> 144:ef7eb2e8f9f7 22771 #define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) /*!< SDH CTL: DIEN Mask */
<> 144:ef7eb2e8f9f7 22772
<> 144:ef7eb2e8f9f7 22773 #define SDH_CTL_DOEN_Pos (3) /*!< SDH CTL: DOEN Position */
<> 144:ef7eb2e8f9f7 22774 #define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) /*!< SDH CTL: DOEN Mask */
<> 144:ef7eb2e8f9f7 22775
<> 144:ef7eb2e8f9f7 22776 #define SDH_CTL_R2EN_Pos (4) /*!< SDH CTL: R2EN Position */
<> 144:ef7eb2e8f9f7 22777 #define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) /*!< SDH CTL: R2EN Mask */
<> 144:ef7eb2e8f9f7 22778
<> 144:ef7eb2e8f9f7 22779 #define SDH_CTL_CLK74OEN_Pos (5) /*!< SDH CTL: CLK74OEN Position */
<> 144:ef7eb2e8f9f7 22780 #define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) /*!< SDH CTL: CLK74OEN Mask */
<> 144:ef7eb2e8f9f7 22781
<> 144:ef7eb2e8f9f7 22782 #define SDH_CTL_CLK8OEN_Pos (6) /*!< SDH CTL: CLK8OEN Position */
<> 144:ef7eb2e8f9f7 22783 #define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) /*!< SDH CTL: CLK8OEN Mask */
<> 144:ef7eb2e8f9f7 22784
<> 144:ef7eb2e8f9f7 22785 #define SDH_CTL_CLKKEEP0_Pos (7) /*!< SDH CTL: CLKKEEP0 Position */
<> 144:ef7eb2e8f9f7 22786 #define SDH_CTL_CLKKEEP0_Msk (0x1ul << SDH_CTL_CLKKEEP0_Pos) /*!< SDH CTL: CLKKEEP0 Mask */
<> 144:ef7eb2e8f9f7 22787
<> 144:ef7eb2e8f9f7 22788 #define SDH_CTL_CMDCODE_Pos (8) /*!< SDH CTL: CMDCODE Position */
<> 144:ef7eb2e8f9f7 22789 #define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) /*!< SDH CTL: CMDCODE Mask */
<> 144:ef7eb2e8f9f7 22790
<> 144:ef7eb2e8f9f7 22791 #define SDH_CTL_CTLRST_Pos (14) /*!< SDH CTL: CTLRST Position */
<> 144:ef7eb2e8f9f7 22792 #define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) /*!< SDH CTL: CTLRST Mask */
<> 144:ef7eb2e8f9f7 22793
<> 144:ef7eb2e8f9f7 22794 #define SDH_CTL_DBW_Pos (15) /*!< SDH CTL: DBW Position */
<> 144:ef7eb2e8f9f7 22795 #define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) /*!< SDH CTL: DBW Mask */
<> 144:ef7eb2e8f9f7 22796
<> 144:ef7eb2e8f9f7 22797 #define SDH_CTL_BLKCNT_Pos (16) /*!< SDH CTL: BLKCNT Position */
<> 144:ef7eb2e8f9f7 22798 #define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) /*!< SDH CTL: BLKCNT Mask */
<> 144:ef7eb2e8f9f7 22799
<> 144:ef7eb2e8f9f7 22800 #define SDH_CTL_SDNWR_Pos (24) /*!< SDH CTL: SDNWR Position */
<> 144:ef7eb2e8f9f7 22801 #define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) /*!< SDH CTL: SDNWR Mask */
<> 144:ef7eb2e8f9f7 22802
<> 144:ef7eb2e8f9f7 22803 #define SDH_CTL_SDPORT_Pos (29) /*!< SDH CTL: SDPORT Position */
<> 144:ef7eb2e8f9f7 22804 #define SDH_CTL_SDPORT_Msk (0x3ul << SDH_CTL_SDPORT_Pos) /*!< SDH CTL: SDPORT Mask */
<> 144:ef7eb2e8f9f7 22805
<> 144:ef7eb2e8f9f7 22806 #define SDH_CTL_CLKKEEP1_Pos (31) /*!< SDH CTL: CLKKEEP1 Position */
<> 144:ef7eb2e8f9f7 22807 #define SDH_CTL_CLKKEEP1_Msk (0x1ul << SDH_CTL_CLKKEEP1_Pos) /*!< SDH CTL: CLKKEEP1 Mask */
<> 144:ef7eb2e8f9f7 22808
<> 144:ef7eb2e8f9f7 22809 #define SDH_CMDARG_ARGUMENT_Pos (0) /*!< SDH CMDARG: ARGUMENT Position */
<> 144:ef7eb2e8f9f7 22810 #define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) /*!< SDH CMDARG: ARGUMENT Mask */
<> 144:ef7eb2e8f9f7 22811
<> 144:ef7eb2e8f9f7 22812 #define SDH_INTEN_BLKDIEN_Pos (0) /*!< SDH INTEN: BLKDIEN Position */
<> 144:ef7eb2e8f9f7 22813 #define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) /*!< SDH INTEN: BLKDIEN Mask */
<> 144:ef7eb2e8f9f7 22814
<> 144:ef7eb2e8f9f7 22815 #define SDH_INTEN_CRCIEN_Pos (1) /*!< SDH INTEN: CRCIEN Position */
<> 144:ef7eb2e8f9f7 22816 #define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) /*!< SDH INTEN: CRCIEN Mask */
<> 144:ef7eb2e8f9f7 22817
<> 144:ef7eb2e8f9f7 22818 #define SDH_INTEN_CDIEN0_Pos (8) /*!< SDH INTEN: CDIEN0 Position */
<> 144:ef7eb2e8f9f7 22819 #define SDH_INTEN_CDIEN0_Msk (0x1ul << SDH_INTEN_CDIEN0_Pos) /*!< SDH INTEN: CDIEN0 Mask */
<> 144:ef7eb2e8f9f7 22820
<> 144:ef7eb2e8f9f7 22821 #define SDH_INTEN_CDIEN1_Pos (9) /*!< SDH INTEN: CDIEN1 Position */
<> 144:ef7eb2e8f9f7 22822 #define SDH_INTEN_CDIEN1_Msk (0x1ul << SDH_INTEN_CDIEN1_Pos) /*!< SDH INTEN: CDIEN1 Mask */
<> 144:ef7eb2e8f9f7 22823
<> 144:ef7eb2e8f9f7 22824 #define SDH_INTEN_SDHOST0IEN_Pos (10) /*!< SDH INTSTS: SDHOST0IEN Position */
<> 144:ef7eb2e8f9f7 22825 #define SDH_INTEN_SDHOST0IEN_Msk (0x1ul << SDH_INTEN_SDHOST0IEN_Pos) /*!< SDH INTSTS: SDHOST0IEN Mask */
<> 144:ef7eb2e8f9f7 22826
<> 144:ef7eb2e8f9f7 22827 #define SDH_INTEN_SDHOST1IEN_Pos (11) /*!< SDH INTSTS: SDHOST1IEN Position */
<> 144:ef7eb2e8f9f7 22828 #define SDH_INTEN_SDHOST1IEN_Msk (0x1ul << SDH_INTEN_SDHOST1IEN_Pos) /*!< SDH INTSTS: SDHOST1IEN Mask */
<> 144:ef7eb2e8f9f7 22829
<> 144:ef7eb2e8f9f7 22830 #define SDH_INTEN_RTOIEN_Pos (12) /*!< SDH INTEN: RTOIEN Position */
<> 144:ef7eb2e8f9f7 22831 #define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) /*!< SDH INTEN: RTOIEN Mask */
<> 144:ef7eb2e8f9f7 22832
<> 144:ef7eb2e8f9f7 22833 #define SDH_INTEN_DITOIEN_Pos (13) /*!< SDH INTEN: DITOIEN Position */
<> 144:ef7eb2e8f9f7 22834 #define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) /*!< SDH INTEN: DITOIEN Mask */
<> 144:ef7eb2e8f9f7 22835
<> 144:ef7eb2e8f9f7 22836 #define SDH_INTEN_WKIEN_Pos (14) /*!< SDH INTEN: WKIEN Position */
<> 144:ef7eb2e8f9f7 22837 #define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) /*!< SDH INTEN: WKIEN Mask */
<> 144:ef7eb2e8f9f7 22838
<> 144:ef7eb2e8f9f7 22839 #define SDH_INTEN_CDSRC0_Pos (30) /*!< SDH INTEN: CDSRC0 Position */
<> 144:ef7eb2e8f9f7 22840 #define SDH_INTEN_CDSRC0_Msk (0x1ul << SDH_INTEN_CDSRC0_Pos) /*!< SDH INTEN: CDSRC0 Mask */
<> 144:ef7eb2e8f9f7 22841
<> 144:ef7eb2e8f9f7 22842 #define SDH_INTEN_CDSRC1_Pos (31) /*!< SDH INTEN: CDSRC1 Position */
<> 144:ef7eb2e8f9f7 22843 #define SDH_INTEN_CDSRC1_Msk (0x1ul << SDH_INTEN_CDSRC1_Pos) /*!< SDH INTEN: CDSRC1 Mask */
<> 144:ef7eb2e8f9f7 22844
<> 144:ef7eb2e8f9f7 22845 #define SDH_INTSTS_BLKDIF_Pos (0) /*!< SDH INTSTS: BLKDIF Position */
<> 144:ef7eb2e8f9f7 22846 #define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) /*!< SDH INTSTS: BLKDIF Mask */
<> 144:ef7eb2e8f9f7 22847
<> 144:ef7eb2e8f9f7 22848 #define SDH_INTSTS_CRCIF_Pos (1) /*!< SDH INTSTS: CRCIF Position */
<> 144:ef7eb2e8f9f7 22849 #define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) /*!< SDH INTSTS: CRCIF Mask */
<> 144:ef7eb2e8f9f7 22850
<> 144:ef7eb2e8f9f7 22851 #define SDH_INTSTS_CRC7_Pos (2) /*!< SDH INTSTS: CRC7 Position */
<> 144:ef7eb2e8f9f7 22852 #define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) /*!< SDH INTSTS: CRC7 Mask */
<> 144:ef7eb2e8f9f7 22853
<> 144:ef7eb2e8f9f7 22854 #define SDH_INTSTS_CRC16_Pos (3) /*!< SDH INTSTS: CRC16 Position */
<> 144:ef7eb2e8f9f7 22855 #define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) /*!< SDH INTSTS: CRC16 Mask */
<> 144:ef7eb2e8f9f7 22856
<> 144:ef7eb2e8f9f7 22857 #define SDH_INTSTS_CRCSTS_Pos (4) /*!< SDH INTSTS: CRCSTS Position */
<> 144:ef7eb2e8f9f7 22858 #define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) /*!< SDH INTSTS: CRCSTS Mask */
<> 144:ef7eb2e8f9f7 22859
<> 144:ef7eb2e8f9f7 22860 #define SDH_INTSTS_DAT0STS_Pos (7) /*!< SDH INTSTS: DAT0STS Position */
<> 144:ef7eb2e8f9f7 22861 #define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) /*!< SDH INTSTS: DAT0STS Mask */
<> 144:ef7eb2e8f9f7 22862
<> 144:ef7eb2e8f9f7 22863 #define SDH_INTSTS_CDIF0_Pos (8) /*!< SDH INTSTS: CDIF0 Position */
<> 144:ef7eb2e8f9f7 22864 #define SDH_INTSTS_CDIF0_Msk (0x1ul << SDH_INTSTS_CDIF0_Pos) /*!< SDH INTSTS: CDIF0 Mask */
<> 144:ef7eb2e8f9f7 22865
<> 144:ef7eb2e8f9f7 22866 #define SDH_INTSTS_CDIF1_Pos (9) /*!< SDH INTSTS: CDIF1 Position */
<> 144:ef7eb2e8f9f7 22867 #define SDH_INTSTS_CDIF1_Msk (0x1ul << SDH_INTSTS_CDIF1_Pos) /*!< SDH INTSTS: CDIF1 Mask */
<> 144:ef7eb2e8f9f7 22868
<> 144:ef7eb2e8f9f7 22869 #define SDH_INTSTS_SDHOST0IF_Pos (10) /*!< SDH INTSTS: SDHOST0IF Position */
<> 144:ef7eb2e8f9f7 22870 #define SDH_INTSTS_SDHOST0IF_Msk (0x1ul << SDH_INTSTS_SDHOST0IF_Pos) /*!< SDH INTSTS: SDHOST0IF Mask */
<> 144:ef7eb2e8f9f7 22871
<> 144:ef7eb2e8f9f7 22872 #define SDH_INTSTS_SDHOST1IF_Pos (11) /*!< SDH INTSTS: SDHOST1IF Position */
<> 144:ef7eb2e8f9f7 22873 #define SDH_INTSTS_SDHOST1IF_Msk (0x1ul << SDH_INTSTS_SDHOST1IF_Pos) /*!< SDH INTSTS: SDHOST1IF Mask */
<> 144:ef7eb2e8f9f7 22874
<> 144:ef7eb2e8f9f7 22875 #define SDH_INTSTS_RTOIF_Pos (12) /*!< SDH INTSTS: RTOIF Position */
<> 144:ef7eb2e8f9f7 22876 #define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) /*!< SDH INTSTS: RTOIF Mask */
<> 144:ef7eb2e8f9f7 22877
<> 144:ef7eb2e8f9f7 22878 #define SDH_INTSTS_DINTOIF_Pos (13) /*!< SDH INTSTS: DINTOIF Position */
<> 144:ef7eb2e8f9f7 22879 #define SDH_INTSTS_DINTOIF_Msk (0x1ul << SDH_INTSTS_DINTOIF_Pos) /*!< SDH INTSTS: DINTOIF Mask */
<> 144:ef7eb2e8f9f7 22880
<> 144:ef7eb2e8f9f7 22881 #define SDH_INTSTS_CDSTS0_Pos (16) /*!< SDH INTSTS: CDSTS0 Position */
<> 144:ef7eb2e8f9f7 22882 #define SDH_INTSTS_CDSTS0_Msk (0x1ul << SDH_INTSTS_CDSTS0_Pos) /*!< SDH INTSTS: CDSTS0 Mask */
<> 144:ef7eb2e8f9f7 22883
<> 144:ef7eb2e8f9f7 22884 #define SDH_INTSTS_CDSTS1_Pos (17) /*!< SDH INTSTS: CDSTS1 Position */
<> 144:ef7eb2e8f9f7 22885 #define SDH_INTSTS_CDSTS1_Msk (0x1ul << SDH_INTSTS_CDSTS1_Pos) /*!< SDH INTSTS: CDSTS1 Mask */
<> 144:ef7eb2e8f9f7 22886
<> 144:ef7eb2e8f9f7 22887 #define SDH_INTSTS_DAT1STS_Pos (18) /*!< SDH INTSTS: DAT1STS Position */
<> 144:ef7eb2e8f9f7 22888 #define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) /*!< SDH INTSTS: DAT1STS Mask */
<> 144:ef7eb2e8f9f7 22889
<> 144:ef7eb2e8f9f7 22890 #define SDH_RESP0_RESPTK0_Pos (0) /*!< SDH RESP0: RESPTK0 Position */
<> 144:ef7eb2e8f9f7 22891 #define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) /*!< SDH RESP0: RESPTK0 Mask */
<> 144:ef7eb2e8f9f7 22892
<> 144:ef7eb2e8f9f7 22893 #define SDH_RESP1_RESPTK1_Pos (0) /*!< SDH RESP1: RESPTK1 Position */
<> 144:ef7eb2e8f9f7 22894 #define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) /*!< SDH RESP1: RESPTK1 Mask */
<> 144:ef7eb2e8f9f7 22895
<> 144:ef7eb2e8f9f7 22896 #define SDH_BLEN_BLKLEN_Pos (0) /*!< SDH BLEN: BLKLEN Position */
<> 144:ef7eb2e8f9f7 22897 #define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) /*!< SDH BLEN: BLKLEN Mask */
<> 144:ef7eb2e8f9f7 22898
<> 144:ef7eb2e8f9f7 22899 #define SDH_TOUT_TOUT_Pos (0) /*!< SDH TOUT: TOUT Position */
<> 144:ef7eb2e8f9f7 22900 #define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) /*!< SDH TOUT: TOUT Mask */
<> 144:ef7eb2e8f9f7 22901
<> 144:ef7eb2e8f9f7 22902 /**@}*/ /* SDH_CONST */
<> 144:ef7eb2e8f9f7 22903 /**@}*/ /* end of SDH register group */
<> 144:ef7eb2e8f9f7 22904
<> 144:ef7eb2e8f9f7 22905
<> 144:ef7eb2e8f9f7 22906 /*---------------------- Serial Peripheral Interface Controller -------------------------*/
<> 144:ef7eb2e8f9f7 22907 /**
<> 144:ef7eb2e8f9f7 22908 @addtogroup SPI Serial Peripheral Interface Controller(SPI)
<> 144:ef7eb2e8f9f7 22909 Memory Mapped Structure for SPI Controller
<> 144:ef7eb2e8f9f7 22910 @{ */
<> 144:ef7eb2e8f9f7 22911
<> 144:ef7eb2e8f9f7 22912 typedef struct {
<> 144:ef7eb2e8f9f7 22913
<> 144:ef7eb2e8f9f7 22914
<> 144:ef7eb2e8f9f7 22915 /**
<> 144:ef7eb2e8f9f7 22916 * CTL
<> 144:ef7eb2e8f9f7 22917 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22918 * Offset: 0x00 SPI Control Register
<> 144:ef7eb2e8f9f7 22919 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22920 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22921 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 22922 * |[0] |SPIEN |SPI Transfer Control Enable Control
<> 144:ef7eb2e8f9f7 22923 * | | |0 = Transfer control Disabled.
<> 144:ef7eb2e8f9f7 22924 * | | |1 = Transfer control Enabled.
<> 144:ef7eb2e8f9f7 22925 * | | |Note1: In Master mode, the transfer will start when there is data in the FIFO buffer after this is set to 1.
<> 144:ef7eb2e8f9f7 22926 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1.
<> 144:ef7eb2e8f9f7 22927 * | | |Note2: All configurations should be set before writing 1 to this SPIEN bit.
<> 144:ef7eb2e8f9f7 22928 * | | |(eg: TXNEG, RXNEG, DWIDTH, LSB, CLKPOL, and so on).
<> 144:ef7eb2e8f9f7 22929 * |[1] |RXNEG |Receive On Negative Edge
<> 144:ef7eb2e8f9f7 22930 * | | |0 = Received data input signal is latched on the rising edge of SPICLK.
<> 144:ef7eb2e8f9f7 22931 * | | |1 = Received data input signal is latched on the falling edge of SPICLK.
<> 144:ef7eb2e8f9f7 22932 * |[2] |TXNEG |Transmit On Negative Edge
<> 144:ef7eb2e8f9f7 22933 * | | |0 = Transmitted data output signal is changed on the rising edge of SPICLK.
<> 144:ef7eb2e8f9f7 22934 * | | |1 = Transmitted data output signal is changed on the falling edge of SPICLK.
<> 144:ef7eb2e8f9f7 22935 * |[3] |CLKPOL |Clock Polarity
<> 144:ef7eb2e8f9f7 22936 * | | |0 = SPICLK is idle low.
<> 144:ef7eb2e8f9f7 22937 * | | |1 = SPICLK is idle high.
<> 144:ef7eb2e8f9f7 22938 * |[4:7] |SUSPITV |Suspend Interval (Master Only)
<> 144:ef7eb2e8f9f7 22939 * | | |SUSPITV = 0x0 ... 0.5 SPICLK clock cycle.
<> 144:ef7eb2e8f9f7 22940 * | | |SUSPITV = 0x1 ... 1.5 SPICLK clock cycle.
<> 144:ef7eb2e8f9f7 22941 * | | |......
<> 144:ef7eb2e8f9f7 22942 * | | |SUSPITV = 0xE ... 14.5 SPICLK clock cycle.
<> 144:ef7eb2e8f9f7 22943 * | | |SUSPITV = 0xF ... 15.5 SPICLK clock cycle.
<> 144:ef7eb2e8f9f7 22944 * | | |Note: The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer.
<> 144:ef7eb2e8f9f7 22945 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word.
<> 144:ef7eb2e8f9f7 22946 * | | |The default value is 0x3.
<> 144:ef7eb2e8f9f7 22947 * | | |The period of the suspend interval is obtained according to the following equation.
<> 144:ef7eb2e8f9f7 22948 * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle
<> 144:ef7eb2e8f9f7 22949 * |[8:12] |DWIDTH |Data Transmit Bit Width
<> 144:ef7eb2e8f9f7 22950 * | | |This field specifies how many bits can be transmitted / received in one transaction.
<> 144:ef7eb2e8f9f7 22951 * | | |The minimum bit length is 8 bits and can up to 32 bits.
<> 144:ef7eb2e8f9f7 22952 * | | |DWIDTH = 0x08 ... 8 bits.
<> 144:ef7eb2e8f9f7 22953 * | | |DWIDTH = 0x09 ... 9 bits.
<> 144:ef7eb2e8f9f7 22954 * | | |......
<> 144:ef7eb2e8f9f7 22955 * | | |DWIDTH = 0x1F ... 31 bits.
<> 144:ef7eb2e8f9f7 22956 * | | |DWIDTH = 0x00 ... 32 bits.
<> 144:ef7eb2e8f9f7 22957 * |[13] |LSB |Send LSB First
<> 144:ef7eb2e8f9f7 22958 * | | |0 = MSB first.
<> 144:ef7eb2e8f9f7 22959 * | | |1 = LSB first.
<> 144:ef7eb2e8f9f7 22960 * | | |Note1: The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX).
<> 144:ef7eb2e8f9f7 22961 * | | |Note2: The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first.
<> 144:ef7eb2e8f9f7 22962 * |[16] |TWOBIT |2-Bit Mode Enable Control
<> 144:ef7eb2e8f9f7 22963 * | | |0 = 2-bit mode Disabled.
<> 144:ef7eb2e8f9f7 22964 * | | |1 = 2-bit mode Enabled.
<> 144:ef7eb2e8f9f7 22965 * | | |Note: When 2-bit mode is enabled, the first serial transmitted bit data is from the first FIFO buffer data, and the 2nd
<> 144:ef7eb2e8f9f7 22966 * | | |serial transmitted bit data is from the second FIFO buffer data.
<> 144:ef7eb2e8f9f7 22967 * | | |As the same as transmitted function, the first received bit data is stored into the first FIFO buffer and the 2nd received bit data is stored into the second FIFO buffer at the same time.
<> 144:ef7eb2e8f9f7 22968 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Control
<> 144:ef7eb2e8f9f7 22969 * | | |0 = SPI unit transfer interrupt Disabled.
<> 144:ef7eb2e8f9f7 22970 * | | |1 = SPI unit transfer interrupt Enabled.
<> 144:ef7eb2e8f9f7 22971 * |[18] |SLAVE |Slave Mode Enable Control
<> 144:ef7eb2e8f9f7 22972 * | | |0 = Master mode.
<> 144:ef7eb2e8f9f7 22973 * | | |1 = Slave mode.
<> 144:ef7eb2e8f9f7 22974 * |[19] |REORDER |Byte Reorder Function Enable Control
<> 144:ef7eb2e8f9f7 22975 * | | |0 = Byte reorder function Disabled.
<> 144:ef7eb2e8f9f7 22976 * | | |1 = Byte reorder function Enabled.
<> 144:ef7eb2e8f9f7 22977 * | | |Note1: Byte reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits.
<> 144:ef7eb2e8f9f7 22978 * | | |Note2: The byte reorder function is not supported when the Quad or Dual I/O mode is enabled.
<> 144:ef7eb2e8f9f7 22979 * | | |Note3: A byte suspend interval will be inserted among each byte.
<> 144:ef7eb2e8f9f7 22980 * | | |The period of the byte suspend interval depends on the setting of SUSPITV.
<> 144:ef7eb2e8f9f7 22981 * |[20] |QDIODIR |Quad Or Dual I/O Mode Direction Control
<> 144:ef7eb2e8f9f7 22982 * | | |0 = Quad or Dual Input mode.
<> 144:ef7eb2e8f9f7 22983 * | | |1 = Quad or Dual Output mode.
<> 144:ef7eb2e8f9f7 22984 * |[21] |DUALIOEN |Dual I/O Mode Enable Control
<> 144:ef7eb2e8f9f7 22985 * | | |0 = Dual I/O mode Disabled.
<> 144:ef7eb2e8f9f7 22986 * | | |1 = Dual I/O mode Enabled.
<> 144:ef7eb2e8f9f7 22987 * |[22] |QUADIOEN |Quad I/O Mode Enable Control
<> 144:ef7eb2e8f9f7 22988 * | | |0 = Quad I/O mode Disabled.
<> 144:ef7eb2e8f9f7 22989 * | | |1 = Quad I/O mode Enabled.
<> 144:ef7eb2e8f9f7 22990 */
<> 144:ef7eb2e8f9f7 22991 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 22992
<> 144:ef7eb2e8f9f7 22993 /**
<> 144:ef7eb2e8f9f7 22994 * CLKDIV
<> 144:ef7eb2e8f9f7 22995 * ===================================================================================================
<> 144:ef7eb2e8f9f7 22996 * Offset: 0x04 SPI Clock Divider Register
<> 144:ef7eb2e8f9f7 22997 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 22998 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 22999 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23000 * |[0:7] |DIVIDER |Clock Divider Register
<> 144:ef7eb2e8f9f7 23001 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI master.
<> 144:ef7eb2e8f9f7 23002 * | | |The frequency is obtained according to the following equation.
<> 144:ef7eb2e8f9f7 23003 * | | |Note1: is the peripheral clock source, which is defined in the clock control, CLK_SEL1 register.
<> 144:ef7eb2e8f9f7 23004 * | | |Note2: is the peripheral clock which is used to drive the SPI logic unit.
<> 144:ef7eb2e8f9f7 23005 */
<> 144:ef7eb2e8f9f7 23006 __IO uint32_t CLKDIV;
<> 144:ef7eb2e8f9f7 23007
<> 144:ef7eb2e8f9f7 23008 /**
<> 144:ef7eb2e8f9f7 23009 * SSCTL
<> 144:ef7eb2e8f9f7 23010 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23011 * Offset: 0x08 SPI Slave Select Control Register
<> 144:ef7eb2e8f9f7 23012 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23013 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23014 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23015 * |[0:1] |SS |Slave Select Control (Master Only)
<> 144:ef7eb2e8f9f7 23016 * | | |If AUTOSS bit is cleared to 0,
<> 144:ef7eb2e8f9f7 23017 * | | |0 = Set the SPI_SS line to inactive state.
<> 144:ef7eb2e8f9f7 23018 * | | |1 = Set the proper SPI_SS line to active state.
<> 144:ef7eb2e8f9f7 23019 * | | |If AUTOSS bit is set to 1,
<> 144:ef7eb2e8f9f7 23020 * | | |0 = Keep the SPI_SS line at inactive state.
<> 144:ef7eb2e8f9f7 23021 * | | |1 = Select the SPI_SS line to be automatically driven to active state for the duration of transmission/reception, and will be driven to inactive state for the rest of the time.
<> 144:ef7eb2e8f9f7 23022 * | | |The active state of SPI_SS is specified in SSACTPOL bit.
<> 144:ef7eb2e8f9f7 23023 * | | |Note: SPI_SS0 is defined as the slave select input in Slave mode.
<> 144:ef7eb2e8f9f7 23024 * |[2] |SSACTPOL |Slave Select Active Level
<> 144:ef7eb2e8f9f7 23025 * | | |0 = The slave select signal SPI_SS0/1 is active on low-level.
<> 144:ef7eb2e8f9f7 23026 * | | |1 = The slave select signal SPI_SS0/1 is active on high-level.
<> 144:ef7eb2e8f9f7 23027 * | | |Note: This bit defines the active status of slave select signal (SPI_SS0/1).
<> 144:ef7eb2e8f9f7 23028 * |[3] |AUTOSS |Automatic Slave Select Function Enable Control (Master Only)
<> 144:ef7eb2e8f9f7 23029 * | | |0 = Automatic slave select function Disabled.
<> 144:ef7eb2e8f9f7 23030 * | | |1 = Automatic slave select function Enabled.
<> 144:ef7eb2e8f9f7 23031 * | | |Note1: If this bit is cleared, slave select signals will be asserted/de-asserted by setting /clearing the corresponding bits of SPI_SSCTL[1:0].
<> 144:ef7eb2e8f9f7 23032 * | | |Note2: If this bit is set, SPI_SS0/1 signals will be generated automatically.
<> 144:ef7eb2e8f9f7 23033 * | | |It means that device/slave select signal, which is set in SPI_SSCTL[1:0], will be asserted by the SPI controller when transmit/receive is started, and will be de-asserted after each transmit/receive is finished.
<> 144:ef7eb2e8f9f7 23034 * |[4] |SLV3WIRE |Slave 3-Wire Mode Enable Control
<> 144:ef7eb2e8f9f7 23035 * | | |0 = 4-wire bi-direction interface.
<> 144:ef7eb2e8f9f7 23036 * | | |1 = 3-wire bi-direction interface.
<> 144:ef7eb2e8f9f7 23037 * | | |Note: This is used to ignore the slave select signal in Slave mode.
<> 144:ef7eb2e8f9f7 23038 * | | |The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI.
<> 144:ef7eb2e8f9f7 23039 * |[5] |SLVTOIEN |Slave Mode Time-Out Interrupt Enable Control
<> 144:ef7eb2e8f9f7 23040 * | | |0 = Slave mode time-out interrupt Disabled.
<> 144:ef7eb2e8f9f7 23041 * | | |1 = Slave mode time-out interrupt Enabled.
<> 144:ef7eb2e8f9f7 23042 * |[6] |SLVTORST |Slave Mode Time-Out FIFO Clear
<> 144:ef7eb2e8f9f7 23043 * | | |0 = Time out FIFO clear Disabled.
<> 144:ef7eb2e8f9f7 23044 * | | |1 = Time out FIFO clear Enabled.
<> 144:ef7eb2e8f9f7 23045 * | | |Note: Both the FIFO clear function, TX_CLK and RXRST, active automatically when there is slave mode time-out event.
<> 144:ef7eb2e8f9f7 23046 * |[8] |SLVBEIEN |Slave Mode Error 0 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 23047 * | | |0 = Slave mode error 0 interrupt Disabled.
<> 144:ef7eb2e8f9f7 23048 * | | |1 = Slave mode error 0 interrupt Enabled.
<> 144:ef7eb2e8f9f7 23049 * |[9] |SLVURIEN |Slave Mode Error 1 Interrupt Enable Control
<> 144:ef7eb2e8f9f7 23050 * | | |0 = Slave mode error 1 interrupt Disabled.
<> 144:ef7eb2e8f9f7 23051 * | | |1 = Slave mode error 1 interrupt Enabled.
<> 144:ef7eb2e8f9f7 23052 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Control
<> 144:ef7eb2e8f9f7 23053 * | | |0 = Slave select active interrupt Disabled.
<> 144:ef7eb2e8f9f7 23054 * | | |1 = Slave select active interrupt Enabled.
<> 144:ef7eb2e8f9f7 23055 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Control
<> 144:ef7eb2e8f9f7 23056 * | | |0 = Slave select inactive interrupt Disabled.
<> 144:ef7eb2e8f9f7 23057 * | | |1 = Slave select inactive interrupt Enabled.
<> 144:ef7eb2e8f9f7 23058 * |[16:31] |SLVTOCNT |Slave Mode Time-Out Period
<> 144:ef7eb2e8f9f7 23059 * | | |0 = Slave time out function disabled.
<> 144:ef7eb2e8f9f7 23060 * | | |Others = Slave time out period.
<> 144:ef7eb2e8f9f7 23061 * | | |Note: In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active.
<> 144:ef7eb2e8f9f7 23062 * | | |The clock source of the time-out counter is Slave peripheral clock.
<> 144:ef7eb2e8f9f7 23063 * | | |If the value is 0, it indicates the slave mode time-out function is disabled.
<> 144:ef7eb2e8f9f7 23064 */
<> 144:ef7eb2e8f9f7 23065 __IO uint32_t SSCTL;
<> 144:ef7eb2e8f9f7 23066
<> 144:ef7eb2e8f9f7 23067 /**
<> 144:ef7eb2e8f9f7 23068 * PDMACTL
<> 144:ef7eb2e8f9f7 23069 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23070 * Offset: 0x0C SPI PDMA Control Register
<> 144:ef7eb2e8f9f7 23071 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23072 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23073 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23074 * |[0] |TXPDMAEN |Transmit DMA Enable Control
<> 144:ef7eb2e8f9f7 23075 * | | |0 = Transmit PDMA Disabled.
<> 144:ef7eb2e8f9f7 23076 * | | |1 = Transmit PDMA Enabled.
<> 144:ef7eb2e8f9f7 23077 * | | |Note: Setting this bit to 1 will start the transmit PDMA process.
<> 144:ef7eb2e8f9f7 23078 * | | |SPI controller will issue request to PDMA controller automatically.
<> 144:ef7eb2e8f9f7 23079 * | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
<> 144:ef7eb2e8f9f7 23080 * |[1] |RXPDMAEN |Receive PDMA Enable Control
<> 144:ef7eb2e8f9f7 23081 * | | |0 = Receive PDMA Disabled.
<> 144:ef7eb2e8f9f7 23082 * | | |1 = Receive PDMA Enabled.
<> 144:ef7eb2e8f9f7 23083 * | | |Note: Setting this bit to 1 will start the receive PDMA process.
<> 144:ef7eb2e8f9f7 23084 * | | |The SPI controller will issue request to PDMA controller automatically when the SPI receive buffer is not empty.
<> 144:ef7eb2e8f9f7 23085 * | | |This bit will be cleared to 0 by hardware automatically after PDMA transfer is done.
<> 144:ef7eb2e8f9f7 23086 * |[2] |PDMARST |PDMA Reset
<> 144:ef7eb2e8f9f7 23087 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 23088 * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be cleared to 0 automatically.
<> 144:ef7eb2e8f9f7 23089 */
<> 144:ef7eb2e8f9f7 23090 __IO uint32_t PDMACTL;
<> 144:ef7eb2e8f9f7 23091
<> 144:ef7eb2e8f9f7 23092 /**
<> 144:ef7eb2e8f9f7 23093 * FIFOCTL
<> 144:ef7eb2e8f9f7 23094 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23095 * Offset: 0x10 SPI FIFO Control Register
<> 144:ef7eb2e8f9f7 23096 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23097 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23098 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23099 * |[0] |RXRST |Clear Receive FIFO Buffer
<> 144:ef7eb2e8f9f7 23100 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 23101 * | | |1 = Clear receive FIFO buffer.
<> 144:ef7eb2e8f9f7 23102 * | | |Note1: If there is slave receive time-out event, the RXRST will be set 1 when the SLVTORST, SPI_SSCTL[6], is enabled.
<> 144:ef7eb2e8f9f7 23103 * | | |Note2: The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1.
<> 144:ef7eb2e8f9f7 23104 * | | |This bit will be cleared to 0 by hardware about 3 system clocks + 3 peripheral clock after it is set to 1.
<> 144:ef7eb2e8f9f7 23105 * |[1] |TXRST |Clear Transmit FIFO Buffer
<> 144:ef7eb2e8f9f7 23106 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 23107 * | | |1 = Clear transmit FIFO buffer.
<> 144:ef7eb2e8f9f7 23108 * | | |Note1: If there is slave receive time-out event, the TXRST will be set 1 when the SLVTORST, SPI_SSCTL[6], is enabled.
<> 144:ef7eb2e8f9f7 23109 * | | |Note2: The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1.
<> 144:ef7eb2e8f9f7 23110 * | | |This bit will be cleared to 0 by hardware about 3 system clocks + 3 peripheral clock after it is set to 1.
<> 144:ef7eb2e8f9f7 23111 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Control
<> 144:ef7eb2e8f9f7 23112 * | | |0 = RX FIFO threshold interrupt Disabled.
<> 144:ef7eb2e8f9f7 23113 * | | |1 = RX FIFO threshold interrupt Enabled.
<> 144:ef7eb2e8f9f7 23114 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Control
<> 144:ef7eb2e8f9f7 23115 * | | |0 = TX FIFO threshold interrupt Disabled.
<> 144:ef7eb2e8f9f7 23116 * | | |1 = TX FIFO threshold interrupt Enabled.
<> 144:ef7eb2e8f9f7 23117 * |[4] |RXTOIEN |Slave Receive Time-Out Interrupt Enable Control (Slave Only)
<> 144:ef7eb2e8f9f7 23118 * | | |0 = Receive time-out interrupt Disabled.
<> 144:ef7eb2e8f9f7 23119 * | | |1 = Receive time-out interrupt Enabled.
<> 144:ef7eb2e8f9f7 23120 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Control
<> 144:ef7eb2e8f9f7 23121 * | | |0 = Receive FIFO overrun interrupt Disabled.
<> 144:ef7eb2e8f9f7 23122 * | | |1 = Receive FIFO overrun interrupt Enabled.
<> 144:ef7eb2e8f9f7 23123 * |[6] |TXUFPOL |Transmit Under-Run Data Out (Slave Only)
<> 144:ef7eb2e8f9f7 23124 * | | |0 = The SPI data bus is keep low if there is transmit under-run event.
<> 144:ef7eb2e8f9f7 23125 * | | |1 = The SPI data bus is keep high if there is transmit under-run event.
<> 144:ef7eb2e8f9f7 23126 * | | |Note1: The under run event is activated after the bus clock input and the hardware synchronous, so that the first 1~3 bit (depending on the relation between system clock and the peripheral clock) data out will be the last transaction data.
<> 144:ef7eb2e8f9f7 23127 * | | |Note2: If the frequency of system clock approach to peripheral clock, they may need 3-bit time to report the transmit under-run event.
<> 144:ef7eb2e8f9f7 23128 * |[7] |TXUFIEN |Transmit Under Run Interrupt Enable Control (Slave Only)
<> 144:ef7eb2e8f9f7 23129 * | | |0 = Transmit FIFO under-run interrupt Disabled.
<> 144:ef7eb2e8f9f7 23130 * | | |1 = Transmit FIFO under-run interrupt Enabled.
<> 144:ef7eb2e8f9f7 23131 * |[24:26] |RXTH |Receive FIFO Threshold
<> 144:ef7eb2e8f9f7 23132 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0.
<> 144:ef7eb2e8f9f7 23133 * |[28:30] |TXTH |Transmit FIFO Threshold
<> 144:ef7eb2e8f9f7 23134 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0.
<> 144:ef7eb2e8f9f7 23135 */
<> 144:ef7eb2e8f9f7 23136 __IO uint32_t FIFOCTL;
<> 144:ef7eb2e8f9f7 23137
<> 144:ef7eb2e8f9f7 23138 /**
<> 144:ef7eb2e8f9f7 23139 * STATUS
<> 144:ef7eb2e8f9f7 23140 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23141 * Offset: 0x14 SPI Status Register
<> 144:ef7eb2e8f9f7 23142 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23143 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23144 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23145 * |[0] |BUSY |Busy Status (Read Only)
<> 144:ef7eb2e8f9f7 23146 * | | |0 = SPI controller is in Idle state.
<> 144:ef7eb2e8f9f7 23147 * | | |1 = SPI controller is in busy state.
<> 144:ef7eb2e8f9f7 23148 * | | |The following listing are the bus busy conditions:
<> 144:ef7eb2e8f9f7 23149 * | | |*. SPIEN = 1 and the TXEMPTY = 0.
<> 144:ef7eb2e8f9f7 23150 * | | |*. For SPI Master, the TXEMPTY = 1 but the current transaction is not finished yet.
<> 144:ef7eb2e8f9f7 23151 * | | |*. For SPI Slave receive mode, the SPIEN = 1 and there is serial clock input into the SPI core logic when slave select is active.
<> 144:ef7eb2e8f9f7 23152 * | | |*. For SPI Slave transmit mode, the SPIEN = 1 and the transmit buffer is not empty in SPI core logic even if the slave select is inactive.
<> 144:ef7eb2e8f9f7 23153 * |[1] |UNITIF |Unit Transfer Interrupt Status
<> 144:ef7eb2e8f9f7 23154 * | | |0 = No transaction has been finished since this bit was cleared to 0.
<> 144:ef7eb2e8f9f7 23155 * | | |1 = SPI controller has finished one unit transfer.
<> 144:ef7eb2e8f9f7 23156 * | | |Note: This bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23157 * |[2] |SSACTIF |Slave Select Active Interrupt Status
<> 144:ef7eb2e8f9f7 23158 * | | |0 = Slave select active interrupt is clear or not occur.
<> 144:ef7eb2e8f9f7 23159 * | | |1 = Slave select active interrupt event occurred.
<> 144:ef7eb2e8f9f7 23160 * | | |Note: This bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23161 * |[3] |SSINAIF |Slave Select Inactive Interrupt Status
<> 144:ef7eb2e8f9f7 23162 * | | |0 = Slave select inactive interrupt is clear or not occur.
<> 144:ef7eb2e8f9f7 23163 * | | |1 = Slave select inactive interrupt event occurred.
<> 144:ef7eb2e8f9f7 23164 * | | |Note: This bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23165 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only)
<> 144:ef7eb2e8f9f7 23166 * | | |0 = Indicates the slave select line bus status is 0.
<> 144:ef7eb2e8f9f7 23167 * | | |1 = Indicates the slave select line bus status is 1.
<> 144:ef7eb2e8f9f7 23168 * | | |Note: If SSACTPOL, SPI_SSCTL[2], is set 0, and the SSLINE is 1, the SPI slave select is in inactive status.
<> 144:ef7eb2e8f9f7 23169 * |[5] |SLVTOIF |Slave Time-Out Interrupt Status
<> 144:ef7eb2e8f9f7 23170 * | | |0 = Slave time-out is not active.
<> 144:ef7eb2e8f9f7 23171 * | | |1 = Slave time-out is active.
<> 144:ef7eb2e8f9f7 23172 * | | |Note1: If the DWIDTH is set 16, one transaction is equal 16 bits bus clock period.
<> 144:ef7eb2e8f9f7 23173 * | | |This bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23174 * | | |Note2: When the Slave Select is active and the value of SLVTOCNT is not 0 and the busclock input, the slave time-out counter in SPI controller logic will be start.
<> 144:ef7eb2e8f9f7 23175 * | | |When the value of time-out counter greater or equal than the value of SLVTOCNT, SPI_SSCTL[31:16], during before one transaction done, the slave time-out interrupt event will active.
<> 144:ef7eb2e8f9f7 23176 * |[6] |SLVBEIF |Slave Mode Error 0 Interrupt Status
<> 144:ef7eb2e8f9f7 23177 * | | |0 = No Slave mode error 0 event.
<> 144:ef7eb2e8f9f7 23178 * | | |1 = Slave mode error 0 occurs.
<> 144:ef7eb2e8f9f7 23179 * | | |Note1: If the slave select active but there is no any bus clock input, the SLVER0_INTSTS also active when the slave select goes to inactive state.
<> 144:ef7eb2e8f9f7 23180 * | | |This bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23181 * | | |Note2: In Slave mode, there is bit counter mismatch with DWIDTH when the slave select line goes to inactive state.
<> 144:ef7eb2e8f9f7 23182 * |[7] |SLVURIF |Slave Mode Error 1 Interrupt Status
<> 144:ef7eb2e8f9f7 23183 * | | |0 = No Slave mode error 1 event.
<> 144:ef7eb2e8f9f7 23184 * | | |1 = Slave mode error 1 occurs.
<> 144:ef7eb2e8f9f7 23185 * | | |Note: In Slave mode, transmit under-run occurs when the slave select line goes to inactive state.
<> 144:ef7eb2e8f9f7 23186 * | | |This bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23187 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
<> 144:ef7eb2e8f9f7 23188 * | | |0 = Receive FIFO buffer is not empty.
<> 144:ef7eb2e8f9f7 23189 * | | |1 = Receive FIFO buffer is empty.
<> 144:ef7eb2e8f9f7 23190 * |[9] |RXFULL |Receive FIFO Buffer Empty Indicator (Read Only)
<> 144:ef7eb2e8f9f7 23191 * | | |0 = Receive FIFO buffer is not empty.
<> 144:ef7eb2e8f9f7 23192 * | | |1 = Receive FIFO buffer is empty.
<> 144:ef7eb2e8f9f7 23193 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Status (Read Only)
<> 144:ef7eb2e8f9f7 23194 * | | |0 = The valid data count within the Rx FIFO buffer is smaller than or equal to the setting value of RXTH.
<> 144:ef7eb2e8f9f7 23195 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH.
<> 144:ef7eb2e8f9f7 23196 * | | |Note: If RX_INTEN = 1 and RX_INTSTS = 1, the SPI controller will generate a SPI interrupt request.
<> 144:ef7eb2e8f9f7 23197 * |[11] |RXOVIF |Receive FIFO Overrun Status
<> 144:ef7eb2e8f9f7 23198 * | | |0 = No FIFO over-run event.
<> 144:ef7eb2e8f9f7 23199 * | | |1 = FIFO over-run event occurred.
<> 144:ef7eb2e8f9f7 23200 * | | |Note: When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1.
<> 144:ef7eb2e8f9f7 23201 * | | |This bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23202 * |[12] |RXTOIF |Receive Time-Out Interrupt Status
<> 144:ef7eb2e8f9f7 23203 * | | |0 = No receive FIFO time-out event.
<> 144:ef7eb2e8f9f7 23204 * | | |1 = FIFO time-out event occurred.
<> 144:ef7eb2e8f9f7 23205 * | | |Note: Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI clock period in Master mode or over 576 peripheral clock period in Slave mode.
<> 144:ef7eb2e8f9f7 23206 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically.
<> 144:ef7eb2e8f9f7 23207 * | | |This bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23208 * |[15] |SPIENSTS |SPI Enable Bit Status (Read Only)
<> 144:ef7eb2e8f9f7 23209 * | | |0 = Indicates the transmit control bit is disabled.
<> 144:ef7eb2e8f9f7 23210 * | | |1 = Indicates the transfer control bit is active.
<> 144:ef7eb2e8f9f7 23211 * | | |Note: The clock source of SPI controller logic is peripheral clock, it is asynchronous with the system clock.
<> 144:ef7eb2e8f9f7 23212 * | | |In order to make sure the function is disabled in SPI controller logic, this bit indicates the real status of SPIEN in SPI controller logic for user.
<> 144:ef7eb2e8f9f7 23213 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
<> 144:ef7eb2e8f9f7 23214 * | | |0 = Transmit FIFO buffer is not empty.
<> 144:ef7eb2e8f9f7 23215 * | | |1 = Transmit FIFO buffer is empty.
<> 144:ef7eb2e8f9f7 23216 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
<> 144:ef7eb2e8f9f7 23217 * | | |0 = Transmit FIFO buffer is not full.
<> 144:ef7eb2e8f9f7 23218 * | | |1 = Transmit FIFO buffer is full.
<> 144:ef7eb2e8f9f7 23219 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Status (Read Only)
<> 144:ef7eb2e8f9f7 23220 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH.
<> 144:ef7eb2e8f9f7 23221 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH.
<> 144:ef7eb2e8f9f7 23222 * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI controller will generate a SPI interrupt request.
<> 144:ef7eb2e8f9f7 23223 * |[19] |TXUFIF |Transmit FIFO Under-Run Interrupt Status
<> 144:ef7eb2e8f9f7 23224 * | | |0 =No under-run interrupt event.
<> 144:ef7eb2e8f9f7 23225 * | | |1 = Under-run interrupt occurred.
<> 144:ef7eb2e8f9f7 23226 * | | |Note: When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input , the output data depends on the setting of SLVUDFPOL and this bit will be set to 1 and this bit will be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 23227 * |[23] |TXRXRST |FIFO CLR Status (Read Only)
<> 144:ef7eb2e8f9f7 23228 * | | |0 = Done the FIFO buffer clear function of TXRST or RXRST.
<> 144:ef7eb2e8f9f7 23229 * | | |1 = Doing the FIFO buffer clear function of TXRST or RXRST.
<> 144:ef7eb2e8f9f7 23230 * | | |Note: Both the TXRST, RXRST, need 3 system clock + 3 peripheral clock , the status of this bit support the user to monitor the clear function is doing or done.
<> 144:ef7eb2e8f9f7 23231 * |[24:27] |RXCNT |Receive FIFO Data Count (Read Only)
<> 144:ef7eb2e8f9f7 23232 * | | |This bit field indicates the valid data count of receive FIFO buffer.
<> 144:ef7eb2e8f9f7 23233 * |[28:31] |TXCNT |Transmit FIFO Data Count (Read Only)
<> 144:ef7eb2e8f9f7 23234 * | | |This bit field indicates the valid data count of transmit FIFO buffer.
<> 144:ef7eb2e8f9f7 23235 */
<> 144:ef7eb2e8f9f7 23236 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 23237 uint32_t RESERVE0[2];
<> 144:ef7eb2e8f9f7 23238
<> 144:ef7eb2e8f9f7 23239
<> 144:ef7eb2e8f9f7 23240 /**
<> 144:ef7eb2e8f9f7 23241 * TX
<> 144:ef7eb2e8f9f7 23242 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23243 * Offset: 0x20 SPI Data Transmit Register
<> 144:ef7eb2e8f9f7 23244 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23245 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23246 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23247 * |[0:31] |TX |Data Transmit Bits
<> 144:ef7eb2e8f9f7 23248 * | | |The data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer.
<> 144:ef7eb2e8f9f7 23249 * | | |The number of valid bits depends on the setting of transmit bit width field of the SPI_CTL register.
<> 144:ef7eb2e8f9f7 23250 * | | |In Master mode, the serial data in SPI bus output need 5 module clock cycle when the data transmit registers pass through the transmitted data into the 8-level transmit FIFO buffer.
<> 144:ef7eb2e8f9f7 23251 * | | |For example, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted.
<> 144:ef7eb2e8f9f7 23252 * | | |If DWIDTH is set to 0x00, the SPI controller will perform a 32-bit transfer.
<> 144:ef7eb2e8f9f7 23253 */
<> 144:ef7eb2e8f9f7 23254 __O uint32_t TX;
<> 144:ef7eb2e8f9f7 23255 uint32_t RESERVE1[3];
<> 144:ef7eb2e8f9f7 23256
<> 144:ef7eb2e8f9f7 23257
<> 144:ef7eb2e8f9f7 23258 /**
<> 144:ef7eb2e8f9f7 23259 * RX
<> 144:ef7eb2e8f9f7 23260 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23261 * Offset: 0x30 SPI Data Receive Register
<> 144:ef7eb2e8f9f7 23262 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23263 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23264 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23265 * |[0:31] |RX |Data Receive Bits
<> 144:ef7eb2e8f9f7 23266 * | | |There is 8-level FIFO buffer in this controller.
<> 144:ef7eb2e8f9f7 23267 * | | |The data receive register holds the earliest datum received from SPI data input pin.
<> 144:ef7eb2e8f9f7 23268 * | | |If the RXEMPTY bit, SPI_STATUS[8], is not set to 1, the receive FIFO buffer can be accessed through software by reading this register.
<> 144:ef7eb2e8f9f7 23269 * | | |This is a read only register.
<> 144:ef7eb2e8f9f7 23270 */
<> 144:ef7eb2e8f9f7 23271 __I uint32_t RX;
<> 144:ef7eb2e8f9f7 23272
<> 144:ef7eb2e8f9f7 23273 } SPI_T;
<> 144:ef7eb2e8f9f7 23274
<> 144:ef7eb2e8f9f7 23275 /**
<> 144:ef7eb2e8f9f7 23276 @addtogroup SPI_CONST SPI Bit Field Definition
<> 144:ef7eb2e8f9f7 23277 Constant Definitions for SPI Controller
<> 144:ef7eb2e8f9f7 23278 @{ */
<> 144:ef7eb2e8f9f7 23279
<> 144:ef7eb2e8f9f7 23280 #define SPI_CTL_SPIEN_Pos (0) /*!< SPI CTL: SPIEN Position */
<> 144:ef7eb2e8f9f7 23281 #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI CTL: SPIEN Mask */
<> 144:ef7eb2e8f9f7 23282
<> 144:ef7eb2e8f9f7 23283 #define SPI_CTL_RXNEG_Pos (1) /*!< SPI CTL: RXNEG Position */
<> 144:ef7eb2e8f9f7 23284 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI CTL: RXNEG Mask */
<> 144:ef7eb2e8f9f7 23285
<> 144:ef7eb2e8f9f7 23286 #define SPI_CTL_TXNEG_Pos (2) /*!< SPI CTL: TXNEG Position */
<> 144:ef7eb2e8f9f7 23287 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI CTL: TXNEG Mask */
<> 144:ef7eb2e8f9f7 23288
<> 144:ef7eb2e8f9f7 23289 #define SPI_CTL_CLKPOL_Pos (3) /*!< SPI CTL: CLKPOL Position */
<> 144:ef7eb2e8f9f7 23290 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI CTL: CLKPOL Mask */
<> 144:ef7eb2e8f9f7 23291
<> 144:ef7eb2e8f9f7 23292 #define SPI_CTL_SUSPITV_Pos (4) /*!< SPI CTL: SUSPITV Position */
<> 144:ef7eb2e8f9f7 23293 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI CTL: SUSPITV Mask */
<> 144:ef7eb2e8f9f7 23294
<> 144:ef7eb2e8f9f7 23295 #define SPI_CTL_DWIDTH_Pos (8) /*!< SPI CTL: DWIDTH Position */
<> 144:ef7eb2e8f9f7 23296 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI CTL: DWIDTH Mask */
<> 144:ef7eb2e8f9f7 23297
<> 144:ef7eb2e8f9f7 23298 #define SPI_CTL_LSB_Pos (13) /*!< SPI CTL: LSB Position */
<> 144:ef7eb2e8f9f7 23299 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI CTL: LSB Mask */
<> 144:ef7eb2e8f9f7 23300
<> 144:ef7eb2e8f9f7 23301 #define SPI_CTL_TWOBIT_Pos (16) /*!< SPI CTL: TWOBIT Position */
<> 144:ef7eb2e8f9f7 23302 #define SPI_CTL_TWOBIT_Msk (0x1ul << SPI_CTL_TWOBIT_Pos) /*!< SPI CTL: TWOBIT Mask */
<> 144:ef7eb2e8f9f7 23303
<> 144:ef7eb2e8f9f7 23304 #define SPI_CTL_UNITIEN_Pos (17) /*!< SPI CTL: UNITIEN Position */
<> 144:ef7eb2e8f9f7 23305 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI CTL: UNITIEN Mask */
<> 144:ef7eb2e8f9f7 23306
<> 144:ef7eb2e8f9f7 23307 #define SPI_CTL_SLAVE_Pos (18) /*!< SPI CTL: SLAVE Position */
<> 144:ef7eb2e8f9f7 23308 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI CTL: SLAVE Mask */
<> 144:ef7eb2e8f9f7 23309
<> 144:ef7eb2e8f9f7 23310 #define SPI_CTL_REORDER_Pos (19) /*!< SPI CTL: REORDER Position */
<> 144:ef7eb2e8f9f7 23311 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI CTL: REORDER Mask */
<> 144:ef7eb2e8f9f7 23312
<> 144:ef7eb2e8f9f7 23313 #define SPI_CTL_QDIODIR_Pos (20) /*!< SPI CTL: QDIODIR Position */
<> 144:ef7eb2e8f9f7 23314 #define SPI_CTL_QDIODIR_Msk (0x1ul << SPI_CTL_QDIODIR_Pos) /*!< SPI CTL: QDIODIR Mask */
<> 144:ef7eb2e8f9f7 23315
<> 144:ef7eb2e8f9f7 23316 #define SPI_CTL_DUALIOEN_Pos (21) /*!< SPI CTL: DUALIOEN Position */
<> 144:ef7eb2e8f9f7 23317 #define SPI_CTL_DUALIOEN_Msk (0x1ul << SPI_CTL_DUALIOEN_Pos) /*!< SPI CTL: DUALIOEN Mask */
<> 144:ef7eb2e8f9f7 23318
<> 144:ef7eb2e8f9f7 23319 #define SPI_CTL_QUADIOEN_Pos (22) /*!< SPI CTL: QUADIOEN Position */
<> 144:ef7eb2e8f9f7 23320 #define SPI_CTL_QUADIOEN_Msk (0x1ul << SPI_CTL_QUADIOEN_Pos) /*!< SPI CTL: QUADIOEN Mask */
<> 144:ef7eb2e8f9f7 23321
<> 144:ef7eb2e8f9f7 23322 #define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI CLKDIV: DIVIDER Position */
<> 144:ef7eb2e8f9f7 23323 #define SPI_CLKDIV_DIVIDER_Msk (0xfful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI CLKDIV: DIVIDER Mask */
<> 144:ef7eb2e8f9f7 23324
<> 144:ef7eb2e8f9f7 23325 #define SPI_SSCTL_SS_Pos (0) /*!< SPI SSCTL: SS Position */
<> 144:ef7eb2e8f9f7 23326 #define SPI_SSCTL_SS_Msk (0x3ul << SPI_SSCTL_SS_Pos) /*!< SPI SSCTL: SS Mask */
<> 144:ef7eb2e8f9f7 23327
<> 144:ef7eb2e8f9f7 23328 #define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI SSCTL: SSACTPOL Position */
<> 144:ef7eb2e8f9f7 23329 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI SSCTL: SSACTPOL Mask */
<> 144:ef7eb2e8f9f7 23330
<> 144:ef7eb2e8f9f7 23331 #define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI SSCTL: AUTOSS Position */
<> 144:ef7eb2e8f9f7 23332 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI SSCTL: AUTOSS Mask */
<> 144:ef7eb2e8f9f7 23333
<> 144:ef7eb2e8f9f7 23334 #define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI SSCTL: SLV3WIRE Position */
<> 144:ef7eb2e8f9f7 23335 #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI SSCTL: SLV3WIRE Mask */
<> 144:ef7eb2e8f9f7 23336
<> 144:ef7eb2e8f9f7 23337 #define SPI_SSCTL_SLVTOIEN_Pos (5) /*!< SPI SSCTL: SLVTOIEN Position */
<> 144:ef7eb2e8f9f7 23338 #define SPI_SSCTL_SLVTOIEN_Msk (0x1ul << SPI_SSCTL_SLVTOIEN_Pos) /*!< SPI SSCTL: SLVTOIEN Mask */
<> 144:ef7eb2e8f9f7 23339
<> 144:ef7eb2e8f9f7 23340 #define SPI_SSCTL_SLVTORST_Pos (6) /*!< SPI SSCTL: SLVTORST Position */
<> 144:ef7eb2e8f9f7 23341 #define SPI_SSCTL_SLVTORST_Msk (0x1ul << SPI_SSCTL_SLVTORST_Pos) /*!< SPI SSCTL: SLVTORST Mask */
<> 144:ef7eb2e8f9f7 23342
<> 144:ef7eb2e8f9f7 23343 #define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI SSCTL: SLVBEIEN Position */
<> 144:ef7eb2e8f9f7 23344 #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI SSCTL: SLVBEIEN Mask */
<> 144:ef7eb2e8f9f7 23345
<> 144:ef7eb2e8f9f7 23346 #define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI SSCTL: SLVURIEN Position */
<> 144:ef7eb2e8f9f7 23347 #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI SSCTL: SLVURIEN Mask */
<> 144:ef7eb2e8f9f7 23348
<> 144:ef7eb2e8f9f7 23349 #define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI SSCTL: SSACTIEN Position */
<> 144:ef7eb2e8f9f7 23350 #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI SSCTL: SSACTIEN Mask */
<> 144:ef7eb2e8f9f7 23351
<> 144:ef7eb2e8f9f7 23352 #define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI SSCTL: SSINAIEN Position */
<> 144:ef7eb2e8f9f7 23353 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI SSCTL: SSINAIEN Mask */
<> 144:ef7eb2e8f9f7 23354
<> 144:ef7eb2e8f9f7 23355 #define SPI_SSCTL_SLVTOCNT_Pos (16) /*!< SPI SSCTL: SLVTOCNT Position */
<> 144:ef7eb2e8f9f7 23356 #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) /*!< SPI SSCTL: SLVTOCNT Mask */
<> 144:ef7eb2e8f9f7 23357
<> 144:ef7eb2e8f9f7 23358 #define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI PDMACTL: TXPDMAEN Position */
<> 144:ef7eb2e8f9f7 23359 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI PDMACTL: TXPDMAEN Mask */
<> 144:ef7eb2e8f9f7 23360
<> 144:ef7eb2e8f9f7 23361 #define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI PDMACTL: RXPDMAEN Position */
<> 144:ef7eb2e8f9f7 23362 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI PDMACTL: RXPDMAEN Mask */
<> 144:ef7eb2e8f9f7 23363
<> 144:ef7eb2e8f9f7 23364 #define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI PDMACTL: PDMARST Position */
<> 144:ef7eb2e8f9f7 23365 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI PDMACTL: PDMARST Mask */
<> 144:ef7eb2e8f9f7 23366
<> 144:ef7eb2e8f9f7 23367 #define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI FIFOCTL: RXRST Position */
<> 144:ef7eb2e8f9f7 23368 #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI FIFOCTL: RXRST Mask */
<> 144:ef7eb2e8f9f7 23369
<> 144:ef7eb2e8f9f7 23370 #define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI FIFOCTL: TXRST Position */
<> 144:ef7eb2e8f9f7 23371 #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI FIFOCTL: TXRST Mask */
<> 144:ef7eb2e8f9f7 23372
<> 144:ef7eb2e8f9f7 23373 #define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI FIFOCTL: RXTHIEN Position */
<> 144:ef7eb2e8f9f7 23374 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI FIFOCTL: RXTHIEN Mask */
<> 144:ef7eb2e8f9f7 23375
<> 144:ef7eb2e8f9f7 23376 #define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI FIFOCTL: TXTHIEN Position */
<> 144:ef7eb2e8f9f7 23377 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI FIFOCTL: TXTHIEN Mask */
<> 144:ef7eb2e8f9f7 23378
<> 144:ef7eb2e8f9f7 23379 #define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI FIFOCTL: RXTOIEN Position */
<> 144:ef7eb2e8f9f7 23380 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI FIFOCTL: RXTOIEN Mask */
<> 144:ef7eb2e8f9f7 23381
<> 144:ef7eb2e8f9f7 23382 #define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI FIFOCTL: RXOVIEN Position */
<> 144:ef7eb2e8f9f7 23383 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI FIFOCTL: RXOVIEN Mask */
<> 144:ef7eb2e8f9f7 23384
<> 144:ef7eb2e8f9f7 23385 #define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI FIFOCTL: TXUFPOL Position */
<> 144:ef7eb2e8f9f7 23386 #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI FIFOCTL: TXUFPOL Mask */
<> 144:ef7eb2e8f9f7 23387
<> 144:ef7eb2e8f9f7 23388 #define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI FIFOCTL: TXUFIEN Position */
<> 144:ef7eb2e8f9f7 23389 #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI FIFOCTL: TXUFIEN Mask */
<> 144:ef7eb2e8f9f7 23390
<> 144:ef7eb2e8f9f7 23391 #define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI FIFOCTL: RXTH Position */
<> 144:ef7eb2e8f9f7 23392 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI FIFOCTL: RXTH Mask */
<> 144:ef7eb2e8f9f7 23393
<> 144:ef7eb2e8f9f7 23394 #define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI FIFOCTL: TXTH Position */
<> 144:ef7eb2e8f9f7 23395 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI FIFOCTL: TXTH Mask */
<> 144:ef7eb2e8f9f7 23396
<> 144:ef7eb2e8f9f7 23397 #define SPI_STATUS_BUSY_Pos (0) /*!< SPI STATUS: BUSY Position */
<> 144:ef7eb2e8f9f7 23398 #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI STATUS: BUSY Mask */
<> 144:ef7eb2e8f9f7 23399
<> 144:ef7eb2e8f9f7 23400 #define SPI_STATUS_UNITIF_Pos (1) /*!< SPI STATUS: UNITIF Position */
<> 144:ef7eb2e8f9f7 23401 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI STATUS: UNITIF Mask */
<> 144:ef7eb2e8f9f7 23402
<> 144:ef7eb2e8f9f7 23403 #define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI STATUS: SSACTIF Position */
<> 144:ef7eb2e8f9f7 23404 #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI STATUS: SSACTIF Mask */
<> 144:ef7eb2e8f9f7 23405
<> 144:ef7eb2e8f9f7 23406 #define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI STATUS: SSINAIF Position */
<> 144:ef7eb2e8f9f7 23407 #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI STATUS: SSINAIF Mask */
<> 144:ef7eb2e8f9f7 23408
<> 144:ef7eb2e8f9f7 23409 #define SPI_STATUS_SSLINE_Pos (4) /*!< SPI STATUS: SSLINE Position */
<> 144:ef7eb2e8f9f7 23410 #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI STATUS: SSLINE Mask */
<> 144:ef7eb2e8f9f7 23411
<> 144:ef7eb2e8f9f7 23412 #define SPI_STATUS_SLVTOIF_Pos (5) /*!< SPI STATUS: SLVTOIF Position */
<> 144:ef7eb2e8f9f7 23413 #define SPI_STATUS_SLVTOIF_Msk (0x1ul << SPI_STATUS_SLVTOIF_Pos) /*!< SPI STATUS: SLVTOIF Mask */
<> 144:ef7eb2e8f9f7 23414
<> 144:ef7eb2e8f9f7 23415 #define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI STATUS: SLVBEIF Position */
<> 144:ef7eb2e8f9f7 23416 #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI STATUS: SLVBEIF Mask */
<> 144:ef7eb2e8f9f7 23417
<> 144:ef7eb2e8f9f7 23418 #define SPI_STATUS_SLVUDRIF_Pos (7) /*!< SPI STATUS: SLVUDRIF Position */
<> 144:ef7eb2e8f9f7 23419 #define SPI_STATUS_SLVUDRIF_Msk (0x1ul << SPI_STATUS_SLVUDRIF_Pos) /*!< SPI STATUS: SLVUDRIF Mask */
<> 144:ef7eb2e8f9f7 23420
<> 144:ef7eb2e8f9f7 23421 #define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI STATUS: RXEMPTY Position */
<> 144:ef7eb2e8f9f7 23422 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI STATUS: RXEMPTY Mask */
<> 144:ef7eb2e8f9f7 23423
<> 144:ef7eb2e8f9f7 23424 #define SPI_STATUS_RXFULL_Pos (9) /*!< SPI STATUS: RXFULL Position */
<> 144:ef7eb2e8f9f7 23425 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI STATUS: RXFULL Mask */
<> 144:ef7eb2e8f9f7 23426
<> 144:ef7eb2e8f9f7 23427 #define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI STATUS: RXTHIF Position */
<> 144:ef7eb2e8f9f7 23428 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI STATUS: RXTHIF Mask */
<> 144:ef7eb2e8f9f7 23429
<> 144:ef7eb2e8f9f7 23430 #define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI STATUS: RXOVIF Position */
<> 144:ef7eb2e8f9f7 23431 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI STATUS: RXOVIF Mask */
<> 144:ef7eb2e8f9f7 23432
<> 144:ef7eb2e8f9f7 23433 #define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI STATUS: RXTOIF Position */
<> 144:ef7eb2e8f9f7 23434 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI STATUS: RXTOIF Mask */
<> 144:ef7eb2e8f9f7 23435
<> 144:ef7eb2e8f9f7 23436 #define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI STATUS: SPIENSTS Position */
<> 144:ef7eb2e8f9f7 23437 #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI STATUS: SPIENSTS Mask */
<> 144:ef7eb2e8f9f7 23438
<> 144:ef7eb2e8f9f7 23439 #define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI STATUS: TXEMPTY Position */
<> 144:ef7eb2e8f9f7 23440 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI STATUS: TXEMPTY Mask */
<> 144:ef7eb2e8f9f7 23441
<> 144:ef7eb2e8f9f7 23442 #define SPI_STATUS_TXFULL_Pos (17) /*!< SPI STATUS: TXFULL Position */
<> 144:ef7eb2e8f9f7 23443 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI STATUS: TXFULL Mask */
<> 144:ef7eb2e8f9f7 23444
<> 144:ef7eb2e8f9f7 23445 #define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI STATUS: TXTHIF Position */
<> 144:ef7eb2e8f9f7 23446 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI STATUS: TXTHIF Mask */
<> 144:ef7eb2e8f9f7 23447
<> 144:ef7eb2e8f9f7 23448 #define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI STATUS: TXUFIF Position */
<> 144:ef7eb2e8f9f7 23449 #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI STATUS: TXUFIF Mask */
<> 144:ef7eb2e8f9f7 23450
<> 144:ef7eb2e8f9f7 23451 #define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI STATUS: TXRXRST Position */
<> 144:ef7eb2e8f9f7 23452 #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI STATUS: TXRXRST Mask */
<> 144:ef7eb2e8f9f7 23453
<> 144:ef7eb2e8f9f7 23454 #define SPI_STATUS_RXCNT_Pos (24) /*!< SPI STATUS: RXCNT Position */
<> 144:ef7eb2e8f9f7 23455 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI STATUS: RXCNT Mask */
<> 144:ef7eb2e8f9f7 23456
<> 144:ef7eb2e8f9f7 23457 #define SPI_STATUS_TXCNT_Pos (28) /*!< SPI STATUS: TXCNT Position */
<> 144:ef7eb2e8f9f7 23458 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI STATUS: TXCNT Mask */
<> 144:ef7eb2e8f9f7 23459
<> 144:ef7eb2e8f9f7 23460 #define SPI_TX_TX_Pos (0) /*!< SPI TX: TX Position */
<> 144:ef7eb2e8f9f7 23461 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI TX: TX Mask */
<> 144:ef7eb2e8f9f7 23462
<> 144:ef7eb2e8f9f7 23463 #define SPI_RX_RX_Pos (0) /*!< SPI RX: RX Position */
<> 144:ef7eb2e8f9f7 23464 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI RX: RX Mask */
<> 144:ef7eb2e8f9f7 23465
<> 144:ef7eb2e8f9f7 23466 /**@}*/ /* SPI_CONST */
<> 144:ef7eb2e8f9f7 23467 /**@}*/ /* end of SPI register group */
<> 144:ef7eb2e8f9f7 23468
<> 144:ef7eb2e8f9f7 23469
<> 144:ef7eb2e8f9f7 23470 /*---------------------- System Manger Controller -------------------------*/
<> 144:ef7eb2e8f9f7 23471 /**
<> 144:ef7eb2e8f9f7 23472 @addtogroup SYS System Manger Controller(SYS)
<> 144:ef7eb2e8f9f7 23473 Memory Mapped Structure for SYS Controller
<> 144:ef7eb2e8f9f7 23474 @{ */
<> 144:ef7eb2e8f9f7 23475
<> 144:ef7eb2e8f9f7 23476 typedef struct {
<> 144:ef7eb2e8f9f7 23477
<> 144:ef7eb2e8f9f7 23478
<> 144:ef7eb2e8f9f7 23479 /**
<> 144:ef7eb2e8f9f7 23480 * PDID
<> 144:ef7eb2e8f9f7 23481 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23482 * Offset: 0x00 Part Device Identification Number Register
<> 144:ef7eb2e8f9f7 23483 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23484 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23485 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23486 * |[0:31] |SYS_PDID |Part Device Identification Number
<> 144:ef7eb2e8f9f7 23487 * | | |This register reflects device part number code.
<> 144:ef7eb2e8f9f7 23488 * | | |S/W can read this register to identify which device is used.
<> 144:ef7eb2e8f9f7 23489 */
<> 144:ef7eb2e8f9f7 23490 __I uint32_t PDID;
<> 144:ef7eb2e8f9f7 23491
<> 144:ef7eb2e8f9f7 23492 /**
<> 144:ef7eb2e8f9f7 23493 * RSTSTS
<> 144:ef7eb2e8f9f7 23494 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23495 * Offset: 0x04 System Reset Source Register
<> 144:ef7eb2e8f9f7 23496 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23497 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23498 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23499 * |[0] |PORF |The PORF Flag Is Set By The "Reset Signal" From The Power-On Reset (POR) Controller Or Bit CHIPRST (SYS_IPRST0[0]) To Indicate The Previous Reset Source
<> 144:ef7eb2e8f9f7 23500 * | | |0 = No reset from POR or CHIPRST.
<> 144:ef7eb2e8f9f7 23501 * | | |1 = Power-On Reset (POR) or CHIPRST had issued the reset signal to reset the system.
<> 144:ef7eb2e8f9f7 23502 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 23503 * |[1] |PINRF |The PINRF Flag Is Set By The "Reset Signal" From The /RESET Pin To Indicate The Previous Reset Source
<> 144:ef7eb2e8f9f7 23504 * | | |0 = No reset from /RESET pin.
<> 144:ef7eb2e8f9f7 23505 * | | |1 = The Pin /RESET had issued the reset signal to reset the system.
<> 144:ef7eb2e8f9f7 23506 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 23507 * |[2] |WDTRF |The WDTRF Flag Is Set By The "Reset Signal" From The Watchdog Timer To Indicate The Previous Reset Source
<> 144:ef7eb2e8f9f7 23508 * | | |0 = No reset from watchdog timer.
<> 144:ef7eb2e8f9f7 23509 * | | |1 = The watchdog timer had issued the reset signal to reset the system.
<> 144:ef7eb2e8f9f7 23510 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 23511 * |[3] |LVRF |The LVRF Flag Is Set By The "Reset Signal" From The Low-Voltage-Reset Controller To Indicate The Previous Reset Source
<> 144:ef7eb2e8f9f7 23512 * | | |0 = No reset from LVR.
<> 144:ef7eb2e8f9f7 23513 * | | |1 = The LVR controller had issued the reset signal to reset the system.
<> 144:ef7eb2e8f9f7 23514 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 23515 * |[4] |BODRF |The BODRF Flag Is Set By The "Reset Signal" From The Brown-Out-Detector To Indicate The Previous Reset Source
<> 144:ef7eb2e8f9f7 23516 * | | |0 = No reset from BOD.
<> 144:ef7eb2e8f9f7 23517 * | | |1 = The BOD had issued the reset signal to reset the system.
<> 144:ef7eb2e8f9f7 23518 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 23519 * |[5] |SYSRF |The SYSRF Flag Is Set By The "Reset Signal" From The Cortex(TM)-M4 Core To Indicate The Previous Reset Source
<> 144:ef7eb2e8f9f7 23520 * | | |0 = No reset from Cortex(TM)-M4.
<> 144:ef7eb2e8f9f7 23521 * | | |1 = The Cortex(TM)-M4 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex(TM)-M4 core.
<> 144:ef7eb2e8f9f7 23522 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 23523 * |[7] |CPURF |The CPURF Flag Is Set By Hardware If Software Writes CPURST (SYS_IPRST0[1]) 1 To Reset Cortex(TM)-M4 Core And Flash Memory Controller (FMC)
<> 144:ef7eb2e8f9f7 23524 * | | |0 = No reset from CPU.
<> 144:ef7eb2e8f9f7 23525 * | | |1 = The Cortex(TM)-M4 Core and FMC are reset by software setting CPURST to 1.
<> 144:ef7eb2e8f9f7 23526 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 23527 */
<> 144:ef7eb2e8f9f7 23528 __IO uint32_t RSTSTS;
<> 144:ef7eb2e8f9f7 23529
<> 144:ef7eb2e8f9f7 23530 /**
<> 144:ef7eb2e8f9f7 23531 * IPRST0
<> 144:ef7eb2e8f9f7 23532 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23533 * Offset: 0x08 Peripheral Controller Reset Control Register 1
<> 144:ef7eb2e8f9f7 23534 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23535 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23536 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23537 * |[0] |CHIPRST |Chip One-Shot Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23538 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles.
<> 144:ef7eb2e8f9f7 23539 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload.
<> 144:ef7eb2e8f9f7 23540 * | | |This bit is a write protected bit, which means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23541 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23542 * | | |0 = Chip normal operation.
<> 144:ef7eb2e8f9f7 23543 * | | |1 = Chip one shot reset.
<> 144:ef7eb2e8f9f7 23544 * |[1] |CPURST |Processor Core One-Shot Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23545 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles
<> 144:ef7eb2e8f9f7 23546 * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23547 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23548 * | | |0 = Processor core normal operation.
<> 144:ef7eb2e8f9f7 23549 * | | |1 = Processor core one-shot reset.
<> 144:ef7eb2e8f9f7 23550 * |[2] |PDMARST |PDMA Controller Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23551 * | | |Setting this bit to 1 will generate a reset signal to the PDMA.
<> 144:ef7eb2e8f9f7 23552 * | | |User needs to set this bit to 0 to release from reset state.
<> 144:ef7eb2e8f9f7 23553 * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23554 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23555 * | | |0 = PDMA controller normal operation.
<> 144:ef7eb2e8f9f7 23556 * | | |1 = PDMA controller reset.
<> 144:ef7eb2e8f9f7 23557 * |[3] |EBIRST |EBI Controller Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23558 * | | |Setting this bit to 1 will generate a reset signal to the EBI.
<> 144:ef7eb2e8f9f7 23559 * | | |User needs to set this bit to 0 to release from the reset state.
<> 144:ef7eb2e8f9f7 23560 * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23561 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23562 * | | |0 = EBI controller normal operation.
<> 144:ef7eb2e8f9f7 23563 * | | |1 = EBI controller reset.
<> 144:ef7eb2e8f9f7 23564 * |[4] |USBHRST |UHC Controller Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23565 * | | |Setting this bit to 1 will generate a reset signal to the HSB HOST controller.
<> 144:ef7eb2e8f9f7 23566 * | | |User needs to set this bit to 0 to release from the reset state.
<> 144:ef7eb2e8f9f7 23567 * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23568 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23569 * | | |0 = UHC controller normal operation.
<> 144:ef7eb2e8f9f7 23570 * | | |1 = UHC controller reset.
<> 144:ef7eb2e8f9f7 23571 * |[5] |SDHRST |EMAC Controller Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23572 * | | |Setting this bit to 1 will generate a reset signal to the EMAC controller.
<> 144:ef7eb2e8f9f7 23573 * | | |User needs to set this bit to 0 to release from the reset state.
<> 144:ef7eb2e8f9f7 23574 * | | |This bit is the protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23575 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23576 * | | |0 = EMAC controller normal operation.
<> 144:ef7eb2e8f9f7 23577 * | | |1 = EMAC controller reset.
<> 144:ef7eb2e8f9f7 23578 * |[6] |SDHOST_RST|SD HOST Controller Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23579 * | | |Setting this bit to 1 will generate a reset signal to the SD HOST controller.
<> 144:ef7eb2e8f9f7 23580 * | | |User needs to set this bit to 0 to release from the reset state.
<> 144:ef7eb2e8f9f7 23581 * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23582 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23583 * | | |0 = SD HOST controller normal operation.
<> 144:ef7eb2e8f9f7 23584 * | | |1 = SD HOST controller reset.
<> 144:ef7eb2e8f9f7 23585 * |[7] |CRCRST |CRC Controller Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23586 * | | |Setting this bit to 1 will generate a reset signal to the CRC controller.
<> 144:ef7eb2e8f9f7 23587 * | | |User needs to set this bit to 0 to release from the reset state.
<> 144:ef7eb2e8f9f7 23588 * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23589 * | | |Reference the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23590 * | | |0 = CRC controller normal operation.
<> 144:ef7eb2e8f9f7 23591 * | | |1 = CRC controller reset.
<> 144:ef7eb2e8f9f7 23592 * |[8] |CAPRST |Image Capture Controller Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23593 * | | |Setting this bit to 1 will generate a reset signal to the CAP controller.
<> 144:ef7eb2e8f9f7 23594 * | | |User needs to set this bit to 0 to release from the reset state.
<> 144:ef7eb2e8f9f7 23595 * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23596 * | | |Reference the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23597 * | | |0 = CAP controller normal operation.
<> 144:ef7eb2e8f9f7 23598 * | | |1 = CAP controller reset.
<> 144:ef7eb2e8f9f7 23599 * |[12] |CRPT_RST |CRYPTO Controller Reset (Write Protect)
<> 144:ef7eb2e8f9f7 23600 * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller.
<> 144:ef7eb2e8f9f7 23601 * | | |User needs to set this bit to 0 to release from the reset state.
<> 144:ef7eb2e8f9f7 23602 * | | |This bit is a write protected bit, It means programming this bit needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23603 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23604 * | | |0 = CRYPTO controller normal operation.
<> 144:ef7eb2e8f9f7 23605 * | | |1 = CRYPTO controller reset.
<> 144:ef7eb2e8f9f7 23606 */
<> 144:ef7eb2e8f9f7 23607 __IO uint32_t IPRST0;
<> 144:ef7eb2e8f9f7 23608
<> 144:ef7eb2e8f9f7 23609 /**
<> 144:ef7eb2e8f9f7 23610 * IPRST1
<> 144:ef7eb2e8f9f7 23611 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23612 * Offset: 0x0C Peripheral Controller Reset Control Register 2
<> 144:ef7eb2e8f9f7 23613 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23614 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23615 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23616 * |[1] |GPIORST |GPIO Controller Reset
<> 144:ef7eb2e8f9f7 23617 * | | |0 = GPIO controller normal operation.
<> 144:ef7eb2e8f9f7 23618 * | | |1 = GPIO controller reset.
<> 144:ef7eb2e8f9f7 23619 * |[2] |TMR0RST |Timer0 Controller Reset
<> 144:ef7eb2e8f9f7 23620 * | | |0 = Timer0 controller normal operation.
<> 144:ef7eb2e8f9f7 23621 * | | |1 = Timer0 controller reset.
<> 144:ef7eb2e8f9f7 23622 * |[3] |TMR1RST |Timer1 Controller Reset
<> 144:ef7eb2e8f9f7 23623 * | | |0 = Timer1 controller normal operation.
<> 144:ef7eb2e8f9f7 23624 * | | |1 = Timer1 controller reset.
<> 144:ef7eb2e8f9f7 23625 * |[4] |TMR2RST |Timer2 Controller Reset
<> 144:ef7eb2e8f9f7 23626 * | | |0 = Timer2 controller normal operation.
<> 144:ef7eb2e8f9f7 23627 * | | |1 = Timer2 controller reset.
<> 144:ef7eb2e8f9f7 23628 * |[5] |TMR3RST |Timer3 Controller Reset
<> 144:ef7eb2e8f9f7 23629 * | | |0 = Timer3 controller normal operation.
<> 144:ef7eb2e8f9f7 23630 * | | |1 = Timer3 controller reset.
<> 144:ef7eb2e8f9f7 23631 * |[7] |ACMPRST |Analog Comparator Controller Reset
<> 144:ef7eb2e8f9f7 23632 * | | |0 = Analog Comparator controller normal operation.
<> 144:ef7eb2e8f9f7 23633 * | | |1 = Analog Comparator controller reset.
<> 144:ef7eb2e8f9f7 23634 * |[8] |I2C0RST |I2C0 Controller Reset
<> 144:ef7eb2e8f9f7 23635 * | | |0 = I2C0 controller normal operation.
<> 144:ef7eb2e8f9f7 23636 * | | |1 = I2C0 controller reset.
<> 144:ef7eb2e8f9f7 23637 * |[9] |I2C1RST |I2C1 Controller Reset
<> 144:ef7eb2e8f9f7 23638 * | | |0 = I2C1 controller normal operation.
<> 144:ef7eb2e8f9f7 23639 * | | |1 = I2C1 controller reset.
<> 144:ef7eb2e8f9f7 23640 * |[12] |SPI0RST |SPI0 Controller Reset
<> 144:ef7eb2e8f9f7 23641 * | | |0 = SPI0 controller normal operation.
<> 144:ef7eb2e8f9f7 23642 * | | |1 = SPI0 controller reset.
<> 144:ef7eb2e8f9f7 23643 * |[13] |SPI1RST |SPI1 Controller Reset
<> 144:ef7eb2e8f9f7 23644 * | | |0 = SPI1 controller normal operation.
<> 144:ef7eb2e8f9f7 23645 * | | |1 = SPI1 controller reset.
<> 144:ef7eb2e8f9f7 23646 * |[14] |SPI2RST |SPI2 Controller Reset
<> 144:ef7eb2e8f9f7 23647 * | | |0 = SPI2 controller normal operation.
<> 144:ef7eb2e8f9f7 23648 * | | |1 = SPI2 controller reset.
<> 144:ef7eb2e8f9f7 23649 * |[15] |SPI3RST |SPI3 Controller Reset
<> 144:ef7eb2e8f9f7 23650 * | | |0 = SPI3 controller normal operation.
<> 144:ef7eb2e8f9f7 23651 * | | |1 = SPI3 controller reset.
<> 144:ef7eb2e8f9f7 23652 * |[16] |UART0RST |UART0 Controller Reset
<> 144:ef7eb2e8f9f7 23653 * | | |0 = UART0 controller normal operation.
<> 144:ef7eb2e8f9f7 23654 * | | |1 = UART0 controller reset.
<> 144:ef7eb2e8f9f7 23655 * |[17] |UART1RST |UART1 Controller Reset
<> 144:ef7eb2e8f9f7 23656 * | | |0 = UART1 controller normal operation.
<> 144:ef7eb2e8f9f7 23657 * | | |1 = UART1 controller reset.
<> 144:ef7eb2e8f9f7 23658 * |[18] |UART2RST |UART2 Controller Reset
<> 144:ef7eb2e8f9f7 23659 * | | |0 = UART2 controller normal operation.
<> 144:ef7eb2e8f9f7 23660 * | | |1 = UART2 controller reset.
<> 144:ef7eb2e8f9f7 23661 * |[19] |UART3RST |UART3 Controller Reset
<> 144:ef7eb2e8f9f7 23662 * | | |0 = UART3 controller normal operation.
<> 144:ef7eb2e8f9f7 23663 * | | |1 = UART3 controller reset.
<> 144:ef7eb2e8f9f7 23664 * |[20] |UART4RST |UART4 Controller Reset
<> 144:ef7eb2e8f9f7 23665 * | | |0 = UART4 controller normal operation.
<> 144:ef7eb2e8f9f7 23666 * | | |1 = UART4 controller reset.
<> 144:ef7eb2e8f9f7 23667 * |[21] |UART5RST |UART2 Controller Reset
<> 144:ef7eb2e8f9f7 23668 * | | |0 = UART5 controller normal operation.
<> 144:ef7eb2e8f9f7 23669 * | | |1 = UART5 controller reset.
<> 144:ef7eb2e8f9f7 23670 * |[24] |CAN0RST |CAN0 Controller Reset
<> 144:ef7eb2e8f9f7 23671 * | | |0 = CAN0 controller normal operation.
<> 144:ef7eb2e8f9f7 23672 * | | |1 = CAN0 controller reset.
<> 144:ef7eb2e8f9f7 23673 * |[25] |CAN1RST |CAN1 Controller Reset
<> 144:ef7eb2e8f9f7 23674 * | | |0 = CAN1 controller normal operation.
<> 144:ef7eb2e8f9f7 23675 * | | |1 = CAN1 controller reset.
<> 144:ef7eb2e8f9f7 23676 * |[27] |USBDRST |USB Device Controller Reset
<> 144:ef7eb2e8f9f7 23677 * | | |0 = USB device controller normal operation.
<> 144:ef7eb2e8f9f7 23678 * | | |1 = USB device controller reset.
<> 144:ef7eb2e8f9f7 23679 * |[28] |ADCRST |ADC Controller Reset
<> 144:ef7eb2e8f9f7 23680 * | | |0 = ADC controller normal operation.
<> 144:ef7eb2e8f9f7 23681 * | | |1 = ADC controller reset.
<> 144:ef7eb2e8f9f7 23682 * |[29] |I2SRST |I2S Controller Reset
<> 144:ef7eb2e8f9f7 23683 * | | |0 = I2S controller normal operation.
<> 144:ef7eb2e8f9f7 23684 * | | |1 = I2S controller reset.
<> 144:ef7eb2e8f9f7 23685 * |[30] |I2S1RST |I2S1 Controller Reset
<> 144:ef7eb2e8f9f7 23686 * | | |0 = I2S1 controller normal operation.
<> 144:ef7eb2e8f9f7 23687 * | | |1 = I2S1 controller reset.
<> 144:ef7eb2e8f9f7 23688 * |[31] |PS2RST |PS/2 Controller Reset
<> 144:ef7eb2e8f9f7 23689 * | | |0 = PS/2 controller normal operation.
<> 144:ef7eb2e8f9f7 23690 * | | |1 = PS/2 controller reset.
<> 144:ef7eb2e8f9f7 23691 */
<> 144:ef7eb2e8f9f7 23692 __IO uint32_t IPRST1;
<> 144:ef7eb2e8f9f7 23693
<> 144:ef7eb2e8f9f7 23694 /**
<> 144:ef7eb2e8f9f7 23695 * IPRST2
<> 144:ef7eb2e8f9f7 23696 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23697 * Offset: 0x10 Peripheral Controller Reset Control Register 3
<> 144:ef7eb2e8f9f7 23698 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23699 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23700 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23701 * |[0] |SC0RST |SC0 Controller Reset
<> 144:ef7eb2e8f9f7 23702 * | | |0 = SC0 controller normal operation.
<> 144:ef7eb2e8f9f7 23703 * | | |1 = SC0 controller reset.
<> 144:ef7eb2e8f9f7 23704 * |[1] |SC1RST |SC1 Controller Reset
<> 144:ef7eb2e8f9f7 23705 * | | |0 = SC1 controller normal operation.
<> 144:ef7eb2e8f9f7 23706 * | | |1 = SC1 controller reset.
<> 144:ef7eb2e8f9f7 23707 * |[2] |SC2RST |SC2 Controller Reset
<> 144:ef7eb2e8f9f7 23708 * | | |0 = SC2 controller normal operation.
<> 144:ef7eb2e8f9f7 23709 * | | |1 = SC2 controller reset.
<> 144:ef7eb2e8f9f7 23710 * |[3] |SC3RST |SC3 Controller Reset
<> 144:ef7eb2e8f9f7 23711 * | | |0 = SC3 controller normal operation.
<> 144:ef7eb2e8f9f7 23712 * | | |1 = SC3 controller reset.
<> 144:ef7eb2e8f9f7 23713 * |[4] |SC4RST |SC4 Controller Reset
<> 144:ef7eb2e8f9f7 23714 * | | |0 = SC4 controller normal operation.
<> 144:ef7eb2e8f9f7 23715 * | | |1 = SC4 controller reset.
<> 144:ef7eb2e8f9f7 23716 * |[5] |SC5RST |SC5 Controller Reset
<> 144:ef7eb2e8f9f7 23717 * | | |0 = SC5 controller normal operation.
<> 144:ef7eb2e8f9f7 23718 * | | |1 = SC5 controller reset.
<> 144:ef7eb2e8f9f7 23719 * |[8] |I2C4RST |I2C4 Controller Reset
<> 144:ef7eb2e8f9f7 23720 * | | |0 = I2C4 controller normal operation.
<> 144:ef7eb2e8f9f7 23721 * | | |1 = I2C4 controller reset.
<> 144:ef7eb2e8f9f7 23722 * |[16] |PWM0RST |PWM0 Controller Reset
<> 144:ef7eb2e8f9f7 23723 * | | |0 = PWM0 controller normal operation.
<> 144:ef7eb2e8f9f7 23724 * | | |1 = PWM0 controller reset.
<> 144:ef7eb2e8f9f7 23725 * |[17] |PWM1RST |PWM1 Controller Reset
<> 144:ef7eb2e8f9f7 23726 * | | |0 = PWM1 controller normal operation.
<> 144:ef7eb2e8f9f7 23727 * | | |1 = PWM1 controller reset.
<> 144:ef7eb2e8f9f7 23728 * |[22] |QEI0RST |QEI0 Controller Reset
<> 144:ef7eb2e8f9f7 23729 * | | |0 = QEI0 controller normal operation.
<> 144:ef7eb2e8f9f7 23730 * | | |1 = QEI0 controller reset.
<> 144:ef7eb2e8f9f7 23731 * |[23] |QEI1RST |QEI1 Controller Reset
<> 144:ef7eb2e8f9f7 23732 * | | |0 = QEI1 controller normal operation.
<> 144:ef7eb2e8f9f7 23733 * | | |1 = QEI1 controller reset.
<> 144:ef7eb2e8f9f7 23734 */
<> 144:ef7eb2e8f9f7 23735 __IO uint32_t IPRST2;
<> 144:ef7eb2e8f9f7 23736 uint32_t RESERVE0[1];
<> 144:ef7eb2e8f9f7 23737
<> 144:ef7eb2e8f9f7 23738
<> 144:ef7eb2e8f9f7 23739 /**
<> 144:ef7eb2e8f9f7 23740 * BODCTL
<> 144:ef7eb2e8f9f7 23741 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23742 * Offset: 0x18 Brown-out Detector Control Register
<> 144:ef7eb2e8f9f7 23743 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23744 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23745 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23746 * |[0] |BODEN |Brown-Out Detector Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 23747 * | | |The default value is set by flash controller user configuration register config0 bit[23]
<> 144:ef7eb2e8f9f7 23748 * | | |0 = Brown-out Detector function Disabled.
<> 144:ef7eb2e8f9f7 23749 * | | |1 = Brown-out Detector function Enabled.
<> 144:ef7eb2e8f9f7 23750 * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23751 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23752 * |[1:2] |BODVL |Brown-Out Detector Threshold Voltage Selection (Write Protect)
<> 144:ef7eb2e8f9f7 23753 * | | |The default value is set by flash controller user configuration register config0 bit[22:21]
<> 144:ef7eb2e8f9f7 23754 * | | |Relationship between BODVL and Brown-out voltage listed below:
<> 144:ef7eb2e8f9f7 23755 * | | |00 = 2.2V.
<> 144:ef7eb2e8f9f7 23756 * | | |01 = 2.7V.
<> 144:ef7eb2e8f9f7 23757 * | | |10 = 3.8V.
<> 144:ef7eb2e8f9f7 23758 * | | |11 = 4.5V.
<> 144:ef7eb2e8f9f7 23759 * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23760 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23761 * |[3] |BODRSTEN |Brown-Out Reset Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 23762 * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high).
<> 144:ef7eb2e8f9f7 23763 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if BODOUT is high.
<> 144:ef7eb2e8f9f7 23764 * | | |BOD interrupt will keep till to the BODEN set to 0.
<> 144:ef7eb2e8f9f7 23765 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low).
<> 144:ef7eb2e8f9f7 23766 * | | |The default value is set by flash controller user configuration register config0 bit[20].
<> 144:ef7eb2e8f9f7 23767 * | | |0 = Brown-out "INTERRUPT" function Enabled.
<> 144:ef7eb2e8f9f7 23768 * | | |1 = Brown-out "RESET" function Enabled.
<> 144:ef7eb2e8f9f7 23769 * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23770 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23771 * |[4] |BODINTF |Brown-Out Detector Interrupt Flag
<> 144:ef7eb2e8f9f7 23772 * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting.
<> 144:ef7eb2e8f9f7 23773 * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled.
<> 144:ef7eb2e8f9f7 23774 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 23775 * |[5] |BODLPM |Brown-Out Detector Low Power Mode (Write Protect)
<> 144:ef7eb2e8f9f7 23776 * | | |The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response.
<> 144:ef7eb2e8f9f7 23777 * | | |0 = BOD operate in normal mode (default).
<> 144:ef7eb2e8f9f7 23778 * | | |1 = BOD Low Power mode Enabled.
<> 144:ef7eb2e8f9f7 23779 * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23780 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23781 * |[6] |BODOUT |Brown-Out Detector Output Status
<> 144:ef7eb2e8f9f7 23782 * | | |0 = Brown-out Detector output status is 0.
<> 144:ef7eb2e8f9f7 23783 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0.
<> 144:ef7eb2e8f9f7 23784 * | | |1 = Brown-out Detector output status is 1.
<> 144:ef7eb2e8f9f7 23785 * | | |It means the detected voltage is lower than BODVL setting.
<> 144:ef7eb2e8f9f7 23786 * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0000.
<> 144:ef7eb2e8f9f7 23787 * |[7] |LVREN |Low Voltage Reset Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 23788 * | | |The LVR function reset the chip when the input power voltage is lower than LVR circuit setting.
<> 144:ef7eb2e8f9f7 23789 * | | |LVR function is enabled in default.
<> 144:ef7eb2e8f9f7 23790 * | | |0 = Low Voltage Reset function Disabled.
<> 144:ef7eb2e8f9f7 23791 * | | |1 = Low Voltage Reset function Enabled - After enabling the bit, the LVR function will be active with 100uS delay for LVR output stable (default).
<> 144:ef7eb2e8f9f7 23792 * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23793 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23794 */
<> 144:ef7eb2e8f9f7 23795 __IO uint32_t BODCTL;
<> 144:ef7eb2e8f9f7 23796
<> 144:ef7eb2e8f9f7 23797 /**
<> 144:ef7eb2e8f9f7 23798 * TEMPCTL
<> 144:ef7eb2e8f9f7 23799 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23800 * Offset: 0x1C Temperature Sensor Control Register
<> 144:ef7eb2e8f9f7 23801 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23802 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23803 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23804 * |[0] |VTEMPEN |Temperature Sensor Enable Control
<> 144:ef7eb2e8f9f7 23805 * | | |This bit is used to enable/disable temperature sensor function.
<> 144:ef7eb2e8f9f7 23806 * | | |0 = Temperature sensor function Disabled (default).
<> 144:ef7eb2e8f9f7 23807 * | | |1 = Temperature sensor function Enabled.
<> 144:ef7eb2e8f9f7 23808 * | | |After this bit is set to 1, the value of temperature sensor output can be obtained from ADC conversion result.
<> 144:ef7eb2e8f9f7 23809 * | | |Please refer to ADC function chapter for details.
<> 144:ef7eb2e8f9f7 23810 */
<> 144:ef7eb2e8f9f7 23811 __IO uint32_t TEMPCTL;
<> 144:ef7eb2e8f9f7 23812
<> 144:ef7eb2e8f9f7 23813 /**
<> 144:ef7eb2e8f9f7 23814 * VCID
<> 144:ef7eb2e8f9f7 23815 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23816 * Offset: 0x20 Hardware Version Control Register
<> 144:ef7eb2e8f9f7 23817 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23818 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23819 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23820 * |[0:15] |VCID |Hardware Version Control (Ready Only)
<> 144:ef7eb2e8f9f7 23821 * | | |These registers repress hardware version.
<> 144:ef7eb2e8f9f7 23822 * | | |These bits are the read protected bits.
<> 144:ef7eb2e8f9f7 23823 * | | |It means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23824 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23825 */
<> 144:ef7eb2e8f9f7 23826 __I uint32_t VCID;
<> 144:ef7eb2e8f9f7 23827
<> 144:ef7eb2e8f9f7 23828 /**
<> 144:ef7eb2e8f9f7 23829 * PORCTL
<> 144:ef7eb2e8f9f7 23830 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23831 * Offset: 0x24 Power-On-Reset Controller Register
<> 144:ef7eb2e8f9f7 23832 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23833 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23834 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23835 * |[0:15] |POROFF |Power-On-Reset Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 23836 * | | |When power on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again.
<> 144:ef7eb2e8f9f7 23837 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field.
<> 144:ef7eb2e8f9f7 23838 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including:
<> 144:ef7eb2e8f9f7 23839 * | | |/RESET, Watch dog, LVR reset, BOD reset, ICE reset command and the software-chip reset function
<> 144:ef7eb2e8f9f7 23840 * | | |This bit is the protected bit, which means programming this needs to write "59h", "16h", "88h" to address 0x4000_0100 to disable register protection.
<> 144:ef7eb2e8f9f7 23841 * | | |Refer to the register SYS_REGLCTL at address GCR_BA+0x100.
<> 144:ef7eb2e8f9f7 23842 */
<> 144:ef7eb2e8f9f7 23843 __IO uint32_t PORCTL;
<> 144:ef7eb2e8f9f7 23844
<> 144:ef7eb2e8f9f7 23845 /**
<> 144:ef7eb2e8f9f7 23846 * VREFCTL
<> 144:ef7eb2e8f9f7 23847 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23848 * Offset: 0x28 ADC VREF Control Register
<> 144:ef7eb2e8f9f7 23849 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23850 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23851 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23852 * |[0:4] |VREFCTL |Vref control bits (Write Protect)
<> 144:ef7eb2e8f9f7 23853 * | | |00011=Vref is internal 2.65V
<> 144:ef7eb2e8f9f7 23854 * | | |00111=Vref is internal 2.048V
<> 144:ef7eb2e8f9f7 23855 * | | |01011=Vref is internal 3.072V
<> 144:ef7eb2e8f9f7 23856 * | | |01111=Vref is internal 4.096V
<> 144:ef7eb2e8f9f7 23857 * | | |10000=Vref is from AVDD
<> 144:ef7eb2e8f9f7 23858 * | | |Others=Reserved
<> 144:ef7eb2e8f9f7 23859 * |[8] |ADCMODESEL|ADC IP Selection (Write Protect)
<> 144:ef7eb2e8f9f7 23860 * | | |0 = ADC mode.
<> 144:ef7eb2e8f9f7 23861 * | | |1 = E ADC mode.
<> 144:ef7eb2e8f9f7 23862 * |[9] |PWMSYNCMODE|PWM SYNC MODE (Write Protect)
<> 144:ef7eb2e8f9f7 23863 * | | |0 = PWM SYNC MODE Disabled; PWM engine clock can different with HCLK.
<> 144:ef7eb2e8f9f7 23864 * | | |1 = PWM SYNC MODE Enabled; PWM engine clock is same as HCLK.
<> 144:ef7eb2e8f9f7 23865 */
<> 144:ef7eb2e8f9f7 23866 __IO uint32_t VREFCTL;
<> 144:ef7eb2e8f9f7 23867
<> 144:ef7eb2e8f9f7 23868 /**
<> 144:ef7eb2e8f9f7 23869 * USBPHY
<> 144:ef7eb2e8f9f7 23870 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23871 * Offset: 0x2C USB PHY Control Register
<> 144:ef7eb2e8f9f7 23872 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23873 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23874 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23875 * |[0:1] |USBROLE |USB Role Configuration (Write Protect)
<> 144:ef7eb2e8f9f7 23876 * | | |USB role configuration can be from ROMMAP or software setting if software setting option, controlled by ROMMAP, is enabled.
<> 144:ef7eb2e8f9f7 23877 * | | |00 = Standard USB device.
<> 144:ef7eb2e8f9f7 23878 * | | |01 = Standard USB host.
<> 144:ef7eb2e8f9f7 23879 * | | |10 = ID dependent device.
<> 144:ef7eb2e8f9f7 23880 * | | |11 = On-The-Go device.
<> 144:ef7eb2e8f9f7 23881 * |[8] |LDO33EN |LDO33 Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 23882 * | | |0 = USB LDO33 Disabled.
<> 144:ef7eb2e8f9f7 23883 * | | |1 = USB LDO33 Enabled.
<> 144:ef7eb2e8f9f7 23884 */
<> 144:ef7eb2e8f9f7 23885 __IO uint32_t USBPHY;
<> 144:ef7eb2e8f9f7 23886
<> 144:ef7eb2e8f9f7 23887 /**
<> 144:ef7eb2e8f9f7 23888 * GPA_MFPL
<> 144:ef7eb2e8f9f7 23889 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23890 * Offset: 0x30 Port A Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 23891 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23892 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23893 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23894 * |[0:3] |PA0MFP |PA.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23895 * |[4:7] |PA1MFP |PA.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23896 * |[8:11] |PA2MFP |PA.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23897 * |[12:15] |PA3MFP |PA.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23898 * |[16:19] |PA4MFP |PA.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23899 * |[20:23] |PA5MFP |PA.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23900 * |[24:27] |PA6MFP |PA.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23901 * |[28:31] |PA7MFP |PA.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23902 */
<> 144:ef7eb2e8f9f7 23903 __IO uint32_t GPA_MFPL;
<> 144:ef7eb2e8f9f7 23904
<> 144:ef7eb2e8f9f7 23905 /**
<> 144:ef7eb2e8f9f7 23906 * GPA_MFPH
<> 144:ef7eb2e8f9f7 23907 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23908 * Offset: 0x34 Port A High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 23909 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23910 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23911 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23912 * |[0:3] |PA8MFP |PA.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23913 * |[4:7] |PA9MFP |PA.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23914 * |[8:11] |PA10MFP |PA.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23915 * |[12:15] |PA11MFP |PA.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23916 * |[16:19] |PA12MFP |PA.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23917 * |[20:23] |PA13MFP |PA.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23918 * |[24:27] |PA14MFP |PA.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23919 * |[28:31] |PA15MFP |PA.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23920 */
<> 144:ef7eb2e8f9f7 23921 __IO uint32_t GPA_MFPH;
<> 144:ef7eb2e8f9f7 23922
<> 144:ef7eb2e8f9f7 23923 /**
<> 144:ef7eb2e8f9f7 23924 * GPB_MFPL
<> 144:ef7eb2e8f9f7 23925 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23926 * Offset: 0x38 Port B Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 23927 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23928 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23929 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23930 * |[0:3] |PB0MFP |PB.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23931 * |[4:7] |PB1MFP |PB.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23932 * |[8:11] |PB2MFP |PB.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23933 * |[12:15] |PB3MFP |PB.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23934 * |[16:19] |PB4MFP |PB.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23935 * |[20:23] |PB5MFP |PB.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23936 * |[24:27] |PB6MFP |PB.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23937 * |[28:31] |PB7MFP |PB.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23938 */
<> 144:ef7eb2e8f9f7 23939 __IO uint32_t GPB_MFPL;
<> 144:ef7eb2e8f9f7 23940
<> 144:ef7eb2e8f9f7 23941 /**
<> 144:ef7eb2e8f9f7 23942 * GPB_MFPH
<> 144:ef7eb2e8f9f7 23943 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23944 * Offset: 0x3C Port B High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 23945 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23946 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23947 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23948 * |[0:3] |PB8MFP |PB.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23949 * |[4:7] |PB9MFP |PB.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23950 * |[8:11] |PB10MFP |PB.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23951 * |[12:15] |PB11MFP |PB.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23952 * |[16:19] |PB12MFP |PB.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23953 * |[20:23] |PB13MFP |PB.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23954 * |[24:27] |PB14MFP |PB.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23955 * |[28:31] |PB15MFP |PB.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23956 */
<> 144:ef7eb2e8f9f7 23957 __IO uint32_t GPB_MFPH;
<> 144:ef7eb2e8f9f7 23958
<> 144:ef7eb2e8f9f7 23959 /**
<> 144:ef7eb2e8f9f7 23960 * GPC_MFPL
<> 144:ef7eb2e8f9f7 23961 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23962 * Offset: 0x40 Port C Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 23963 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23964 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23965 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23966 * |[0:3] |PC0MFP |PC.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23967 * |[4:7] |PC1MFP |PC.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23968 * |[8:11] |PC2MFP |PC.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23969 * |[12:15] |PC3MFP |PC.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23970 * |[16:19] |PC4MFP |PC.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23971 * |[20:23] |PC5MFP |PC.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23972 * |[24:27] |PC6MFP |PC.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23973 * |[28:31] |PC7MFP |PC.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23974 */
<> 144:ef7eb2e8f9f7 23975 __IO uint32_t GPC_MFPL;
<> 144:ef7eb2e8f9f7 23976
<> 144:ef7eb2e8f9f7 23977 /**
<> 144:ef7eb2e8f9f7 23978 * GPC_MFPH
<> 144:ef7eb2e8f9f7 23979 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23980 * Offset: 0x44 Port C High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 23981 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 23982 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 23983 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 23984 * |[0:3] |PC8MFP |PC.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23985 * |[4:7] |PC9MFP |PC.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23986 * |[8:11] |PC10MFP |PC.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23987 * |[12:15] |PC11MFP |PC.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23988 * |[16:19] |PC12MFP |PC.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23989 * |[20:23] |PC13MFP |PC.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23990 * |[24:27] |PC14MFP |PC.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23991 * |[28:31] |PC15MFP |PC.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 23992 */
<> 144:ef7eb2e8f9f7 23993 __IO uint32_t GPC_MFPH;
<> 144:ef7eb2e8f9f7 23994
<> 144:ef7eb2e8f9f7 23995 /**
<> 144:ef7eb2e8f9f7 23996 * GPD_MFPL
<> 144:ef7eb2e8f9f7 23997 * ===================================================================================================
<> 144:ef7eb2e8f9f7 23998 * Offset: 0x48 Port D Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 23999 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24000 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24001 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24002 * |[0:3] |PD0MFP |PD.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24003 * |[4:7] |PD1MFP |PD.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24004 * |[8:11] |PD2MFP |PD.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24005 * |[12:15] |PD3MFP |PD.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24006 * |[16:19] |PD4MFP |PD.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24007 * |[20:23] |PD5MFP |PD.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24008 * |[24:27] |PD6MFP |PD.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24009 * |[28:31] |PD7MFP |PD.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24010 */
<> 144:ef7eb2e8f9f7 24011 __IO uint32_t GPD_MFPL;
<> 144:ef7eb2e8f9f7 24012
<> 144:ef7eb2e8f9f7 24013 /**
<> 144:ef7eb2e8f9f7 24014 * GPD_MFPH
<> 144:ef7eb2e8f9f7 24015 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24016 * Offset: 0x4C Port D High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24017 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24018 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24019 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24020 * |[0:3] |PD8MFP |PD.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24021 * |[4:7] |PD9MFP |PD.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24022 * |[8:11] |PD10MFP |PD.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24023 * |[12:15] |PD11MFP |PD.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24024 * |[16:19] |PD12MFP |PD.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24025 * |[20:23] |PD13MFP |PD.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24026 * |[24:27] |PD14MFP |PD.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24027 * |[28:31] |PD15MFP |PD.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24028 */
<> 144:ef7eb2e8f9f7 24029 __IO uint32_t GPD_MFPH;
<> 144:ef7eb2e8f9f7 24030
<> 144:ef7eb2e8f9f7 24031 /**
<> 144:ef7eb2e8f9f7 24032 * GPE_MFPL
<> 144:ef7eb2e8f9f7 24033 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24034 * Offset: 0x50 Port E Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24035 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24036 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24037 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24038 * |[0:3] |PE0MFP |PE.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24039 * |[4:7] |PE1MFP |PE.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24040 * |[8:11] |PE2MFP |PE.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24041 * |[12:15] |PE3MFP |PE.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24042 * |[16:19] |PE4MFP |PE.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24043 * |[20:23] |PE5MFP |PE.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24044 * |[24:27] |PE6MFP |PE.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24045 * |[28:31] |PE7MFP |PE.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24046 */
<> 144:ef7eb2e8f9f7 24047 __IO uint32_t GPE_MFPL;
<> 144:ef7eb2e8f9f7 24048
<> 144:ef7eb2e8f9f7 24049 /**
<> 144:ef7eb2e8f9f7 24050 * GPE_MFPH
<> 144:ef7eb2e8f9f7 24051 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24052 * Offset: 0x54 Port E High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24053 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24054 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24055 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24056 * |[0:3] |PE8MFP |PE.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24057 * |[4:7] |PE9MFP |PE.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24058 * |[8:11] |PE10MFP |PE.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24059 * |[12:15] |PE11MFP |PE.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24060 * |[16:19] |PE12MFP |PE.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24061 * |[20:23] |PE13MFP |PE.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24062 * |[24:27] |PE14MFP |PE.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24063 * |[28:31] |PE15MFP |PE.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24064 */
<> 144:ef7eb2e8f9f7 24065 __IO uint32_t GPE_MFPH;
<> 144:ef7eb2e8f9f7 24066
<> 144:ef7eb2e8f9f7 24067 /**
<> 144:ef7eb2e8f9f7 24068 * GPF_MFPL
<> 144:ef7eb2e8f9f7 24069 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24070 * Offset: 0x58 Port F Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24071 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24072 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24073 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24074 * |[0:3] |PF0MFP |PF.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24075 * |[4:7] |PF1MFP |PF.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24076 * |[8:11] |PF2MFP |PF.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24077 * |[12:15] |PF3MFP |PF.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24078 * |[16:19] |PF4MFP |PF.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24079 * |[20:23] |PF5MFP |PF.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24080 * |[24:27] |PF6MFP |PF.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24081 * |[28:31] |PF7MFP |PF.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24082 */
<> 144:ef7eb2e8f9f7 24083 __IO uint32_t GPF_MFPL;
<> 144:ef7eb2e8f9f7 24084
<> 144:ef7eb2e8f9f7 24085 /**
<> 144:ef7eb2e8f9f7 24086 * GPF_MFPH
<> 144:ef7eb2e8f9f7 24087 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24088 * Offset: 0x5C Port F High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24089 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24090 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24091 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24092 * |[0:3] |PF8MFP |PF.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24093 * |[4:7] |PF9MFP |PF.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24094 * |[8:11] |PF10MFP |PF.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24095 * |[12:15] |PF11MFP |PF.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24096 * |[16:19] |PF12MFP |PF.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24097 * |[20:23] |PF13MFP |PF.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24098 * |[24:27] |PF14MFP |PF.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24099 * |[28:31] |PF15MFP |PF.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24100 */
<> 144:ef7eb2e8f9f7 24101 __IO uint32_t GPF_MFPH;
<> 144:ef7eb2e8f9f7 24102
<> 144:ef7eb2e8f9f7 24103 /**
<> 144:ef7eb2e8f9f7 24104 * GPG_MFPL
<> 144:ef7eb2e8f9f7 24105 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24106 * Offset: 0x60 Port G Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24107 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24108 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24109 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24110 * |[0:3] |PG0MFP |PG.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24111 * |[4:7] |PG1MFP |PG.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24112 * |[8:11] |PG2MFP |PG.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24113 * |[12:15] |PG3MFP |PG.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24114 * |[16:19] |PG4MFP |PG.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24115 * |[20:23] |PG5MFP |PG.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24116 * |[24:27] |PG6MFP |PG.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24117 * |[28:31] |PG7MFP |PG.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24118 */
<> 144:ef7eb2e8f9f7 24119 __IO uint32_t GPG_MFPL;
<> 144:ef7eb2e8f9f7 24120
<> 144:ef7eb2e8f9f7 24121 /**
<> 144:ef7eb2e8f9f7 24122 * GPG_MFPH
<> 144:ef7eb2e8f9f7 24123 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24124 * Offset: 0x64 Port G High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24125 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24126 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24127 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24128 * |[0:3] |PG8MFP |PG.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24129 * |[4:7] |PG9MFP |PG.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24130 * |[8:11] |PG10MFP |PG.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24131 * |[12:15] |PG11MFP |PG.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24132 * |[16:19] |PG12MFP |PG.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24133 * |[20:23] |PG13MFP |PG.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24134 * |[24:27] |PG14MFP |PG.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24135 * |[28:31] |PG15MFP |PG.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24136 */
<> 144:ef7eb2e8f9f7 24137 __IO uint32_t GPG_MFPH;
<> 144:ef7eb2e8f9f7 24138
<> 144:ef7eb2e8f9f7 24139 /**
<> 144:ef7eb2e8f9f7 24140 * GPH_MFPL
<> 144:ef7eb2e8f9f7 24141 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24142 * Offset: 0x68 Port H Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24143 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24144 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24145 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24146 * |[0:3] |PH0MFP |PH.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24147 * |[4:7] |PH1MFP |PH.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24148 * |[8:11] |PH2MFP |PH.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24149 * |[12:15] |PH3MFP |PH.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24150 * |[16:19] |PH4MFP |PH.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24151 * |[20:23] |PH5MFP |PH.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24152 * |[24:27] |PH6MFP |PH.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24153 * |[28:31] |PH7MFP |PH.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24154 */
<> 144:ef7eb2e8f9f7 24155 __IO uint32_t GPH_MFPL;
<> 144:ef7eb2e8f9f7 24156
<> 144:ef7eb2e8f9f7 24157 /**
<> 144:ef7eb2e8f9f7 24158 * GPH_MFPH
<> 144:ef7eb2e8f9f7 24159 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24160 * Offset: 0x6C Port H High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24161 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24162 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24163 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24164 * |[0:3] |PH8MFP |PH.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24165 * |[4:7] |PH9MFP |PH.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24166 * |[8:11] |PH10MFP |PH.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24167 * |[12:15] |PH11MFP |PH.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24168 * |[16:19] |PH12MFP |PH.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24169 * |[20:23] |PH13MFP |PH.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24170 * |[24:27] |PH14MFP |PH.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24171 * |[28:31] |PH15MFP |PH.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24172 */
<> 144:ef7eb2e8f9f7 24173 __IO uint32_t GPH_MFPH;
<> 144:ef7eb2e8f9f7 24174
<> 144:ef7eb2e8f9f7 24175 /**
<> 144:ef7eb2e8f9f7 24176 * GPI_MFPL
<> 144:ef7eb2e8f9f7 24177 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24178 * Offset: 0x70 Port I Low Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24179 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24180 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24181 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24182 * |[0:3] |PI0MFP |PI.0 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24183 * |[4:7] |PI1MFP |PI.1 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24184 * |[8:11] |PI2MFP |PI.2 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24185 * |[12:15] |PI3MFP |PI.3 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24186 * |[16:19] |PI4MFP |PI.4 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24187 * |[20:23] |PI5MFP |PI.5 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24188 * |[24:27] |PI6MFP |PI.6 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24189 * |[28:31] |PI7MFP |PI.7 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24190 */
<> 144:ef7eb2e8f9f7 24191 __IO uint32_t GPI_MFPL;
<> 144:ef7eb2e8f9f7 24192
<> 144:ef7eb2e8f9f7 24193 /**
<> 144:ef7eb2e8f9f7 24194 * GPI_MFPH
<> 144:ef7eb2e8f9f7 24195 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24196 * Offset: 0x74 Port I High Byte Multi-function Control Register
<> 144:ef7eb2e8f9f7 24197 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24198 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24199 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24200 * |[0:3] |PI8MFP |PI.8 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24201 * |[4:7] |PI9MFP |PI.9 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24202 * |[8:11] |PI10MFP |PI.10 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24203 * |[12:15] |PI11MFP |PI.11 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24204 * |[16:19] |PI12MFP |PI.12 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24205 * |[20:23] |PI13MFP |PI.13 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24206 * |[24:27] |PI14MFP |PI.14 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24207 * |[28:31] |PI15MFP |PI.15 Multi-function Pin Selection
<> 144:ef7eb2e8f9f7 24208 */
<> 144:ef7eb2e8f9f7 24209 __IO uint32_t GPI_MFPH;
<> 144:ef7eb2e8f9f7 24210 uint32_t RESERVE1[18];
<> 144:ef7eb2e8f9f7 24211
<> 144:ef7eb2e8f9f7 24212
<> 144:ef7eb2e8f9f7 24213 /**
<> 144:ef7eb2e8f9f7 24214 * SRAM_INTCTL
<> 144:ef7eb2e8f9f7 24215 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24216 * Offset: 0xC0 SRAM Failed Interrupt Enable Control Register
<> 144:ef7eb2e8f9f7 24217 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24218 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24219 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24220 * |[0] |PERRIEN |SRAM Parity Check Fail Interrupt Enable Control
<> 144:ef7eb2e8f9f7 24221 * | | |0 = SRAMF INT Disabled.
<> 144:ef7eb2e8f9f7 24222 * | | |1 = SRAMF INT Enabled when SRAM fail flag.
<> 144:ef7eb2e8f9f7 24223 */
<> 144:ef7eb2e8f9f7 24224 __IO uint32_t SRAM_INTCTL;
<> 144:ef7eb2e8f9f7 24225
<> 144:ef7eb2e8f9f7 24226 /**
<> 144:ef7eb2e8f9f7 24227 * SRAM_STATUS
<> 144:ef7eb2e8f9f7 24228 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24229 * Offset: 0xC4 SRAM Parity Check Error Flag
<> 144:ef7eb2e8f9f7 24230 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24231 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24232 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24233 * |[0] |PERRIF0 |SRAM Parity Check Fail Flag
<> 144:ef7eb2e8f9f7 24234 * | | |0 = No first 1 SRAM fail.
<> 144:ef7eb2e8f9f7 24235 * | | |1 = First SRAM Fail.
<> 144:ef7eb2e8f9f7 24236 * |[1] |PERRIF1 |SRAM Parity Check Fail Flag
<> 144:ef7eb2e8f9f7 24237 * | | |0 = 2nd SRAM fail.
<> 144:ef7eb2e8f9f7 24238 * | | |1 = 2nd SRAM Fail.
<> 144:ef7eb2e8f9f7 24239 */
<> 144:ef7eb2e8f9f7 24240 __IO uint32_t SRAM_STATUS;
<> 144:ef7eb2e8f9f7 24241
<> 144:ef7eb2e8f9f7 24242 /**
<> 144:ef7eb2e8f9f7 24243 * SRAM0_ERRADDR
<> 144:ef7eb2e8f9f7 24244 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24245 * Offset: 0xC8 SRAM Parity Check Error First Address1
<> 144:ef7eb2e8f9f7 24246 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24247 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24248 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24249 * |[0:31] |PERRADDR |First SRAM parity check fail address
<> 144:ef7eb2e8f9f7 24250 */
<> 144:ef7eb2e8f9f7 24251 __I uint32_t SRAM0_ERRADDR;
<> 144:ef7eb2e8f9f7 24252
<> 144:ef7eb2e8f9f7 24253 /**
<> 144:ef7eb2e8f9f7 24254 * SRAM1_ERRADDR
<> 144:ef7eb2e8f9f7 24255 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24256 * Offset: 0xCC SRAM Parity Check Error First Address2
<> 144:ef7eb2e8f9f7 24257 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24258 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24259 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24260 * |[0:31] |PERRADDR |2nd
<> 144:ef7eb2e8f9f7 24261 * | | |SRAM parity check fail address
<> 144:ef7eb2e8f9f7 24262 */
<> 144:ef7eb2e8f9f7 24263 __I uint32_t SRAM1_ERRADDR;
<> 144:ef7eb2e8f9f7 24264 uint32_t RESERVE2[8];
<> 144:ef7eb2e8f9f7 24265
<> 144:ef7eb2e8f9f7 24266
<> 144:ef7eb2e8f9f7 24267 /**
<> 144:ef7eb2e8f9f7 24268 * IRCTCTL
<> 144:ef7eb2e8f9f7 24269 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24270 * Offset: 0xF0 IRC Trim Control Register
<> 144:ef7eb2e8f9f7 24271 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24272 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24273 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24274 * |[0:1] |FREQSEL |Trim Frequency Selection
<> 144:ef7eb2e8f9f7 24275 * | | |This field indicates the target frequency of HIRC auto trim.
<> 144:ef7eb2e8f9f7 24276 * | | |If no any target frequency is selected (FREQSEL is 00), the HIRC auto trim function is disabled.
<> 144:ef7eb2e8f9f7 24277 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically.
<> 144:ef7eb2e8f9f7 24278 * | | |00 = Disable HIRC auto trim function.
<> 144:ef7eb2e8f9f7 24279 * | | |01 = Enable HIRC auto trim function and trim HIRC to 22.1184 MHz.
<> 144:ef7eb2e8f9f7 24280 * | | |10 = Enable HIRC auto trim function and trim HIRC to 24 MHz.
<> 144:ef7eb2e8f9f7 24281 * | | |11 = Reserved.
<> 144:ef7eb2e8f9f7 24282 * |[4:5] |LOOPSEL |Trim Calculation Loop
<> 144:ef7eb2e8f9f7 24283 * | | |This field defines that trim value calculation is based on how many 32.768 kHz clock.
<> 144:ef7eb2e8f9f7 24284 * | | |For example, if CALCLOOP is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 32.768 kHz clock.
<> 144:ef7eb2e8f9f7 24285 * | | |00 = Trim value calculation is based on average difference in 4 32.768 kHz clock.
<> 144:ef7eb2e8f9f7 24286 * | | |01 = Trim value calculation is based on average difference in 8 32.768 kHz clock.
<> 144:ef7eb2e8f9f7 24287 * | | |10 = Trim value calculation is based on average difference in 16 32.768 kHz clock.
<> 144:ef7eb2e8f9f7 24288 * | | |11 = Trim value calculation is based on average difference in 32 32.768 kHz clock.
<> 144:ef7eb2e8f9f7 24289 * |[6:7] |RETRYCNT |Trim Value Update Limitation Count
<> 144:ef7eb2e8f9f7 24290 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.
<> 144:ef7eb2e8f9f7 24291 * | | |Once the HIRC locked, the internal trim value update counter will be reset.
<> 144:ef7eb2e8f9f7 24292 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00.
<> 144:ef7eb2e8f9f7 24293 * | | |00 = Trim retry count limitation is 64.
<> 144:ef7eb2e8f9f7 24294 * | | |01 = Trim retry count limitation is 128.
<> 144:ef7eb2e8f9f7 24295 * | | |10 = Trim retry count limitation is 256.
<> 144:ef7eb2e8f9f7 24296 * | | |11 = Trim retry count limitation is 512.
<> 144:ef7eb2e8f9f7 24297 * |[8] |CESTOPEN |Clock Error Stop Enable Control
<> 144:ef7eb2e8f9f7 24298 * | | |0 = The trim operation is keep going if clock is inaccuracy.
<> 144:ef7eb2e8f9f7 24299 * | | |1 = The trim operation is stopped if clock is inaccuracy.
<> 144:ef7eb2e8f9f7 24300 */
<> 144:ef7eb2e8f9f7 24301 __IO uint32_t IRCTCTL;
<> 144:ef7eb2e8f9f7 24302
<> 144:ef7eb2e8f9f7 24303 /**
<> 144:ef7eb2e8f9f7 24304 * IRCTIEN
<> 144:ef7eb2e8f9f7 24305 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24306 * Offset: 0xF4 IRC Trim Interrupt Enable Control Register
<> 144:ef7eb2e8f9f7 24307 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24308 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24309 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24310 * |[1] |TFAILIEN |Trim Failure Interrupt Enable
<> 144:ef7eb2e8f9f7 24311 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL.
<> 144:ef7eb2e8f9f7 24312 * | | |If this bit is high and TFAILIF is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
<> 144:ef7eb2e8f9f7 24313 * | | |0 = Disable TFAILIF status to trigger an interrupt to CPU.
<> 144:ef7eb2e8f9f7 24314 * | | |1 = Enable TFAILIF status to trigger an interrupt to CPU.
<> 144:ef7eb2e8f9f7 24315 * |[2] |CLKEIEN |Clock Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 24316 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.
<> 144:ef7eb2e8f9f7 24317 * | | |If this bit is set to1, and CLKERRIF is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy.
<> 144:ef7eb2e8f9f7 24318 * | | |0 = Disable CLKERRIF status to trigger an interrupt to CPU.
<> 144:ef7eb2e8f9f7 24319 * | | |1 = Enable CLKERRIF status to trigger an interrupt to CPU.
<> 144:ef7eb2e8f9f7 24320 */
<> 144:ef7eb2e8f9f7 24321 __IO uint32_t IRCTIEN;
<> 144:ef7eb2e8f9f7 24322
<> 144:ef7eb2e8f9f7 24323 /**
<> 144:ef7eb2e8f9f7 24324 * IRCTISTS
<> 144:ef7eb2e8f9f7 24325 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24326 * Offset: 0xF8 IRC Trim Interrupt Status Register
<> 144:ef7eb2e8f9f7 24327 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24328 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24329 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24330 * |[0] |FREQLOCK |HIRC Frequency Lock Status
<> 144:ef7eb2e8f9f7 24331 * | | |This bit indicates the HIRC frequency is locked.
<> 144:ef7eb2e8f9f7 24332 * | | |This is a status bit and doesn't trigger any interrupt.
<> 144:ef7eb2e8f9f7 24333 * |[1] |TFAILIF |Trim Failure Interrupt Status
<> 144:ef7eb2e8f9f7 24334 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked.
<> 144:ef7eb2e8f9f7 24335 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically.
<> 144:ef7eb2e8f9f7 24336 * | | |If this bit is set and TFAILIEN is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached.
<> 144:ef7eb2e8f9f7 24337 * | | |Write 1 to clear this to 0.
<> 144:ef7eb2e8f9f7 24338 * | | |0 = Trim value update limitation count does not reach.
<> 144:ef7eb2e8f9f7 24339 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked.
<> 144:ef7eb2e8f9f7 24340 * |[2] |CLKERRIF |Clock Error Interrupt Status
<> 144:ef7eb2e8f9f7 24341 * | | |When the frequency of external 32.768 kHz low-speed crystal or HIRC is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy
<> 144:ef7eb2e8f9f7 24342 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL will be cleared to 00 by hardware automatically if CESTOPEN is set to 1.
<> 144:ef7eb2e8f9f7 24343 * | | |If this bit is set and CLKEIEN is high, an interrupt will be triggered to notify the clock frequency is inaccuracy.
<> 144:ef7eb2e8f9f7 24344 * | | |Write 1 to clear this to 0.
<> 144:ef7eb2e8f9f7 24345 * | | |0 = Clock frequency is accuracy.
<> 144:ef7eb2e8f9f7 24346 * | | |1 = Clock frequency is inaccuracy.
<> 144:ef7eb2e8f9f7 24347 */
<> 144:ef7eb2e8f9f7 24348 __IO uint32_t IRCTISTS;
<> 144:ef7eb2e8f9f7 24349 uint32_t RESERVE3[1];
<> 144:ef7eb2e8f9f7 24350
<> 144:ef7eb2e8f9f7 24351
<> 144:ef7eb2e8f9f7 24352 /**
<> 144:ef7eb2e8f9f7 24353 * REGLCTL
<> 144:ef7eb2e8f9f7 24354 * ===================================================================================================
<> 144:ef7eb2e8f9f7 24355 * Offset: 0x100 Register Write-Protection Control Register
<> 144:ef7eb2e8f9f7 24356 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 24357 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 24358 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 24359 * |[0] |REGLCTL |Register Write-Protection Disable Index (Read Only)
<> 144:ef7eb2e8f9f7 24360 * | | |0 = Write-protection Enabled for writing protected registers.
<> 144:ef7eb2e8f9f7 24361 * | | |Any write to the protected register is ignored.
<> 144:ef7eb2e8f9f7 24362 * | | |1 = Write-protection Disabled for writing protected registers.
<> 144:ef7eb2e8f9f7 24363 * | | |The Protected registers are:
<> 144:ef7eb2e8f9f7 24364 * | | |SYS_IPRST0: address 0x4000_0008
<> 144:ef7eb2e8f9f7 24365 * | | |SYS_BODCTL: address 0x4000_0018
<> 144:ef7eb2e8f9f7 24366 * | | |SYS_PORCTL: address 0x4000_0024
<> 144:ef7eb2e8f9f7 24367 * | | |PWRCON: address 0x4000_0200 (bit[6] is not protected for power wake-up interrupt clear)
<> 144:ef7eb2e8f9f7 24368 * | | |APBCLK bit[0]: address 0x4000_0208 (bit[0] is watchdog clock enable)
<> 144:ef7eb2e8f9f7 24369 * | | |CLKSEL0: address 0x4000_0210 (for HCLK and CPU STCLK clock source select)
<> 144:ef7eb2e8f9f7 24370 * | | |CLKSEL1 bit[1:0]: address 0x4000_0214 (for watchdog clock source select)
<> 144:ef7eb2e8f9f7 24371 * | | |NMI_SEL]: address 0x4000_0300 (for NMI source select)
<> 144:ef7eb2e8f9f7 24372 * | | |ISPCON: address 0x4000_5000 (Flash ISP Control register)
<> 144:ef7eb2e8f9f7 24373 * | | |ISPTRG: address 0x4000_5010 (ISP Trigger Control register)
<> 144:ef7eb2e8f9f7 24374 * | | |WTCR: address 0x4004_0000
<> 144:ef7eb2e8f9f7 24375 * | | |FATCON: address 0x4000_5018
<> 144:ef7eb2e8f9f7 24376 * | | |TAMPER: address 0x400E_1000
<> 144:ef7eb2e8f9f7 24377 * |[0:7] |SYS_REGLCTL|Register Write-Protection Code (Write Only)
<> 144:ef7eb2e8f9f7 24378 * | | |Some registers have write-protection function.
<> 144:ef7eb2e8f9f7 24379 * | | |Writing these registers have to disable the protected function by writing the sequence value "59h", "16h", "88h" to this field.
<> 144:ef7eb2e8f9f7 24380 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
<> 144:ef7eb2e8f9f7 24381 */
<> 144:ef7eb2e8f9f7 24382 __IO uint32_t REGLCTL;
<> 144:ef7eb2e8f9f7 24383
<> 144:ef7eb2e8f9f7 24384 } SYS_T;
<> 144:ef7eb2e8f9f7 24385
<> 144:ef7eb2e8f9f7 24386 /**
<> 144:ef7eb2e8f9f7 24387 @addtogroup SYS_CONST SYS Bit Field Definition
<> 144:ef7eb2e8f9f7 24388 Constant Definitions for SYS Controller
<> 144:ef7eb2e8f9f7 24389 @{ */
<> 144:ef7eb2e8f9f7 24390
<> 144:ef7eb2e8f9f7 24391 #define SYS_PDID_SYS_PDID_Pos (0) /*!< SYS PDID: SYS_PDID Position */
<> 144:ef7eb2e8f9f7 24392 #define SYS_PDID_SYS_PDID_Msk (0xfffffffful << SYS_PDID_SYS_PDID_Pos) /*!< SYS PDID: SYS_PDID Mask */
<> 144:ef7eb2e8f9f7 24393
<> 144:ef7eb2e8f9f7 24394 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS RSTSTS: PORF Position */
<> 144:ef7eb2e8f9f7 24395 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS RSTSTS: PORF Mask */
<> 144:ef7eb2e8f9f7 24396
<> 144:ef7eb2e8f9f7 24397 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS RSTSTS: PINRF Position */
<> 144:ef7eb2e8f9f7 24398 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS RSTSTS: PINRF Mask */
<> 144:ef7eb2e8f9f7 24399
<> 144:ef7eb2e8f9f7 24400 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS RSTSTS: WDTRF Position */
<> 144:ef7eb2e8f9f7 24401 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS RSTSTS: WDTRF Mask */
<> 144:ef7eb2e8f9f7 24402
<> 144:ef7eb2e8f9f7 24403 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS RSTSTS: LVRF Position */
<> 144:ef7eb2e8f9f7 24404 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS RSTSTS: LVRF Mask */
<> 144:ef7eb2e8f9f7 24405
<> 144:ef7eb2e8f9f7 24406 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS RSTSTS: BODRF Position */
<> 144:ef7eb2e8f9f7 24407 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS RSTSTS: BODRF Mask */
<> 144:ef7eb2e8f9f7 24408
<> 144:ef7eb2e8f9f7 24409 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS RSTSTS: SYSRF Position */
<> 144:ef7eb2e8f9f7 24410 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS RSTSTS: SYSRF Mask */
<> 144:ef7eb2e8f9f7 24411
<> 144:ef7eb2e8f9f7 24412 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS RSTSTS: CPURF Position */
<> 144:ef7eb2e8f9f7 24413 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS RSTSTS: CPURF Mask */
<> 144:ef7eb2e8f9f7 24414
<> 144:ef7eb2e8f9f7 24415 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS IPRST0: CHIPRST Position */
<> 144:ef7eb2e8f9f7 24416 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS IPRST0: CHIPRST Mask */
<> 144:ef7eb2e8f9f7 24417
<> 144:ef7eb2e8f9f7 24418 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS IPRST0: CPURST Position */
<> 144:ef7eb2e8f9f7 24419 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS IPRST0: CPURST Mask */
<> 144:ef7eb2e8f9f7 24420
<> 144:ef7eb2e8f9f7 24421 #define SYS_IPRST0_PDMARST_Pos (2) /*!< SYS IPRST0: PDMARST Position */
<> 144:ef7eb2e8f9f7 24422 #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) /*!< SYS IPRST0: PDMARST Mask */
<> 144:ef7eb2e8f9f7 24423
<> 144:ef7eb2e8f9f7 24424 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS IPRST0: EBIRST Position */
<> 144:ef7eb2e8f9f7 24425 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS IPRST0: EBIRST Mask */
<> 144:ef7eb2e8f9f7 24426
<> 144:ef7eb2e8f9f7 24427 #define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS IPRST0: USBHRST Position */
<> 144:ef7eb2e8f9f7 24428 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS IPRST0: USBHRST Mask */
<> 144:ef7eb2e8f9f7 24429
<> 144:ef7eb2e8f9f7 24430 #define SYS_IPRST0_SDHRST_Pos (5) /*!< SYS IPRST0: SDHRST Position */
<> 144:ef7eb2e8f9f7 24431 #define SYS_IPRST0_SDHRST_Msk (0x1ul << SYS_IPRST0_SDHRST_Pos) /*!< SYS IPRST0: SDHRST Mask */
<> 144:ef7eb2e8f9f7 24432
<> 144:ef7eb2e8f9f7 24433 #define SYS_IPRST0_SDHOST_RST_Pos (6) /*!< SYS IPRST0: SDHOST_RST Position */
<> 144:ef7eb2e8f9f7 24434 #define SYS_IPRST0_SDHOST_RST_Msk (0x1ul << SYS_IPRST0_SDHOST_RST_Pos) /*!< SYS IPRST0: SDHOST_RST Mask */
<> 144:ef7eb2e8f9f7 24435
<> 144:ef7eb2e8f9f7 24436 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS IPRST0: CRCRST Position */
<> 144:ef7eb2e8f9f7 24437 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS IPRST0: CRCRST Mask */
<> 144:ef7eb2e8f9f7 24438
<> 144:ef7eb2e8f9f7 24439 #define SYS_IPRST0_CAPRST_Pos (8) /*!< SYS IPRST0: CAPRST Position */
<> 144:ef7eb2e8f9f7 24440 #define SYS_IPRST0_CAPRST_Msk (0x1ul << SYS_IPRST0_CAPRST_Pos) /*!< SYS IPRST0: CAPRST Mask */
<> 144:ef7eb2e8f9f7 24441
<> 144:ef7eb2e8f9f7 24442 #define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS IPRST0: CRPTRST Position */
<> 144:ef7eb2e8f9f7 24443 #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS IPRST0: CRPTRST Mask */
<> 144:ef7eb2e8f9f7 24444
<> 144:ef7eb2e8f9f7 24445 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS IPRST1: GPIORST Position */
<> 144:ef7eb2e8f9f7 24446 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS IPRST1: GPIORST Mask */
<> 144:ef7eb2e8f9f7 24447
<> 144:ef7eb2e8f9f7 24448 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS IPRST1: TMR0RST Position */
<> 144:ef7eb2e8f9f7 24449 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS IPRST1: TMR0RST Mask */
<> 144:ef7eb2e8f9f7 24450
<> 144:ef7eb2e8f9f7 24451 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS IPRST1: TMR1RST Position */
<> 144:ef7eb2e8f9f7 24452 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS IPRST1: TMR1RST Mask */
<> 144:ef7eb2e8f9f7 24453
<> 144:ef7eb2e8f9f7 24454 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS IPRST1: TMR2RST Position */
<> 144:ef7eb2e8f9f7 24455 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS IPRST1: TMR2RST Mask */
<> 144:ef7eb2e8f9f7 24456
<> 144:ef7eb2e8f9f7 24457 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS IPRST1: TMR3RST Position */
<> 144:ef7eb2e8f9f7 24458 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS IPRST1: TMR3RST Mask */
<> 144:ef7eb2e8f9f7 24459
<> 144:ef7eb2e8f9f7 24460 #define SYS_IPRST1_ACMPRST_Pos (7) /*!< SYS IPRST1: ACMPRST Position */
<> 144:ef7eb2e8f9f7 24461 #define SYS_IPRST1_ACMPRST_Msk (0x1ul << SYS_IPRST1_ACMPRST_Pos) /*!< SYS IPRST1: ACMPRST Mask */
<> 144:ef7eb2e8f9f7 24462
<> 144:ef7eb2e8f9f7 24463 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS IPRST1: I2C0RST Position */
<> 144:ef7eb2e8f9f7 24464 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS IPRST1: I2C0RST Mask */
<> 144:ef7eb2e8f9f7 24465
<> 144:ef7eb2e8f9f7 24466 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS IPRST1: I2C1RST Position */
<> 144:ef7eb2e8f9f7 24467 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS IPRST1: I2C1RST Mask */
<> 144:ef7eb2e8f9f7 24468
<> 144:ef7eb2e8f9f7 24469 #define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS IPRST1: I2C2RST Position */
<> 144:ef7eb2e8f9f7 24470 #define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS IPRST1: I2C2RST Mask */
<> 144:ef7eb2e8f9f7 24471
<> 144:ef7eb2e8f9f7 24472 #define SYS_IPRST1_I2C3RST_Pos (11) /*!< SYS IPRST1: I2C3RST Position */
<> 144:ef7eb2e8f9f7 24473 #define SYS_IPRST1_I2C3RST_Msk (0x1ul << SYS_IPRST1_I2C3RST_Pos) /*!< SYS IPRST1: I2C3RST Mask */
<> 144:ef7eb2e8f9f7 24474
<> 144:ef7eb2e8f9f7 24475 #define SYS_IPRST1_SPI0RST_Pos (12) /*!< SYS IPRST1: SPI0RST Position */
<> 144:ef7eb2e8f9f7 24476 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS IPRST1: SPI0RST Mask */
<> 144:ef7eb2e8f9f7 24477
<> 144:ef7eb2e8f9f7 24478 #define SYS_IPRST1_SPI1RST_Pos (13) /*!< SYS IPRST1: SPI1RST Position */
<> 144:ef7eb2e8f9f7 24479 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS IPRST1: SPI1RST Mask */
<> 144:ef7eb2e8f9f7 24480
<> 144:ef7eb2e8f9f7 24481 #define SYS_IPRST1_SPI2RST_Pos (14) /*!< SYS IPRST1: SPI2RST Position */
<> 144:ef7eb2e8f9f7 24482 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS IPRST1: SPI2RST Mask */
<> 144:ef7eb2e8f9f7 24483
<> 144:ef7eb2e8f9f7 24484 #define SYS_IPRST1_SPI3RST_Pos (15) /*!< SYS IPRST1: SPI3RST Position */
<> 144:ef7eb2e8f9f7 24485 #define SYS_IPRST1_SPI3RST_Msk (0x1ul << SYS_IPRST1_SPI3RST_Pos) /*!< SYS IPRST1: SPI3RST Mask */
<> 144:ef7eb2e8f9f7 24486
<> 144:ef7eb2e8f9f7 24487 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS IPRST1: UART0RST Position */
<> 144:ef7eb2e8f9f7 24488 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS IPRST1: UART0RST Mask */
<> 144:ef7eb2e8f9f7 24489
<> 144:ef7eb2e8f9f7 24490 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS IPRST1: UART1RST Position */
<> 144:ef7eb2e8f9f7 24491 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS IPRST1: UART1RST Mask */
<> 144:ef7eb2e8f9f7 24492
<> 144:ef7eb2e8f9f7 24493 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS IPRST1: UART2RST Position */
<> 144:ef7eb2e8f9f7 24494 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS IPRST1: UART2RST Mask */
<> 144:ef7eb2e8f9f7 24495
<> 144:ef7eb2e8f9f7 24496 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS IPRST1: UART3RST Position */
<> 144:ef7eb2e8f9f7 24497 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS IPRST1: UART3RST Mask */
<> 144:ef7eb2e8f9f7 24498
<> 144:ef7eb2e8f9f7 24499 #define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS IPRST1: UART4RST Position */
<> 144:ef7eb2e8f9f7 24500 #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS IPRST1: UART4RST Mask */
<> 144:ef7eb2e8f9f7 24501
<> 144:ef7eb2e8f9f7 24502 #define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS IPRST1: UART5RST Position */
<> 144:ef7eb2e8f9f7 24503 #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS IPRST1: UART5RST Mask */
<> 144:ef7eb2e8f9f7 24504
<> 144:ef7eb2e8f9f7 24505 #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS IPRST1: CAN0RST Position */
<> 144:ef7eb2e8f9f7 24506 #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS IPRST1: CAN0RST Mask */
<> 144:ef7eb2e8f9f7 24507
<> 144:ef7eb2e8f9f7 24508 #define SYS_IPRST1_CAN1RST_Pos (25) /*!< SYS IPRST1: CAN1RST Position */
<> 144:ef7eb2e8f9f7 24509 #define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) /*!< SYS IPRST1: CAN1RST Mask */
<> 144:ef7eb2e8f9f7 24510
<> 144:ef7eb2e8f9f7 24511 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS IPRST1: USBDRST Position */
<> 144:ef7eb2e8f9f7 24512 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS IPRST1: USBDRST Mask */
<> 144:ef7eb2e8f9f7 24513
<> 144:ef7eb2e8f9f7 24514 #define SYS_IPRST1_ADCRST_Pos (28) /*!< SYS IPRST1: ADCRST Position */
<> 144:ef7eb2e8f9f7 24515 #define SYS_IPRST1_ADCRST_Msk (0x1ul << SYS_IPRST1_ADCRST_Pos) /*!< SYS IPRST1: ADCRST Mask */
<> 144:ef7eb2e8f9f7 24516
<> 144:ef7eb2e8f9f7 24517 #define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS IPRST1: I2SRST Position */
<> 144:ef7eb2e8f9f7 24518 #define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS IPRST1: I2SRST Mask */
<> 144:ef7eb2e8f9f7 24519
<> 144:ef7eb2e8f9f7 24520 #define SYS_IPRST1_I2S1RST_Pos (30) /*!< SYS IPRST1: I2S1RST Position */
<> 144:ef7eb2e8f9f7 24521 #define SYS_IPRST1_I2S1RST_Msk (0x1ul << SYS_IPRST1_I2S1RST_Pos) /*!< SYS IPRST1: I2S1RST Mask */
<> 144:ef7eb2e8f9f7 24522
<> 144:ef7eb2e8f9f7 24523 #define SYS_IPRST1_PS2RST_Pos (31) /*!< SYS IPRST1: PS2RST Position */
<> 144:ef7eb2e8f9f7 24524 #define SYS_IPRST1_PS2RST_Msk (0x1ul << SYS_IPRST1_PS2RST_Pos) /*!< SYS IPRST1: PS2RST Mask */
<> 144:ef7eb2e8f9f7 24525
<> 144:ef7eb2e8f9f7 24526 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS IPRST2: SC0RST Position */
<> 144:ef7eb2e8f9f7 24527 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS IPRST2: SC0RST Mask */
<> 144:ef7eb2e8f9f7 24528
<> 144:ef7eb2e8f9f7 24529 #define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS IPRST2: SC1RST Position */
<> 144:ef7eb2e8f9f7 24530 #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS IPRST2: SC1RST Mask */
<> 144:ef7eb2e8f9f7 24531
<> 144:ef7eb2e8f9f7 24532 #define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS IPRST2: SC2RST Position */
<> 144:ef7eb2e8f9f7 24533 #define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS IPRST2: SC2RST Mask */
<> 144:ef7eb2e8f9f7 24534
<> 144:ef7eb2e8f9f7 24535 #define SYS_IPRST2_SC3RST_Pos (3) /*!< SYS IPRST2: SC3RST Position */
<> 144:ef7eb2e8f9f7 24536 #define SYS_IPRST2_SC3RST_Msk (0x1ul << SYS_IPRST2_SC3RST_Pos) /*!< SYS IPRST2: SC3RST Mask */
<> 144:ef7eb2e8f9f7 24537
<> 144:ef7eb2e8f9f7 24538 #define SYS_IPRST2_SC4RST_Pos (4) /*!< SYS IPRST2: SC4RST Position */
<> 144:ef7eb2e8f9f7 24539 #define SYS_IPRST2_SC4RST_Msk (0x1ul << SYS_IPRST2_SC4RST_Pos) /*!< SYS IPRST2: SC4RST Mask */
<> 144:ef7eb2e8f9f7 24540
<> 144:ef7eb2e8f9f7 24541 #define SYS_IPRST2_SC5RST_Pos (5) /*!< SYS IPRST2: SC5RST Position */
<> 144:ef7eb2e8f9f7 24542 #define SYS_IPRST2_SC5RST_Msk (0x1ul << SYS_IPRST2_SC5RST_Pos) /*!< SYS IPRST2: SC5RST Mask */
<> 144:ef7eb2e8f9f7 24543
<> 144:ef7eb2e8f9f7 24544 #define SYS_IPRST2_I2C4RST_Pos (8) /*!< SYS IPRST2: I2C4RST Position */
<> 144:ef7eb2e8f9f7 24545 #define SYS_IPRST2_I2C4RST_Msk (0x1ul << SYS_IPRST2_I2C4RST_Pos) /*!< SYS IPRST2: I2C4RST Mask */
<> 144:ef7eb2e8f9f7 24546
<> 144:ef7eb2e8f9f7 24547 #define SYS_IPRST2_PWM0RST_Pos (16) /*!< SYS IPRST2: PWM0RST Position */
<> 144:ef7eb2e8f9f7 24548 #define SYS_IPRST2_PWM0RST_Msk (0x1ul << SYS_IPRST2_PWM0RST_Pos) /*!< SYS IPRST2: PWM0RST Mask */
<> 144:ef7eb2e8f9f7 24549
<> 144:ef7eb2e8f9f7 24550 #define SYS_IPRST2_PWM1RST_Pos (17) /*!< SYS IPRST2: PWM1RST Position */
<> 144:ef7eb2e8f9f7 24551 #define SYS_IPRST2_PWM1RST_Msk (0x1ul << SYS_IPRST2_PWM1RST_Pos) /*!< SYS IPRST2: PWM1RST Mask */
<> 144:ef7eb2e8f9f7 24552
<> 144:ef7eb2e8f9f7 24553 #define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS IPRST2: QEI0RST Position */
<> 144:ef7eb2e8f9f7 24554 #define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS IPRST2: QEI0RST Mask */
<> 144:ef7eb2e8f9f7 24555
<> 144:ef7eb2e8f9f7 24556 #define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS IPRST2: QEI1RST Position */
<> 144:ef7eb2e8f9f7 24557 #define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS IPRST2: QEI1RST Mask */
<> 144:ef7eb2e8f9f7 24558
<> 144:ef7eb2e8f9f7 24559 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS BODCTL: BODEN Position */
<> 144:ef7eb2e8f9f7 24560 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS BODCTL: BODEN Mask */
<> 144:ef7eb2e8f9f7 24561
<> 144:ef7eb2e8f9f7 24562 #define SYS_BODCTL_BODVL_Pos (1) /*!< SYS BODCTL: BODVL Position */
<> 144:ef7eb2e8f9f7 24563 #define SYS_BODCTL_BODVL_Msk (0x3ul << SYS_BODCTL_BODVL_Pos) /*!< SYS BODCTL: BODVL Mask */
<> 144:ef7eb2e8f9f7 24564
<> 144:ef7eb2e8f9f7 24565 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS BODCTL: BODRSTEN Position */
<> 144:ef7eb2e8f9f7 24566 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS BODCTL: BODRSTEN Mask */
<> 144:ef7eb2e8f9f7 24567
<> 144:ef7eb2e8f9f7 24568 #define SYS_BODCTL_BODINTF_Pos (4) /*!< SYS BODCTL: BODINTF Position */
<> 144:ef7eb2e8f9f7 24569 #define SYS_BODCTL_BODINTF_Msk (0x1ul << SYS_BODCTL_BODINTF_Pos) /*!< SYS BODCTL: BODINTF Mask */
<> 144:ef7eb2e8f9f7 24570
<> 144:ef7eb2e8f9f7 24571 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS BODCTL: BODLPM Position */
<> 144:ef7eb2e8f9f7 24572 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS BODCTL: BODLPM Mask */
<> 144:ef7eb2e8f9f7 24573
<> 144:ef7eb2e8f9f7 24574 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS BODCTL: BODOUT Position */
<> 144:ef7eb2e8f9f7 24575 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS BODCTL: BODOUT Mask */
<> 144:ef7eb2e8f9f7 24576
<> 144:ef7eb2e8f9f7 24577 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS BODCTL: LVREN Position */
<> 144:ef7eb2e8f9f7 24578 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS BODCTL: LVREN Mask */
<> 144:ef7eb2e8f9f7 24579
<> 144:ef7eb2e8f9f7 24580 #define SYS_TEMPCTL_VTEMPEN_Pos (0) /*!< SYS TEMPCTL: VTEMPEN Position */
<> 144:ef7eb2e8f9f7 24581 #define SYS_TEMPCTL_VTEMPEN_Msk (0x1ul << SYS_TEMPCTL_VTEMPEN_Pos) /*!< SYS TEMPCTL: VTEMPEN Mask */
<> 144:ef7eb2e8f9f7 24582
<> 144:ef7eb2e8f9f7 24583 #define SYS_VCID_VCID_Pos (0) /*!< SYS VCID: VCID Position */
<> 144:ef7eb2e8f9f7 24584 #define SYS_VCID_VCID_Msk (0xfffful << SYS_VCID_VCID_Pos) /*!< SYS VCID: VCID Mask */
<> 144:ef7eb2e8f9f7 24585
<> 144:ef7eb2e8f9f7 24586 #define SYS_PORCTL_POROFF_Pos (0) /*!< SYS PORCTL: POROFF Position */
<> 144:ef7eb2e8f9f7 24587 #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) /*!< SYS PORCTL: POROFF Mask */
<> 144:ef7eb2e8f9f7 24588
<> 144:ef7eb2e8f9f7 24589 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS VREFCTL: VREFCTL Position */
<> 144:ef7eb2e8f9f7 24590 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS VREFCTL: VREFCTL Mask */
<> 144:ef7eb2e8f9f7 24591
<> 144:ef7eb2e8f9f7 24592 #define SYS_VREFCTL_ADCMODESEL_Pos (8) /*!< SYS VREFCTL: ADCMODESEL Position */
<> 144:ef7eb2e8f9f7 24593 #define SYS_VREFCTL_ADCMODESEL_Msk (0x1ul << SYS_VREFCTL_ADCMODESEL_Pos) /*!< SYS VREFCTL: ADCMODESEL Mask */
<> 144:ef7eb2e8f9f7 24594
<> 144:ef7eb2e8f9f7 24595 #define SYS_VREFCTL_PWMSYNCMODE_Pos (9) /*!< SYS VREFCTL: PWMSYNCMODE Position */
<> 144:ef7eb2e8f9f7 24596 #define SYS_VREFCTL_PWMSYNCMODE_Msk (0x1ul << SYS_VREFCTL_PWMSYNCMODE_Pos) /*!< SYS VREFCTL: PWMSYNCMODE Mask */
<> 144:ef7eb2e8f9f7 24597
<> 144:ef7eb2e8f9f7 24598 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS USBPHY: USBROLE Position */
<> 144:ef7eb2e8f9f7 24599 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS USBPHY: USBROLE Mask */
<> 144:ef7eb2e8f9f7 24600
<> 144:ef7eb2e8f9f7 24601 #define SYS_USBPHY_LDO33EN_Pos (8) /*!< SYS USBPHY: LDO33EN Position */
<> 144:ef7eb2e8f9f7 24602 #define SYS_USBPHY_LDO33EN_Msk (0x1ul << SYS_USBPHY_LDO33EN_Pos) /*!< SYS USBPHY: LDO33EN Mask */
<> 144:ef7eb2e8f9f7 24603
<> 144:ef7eb2e8f9f7 24604 #define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS GPA_MFPL: PA0MFP Position */
<> 144:ef7eb2e8f9f7 24605 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS GPA_MFPL: PA0MFP Mask */
<> 144:ef7eb2e8f9f7 24606
<> 144:ef7eb2e8f9f7 24607 #define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS GPA_MFPL: PA1MFP Position */
<> 144:ef7eb2e8f9f7 24608 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS GPA_MFPL: PA1MFP Mask */
<> 144:ef7eb2e8f9f7 24609
<> 144:ef7eb2e8f9f7 24610 #define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS GPA_MFPL: PA2MFP Position */
<> 144:ef7eb2e8f9f7 24611 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS GPA_MFPL: PA2MFP Mask */
<> 144:ef7eb2e8f9f7 24612
<> 144:ef7eb2e8f9f7 24613 #define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS GPA_MFPL: PA3MFP Position */
<> 144:ef7eb2e8f9f7 24614 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS GPA_MFPL: PA3MFP Mask */
<> 144:ef7eb2e8f9f7 24615
<> 144:ef7eb2e8f9f7 24616 #define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS GPA_MFPL: PA4MFP Position */
<> 144:ef7eb2e8f9f7 24617 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS GPA_MFPL: PA4MFP Mask */
<> 144:ef7eb2e8f9f7 24618
<> 144:ef7eb2e8f9f7 24619 #define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS GPA_MFPL: PA5MFP Position */
<> 144:ef7eb2e8f9f7 24620 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS GPA_MFPL: PA5MFP Mask */
<> 144:ef7eb2e8f9f7 24621
<> 144:ef7eb2e8f9f7 24622 #define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS GPA_MFPL: PA6MFP Position */
<> 144:ef7eb2e8f9f7 24623 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS GPA_MFPL: PA6MFP Mask */
<> 144:ef7eb2e8f9f7 24624
<> 144:ef7eb2e8f9f7 24625 #define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS GPA_MFPL: PA7MFP Position */
<> 144:ef7eb2e8f9f7 24626 #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS GPA_MFPL: PA7MFP Mask */
<> 144:ef7eb2e8f9f7 24627
<> 144:ef7eb2e8f9f7 24628 #define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS GPA_MFPH: PA8MFP Position */
<> 144:ef7eb2e8f9f7 24629 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS GPA_MFPH: PA8MFP Mask */
<> 144:ef7eb2e8f9f7 24630
<> 144:ef7eb2e8f9f7 24631 #define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS GPA_MFPH: PA9MFP Position */
<> 144:ef7eb2e8f9f7 24632 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS GPA_MFPH: PA9MFP Mask */
<> 144:ef7eb2e8f9f7 24633
<> 144:ef7eb2e8f9f7 24634 #define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS GPA_MFPH: PA10MFP Position */
<> 144:ef7eb2e8f9f7 24635 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS GPA_MFPH: PA10MFP Mask */
<> 144:ef7eb2e8f9f7 24636
<> 144:ef7eb2e8f9f7 24637 #define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS GPA_MFPH: PA11MFP Position */
<> 144:ef7eb2e8f9f7 24638 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS GPA_MFPH: PA11MFP Mask */
<> 144:ef7eb2e8f9f7 24639
<> 144:ef7eb2e8f9f7 24640 #define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS GPA_MFPH: PA12MFP Position */
<> 144:ef7eb2e8f9f7 24641 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS GPA_MFPH: PA12MFP Mask */
<> 144:ef7eb2e8f9f7 24642
<> 144:ef7eb2e8f9f7 24643 #define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS GPA_MFPH: PA13MFP Position */
<> 144:ef7eb2e8f9f7 24644 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS GPA_MFPH: PA13MFP Mask */
<> 144:ef7eb2e8f9f7 24645
<> 144:ef7eb2e8f9f7 24646 #define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS GPA_MFPH: PA14MFP Position */
<> 144:ef7eb2e8f9f7 24647 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS GPA_MFPH: PA14MFP Mask */
<> 144:ef7eb2e8f9f7 24648
<> 144:ef7eb2e8f9f7 24649 #define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS GPA_MFPH: PA15MFP Position */
<> 144:ef7eb2e8f9f7 24650 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS GPA_MFPH: PA15MFP Mask */
<> 144:ef7eb2e8f9f7 24651
<> 144:ef7eb2e8f9f7 24652 #define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS GPB_MFPL: PB0MFP Position */
<> 144:ef7eb2e8f9f7 24653 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS GPB_MFPL: PB0MFP Mask */
<> 144:ef7eb2e8f9f7 24654
<> 144:ef7eb2e8f9f7 24655 #define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS GPB_MFPL: PB1MFP Position */
<> 144:ef7eb2e8f9f7 24656 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS GPB_MFPL: PB1MFP Mask */
<> 144:ef7eb2e8f9f7 24657
<> 144:ef7eb2e8f9f7 24658 #define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS GPB_MFPL: PB2MFP Position */
<> 144:ef7eb2e8f9f7 24659 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS GPB_MFPL: PB2MFP Mask */
<> 144:ef7eb2e8f9f7 24660
<> 144:ef7eb2e8f9f7 24661 #define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS GPB_MFPL: PB3MFP Position */
<> 144:ef7eb2e8f9f7 24662 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS GPB_MFPL: PB3MFP Mask */
<> 144:ef7eb2e8f9f7 24663
<> 144:ef7eb2e8f9f7 24664 #define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS GPB_MFPL: PB4MFP Position */
<> 144:ef7eb2e8f9f7 24665 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS GPB_MFPL: PB4MFP Mask */
<> 144:ef7eb2e8f9f7 24666
<> 144:ef7eb2e8f9f7 24667 #define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS GPB_MFPL: PB5MFP Position */
<> 144:ef7eb2e8f9f7 24668 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS GPB_MFPL: PB5MFP Mask */
<> 144:ef7eb2e8f9f7 24669
<> 144:ef7eb2e8f9f7 24670 #define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS GPB_MFPL: PB6MFP Position */
<> 144:ef7eb2e8f9f7 24671 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS GPB_MFPL: PB6MFP Mask */
<> 144:ef7eb2e8f9f7 24672
<> 144:ef7eb2e8f9f7 24673 #define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS GPB_MFPL: PB7MFP Position */
<> 144:ef7eb2e8f9f7 24674 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS GPB_MFPL: PB7MFP Mask */
<> 144:ef7eb2e8f9f7 24675
<> 144:ef7eb2e8f9f7 24676 #define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS GPB_MFPH: PB8MFP Position */
<> 144:ef7eb2e8f9f7 24677 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS GPB_MFPH: PB8MFP Mask */
<> 144:ef7eb2e8f9f7 24678
<> 144:ef7eb2e8f9f7 24679 #define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS GPB_MFPH: PB9MFP Position */
<> 144:ef7eb2e8f9f7 24680 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS GPB_MFPH: PB9MFP Mask */
<> 144:ef7eb2e8f9f7 24681
<> 144:ef7eb2e8f9f7 24682 #define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS GPB_MFPH: PB10MFP Position */
<> 144:ef7eb2e8f9f7 24683 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS GPB_MFPH: PB10MFP Mask */
<> 144:ef7eb2e8f9f7 24684
<> 144:ef7eb2e8f9f7 24685 #define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS GPB_MFPH: PB11MFP Position */
<> 144:ef7eb2e8f9f7 24686 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS GPB_MFPH: PB11MFP Mask */
<> 144:ef7eb2e8f9f7 24687
<> 144:ef7eb2e8f9f7 24688 #define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS GPB_MFPH: PB12MFP Position */
<> 144:ef7eb2e8f9f7 24689 #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS GPB_MFPH: PB12MFP Mask */
<> 144:ef7eb2e8f9f7 24690
<> 144:ef7eb2e8f9f7 24691 #define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS GPB_MFPH: PB13MFP Position */
<> 144:ef7eb2e8f9f7 24692 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS GPB_MFPH: PB13MFP Mask */
<> 144:ef7eb2e8f9f7 24693
<> 144:ef7eb2e8f9f7 24694 #define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS GPB_MFPH: PB14MFP Position */
<> 144:ef7eb2e8f9f7 24695 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS GPB_MFPH: PB14MFP Mask */
<> 144:ef7eb2e8f9f7 24696
<> 144:ef7eb2e8f9f7 24697 #define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS GPB_MFPH: PB15MFP Position */
<> 144:ef7eb2e8f9f7 24698 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS GPB_MFPH: PB15MFP Mask */
<> 144:ef7eb2e8f9f7 24699
<> 144:ef7eb2e8f9f7 24700 #define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS GPC_MFPL: PC0MFP Position */
<> 144:ef7eb2e8f9f7 24701 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS GPC_MFPL: PC0MFP Mask */
<> 144:ef7eb2e8f9f7 24702
<> 144:ef7eb2e8f9f7 24703 #define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS GPC_MFPL: PC1MFP Position */
<> 144:ef7eb2e8f9f7 24704 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS GPC_MFPL: PC1MFP Mask */
<> 144:ef7eb2e8f9f7 24705
<> 144:ef7eb2e8f9f7 24706 #define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS GPC_MFPL: PC2MFP Position */
<> 144:ef7eb2e8f9f7 24707 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS GPC_MFPL: PC2MFP Mask */
<> 144:ef7eb2e8f9f7 24708
<> 144:ef7eb2e8f9f7 24709 #define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS GPC_MFPL: PC3MFP Position */
<> 144:ef7eb2e8f9f7 24710 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS GPC_MFPL: PC3MFP Mask */
<> 144:ef7eb2e8f9f7 24711
<> 144:ef7eb2e8f9f7 24712 #define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS GPC_MFPL: PC4MFP Position */
<> 144:ef7eb2e8f9f7 24713 #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS GPC_MFPL: PC4MFP Mask */
<> 144:ef7eb2e8f9f7 24714
<> 144:ef7eb2e8f9f7 24715 #define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS GPC_MFPL: PC5MFP Position */
<> 144:ef7eb2e8f9f7 24716 #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS GPC_MFPL: PC5MFP Mask */
<> 144:ef7eb2e8f9f7 24717
<> 144:ef7eb2e8f9f7 24718 #define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS GPC_MFPL: PC6MFP Position */
<> 144:ef7eb2e8f9f7 24719 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS GPC_MFPL: PC6MFP Mask */
<> 144:ef7eb2e8f9f7 24720
<> 144:ef7eb2e8f9f7 24721 #define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS GPC_MFPL: PC7MFP Position */
<> 144:ef7eb2e8f9f7 24722 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS GPC_MFPL: PC7MFP Mask */
<> 144:ef7eb2e8f9f7 24723
<> 144:ef7eb2e8f9f7 24724 #define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS GPC_MFPH: PC8MFP Position */
<> 144:ef7eb2e8f9f7 24725 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS GPC_MFPH: PC8MFP Mask */
<> 144:ef7eb2e8f9f7 24726
<> 144:ef7eb2e8f9f7 24727 #define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS GPC_MFPH: PC9MFP Position */
<> 144:ef7eb2e8f9f7 24728 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS GPC_MFPH: PC9MFP Mask */
<> 144:ef7eb2e8f9f7 24729
<> 144:ef7eb2e8f9f7 24730 #define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS GPC_MFPH: PC10MFP Position */
<> 144:ef7eb2e8f9f7 24731 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS GPC_MFPH: PC10MFP Mask */
<> 144:ef7eb2e8f9f7 24732
<> 144:ef7eb2e8f9f7 24733 #define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS GPC_MFPH: PC11MFP Position */
<> 144:ef7eb2e8f9f7 24734 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS GPC_MFPH: PC11MFP Mask */
<> 144:ef7eb2e8f9f7 24735
<> 144:ef7eb2e8f9f7 24736 #define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS GPC_MFPH: PC12MFP Position */
<> 144:ef7eb2e8f9f7 24737 #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS GPC_MFPH: PC12MFP Mask */
<> 144:ef7eb2e8f9f7 24738
<> 144:ef7eb2e8f9f7 24739 #define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS GPC_MFPH: PC13MFP Position */
<> 144:ef7eb2e8f9f7 24740 #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS GPC_MFPH: PC13MFP Mask */
<> 144:ef7eb2e8f9f7 24741
<> 144:ef7eb2e8f9f7 24742 #define SYS_GPC_MFPH_PC14MFP_Pos (24) /*!< SYS GPC_MFPH: PC14MFP Position */
<> 144:ef7eb2e8f9f7 24743 #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) /*!< SYS GPC_MFPH: PC14MFP Mask */
<> 144:ef7eb2e8f9f7 24744
<> 144:ef7eb2e8f9f7 24745 #define SYS_GPC_MFPH_PC15MFP_Pos (28) /*!< SYS GPC_MFPH: PC15MFP Position */
<> 144:ef7eb2e8f9f7 24746 #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) /*!< SYS GPC_MFPH: PC15MFP Mask */
<> 144:ef7eb2e8f9f7 24747
<> 144:ef7eb2e8f9f7 24748 #define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS GPD_MFPL: PD0MFP Position */
<> 144:ef7eb2e8f9f7 24749 #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS GPD_MFPL: PD0MFP Mask */
<> 144:ef7eb2e8f9f7 24750
<> 144:ef7eb2e8f9f7 24751 #define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS GPD_MFPL: PD1MFP Position */
<> 144:ef7eb2e8f9f7 24752 #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS GPD_MFPL: PD1MFP Mask */
<> 144:ef7eb2e8f9f7 24753
<> 144:ef7eb2e8f9f7 24754 #define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS GPD_MFPL: PD2MFP Position */
<> 144:ef7eb2e8f9f7 24755 #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS GPD_MFPL: PD2MFP Mask */
<> 144:ef7eb2e8f9f7 24756
<> 144:ef7eb2e8f9f7 24757 #define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS GPD_MFPL: PD3MFP Position */
<> 144:ef7eb2e8f9f7 24758 #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS GPD_MFPL: PD3MFP Mask */
<> 144:ef7eb2e8f9f7 24759
<> 144:ef7eb2e8f9f7 24760 #define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS GPD_MFPL: PD4MFP Position */
<> 144:ef7eb2e8f9f7 24761 #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS GPD_MFPL: PD4MFP Mask */
<> 144:ef7eb2e8f9f7 24762
<> 144:ef7eb2e8f9f7 24763 #define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS GPD_MFPL: PD5MFP Position */
<> 144:ef7eb2e8f9f7 24764 #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS GPD_MFPL: PD5MFP Mask */
<> 144:ef7eb2e8f9f7 24765
<> 144:ef7eb2e8f9f7 24766 #define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS GPD_MFPL: PD6MFP Position */
<> 144:ef7eb2e8f9f7 24767 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS GPD_MFPL: PD6MFP Mask */
<> 144:ef7eb2e8f9f7 24768
<> 144:ef7eb2e8f9f7 24769 #define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS GPD_MFPL: PD7MFP Position */
<> 144:ef7eb2e8f9f7 24770 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS GPD_MFPL: PD7MFP Mask */
<> 144:ef7eb2e8f9f7 24771
<> 144:ef7eb2e8f9f7 24772 #define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS GPD_MFPH: PD8MFP Position */
<> 144:ef7eb2e8f9f7 24773 #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS GPD_MFPH: PD8MFP Mask */
<> 144:ef7eb2e8f9f7 24774
<> 144:ef7eb2e8f9f7 24775 #define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS GPD_MFPH: PD9MFP Position */
<> 144:ef7eb2e8f9f7 24776 #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS GPD_MFPH: PD9MFP Mask */
<> 144:ef7eb2e8f9f7 24777
<> 144:ef7eb2e8f9f7 24778 #define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS GPD_MFPH: PD10MFP Position */
<> 144:ef7eb2e8f9f7 24779 #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS GPD_MFPH: PD10MFP Mask */
<> 144:ef7eb2e8f9f7 24780
<> 144:ef7eb2e8f9f7 24781 #define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS GPD_MFPH: PD11MFP Position */
<> 144:ef7eb2e8f9f7 24782 #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS GPD_MFPH: PD11MFP Mask */
<> 144:ef7eb2e8f9f7 24783
<> 144:ef7eb2e8f9f7 24784 #define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS GPD_MFPH: PD12MFP Position */
<> 144:ef7eb2e8f9f7 24785 #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS GPD_MFPH: PD12MFP Mask */
<> 144:ef7eb2e8f9f7 24786
<> 144:ef7eb2e8f9f7 24787 #define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS GPD_MFPH: PD13MFP Position */
<> 144:ef7eb2e8f9f7 24788 #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS GPD_MFPH: PD13MFP Mask */
<> 144:ef7eb2e8f9f7 24789
<> 144:ef7eb2e8f9f7 24790 #define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS GPD_MFPH: PD14MFP Position */
<> 144:ef7eb2e8f9f7 24791 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS GPD_MFPH: PD14MFP Mask */
<> 144:ef7eb2e8f9f7 24792
<> 144:ef7eb2e8f9f7 24793 #define SYS_GPD_MFPH_PD15MFP_Pos (28) /*!< SYS GPD_MFPH: PD15MFP Position */
<> 144:ef7eb2e8f9f7 24794 #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) /*!< SYS GPD_MFPH: PD15MFP Mask */
<> 144:ef7eb2e8f9f7 24795
<> 144:ef7eb2e8f9f7 24796 #define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS GPE_MFPL: PE0MFP Position */
<> 144:ef7eb2e8f9f7 24797 #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS GPE_MFPL: PE0MFP Mask */
<> 144:ef7eb2e8f9f7 24798
<> 144:ef7eb2e8f9f7 24799 #define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS GPE_MFPL: PE1MFP Position */
<> 144:ef7eb2e8f9f7 24800 #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS GPE_MFPL: PE1MFP Mask */
<> 144:ef7eb2e8f9f7 24801
<> 144:ef7eb2e8f9f7 24802 #define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS GPE_MFPL: PE2MFP Position */
<> 144:ef7eb2e8f9f7 24803 #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS GPE_MFPL: PE2MFP Mask */
<> 144:ef7eb2e8f9f7 24804
<> 144:ef7eb2e8f9f7 24805 #define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS GPE_MFPL: PE3MFP Position */
<> 144:ef7eb2e8f9f7 24806 #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS GPE_MFPL: PE3MFP Mask */
<> 144:ef7eb2e8f9f7 24807
<> 144:ef7eb2e8f9f7 24808 #define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS GPE_MFPL: PE4MFP Position */
<> 144:ef7eb2e8f9f7 24809 #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS GPE_MFPL: PE4MFP Mask */
<> 144:ef7eb2e8f9f7 24810
<> 144:ef7eb2e8f9f7 24811 #define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS GPE_MFPL: PE5MFP Position */
<> 144:ef7eb2e8f9f7 24812 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS GPE_MFPL: PE5MFP Mask */
<> 144:ef7eb2e8f9f7 24813
<> 144:ef7eb2e8f9f7 24814 #define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS GPE_MFPL: PE6MFP Position */
<> 144:ef7eb2e8f9f7 24815 #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS GPE_MFPL: PE6MFP Mask */
<> 144:ef7eb2e8f9f7 24816
<> 144:ef7eb2e8f9f7 24817 #define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS GPE_MFPL: PE7MFP Position */
<> 144:ef7eb2e8f9f7 24818 #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS GPE_MFPL: PE7MFP Mask */
<> 144:ef7eb2e8f9f7 24819
<> 144:ef7eb2e8f9f7 24820 #define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS GPE_MFPH: PE8MFP Position */
<> 144:ef7eb2e8f9f7 24821 #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS GPE_MFPH: PE8MFP Mask */
<> 144:ef7eb2e8f9f7 24822
<> 144:ef7eb2e8f9f7 24823 #define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS GPE_MFPH: PE9MFP Position */
<> 144:ef7eb2e8f9f7 24824 #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS GPE_MFPH: PE9MFP Mask */
<> 144:ef7eb2e8f9f7 24825
<> 144:ef7eb2e8f9f7 24826 #define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS GPE_MFPH: PE10MFP Position */
<> 144:ef7eb2e8f9f7 24827 #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS GPE_MFPH: PE10MFP Mask */
<> 144:ef7eb2e8f9f7 24828
<> 144:ef7eb2e8f9f7 24829 #define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS GPE_MFPH: PE11MFP Position */
<> 144:ef7eb2e8f9f7 24830 #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS GPE_MFPH: PE11MFP Mask */
<> 144:ef7eb2e8f9f7 24831
<> 144:ef7eb2e8f9f7 24832 #define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS GPE_MFPH: PE12MFP Position */
<> 144:ef7eb2e8f9f7 24833 #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS GPE_MFPH: PE12MFP Mask */
<> 144:ef7eb2e8f9f7 24834
<> 144:ef7eb2e8f9f7 24835 #define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS GPE_MFPH: PE13MFP Position */
<> 144:ef7eb2e8f9f7 24836 #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS GPE_MFPH: PE13MFP Mask */
<> 144:ef7eb2e8f9f7 24837
<> 144:ef7eb2e8f9f7 24838 #define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS GPE_MFPH: PE14MFP Position */
<> 144:ef7eb2e8f9f7 24839 #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS GPE_MFPH: PE14MFP Mask */
<> 144:ef7eb2e8f9f7 24840
<> 144:ef7eb2e8f9f7 24841 #define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS GPE_MFPH: PE15MFP Position */
<> 144:ef7eb2e8f9f7 24842 #define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS GPE_MFPH: PE15MFP Mask */
<> 144:ef7eb2e8f9f7 24843
<> 144:ef7eb2e8f9f7 24844 #define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS GPF_MFPL: PF0MFP Position */
<> 144:ef7eb2e8f9f7 24845 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS GPF_MFPL: PF0MFP Mask */
<> 144:ef7eb2e8f9f7 24846
<> 144:ef7eb2e8f9f7 24847 #define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS GPF_MFPL: PF1MFP Position */
<> 144:ef7eb2e8f9f7 24848 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS GPF_MFPL: PF1MFP Mask */
<> 144:ef7eb2e8f9f7 24849
<> 144:ef7eb2e8f9f7 24850 #define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS GPF_MFPL: PF2MFP Position */
<> 144:ef7eb2e8f9f7 24851 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS GPF_MFPL: PF2MFP Mask */
<> 144:ef7eb2e8f9f7 24852
<> 144:ef7eb2e8f9f7 24853 #define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS GPF_MFPL: PF3MFP Position */
<> 144:ef7eb2e8f9f7 24854 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS GPF_MFPL: PF3MFP Mask */
<> 144:ef7eb2e8f9f7 24855
<> 144:ef7eb2e8f9f7 24856 #define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS GPF_MFPL: PF4MFP Position */
<> 144:ef7eb2e8f9f7 24857 #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS GPF_MFPL: PF4MFP Mask */
<> 144:ef7eb2e8f9f7 24858
<> 144:ef7eb2e8f9f7 24859 #define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS GPF_MFPL: PF5MFP Position */
<> 144:ef7eb2e8f9f7 24860 #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS GPF_MFPL: PF5MFP Mask */
<> 144:ef7eb2e8f9f7 24861
<> 144:ef7eb2e8f9f7 24862 #define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS GPF_MFPL: PF6MFP Position */
<> 144:ef7eb2e8f9f7 24863 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS GPF_MFPL: PF6MFP Mask */
<> 144:ef7eb2e8f9f7 24864
<> 144:ef7eb2e8f9f7 24865 #define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS GPF_MFPL: PF7MFP Position */
<> 144:ef7eb2e8f9f7 24866 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS GPF_MFPL: PF7MFP Mask */
<> 144:ef7eb2e8f9f7 24867
<> 144:ef7eb2e8f9f7 24868 #define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS GPF_MFPH: PF8MFP Position */
<> 144:ef7eb2e8f9f7 24869 #define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS GPF_MFPH: PF8MFP Mask */
<> 144:ef7eb2e8f9f7 24870
<> 144:ef7eb2e8f9f7 24871 #define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS GPF_MFPH: PF9MFP Position */
<> 144:ef7eb2e8f9f7 24872 #define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS GPF_MFPH: PF9MFP Mask */
<> 144:ef7eb2e8f9f7 24873
<> 144:ef7eb2e8f9f7 24874 #define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS GPF_MFPH: PF10MFP Position */
<> 144:ef7eb2e8f9f7 24875 #define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS GPF_MFPH: PF10MFP Mask */
<> 144:ef7eb2e8f9f7 24876
<> 144:ef7eb2e8f9f7 24877 #define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS GPF_MFPH: PF11MFP Position */
<> 144:ef7eb2e8f9f7 24878 #define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS GPF_MFPH: PF11MFP Mask */
<> 144:ef7eb2e8f9f7 24879
<> 144:ef7eb2e8f9f7 24880 #define SYS_GPF_MFPH_PF12MFP_Pos (16) /*!< SYS GPF_MFPH: PF12MFP Position */
<> 144:ef7eb2e8f9f7 24881 #define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) /*!< SYS GPF_MFPH: PF12MFP Mask */
<> 144:ef7eb2e8f9f7 24882
<> 144:ef7eb2e8f9f7 24883 #define SYS_GPF_MFPH_PF13MFP_Pos (20) /*!< SYS GPF_MFPH: PF13MFP Position */
<> 144:ef7eb2e8f9f7 24884 #define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) /*!< SYS GPF_MFPH: PF13MFP Mask */
<> 144:ef7eb2e8f9f7 24885
<> 144:ef7eb2e8f9f7 24886 #define SYS_GPF_MFPH_PF14MFP_Pos (24) /*!< SYS GPF_MFPH: PF14MFP Position */
<> 144:ef7eb2e8f9f7 24887 #define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) /*!< SYS GPF_MFPH: PF14MFP Mask */
<> 144:ef7eb2e8f9f7 24888
<> 144:ef7eb2e8f9f7 24889 #define SYS_GPF_MFPH_PF15MFP_Pos (28) /*!< SYS GPF_MFPH: PF15MFP Position */
<> 144:ef7eb2e8f9f7 24890 #define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) /*!< SYS GPF_MFPH: PF15MFP Mask */
<> 144:ef7eb2e8f9f7 24891
<> 144:ef7eb2e8f9f7 24892 #define SYS_GPG_MFPL_PG0MFP_Pos (0) /*!< SYS GPG_MFPL: PG0MFP Position */
<> 144:ef7eb2e8f9f7 24893 #define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) /*!< SYS GPG_MFPL: PG0MFP Mask */
<> 144:ef7eb2e8f9f7 24894
<> 144:ef7eb2e8f9f7 24895 #define SYS_GPG_MFPL_PG1MFP_Pos (4) /*!< SYS GPG_MFPL: PG1MFP Position */
<> 144:ef7eb2e8f9f7 24896 #define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) /*!< SYS GPG_MFPL: PG1MFP Mask */
<> 144:ef7eb2e8f9f7 24897
<> 144:ef7eb2e8f9f7 24898 #define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS GPG_MFPL: PG2MFP Position */
<> 144:ef7eb2e8f9f7 24899 #define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS GPG_MFPL: PG2MFP Mask */
<> 144:ef7eb2e8f9f7 24900
<> 144:ef7eb2e8f9f7 24901 #define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS GPG_MFPL: PG3MFP Position */
<> 144:ef7eb2e8f9f7 24902 #define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS GPG_MFPL: PG3MFP Mask */
<> 144:ef7eb2e8f9f7 24903
<> 144:ef7eb2e8f9f7 24904 #define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS GPG_MFPL: PG4MFP Position */
<> 144:ef7eb2e8f9f7 24905 #define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS GPG_MFPL: PG4MFP Mask */
<> 144:ef7eb2e8f9f7 24906
<> 144:ef7eb2e8f9f7 24907 #define SYS_GPG_MFPL_PG5MFP_Pos (20) /*!< SYS GPG_MFPL: PG5MFP Position */
<> 144:ef7eb2e8f9f7 24908 #define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) /*!< SYS GPG_MFPL: PG5MFP Mask */
<> 144:ef7eb2e8f9f7 24909
<> 144:ef7eb2e8f9f7 24910 #define SYS_GPG_MFPL_PG6MFP_Pos (24) /*!< SYS GPG_MFPL: PG6MFP Position */
<> 144:ef7eb2e8f9f7 24911 #define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) /*!< SYS GPG_MFPL: PG6MFP Mask */
<> 144:ef7eb2e8f9f7 24912
<> 144:ef7eb2e8f9f7 24913 #define SYS_GPG_MFPL_PG7MFP_Pos (28) /*!< SYS GPG_MFPL: PG7MFP Position */
<> 144:ef7eb2e8f9f7 24914 #define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) /*!< SYS GPG_MFPL: PG7MFP Mask */
<> 144:ef7eb2e8f9f7 24915
<> 144:ef7eb2e8f9f7 24916 #define SYS_GPG_MFPH_PG8MFP_Pos (0) /*!< SYS GPG_MFPH: PG8MFP Position */
<> 144:ef7eb2e8f9f7 24917 #define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) /*!< SYS GPG_MFPH: PG8MFP Mask */
<> 144:ef7eb2e8f9f7 24918
<> 144:ef7eb2e8f9f7 24919 #define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS GPG_MFPH: PG9MFP Position */
<> 144:ef7eb2e8f9f7 24920 #define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS GPG_MFPH: PG9MFP Mask */
<> 144:ef7eb2e8f9f7 24921
<> 144:ef7eb2e8f9f7 24922 #define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS GPG_MFPH: PG10MFP Position */
<> 144:ef7eb2e8f9f7 24923 #define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS GPG_MFPH: PG10MFP Mask */
<> 144:ef7eb2e8f9f7 24924
<> 144:ef7eb2e8f9f7 24925 #define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS GPG_MFPH: PG11MFP Position */
<> 144:ef7eb2e8f9f7 24926 #define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS GPG_MFPH: PG11MFP Mask */
<> 144:ef7eb2e8f9f7 24927
<> 144:ef7eb2e8f9f7 24928 #define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS GPG_MFPH: PG12MFP Position */
<> 144:ef7eb2e8f9f7 24929 #define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS GPG_MFPH: PG12MFP Mask */
<> 144:ef7eb2e8f9f7 24930
<> 144:ef7eb2e8f9f7 24931 #define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS GPG_MFPH: PG13MFP Position */
<> 144:ef7eb2e8f9f7 24932 #define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS GPG_MFPH: PG13MFP Mask */
<> 144:ef7eb2e8f9f7 24933
<> 144:ef7eb2e8f9f7 24934 #define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS GPG_MFPH: PG14MFP Position */
<> 144:ef7eb2e8f9f7 24935 #define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS GPG_MFPH: PG14MFP Mask */
<> 144:ef7eb2e8f9f7 24936
<> 144:ef7eb2e8f9f7 24937 #define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS GPG_MFPH: PG15MFP Position */
<> 144:ef7eb2e8f9f7 24938 #define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS GPG_MFPH: PG15MFP Mask */
<> 144:ef7eb2e8f9f7 24939
<> 144:ef7eb2e8f9f7 24940 #define SYS_GPH_MFPL_PH0MFP_Pos (0) /*!< SYS GPH_MFPL: PH0MFP Position */
<> 144:ef7eb2e8f9f7 24941 #define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) /*!< SYS GPH_MFPL: PH0MFP Mask */
<> 144:ef7eb2e8f9f7 24942
<> 144:ef7eb2e8f9f7 24943 #define SYS_GPH_MFPL_PH1MFP_Pos (4) /*!< SYS GPH_MFPL: PH1MFP Position */
<> 144:ef7eb2e8f9f7 24944 #define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) /*!< SYS GPH_MFPL: PH1MFP Mask */
<> 144:ef7eb2e8f9f7 24945
<> 144:ef7eb2e8f9f7 24946 #define SYS_GPH_MFPL_PH2MFP_Pos (8) /*!< SYS GPH_MFPL: PH2MFP Position */
<> 144:ef7eb2e8f9f7 24947 #define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) /*!< SYS GPH_MFPL: PH2MFP Mask */
<> 144:ef7eb2e8f9f7 24948
<> 144:ef7eb2e8f9f7 24949 #define SYS_GPH_MFPL_PH3MFP_Pos (12) /*!< SYS GPH_MFPL: PH3MFP Position */
<> 144:ef7eb2e8f9f7 24950 #define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) /*!< SYS GPH_MFPL: PH3MFP Mask */
<> 144:ef7eb2e8f9f7 24951
<> 144:ef7eb2e8f9f7 24952 #define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS GPH_MFPL: PH4MFP Position */
<> 144:ef7eb2e8f9f7 24953 #define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS GPH_MFPL: PH4MFP Mask */
<> 144:ef7eb2e8f9f7 24954
<> 144:ef7eb2e8f9f7 24955 #define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS GPH_MFPL: PH5MFP Position */
<> 144:ef7eb2e8f9f7 24956 #define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS GPH_MFPL: PH5MFP Mask */
<> 144:ef7eb2e8f9f7 24957
<> 144:ef7eb2e8f9f7 24958 #define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS GPH_MFPL: PH6MFP Position */
<> 144:ef7eb2e8f9f7 24959 #define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS GPH_MFPL: PH6MFP Mask */
<> 144:ef7eb2e8f9f7 24960
<> 144:ef7eb2e8f9f7 24961 #define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS GPH_MFPL: PH7MFP Position */
<> 144:ef7eb2e8f9f7 24962 #define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS GPH_MFPL: PH7MFP Mask */
<> 144:ef7eb2e8f9f7 24963
<> 144:ef7eb2e8f9f7 24964 #define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS GPH_MFPH: PH8MFP Position */
<> 144:ef7eb2e8f9f7 24965 #define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS GPH_MFPH: PH8MFP Mask */
<> 144:ef7eb2e8f9f7 24966
<> 144:ef7eb2e8f9f7 24967 #define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS GPH_MFPH: PH9MFP Position */
<> 144:ef7eb2e8f9f7 24968 #define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS GPH_MFPH: PH9MFP Mask */
<> 144:ef7eb2e8f9f7 24969
<> 144:ef7eb2e8f9f7 24970 #define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS GPH_MFPH: PH10MFP Position */
<> 144:ef7eb2e8f9f7 24971 #define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS GPH_MFPH: PH10MFP Mask */
<> 144:ef7eb2e8f9f7 24972
<> 144:ef7eb2e8f9f7 24973 #define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS GPH_MFPH: PH11MFP Position */
<> 144:ef7eb2e8f9f7 24974 #define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS GPH_MFPH: PH11MFP Mask */
<> 144:ef7eb2e8f9f7 24975
<> 144:ef7eb2e8f9f7 24976 #define SYS_GPH_MFPH_PH12MFP_Pos (16) /*!< SYS GPH_MFPH: PH12MFP Position */
<> 144:ef7eb2e8f9f7 24977 #define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) /*!< SYS GPH_MFPH: PH12MFP Mask */
<> 144:ef7eb2e8f9f7 24978
<> 144:ef7eb2e8f9f7 24979 #define SYS_GPH_MFPH_PH13MFP_Pos (20) /*!< SYS GPH_MFPH: PH13MFP Position */
<> 144:ef7eb2e8f9f7 24980 #define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) /*!< SYS GPH_MFPH: PH13MFP Mask */
<> 144:ef7eb2e8f9f7 24981
<> 144:ef7eb2e8f9f7 24982 #define SYS_GPH_MFPH_PH14MFP_Pos (24) /*!< SYS GPH_MFPH: PH14MFP Position */
<> 144:ef7eb2e8f9f7 24983 #define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) /*!< SYS GPH_MFPH: PH14MFP Mask */
<> 144:ef7eb2e8f9f7 24984
<> 144:ef7eb2e8f9f7 24985 #define SYS_GPH_MFPH_PH15MFP_Pos (28) /*!< SYS GPH_MFPH: PH15MFP Position */
<> 144:ef7eb2e8f9f7 24986 #define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) /*!< SYS GPH_MFPH: PH15MFP Mask */
<> 144:ef7eb2e8f9f7 24987
<> 144:ef7eb2e8f9f7 24988 #define SYS_GPI_MFPL_PI0MFP_Pos (0) /*!< SYS GPI_MFPL: PI0MFP Position */
<> 144:ef7eb2e8f9f7 24989 #define SYS_GPI_MFPL_PI0MFP_Msk (0xful << SYS_GPI_MFPL_PI0MFP_Pos) /*!< SYS GPI_MFPL: PI0MFP Mask */
<> 144:ef7eb2e8f9f7 24990
<> 144:ef7eb2e8f9f7 24991 #define SYS_GPI_MFPL_PI1MFP_Pos (4) /*!< SYS GPI_MFPL: PI1MFP Position */
<> 144:ef7eb2e8f9f7 24992 #define SYS_GPI_MFPL_PI1MFP_Msk (0xful << SYS_GPI_MFPL_PI1MFP_Pos) /*!< SYS GPI_MFPL: PI1MFP Mask */
<> 144:ef7eb2e8f9f7 24993
<> 144:ef7eb2e8f9f7 24994 #define SYS_GPI_MFPL_PI2MFP_Pos (8) /*!< SYS GPI_MFPL: PI2MFP Position */
<> 144:ef7eb2e8f9f7 24995 #define SYS_GPI_MFPL_PI2MFP_Msk (0xful << SYS_GPI_MFPL_PI2MFP_Pos) /*!< SYS GPI_MFPL: PI2MFP Mask */
<> 144:ef7eb2e8f9f7 24996
<> 144:ef7eb2e8f9f7 24997 #define SYS_GPI_MFPL_PI3MFP_Pos (12) /*!< SYS GPI_MFPL: PI3MFP Position */
<> 144:ef7eb2e8f9f7 24998 #define SYS_GPI_MFPL_PI3MFP_Msk (0xful << SYS_GPI_MFPL_PI3MFP_Pos) /*!< SYS GPI_MFPL: PI3MFP Mask */
<> 144:ef7eb2e8f9f7 24999
<> 144:ef7eb2e8f9f7 25000 #define SYS_GPI_MFPL_PI4MFP_Pos (16) /*!< SYS GPI_MFPL: PI4MFP Position */
<> 144:ef7eb2e8f9f7 25001 #define SYS_GPI_MFPL_PI4MFP_Msk (0xful << SYS_GPI_MFPL_PI4MFP_Pos) /*!< SYS GPI_MFPL: PI4MFP Mask */
<> 144:ef7eb2e8f9f7 25002
<> 144:ef7eb2e8f9f7 25003 #define SYS_GPI_MFPL_PI5MFP_Pos (20) /*!< SYS GPI_MFPL: PI5MFP Position */
<> 144:ef7eb2e8f9f7 25004 #define SYS_GPI_MFPL_PI5MFP_Msk (0xful << SYS_GPI_MFPL_PI5MFP_Pos) /*!< SYS GPI_MFPL: PI5MFP Mask */
<> 144:ef7eb2e8f9f7 25005
<> 144:ef7eb2e8f9f7 25006 #define SYS_GPI_MFPL_PI6MFP_Pos (24) /*!< SYS GPI_MFPL: PI6MFP Position */
<> 144:ef7eb2e8f9f7 25007 #define SYS_GPI_MFPL_PI6MFP_Msk (0xful << SYS_GPI_MFPL_PI6MFP_Pos) /*!< SYS GPI_MFPL: PI6MFP Mask */
<> 144:ef7eb2e8f9f7 25008
<> 144:ef7eb2e8f9f7 25009 #define SYS_GPI_MFPL_PI7MFP_Pos (28) /*!< SYS GPI_MFPL: PI7MFP Position */
<> 144:ef7eb2e8f9f7 25010 #define SYS_GPI_MFPL_PI7MFP_Msk (0xful << SYS_GPI_MFPL_PI7MFP_Pos) /*!< SYS GPI_MFPL: PI7MFP Mask */
<> 144:ef7eb2e8f9f7 25011
<> 144:ef7eb2e8f9f7 25012 #define SYS_GPI_MFPH_PI8MFP_Pos (0) /*!< SYS GPI_MFPH: PI8MFP Position */
<> 144:ef7eb2e8f9f7 25013 #define SYS_GPI_MFPH_PI8MFP_Msk (0xful << SYS_GPI_MFPH_PI8MFP_Pos) /*!< SYS GPI_MFPH: PI8MFP Mask */
<> 144:ef7eb2e8f9f7 25014
<> 144:ef7eb2e8f9f7 25015 #define SYS_GPI_MFPH_PI9MFP_Pos (4) /*!< SYS GPI_MFPH: PI9MFP Position */
<> 144:ef7eb2e8f9f7 25016 #define SYS_GPI_MFPH_PI9MFP_Msk (0xful << SYS_GPI_MFPH_PI9MFP_Pos) /*!< SYS GPI_MFPH: PI9MFP Mask */
<> 144:ef7eb2e8f9f7 25017
<> 144:ef7eb2e8f9f7 25018 #define SYS_GPI_MFPH_PI10MFP_Pos (8) /*!< SYS GPI_MFPH: PI10MFP Position */
<> 144:ef7eb2e8f9f7 25019 #define SYS_GPI_MFPH_PI10MFP_Msk (0xful << SYS_GPI_MFPH_PI10MFP_Pos) /*!< SYS GPI_MFPH: PI10MFP Mask */
<> 144:ef7eb2e8f9f7 25020
<> 144:ef7eb2e8f9f7 25021 #define SYS_GPI_MFPH_PI11MFP_Pos (12) /*!< SYS GPI_MFPH: PI11MFP Position */
<> 144:ef7eb2e8f9f7 25022 #define SYS_GPI_MFPH_PI11MFP_Msk (0xful << SYS_GPI_MFPH_PI11MFP_Pos) /*!< SYS GPI_MFPH: PI11MFP Mask */
<> 144:ef7eb2e8f9f7 25023
<> 144:ef7eb2e8f9f7 25024 #define SYS_GPI_MFPH_PI12MFP_Pos (16) /*!< SYS GPI_MFPH: PI12MFP Position */
<> 144:ef7eb2e8f9f7 25025 #define SYS_GPI_MFPH_PI12MFP_Msk (0xful << SYS_GPI_MFPH_PI12MFP_Pos) /*!< SYS GPI_MFPH: PI12MFP Mask */
<> 144:ef7eb2e8f9f7 25026
<> 144:ef7eb2e8f9f7 25027 #define SYS_GPI_MFPH_PI13MFP_Pos (20) /*!< SYS GPI_MFPH: PI13MFP Position */
<> 144:ef7eb2e8f9f7 25028 #define SYS_GPI_MFPH_PI13MFP_Msk (0xful << SYS_GPI_MFPH_PI13MFP_Pos) /*!< SYS GPI_MFPH: PI13MFP Mask */
<> 144:ef7eb2e8f9f7 25029
<> 144:ef7eb2e8f9f7 25030 #define SYS_GPI_MFPH_PI14MFP_Pos (24) /*!< SYS GPI_MFPH: PI14MFP Position */
<> 144:ef7eb2e8f9f7 25031 #define SYS_GPI_MFPH_PI14MFP_Msk (0xful << SYS_GPI_MFPH_PI14MFP_Pos) /*!< SYS GPI_MFPH: PI14MFP Mask */
<> 144:ef7eb2e8f9f7 25032
<> 144:ef7eb2e8f9f7 25033 #define SYS_GPI_MFPH_PI15MFP_Pos (28) /*!< SYS GPI_MFPH: PI15MFP Position */
<> 144:ef7eb2e8f9f7 25034 #define SYS_GPI_MFPH_PI15MFP_Msk (0xful << SYS_GPI_MFPH_PI15MFP_Pos) /*!< SYS GPI_MFPH: PI15MFP Mask */
<> 144:ef7eb2e8f9f7 25035
<> 144:ef7eb2e8f9f7 25036 #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) /*!< SYS SRAM_INTCTL: PERRIEN Position */
<> 144:ef7eb2e8f9f7 25037 #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) /*!< SYS SRAM_INTCTL: PERRIEN Mask */
<> 144:ef7eb2e8f9f7 25038
<> 144:ef7eb2e8f9f7 25039 #define SYS_SRAM_STATUS_PERRIF0_Pos (0) /*!< SYS SRAM_STATUS: PERRIF0 Position */
<> 144:ef7eb2e8f9f7 25040 #define SYS_SRAM_STATUS_PERRIF0_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF0_Pos) /*!< SYS SRAM_STATUS: PERRIF0 Mask */
<> 144:ef7eb2e8f9f7 25041
<> 144:ef7eb2e8f9f7 25042 #define SYS_SRAM_STATUS_PERRIF1_Pos (1) /*!< SYS SRAM_STATUS: PERRIF1 Position */
<> 144:ef7eb2e8f9f7 25043 #define SYS_SRAM_STATUS_PERRIF1_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF1_Pos) /*!< SYS SRAM_STATUS: PERRIF1 Mask */
<> 144:ef7eb2e8f9f7 25044
<> 144:ef7eb2e8f9f7 25045 #define SYS_SRAM0_ERRADDR_PERRADDR_Pos (0) /*!< SYS SRAM0_ERRADDR: PERRADDR Position */
<> 144:ef7eb2e8f9f7 25046 #define SYS_SRAM0_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM0_ERRADDR_PERRADDR_Pos) /*!< SYS SRAM0_ERRADDR: PERRADDR Mask */
<> 144:ef7eb2e8f9f7 25047
<> 144:ef7eb2e8f9f7 25048 #define SYS_SRAM1_ERRADDR_PERRADDR_Pos (0) /*!< SYS SRAM1_ERRADDR: PERRADDR Position */
<> 144:ef7eb2e8f9f7 25049 #define SYS_SRAM1_ERRADDR_PERRADDR_Msk (0xfffffffful << SYS_SRAM1_ERRADDR_PERRADDR_Pos) /*!< SYS SRAM1_ERRADDR: PERRADDR Mask */
<> 144:ef7eb2e8f9f7 25050
<> 144:ef7eb2e8f9f7 25051 #define SYS_IRCTCTL_FREQSEL_Pos (0) /*!< SYS IRCTCTL: FREQSEL Position */
<> 144:ef7eb2e8f9f7 25052 #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) /*!< SYS IRCTCTL: FREQSEL Mask */
<> 144:ef7eb2e8f9f7 25053
<> 144:ef7eb2e8f9f7 25054 #define SYS_IRCTCTL_CALCLOOP_Pos (4) /*!< SYS IRCTCTL: CALCLOOP Position */
<> 144:ef7eb2e8f9f7 25055 #define SYS_IRCTCTL_CALCLOOP_Msk (0x3ul << SYS_IRCTCTL_CALCLOOP_Pos) /*!< SYS IRCTCTL: CALCLOOP Mask */
<> 144:ef7eb2e8f9f7 25056
<> 144:ef7eb2e8f9f7 25057 #define SYS_IRCTCTL_RETRYCNT_Pos (6) /*!< SYS IRCTCTL: RETRYCNT Position */
<> 144:ef7eb2e8f9f7 25058 #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) /*!< SYS IRCTCTL: RETRYCNT Mask */
<> 144:ef7eb2e8f9f7 25059
<> 144:ef7eb2e8f9f7 25060 #define SYS_IRCTCTL_CESTOPEN_Pos (8) /*!< SYS IRCTCTL: CESTOPEN Position */
<> 144:ef7eb2e8f9f7 25061 #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) /*!< SYS IRCTCTL: CESTOPEN Mask */
<> 144:ef7eb2e8f9f7 25062
<> 144:ef7eb2e8f9f7 25063 #define SYS_IRCTIEN_TFAILIEN_Pos (1) /*!< SYS IRCTIEN: TFAILIEN Position */
<> 144:ef7eb2e8f9f7 25064 #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) /*!< SYS IRCTIEN: TFAILIEN Mask */
<> 144:ef7eb2e8f9f7 25065
<> 144:ef7eb2e8f9f7 25066 #define SYS_IRCTIEN_CLKEIEN_Pos (2) /*!< SYS IRCTIEN: CLKEIEN Position */
<> 144:ef7eb2e8f9f7 25067 #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) /*!< SYS IRCTIEN: CLKEIEN Mask */
<> 144:ef7eb2e8f9f7 25068
<> 144:ef7eb2e8f9f7 25069 #define SYS_IRCTISTS_FREQLOCK_Pos (0) /*!< SYS IRCTISTS: FREQLOCK Position */
<> 144:ef7eb2e8f9f7 25070 #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) /*!< SYS IRCTISTS: FREQLOCK Mask */
<> 144:ef7eb2e8f9f7 25071
<> 144:ef7eb2e8f9f7 25072 #define SYS_IRCTISTS_TFAILIF_Pos (1) /*!< SYS IRCTISTS: TFAILIF Position */
<> 144:ef7eb2e8f9f7 25073 #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) /*!< SYS IRCTISTS: TFAILIF Mask */
<> 144:ef7eb2e8f9f7 25074
<> 144:ef7eb2e8f9f7 25075 #define SYS_IRCTISTS_CLKERRIF_Pos (2) /*!< SYS IRCTISTS: CLKERRIF Position */
<> 144:ef7eb2e8f9f7 25076 #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) /*!< SYS IRCTISTS: CLKERRIF Mask */
<> 144:ef7eb2e8f9f7 25077
<> 144:ef7eb2e8f9f7 25078 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS REGLCTL: REGLCTL Position */
<> 144:ef7eb2e8f9f7 25079 #define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS REGLCTL: REGLCTL Mask */
<> 144:ef7eb2e8f9f7 25080
<> 144:ef7eb2e8f9f7 25081 #define SYS_REGLCTL_SYS_REGLCTL_Pos (0) /*!< SYS REGLCTL: SYS_REGLCTL Position */
<> 144:ef7eb2e8f9f7 25082 #define SYS_REGLCTL_SYS_REGLCTL_Msk (0xfful << SYS_REGLCTL_SYS_REGLCTL_Pos) /*!< SYS REGLCTL: SYS_REGLCTL Mask */
<> 144:ef7eb2e8f9f7 25083
<> 144:ef7eb2e8f9f7 25084 /**@}*/ /* SYS_CONST */
<> 144:ef7eb2e8f9f7 25085 /**@}*/ /* end of SYS register group */
<> 144:ef7eb2e8f9f7 25086
<> 144:ef7eb2e8f9f7 25087
<> 144:ef7eb2e8f9f7 25088 /*---------------------- Timer Controller -------------------------*/
<> 144:ef7eb2e8f9f7 25089 /**
<> 144:ef7eb2e8f9f7 25090 @addtogroup TIMER Timer Controller(TIMER)
<> 144:ef7eb2e8f9f7 25091 Memory Mapped Structure for TIMER Controller
<> 144:ef7eb2e8f9f7 25092 @{ */
<> 144:ef7eb2e8f9f7 25093
<> 144:ef7eb2e8f9f7 25094 typedef struct {
<> 144:ef7eb2e8f9f7 25095
<> 144:ef7eb2e8f9f7 25096
<> 144:ef7eb2e8f9f7 25097 /**
<> 144:ef7eb2e8f9f7 25098 * CTL
<> 144:ef7eb2e8f9f7 25099 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25100 * Offset: 0x00 Timer Control and Status Register
<> 144:ef7eb2e8f9f7 25101 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25102 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25103 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25104 * |[0:7] |PSC |PSC Counter
<> 144:ef7eb2e8f9f7 25105 * | | |Timer input clock source is divided by (PSC+1) before it is fed to the timer up counter.
<> 144:ef7eb2e8f9f7 25106 * | | |If this field is 0 (PSC = 0), then there is no scaling.
<> 144:ef7eb2e8f9f7 25107 * |[16] |CNTDATEN |Data Load Enable
<> 144:ef7eb2e8f9f7 25108 * | | |When this bit is set, timer counter value (TIMER_CNT) will be updated continuously to monitor internal 24-bit up counter value as the counter is counting.
<> 144:ef7eb2e8f9f7 25109 * | | |0 = Timer Data Register update Disabled.
<> 144:ef7eb2e8f9f7 25110 * | | |1 = Timer Data Register update Enabled while timer counter is active.
<> 144:ef7eb2e8f9f7 25111 * |[21] |TOGDIS1 |Toggle Output 1 Disable
<> 144:ef7eb2e8f9f7 25112 * | | |Setting this bit will disable the Toggle output pins group 1.
<> 144:ef7eb2e8f9f7 25113 * | | |0 = Toggle output pins group 1 Enabled.
<> 144:ef7eb2e8f9f7 25114 * | | |1 = Toggle output pins group 1 Disabled.
<> 144:ef7eb2e8f9f7 25115 * | | |Note: The group1 pins are PB4, PB1, PC6, and PC1.
<> 144:ef7eb2e8f9f7 25116 * |[22] |TOGDIS2 |Toggle Output 2 Disable
<> 144:ef7eb2e8f9f7 25117 * | | |Setting this bit will disable the Toggle output pins group 2.
<> 144:ef7eb2e8f9f7 25118 * | | |0 = Toggle output pins group 2 Enabled.
<> 144:ef7eb2e8f9f7 25119 * | | |1 = Toggle output pins group 2 Disabled.
<> 144:ef7eb2e8f9f7 25120 * | | |Note1: If both TOUT1 (group 1 pins) and TOUT2 (group 2 pins) function are enabled, toggle output signal is generated only from TOUT1 pins.
<> 144:ef7eb2e8f9f7 25121 * | | |Note2: The group2 pins are PD1, PE8, PE1, and PD11.
<> 144:ef7eb2e8f9f7 25122 * |[23] |WKEN |Wake-Up Enable
<> 144:ef7eb2e8f9f7 25123 * | | |If this bit is set to 1, while timer interrupt flag TIF (TIMER_INTSTS[0]) is 1 and INTEN (TIMERX_CTL[29]) is enabled, the timer interrupt signal will generate a wake-up trigger event to CPU.
<> 144:ef7eb2e8f9f7 25124 * | | |0 = Wake-up trigger event Disabled if timer interrupt signal generated.
<> 144:ef7eb2e8f9f7 25125 * | | |1 = Wake-up trigger event Enabled if timer interrupt signal generated.
<> 144:ef7eb2e8f9f7 25126 * |[24] |EXTCNTEN |Counter Mode Enable Bit
<> 144:ef7eb2e8f9f7 25127 * | | |This bit is for external counting pin function enabled.
<> 144:ef7eb2e8f9f7 25128 * | | |When timer is used as an event counter, this bit should be set to 1 and select PCLK as timer clock source.
<> 144:ef7eb2e8f9f7 25129 * | | |0 = External counter mode Disabled.
<> 144:ef7eb2e8f9f7 25130 * | | |1 = External counter mode Enabled.
<> 144:ef7eb2e8f9f7 25131 * |[25] |ACTSTS |Timer Active Status Bit (Read Only)
<> 144:ef7eb2e8f9f7 25132 * | | |This bit indicates the 24-bit up counter status.
<> 144:ef7eb2e8f9f7 25133 * | | |0 = 24-bit up counter is not active.
<> 144:ef7eb2e8f9f7 25134 * | | |1 = 24-bit up counter is active.
<> 144:ef7eb2e8f9f7 25135 * |[26] |RSTCNT |Timer Reset Bit
<> 144:ef7eb2e8f9f7 25136 * | | |Setting this bit will reset the 24-bit up counter value (TIMER_CNT) and also force CNTEN (TIMERX_CTL[30]) to 0 if ACTSTS (TIMERX_CTL[25]) is 1.
<> 144:ef7eb2e8f9f7 25137 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 25138 * | | |1 = Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit.
<> 144:ef7eb2e8f9f7 25139 * |[27:28] |OPMODE |Timer Operation Mode
<> 144:ef7eb2e8f9f7 25140 * | | |00 = The Timer controller is operated in One-shot mode.
<> 144:ef7eb2e8f9f7 25141 * | | |01 = The Timer controller is operated in Periodic mode.
<> 144:ef7eb2e8f9f7 25142 * | | |10 = The Timer controller is operated in Toggle-output mode.
<> 144:ef7eb2e8f9f7 25143 * | | |11 = The Timer controller is operated in Continuous Counting mode.
<> 144:ef7eb2e8f9f7 25144 * |[29] |INTEN |Interrupt Enable Bit
<> 144:ef7eb2e8f9f7 25145 * | | |0 = Timer Interrupt Disabled.
<> 144:ef7eb2e8f9f7 25146 * | | |1 = Timer Interrupt Enabled.
<> 144:ef7eb2e8f9f7 25147 * | | |If this bit is enabled, when the timer interrupt flag TIF is set to 1, the timer interrupt signal is generated and inform to CPU.
<> 144:ef7eb2e8f9f7 25148 * |[30] |CNTEN |Timer Enable
<> 144:ef7eb2e8f9f7 25149 * | | |0 = Stops/Suspends counting.
<> 144:ef7eb2e8f9f7 25150 * | | |1 = Starts counting.
<> 144:ef7eb2e8f9f7 25151 * | | |Note1: In stop status, and then set CNTEN to 1 will enable the 24-bit up counter to keep counting from the last stop counting value.
<> 144:ef7eb2e8f9f7 25152 * | | |Note2: This bit is auto-cleared by hardware in one-shot mode (TIMERX_CTL[28:27] = 00) when the timer interrupt flag TIF (TIMER_INTSTS[0]) is generated.
<> 144:ef7eb2e8f9f7 25153 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable (Write Protect)
<> 144:ef7eb2e8f9f7 25154 * | | |0 = ICE debug mode acknowledgement effects TIMER counting.
<> 144:ef7eb2e8f9f7 25155 * | | |TIMER counter will be held while CPU is held by ICE.
<> 144:ef7eb2e8f9f7 25156 * | | |1 = ICE debug mode acknowledgement Disabled.
<> 144:ef7eb2e8f9f7 25157 * | | |TIMER counter will keep going no matter CPU is held by ICE or not.
<> 144:ef7eb2e8f9f7 25158 */
<> 144:ef7eb2e8f9f7 25159 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 25160
<> 144:ef7eb2e8f9f7 25161 /**
<> 144:ef7eb2e8f9f7 25162 * CMP
<> 144:ef7eb2e8f9f7 25163 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25164 * Offset: 0x04 Timer Compare Register
<> 144:ef7eb2e8f9f7 25165 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25166 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25167 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25168 * |[0:23] |CMPDAT |Timer Compared Value
<> 144:ef7eb2e8f9f7 25169 * | | |CMPDAT is a 24-bit compared value register.
<> 144:ef7eb2e8f9f7 25170 * | | |When the internal 24-bit up counter value is equal to CMPDAT value, the TIF (TIMER_INTSTS[0] timer interrupt flag) will set to 1.
<> 144:ef7eb2e8f9f7 25171 * | | |Time-out period = (Period of timer clock input) * (8-bit PSC + 1) * (24-bit CMPDAT).
<> 144:ef7eb2e8f9f7 25172 * | | |Note1: Never write 0x0 or 0x1 in CMPDAT field, or the timer will run into unknown state.
<> 144:ef7eb2e8f9f7 25173 * | | |Note2: When timer is operating at continuous counting mode, the 24-bit up counter will keep counting continuously even if software writes a new value into CMPDAT field.
<> 144:ef7eb2e8f9f7 25174 * | | |But if timer is operating at other modes, the 24-bit up counter will restart counting and using newest CMPDAT value to be the timer compared value if software writes a new value into CMPDAT field.
<> 144:ef7eb2e8f9f7 25175 */
<> 144:ef7eb2e8f9f7 25176 __IO uint32_t CMP;
<> 144:ef7eb2e8f9f7 25177
<> 144:ef7eb2e8f9f7 25178 /**
<> 144:ef7eb2e8f9f7 25179 * INTSTS
<> 144:ef7eb2e8f9f7 25180 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25181 * Offset: 0x08 Timer Interrupt Status Register
<> 144:ef7eb2e8f9f7 25182 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25183 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25184 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25185 * |[0] |TIF |Timer Interrupt Flag
<> 144:ef7eb2e8f9f7 25186 * | | |This bit indicates the interrupt flag status of Timer while TIMER_CNT value reaches to CMPDAT value.
<> 144:ef7eb2e8f9f7 25187 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 25188 * | | |1 = TIMER_CNT value matches the CMPDAT value.
<> 144:ef7eb2e8f9f7 25189 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25190 * |[1] |TWKF |Timer Wake-Up Flag
<> 144:ef7eb2e8f9f7 25191 * | | |This bit indicates the interrupt wake-up flag status of timer.
<> 144:ef7eb2e8f9f7 25192 * | | |0 = Timer does not cause CPU wake-up.
<> 144:ef7eb2e8f9f7 25193 * | | |1 = CPU wake-up from Idle or power-down mode if timer time-out interrupt signal generated.
<> 144:ef7eb2e8f9f7 25194 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25195 */
<> 144:ef7eb2e8f9f7 25196 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 25197
<> 144:ef7eb2e8f9f7 25198 /**
<> 144:ef7eb2e8f9f7 25199 * CNT
<> 144:ef7eb2e8f9f7 25200 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25201 * Offset: 0x0C Timer Data Register
<> 144:ef7eb2e8f9f7 25202 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25203 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25204 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25205 * |[0:23] |TIMER_CNT |Timer Data Register
<> 144:ef7eb2e8f9f7 25206 * | | |1. EXTCNTEN (TIMERX_CTL[24] ) = 0 : TIMER_CNT is 24- bit counter value.
<> 144:ef7eb2e8f9f7 25207 * | | |User can read TIMER_CNT for getting current 24- bit counter value if TIMERX_CTL[24] is set to 0
<> 144:ef7eb2e8f9f7 25208 * | | |2. EXTCNTEN (TIMERX_CTL[24] ) = 1 : TIMER_CNT is 24- bit event counter value.
<> 144:ef7eb2e8f9f7 25209 * | | |User can read TIMER_CNT for getting current 24- bit event counter value if TIMERX_CTL[24] is 1
<> 144:ef7eb2e8f9f7 25210 */
<> 144:ef7eb2e8f9f7 25211 __I uint32_t CNT;
<> 144:ef7eb2e8f9f7 25212
<> 144:ef7eb2e8f9f7 25213 /**
<> 144:ef7eb2e8f9f7 25214 * CAP
<> 144:ef7eb2e8f9f7 25215 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25216 * Offset: 0x10 Timer Capture Data Register
<> 144:ef7eb2e8f9f7 25217 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25218 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25219 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25220 * |[0:23] |CAPDAT |Timer Capture Data Register
<> 144:ef7eb2e8f9f7 25221 * | | |When CAPEN (TIMER_EXTCTL[3]) bit is set, CAPFUNCS (TIMER_EXTCTL[4]) bit is 0, and a transition on TMx_EXT pin matched the CAPEDGE (TIMER_EXTCTL[2:1]) setting, CAPIF (TIMER_EINTSTS[0]) will set to 1 and the current timer counter value (TIMER_CNT value) will be auto-loaded into this CAPDAT field.
<> 144:ef7eb2e8f9f7 25222 */
<> 144:ef7eb2e8f9f7 25223 __I uint32_t CAP;
<> 144:ef7eb2e8f9f7 25224
<> 144:ef7eb2e8f9f7 25225 /**
<> 144:ef7eb2e8f9f7 25226 * EXTCTL
<> 144:ef7eb2e8f9f7 25227 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25228 * Offset: 0x14 Timer External Control Register
<> 144:ef7eb2e8f9f7 25229 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25230 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25231 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25232 * |[0] |CNTPHASE |Timer External Count Phase
<> 144:ef7eb2e8f9f7 25233 * | | |This bit indicates the detection phase of external counting pin.
<> 144:ef7eb2e8f9f7 25234 * | | |0 = A falling edge of external counting pin will be counted.
<> 144:ef7eb2e8f9f7 25235 * | | |1 = A rising edge of external counting pin will be counted.
<> 144:ef7eb2e8f9f7 25236 * |[1:2] |CAPEDGE |Timer External Pin Edge Detect
<> 144:ef7eb2e8f9f7 25237 * | | |00 = A 1 to 0 transition on TMx_EXT (x= 0~3) pin will be detected.
<> 144:ef7eb2e8f9f7 25238 * | | |01 = A 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected.
<> 144:ef7eb2e8f9f7 25239 * | | |10 = Either 1 to 0 or 0 to 1 transition on TMx_EXT (x= 0~3) pin will be detected.
<> 144:ef7eb2e8f9f7 25240 * | | |11 = Reserved.
<> 144:ef7eb2e8f9f7 25241 * |[3] |CAPEN |Timer External Pin Enable
<> 144:ef7eb2e8f9f7 25242 * | | |This bit enables the CAPFUNCS (TIMER_EXTCTL[4]) function on the TMx_EXT pin.
<> 144:ef7eb2e8f9f7 25243 * | | |0 = CAPFUNCS function of TMx_EXT (x= 0~3) pin will be ignored.
<> 144:ef7eb2e8f9f7 25244 * | | |1 = CAPFUNCS function of TMx_EXT (x= 0~3) pin is active.
<> 144:ef7eb2e8f9f7 25245 * |[4] |CAPFUNCS |Timer External Reset Counter / Capture Mode Select
<> 144:ef7eb2e8f9f7 25246 * | | |0 = Transition on TMx_EXT (x= 0~3) pin is using to save the 24-bit timer counter value.
<> 144:ef7eb2e8f9f7 25247 * | | |(TIMER_CNT value) to timer capture value (TIMER_CAP value) if CAPIF (TIMER_EINTSTS[0]) is set to 1
<> 144:ef7eb2e8f9f7 25248 * | | |1 = Transition on TMx_EXT (x= 0~3) pin is using to reset the 24-bit timer counter value.
<> 144:ef7eb2e8f9f7 25249 * |[5] |CAPIEN |Timer External Interrupt Enable
<> 144:ef7eb2e8f9f7 25250 * | | |0 = TMx_EXT (x= 0~3) pin detection Interrupt Disabled.
<> 144:ef7eb2e8f9f7 25251 * | | |1 = TMx_EXT (x= 0~3) pin detection Interrupt Enabled.
<> 144:ef7eb2e8f9f7 25252 * | | |CAPIEN is used to enable timer external interrupt.
<> 144:ef7eb2e8f9f7 25253 * | | |If CAPIEN enabled, timer will rise an interrupt when CAPIF = 1.
<> 144:ef7eb2e8f9f7 25254 * | | |For example, while CAPIEN = 1, CAPEN = 1, and CAPEDGE = 00, a 1 to 0 transition on the TEX pin will cause the CAPIF(TIMER_EINTSTS[0]) interrupt flag to be set then the interrupt signal is generated and sent to NVIC to inform CPU.
<> 144:ef7eb2e8f9f7 25255 * |[6] |CAPDBEN |Timer External Capture Pin De-Bounce Enable
<> 144:ef7eb2e8f9f7 25256 * | | |0 = TMx_EXT (x= 0~3) pin de-bounce Disabled.
<> 144:ef7eb2e8f9f7 25257 * | | |1 = TMx_EXT (x= 0~3) pin de-bounce Enabled.
<> 144:ef7eb2e8f9f7 25258 * | | |If this bit is enabled, the edge detection of TMx_EXT pin is detected with de-bounce circuit.
<> 144:ef7eb2e8f9f7 25259 * |[7] |ECNTDBEN |Timer Counter Pin De-Bounce Enable
<> 144:ef7eb2e8f9f7 25260 * | | |0 = TMx (x= 0~3) pin de-bounce Disabled.
<> 144:ef7eb2e8f9f7 25261 * | | |1 = TMx (x= 0~3) pin de-bounce Enabled.
<> 144:ef7eb2e8f9f7 25262 * | | |If this bit is enabled, the edge detection of TMx pin is detected with de-bounce circuit.
<> 144:ef7eb2e8f9f7 25263 */
<> 144:ef7eb2e8f9f7 25264 __IO uint32_t EXTCTL;
<> 144:ef7eb2e8f9f7 25265
<> 144:ef7eb2e8f9f7 25266 /**
<> 144:ef7eb2e8f9f7 25267 * EINTSTS
<> 144:ef7eb2e8f9f7 25268 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25269 * Offset: 0x18 Timer External Interrupt Status Register
<> 144:ef7eb2e8f9f7 25270 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25271 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25272 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25273 * |[0] |CAPIF |Timer External Interrupt Flag
<> 144:ef7eb2e8f9f7 25274 * | | |This bit indicates the timer external interrupt flag status.
<> 144:ef7eb2e8f9f7 25275 * | | |When CAPEN (TIMER_EXTCTL[3]) bit is set, CAPFUNCS (TIMER_EXTCTL[4]) bit is 0, and a transition on TMx_EXT (x= 0~3) pin matched the CAPEDGE (TIMER_EXTCTL[2:1]) setting, this bit will set to 1 by hardware.
<> 144:ef7eb2e8f9f7 25276 * | | |0 = TMx_EXT (x= 0~3) pin interrupt did not occur.
<> 144:ef7eb2e8f9f7 25277 * | | |1 = TMx_EXT (x= 0~3) pin interrupt occurred.
<> 144:ef7eb2e8f9f7 25278 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25279 */
<> 144:ef7eb2e8f9f7 25280 __IO uint32_t EINTSTS;
<> 144:ef7eb2e8f9f7 25281
<> 144:ef7eb2e8f9f7 25282 } TIMER_T;
<> 144:ef7eb2e8f9f7 25283
<> 144:ef7eb2e8f9f7 25284 /**
<> 144:ef7eb2e8f9f7 25285 @addtogroup TIMER_CONST TIMER Bit Field Definition
<> 144:ef7eb2e8f9f7 25286 Constant Definitions for TIMER Controller
<> 144:ef7eb2e8f9f7 25287 @{ */
<> 144:ef7eb2e8f9f7 25288
<> 144:ef7eb2e8f9f7 25289 #define TIMER_CTL_PSC_Pos (0) /*!< TIMER CTL: PSC Position */
<> 144:ef7eb2e8f9f7 25290 #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) /*!< TIMER CTL: PSC Mask */
<> 144:ef7eb2e8f9f7 25291
<> 144:ef7eb2e8f9f7 25292 #define TIMER_CTL_CNTDATEN_Pos (16) /*!< TIMER CTL: CNTDATEN Position */
<> 144:ef7eb2e8f9f7 25293 #define TIMER_CTL_CNTDATEN_Msk (0x1ul << TIMER_CTL_CNTDATEN_Pos) /*!< TIMER CTL: CNTDATEN Mask */
<> 144:ef7eb2e8f9f7 25294
<> 144:ef7eb2e8f9f7 25295 #define TIMER_CTL_TOGDIS1_Pos (21) /*!< TIMER CTL: TOGDIS1 Position */
<> 144:ef7eb2e8f9f7 25296 #define TIMER_CTL_TOGDIS1_Msk (0x1ul << TIMER_CTL_TOGDIS1_Pos) /*!< TIMER CTL: TOGDIS1 Mask */
<> 144:ef7eb2e8f9f7 25297
<> 144:ef7eb2e8f9f7 25298 #define TIMER_CTL_TOGDIS2_Pos (22) /*!< TIMER CTL: TOGDIS2 Position */
<> 144:ef7eb2e8f9f7 25299 #define TIMER_CTL_TOGDIS2_Msk (0x1ul << TIMER_CTL_TOGDIS2_Pos) /*!< TIMER CTL: TOGDIS2 Mask */
<> 144:ef7eb2e8f9f7 25300
<> 144:ef7eb2e8f9f7 25301 #define TIMER_CTL_WKEN_Pos (23) /*!< TIMER CTL: WKEN Position */
<> 144:ef7eb2e8f9f7 25302 #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) /*!< TIMER CTL: WKEN Mask */
<> 144:ef7eb2e8f9f7 25303
<> 144:ef7eb2e8f9f7 25304 #define TIMER_CTL_EXTCNTEN_Pos (24) /*!< TIMER CTL: EXTCNTEN Position */
<> 144:ef7eb2e8f9f7 25305 #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) /*!< TIMER CTL: EXTCNTEN Mask */
<> 144:ef7eb2e8f9f7 25306
<> 144:ef7eb2e8f9f7 25307 #define TIMER_CTL_ACTSTS_Pos (25) /*!< TIMER CTL: ACTSTS Position */
<> 144:ef7eb2e8f9f7 25308 #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) /*!< TIMER CTL: ACTSTS Mask */
<> 144:ef7eb2e8f9f7 25309
<> 144:ef7eb2e8f9f7 25310 #define TIMER_CTL_RSTCNT_Pos (26) /*!< TIMER CTL: RSTCNT Position */
<> 144:ef7eb2e8f9f7 25311 #define TIMER_CTL_RSTCNT_Msk (0x1ul << TIMER_CTL_RSTCNT_Pos) /*!< TIMER CTL: RSTCNT Mask */
<> 144:ef7eb2e8f9f7 25312
<> 144:ef7eb2e8f9f7 25313 #define TIMER_CTL_OPMODE_Pos (27) /*!< TIMER CTL: OPMODE Position */
<> 144:ef7eb2e8f9f7 25314 #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) /*!< TIMER CTL: OPMODE Mask */
<> 144:ef7eb2e8f9f7 25315
<> 144:ef7eb2e8f9f7 25316 #define TIMER_CTL_INTEN_Pos (29) /*!< TIMER CTL: INTEN Position */
<> 144:ef7eb2e8f9f7 25317 #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) /*!< TIMER CTL: INTEN Mask */
<> 144:ef7eb2e8f9f7 25318
<> 144:ef7eb2e8f9f7 25319 #define TIMER_CTL_CNTEN_Pos (30) /*!< TIMER CTL: CNTEN Position */
<> 144:ef7eb2e8f9f7 25320 #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) /*!< TIMER CTL: CNTEN Mask */
<> 144:ef7eb2e8f9f7 25321
<> 144:ef7eb2e8f9f7 25322 #define TIMER_CTL_ICEDEBUG_Pos (31) /*!< TIMER CTL: ICEDEBUG Position */
<> 144:ef7eb2e8f9f7 25323 #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) /*!< TIMER CTL: ICEDEBUG Mask */
<> 144:ef7eb2e8f9f7 25324
<> 144:ef7eb2e8f9f7 25325 #define TIMER_CMP_CMPDAT_Pos (0) /*!< TIMER CMP: CMPDAT Position */
<> 144:ef7eb2e8f9f7 25326 #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) /*!< TIMER CMP: CMPDAT Mask */
<> 144:ef7eb2e8f9f7 25327
<> 144:ef7eb2e8f9f7 25328 #define TIMER_INTSTS_TIF_Pos (0) /*!< TIMER INTSTS: TIF Position */
<> 144:ef7eb2e8f9f7 25329 #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) /*!< TIMER INTSTS: TIF Mask */
<> 144:ef7eb2e8f9f7 25330
<> 144:ef7eb2e8f9f7 25331 #define TIMER_INTSTS_TWKF_Pos (1) /*!< TIMER INTSTS: TWKF Position */
<> 144:ef7eb2e8f9f7 25332 #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) /*!< TIMER INTSTS: TWKF Mask */
<> 144:ef7eb2e8f9f7 25333
<> 144:ef7eb2e8f9f7 25334 #define TIMER_CNT_TIMER_CNT_Pos (0) /*!< TIMER CNT: TIMER_CNT Position */
<> 144:ef7eb2e8f9f7 25335 #define TIMER_CNT_TIMER_CNT_Msk (0xfffffful << TIMER_CNT_TIMER_CNT_Pos) /*!< TIMER CNT: TIMER_CNT Mask */
<> 144:ef7eb2e8f9f7 25336
<> 144:ef7eb2e8f9f7 25337 #define TIMER_CAP_CAPDAT_Pos (0) /*!< TIMER CAP: CAPDAT Position */
<> 144:ef7eb2e8f9f7 25338 #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) /*!< TIMER CAP: CAPDAT Mask */
<> 144:ef7eb2e8f9f7 25339
<> 144:ef7eb2e8f9f7 25340 #define TIMER_EXTCTL_CNTPHASE_Pos (0) /*!< TIMER EXTCTL: CNTPHASE Position */
<> 144:ef7eb2e8f9f7 25341 #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) /*!< TIMER EXTCTL: CNTPHASE Mask */
<> 144:ef7eb2e8f9f7 25342
<> 144:ef7eb2e8f9f7 25343 #define TIMER_EXTCTL_CAPEDGE_Pos (1) /*!< TIMER EXTCTL: CAPEDGE Position */
<> 144:ef7eb2e8f9f7 25344 #define TIMER_EXTCTL_CAPEDGE_Msk (0x3ul << TIMER_EXTCTL_CAPEDGE_Pos) /*!< TIMER EXTCTL: CAPEDGE Mask */
<> 144:ef7eb2e8f9f7 25345
<> 144:ef7eb2e8f9f7 25346 #define TIMER_EXTCTL_CAPEN_Pos (3) /*!< TIMER EXTCTL: CAPEN Position */
<> 144:ef7eb2e8f9f7 25347 #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) /*!< TIMER EXTCTL: CAPEN Mask */
<> 144:ef7eb2e8f9f7 25348
<> 144:ef7eb2e8f9f7 25349 #define TIMER_EXTCTL_CAPFUNCS_Pos (4) /*!< TIMER EXTCTL: CAPFUNCS Position */
<> 144:ef7eb2e8f9f7 25350 #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< TIMER EXTCTL: CAPFUNCS Mask */
<> 144:ef7eb2e8f9f7 25351
<> 144:ef7eb2e8f9f7 25352 #define TIMER_EXTCTL_CAPIEN_Pos (5) /*!< TIMER EXTCTL: CAPIEN Position */
<> 144:ef7eb2e8f9f7 25353 #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) /*!< TIMER EXTCTL: CAPIEN Mask */
<> 144:ef7eb2e8f9f7 25354
<> 144:ef7eb2e8f9f7 25355 #define TIMER_EXTCTL_CAPDBEN_Pos (6) /*!< TIMER EXTCTL: CAPDBEN Position */
<> 144:ef7eb2e8f9f7 25356 #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) /*!< TIMER EXTCTL: CAPDBEN Mask */
<> 144:ef7eb2e8f9f7 25357
<> 144:ef7eb2e8f9f7 25358 #define TIMER_EXTCTL_ECNTDBEN_Pos (7) /*!< TIMER EXTCTL: ECNTDBEN Position */
<> 144:ef7eb2e8f9f7 25359 #define TIMER_EXTCTL_ECNTDBEN_Msk (0x1ul << TIMER_EXTCTL_ECNTDBEN_Pos) /*!< TIMER EXTCTL: ECNTDBEN Mask */
<> 144:ef7eb2e8f9f7 25360
<> 144:ef7eb2e8f9f7 25361 #define TIMER_EINTSTS_CAPIF_Pos (0) /*!< TIMER EINTSTS: CAPIF Position */
<> 144:ef7eb2e8f9f7 25362 #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) /*!< TIMER EINTSTS: CAPIF Mask */
<> 144:ef7eb2e8f9f7 25363
<> 144:ef7eb2e8f9f7 25364
<> 144:ef7eb2e8f9f7 25365 /**@}*/ /* TIMER_CONST */
<> 144:ef7eb2e8f9f7 25366 /**@}*/ /* end of TMR register group */
<> 144:ef7eb2e8f9f7 25367
<> 144:ef7eb2e8f9f7 25368
<> 144:ef7eb2e8f9f7 25369 /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
<> 144:ef7eb2e8f9f7 25370 /**
<> 144:ef7eb2e8f9f7 25371 @addtogroup UART Universal Asynchronous Receiver/Transmitter Controller(UART)
<> 144:ef7eb2e8f9f7 25372 Memory Mapped Structure for UART Controller
<> 144:ef7eb2e8f9f7 25373 @{ */
<> 144:ef7eb2e8f9f7 25374
<> 144:ef7eb2e8f9f7 25375 typedef struct {
<> 144:ef7eb2e8f9f7 25376
<> 144:ef7eb2e8f9f7 25377
<> 144:ef7eb2e8f9f7 25378 /**
<> 144:ef7eb2e8f9f7 25379 * DAT
<> 144:ef7eb2e8f9f7 25380 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25381 * Offset: 0x00 UARTx Receive / Transmit Buffer Register
<> 144:ef7eb2e8f9f7 25382 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25383 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25384 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25385 * |[0:7] |DAT |Receiving/Transmit Buffer
<> 144:ef7eb2e8f9f7 25386 * | | |Write Operation:
<> 144:ef7eb2e8f9f7 25387 * | | |By writing one byte to this register, the data byte will be stored in transmitter FIFO. The
<> 144:ef7eb2e8f9f7 25388 * | | |UART Controller will send out the data stored in transmitter FIFO top location through the
<> 144:ef7eb2e8f9f7 25389 * | | |UART_TXD.
<> 144:ef7eb2e8f9f7 25390 * | | |Read Operation:
<> 144:ef7eb2e8f9f7 25391 * | | |By reading this register, the UART will return an 8-bit data received from receiving FIFO
<> 144:ef7eb2e8f9f7 25392 */
<> 144:ef7eb2e8f9f7 25393 __IO uint32_t DAT;
<> 144:ef7eb2e8f9f7 25394
<> 144:ef7eb2e8f9f7 25395 /**
<> 144:ef7eb2e8f9f7 25396 * INTEN
<> 144:ef7eb2e8f9f7 25397 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25398 * Offset: 0x04 UARTx Interrupt Enable Register
<> 144:ef7eb2e8f9f7 25399 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25400 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25401 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25402 * |[0] |RDAIEN |Receive Data Available Interrupt Enable Control
<> 144:ef7eb2e8f9f7 25403 * | | |0 = INT_RDA Disabled.
<> 144:ef7eb2e8f9f7 25404 * | | |1 = INT_RDA Enabled.
<> 144:ef7eb2e8f9f7 25405 * |[1] |THREIEN |Transmit Holding Register Empty Interrupt Enable Control
<> 144:ef7eb2e8f9f7 25406 * | | |0 = INT_THRE Disabled.
<> 144:ef7eb2e8f9f7 25407 * | | |1 = INT_THRE Enabled.
<> 144:ef7eb2e8f9f7 25408 * |[2] |RLSIEN |Receive Line Status Interrupt Enable Control
<> 144:ef7eb2e8f9f7 25409 * | | |0 = INT_RLS Disabled.
<> 144:ef7eb2e8f9f7 25410 * | | |1 = INT_RLS Enabled.
<> 144:ef7eb2e8f9f7 25411 * |[3] |MODEMIEN |Modem Status Interrupt Enable Control
<> 144:ef7eb2e8f9f7 25412 * | | |0 = INT_MODEM Disabled.
<> 144:ef7eb2e8f9f7 25413 * | | |1 = INT_MODEM Enabled.
<> 144:ef7eb2e8f9f7 25414 * |[4] |RXTOIEN |RX Time-Out Interrupt Enable Control
<> 144:ef7eb2e8f9f7 25415 * | | |0 = NT_TOUT Disabled.
<> 144:ef7eb2e8f9f7 25416 * | | |1 = INT_TOUT Enabled.
<> 144:ef7eb2e8f9f7 25417 * |[5] |BUFERRIEN |Buffer Error Interrupt Enable Control
<> 144:ef7eb2e8f9f7 25418 * | | |0 = INT_BUF_ERR Disabled.
<> 144:ef7eb2e8f9f7 25419 * | | |1 = INT_BUF_ERR Enabled.
<> 144:ef7eb2e8f9f7 25420 * |[6] |WKCTSIEN |UART Wake-Up Function Enable Control
<> 144:ef7eb2e8f9f7 25421 * | | |0 = UART wake-up function Disabled.
<> 144:ef7eb2e8f9f7 25422 * | | |1 = UART wake-up function Enabled when the chip is in Power-down mode, an external CTS change will wake up chip from Power-down mode.
<> 144:ef7eb2e8f9f7 25423 * |[8] |LINIEN |LIN RX Break Field Detected Interrupt Enable Control
<> 144:ef7eb2e8f9f7 25424 * | | |0 = Lin bus RX break filed interrupt Disabled.
<> 144:ef7eb2e8f9f7 25425 * | | |1 = Lin bus RX break filed interrupt Enabled.
<> 144:ef7eb2e8f9f7 25426 * | | |Note: This field is used for LIN function mode.
<> 144:ef7eb2e8f9f7 25427 * |[11] |TOCNTEN |Time-Out Counter Enable Control
<> 144:ef7eb2e8f9f7 25428 * | | |0 = Time-out counter Disabled.
<> 144:ef7eb2e8f9f7 25429 * | | |1 = Time-out counter Enabled.
<> 144:ef7eb2e8f9f7 25430 * |[12] |ATORTSEN |RTS Auto Flow Control Enable Control
<> 144:ef7eb2e8f9f7 25431 * | | |0 = RTS auto flow control Disabled.
<> 144:ef7eb2e8f9f7 25432 * | | |1 = RTS auto flow control Enabled.
<> 144:ef7eb2e8f9f7 25433 * | | |When RTS auto-flow is enabled, if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]), the UART will de-assert RTS signal.
<> 144:ef7eb2e8f9f7 25434 * |[13] |ATOCTSEN |CTS Auto Flow Control Enable Control
<> 144:ef7eb2e8f9f7 25435 * | | |0 = CTS auto flow control Disabled.
<> 144:ef7eb2e8f9f7 25436 * | | |1 = CTS auto flow control Enabled.
<> 144:ef7eb2e8f9f7 25437 * | | |When CTS auto-flow is enabled, the UART will send data to external device when CTS input assert (UART will not send data to device until CTS is asserted).
<> 144:ef7eb2e8f9f7 25438 * |[14] |TXPDMAEN |TX DMA Enable Control
<> 144:ef7eb2e8f9f7 25439 * | | |This bit can enable or disable TX DMA service.
<> 144:ef7eb2e8f9f7 25440 * | | |0 = TX DMA Disabled.
<> 144:ef7eb2e8f9f7 25441 * | | |1 = TX DMA Enabled.
<> 144:ef7eb2e8f9f7 25442 * |[15] |RXPDMAEN |RX DMA Enable Control
<> 144:ef7eb2e8f9f7 25443 * | | |This bit can enable or disable RX DMA service.
<> 144:ef7eb2e8f9f7 25444 * | | |0 = RX DMA Disabled.
<> 144:ef7eb2e8f9f7 25445 * | | |1 = RX DMA Enabled.
<> 144:ef7eb2e8f9f7 25446 */
<> 144:ef7eb2e8f9f7 25447 __IO uint32_t INTEN;
<> 144:ef7eb2e8f9f7 25448
<> 144:ef7eb2e8f9f7 25449 /**
<> 144:ef7eb2e8f9f7 25450 * FIFO
<> 144:ef7eb2e8f9f7 25451 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25452 * Offset: 0x08 UARTx FIFO Control Register
<> 144:ef7eb2e8f9f7 25453 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25454 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25455 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25456 * |[1] |RXRST |RX Field Software Reset
<> 144:ef7eb2e8f9f7 25457 * | | |When RX_RST is set, all the byte in the receiver FIFO and RX internal state machine are cleared.
<> 144:ef7eb2e8f9f7 25458 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 25459 * | | |1 = Reset the RX internal state machine and pointers.
<> 144:ef7eb2e8f9f7 25460 * | | |Note: This bit will be automatically cleared for at least 3 UART engine clock cycles.
<> 144:ef7eb2e8f9f7 25461 * |[2] |TXRST |TX Field Software Reset
<> 144:ef7eb2e8f9f7 25462 * | | |When TX_RST is set, all the byte in the transmit FIFO and TX internal state machine are cleared.
<> 144:ef7eb2e8f9f7 25463 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 25464 * | | |1 = Reset the TX internal state machine and pointers.
<> 144:ef7eb2e8f9f7 25465 * | | |Note: This bit will auto clear needs at least 3 UART engine clock cycles.
<> 144:ef7eb2e8f9f7 25466 * |[4:7] |RFITL |RX FIFO Interrupt (INT_RDA) Trigger Level
<> 144:ef7eb2e8f9f7 25467 * | | |When the number of bytes in the receive FIFO equals the RFITL, the RDAIF will be set (if RDAIEN (UART_INTEN [0]) is enabled, an interrupt will generated).
<> 144:ef7eb2e8f9f7 25468 * | | |0000 = 1 byte
<> 144:ef7eb2e8f9f7 25469 * | | |0001 = 4 bytes
<> 144:ef7eb2e8f9f7 25470 * | | |0010 = 8 bytes
<> 144:ef7eb2e8f9f7 25471 * | | |0011 = 14 bytes
<> 144:ef7eb2e8f9f7 25472 * | | |0100 = 30/14 bytes (High-speed/Normal Speed)
<> 144:ef7eb2e8f9f7 25473 * | | |0101 = 46/14 bytes (High-speed/Normal Speed)
<> 144:ef7eb2e8f9f7 25474 * | | |0110 = 62/14 bytes (High-speed/Normal Speed)
<> 144:ef7eb2e8f9f7 25475 * | | |others = 62/14 bytes (High-speed/Normal Speed)
<> 144:ef7eb2e8f9f7 25476 * |[8] |RXOFF |Receiver Disable
<> 144:ef7eb2e8f9f7 25477 * | | |The receiver is disabled or not.
<> 144:ef7eb2e8f9f7 25478 * | | |0 = Receiver Enabled.
<> 144:ef7eb2e8f9f7 25479 * | | |1 = Receiver Disabled.
<> 144:ef7eb2e8f9f7 25480 * | | |Note: This field is used for RS-485 Normal Multi-drop mode.
<> 144:ef7eb2e8f9f7 25481 * | | |It should be programmed before RS-485_NMM (UART_ALTCTL [8]) is programmed.
<> 144:ef7eb2e8f9f7 25482 * |[16:19] |RTSTRGLV |RTS Trigger Level For Auto-Flow Control Use
<> 144:ef7eb2e8f9f7 25483 * | | |0000 = 01 byte
<> 144:ef7eb2e8f9f7 25484 * | | |0001 = 04 bytes
<> 144:ef7eb2e8f9f7 25485 * | | |0010 = 08 bytes
<> 144:ef7eb2e8f9f7 25486 * | | |0011 = 14 bytes
<> 144:ef7eb2e8f9f7 25487 * | | |0100 = 30/14 bytes (High-speed/Normal Speed)
<> 144:ef7eb2e8f9f7 25488 * | | |0101 = 46/14 bytes (High-speed/Normal Speed)
<> 144:ef7eb2e8f9f7 25489 * | | |0110 = 62/14 bytes (High-speed/Normal Speed)
<> 144:ef7eb2e8f9f7 25490 * | | |others = 62/14 bytes (High-speed/Normal Speed)
<> 144:ef7eb2e8f9f7 25491 * | | |Note: This field is used for auto RTS flow control.
<> 144:ef7eb2e8f9f7 25492 */
<> 144:ef7eb2e8f9f7 25493 __IO uint32_t FIFO;
<> 144:ef7eb2e8f9f7 25494
<> 144:ef7eb2e8f9f7 25495 /**
<> 144:ef7eb2e8f9f7 25496 * LINE
<> 144:ef7eb2e8f9f7 25497 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25498 * Offset: 0x0C UARTx Line Control Register
<> 144:ef7eb2e8f9f7 25499 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25500 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25501 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25502 * |[0:1] |WLS |Word Length Selection
<> 144:ef7eb2e8f9f7 25503 * | | |00 = 5-bit
<> 144:ef7eb2e8f9f7 25504 * | | |01 = 6-bit
<> 144:ef7eb2e8f9f7 25505 * | | |10 = 7-bit
<> 144:ef7eb2e8f9f7 25506 * | | |11 = 8-bit
<> 144:ef7eb2e8f9f7 25507 * |[2] |NSB |Number Of "STOP Bit"
<> 144:ef7eb2e8f9f7 25508 * | | |0= One " STOP bit" is generated in the transmitted data.
<> 144:ef7eb2e8f9f7 25509 * | | |1= One and a half " STOP bit" is generated in the transmitted data when 5-bit word length is selected.
<> 144:ef7eb2e8f9f7 25510 * | | |Two "STOP bit" is generated when 6-, 7- and 8-bit word length is selected.
<> 144:ef7eb2e8f9f7 25511 * |[3] |PBE |Parity Bit Enable Control
<> 144:ef7eb2e8f9f7 25512 * | | |0 = No parity bit.
<> 144:ef7eb2e8f9f7 25513 * | | |1 = Parity bit is generated on each outgoing character and is checked on each incoming data.
<> 144:ef7eb2e8f9f7 25514 * |[4] |EPE |Even Parity Enable Control
<> 144:ef7eb2e8f9f7 25515 * | | |0 = Odd number of logic 1's is transmitted and checked in each word.
<> 144:ef7eb2e8f9f7 25516 * | | |1 = Even number of logic 1's is transmitted and checked in each word.
<> 144:ef7eb2e8f9f7 25517 * | | |This bit is effective only when bit 3 (parity bit enable) is set.
<> 144:ef7eb2e8f9f7 25518 * |[5] |SPE |Stick Parity Enable Control
<> 144:ef7eb2e8f9f7 25519 * | | |0 = Stick parity Disabled.
<> 144:ef7eb2e8f9f7 25520 * | | |1 = If bit 3 and 4 are logic 1, the parity bit is transmitted and checked as logic 0.
<> 144:ef7eb2e8f9f7 25521 * | | |If bit 3 is 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1.
<> 144:ef7eb2e8f9f7 25522 * |[6] |BCB |Break Control
<> 144:ef7eb2e8f9f7 25523 * | | |When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State (logic 0).
<> 144:ef7eb2e8f9f7 25524 * | | |This bit acts only on TX and has no effect on the transmitter logic.
<> 144:ef7eb2e8f9f7 25525 */
<> 144:ef7eb2e8f9f7 25526 __IO uint32_t LINE;
<> 144:ef7eb2e8f9f7 25527
<> 144:ef7eb2e8f9f7 25528 /**
<> 144:ef7eb2e8f9f7 25529 * MODEM
<> 144:ef7eb2e8f9f7 25530 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25531 * Offset: 0x10 UARTx Modem Control Register
<> 144:ef7eb2e8f9f7 25532 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25533 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25534 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25535 * |[1] |RTS |RTS (Request-To-Send) Signal
<> 144:ef7eb2e8f9f7 25536 * | | |0 = Drive RTS pin to logic 1 (If the RTSACTLV
<> 144:ef7eb2e8f9f7 25537 * | | |set to low level triggered).
<> 144:ef7eb2e8f9f7 25538 * | | |1 = Drive RTS pin to logic 0 (If the RTSACTLV set to low level triggered).
<> 144:ef7eb2e8f9f7 25539 * | | |0 = Drive RTS pin to logic 0 (If the RTSACTLV
<> 144:ef7eb2e8f9f7 25540 * | | |set to high level triggered).
<> 144:ef7eb2e8f9f7 25541 * | | |1 = Drive RTS pin to logic 1 (If the RTSACTLV set to high level triggered).
<> 144:ef7eb2e8f9f7 25542 * |[9] |RTSACTLV |RTS Trigger Level
<> 144:ef7eb2e8f9f7 25543 * | | |This bit can change the RTS trigger level.
<> 144:ef7eb2e8f9f7 25544 * | | |0= Low level triggered.
<> 144:ef7eb2e8f9f7 25545 * | | |1= High level triggered.
<> 144:ef7eb2e8f9f7 25546 * |[13] |RTSSTS |RTS Pin State (Read Only)
<> 144:ef7eb2e8f9f7 25547 * | | |This bit is the output pin status of RTS.
<> 144:ef7eb2e8f9f7 25548 */
<> 144:ef7eb2e8f9f7 25549 __IO uint32_t MODEM;
<> 144:ef7eb2e8f9f7 25550
<> 144:ef7eb2e8f9f7 25551 /**
<> 144:ef7eb2e8f9f7 25552 * MODEMSTS
<> 144:ef7eb2e8f9f7 25553 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25554 * Offset: 0x14 UARTx Modem Status Register
<> 144:ef7eb2e8f9f7 25555 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25556 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25557 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25558 * |[0] |CTSDETF |Detect CTS State Change Flag (Read Only)
<> 144:ef7eb2e8f9f7 25559 * | | |This bit is set whenever CTS input has change state, and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.
<> 144:ef7eb2e8f9f7 25560 * | | |Software can write 1 to clear this bit to 0
<> 144:ef7eb2e8f9f7 25561 * |[4] |CTSSTS |CTS Pin Status (Read Only)
<> 144:ef7eb2e8f9f7 25562 * | | |This bit is the pin status of CTS.
<> 144:ef7eb2e8f9f7 25563 * |[8] |CTSACTLV |CTS Trigger Level
<> 144:ef7eb2e8f9f7 25564 * | | |This bit can change the CTS trigger level.
<> 144:ef7eb2e8f9f7 25565 * | | |0= Low level triggered.
<> 144:ef7eb2e8f9f7 25566 * | | |1= High level triggered.
<> 144:ef7eb2e8f9f7 25567 */
<> 144:ef7eb2e8f9f7 25568 __IO uint32_t MODEMSTS;
<> 144:ef7eb2e8f9f7 25569
<> 144:ef7eb2e8f9f7 25570 /**
<> 144:ef7eb2e8f9f7 25571 * FIFOSTS
<> 144:ef7eb2e8f9f7 25572 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25573 * Offset: 0x18 UARTx FIFO Status Register
<> 144:ef7eb2e8f9f7 25574 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25575 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25576 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25577 * |[0] |RXOVIF |RX Overflow Error IF (Read Only)
<> 144:ef7eb2e8f9f7 25578 * | | |This bit is set when RX FIFO overflow.
<> 144:ef7eb2e8f9f7 25579 * | | |If the number of bytes of received data is greater than RX_FIFO (UART_DAT) size, 64/16 bytes of UART0/UART1, this bit will be set.
<> 144:ef7eb2e8f9f7 25580 * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 25581 * |[2] |SCERR |Smart Card Over Error Retry Flag
<> 144:ef7eb2e8f9f7 25582 * | | |It is set to 1 when transmitter re-transmits over the retry number (TXRTY (UART_SCCTL[6:4])) or the receiver transfer error retry over retry number (RXRTY (UART_SCCTL[2:0]))
<> 144:ef7eb2e8f9f7 25583 * | | |0 = No any transmitter re-transmits over or receiver transfer error retry over.
<> 144:ef7eb2e8f9f7 25584 * | | |1 = one of the transmitter re-transmits over active or receiver transfer error retry over active.
<> 144:ef7eb2e8f9f7 25585 * | | |Note1: This field is used for SC function mode.
<> 144:ef7eb2e8f9f7 25586 * | | |Note2: This bit is read only, but it can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 25587 * |[3] |ADDRDETF |RS-485 Address Byte Detection Flag (Read Only)
<> 144:ef7eb2e8f9f7 25588 * | | |This bit is set to logic 1 and set RS-485_ADD_EN (UART_ALTCTL[15]) whenever in RS-485 mode the receiver detect any address byte received address byte character (bit9 = '1') bit, and it is reset whenever the CPU writes 1 to this bit.
<> 144:ef7eb2e8f9f7 25589 * | | |Note1: This field is used for RS-485 function mode.
<> 144:ef7eb2e8f9f7 25590 * | | |Note2: This bit is read only, but it can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 25591 * |[4] |PEF |Parity Error Flag (Read Only)
<> 144:ef7eb2e8f9f7 25592 * | | |This bit is set to logic 1 whenever the received character does not have a valid "parity bit", and is reset whenever the CPU writes 1 to this bit.
<> 144:ef7eb2e8f9f7 25593 * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 25594 * |[5] |FEF |Framing Error Flag (Read Only)
<> 144:ef7eb2e8f9f7 25595 * | | |This bit is set to logic 1 whenever the received character does not have a valid "stop bit" (that is, the stop bit following the last data bit or parity bit is detected as a logic 0), and is reset whenever the CPU writes 1 to this bit.
<> 144:ef7eb2e8f9f7 25596 * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 25597 * |[6] |BIF |Break Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25598 * | | |This bit is set to a logic 1 whenever the received data input(RX) is held in the "spacing state" (logic 0) for longer than a full word transmission time (that is, the total time of "start bit" + data bits + parity + stop bits) and is reset whenever the CPU writes 1 to this bit.
<> 144:ef7eb2e8f9f7 25599 * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 25600 * |[8:13] |RXPTR |RX FIFO Pointer (Read Only)
<> 144:ef7eb2e8f9f7 25601 * | | |This field indicates the RX FIFO Buffer Pointer.
<> 144:ef7eb2e8f9f7 25602 * | | |When UART receives one byte from external device, RXPTR increases one.
<> 144:ef7eb2e8f9f7 25603 * | | |When one byte of RX FIFO is read by CPU, RXPTR decreases one.
<> 144:ef7eb2e8f9f7 25604 * |[14] |RXEMPTY |Receiver FIFO Empty (Read Only)
<> 144:ef7eb2e8f9f7 25605 * | | |This bit initiate RX FIFO empty or not.
<> 144:ef7eb2e8f9f7 25606 * | | |When the last byte of RX FIFO has been read by CPU, hardware sets this bit high.
<> 144:ef7eb2e8f9f7 25607 * | | |It will be cleared when UART receives any new data.
<> 144:ef7eb2e8f9f7 25608 * |[15] |RXFULL |Receiver FIFO Full (Read Only)
<> 144:ef7eb2e8f9f7 25609 * | | |This bit initiates RX FIFO full or not.
<> 144:ef7eb2e8f9f7 25610 * | | |This bit is set when RXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
<> 144:ef7eb2e8f9f7 25611 * |[16:21] |TXPTR |TX FIFO Pointer (Read Only)
<> 144:ef7eb2e8f9f7 25612 * | | |This field indicates the TX FIFO Buffer Pointer.
<> 144:ef7eb2e8f9f7 25613 * | | |When CPU writes one byte into UART_DAT, TXPTR increases one.
<> 144:ef7eb2e8f9f7 25614 * | | |When one byte of TX FIFO is transferred to Transmitter Shift Register, TXPTR decreases one.
<> 144:ef7eb2e8f9f7 25615 * |[22] |TXEMPTY |Transmitter FIFO Empty (Read Only)
<> 144:ef7eb2e8f9f7 25616 * | | |This bit indicates TX FIFO empty or not.
<> 144:ef7eb2e8f9f7 25617 * | | |When the last byte of TX FIFO has been transferred to Transmitter Shift Register, hardware sets this bit high.
<> 144:ef7eb2e8f9f7 25618 * | | |It will be cleared when writing data into DAT (TX FIFO not empty).
<> 144:ef7eb2e8f9f7 25619 * |[23] |TX_FULL |Transmitter FIFO Full (Read Only)
<> 144:ef7eb2e8f9f7 25620 * | | |This bit indicates TX FIFO full or not.
<> 144:ef7eb2e8f9f7 25621 * | | |This bit is set when TXPTR is equal to 64/16(UART0/UART1~5), otherwise is cleared by hardware.
<> 144:ef7eb2e8f9f7 25622 * |[24] |TXOVIF |TX Overflow Error Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25623 * | | |If TX FIFO (UART_DAT) is full, an additional write to UART_DAT will cause this bit to
<> 144:ef7eb2e8f9f7 25624 * | | |logic 1.
<> 144:ef7eb2e8f9f7 25625 * | | |Note: This bit is read only, but it can be cleared by writing '1' to it.
<> 144:ef7eb2e8f9f7 25626 * |[28] |TXEMPTYF |Transmitter Empty Flag (Read Only)
<> 144:ef7eb2e8f9f7 25627 * | | |Bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.
<> 144:ef7eb2e8f9f7 25628 * | | |Bit is cleared automatically when TX FIFO is not empty or the last byte transmission has not completed.
<> 144:ef7eb2e8f9f7 25629 */
<> 144:ef7eb2e8f9f7 25630 __IO uint32_t FIFOSTS;
<> 144:ef7eb2e8f9f7 25631
<> 144:ef7eb2e8f9f7 25632 /**
<> 144:ef7eb2e8f9f7 25633 * INTSTS
<> 144:ef7eb2e8f9f7 25634 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25635 * Offset: 0x1C UARTx Interrupt Status Register
<> 144:ef7eb2e8f9f7 25636 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25637 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25638 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25639 * |[0] |RDAIF |Receive Data Available Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25640 * | | |When the number of bytes in the RX FIFO equals the RFITL then the RDAIF will be set.
<> 144:ef7eb2e8f9f7 25641 * | | |If RDAIEN bit (UART_INTEN[0]) is enabled, the RDA interrupt will be generated.
<> 144:ef7eb2e8f9f7 25642 * | | |Note: This bit is read only and it will be cleared when the number of unread bytes of RX FIFO drops below the threshold level (RFITL).
<> 144:ef7eb2e8f9f7 25643 * |[1] |THREIF |Transmit Holding Register Empty Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25644 * | | |This bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register.
<> 144:ef7eb2e8f9f7 25645 * | | |If THREIEN bit (UART_INTEN[1]) is enabled, the THRE interrupt will be generated.
<> 144:ef7eb2e8f9f7 25646 * | | |Note: This bit is read only and it will be cleared when writing data into DAT (TX FIFO not empty).
<> 144:ef7eb2e8f9f7 25647 * |[2] |RLSIF |Receive Line Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25648 * | | |This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set).
<> 144:ef7eb2e8f9f7 25649 * | | |If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
<> 144:ef7eb2e8f9f7 25650 * | | |Note1: In RS-485 function mode, this field include receiver detect any address byte received address byte character (bit9 = '1') bit.
<> 144:ef7eb2e8f9f7 25651 * | | |Note2: In SC function mode, this field includes error retry over flag .
<> 144:ef7eb2e8f9f7 25652 * | | |Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
<> 144:ef7eb2e8f9f7 25653 * |[3] |MODENIF |MODEM Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25654 * | | |This bit is set when the CTS pin has state change (CTSDETF=1).
<> 144:ef7eb2e8f9f7 25655 * | | |If MODEMIEN bit (UART_INTEN[3]) is enabled, the Modem interrupt will be generated.
<> 144:ef7eb2e8f9f7 25656 * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
<> 144:ef7eb2e8f9f7 25657 * |[4] |RXTOIF |Time-Out Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25658 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
<> 144:ef7eb2e8f9f7 25659 * | | |If TIME_OUT_IEN bit (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated.
<> 144:ef7eb2e8f9f7 25660 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
<> 144:ef7eb2e8f9f7 25661 * |[5] |BUFERRIF |Buffer Error Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25662 * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set).
<> 144:ef7eb2e8f9f7 25663 * | | |When BERRIF is set, the transfer maybe is not correct.
<> 144:ef7eb2e8f9f7 25664 * | | |If BUFERRIEN bit (UART_INTEN[5]) is enabled, the buffer error interrupt will be generated.
<> 144:ef7eb2e8f9f7 25665 * | | |Note: This bit is cleared when both TXOVIF and RXOVIF are cleared.
<> 144:ef7eb2e8f9f7 25666 * |[7] |LIN_IF |LIN Bus Flag (Read Only)
<> 144:ef7eb2e8f9f7 25667 * | | |This bit is set when LIN slave header detect (SLVHDETF=1), LIN break detect (BRKDETF=1), bit error detect (BITEF=1), LIN slave ID parity error (SLVIDPEF) or LIN slave header error detect (SLVHEF) If LIN_RX_BRK_ IEN bit (UART_INTEN[8]) is enabled the LIN interrupt will be generated.
<> 144:ef7eb2e8f9f7 25668 * | | |Note: This bit is cleared when both SLVHDETF and LIN_BRDER_F and BITEF and LINS_IDPENR_F and SLVHEF are cleared
<> 144:ef7eb2e8f9f7 25669 * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25670 * | | |This bit is set if RDAIEN and RDAIF are both set to 1.
<> 144:ef7eb2e8f9f7 25671 * | | |0 = No RDA interrupt is generated.
<> 144:ef7eb2e8f9f7 25672 * | | |1 = RDA interrupt is generated.
<> 144:ef7eb2e8f9f7 25673 * |[9] |THREINT |Transmit Holding Register Empty Interrupt
<> 144:ef7eb2e8f9f7 25674 * | | |Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25675 * | | |This bit is set if THREIEN and THREIF are both set to 1.
<> 144:ef7eb2e8f9f7 25676 * | | |0 = No THRE interrupt is generated.
<> 144:ef7eb2e8f9f7 25677 * | | |1 = THRE interrupt is generated.
<> 144:ef7eb2e8f9f7 25678 * |[10] |RLSINT |Receive Line Status Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25679 * | | |This bit is set if RLSIEN and RLSIF are both set to 1.
<> 144:ef7eb2e8f9f7 25680 * | | |0 = No RLS interrupt is generated.
<> 144:ef7eb2e8f9f7 25681 * | | |1 = RLS interrupt is generated.
<> 144:ef7eb2e8f9f7 25682 * |[11] |MODEMINT |MODEM Status Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25683 * | | |This bit is set if MODEMIEN and MODENIF are both set to 1.
<> 144:ef7eb2e8f9f7 25684 * | | |0 = No Modem interrupt is generated.
<> 144:ef7eb2e8f9f7 25685 * | | |1 = Modem interrupt is generated.
<> 144:ef7eb2e8f9f7 25686 * |[12] |RXTOINT |Time-Out Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25687 * | | |This bit is set if TOUT_IEN and RXTOIF are both set to 1.
<> 144:ef7eb2e8f9f7 25688 * | | |0 = No Tout interrupt is generated.
<> 144:ef7eb2e8f9f7 25689 * | | |1 = Tout interrupt is generated.
<> 144:ef7eb2e8f9f7 25690 * |[13] |BUFERRINT |Buffer Error Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25691 * | | |This bit is set if BUFERRIEN and BERRIF are both set to 1.
<> 144:ef7eb2e8f9f7 25692 * | | |0 = No buffer error interrupt is generated.
<> 144:ef7eb2e8f9f7 25693 * | | |1 = The buffer error interrupt is generated.
<> 144:ef7eb2e8f9f7 25694 * |[15] |LININT |LIN Bus Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25695 * | | |This bit is set if LIN_IEN and LIN_RX_BREAK_IF are both set to 1.
<> 144:ef7eb2e8f9f7 25696 * | | |0 = No LIN RX Break interrupt is generated.
<> 144:ef7eb2e8f9f7 25697 * | | |1 = LIN RX Break interrupt is generated.
<> 144:ef7eb2e8f9f7 25698 * |[18] |HWRLSIF |In DMA Mode, Receive Line Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 25699 * | | |This bit is set when the RX receive data have parity error, framing error or break error (at least one of 3 bits, BIF, FEF and PEF, is set).
<> 144:ef7eb2e8f9f7 25700 * | | |If RLSIEN bit (UART_INTEN[2]) is enabled, the RLS interrupt will be generated.
<> 144:ef7eb2e8f9f7 25701 * | | |Note1: In RS-485 function mode, this field includes receiver detect any address byte received address byte character (bit9 = '1') bit.
<> 144:ef7eb2e8f9f7 25702 * | | |Note2: In SC function mode, this field includes error retry over flag.
<> 144:ef7eb2e8f9f7 25703 * | | |Note3: This bit is read only and reset to 0 when all bits of BIF, FEF and PEF are cleared.
<> 144:ef7eb2e8f9f7 25704 * |[19] |HWMODIF |In DMA Mode, MODEM Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25705 * | | |This bit is set when the CTS pin has state change (CTSDETF = 1).
<> 144:ef7eb2e8f9f7 25706 * | | |If MODEMIEN (UART_INTEN[3]) is enabled, the Modem interrupt will be generated.
<> 144:ef7eb2e8f9f7 25707 * | | |Note: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF.
<> 144:ef7eb2e8f9f7 25708 * |[20] |HWTOIF |In DMA Mode, Time-Out Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25709 * | | |This bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC.
<> 144:ef7eb2e8f9f7 25710 * | | |If TIME_OUT_IEN (UART_INTEN[11]) is enabled, the Time-out interrupt will be generated.
<> 144:ef7eb2e8f9f7 25711 * | | |Note: This bit is read only and user can read UART_DAT (RX is in active) to clear it.
<> 144:ef7eb2e8f9f7 25712 * |[21] |HWBUFEIF |In DMA Mode, Buffer Error Interrupt Flag (Read Only)
<> 144:ef7eb2e8f9f7 25713 * | | |This bit is set when the TX or RX FIFO overflows (TXOVIF or RXOVIF is set).
<> 144:ef7eb2e8f9f7 25714 * | | |When BERRIF is set, the transfer maybe is not correct.
<> 144:ef7eb2e8f9f7 25715 * | | |If BUFERRIEN bit (UART_INTEN [5]) is enabled, the buffer error interrupt will be generated.
<> 144:ef7eb2e8f9f7 25716 * | | |Note: This bit is cleared when both TXOVIF and RXOVIF are cleared.
<> 144:ef7eb2e8f9f7 25717 * |[26] |HWRLSINT |In DMA Mode, Receive Line Status Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25718 * | | |This bit is set if RLSIEN and HWRLSIF are both set to 1.
<> 144:ef7eb2e8f9f7 25719 * | | |0 = No RLS interrupt is generated in DMA mode.
<> 144:ef7eb2e8f9f7 25720 * | | |1 = RLS interrupt is generated in DMA mode.
<> 144:ef7eb2e8f9f7 25721 * |[27] |HWMODINT |In DMA Mode, MODEM Status Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25722 * | | |This bit is set if MODEMIEN and HWMODIF are both set to 1.
<> 144:ef7eb2e8f9f7 25723 * | | |0 = No Modem interrupt is generated in DMA mode.
<> 144:ef7eb2e8f9f7 25724 * | | |1 = Modem interrupt is generated in DMA mode.
<> 144:ef7eb2e8f9f7 25725 * |[28] |HWTOINT |In DMA Mode, Time-Out Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25726 * | | |This bit is set if TOUT_IEN and HWTOIF are both set to 1.
<> 144:ef7eb2e8f9f7 25727 * | | |0 = No Tout interrupt is generated in DMA mode.
<> 144:ef7eb2e8f9f7 25728 * | | |1 = Tout interrupt is generated in DMA mode.
<> 144:ef7eb2e8f9f7 25729 * |[29] |HWBUFEINT |In DMA Mode, Buffer Error Interrupt Indicator (Read Only)
<> 144:ef7eb2e8f9f7 25730 * | | |This bit is set if BUFERRIEN and HWBFERIF are both set to 1.
<> 144:ef7eb2e8f9f7 25731 * | | |0 = No buffer error interrupt is generated in DMA mode.
<> 144:ef7eb2e8f9f7 25732 * | | |1 = The buffer error interrupt is generated in DMA mode.
<> 144:ef7eb2e8f9f7 25733 */
<> 144:ef7eb2e8f9f7 25734 __IO uint32_t INTSTS;
<> 144:ef7eb2e8f9f7 25735
<> 144:ef7eb2e8f9f7 25736 /**
<> 144:ef7eb2e8f9f7 25737 * TOUT
<> 144:ef7eb2e8f9f7 25738 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25739 * Offset: 0x20 UARTx Time-out Register
<> 144:ef7eb2e8f9f7 25740 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25741 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25742 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25743 * |[0:7] |TOIC |Time-Out Interrupt Comparator
<> 144:ef7eb2e8f9f7 25744 * | | |The time-out counter resets and starts counting (the counting clock = baud rate clock) whenever the RX FIFO receives a new data word.
<> 144:ef7eb2e8f9f7 25745 * | | |Once the content of time-out counter (TOUT_CNT) is equal to that of time-out interrupt comparator (TOIC), a receiver time-out interrupt (INT_TOUT) is generated if RXTOIEN (UART_INTEN[4]).
<> 144:ef7eb2e8f9f7 25746 * | | |A new incoming data word or RX FIFO empty clears INT_TOUT.
<> 144:ef7eb2e8f9f7 25747 * | | |In order to avoid receiver time-out interrupt generation immediately during one character is being received, TOIC value should be set between 40 and 255.
<> 144:ef7eb2e8f9f7 25748 * | | |So, for example, if TOIC is set with 40, the time-out interrupt is generated after four characters are not received when 1 stop bit and no parity check is set for UART transfer.
<> 144:ef7eb2e8f9f7 25749 * |[8:15] |DLY |TX Delay Time Value
<> 144:ef7eb2e8f9f7 25750 * | | |This field is use to programming the transfer delay time between the last stop bit and next start bit.
<> 144:ef7eb2e8f9f7 25751 * | | |Note: The counter clock is baud rate clock
<> 144:ef7eb2e8f9f7 25752 */
<> 144:ef7eb2e8f9f7 25753 __IO uint32_t TOUT;
<> 144:ef7eb2e8f9f7 25754
<> 144:ef7eb2e8f9f7 25755 /**
<> 144:ef7eb2e8f9f7 25756 * BAUD
<> 144:ef7eb2e8f9f7 25757 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25758 * Offset: 0x24 UARTx Baud Rate Divisor Register
<> 144:ef7eb2e8f9f7 25759 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25760 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25761 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25762 * |[0:15] |BRD |Baud Rate Divider
<> 144:ef7eb2e8f9f7 25763 * | | |The field indicated the baud rate divider
<> 144:ef7eb2e8f9f7 25764 * |[24:27] |EDIVM1 |Divider X
<> 144:ef7eb2e8f9f7 25765 * | | |The baud rate divider M = X+1.
<> 144:ef7eb2e8f9f7 25766 * |[28] |BAUDM0 |Divider X Equal To 1
<> 144:ef7eb2e8f9f7 25767 * | | |0 = Divider M = X (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must >= 8).
<> 144:ef7eb2e8f9f7 25768 * | | |1 = Divider M = 1 (the equation of M = 1, but BRD (UART_BAUD[15:0]) must >= 3).
<> 144:ef7eb2e8f9f7 25769 * | | |Refer to the table below for more information.
<> 144:ef7eb2e8f9f7 25770 * |[29] |BAUDM1 |Divider X Enable Control
<> 144:ef7eb2e8f9f7 25771 * | | |The BRD = Baud Rate Divider, and the baud rate equation is
<> 144:ef7eb2e8f9f7 25772 * | | |Baud Rate = Clock / [M * (BRD + 2)]; The default value of M is 16.
<> 144:ef7eb2e8f9f7 25773 * | | |0 = Divider X Disabled (the equation of M = 16).
<> 144:ef7eb2e8f9f7 25774 * | | |1 = Divider X Enabled (the equation of M = X+1, but EDIVM1 (UART_BAUD[27:24]) must >= 8).
<> 144:ef7eb2e8f9f7 25775 * | | |Refer to the table below for more information.
<> 144:ef7eb2e8f9f7 25776 * | | |Note: In IrDA mode, this bit must disable.
<> 144:ef7eb2e8f9f7 25777 */
<> 144:ef7eb2e8f9f7 25778 __IO uint32_t BAUD;
<> 144:ef7eb2e8f9f7 25779
<> 144:ef7eb2e8f9f7 25780 /**
<> 144:ef7eb2e8f9f7 25781 * IRDA
<> 144:ef7eb2e8f9f7 25782 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25783 * Offset: 0x28 UARTx IrDA Control Register
<> 144:ef7eb2e8f9f7 25784 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25785 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25786 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25787 * |[1] |TXEN |IrDA Receiver/Transmitter Selection Enable Bit
<> 144:ef7eb2e8f9f7 25788 * | | |0 = IrDA receiver Enabled.
<> 144:ef7eb2e8f9f7 25789 * | | |1 = IrDA transmitter Enabled.
<> 144:ef7eb2e8f9f7 25790 * |[5] |TXINV |IrDA Inverse Transmitting Output Signal
<> 144:ef7eb2e8f9f7 25791 * | | |0 = No inversion.
<> 144:ef7eb2e8f9f7 25792 * | | |1 = Inverse TX output signal.
<> 144:ef7eb2e8f9f7 25793 * |[6] |RXINV |IrDA Inverse Receive Input Signal
<> 144:ef7eb2e8f9f7 25794 * | | |0 = No inversion.
<> 144:ef7eb2e8f9f7 25795 * | | |1 = Inverse RX input signal.
<> 144:ef7eb2e8f9f7 25796 * |[7] |FIXPULSE |Pulse width of TX is fixed 1.6us.
<> 144:ef7eb2e8f9f7 25797 */
<> 144:ef7eb2e8f9f7 25798 __IO uint32_t IRDA;
<> 144:ef7eb2e8f9f7 25799
<> 144:ef7eb2e8f9f7 25800 /**
<> 144:ef7eb2e8f9f7 25801 * ALTCTL
<> 144:ef7eb2e8f9f7 25802 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25803 * Offset: 0x2C UARTx Alternate Control/Status Register
<> 144:ef7eb2e8f9f7 25804 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25805 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25806 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25807 * |[0:3] |BKFL |LIN Break Field Length
<> 144:ef7eb2e8f9f7 25808 * | | |This field indicates a 4-bit LIN TX break field count.
<> 144:ef7eb2e8f9f7 25809 * | | |Note1: This break field length is BRKFL + 1.
<> 144:ef7eb2e8f9f7 25810 * | | |Note2: According to LIN spec, the reset value is 0xC (break field length = 13).
<> 144:ef7eb2e8f9f7 25811 * |[6] |LINRXEN |LIN RX Enable Control
<> 144:ef7eb2e8f9f7 25812 * | | |0 = LIN RX mode Disabled.
<> 144:ef7eb2e8f9f7 25813 * | | |1 = LIN RX mode Enabled.
<> 144:ef7eb2e8f9f7 25814 * |[7] |LINTXEN |LIN TX Break Mode Enable Control
<> 144:ef7eb2e8f9f7 25815 * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field" depending on the setting HSEL register.
<> 144:ef7eb2e8f9f7 25816 * | | |0 = Send LIN TX header Disabled.
<> 144:ef7eb2e8f9f7 25817 * | | |1 = Send LIN TX header Enabled.
<> 144:ef7eb2e8f9f7 25818 * | | |Note: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
<> 144:ef7eb2e8f9f7 25819 * |[8] |RS485NMM |RS-485 Normal Multi-Drop Operation Mode (NMM)
<> 144:ef7eb2e8f9f7 25820 * | | |0 = RS-485 Normal Multi-drop Operation Mode (NMM) Disabled.
<> 144:ef7eb2e8f9f7 25821 * | | |1 = RS-485 Normal Multi-drop Operation Mode (NMM) Enabled.
<> 144:ef7eb2e8f9f7 25822 * | | |Note: It can't be active with RS-485_AAD operation mode.
<> 144:ef7eb2e8f9f7 25823 * |[9] |RS485AAD |RS-485 Auto Address Detection Operation Mode (AAD)
<> 144:ef7eb2e8f9f7 25824 * | | |0 = RS-485 Auto Address Detection (AAD) Operation mode Disabled.
<> 144:ef7eb2e8f9f7 25825 * | | |1 = RS-485 Auto Address Detection (AAD) Operation mode Enabled.
<> 144:ef7eb2e8f9f7 25826 * | | |Note: It can't be active with RS-485_NMM operation mode.
<> 144:ef7eb2e8f9f7 25827 * |[10] |RS485AUD |RS-485 Auto Direction Mode (AUD)
<> 144:ef7eb2e8f9f7 25828 * | | |0 = RS-485 Auto Direction Operation (AUO) mode Disabled.
<> 144:ef7eb2e8f9f7 25829 * | | |1 = RS-485 Auto Direction Operation (AUO) mode Enabled.
<> 144:ef7eb2e8f9f7 25830 * | | |Note: It can be active with RS-485_AAD or RS-485_NMM operation mode.
<> 144:ef7eb2e8f9f7 25831 * |[15] |ADDRDEN |RS-485 Address Detection Enable Control
<> 144:ef7eb2e8f9f7 25832 * | | |This bit is use to enable RS-485 address detection mode.
<> 144:ef7eb2e8f9f7 25833 * | | |0 = address detection mode Disabled.
<> 144:ef7eb2e8f9f7 25834 * | | |1 = Address detection mode Enabled.
<> 144:ef7eb2e8f9f7 25835 * | | |Note: This field is used for RS-485 any operation mode.
<> 144:ef7eb2e8f9f7 25836 * |[24:31] |ADDRMV |Address Match Value
<> 144:ef7eb2e8f9f7 25837 * | | |This field contains the RS-485 address match values.
<> 144:ef7eb2e8f9f7 25838 * | | |Note: This field is used for RS-485 auto address detection mode.
<> 144:ef7eb2e8f9f7 25839 */
<> 144:ef7eb2e8f9f7 25840 __IO uint32_t ALTCTL;
<> 144:ef7eb2e8f9f7 25841
<> 144:ef7eb2e8f9f7 25842 /**
<> 144:ef7eb2e8f9f7 25843 * FUNCSEL
<> 144:ef7eb2e8f9f7 25844 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25845 * Offset: 0x30 UARTx Function Select Register
<> 144:ef7eb2e8f9f7 25846 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25847 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25848 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25849 * |[0:2] |FUNCSEL |Function Select Enable Control
<> 144:ef7eb2e8f9f7 25850 * | | |000 = UART function.
<> 144:ef7eb2e8f9f7 25851 * | | |001 = LIN function Enabled.
<> 144:ef7eb2e8f9f7 25852 * | | |010 = IrDA function Enabled.
<> 144:ef7eb2e8f9f7 25853 * | | |011 = RS-485 function Enabled.
<> 144:ef7eb2e8f9f7 25854 * | | |100 = Smart-Card function Enabled.
<> 144:ef7eb2e8f9f7 25855 */
<> 144:ef7eb2e8f9f7 25856 __IO uint32_t FUNCSEL;
<> 144:ef7eb2e8f9f7 25857
<> 144:ef7eb2e8f9f7 25858 /**
<> 144:ef7eb2e8f9f7 25859 * LINCTL
<> 144:ef7eb2e8f9f7 25860 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25861 * Offset: 0x34 UARTx LIN Control Register
<> 144:ef7eb2e8f9f7 25862 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25863 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25864 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25865 * |[0] |SLVEN |LIN Slave Mode Enable Control
<> 144:ef7eb2e8f9f7 25866 * | | |0 = LIN slave mode Disabled.
<> 144:ef7eb2e8f9f7 25867 * | | |1 = LIN slave mode Enabled.
<> 144:ef7eb2e8f9f7 25868 * |[1] |SLVHDEN |LIN Slave Header Detection Enable Control
<> 144:ef7eb2e8f9f7 25869 * | | |0 = LIN slave header detection Disabled.
<> 144:ef7eb2e8f9f7 25870 * | | |1 = LIN slave header detection Enabled.
<> 144:ef7eb2e8f9f7 25871 * | | |Note1: This bit only valid in LIN slave mode (SLVEN = 1).
<> 144:ef7eb2e8f9f7 25872 * | | |Note2: In LIN function mode, when header field (break + sync + frame ID) is detected, hardware will generate an interrupt to CPU (INT_LIN) and the SLVHDETF flag (UART_LINSTS[0]) will be asserted.
<> 144:ef7eb2e8f9f7 25873 * |[2] |SLVAREN |LIN Slave Automatic Resynchronization Mode Enable Control
<> 144:ef7eb2e8f9f7 25874 * | | |0 = LIN automatic resynchronization Disabled.
<> 144:ef7eb2e8f9f7 25875 * | | |1 = LIN automatic resynchronization Enabled.
<> 144:ef7eb2e8f9f7 25876 * | | |Note1: This bit only valid in LIN slave mode (SLVEN = 1).
<> 144:ef7eb2e8f9f7 25877 * | | |Note2: When operating in Automatic Resynchronization mode, the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).
<> 144:ef7eb2e8f9f7 25878 * | | |Note3: The control and interactions of this field are explained in 6.31.5.3.
<> 144:ef7eb2e8f9f7 25879 * |[3] |SLVDUEN |LIN Slave Divider Update Method Enable Control
<> 144:ef7eb2e8f9f7 25880 * | | |0 = UART_BAUD is updated as soon as UART_BAUD is writing by software (if no automatic resynchronization update occurs at the same time).
<> 144:ef7eb2e8f9f7 25881 * | | |1 = UART_BAUD is updated at the next received character.
<> 144:ef7eb2e8f9f7 25882 * | | |User must set the bit before checksum reception.
<> 144:ef7eb2e8f9f7 25883 * | | |Note1: This bit only valid in LIN slave mode (SLVEN = 1).
<> 144:ef7eb2e8f9f7 25884 * | | |Note2: This bit is used for LIN slave automatic resynchronization mode (for non-automatic resynchronization mode, this bit should be kept cleared).
<> 144:ef7eb2e8f9f7 25885 * | | |Note3: The control and interactions of this field are explained in 6.31.5.3.
<> 144:ef7eb2e8f9f7 25886 * |[4] |MUTE |LIN Mute Mode Enable Control
<> 144:ef7eb2e8f9f7 25887 * | | |0 = LIN mute mode. Disabled
<> 144:ef7eb2e8f9f7 25888 * | | |1 = LIN mute mode Enabled.
<> 144:ef7eb2e8f9f7 25889 * | | |Note: The wake-up condition from mute mode and each control and interactions of this field are explained in 6.31.5.3.
<> 144:ef7eb2e8f9f7 25890 * |[8] |SENDH |LIN TX Send Header Enable Control
<> 144:ef7eb2e8f9f7 25891 * | | |The LIN TX header can be "break field" or "break and sync field" or "break, sync and frame ID field" depending on the setting HSEL register.
<> 144:ef7eb2e8f9f7 25892 * | | |0 = Send LIN TX header Disabled.
<> 144:ef7eb2e8f9f7 25893 * | | |1 = Send LIN TX header Enabled.
<> 144:ef7eb2e8f9f7 25894 * | | |Note: When transmitter header field (it may be "break" or "break + sync" or "break + sync + frame ID" selected by HSEL field) transfer operation finished, this bit will be cleared automatically.
<> 144:ef7eb2e8f9f7 25895 * |[9] |IDPEN |LIN ID Parity Enable Control
<> 144:ef7eb2e8f9f7 25896 * | | |0 = LIN frame ID parity Disabled.
<> 144:ef7eb2e8f9f7 25897 * | | |1 = LIN frame ID parity Enabled.
<> 144:ef7eb2e8f9f7 25898 * | | |Note1: This bit can be used for LIN master to sending header field (SENDH = 1 and HSEL = 2'b10) or be used for enable LIN slave received frame ID parity checked.
<> 144:ef7eb2e8f9f7 25899 * | | |Note2: This bit is only used when operation header transmitter is in HSEL = 2'b10.
<> 144:ef7eb2e8f9f7 25900 * |[10] |BRKDETEN |LIN Break Detection Enable Control
<> 144:ef7eb2e8f9f7 25901 * | | |When detect great than 11/10 bits are detected as 0, and are followed by a delimiter character, the BRKDETF flag (UART_LINSTS[8]) at the end of break field.
<> 144:ef7eb2e8f9f7 25902 * | | |If the LINIEN bit (UART_INTEN[8]) = 1, an interrupt will be generated.
<> 144:ef7eb2e8f9f7 25903 * | | |0 = LIN break detection Disabled.
<> 144:ef7eb2e8f9f7 25904 * | | |1 = LIN break detection Enabled.
<> 144:ef7eb2e8f9f7 25905 * |[11] |RXOFF |If the receiver is be enabled (RXOFF = 0), all received byte data will be accepted and stored in the RX-FIFO, and if the receiver is disabled (RXOFF = 1), all received byte data will be ignore.
<> 144:ef7eb2e8f9f7 25906 * | | |0 = Bit error detection function Disabled.
<> 144:ef7eb2e8f9f7 25907 * | | |1 = Bit error detection Enabled.
<> 144:ef7eb2e8f9f7 25908 * | | |Note: This bit is only valid when operating in LIN function mode (UART_FUNCSEL = 2'b01).
<> 144:ef7eb2e8f9f7 25909 * |[12] |BITERREN |Bit Error Detect Enable Control
<> 144:ef7eb2e8f9f7 25910 * | | |0 = Bit error detection function Disabled.
<> 144:ef7eb2e8f9f7 25911 * | | |1 = Bit error detection Enabled.
<> 144:ef7eb2e8f9f7 25912 * | | |Note: In LIN function mode, when occur bit error, hardware will generate an interrupt to CPU (INT_LIN) and the BITEF (UART_LINSTS[9]) flag will be asserted.
<> 144:ef7eb2e8f9f7 25913 * |[16:19] |BRKFL |LIN Break Field Length
<> 144:ef7eb2e8f9f7 25914 * | | |This field indicates a 4-bit LIN TX break field count.
<> 144:ef7eb2e8f9f7 25915 * | | |Note1: These registers are shadow registers of LIN_BKFL (UART_ALTCTL[3:0]), User can read/write it by setting LIN_BKFL (UART_ALTCTL[3:0]) or LIN_BKFL (UART_LINCTL[19:16]).
<> 144:ef7eb2e8f9f7 25916 * | | |Note2: This break field length is BRKFL + 1.
<> 144:ef7eb2e8f9f7 25917 * | | |Note3: According to LIN spec, the reset value is 0XC (break field length = 13).
<> 144:ef7eb2e8f9f7 25918 * |[20:21] |BSL |LIN Break/Sync Delimiter Length
<> 144:ef7eb2e8f9f7 25919 * | | |00 = LIN break/sync delimiter length is 1 bit time.
<> 144:ef7eb2e8f9f7 25920 * | | |10 = The LIN break/sync delimiter length is 2 bit time.
<> 144:ef7eb2e8f9f7 25921 * | | |10 = The LIN break/sync delimiter length is 3 bit time.
<> 144:ef7eb2e8f9f7 25922 * | | |11 = The LIN break/sync delimiter length is 4 bit time.
<> 144:ef7eb2e8f9f7 25923 * | | |Note: This bit used for LIN master to send header field.
<> 144:ef7eb2e8f9f7 25924 * |[22:23] |HSEL |LIN Header Selection
<> 144:ef7eb2e8f9f7 25925 * | | |00 = LIN header includes "break field".
<> 144:ef7eb2e8f9f7 25926 * | | |01 = LIN header includes "break field" and "sync field".
<> 144:ef7eb2e8f9f7 25927 * | | |10 = LIN header includes "break field", "sync field" and "frame ID field".
<> 144:ef7eb2e8f9f7 25928 * | | |11 = LIN header includes "break field", "sync field" and "frame ID field", but this mode only supports Receiver mode, not support transmitter mode.
<> 144:ef7eb2e8f9f7 25929 * | | |This mode difference with mode "10"; in this mode, the receiver will receive ID field (not check the PID (UART_LINCTL[31:24]) register) and when received ID field the SLVHDETF will be asserted (if SLVHDEN (UART_LINCTL[1]) be set).
<> 144:ef7eb2e8f9f7 25930 * | | |Note: This bit is used to master mode for LIN to sending header field (SENDH = 1) or used to slave to indicates wake-up condition from mute mode (MUTE).
<> 144:ef7eb2e8f9f7 25931 * |[24:31] |PID |This Field Contains The LIN Frame ID Value In LIN Function Mode, The Frame ID Parity Can Be Generated By Software Or Hardware Depending On UART_LINCTL [IDPEN]
<> 144:ef7eb2e8f9f7 25932 * | | |If the parity generated by hardware (IDPEN (UART_LINCTL[9]) = 1), user fill ID0~ID5, hardware will calculi P0 and P1, otherwise user must filled frame ID and parity in this field.
<> 144:ef7eb2e8f9f7 25933 * | | |Note1: User can fill any 8-bit value to this field and the bit 24 indicates ID0 (LSB first)
<> 144:ef7eb2e8f9f7 25934 * | | |Note2: This field can be used for LIN Master mode or Slave mode.
<> 144:ef7eb2e8f9f7 25935 */
<> 144:ef7eb2e8f9f7 25936 __IO uint32_t LINCTL;
<> 144:ef7eb2e8f9f7 25937
<> 144:ef7eb2e8f9f7 25938 /**
<> 144:ef7eb2e8f9f7 25939 * LINSTS
<> 144:ef7eb2e8f9f7 25940 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25941 * Offset: 0x38 UARTx LIN Status Register
<> 144:ef7eb2e8f9f7 25942 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25943 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25944 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25945 * |[0] |SLVHDETF |LIN Slave Header Detection Flag (Read Only)
<> 144:ef7eb2e8f9f7 25946 * | | |This bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25947 * | | |0 = LIN header not detected.
<> 144:ef7eb2e8f9f7 25948 * | | |1 = LIN header detected (break + sync + frame ID).
<> 144:ef7eb2e8f9f7 25949 * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25950 * | | |Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN slave header detection function (SLVHDEN (UART_LINCTL[1])) is enabled.
<> 144:ef7eb2e8f9f7 25951 * | | |Note3: When the ID parity check (IDPEN (UART_LINCTL[9]) = 1) is enabled, if hardware detect complete harder ("break + sync + frame ID"), the LINS_HEDT_F (UART_LINCTL[1]) will be set no matter the frame ID is corrected or not.
<> 144:ef7eb2e8f9f7 25952 * |[1] |SLVHEF |LIN Slave Header Error Flag (Read Only)
<> 144:ef7eb2e8f9f7 25953 * | | |This bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25954 * | | |The header include "break delimiter is too short", "frame error in sync field or Identifier field", "sync field data is not 0x55 without automatic resynchronization mode", "sync field deviation error with automatic resynchronization mode", "sync field measure time-out with automatic resynchronization mode" and "LIN header reception time-out".
<> 144:ef7eb2e8f9f7 25955 * | | |0 = LIN header error not detected.
<> 144:ef7eb2e8f9f7 25956 * | | |1 = LIN header error detected.
<> 144:ef7eb2e8f9f7 25957 * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25958 * | | |Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN slave header detection function (SLVHDEN (UART_LINCTL[1])) is enabled.
<> 144:ef7eb2e8f9f7 25959 * |[2] |SLVIDPEF |LIN Slave ID Parity Error Flag (Read Only)
<> 144:ef7eb2e8f9f7 25960 * | | |This bit is set by hardware when receipted frame ID parity is not correct.
<> 144:ef7eb2e8f9f7 25961 * | | |0 = no active.
<> 144:ef7eb2e8f9f7 25962 * | | |1 = Receipted frame ID parity is not correct.
<> 144:ef7eb2e8f9f7 25963 * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25964 * | | |Note2: This bit is only valid in LIN slave mode (SLVEN (UART_LINCTL[0]) = 1) and LIN frame ID parity check function (IDPEN (UART_LINCTL[9])) is enabled.
<> 144:ef7eb2e8f9f7 25965 * |[3] |SLVSYNCF |LIN Slave Sync Field
<> 144:ef7eb2e8f9f7 25966 * | | |This bit indicates that the LIN sync field is being analyzed.
<> 144:ef7eb2e8f9f7 25967 * | | |When the receiver header have some error been detect, user must to reset the internal circuit to re-search new frame header by writing 1 to this bit.
<> 144:ef7eb2e8f9f7 25968 * | | |0 = The current character is not at LIN sync state.
<> 144:ef7eb2e8f9f7 25969 * | | |1 = The current character is at LIN sync state.
<> 144:ef7eb2e8f9f7 25970 * | | |Note1: This bit only valid in LIN Slave mode (SLVEN = 1).
<> 144:ef7eb2e8f9f7 25971 * | | |Note2: This bit is read only, but can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25972 * | | |Note3: When user writing 1 to it, hardware will reload the initial baud-rate and re-search new frame header, the control and interactions of this field are explained in 6.31.5.3.
<> 144:ef7eb2e8f9f7 25973 * |[8] |BRKDETF |LIN Break Detection Flag (Read Only)
<> 144:ef7eb2e8f9f7 25974 * | | |This bit is set by hardware when a break is detected and be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25975 * | | |0 = LIN break not detected.
<> 144:ef7eb2e8f9f7 25976 * | | |1 = LIN break detected.
<> 144:ef7eb2e8f9f7 25977 * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25978 * | | |Note2: This bit is only valid when enable LIN break detection function (BRKDETEN (UART_LINCTL[10]))
<> 144:ef7eb2e8f9f7 25979 * |[9] |BITEF |Bit Error Detect Status Flag (Read Only)
<> 144:ef7eb2e8f9f7 25980 * | | |At TX transfer state, hardware will monitoring the bus state, if the input pin (SIN) state not equals to the output pin (SOUT) state, BITEF will be set.
<> 144:ef7eb2e8f9f7 25981 * | | |When occur bit error, hardware will generate an interrupt to CPU (INT_LIN).
<> 144:ef7eb2e8f9f7 25982 * | | |Note1: This bit is read only, but can be cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 25983 * | | |Note2: This bit is only valid when enable bit error detection function (BRKL (UART_LINCTL[12]) == 1).
<> 144:ef7eb2e8f9f7 25984 */
<> 144:ef7eb2e8f9f7 25985 __IO uint32_t LINSTS;
<> 144:ef7eb2e8f9f7 25986
<> 144:ef7eb2e8f9f7 25987 /**
<> 144:ef7eb2e8f9f7 25988 * LINDEBUG
<> 144:ef7eb2e8f9f7 25989 * ===================================================================================================
<> 144:ef7eb2e8f9f7 25990 * Offset: 0x3C UARTx LIN Debug Register
<> 144:ef7eb2e8f9f7 25991 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 25992 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 25993 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 25994 * |[0] |DEVERRF |LIN Header Deviation Error (Read Only)
<> 144:ef7eb2e8f9f7 25995 * | | |This bit indicates the header error cause by the sync field deviation error or sync field measure time-out with automatic resynchronization mode.
<> 144:ef7eb2e8f9f7 25996 * |[1] |TOF |LIN Header Time-Out (Read Only)
<> 144:ef7eb2e8f9f7 25997 * | | |This bit indicates the header error cause by the LIN header reception time-out.
<> 144:ef7eb2e8f9f7 25998 * |[2] |FRAMEERRF |LIN Header Frame Error Flag (Read Only)
<> 144:ef7eb2e8f9f7 25999 * | | |This bit indicates the header error cause by break delimiter is too short or frame error in sync field or Identifier field.
<> 144:ef7eb2e8f9f7 26000 * |[3] |SYNCERRF |LIN Header Sync Data Error (Read Only)
<> 144:ef7eb2e8f9f7 26001 * | | |This bit indicates the header error cause by the LIN received sync data is not 0x55.
<> 144:ef7eb2e8f9f7 26002 */
<> 144:ef7eb2e8f9f7 26003 __IO uint32_t LINDEBUG;
<> 144:ef7eb2e8f9f7 26004
<> 144:ef7eb2e8f9f7 26005
<> 144:ef7eb2e8f9f7 26006 } UART_T;
<> 144:ef7eb2e8f9f7 26007
<> 144:ef7eb2e8f9f7 26008 /**
<> 144:ef7eb2e8f9f7 26009 @addtogroup UART_CONST UART Bit Field Definition
<> 144:ef7eb2e8f9f7 26010 Constant Definitions for UART Controller
<> 144:ef7eb2e8f9f7 26011 @{ */
<> 144:ef7eb2e8f9f7 26012
<> 144:ef7eb2e8f9f7 26013 #define UART_DAT_DAT_Pos (0) /*!< UART DAT: DAT Position */
<> 144:ef7eb2e8f9f7 26014 #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) /*!< UART DAT: DAT Mask */
<> 144:ef7eb2e8f9f7 26015
<> 144:ef7eb2e8f9f7 26016 #define UART_INTEN_RDAIEN_Pos (0) /*!< UART INTEN: RDAIEN Position */
<> 144:ef7eb2e8f9f7 26017 #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) /*!< UART INTEN: RDAIEN Mask */
<> 144:ef7eb2e8f9f7 26018
<> 144:ef7eb2e8f9f7 26019 #define UART_INTEN_THREIEN_Pos (1) /*!< UART INTEN: THREIEN Position */
<> 144:ef7eb2e8f9f7 26020 #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) /*!< UART INTEN: THREIEN Mask */
<> 144:ef7eb2e8f9f7 26021
<> 144:ef7eb2e8f9f7 26022 #define UART_INTEN_RLSIEN_Pos (2) /*!< UART INTEN: RLSIEN Position */
<> 144:ef7eb2e8f9f7 26023 #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) /*!< UART INTEN: RLSIEN Mask */
<> 144:ef7eb2e8f9f7 26024
<> 144:ef7eb2e8f9f7 26025 #define UART_INTEN_MODEMIEN_Pos (3) /*!< UART INTEN: MODEMIEN Position */
<> 144:ef7eb2e8f9f7 26026 #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) /*!< UART INTEN: MODEMIEN Mask */
<> 144:ef7eb2e8f9f7 26027
<> 144:ef7eb2e8f9f7 26028 #define UART_INTEN_RXTOIEN_Pos (4) /*!< UART INTEN: RXTOIEN Position */
<> 144:ef7eb2e8f9f7 26029 #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) /*!< UART INTEN: RXTOIEN Mask */
<> 144:ef7eb2e8f9f7 26030
<> 144:ef7eb2e8f9f7 26031 #define UART_INTEN_BUFERRIEN_Pos (5) /*!< UART INTEN: BUFERRIEN Position */
<> 144:ef7eb2e8f9f7 26032 #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) /*!< UART INTEN: BUFERRIEN Mask */
<> 144:ef7eb2e8f9f7 26033
<> 144:ef7eb2e8f9f7 26034 #define UART_INTEN_WKCTSIEN_Pos (6) /*!< UART INTEN: WKCTSIEN Position */
<> 144:ef7eb2e8f9f7 26035 #define UART_INTEN_WKCTSIEN_Msk (0x1ul << UART_INTEN_WKCTSIEN_Pos) /*!< UART INTEN: WKCTSIEN Mask */
<> 144:ef7eb2e8f9f7 26036
<> 144:ef7eb2e8f9f7 26037 #define UART_INTEN_LINIEN_Pos (8) /*!< UART INTEN: LINIEN Position */
<> 144:ef7eb2e8f9f7 26038 #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) /*!< UART INTEN: LINIEN Mask */
<> 144:ef7eb2e8f9f7 26039
<> 144:ef7eb2e8f9f7 26040 #define UART_INTEN_TOCNTEN_Pos (11) /*!< UART INTEN: TOCNTEN Position */
<> 144:ef7eb2e8f9f7 26041 #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) /*!< UART INTEN: TOCNTEN Mask */
<> 144:ef7eb2e8f9f7 26042
<> 144:ef7eb2e8f9f7 26043 #define UART_INTEN_ATORTSEN_Pos (12) /*!< UART INTEN: ATORTSEN Position */
<> 144:ef7eb2e8f9f7 26044 #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) /*!< UART INTEN: ATORTSEN Mask */
<> 144:ef7eb2e8f9f7 26045
<> 144:ef7eb2e8f9f7 26046 #define UART_INTEN_ATOCTSEN_Pos (13) /*!< UART INTEN: ATOCTSEN Position */
<> 144:ef7eb2e8f9f7 26047 #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) /*!< UART INTEN: ATOCTSEN Mask */
<> 144:ef7eb2e8f9f7 26048
<> 144:ef7eb2e8f9f7 26049 #define UART_INTEN_TXPDMAEN_Pos (14) /*!< UART INTEN: TXPDMAEN Position */
<> 144:ef7eb2e8f9f7 26050 #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) /*!< UART INTEN: TXPDMAEN Mask */
<> 144:ef7eb2e8f9f7 26051
<> 144:ef7eb2e8f9f7 26052 #define UART_INTEN_RXPDMAEN_Pos (15) /*!< UART INTEN: RXPDMAEN Position */
<> 144:ef7eb2e8f9f7 26053 #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) /*!< UART INTEN: RXPDMAEN Mask */
<> 144:ef7eb2e8f9f7 26054
<> 144:ef7eb2e8f9f7 26055 #define UART_FIFO_RXRST_Pos (1) /*!< UART FIFO: RXRST Position */
<> 144:ef7eb2e8f9f7 26056 #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) /*!< UART FIFO: RXRST Mask */
<> 144:ef7eb2e8f9f7 26057
<> 144:ef7eb2e8f9f7 26058 #define UART_FIFO_TXRST_Pos (2) /*!< UART FIFO: TXRST Position */
<> 144:ef7eb2e8f9f7 26059 #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) /*!< UART FIFO: TXRST Mask */
<> 144:ef7eb2e8f9f7 26060
<> 144:ef7eb2e8f9f7 26061 #define UART_FIFO_RFITL_Pos (4) /*!< UART FIFO: RFITL Position */
<> 144:ef7eb2e8f9f7 26062 #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) /*!< UART FIFO: RFITL Mask */
<> 144:ef7eb2e8f9f7 26063
<> 144:ef7eb2e8f9f7 26064 #define UART_FIFO_RXOFF_Pos (8) /*!< UART FIFO: RXOFF Position */
<> 144:ef7eb2e8f9f7 26065 #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) /*!< UART FIFO: RXOFF Mask */
<> 144:ef7eb2e8f9f7 26066
<> 144:ef7eb2e8f9f7 26067 #define UART_FIFO_RTSTRGLV_Pos (16) /*!< UART FIFO: RTSTRGLV Position */
<> 144:ef7eb2e8f9f7 26068 #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) /*!< UART FIFO: RTSTRGLV Mask */
<> 144:ef7eb2e8f9f7 26069
<> 144:ef7eb2e8f9f7 26070 #define UART_LINE_WLS_Pos (0) /*!< UART LINE: WLS Position */
<> 144:ef7eb2e8f9f7 26071 #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) /*!< UART LINE: WLS Mask */
<> 144:ef7eb2e8f9f7 26072
<> 144:ef7eb2e8f9f7 26073 #define UART_LINE_NSB_Pos (2) /*!< UART LINE: NSB Position */
<> 144:ef7eb2e8f9f7 26074 #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) /*!< UART LINE: NSB Mask */
<> 144:ef7eb2e8f9f7 26075
<> 144:ef7eb2e8f9f7 26076 #define UART_LINE_PBE_Pos (3) /*!< UART LINE: PBE Position */
<> 144:ef7eb2e8f9f7 26077 #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) /*!< UART LINE: PBE Mask */
<> 144:ef7eb2e8f9f7 26078
<> 144:ef7eb2e8f9f7 26079 #define UART_LINE_EPE_Pos (4) /*!< UART LINE: EPE Position */
<> 144:ef7eb2e8f9f7 26080 #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) /*!< UART LINE: EPE Mask */
<> 144:ef7eb2e8f9f7 26081
<> 144:ef7eb2e8f9f7 26082 #define UART_LINE_SPE_Pos (5) /*!< UART LINE: SPE Position */
<> 144:ef7eb2e8f9f7 26083 #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) /*!< UART LINE: SPE Mask */
<> 144:ef7eb2e8f9f7 26084
<> 144:ef7eb2e8f9f7 26085 #define UART_LINE_BCB_Pos (6) /*!< UART LINE: BCB Position */
<> 144:ef7eb2e8f9f7 26086 #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) /*!< UART LINE: BCB Mask */
<> 144:ef7eb2e8f9f7 26087
<> 144:ef7eb2e8f9f7 26088 #define UART_MODEM_RTS_Pos (1) /*!< UART MODEM: RTS Position */
<> 144:ef7eb2e8f9f7 26089 #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) /*!< UART MODEM: RTS Mask */
<> 144:ef7eb2e8f9f7 26090
<> 144:ef7eb2e8f9f7 26091 #define UART_MODEM_RTSACTLV_Pos (9) /*!< UART MODEM: RTSACTLV Position */
<> 144:ef7eb2e8f9f7 26092 #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) /*!< UART MODEM: RTSACTLV Mask */
<> 144:ef7eb2e8f9f7 26093
<> 144:ef7eb2e8f9f7 26094 #define UART_MODEM_RTSSTS_Pos (13) /*!< UART MODEM: RTSSTS Position */
<> 144:ef7eb2e8f9f7 26095 #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) /*!< UART MODEM: RTSSTS Mask */
<> 144:ef7eb2e8f9f7 26096
<> 144:ef7eb2e8f9f7 26097 #define UART_MODEMSTS_CTSDETF_Pos (0) /*!< UART MODEMSTS: CTSDETF Position */
<> 144:ef7eb2e8f9f7 26098 #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) /*!< UART MODEMSTS: CTSDETF Mask */
<> 144:ef7eb2e8f9f7 26099
<> 144:ef7eb2e8f9f7 26100 #define UART_MODEMSTS_CTSSTS_Pos (4) /*!< UART MODEMSTS: CTSSTS Position */
<> 144:ef7eb2e8f9f7 26101 #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) /*!< UART MODEMSTS: CTSSTS Mask */
<> 144:ef7eb2e8f9f7 26102
<> 144:ef7eb2e8f9f7 26103 #define UART_MODEMSTS_CTSACTLV_Pos (8) /*!< UART MODEMSTS: CTSACTLV Position */
<> 144:ef7eb2e8f9f7 26104 #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) /*!< UART MODEMSTS: CTSACTLV Mask */
<> 144:ef7eb2e8f9f7 26105
<> 144:ef7eb2e8f9f7 26106 #define UART_FIFOSTS_RXOVIF_Pos (0) /*!< UART FIFOSTS: RXOVIF Position */
<> 144:ef7eb2e8f9f7 26107 #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) /*!< UART FIFOSTS: RXOVIF Mask */
<> 144:ef7eb2e8f9f7 26108
<> 144:ef7eb2e8f9f7 26109 #define UART_FIFOSTS_SCERR_Pos (2) /*!< UART FIFOSTS: SCERR Position */
<> 144:ef7eb2e8f9f7 26110 #define UART_FIFOSTS_SCERR_Msk (0x1ul << UART_FIFOSTS_SCERR_Pos) /*!< UART FIFOSTS: SCERR Mask */
<> 144:ef7eb2e8f9f7 26111
<> 144:ef7eb2e8f9f7 26112 #define UART_FIFOSTS_ADDRDETF_Pos (3) /*!< UART FIFOSTS: ADDRDETF Position */
<> 144:ef7eb2e8f9f7 26113 #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) /*!< UART FIFOSTS: ADDRDETF Mask */
<> 144:ef7eb2e8f9f7 26114
<> 144:ef7eb2e8f9f7 26115 #define UART_FIFOSTS_PEF_Pos (4) /*!< UART FIFOSTS: PEF Position */
<> 144:ef7eb2e8f9f7 26116 #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) /*!< UART FIFOSTS: PEF Mask */
<> 144:ef7eb2e8f9f7 26117
<> 144:ef7eb2e8f9f7 26118 #define UART_FIFOSTS_FEF_Pos (5) /*!< UART FIFOSTS: FEF Position */
<> 144:ef7eb2e8f9f7 26119 #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) /*!< UART FIFOSTS: FEF Mask */
<> 144:ef7eb2e8f9f7 26120
<> 144:ef7eb2e8f9f7 26121 #define UART_FIFOSTS_BIF_Pos (6) /*!< UART FIFOSTS: BIF Position */
<> 144:ef7eb2e8f9f7 26122 #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) /*!< UART FIFOSTS: BIF Mask */
<> 144:ef7eb2e8f9f7 26123
<> 144:ef7eb2e8f9f7 26124 #define UART_FIFOSTS_RXPTR_Pos (8) /*!< UART FIFOSTS: RXPTR Position */
<> 144:ef7eb2e8f9f7 26125 #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) /*!< UART FIFOSTS: RXPTR Mask */
<> 144:ef7eb2e8f9f7 26126
<> 144:ef7eb2e8f9f7 26127 #define UART_FIFOSTS_RXEMPTY_Pos (14) /*!< UART FIFOSTS: RXEMPTY Position */
<> 144:ef7eb2e8f9f7 26128 #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) /*!< UART FIFOSTS: RXEMPTY Mask */
<> 144:ef7eb2e8f9f7 26129
<> 144:ef7eb2e8f9f7 26130 #define UART_FIFOSTS_RXFULL_Pos (15) /*!< UART FIFOSTS: RXFULL Position */
<> 144:ef7eb2e8f9f7 26131 #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) /*!< UART FIFOSTS: RXFULL Mask */
<> 144:ef7eb2e8f9f7 26132
<> 144:ef7eb2e8f9f7 26133 #define UART_FIFOSTS_TXPTR_Pos (16) /*!< UART FIFOSTS: TXPTR Position */
<> 144:ef7eb2e8f9f7 26134 #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) /*!< UART FIFOSTS: TXPTR Mask */
<> 144:ef7eb2e8f9f7 26135
<> 144:ef7eb2e8f9f7 26136 #define UART_FIFOSTS_TXEMPTY_Pos (22) /*!< UART FIFOSTS: TXEMPTY Position */
<> 144:ef7eb2e8f9f7 26137 #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) /*!< UART FIFOSTS: TXEMPTY Mask */
<> 144:ef7eb2e8f9f7 26138
<> 144:ef7eb2e8f9f7 26139 #define UART_FIFOSTS_TXFULL_Pos (23) /*!< UART FIFOSTS: TXFULL Position */
<> 144:ef7eb2e8f9f7 26140 #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) /*!< UART FIFOSTS: TXFULL Mask */
<> 144:ef7eb2e8f9f7 26141
<> 144:ef7eb2e8f9f7 26142 #define UART_FIFOSTS_TXOVIF_Pos (24) /*!< UART FIFOSTS: TXOVIF Position */
<> 144:ef7eb2e8f9f7 26143 #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) /*!< UART FIFOSTS: TXOVIF Mask */
<> 144:ef7eb2e8f9f7 26144
<> 144:ef7eb2e8f9f7 26145 #define UART_FIFOSTS_TXEMPTYF_Pos (28) /*!< UART FIFOSTS: TXEMPTYF Position */
<> 144:ef7eb2e8f9f7 26146 #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) /*!< UART FIFOSTS: TXEMPTYF Mask */
<> 144:ef7eb2e8f9f7 26147
<> 144:ef7eb2e8f9f7 26148 #define UART_INTSTS_RDAIF_Pos (0) /*!< UART INTSTS: RDAIF Position */
<> 144:ef7eb2e8f9f7 26149 #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) /*!< UART INTSTS: RDAIF Mask */
<> 144:ef7eb2e8f9f7 26150
<> 144:ef7eb2e8f9f7 26151 #define UART_INTSTS_THREIF_Pos (1) /*!< UART INTSTS: THREIF Position */
<> 144:ef7eb2e8f9f7 26152 #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) /*!< UART INTSTS: THREIF Mask */
<> 144:ef7eb2e8f9f7 26153
<> 144:ef7eb2e8f9f7 26154 #define UART_INTSTS_RLSIF_Pos (2) /*!< UART INTSTS: RLSIF Position */
<> 144:ef7eb2e8f9f7 26155 #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) /*!< UART INTSTS: RLSIF Mask */
<> 144:ef7eb2e8f9f7 26156
<> 144:ef7eb2e8f9f7 26157 #define UART_INTSTS_MODENIF_Pos (3) /*!< UART INTSTS: MODENIF Position */
<> 144:ef7eb2e8f9f7 26158 #define UART_INTSTS_MODENIF_Msk (0x1ul << UART_INTSTS_MODENIF_Pos) /*!< UART INTSTS: MODENIF Mask */
<> 144:ef7eb2e8f9f7 26159
<> 144:ef7eb2e8f9f7 26160 #define UART_INTSTS_RXTOIF_Pos (4) /*!< UART INTSTS: RXTOIF Position */
<> 144:ef7eb2e8f9f7 26161 #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) /*!< UART INTSTS: RXTOIF Mask */
<> 144:ef7eb2e8f9f7 26162
<> 144:ef7eb2e8f9f7 26163 #define UART_INTSTS_BUFERRIF_Pos (5) /*!< UART INTSTS: BUFERRIF Position */
<> 144:ef7eb2e8f9f7 26164 #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) /*!< UART INTSTS: BUFERRIF Mask */
<> 144:ef7eb2e8f9f7 26165
<> 144:ef7eb2e8f9f7 26166 #define UART_INTSTS_LINIF_Pos (7) /*!< UART INTSTS: LINIF Position */
<> 144:ef7eb2e8f9f7 26167 #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) /*!< UART INTSTS: LINIF Mask */
<> 144:ef7eb2e8f9f7 26168
<> 144:ef7eb2e8f9f7 26169 #define UART_INTSTS_RDAINT_Pos (8) /*!< UART INTSTS: RDAINT Position */
<> 144:ef7eb2e8f9f7 26170 #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) /*!< UART INTSTS: RDAINT Mask */
<> 144:ef7eb2e8f9f7 26171
<> 144:ef7eb2e8f9f7 26172 #define UART_INTSTS_THREINT_Pos (9) /*!< UART INTSTS: THERINT Position */
<> 144:ef7eb2e8f9f7 26173 #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) /*!< UART INTSTS: THERINT Mask */
<> 144:ef7eb2e8f9f7 26174
<> 144:ef7eb2e8f9f7 26175 #define UART_INTSTS_RLSINT_Pos (10) /*!< UART INTSTS: RLSINT Position */
<> 144:ef7eb2e8f9f7 26176 #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) /*!< UART INTSTS: RLSINT Mask */
<> 144:ef7eb2e8f9f7 26177
<> 144:ef7eb2e8f9f7 26178 #define UART_INTSTS_MODEMINT_Pos (11) /*!< UART INTSTS: MODEMINT Position */
<> 144:ef7eb2e8f9f7 26179 #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) /*!< UART INTSTS: MODEMINT Mask */
<> 144:ef7eb2e8f9f7 26180
<> 144:ef7eb2e8f9f7 26181 #define UART_INTSTS_RXTOINT_Pos (12) /*!< UART INTSTS: RXTOINT Position */
<> 144:ef7eb2e8f9f7 26182 #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) /*!< UART INTSTS: RXTOINT Mask */
<> 144:ef7eb2e8f9f7 26183
<> 144:ef7eb2e8f9f7 26184 #define UART_INTSTS_BUFERRINT_Pos (13) /*!< UART INTSTS: BUFERRINT Position */
<> 144:ef7eb2e8f9f7 26185 #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) /*!< UART INTSTS: BUFERRINT Mask */
<> 144:ef7eb2e8f9f7 26186
<> 144:ef7eb2e8f9f7 26187 #define UART_INTSTS_LININT_Pos (15) /*!< UART INTSTS: LININT Position */
<> 144:ef7eb2e8f9f7 26188 #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) /*!< UART INTSTS: LININT Mask */
<> 144:ef7eb2e8f9f7 26189
<> 144:ef7eb2e8f9f7 26190 #define UART_INTSTS_HWRLSIF_Pos (18) /*!< UART INTSTS: HWRLSIF Position */
<> 144:ef7eb2e8f9f7 26191 #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) /*!< UART INTSTS: HWRLSIF Mask */
<> 144:ef7eb2e8f9f7 26192
<> 144:ef7eb2e8f9f7 26193 #define UART_INTSTS_HWMODIF_Pos (19) /*!< UART INTSTS: HWMODIF Position */
<> 144:ef7eb2e8f9f7 26194 #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) /*!< UART INTSTS: HWMODIF Mask */
<> 144:ef7eb2e8f9f7 26195
<> 144:ef7eb2e8f9f7 26196 #define UART_INTSTS_HWTOIF_Pos (20) /*!< UART INTSTS: HWTOIF Position */
<> 144:ef7eb2e8f9f7 26197 #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) /*!< UART INTSTS: HWTOIF Mask */
<> 144:ef7eb2e8f9f7 26198
<> 144:ef7eb2e8f9f7 26199 #define UART_INTSTS_HWBUFEIF_Pos (21) /*!< UART INTSTS: HWBUFEIF Position */
<> 144:ef7eb2e8f9f7 26200 #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) /*!< UART INTSTS: HWBUFEIF Mask */
<> 144:ef7eb2e8f9f7 26201
<> 144:ef7eb2e8f9f7 26202 #define UART_INTSTS_HWRLSINT_Pos (26) /*!< UART INTSTS: HWRLSINT Position */
<> 144:ef7eb2e8f9f7 26203 #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) /*!< UART INTSTS: HWRLSINT Mask */
<> 144:ef7eb2e8f9f7 26204
<> 144:ef7eb2e8f9f7 26205 #define UART_INTSTS_HWMODINT_Pos (27) /*!< UART INTSTS: HWMODINT Position */
<> 144:ef7eb2e8f9f7 26206 #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) /*!< UART INTSTS: HWMODINT Mask */
<> 144:ef7eb2e8f9f7 26207
<> 144:ef7eb2e8f9f7 26208 #define UART_INTSTS_HWTOINT_Pos (28) /*!< UART INTSTS: HWTOINT Position */
<> 144:ef7eb2e8f9f7 26209 #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) /*!< UART INTSTS: HWTOINT Mask */
<> 144:ef7eb2e8f9f7 26210
<> 144:ef7eb2e8f9f7 26211 #define UART_INTSTS_HWBUFEINT_Pos (29) /*!< UART INTSTS: HWBUFEINT Position */
<> 144:ef7eb2e8f9f7 26212 #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) /*!< UART INTSTS: HWBUFEINT Mask */
<> 144:ef7eb2e8f9f7 26213
<> 144:ef7eb2e8f9f7 26214 #define UART_TOUT_TOIC_Pos (0) /*!< UART TOUT: TOIC Position */
<> 144:ef7eb2e8f9f7 26215 #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) /*!< UART TOUT: TOIC Mask */
<> 144:ef7eb2e8f9f7 26216
<> 144:ef7eb2e8f9f7 26217 #define UART_TOUT_DLY_Pos (8) /*!< UART TOUT: DLY Position */
<> 144:ef7eb2e8f9f7 26218 #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) /*!< UART TOUT: DLY Mask */
<> 144:ef7eb2e8f9f7 26219
<> 144:ef7eb2e8f9f7 26220 #define UART_BAUD_BRD_Pos (0) /*!< UART BAUD: BRD Position */
<> 144:ef7eb2e8f9f7 26221 #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) /*!< UART BAUD: BRD Mask */
<> 144:ef7eb2e8f9f7 26222
<> 144:ef7eb2e8f9f7 26223 #define UART_BAUD_EDIVM1_Pos (24) /*!< UART BAUD: EDIVM1 Position */
<> 144:ef7eb2e8f9f7 26224 #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) /*!< UART BAUD: EDIVM1 Mask */
<> 144:ef7eb2e8f9f7 26225
<> 144:ef7eb2e8f9f7 26226 #define UART_BAUD_BAUDM0_Pos (28) /*!< UART BAUD: BAUDM0 Position */
<> 144:ef7eb2e8f9f7 26227 #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) /*!< UART BAUD: BAUDM0 Mask */
<> 144:ef7eb2e8f9f7 26228
<> 144:ef7eb2e8f9f7 26229 #define UART_BAUD_BAUDM1_Pos (29) /*!< UART BAUD: BAUDM1 Position */
<> 144:ef7eb2e8f9f7 26230 #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) /*!< UART BAUD: BAUDM1 Mask */
<> 144:ef7eb2e8f9f7 26231
<> 144:ef7eb2e8f9f7 26232 #define UART_IRDA_TXEN_Pos (1) /*!< UART IRDA: TXEN Position */
<> 144:ef7eb2e8f9f7 26233 #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) /*!< UART IRDA: TXEN Mask */
<> 144:ef7eb2e8f9f7 26234
<> 144:ef7eb2e8f9f7 26235 #define UART_IRDA_TXINV_Pos (5) /*!< UART IRDA: TXINV Position */
<> 144:ef7eb2e8f9f7 26236 #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) /*!< UART IRDA: TXINV Mask */
<> 144:ef7eb2e8f9f7 26237
<> 144:ef7eb2e8f9f7 26238 #define UART_IRDA_RXINV_Pos (6) /*!< UART IRDA: RXINV Position */
<> 144:ef7eb2e8f9f7 26239 #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) /*!< UART IRDA: RXINV Mask */
<> 144:ef7eb2e8f9f7 26240
<> 144:ef7eb2e8f9f7 26241 #define UART_IRDA_FIXPULSE_Pos (7) /*!< UART IRDA: FIXPULSE Position */
<> 144:ef7eb2e8f9f7 26242 #define UART_IRDA_FIXPULSE_Msk (0x1ul << UART_IRDA_FIXPULSE_Pos) /*!< UART IRDA: FIXPULSE Mask */
<> 144:ef7eb2e8f9f7 26243
<> 144:ef7eb2e8f9f7 26244 #define UART_ALTCTL_BKFL_Pos (0) /*!< UART ALTCTL: BKFL Position */
<> 144:ef7eb2e8f9f7 26245 #define UART_ALTCTL_BKFL_Msk (0xful << UART_ALTCTL_BKFL_Pos) /*!< UART ALTCTL: BKFL Mask */
<> 144:ef7eb2e8f9f7 26246
<> 144:ef7eb2e8f9f7 26247 #define UART_ALTCTL_LINRXEN_Pos (6) /*!< UART ALTCTL: LINRXEN Position */
<> 144:ef7eb2e8f9f7 26248 #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) /*!< UART ALTCTL: LINRXEN Mask */
<> 144:ef7eb2e8f9f7 26249
<> 144:ef7eb2e8f9f7 26250 #define UART_ALTCTL_LINTXEN_Pos (7) /*!< UART ALTCTL: LINTXEN Position */
<> 144:ef7eb2e8f9f7 26251 #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) /*!< UART ALTCTL: LINTXEN Mask */
<> 144:ef7eb2e8f9f7 26252
<> 144:ef7eb2e8f9f7 26253 #define UART_ALTCTL_RS485NMM_Pos (8) /*!< UART ALTCTL: RS485NMM Position */
<> 144:ef7eb2e8f9f7 26254 #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) /*!< UART ALTCTL: RS485NMM Mask */
<> 144:ef7eb2e8f9f7 26255
<> 144:ef7eb2e8f9f7 26256 #define UART_ALTCTL_RS485AAD_Pos (9) /*!< UART ALTCTL: RS485AAD Position */
<> 144:ef7eb2e8f9f7 26257 #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) /*!< UART ALTCTL: RS485AAD Mask */
<> 144:ef7eb2e8f9f7 26258
<> 144:ef7eb2e8f9f7 26259 #define UART_ALTCTL_RS485AUD_Pos (10) /*!< UART ALTCTL: RS485AUD Position */
<> 144:ef7eb2e8f9f7 26260 #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) /*!< UART ALTCTL: RS485AUD Mask */
<> 144:ef7eb2e8f9f7 26261
<> 144:ef7eb2e8f9f7 26262 #define UART_ALTCTL_ADDRDEN_Pos (15) /*!< UART ALTCTL: ADDRDEN Position */
<> 144:ef7eb2e8f9f7 26263 #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) /*!< UART ALTCTL: ADDRDEN Mask */
<> 144:ef7eb2e8f9f7 26264
<> 144:ef7eb2e8f9f7 26265 #define UART_ALTCTL_ADDRMV_Pos (24) /*!< UART ALTCTL: ADDRMV Position */
<> 144:ef7eb2e8f9f7 26266 #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) /*!< UART ALTCTL: ADDRMV Mask */
<> 144:ef7eb2e8f9f7 26267
<> 144:ef7eb2e8f9f7 26268 #define UART_FUNCSEL_FUNCSEL_Pos (0) /*!< UART FUNCSEL: FUNCSEL Position */
<> 144:ef7eb2e8f9f7 26269 #define UART_FUNCSEL_FUNCSEL_Msk (0x7ul << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART FUNCSEL: FUNCSEL Mask */
<> 144:ef7eb2e8f9f7 26270
<> 144:ef7eb2e8f9f7 26271 #define UART_LINCTL_SLVEN_Pos (0) /*!< UART LINCTL: SLVEN Position */
<> 144:ef7eb2e8f9f7 26272 #define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) /*!< UART LINCTL: SLVEN Mask */
<> 144:ef7eb2e8f9f7 26273
<> 144:ef7eb2e8f9f7 26274 #define UART_LINCTL_SLVHDEN_Pos (1) /*!< UART LINCTL: SLVHDEN Position */
<> 144:ef7eb2e8f9f7 26275 #define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) /*!< UART LINCTL: SLVHDEN Mask */
<> 144:ef7eb2e8f9f7 26276
<> 144:ef7eb2e8f9f7 26277 #define UART_LINCTL_SLVAREN_Pos (2) /*!< UART LINCTL: SLVAREN Position */
<> 144:ef7eb2e8f9f7 26278 #define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) /*!< UART LINCTL: SLVAREN Mask */
<> 144:ef7eb2e8f9f7 26279
<> 144:ef7eb2e8f9f7 26280 #define UART_LINCTL_SLVDUEN_Pos (3) /*!< UART LINCTL: SLVDUEN Position */
<> 144:ef7eb2e8f9f7 26281 #define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) /*!< UART LINCTL: SLVDUEN Mask */
<> 144:ef7eb2e8f9f7 26282
<> 144:ef7eb2e8f9f7 26283 #define UART_LINCTL_MUTE_Pos (4) /*!< UART LINCTL: MUTE Position */
<> 144:ef7eb2e8f9f7 26284 #define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) /*!< UART LINCTL: MUTE Mask */
<> 144:ef7eb2e8f9f7 26285
<> 144:ef7eb2e8f9f7 26286 #define UART_LINCTL_SENDH_Pos (8) /*!< UART LINCTL: SENDH Position */
<> 144:ef7eb2e8f9f7 26287 #define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) /*!< UART LINCTL: SENDH Mask */
<> 144:ef7eb2e8f9f7 26288
<> 144:ef7eb2e8f9f7 26289 #define UART_LINCTL_IDPEN_Pos (9) /*!< UART LINCTL: IDPEN Position */
<> 144:ef7eb2e8f9f7 26290 #define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) /*!< UART LINCTL: IDPEN Mask */
<> 144:ef7eb2e8f9f7 26291
<> 144:ef7eb2e8f9f7 26292 #define UART_LINCTL_BRKDETEN_Pos (10) /*!< UART LINCTL: BRKDETEN Position */
<> 144:ef7eb2e8f9f7 26293 #define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) /*!< UART LINCTL: BRKDETEN Mask */
<> 144:ef7eb2e8f9f7 26294
<> 144:ef7eb2e8f9f7 26295 #define UART_LINCTL_RXOFF_Pos (11) /*!< UART LINCTL: RXOFF Position */
<> 144:ef7eb2e8f9f7 26296 #define UART_LINCTL_RXOFF_Msk (0x1ul << UART_LINCTL_RXOFF_Pos) /*!< UART LINCTL: RXOFF Mask */
<> 144:ef7eb2e8f9f7 26297
<> 144:ef7eb2e8f9f7 26298 #define UART_LINCTL_BITERREN_Pos (12) /*!< UART LINCTL: BITERREN Position */
<> 144:ef7eb2e8f9f7 26299 #define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) /*!< UART LINCTL: BITERREN Mask */
<> 144:ef7eb2e8f9f7 26300
<> 144:ef7eb2e8f9f7 26301 #define UART_LINCTL_BRKFL_Pos (16) /*!< UART LINCTL: BRKFL Position */
<> 144:ef7eb2e8f9f7 26302 #define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) /*!< UART LINCTL: BRKFL Mask */
<> 144:ef7eb2e8f9f7 26303
<> 144:ef7eb2e8f9f7 26304 #define UART_LINCTL_BSL_Pos (20) /*!< UART LINCTL: BSL Position */
<> 144:ef7eb2e8f9f7 26305 #define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) /*!< UART LINCTL: BSL Mask */
<> 144:ef7eb2e8f9f7 26306
<> 144:ef7eb2e8f9f7 26307 #define UART_LINCTL_HSEL_Pos (22) /*!< UART LINCTL: HSEL Position */
<> 144:ef7eb2e8f9f7 26308 #define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) /*!< UART LINCTL: HSEL Mask */
<> 144:ef7eb2e8f9f7 26309
<> 144:ef7eb2e8f9f7 26310 #define UART_LINCTL_PID_Pos (24) /*!< UART LINCTL: PID Position */
<> 144:ef7eb2e8f9f7 26311 #define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) /*!< UART LINCTL: PID Mask */
<> 144:ef7eb2e8f9f7 26312
<> 144:ef7eb2e8f9f7 26313 #define UART_LINSTS_SLVHDETF_Pos (0) /*!< UART LINSTS: SLVHDETF Position */
<> 144:ef7eb2e8f9f7 26314 #define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) /*!< UART LINSTS: SLVHDETF Mask */
<> 144:ef7eb2e8f9f7 26315
<> 144:ef7eb2e8f9f7 26316 #define UART_LINSTS_SLVHEF_Pos (1) /*!< UART LINSTS: SLVHEF Position */
<> 144:ef7eb2e8f9f7 26317 #define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) /*!< UART LINSTS: SLVHEF Mask */
<> 144:ef7eb2e8f9f7 26318
<> 144:ef7eb2e8f9f7 26319 #define UART_LINSTS_SLVIDPEF_Pos (2) /*!< UART LINSTS: SLVIDPEF Position */
<> 144:ef7eb2e8f9f7 26320 #define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) /*!< UART LINSTS: SLVIDPEF Mask */
<> 144:ef7eb2e8f9f7 26321
<> 144:ef7eb2e8f9f7 26322 #define UART_LINSTS_SLVSYNCF_Pos (3) /*!< UART LINSTS: SLVSYNCF Position */
<> 144:ef7eb2e8f9f7 26323 #define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) /*!< UART LINSTS: SLVSYNCF Mask */
<> 144:ef7eb2e8f9f7 26324
<> 144:ef7eb2e8f9f7 26325 #define UART_LINSTS_BRKDETF_Pos (8) /*!< UART LINSTS: BRKDETF Position */
<> 144:ef7eb2e8f9f7 26326 #define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) /*!< UART LINSTS: BRKDETF Mask */
<> 144:ef7eb2e8f9f7 26327
<> 144:ef7eb2e8f9f7 26328 #define UART_LINSTS_BITEF_Pos (9) /*!< UART LINSTS: BITEF Position */
<> 144:ef7eb2e8f9f7 26329 #define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) /*!< UART LINSTS: BITEF Mask */
<> 144:ef7eb2e8f9f7 26330
<> 144:ef7eb2e8f9f7 26331 #define UART_LINDEBUG_DEVERRF_Pos (0) /*!< UART LINDEBUG: DEVERRF Position */
<> 144:ef7eb2e8f9f7 26332 #define UART_LINDEBUG_DEVERRF_Msk (0x1ul << UART_LINDEBUG_DEVERRF_Pos) /*!< UART LINDEBUG: DEVERRF Mask */
<> 144:ef7eb2e8f9f7 26333
<> 144:ef7eb2e8f9f7 26334 #define UART_LINDEBUG_TOF_Pos (1) /*!< UART LINDEBUG: TOF Position */
<> 144:ef7eb2e8f9f7 26335 #define UART_LINDEBUG_TOF_Msk (0x1ul << UART_LINDEBUG_TOF_Pos) /*!< UART LINDEBUG: TOF Mask */
<> 144:ef7eb2e8f9f7 26336
<> 144:ef7eb2e8f9f7 26337 #define UART_LINDEBUG_FRAMEERRF_Pos (2) /*!< UART LINDEBUG: FRAMEERRF Position */
<> 144:ef7eb2e8f9f7 26338 #define UART_LINDEBUG_FRAMEERRF_Msk (0x1ul << UART_LINDEBUG_FRAMEERRF_Pos) /*!< UART LINDEBUG: FRAMEERRF Mask */
<> 144:ef7eb2e8f9f7 26339
<> 144:ef7eb2e8f9f7 26340 #define UART_LINDEBUG_SYNCERRF_Pos (3) /*!< UART LINDEBUG: SYNCERRF Position */
<> 144:ef7eb2e8f9f7 26341 #define UART_LINDEBUG_SYNCERRF_Msk (0x1ul << UART_LINDEBUG_SYNCERRF_Pos) /*!< UART LINDEBUG: SYNCERRF Mask */
<> 144:ef7eb2e8f9f7 26342
<> 144:ef7eb2e8f9f7 26343 /**@}*/ /* UART_CONST */
<> 144:ef7eb2e8f9f7 26344 /**@}*/ /* end of UART register group */
<> 144:ef7eb2e8f9f7 26345
<> 144:ef7eb2e8f9f7 26346
<> 144:ef7eb2e8f9f7 26347 /*---------------------- USB Host Controller -------------------------*/
<> 144:ef7eb2e8f9f7 26348 /**
<> 144:ef7eb2e8f9f7 26349 @addtogroup USBH USB Host Controller(USBH)
<> 144:ef7eb2e8f9f7 26350 Memory Mapped Structure for USBH Controller
<> 144:ef7eb2e8f9f7 26351 @{ */
<> 144:ef7eb2e8f9f7 26352
<> 144:ef7eb2e8f9f7 26353 typedef struct {
<> 144:ef7eb2e8f9f7 26354 /**
<> 144:ef7eb2e8f9f7 26355 * HcRevision
<> 144:ef7eb2e8f9f7 26356 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26357 * Offset: 0x00 Host Controller Revision Register
<> 144:ef7eb2e8f9f7 26358 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26359 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26360 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26361 * |[0:7] |REV |Revision
<> 144:ef7eb2e8f9f7 26362 * | | |Indicates the Open HCI Specification revision number implemented by the Hardware.
<> 144:ef7eb2e8f9f7 26363 * | | |Host Controller supports 1.1 specification.
<> 144:ef7eb2e8f9f7 26364 * | | |(X.Y = XYh).
<> 144:ef7eb2e8f9f7 26365 */
<> 144:ef7eb2e8f9f7 26366 __I uint32_t HcRevision;
<> 144:ef7eb2e8f9f7 26367
<> 144:ef7eb2e8f9f7 26368 /**
<> 144:ef7eb2e8f9f7 26369 * HcControl
<> 144:ef7eb2e8f9f7 26370 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26371 * Offset: 0x04 Host Controller Control Register
<> 144:ef7eb2e8f9f7 26372 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26373 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26374 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26375 * |[0:1] |CBSR |Control Bulk Service Ratio
<> 144:ef7eb2e8f9f7 26376 * | | |Specifies the number of Control Endpoints serviced for every Bulk Endpoint.
<> 144:ef7eb2e8f9f7 26377 * | | |Encoding is N-1 where N is the number of Control Endpoints (i.e.
<> 144:ef7eb2e8f9f7 26378 * | | |'00' = 1 Control Endpoint; '11' = 3 Control Endpoints).
<> 144:ef7eb2e8f9f7 26379 * |[2] |PLE |Periodic List Enable Control
<> 144:ef7eb2e8f9f7 26380 * | | |When set, this bit enables processing of the Periodic (interrupt and isochronous) list.
<> 144:ef7eb2e8f9f7 26381 * | | |The Host Controller checks this bit prior to attempting any periodic transfers in a frame.
<> 144:ef7eb2e8f9f7 26382 * |[3] |IE |Isochronous List Enable Control
<> 144:ef7eb2e8f9f7 26383 * | | |When cleared, this bit disables the Isochronous List when the Periodic List is enabled (so Interrupt EDs may be serviced).
<> 144:ef7eb2e8f9f7 26384 * | | |While processing the Periodic List, the Host Controller will check this bit when it finds an isochronous ED.
<> 144:ef7eb2e8f9f7 26385 * |[4] |CLE |Control List Enable Control
<> 144:ef7eb2e8f9f7 26386 * | | |When set, this bit enables processing of the Control list.
<> 144:ef7eb2e8f9f7 26387 * |[5] |BLE |Bulk List Enable Control
<> 144:ef7eb2e8f9f7 26388 * | | |When set, this bit enables processing of the Bulk list.
<> 144:ef7eb2e8f9f7 26389 * |[6:7] |HCFS |Host Controller Functional State
<> 144:ef7eb2e8f9f7 26390 * | | |This field sets the Host Controller state.
<> 144:ef7eb2e8f9f7 26391 * | | |The Controller may force a state change from USBSUSPEND to USBRESUME after detecting resume signaling from a downstream port.
<> 144:ef7eb2e8f9f7 26392 * | | |States are:.
<> 144:ef7eb2e8f9f7 26393 * | | |00 = USBSUSPEND.
<> 144:ef7eb2e8f9f7 26394 * | | |01 = USBOPERATIONAL.
<> 144:ef7eb2e8f9f7 26395 * | | |10 = USBRESUME.
<> 144:ef7eb2e8f9f7 26396 * | | |11 = USBRESET.
<> 144:ef7eb2e8f9f7 26397 * |[9] |RWC |Remote Wake-Up Connected
<> 144:ef7eb2e8f9f7 26398 * | | |This bit indicated whether the HC supports a remote wake-up signal.
<> 144:ef7eb2e8f9f7 26399 * | | |This implementation does not support any such signal.
<> 144:ef7eb2e8f9f7 26400 * | | |The bit is hard-coded to '0.'.
<> 144:ef7eb2e8f9f7 26401 * |[10] |RWE |Remote Wake-Up Connected Enable Control
<> 144:ef7eb2e8f9f7 26402 * | | |If a remote wake-up signal is supported, this bit enables that operation.
<> 144:ef7eb2e8f9f7 26403 * | | |Since there is no remote wake-up signal supported, this bit is ignored.
<> 144:ef7eb2e8f9f7 26404 */
<> 144:ef7eb2e8f9f7 26405 __IO uint32_t HcControl;
<> 144:ef7eb2e8f9f7 26406
<> 144:ef7eb2e8f9f7 26407 /**
<> 144:ef7eb2e8f9f7 26408 * HcCommandStatus
<> 144:ef7eb2e8f9f7 26409 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26410 * Offset: 0x08 Host Controller Command Status Register
<> 144:ef7eb2e8f9f7 26411 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26412 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26413 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26414 * |[0] |HCR |Host Controller Reset
<> 144:ef7eb2e8f9f7 26415 * | | |This bit is set to initiate the software reset.
<> 144:ef7eb2e8f9f7 26416 * | | |This bit is cleared by the Host Controller, upon completed of the reset operation.
<> 144:ef7eb2e8f9f7 26417 * |[1] |CLF |Control List Filled
<> 144:ef7eb2e8f9f7 26418 * | | |Set to indicate there is an active ED on the Control List.
<> 144:ef7eb2e8f9f7 26419 * | | |It may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Control List.
<> 144:ef7eb2e8f9f7 26420 * |[2] |BLF |Bulk List Filled
<> 144:ef7eb2e8f9f7 26421 * | | |Set to indicate there is an active ED on the Bulk List.
<> 144:ef7eb2e8f9f7 26422 * | | |The bit may be set by either software or the Host Controller and cleared by the Host Controller each time it begins processing the head of the Bulk List.
<> 144:ef7eb2e8f9f7 26423 * |[16:17] |SOC |Schedule Overrun Count
<> 144:ef7eb2e8f9f7 26424 * | | |This field is incremented every time the SchedulingOverrun bit in HcInterruptStatus is set.
<> 144:ef7eb2e8f9f7 26425 * | | |The count wraps from '11' to '00'.
<> 144:ef7eb2e8f9f7 26426 */
<> 144:ef7eb2e8f9f7 26427 __IO uint32_t HcCommandStatus;
<> 144:ef7eb2e8f9f7 26428
<> 144:ef7eb2e8f9f7 26429 /**
<> 144:ef7eb2e8f9f7 26430 * HcInterruptStatus
<> 144:ef7eb2e8f9f7 26431 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26432 * Offset: 0x0C Host Controller Interrupt Status Register
<> 144:ef7eb2e8f9f7 26433 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26434 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26435 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26436 * |[0] |SO |Scheduling Overrun
<> 144:ef7eb2e8f9f7 26437 * | | |Set when the List Processor determines a Schedule Overrun has occurred.
<> 144:ef7eb2e8f9f7 26438 * |[1] |WDH |Write Back Done Head
<> 144:ef7eb2e8f9f7 26439 * | | |Set after the Host Controller has written HcDoneHead to HccaDoneHead.
<> 144:ef7eb2e8f9f7 26440 * |[2] |SF |Start Of Frame
<> 144:ef7eb2e8f9f7 26441 * | | |Set when the Frame Management block signals a 'Start of Frame' event.
<> 144:ef7eb2e8f9f7 26442 * |[3] |RD |Resume Detected
<> 144:ef7eb2e8f9f7 26443 * | | |Set when Host Controller detects resume signaling on a downstream port.
<> 144:ef7eb2e8f9f7 26444 * |[4] |UE |Unrecoverable Error
<> 144:ef7eb2e8f9f7 26445 * | | |This event is not implemented and is hard-coded to '0.' Writes are ignored.
<> 144:ef7eb2e8f9f7 26446 * |[5] |FNOF |Frame Number Overflow
<> 144:ef7eb2e8f9f7 26447 * | | |Set when bit 15 of Frame Number changes value.
<> 144:ef7eb2e8f9f7 26448 * |[6] |RHSC |Root Hub Status Change
<> 144:ef7eb2e8f9f7 26449 * | | |This bit is set when the content of HcRhStatus or the content of any HcRhPortStatus register has changed.
<> 144:ef7eb2e8f9f7 26450 */
<> 144:ef7eb2e8f9f7 26451 __IO uint32_t HcInterruptStatus;
<> 144:ef7eb2e8f9f7 26452
<> 144:ef7eb2e8f9f7 26453 /**
<> 144:ef7eb2e8f9f7 26454 * HcInterruptEnable
<> 144:ef7eb2e8f9f7 26455 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26456 * Offset: 0x10 Host Controller Interrupt Enable Control Register
<> 144:ef7eb2e8f9f7 26457 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26458 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26459 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26460 * |[0] |SO |Scheduling Overrun Enable Control
<> 144:ef7eb2e8f9f7 26461 * | | |0 = The interrupt function Disabled.
<> 144:ef7eb2e8f9f7 26462 * | | |1 = Interrupt generation Enabled due to Scheduling Overrun.
<> 144:ef7eb2e8f9f7 26463 * |[1] |WDH |Write Back Done Head Enable Control
<> 144:ef7eb2e8f9f7 26464 * | | |0 = The interrupt function Disabled.
<> 144:ef7eb2e8f9f7 26465 * | | |1 = Interrupt generation Enabled due to Write-back Done Head.
<> 144:ef7eb2e8f9f7 26466 * |[2] |SF |Start Of Frame Enable Control
<> 144:ef7eb2e8f9f7 26467 * | | |0 = The interrupt function Disabled.
<> 144:ef7eb2e8f9f7 26468 * | | |1 = interrupt generation Enabled due to Start of Frame.
<> 144:ef7eb2e8f9f7 26469 * |[3] |RD |Resume Detected Enable Control
<> 144:ef7eb2e8f9f7 26470 * | | |0 = The interrupt function Disabled.
<> 144:ef7eb2e8f9f7 26471 * | | |1 = interrupt generation Enabled due to Resume Detected.
<> 144:ef7eb2e8f9f7 26472 * |[4] |UE |Unrecoverable Error Enable Control
<> 144:ef7eb2e8f9f7 26473 * | | |This event is not implemented. All writes to this bit are ignored.
<> 144:ef7eb2e8f9f7 26474 * |[5] |FNO |Frame Number Overflow Enable Control
<> 144:ef7eb2e8f9f7 26475 * | | |0 = The interrupt function Disabled.
<> 144:ef7eb2e8f9f7 26476 * | | |1 = Interrupt generation Enabled due to Frame Number Overflow.
<> 144:ef7eb2e8f9f7 26477 * |[6] |RHSC |Root Hub Status Change Enable Control
<> 144:ef7eb2e8f9f7 26478 * | | |0 = The interrupt function Disabled.
<> 144:ef7eb2e8f9f7 26479 * | | |1 = interrupt generation Enabled due to Root Hub Status Change.
<> 144:ef7eb2e8f9f7 26480 * |[31] |MIE |Master Interrupt Enable Control
<> 144:ef7eb2e8f9f7 26481 * | | |This bit is a global interrupt enable.
<> 144:ef7eb2e8f9f7 26482 * | | |A write of '1' allows interrupts to be enabled via the specific enable bits listed above.
<> 144:ef7eb2e8f9f7 26483 */
<> 144:ef7eb2e8f9f7 26484 __IO uint32_t HcInterruptEnable;
<> 144:ef7eb2e8f9f7 26485
<> 144:ef7eb2e8f9f7 26486 /**
<> 144:ef7eb2e8f9f7 26487 * HcInterruptDisable
<> 144:ef7eb2e8f9f7 26488 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26489 * Offset: 0x14 Host Controller Interrupt Disable Control Register
<> 144:ef7eb2e8f9f7 26490 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26491 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26492 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26493 * |[0] |SO |Scheduling Overrun Disable Control
<> 144:ef7eb2e8f9f7 26494 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 26495 * | | |1 = Interrupt generation Disabled due to Scheduling Overrun.
<> 144:ef7eb2e8f9f7 26496 * |[1] |WDH |Write Back Done Head Disable Control
<> 144:ef7eb2e8f9f7 26497 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 26498 * | | |1 = Interrupt generation Disabled due to Write-back Done Head.
<> 144:ef7eb2e8f9f7 26499 * |[2] |SF |Start Of Frame Disable Control
<> 144:ef7eb2e8f9f7 26500 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 26501 * | | |1 = Interrupt generation Disabled due to Start of Frame.
<> 144:ef7eb2e8f9f7 26502 * |[3] |RD |Resume Detected Disable Control
<> 144:ef7eb2e8f9f7 26503 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 26504 * | | |1 = Interrupt generation Disabled due to Resume Detected.
<> 144:ef7eb2e8f9f7 26505 * |[4] |UE |Unrecoverable Error Disable Control
<> 144:ef7eb2e8f9f7 26506 * | | |This event is not implemented. All writes to this bit are ignored.
<> 144:ef7eb2e8f9f7 26507 * |[5] |FNO |Frame Number Overflow Disable Control
<> 144:ef7eb2e8f9f7 26508 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 26509 * | | |1 = Interrupt generation Disabled due to Frame Number Overflow.
<> 144:ef7eb2e8f9f7 26510 * |[6] |RHSC |Root Hub Status Change Disable Control
<> 144:ef7eb2e8f9f7 26511 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 26512 * | | |1 = Interrupt generation Disabled due to Root Hub Status Change.
<> 144:ef7eb2e8f9f7 26513 * |[31] |MIE |Master Interrupt Disable Control
<> 144:ef7eb2e8f9f7 26514 * | | |Global interrupt disable. Writing '1' to disable all interrupts.
<> 144:ef7eb2e8f9f7 26515 */
<> 144:ef7eb2e8f9f7 26516 __IO uint32_t HcInterruptDisable;
<> 144:ef7eb2e8f9f7 26517
<> 144:ef7eb2e8f9f7 26518 /**
<> 144:ef7eb2e8f9f7 26519 * HcHCCA
<> 144:ef7eb2e8f9f7 26520 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26521 * Offset: 0x18 Host Controller Communication Area Register
<> 144:ef7eb2e8f9f7 26522 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26523 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26524 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26525 * |[8:31] |HCCA |Host Controller Communication Area
<> 144:ef7eb2e8f9f7 26526 * | | |Pointer to HCCA base address.
<> 144:ef7eb2e8f9f7 26527 */
<> 144:ef7eb2e8f9f7 26528 __IO uint32_t HcHCCA;
<> 144:ef7eb2e8f9f7 26529
<> 144:ef7eb2e8f9f7 26530 /**
<> 144:ef7eb2e8f9f7 26531 * HcPeriodCurrentED
<> 144:ef7eb2e8f9f7 26532 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26533 * Offset: 0x1C Host Controller Period Current ED Register
<> 144:ef7eb2e8f9f7 26534 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26535 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26536 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26537 * |[4:31] |PCED |Periodic Current ED
<> 144:ef7eb2e8f9f7 26538 * | | |Pointer to the current Periodic List ED.
<> 144:ef7eb2e8f9f7 26539 */
<> 144:ef7eb2e8f9f7 26540 __IO uint32_t HcPeriodCurrentED;
<> 144:ef7eb2e8f9f7 26541
<> 144:ef7eb2e8f9f7 26542 /**
<> 144:ef7eb2e8f9f7 26543 * HcControlHeadED
<> 144:ef7eb2e8f9f7 26544 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26545 * Offset: 0x20 Host Controller Control Head ED Register
<> 144:ef7eb2e8f9f7 26546 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26547 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26548 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26549 * |[4:31] |CHED |Control Head ED
<> 144:ef7eb2e8f9f7 26550 * | | |Pointer to the Control List Head ED.
<> 144:ef7eb2e8f9f7 26551 */
<> 144:ef7eb2e8f9f7 26552 __IO uint32_t HcControlHeadED;
<> 144:ef7eb2e8f9f7 26553
<> 144:ef7eb2e8f9f7 26554 /**
<> 144:ef7eb2e8f9f7 26555 * HcControlCurrentED
<> 144:ef7eb2e8f9f7 26556 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26557 * Offset: 0x24 Host Controller Control Current ED Register
<> 144:ef7eb2e8f9f7 26558 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26559 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26560 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26561 * |[4:31] |CCED |Control Current Head ED
<> 144:ef7eb2e8f9f7 26562 * | | |Pointer to the current Control List Head ED.
<> 144:ef7eb2e8f9f7 26563 */
<> 144:ef7eb2e8f9f7 26564 __IO uint32_t HcControlCurrentED;
<> 144:ef7eb2e8f9f7 26565
<> 144:ef7eb2e8f9f7 26566 /**
<> 144:ef7eb2e8f9f7 26567 * HcBulkHeadED
<> 144:ef7eb2e8f9f7 26568 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26569 * Offset: 0x28 Host Controller Bulk Head ED Register
<> 144:ef7eb2e8f9f7 26570 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26571 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26572 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26573 * |[4:31] |BHED |Bulk Head ED
<> 144:ef7eb2e8f9f7 26574 * | | |Pointer to the Bulk List Head ED.
<> 144:ef7eb2e8f9f7 26575 */
<> 144:ef7eb2e8f9f7 26576 __IO uint32_t HcBulkHeadED;
<> 144:ef7eb2e8f9f7 26577
<> 144:ef7eb2e8f9f7 26578 /**
<> 144:ef7eb2e8f9f7 26579 * HcBulkCurrentED
<> 144:ef7eb2e8f9f7 26580 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26581 * Offset: 0x2C Host Controller Bulk Current ED Register
<> 144:ef7eb2e8f9f7 26582 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26583 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26584 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26585 * |[4:31] |BCED |Bulk Current Head ED
<> 144:ef7eb2e8f9f7 26586 * | | |Pointer to the current Bulk List Head ED.
<> 144:ef7eb2e8f9f7 26587 */
<> 144:ef7eb2e8f9f7 26588 __IO uint32_t HcBulkCurrentED;
<> 144:ef7eb2e8f9f7 26589
<> 144:ef7eb2e8f9f7 26590 /**
<> 144:ef7eb2e8f9f7 26591 * HcDoneHead
<> 144:ef7eb2e8f9f7 26592 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26593 * Offset: 0x30 Host Controller Done Head Register
<> 144:ef7eb2e8f9f7 26594 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26595 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26596 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26597 * |[4:31] |DH |Done Head
<> 144:ef7eb2e8f9f7 26598 * | | |Pointer to the current Done List Head ED.
<> 144:ef7eb2e8f9f7 26599 */
<> 144:ef7eb2e8f9f7 26600 __IO uint32_t HcDoneHead;
<> 144:ef7eb2e8f9f7 26601
<> 144:ef7eb2e8f9f7 26602 /**
<> 144:ef7eb2e8f9f7 26603 * HcFmInterval
<> 144:ef7eb2e8f9f7 26604 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26605 * Offset: 0x34 Host Controller Frame Interval Register
<> 144:ef7eb2e8f9f7 26606 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26607 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26608 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26609 * |[0:13] |FI |Frame Interval
<> 144:ef7eb2e8f9f7 26610 * | | |This field specifies the length of a frame as (bit times - 1).
<> 144:ef7eb2e8f9f7 26611 * | | |For 12,000 bit times in a frame, a value of 11,999 is stored here.
<> 144:ef7eb2e8f9f7 26612 * |[16:30] |FSMPS |FS Largest Data Packet
<> 144:ef7eb2e8f9f7 26613 * | | |This field specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame.
<> 144:ef7eb2e8f9f7 26614 * |[31] |FIT |Frame Interval Toggle
<> 144:ef7eb2e8f9f7 26615 * | | |This bit is toggled by HCD when it loads a new value into Frame Interval.
<> 144:ef7eb2e8f9f7 26616 */
<> 144:ef7eb2e8f9f7 26617 __IO uint32_t HcFmInterval;
<> 144:ef7eb2e8f9f7 26618
<> 144:ef7eb2e8f9f7 26619 /**
<> 144:ef7eb2e8f9f7 26620 * HcFmRemaining
<> 144:ef7eb2e8f9f7 26621 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26622 * Offset: 0x38 Host Controller Frame Remaining Register
<> 144:ef7eb2e8f9f7 26623 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26624 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26625 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26626 * |[0:13] |FR |Frame Remaining
<> 144:ef7eb2e8f9f7 26627 * | | |When the Host Controller is in the USBOPERATIONAL state, this 14-bit field decrements each 12 MHz clock period.
<> 144:ef7eb2e8f9f7 26628 * | | |When the count reaches 0, (end of frame) the counter reloads with Frame Interval.
<> 144:ef7eb2e8f9f7 26629 * | | |In addition, the counter loads when the Host Controller transitions into USBOPERATIONAL.
<> 144:ef7eb2e8f9f7 26630 * |[31] |FRT |Frame Remaining Toggle
<> 144:ef7eb2e8f9f7 26631 * | | |Loaded with Frame Interval Toggle when FrameRemaining is loaded.
<> 144:ef7eb2e8f9f7 26632 */
<> 144:ef7eb2e8f9f7 26633 __I uint32_t HcFmRemaining;
<> 144:ef7eb2e8f9f7 26634
<> 144:ef7eb2e8f9f7 26635 /**
<> 144:ef7eb2e8f9f7 26636 * HcFmNumber
<> 144:ef7eb2e8f9f7 26637 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26638 * Offset: 0x3C Host Controller Frame Number Register
<> 144:ef7eb2e8f9f7 26639 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26640 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26641 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26642 * |[0:15] |FN |Frame Number
<> 144:ef7eb2e8f9f7 26643 * | | |This 16-bit incrementing counter field is incremented coincident with the loading of FrameRemaining.
<> 144:ef7eb2e8f9f7 26644 * | | |The count rolls over from 'FFFFh' to '0h.'.
<> 144:ef7eb2e8f9f7 26645 */
<> 144:ef7eb2e8f9f7 26646 __I uint32_t HcFmNumber;
<> 144:ef7eb2e8f9f7 26647
<> 144:ef7eb2e8f9f7 26648 /**
<> 144:ef7eb2e8f9f7 26649 * HcPeriodicStart
<> 144:ef7eb2e8f9f7 26650 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26651 * Offset: 0x40 Host Controller Periodic Start Register
<> 144:ef7eb2e8f9f7 26652 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26653 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26654 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26655 * |[0:13] |PS |Periodic Start
<> 144:ef7eb2e8f9f7 26656 * | | |This field contains a value used by the List Processor to determine where in a frame the Periodic List processing must begin.
<> 144:ef7eb2e8f9f7 26657 */
<> 144:ef7eb2e8f9f7 26658 __IO uint32_t HcPeriodicStart;
<> 144:ef7eb2e8f9f7 26659
<> 144:ef7eb2e8f9f7 26660 /**
<> 144:ef7eb2e8f9f7 26661 * HcLSThreshold
<> 144:ef7eb2e8f9f7 26662 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26663 * Offset: 0x44 Host Controller Low-speed Threshold Register
<> 144:ef7eb2e8f9f7 26664 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26665 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26666 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26667 * |[0:11] |LST |Low-Speed Threshold
<> 144:ef7eb2e8f9f7 26668 * | | |This field contains a value which is compared to the FrameRemaining field prior to initiating a Low-speed transaction.
<> 144:ef7eb2e8f9f7 26669 * | | |The transaction is started only if FrameRemaining >= this field.
<> 144:ef7eb2e8f9f7 26670 * | | |The value is calculated by HCD with the consideration of transmission and setup overhead.
<> 144:ef7eb2e8f9f7 26671 */
<> 144:ef7eb2e8f9f7 26672 __IO uint32_t HcLSThreshold;
<> 144:ef7eb2e8f9f7 26673
<> 144:ef7eb2e8f9f7 26674 /**
<> 144:ef7eb2e8f9f7 26675 * HcRhDescriptorA
<> 144:ef7eb2e8f9f7 26676 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26677 * Offset: 0x48 Host Controller Root Hub Descriptor A Register
<> 144:ef7eb2e8f9f7 26678 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26679 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26680 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26681 * |[0:7] |NDP |Number Downstream Ports
<> 144:ef7eb2e8f9f7 26682 * | | |Root Hub supports two downstream ports. It's 2 in this Root Hub.
<> 144:ef7eb2e8f9f7 26683 * |[8] |PSM |Power Switching Mode
<> 144:ef7eb2e8f9f7 26684 * | | |Global power switching mode implemented in Root Hub.
<> 144:ef7eb2e8f9f7 26685 * | | |This bit is only valid when NPS bit is cleared.
<> 144:ef7eb2e8f9f7 26686 * | | |This bit should be written '0'.
<> 144:ef7eb2e8f9f7 26687 * | | |0 = Global Switching.
<> 144:ef7eb2e8f9f7 26688 * | | |1 = Individual Switching.
<> 144:ef7eb2e8f9f7 26689 * |[9] |NPS |No Power Switching
<> 144:ef7eb2e8f9f7 26690 * | | |Global power switching implemented in Root Hub.
<> 144:ef7eb2e8f9f7 26691 * | | |This bit should be written to support the external system port power switching implementation.
<> 144:ef7eb2e8f9f7 26692 * | | |0 = Ports are power switched.
<> 144:ef7eb2e8f9f7 26693 * | | |1 = Ports are always powered on.
<> 144:ef7eb2e8f9f7 26694 * |[10] |DT |Device Type
<> 144:ef7eb2e8f9f7 26695 * | | |The OHCI Root Hub is not a compound device.
<> 144:ef7eb2e8f9f7 26696 * |[11] |OCPM |Overcurrent Protection Mode
<> 144:ef7eb2e8f9f7 26697 * | | |Global overcurrent reporting implemented in Root Hub.
<> 144:ef7eb2e8f9f7 26698 * | | |This bit should be written 0 and is only valid when NOCP bit is cleared.
<> 144:ef7eb2e8f9f7 26699 * | | |0 = Global Overcurrent.
<> 144:ef7eb2e8f9f7 26700 * | | |1 = Individual Overcurrent.
<> 144:ef7eb2e8f9f7 26701 * |[12] |NOCP |No Overcurrent Protection
<> 144:ef7eb2e8f9f7 26702 * | | |Global overcurrent reporting implemented in Root Hub.
<> 144:ef7eb2e8f9f7 26703 * | | |This bit should be written to support the external system port overcurrent implementation.
<> 144:ef7eb2e8f9f7 26704 * | | |0 = Overcurrent status is reported.
<> 144:ef7eb2e8f9f7 26705 * | | |1 = Overcurrent status is not reported.
<> 144:ef7eb2e8f9f7 26706 * |[24:31] |POTGT |Power On To Power Good Time
<> 144:ef7eb2e8f9f7 26707 * | | |This field value is represented as the number of 2 ms intervals, which ensuring that the power switching is effective within 2 ms.
<> 144:ef7eb2e8f9f7 26708 * | | |Only bits [25:24] are implemented as R/W.
<> 144:ef7eb2e8f9f7 26709 * | | |The remaining bits are read only as '0'.
<> 144:ef7eb2e8f9f7 26710 * | | |It is not expected that these bits be written to anything other than 1h, but limited adjustment is provided.
<> 144:ef7eb2e8f9f7 26711 * | | |This field should be written to support system implementation.
<> 144:ef7eb2e8f9f7 26712 * | | |This field should always be written to a non-zero value.
<> 144:ef7eb2e8f9f7 26713 */
<> 144:ef7eb2e8f9f7 26714 __IO uint32_t HcRhDescriptorA;
<> 144:ef7eb2e8f9f7 26715
<> 144:ef7eb2e8f9f7 26716 /**
<> 144:ef7eb2e8f9f7 26717 * HcRhDescriptorB
<> 144:ef7eb2e8f9f7 26718 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26719 * Offset: 0x4C Host Controller Root Hub Descriptor B Register
<> 144:ef7eb2e8f9f7 26720 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26721 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26722 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26723 * |[0:2] |DR |Device Removable
<> 144:ef7eb2e8f9f7 26724 * | | |Root Hub ports default to removable devices.
<> 144:ef7eb2e8f9f7 26725 * | | |0 = Device not removable.
<> 144:ef7eb2e8f9f7 26726 * | | |1 = Device removable.
<> 144:ef7eb2e8f9f7 26727 * | | |Port Bit relationship:
<> 144:ef7eb2e8f9f7 26728 * | | |DevRemove[0] = Reserved.
<> 144:ef7eb2e8f9f7 26729 * | | |DevRemove[1] = Port 1.
<> 144:ef7eb2e8f9f7 26730 * | | |DevRemove[2] = Port 2.
<> 144:ef7eb2e8f9f7 26731 */
<> 144:ef7eb2e8f9f7 26732 __IO uint32_t HcRhDescriptorB;
<> 144:ef7eb2e8f9f7 26733
<> 144:ef7eb2e8f9f7 26734 /**
<> 144:ef7eb2e8f9f7 26735 * HcRhStatus
<> 144:ef7eb2e8f9f7 26736 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26737 * Offset: 0x50 Host Controller Root Hub Status Register
<> 144:ef7eb2e8f9f7 26738 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26739 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26740 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26741 * |[0] |LPS |LocalPowerStatus (Read)
<> 144:ef7eb2e8f9f7 26742 * | | |Not Supported. Always read '0'.
<> 144:ef7eb2e8f9f7 26743 * | | |ClearGlobalPower (Write)
<> 144:ef7eb2e8f9f7 26744 * | | |Writing '1' issues a ClearGlobalPower command to the ports. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26745 * |[1] |OCI |Overcurrent Indicator
<> 144:ef7eb2e8f9f7 26746 * | | |This bit reflects the state of the OVRCUR pin.
<> 144:ef7eb2e8f9f7 26747 * | | |This field is only valid if NOCP (RHDESA[12]) and OCPM (RHDESA[11]) are cleared.
<> 144:ef7eb2e8f9f7 26748 * | | |0 = No overcurrent condition.
<> 144:ef7eb2e8f9f7 26749 * | | |1 = Overcurrent condition.
<> 144:ef7eb2e8f9f7 26750 * |[15] |DRWE |Device Remote Wake-Up Enable Control (Read)
<> 144:ef7eb2e8f9f7 26751 * | | |This bit enables ports' CC (HcRhPtr[0]) as a remote wake-up event.
<> 144:ef7eb2e8f9f7 26752 * | | |0 = Disabled.
<> 144:ef7eb2e8f9f7 26753 * | | |1 = Enabled.
<> 144:ef7eb2e8f9f7 26754 * | | |Set Remote Wake-up Enable Control (Write)
<> 144:ef7eb2e8f9f7 26755 * | | |Writing 1' sets DRWEn. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26756 * |[16] |LPSC |Local Power Status Change (Read)
<> 144:ef7eb2e8f9f7 26757 * | | |Not supported. Always read '0'.
<> 144:ef7eb2e8f9f7 26758 * | | |SetGlobalPower (Write)
<> 144:ef7eb2e8f9f7 26759 * | | |Writing '1' issues a SetGlobalPower command to the ports. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26760 * |[17] |OCIC |Overcurrent Indicator Change
<> 144:ef7eb2e8f9f7 26761 * | | |This bit is set when OC bit changes.
<> 144:ef7eb2e8f9f7 26762 * | | |Writing '1' clears this bit. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26763 * |[31] |CRWE |Clear Remote Wake-Up Enable Control
<> 144:ef7eb2e8f9f7 26764 * | | |Writing '1' to this bit clears DRWEn (HcRhStatus[15]). Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26765 */
<> 144:ef7eb2e8f9f7 26766 __IO uint32_t HcRhStatus;
<> 144:ef7eb2e8f9f7 26767
<> 144:ef7eb2e8f9f7 26768 /**
<> 144:ef7eb2e8f9f7 26769 * HcRhPortStatus1/HcRhPortStatus2
<> 144:ef7eb2e8f9f7 26770 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26771 * Offset: 0x54,0x58 Host Controller Root Hub Port Status [1/2]
<> 144:ef7eb2e8f9f7 26772 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26773 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26774 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26775 * |[0] |CCS |Current Connect Status (Read)
<> 144:ef7eb2e8f9f7 26776 * | | |0 = No device connected.
<> 144:ef7eb2e8f9f7 26777 * | | |1 = Device connected.
<> 144:ef7eb2e8f9f7 26778 * | | |Clear Port Enable Control (Write)
<> 144:ef7eb2e8f9f7 26779 * | | |Writing '1' a clears PE. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26780 * |[1] |PES |Port Enable Status (Read)
<> 144:ef7eb2e8f9f7 26781 * | | |0 = Port Disabled.
<> 144:ef7eb2e8f9f7 26782 * | | |1 = Port Enabled.
<> 144:ef7eb2e8f9f7 26783 * | | |SetPortEnable (Write)
<> 144:ef7eb2e8f9f7 26784 * | | |Writing '1' sets PE. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26785 * |[2] |PSS |PortSuspendStatus (Read)
<> 144:ef7eb2e8f9f7 26786 * | | |0 = Port is not suspended.
<> 144:ef7eb2e8f9f7 26787 * | | |1 = Port is selectively suspended.
<> 144:ef7eb2e8f9f7 26788 * | | |SetPortSuspend (Write)
<> 144:ef7eb2e8f9f7 26789 * | | |Writing '1' sets PortSuspendStatus. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26790 * |[3] |POCI |PortOverCurrentIndicator (Read)
<> 144:ef7eb2e8f9f7 26791 * | | |Root Hub supports global overcurrent reporting.
<> 144:ef7eb2e8f9f7 26792 * | | |This bit reflects the state of the OVRCUR pin dedicated to this port.
<> 144:ef7eb2e8f9f7 26793 * | | |This field is only valid if NOCP (RHDESA[12]) is cleared and OCPM (RHDESA[11]) is set.
<> 144:ef7eb2e8f9f7 26794 * | | |0 = No overcurrent condition.
<> 144:ef7eb2e8f9f7 26795 * | | |1 = Overcurrent condition.
<> 144:ef7eb2e8f9f7 26796 * | | |ClearPortSuspend (Write)
<> 144:ef7eb2e8f9f7 26797 * | | |Writing '1' initiates the selective resume sequence for the port. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26798 * |[4] |PRS |PortResetStatus (Read)
<> 144:ef7eb2e8f9f7 26799 * | | |This bit reflects the power state of the port regardless of the power switching mode.
<> 144:ef7eb2e8f9f7 26800 * | | |0 = Port reset signal is not active.
<> 144:ef7eb2e8f9f7 26801 * | | |1 = Port reset signal is active.
<> 144:ef7eb2e8f9f7 26802 * | | |SetPortReset (Write)
<> 144:ef7eb2e8f9f7 26803 * | | |Writing '1' sets PR. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26804 * |[8] |PPS |PortPowerStatus (Read)
<> 144:ef7eb2e8f9f7 26805 * | | |This bit reflects the power state of the port regardless of the power switching mode.
<> 144:ef7eb2e8f9f7 26806 * | | |0 = Port power is off.
<> 144:ef7eb2e8f9f7 26807 * | | |1 = Port power is on.
<> 144:ef7eb2e8f9f7 26808 * | | |Note: If NPS (RHDESA[9]) is set, this bit is always read as '1'.
<> 144:ef7eb2e8f9f7 26809 * | | |SetPortPower (Write)
<> 144:ef7eb2e8f9f7 26810 * | | |Writing '1' sets PPS. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26811 * |[9] |LSDA |LowSpeedDeviceAttached (Read)
<> 144:ef7eb2e8f9f7 26812 * | | |This bit defines the speed (and bud idle) of the attached device. It is only valid when CC bit is set.
<> 144:ef7eb2e8f9f7 26813 * | | |0 = Full Speed device.
<> 144:ef7eb2e8f9f7 26814 * | | |1 = Low-speed device.
<> 144:ef7eb2e8f9f7 26815 * | | |ClearPortPower (Write)
<> 144:ef7eb2e8f9f7 26816 * | | |Writing '1' clears PPS bit. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26817 * |[16] |CSC |Connect Status Change
<> 144:ef7eb2e8f9f7 26818 * | | |This bit indicates connect or disconnect event has been detected.
<> 144:ef7eb2e8f9f7 26819 * | | |Writing '1' clears this bit.
<> 144:ef7eb2e8f9f7 26820 * | | |Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26821 * | | |0 = No connect/disconnect event.
<> 144:ef7eb2e8f9f7 26822 * | | |1 = Hardware detection of connect/disconnect event.
<> 144:ef7eb2e8f9f7 26823 * | | |Note: If DevRemove (HcRhDescriptorB[2:0]) is set, this bit resets to '1'.
<> 144:ef7eb2e8f9f7 26824 * |[17] |PESC |Port Enable Status Change
<> 144:ef7eb2e8f9f7 26825 * | | |This bit indicates that the port has been disabled due to a hardware event (cleared PE bit).
<> 144:ef7eb2e8f9f7 26826 * | | |0 = No port enable change event.
<> 144:ef7eb2e8f9f7 26827 * | | |1 = Port enable state has been changed.
<> 144:ef7eb2e8f9f7 26828 * |[18] |PSSC |Port Reset Status Change
<> 144:ef7eb2e8f9f7 26829 * | | |This bit indicates the completion of the selective resume sequence for the port.
<> 144:ef7eb2e8f9f7 26830 * | | |0 = Port is not resumed.
<> 144:ef7eb2e8f9f7 26831 * | | |1 = Port resume is complete.
<> 144:ef7eb2e8f9f7 26832 * |[19] |OCIC |Port Overcurrent Indicator Change
<> 144:ef7eb2e8f9f7 26833 * | | |This bit is set when OC (HcRhStatus[1]) changes. Writing '1' clears this bit. Writing '0' has no effect.
<> 144:ef7eb2e8f9f7 26834 * |[20] |PRSC |Port Reset Status Change
<> 144:ef7eb2e8f9f7 26835 * | | |This bit indicates that the port reset signal has completed.
<> 144:ef7eb2e8f9f7 26836 * | | |0 = Port reset is not complete.
<> 144:ef7eb2e8f9f7 26837 * | | |1 = Port reset is complete.
<> 144:ef7eb2e8f9f7 26838 */
<> 144:ef7eb2e8f9f7 26839 __IO uint32_t HcRhPortStatus[2];
<> 144:ef7eb2e8f9f7 26840
<> 144:ef7eb2e8f9f7 26841 uint32_t RESERVE0[105];
<> 144:ef7eb2e8f9f7 26842
<> 144:ef7eb2e8f9f7 26843
<> 144:ef7eb2e8f9f7 26844 /**
<> 144:ef7eb2e8f9f7 26845 * HcPhyControl
<> 144:ef7eb2e8f9f7 26846 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26847 * Offset: 0x200 USB PHY Control Register
<> 144:ef7eb2e8f9f7 26848 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26849 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26850 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26851 * |[27] |STBYEN |USB Transceiver Standby Enable Control
<> 144:ef7eb2e8f9f7 26852 * | | |This bit controls if USB 1.1 transceiver could enter the standby mode to reduce power consumption.
<> 144:ef7eb2e8f9f7 26853 * | | |If this bit is low, the USB 1.1 transceiver would never enter the standby mode.
<> 144:ef7eb2e8f9f7 26854 * | | |If this bit is high, the USB 1.1 transceiver will enter standby mode while port is in power off state (port power is inactive).
<> 144:ef7eb2e8f9f7 26855 */
<> 144:ef7eb2e8f9f7 26856 __IO uint32_t HcPhyControl;
<> 144:ef7eb2e8f9f7 26857
<> 144:ef7eb2e8f9f7 26858 /**
<> 144:ef7eb2e8f9f7 26859 * HcMiscControl
<> 144:ef7eb2e8f9f7 26860 * ===================================================================================================
<> 144:ef7eb2e8f9f7 26861 * Offset: 0x204 USB Operational Mode Enable Control Register
<> 144:ef7eb2e8f9f7 26862 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 26863 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 26864 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 26865 * |[0] |DBR16 |Data Buffer Region 16
<> 144:ef7eb2e8f9f7 26866 * | | |When set, the size of the data buffer region is 16 bytes. Otherwise, the size is 32 bytes.
<> 144:ef7eb2e8f9f7 26867 * |[1] |ABORT |AHB Bus ERROR Response
<> 144:ef7eb2e8f9f7 26868 * | | |This bit indicates there is an ERROR response received in AHB bus.
<> 144:ef7eb2e8f9f7 26869 * | | |0 = No ERROR response received.
<> 144:ef7eb2e8f9f7 26870 * | | |1 = ERROR response received.
<> 144:ef7eb2e8f9f7 26871 * |[3] |OCA |Overcurrent Active Low
<> 144:ef7eb2e8f9f7 26872 * | | |This bit controls the polarity of overcurrent flag from external power IC.
<> 144:ef7eb2e8f9f7 26873 * | | |0 = Overcurrent flag is high active.
<> 144:ef7eb2e8f9f7 26874 * | | |1 = Overcurrent flag is low active.
<> 144:ef7eb2e8f9f7 26875 * |[4] |PCAL |Port Power Control Active Low
<> 144:ef7eb2e8f9f7 26876 * | | |This bit controls the polarity of port power control to external power IC.
<> 144:ef7eb2e8f9f7 26877 * | | |0 = Port power control is high active.
<> 144:ef7eb2e8f9f7 26878 * | | |1 = Port power control is low active.
<> 144:ef7eb2e8f9f7 26879 * |[8] |SIEPD |SIE Pipeline Disable Control
<> 144:ef7eb2e8f9f7 26880 * | | |When set, waits for all USB bus activity to complete prior to returning completion status to the List Processor.
<> 144:ef7eb2e8f9f7 26881 * | | |This is a fail safe mechanism to avoid potential problems with the clk_dr transition between 1.5 MHz and 12 MHz.
<> 144:ef7eb2e8f9f7 26882 * |[16] |DPRT1 |Port 1 Disable Control
<> 144:ef7eb2e8f9f7 26883 * | | |This bit controls if the connection between USB host controller and transceiver of port 1 is disabled.
<> 144:ef7eb2e8f9f7 26884 * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
<> 144:ef7eb2e8f9f7 26885 * | | |Set this bit high, the transceiver of port 1 will also be forced into the standby mode no matter what USB host controller operation is.
<> 144:ef7eb2e8f9f7 26886 * | | |0 = The connection between USB host controller and transceiver of port 1 is enabled.
<> 144:ef7eb2e8f9f7 26887 * | | |1 = The connection between USB host controller and transceiver of port 1 is disabled and the transceiver of port 1 will also be forced into the standby mode.
<> 144:ef7eb2e8f9f7 26888 * |[17] |DPRT2 |Port 2 Disable Control
<> 144:ef7eb2e8f9f7 26889 * | | |This bit controls if the connection between USB host controller and transceiver of port 2 is disabled.
<> 144:ef7eb2e8f9f7 26890 * | | |If the connection is disabled, the USB host controller will not recognize any event of USB bus.
<> 144:ef7eb2e8f9f7 26891 * | | |Set this bit high, the transceiver of port 2 will also be forced into the standby mode no matter what USB host controller operation is.
<> 144:ef7eb2e8f9f7 26892 * | | |0 = The connection between USB host controller and transceiver of port 2 is enabled.
<> 144:ef7eb2e8f9f7 26893 * | | |1 = The connection between USB host controller and transceiver of port 2 is disabled and the transceiver of port 2 will also be forced into the standby mode.
<> 144:ef7eb2e8f9f7 26894 */
<> 144:ef7eb2e8f9f7 26895 __IO uint32_t HcMiscControl;
<> 144:ef7eb2e8f9f7 26896
<> 144:ef7eb2e8f9f7 26897 } USBH_T;
<> 144:ef7eb2e8f9f7 26898
<> 144:ef7eb2e8f9f7 26899 /**
<> 144:ef7eb2e8f9f7 26900 @addtogroup USBH_CONST USBH Bit Field Definition
<> 144:ef7eb2e8f9f7 26901 Constant Definitions for USBH Controller
<> 144:ef7eb2e8f9f7 26902 @{ */
<> 144:ef7eb2e8f9f7 26903
<> 144:ef7eb2e8f9f7 26904 #define USBH_HcRevision_REV_Pos (0) /*!< USBH HcRevision: REV Position */
<> 144:ef7eb2e8f9f7 26905 #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) /*!< USBH HcRevision: REV Mask */
<> 144:ef7eb2e8f9f7 26906
<> 144:ef7eb2e8f9f7 26907 #define USBH_HcControl_CBSR_Pos (0) /*!< USBH HcControl: CBSR Position */
<> 144:ef7eb2e8f9f7 26908 #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) /*!< USBH HcControl: CBSR Mask */
<> 144:ef7eb2e8f9f7 26909
<> 144:ef7eb2e8f9f7 26910 #define USBH_HcControl_PLE_Pos (2) /*!< USBH HcControl: CBSR Position */
<> 144:ef7eb2e8f9f7 26911 #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) /*!< USBH HcControl: CBSR Mask */
<> 144:ef7eb2e8f9f7 26912
<> 144:ef7eb2e8f9f7 26913 #define USBH_HcControl_IE_Pos (3) /*!< USBH HcControl: IE Position */
<> 144:ef7eb2e8f9f7 26914 #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) /*!< USBH HcControl: IE Mask */
<> 144:ef7eb2e8f9f7 26915
<> 144:ef7eb2e8f9f7 26916 #define USBH_HcControl_CLE_Pos (4) /*!< USBH HcControl: CLE Position */
<> 144:ef7eb2e8f9f7 26917 #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) /*!< USBH HcControl: CLE Mask */
<> 144:ef7eb2e8f9f7 26918
<> 144:ef7eb2e8f9f7 26919 #define USBH_HcControl_BLE_Pos (5) /*!< USBH HcControl: BLE Position */
<> 144:ef7eb2e8f9f7 26920 #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) /*!< USBH HcControl: BLE Mask */
<> 144:ef7eb2e8f9f7 26921
<> 144:ef7eb2e8f9f7 26922 #define USBH_HcControl_HCFS_Pos (6) /*!< USBH HcControl: HCFS Position */
<> 144:ef7eb2e8f9f7 26923 #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) /*!< USBH HcControl: HCFS Mask */
<> 144:ef7eb2e8f9f7 26924
<> 144:ef7eb2e8f9f7 26925 #define USBH_HcCommandStatus_HCR_Pos (0) /*!< USBH HcCommandStatus: HCR Position */
<> 144:ef7eb2e8f9f7 26926 #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) /*!< USBH HcCommandStatus: HCR Mask */
<> 144:ef7eb2e8f9f7 26927
<> 144:ef7eb2e8f9f7 26928 #define USBH_HcCommandStatus_CLF_Pos (1) /*!< USBH HcCommandStatus: CLF Position */
<> 144:ef7eb2e8f9f7 26929 #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) /*!< USBH HcCommandStatus: CLF Mask */
<> 144:ef7eb2e8f9f7 26930
<> 144:ef7eb2e8f9f7 26931 #define USBH_HcCommandStatus_BLF_Pos (2) /*!< USBH HcCommandStatus: BLF Position */
<> 144:ef7eb2e8f9f7 26932 #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) /*!< USBH HcCommandStatus: BLF Mask */
<> 144:ef7eb2e8f9f7 26933
<> 144:ef7eb2e8f9f7 26934 #define USBH_HcCommandStatus_SOC_Pos (16) /*!< USBH HcCommandStatus: SOC Position */
<> 144:ef7eb2e8f9f7 26935 #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) /*!< USBH HcCommandStatus: SOC Mask */
<> 144:ef7eb2e8f9f7 26936
<> 144:ef7eb2e8f9f7 26937 #define USBH_HcInterruptStatus_SO_Pos (0) /*!< USBH HcInterruptStatus: SO Position */
<> 144:ef7eb2e8f9f7 26938 #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) /*!< USBH HcInterruptStatus: SO Mask */
<> 144:ef7eb2e8f9f7 26939
<> 144:ef7eb2e8f9f7 26940 #define USBH_HcInterruptStatus_WDH_Pos (1) /*!< USBH HcInterruptStatus: WDH Position */
<> 144:ef7eb2e8f9f7 26941 #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) /*!< USBH HcInterruptStatus: WDH Mask */
<> 144:ef7eb2e8f9f7 26942
<> 144:ef7eb2e8f9f7 26943 #define USBH_HcInterruptStatus_SF_Pos (2) /*!< USBH HcInterruptStatus: SF Position */
<> 144:ef7eb2e8f9f7 26944 #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) /*!< USBH HcInterruptStatus: SF Mask */
<> 144:ef7eb2e8f9f7 26945
<> 144:ef7eb2e8f9f7 26946 #define USBH_HcInterruptStatus_RD_Pos (3) /*!< USBH HcInterruptStatus: RD Position */
<> 144:ef7eb2e8f9f7 26947 #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) /*!< USBH HcInterruptStatus: RD Mask */
<> 144:ef7eb2e8f9f7 26948
<> 144:ef7eb2e8f9f7 26949 #define USBH_HcInterruptStatus_FNO_Pos (5) /*!< USBH HcInterruptStatus: FNO Position */
<> 144:ef7eb2e8f9f7 26950 #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) /*!< USBH HcInterruptStatus: FNO Mask */
<> 144:ef7eb2e8f9f7 26951
<> 144:ef7eb2e8f9f7 26952 #define USBH_HcInterruptStatus_RHSC_Pos (6) /*!< USBH HcInterruptStatus: RHSC Position */
<> 144:ef7eb2e8f9f7 26953 #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) /*!< USBH HcInterruptStatus: RHSC Mask */
<> 144:ef7eb2e8f9f7 26954
<> 144:ef7eb2e8f9f7 26955 #define USBH_HcInterruptEnable_SO_Pos (0) /*!< USBH HcInterruptEnable: SO Position */
<> 144:ef7eb2e8f9f7 26956 #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) /*!< USBH HcInterruptEnable: SO Mask */
<> 144:ef7eb2e8f9f7 26957
<> 144:ef7eb2e8f9f7 26958 #define USBH_HcInterruptEnable_WDH_Pos (1) /*!< USBH HcInterruptEnable: WDH Position */
<> 144:ef7eb2e8f9f7 26959 #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) /*!< USBH HcInterruptEnable: WDH Mask */
<> 144:ef7eb2e8f9f7 26960
<> 144:ef7eb2e8f9f7 26961 #define USBH_HcInterruptEnable_SF_Pos (2) /*!< USBH HcInterruptEnable: SF Position */
<> 144:ef7eb2e8f9f7 26962 #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) /*!< USBH HcInterruptEnable: SF Mask */
<> 144:ef7eb2e8f9f7 26963
<> 144:ef7eb2e8f9f7 26964 #define USBH_HcInterruptEnable_RD_Pos (3) /*!< USBH HcInterruptEnable: RD Position */
<> 144:ef7eb2e8f9f7 26965 #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) /*!< USBH HcInterruptEnable: RD Mask */
<> 144:ef7eb2e8f9f7 26966
<> 144:ef7eb2e8f9f7 26967 #define USBH_HcInterruptEnable_FNO_Pos (5) /*!< USBH HcInterruptEnable: FNO Position */
<> 144:ef7eb2e8f9f7 26968 #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) /*!< USBH HcInterruptEnable: FNO Mask */
<> 144:ef7eb2e8f9f7 26969
<> 144:ef7eb2e8f9f7 26970 #define USBH_HcInterruptEnable_RHSC_Pos (6) /*!< USBH HcInterruptEnable: RHSC Position */
<> 144:ef7eb2e8f9f7 26971 #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) /*!< USBH HcInterruptEnable: RHSC Mask */
<> 144:ef7eb2e8f9f7 26972
<> 144:ef7eb2e8f9f7 26973 #define USBH_HcInterruptEnable_MIE_Pos (31) /*!< USBH HcInterruptEnable: MIE Position */
<> 144:ef7eb2e8f9f7 26974 #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) /*!< USBH HcInterruptEnable: MIE Mask */
<> 144:ef7eb2e8f9f7 26975
<> 144:ef7eb2e8f9f7 26976 #define USBH_HcInterruptDisable_SO_Pos (0) /*!< USBH HcInterruptDisable: SO Position */
<> 144:ef7eb2e8f9f7 26977 #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) /*!< USBH HcInterruptDisable: SO Mask */
<> 144:ef7eb2e8f9f7 26978
<> 144:ef7eb2e8f9f7 26979 #define USBH_HcInterruptDisable_WDH_Pos (1) /*!< USBH HcInterruptDisable: WDH Position */
<> 144:ef7eb2e8f9f7 26980 #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) /*!< USBH HcInterruptDisable: WDH Mask */
<> 144:ef7eb2e8f9f7 26981
<> 144:ef7eb2e8f9f7 26982 #define USBH_HcInterruptDisable_SF_Pos (2) /*!< USBH HcInterruptDisable: SF Position */
<> 144:ef7eb2e8f9f7 26983 #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) /*!< USBH HcInterruptDisable: SF Mask */
<> 144:ef7eb2e8f9f7 26984
<> 144:ef7eb2e8f9f7 26985 #define USBH_HcInterruptDisable_RD_Pos (3) /*!< USBH HcInterruptDisable: RD Position */
<> 144:ef7eb2e8f9f7 26986 #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) /*!< USBH HcInterruptDisable: RD Mask */
<> 144:ef7eb2e8f9f7 26987
<> 144:ef7eb2e8f9f7 26988 #define USBH_HcInterruptDisable_FNO_Pos (5) /*!< USBH HcInterruptDisable: FNO Position */
<> 144:ef7eb2e8f9f7 26989 #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) /*!< USBH HcInterruptDisable: FNO Mask */
<> 144:ef7eb2e8f9f7 26990
<> 144:ef7eb2e8f9f7 26991 #define USBH_HcInterruptDisable_RHSC_Pos (6) /*!< USBH HcInterruptDisable: RHSC Position */
<> 144:ef7eb2e8f9f7 26992 #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) /*!< USBH HcInterruptDisable: RHSC Mask */
<> 144:ef7eb2e8f9f7 26993
<> 144:ef7eb2e8f9f7 26994 #define USBH_HcInterruptDisable_MIE_Pos (31) /*!< USBH HcInterruptDisable: MIE Position */
<> 144:ef7eb2e8f9f7 26995 #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) /*!< USBH HcInterruptDisable: MIE Mask */
<> 144:ef7eb2e8f9f7 26996
<> 144:ef7eb2e8f9f7 26997 #define USBH_HcHCCA_HCCA_Pos (8) /*!< USBH HcHCCA: HCCA Position */
<> 144:ef7eb2e8f9f7 26998 #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) /*!< USBH HcHCCA: HCCA Mask */
<> 144:ef7eb2e8f9f7 26999
<> 144:ef7eb2e8f9f7 27000 #define USBH_HcPeriodCurrentED_PCED_Pos (4) /*!< USBH HcPeriodCurrentED: PCED Position */
<> 144:ef7eb2e8f9f7 27001 #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) /*!< USBH HcPeriodCurrentED: PCED Mask */
<> 144:ef7eb2e8f9f7 27002
<> 144:ef7eb2e8f9f7 27003 #define USBH_HcControlHeadED_CHED_Pos (4) /*!< USBH HcControlHeadED: CHED Position */
<> 144:ef7eb2e8f9f7 27004 #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) /*!< USBH HcControlHeadED: CHED Mask */
<> 144:ef7eb2e8f9f7 27005
<> 144:ef7eb2e8f9f7 27006 #define USBH_HcControlCurrentED_CCED_Pos (4) /*!< USBH HcControlCurrentED: CCED Position */
<> 144:ef7eb2e8f9f7 27007 #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) /*!< USBH HcControlCurrentED: CCED Mask */
<> 144:ef7eb2e8f9f7 27008
<> 144:ef7eb2e8f9f7 27009 #define USBH_HcBulkHeadED_BHED_Pos (4) /*!< USBH HcBulkHeadED: BHED Position */
<> 144:ef7eb2e8f9f7 27010 #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) /*!< USBH HcBulkHeadED: BHED Mask */
<> 144:ef7eb2e8f9f7 27011
<> 144:ef7eb2e8f9f7 27012 #define USBH_HcBulkCurrentED_BCED_Pos (4) /*!< USBH HcBulkCurrentED: BCED Position */
<> 144:ef7eb2e8f9f7 27013 #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) /*!< USBH HcBulkCurrentED: BCED Mask */
<> 144:ef7eb2e8f9f7 27014
<> 144:ef7eb2e8f9f7 27015 #define USBH_HcDoneHead_DH_Pos (4) /*!< USBH HcDoneHead: DH Position */
<> 144:ef7eb2e8f9f7 27016 #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) /*!< USBH HcDoneHead: DH Mask */
<> 144:ef7eb2e8f9f7 27017
<> 144:ef7eb2e8f9f7 27018 #define USBH_HcFmInterval_FI_Pos (0) /*!< USBH HcFmInterval: FI Position */
<> 144:ef7eb2e8f9f7 27019 #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) /*!< USBH HcFmInterval: FI Mask */
<> 144:ef7eb2e8f9f7 27020
<> 144:ef7eb2e8f9f7 27021 #define USBH_HcFmInterval_FSMPS_Pos (16) /*!< USBH HcFmInterval: FSMPS Position */
<> 144:ef7eb2e8f9f7 27022 #define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) /*!< USBH HcFmInterval: FSMPS Mask */
<> 144:ef7eb2e8f9f7 27023
<> 144:ef7eb2e8f9f7 27024 #define USBH_HcFmInterval_FIT_Pos (31) /*!< USBH HcFmInterval: FIT Position */
<> 144:ef7eb2e8f9f7 27025 #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) /*!< USBH HcFmInterval: FIT Mask */
<> 144:ef7eb2e8f9f7 27026
<> 144:ef7eb2e8f9f7 27027 #define USBH_HcFmRemaining_FR_Pos (0) /*!< USBH HcFmRemaining: FR Position */
<> 144:ef7eb2e8f9f7 27028 #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) /*!< USBH HcFmRemaining: FR Mask */
<> 144:ef7eb2e8f9f7 27029
<> 144:ef7eb2e8f9f7 27030 #define USBH_HcFmRemaining_FRT_Pos (31) /*!< USBH HcFmRemaining: FRT Position */
<> 144:ef7eb2e8f9f7 27031 #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) /*!< USBH HcFmRemaining: FRT Mask */
<> 144:ef7eb2e8f9f7 27032
<> 144:ef7eb2e8f9f7 27033 #define USBH_HcFmNumber_FN_Pos (0) /*!< USBH HcFmNumber: FN Position */
<> 144:ef7eb2e8f9f7 27034 #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) /*!< USBH HcFmNumber: FN Mask */
<> 144:ef7eb2e8f9f7 27035
<> 144:ef7eb2e8f9f7 27036 #define USBH_HcPeriodicStart_PS_Pos (0) /*!< USBH HcPeriodicStart: PS Position */
<> 144:ef7eb2e8f9f7 27037 #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) /*!< USBH HcPeriodicStart: PS Mask */
<> 144:ef7eb2e8f9f7 27038
<> 144:ef7eb2e8f9f7 27039 #define USBH_HcLSThreshold_LST_Pos (0) /*!< USBH HcLSThreshold: LST Position */
<> 144:ef7eb2e8f9f7 27040 #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) /*!< USBH HcLSThreshold: LST Mask */
<> 144:ef7eb2e8f9f7 27041
<> 144:ef7eb2e8f9f7 27042 #define USBH_HcRhDescriptorA_NDP_Pos (0) /*!< USBH HcRhDescriptorA: NDP Position */
<> 144:ef7eb2e8f9f7 27043 #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) /*!< USBH HcRhDescriptorA: NDP Mask */
<> 144:ef7eb2e8f9f7 27044
<> 144:ef7eb2e8f9f7 27045 #define USBH_HcRhDescriptorA_PSM_Pos (8) /*!< USBH HcRhDescriptorA: PSM Position */
<> 144:ef7eb2e8f9f7 27046 #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) /*!< USBH HcRhDescriptorA: PSM Mask */
<> 144:ef7eb2e8f9f7 27047
<> 144:ef7eb2e8f9f7 27048 #define USBH_HcRhDescriptorA_NPS_Pos (9) /*!< USBH HcRhDescriptorA: NPS Position */
<> 144:ef7eb2e8f9f7 27049 #define USBH_HcRhDescriptorA_NPS_Msk (0x1ul << USBH_HcRhDescriptorA_NPS_Pos) /*!< USBH HcRhDescriptorA: NPS Mask */
<> 144:ef7eb2e8f9f7 27050
<> 144:ef7eb2e8f9f7 27051 #define USBH_HcRhDescriptorA_DT_Pos (10) /*!< USBH HcRhDescriptorA: DT Position */
<> 144:ef7eb2e8f9f7 27052 #define USBH_HcRhDescriptorA_DT_Msk (0x1ul << USBH_HcRhDescriptorA_DT_Pos) /*!< USBH HcRhDescriptorA: DT Mask */
<> 144:ef7eb2e8f9f7 27053
<> 144:ef7eb2e8f9f7 27054 #define USBH_HcRhDescriptorA_OCPM_Pos (11) /*!< USBH HcRhDescriptorA: OCPM Position */
<> 144:ef7eb2e8f9f7 27055 #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) /*!< USBH HcRhDescriptorA: OCPM Mask */
<> 144:ef7eb2e8f9f7 27056
<> 144:ef7eb2e8f9f7 27057 #define USBH_HcRhDescriptorA_NOCP_Pos (12) /*!< USBH HcRhDescriptorA: NOCP Position */
<> 144:ef7eb2e8f9f7 27058 #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) /*!< USBH HcRhDescriptorA: NOCP Mask */
<> 144:ef7eb2e8f9f7 27059
<> 144:ef7eb2e8f9f7 27060 #define USBH_HcRhDescriptorA_POTPGT_Pos (24) /*!< USBH HcRhDescriptorA: POTPGT Position */
<> 144:ef7eb2e8f9f7 27061 #define USBH_HcRhDescriptorA_POTPGT_Msk (0xfful << USBH_HcRhDescriptorA_POTPGT_Pos) /*!< USBH HcRhDescriptorA: POTPGT Mask */
<> 144:ef7eb2e8f9f7 27062
<> 144:ef7eb2e8f9f7 27063 #define USBH_HcRhDescriptorB_PPCM_Pos (16) /*!< USBH HcRhDescriptorB: PPCM Position */
<> 144:ef7eb2e8f9f7 27064 #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) /*!< USBH HcRhDescriptorB: PPCM Mask */
<> 144:ef7eb2e8f9f7 27065
<> 144:ef7eb2e8f9f7 27066 #define USBH_HcRhStatus_LPS_Pos (0) /*!< USBH HcRhStatus: LPS Position */
<> 144:ef7eb2e8f9f7 27067 #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) /*!< USBH HcRhStatus: LPS Mask */
<> 144:ef7eb2e8f9f7 27068
<> 144:ef7eb2e8f9f7 27069 #define USBH_HcRhStatus_OCI_Pos (1) /*!< USBH HcRhStatus: OCI Position */
<> 144:ef7eb2e8f9f7 27070 #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) /*!< USBH HcRhStatus: OCI Mask */
<> 144:ef7eb2e8f9f7 27071
<> 144:ef7eb2e8f9f7 27072 #define USBH_HcRhStatus_DRWE_Pos (15) /*!< USBH HcRhStatus: DRWE Position */
<> 144:ef7eb2e8f9f7 27073 #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) /*!< USBH HcRhStatus: DRWE Mask */
<> 144:ef7eb2e8f9f7 27074
<> 144:ef7eb2e8f9f7 27075 #define USBH_HcRhStatus_LPSC_Pos (16) /*!< USBH HcRhStatus: LPSC Position */
<> 144:ef7eb2e8f9f7 27076 #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) /*!< USBH HcRhStatus: LPSC Mask */
<> 144:ef7eb2e8f9f7 27077
<> 144:ef7eb2e8f9f7 27078 #define USBH_HcRhStatus_OCIC_Pos (17) /*!< USBH HcRhStatus: OCIC Position */
<> 144:ef7eb2e8f9f7 27079 #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) /*!< USBH HcRhStatus: OCIC Mask */
<> 144:ef7eb2e8f9f7 27080
<> 144:ef7eb2e8f9f7 27081 #define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH HcRhStatus: CRWE Position */
<> 144:ef7eb2e8f9f7 27082 #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH HcRhStatus: CRWE Mask */
<> 144:ef7eb2e8f9f7 27083
<> 144:ef7eb2e8f9f7 27084 #define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH HcRhPortStatus: CCS Position */
<> 144:ef7eb2e8f9f7 27085 #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH HcRhPortStatus: CCS Mask */
<> 144:ef7eb2e8f9f7 27086
<> 144:ef7eb2e8f9f7 27087 #define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH HcRhPortStatus: PES Position */
<> 144:ef7eb2e8f9f7 27088 #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH HcRhPortStatus: PES Mask */
<> 144:ef7eb2e8f9f7 27089
<> 144:ef7eb2e8f9f7 27090 #define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH HcRhPortStatus: PSS Position */
<> 144:ef7eb2e8f9f7 27091 #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH HcRhPortStatus: PSS Mask */
<> 144:ef7eb2e8f9f7 27092
<> 144:ef7eb2e8f9f7 27093 #define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH HcRhPortStatus: POCI Position */
<> 144:ef7eb2e8f9f7 27094 #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH HcRhPortStatus: POCI Mask */
<> 144:ef7eb2e8f9f7 27095
<> 144:ef7eb2e8f9f7 27096 #define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH HcRhPortStatus: PRS Position */
<> 144:ef7eb2e8f9f7 27097 #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH HcRhPortStatus: PRS Mask */
<> 144:ef7eb2e8f9f7 27098
<> 144:ef7eb2e8f9f7 27099 #define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH HcRhPortStatus: PPS Position */
<> 144:ef7eb2e8f9f7 27100 #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH HcRhPortStatus: PPS Mask */
<> 144:ef7eb2e8f9f7 27101
<> 144:ef7eb2e8f9f7 27102 #define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH HcRhPortStatus: LSDA Position */
<> 144:ef7eb2e8f9f7 27103 #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH HcRhPortStatus: LSDA Mask */
<> 144:ef7eb2e8f9f7 27104
<> 144:ef7eb2e8f9f7 27105 #define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH HcRhPortStatus: CSC Position */
<> 144:ef7eb2e8f9f7 27106 #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH HcRhPortStatus: CSC Mask */
<> 144:ef7eb2e8f9f7 27107
<> 144:ef7eb2e8f9f7 27108 #define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH HcRhPortStatus: PESC Position */
<> 144:ef7eb2e8f9f7 27109 #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH HcRhPortStatus: PESC Mask */
<> 144:ef7eb2e8f9f7 27110
<> 144:ef7eb2e8f9f7 27111 #define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH HcRhPortStatus: PSSC Position */
<> 144:ef7eb2e8f9f7 27112 #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH HcRhPortStatus: PSSC Mask */
<> 144:ef7eb2e8f9f7 27113
<> 144:ef7eb2e8f9f7 27114 #define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH HcRhPortStatus: OCIC Position */
<> 144:ef7eb2e8f9f7 27115 #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH HcRhPortStatus: OCIC Mask */
<> 144:ef7eb2e8f9f7 27116
<> 144:ef7eb2e8f9f7 27117 #define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH HcRhPortStatus: PRSC Position */
<> 144:ef7eb2e8f9f7 27118 #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH HcRhPortStatus: PRSC Mask */
<> 144:ef7eb2e8f9f7 27119
<> 144:ef7eb2e8f9f7 27120 #define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH HcPhyControl: STBYEN Position */
<> 144:ef7eb2e8f9f7 27121 #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH HcPhyControl: STBYEN Mask */
<> 144:ef7eb2e8f9f7 27122
<> 144:ef7eb2e8f9f7 27123 #define USBH_HcMiscControl_DBR16_Pos (0) /*!< USBH HcMiscControl: DBR16 Position */
<> 144:ef7eb2e8f9f7 27124 #define USBH_HcMiscControl_DBR16_Msk (0x1ul << USBH_HcMiscControl_DBR16_Pos) /*!< USBH HcMiscControl: DBR16 Mask */
<> 144:ef7eb2e8f9f7 27125
<> 144:ef7eb2e8f9f7 27126 #define USBH_HcMiscControl_ABORT_Pos (1) /*!< USBH HcMiscControl: ABORT Position */
<> 144:ef7eb2e8f9f7 27127 #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) /*!< USBH HcMiscControl: ABORT Mask */
<> 144:ef7eb2e8f9f7 27128
<> 144:ef7eb2e8f9f7 27129 #define USBH_HcMiscControl_OCAL_Pos (3) /*!< USBH HcMiscControl: OCAL Position */
<> 144:ef7eb2e8f9f7 27130 #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) /*!< USBH HcMiscControl: OCAL Mask */
<> 144:ef7eb2e8f9f7 27131
<> 144:ef7eb2e8f9f7 27132 #define USBH_HcMiscControl_PCAL_Pos (4) /*!< USBH HcMiscControl: PCAL Position */
<> 144:ef7eb2e8f9f7 27133 #define USBH_HcMiscControl_PCAL_Msk (0x1ul << USBH_HcMiscControl_PCAL_Pos) /*!< USBH HcMiscControl: PCAL Mask */
<> 144:ef7eb2e8f9f7 27134
<> 144:ef7eb2e8f9f7 27135 #define USBH_HcMiscControl_SIEPD_Pos (8) /*!< USBH HcMiscControl: SIEPD Position */
<> 144:ef7eb2e8f9f7 27136 #define USBH_HcMiscControl_SIEPD_Msk (0x1ul << USBH_HcMiscControl_SIEPD_Pos) /*!< USBH HcMiscControl: SIEPD Mask */
<> 144:ef7eb2e8f9f7 27137
<> 144:ef7eb2e8f9f7 27138 #define USBH_HcMiscControl_DPRT1_Pos (16) /*!< USBH HcMiscControl: DPRT1 Position */
<> 144:ef7eb2e8f9f7 27139 #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) /*!< USBH HcMiscControl: DPRT1 Mask */
<> 144:ef7eb2e8f9f7 27140
<> 144:ef7eb2e8f9f7 27141 #define USBH_HcMiscControl_DPRT2_Pos (17) /*!< USBH HcMiscControl: DPRT2 Position */
<> 144:ef7eb2e8f9f7 27142 #define USBH_HcMiscControl_DPRT2_Msk (0x1ul << USBH_HcMiscControl_DPRT2_Pos) /*!< USBH HcMiscControl: DPRT2 Mask */
<> 144:ef7eb2e8f9f7 27143
<> 144:ef7eb2e8f9f7 27144 /**@}*/ /* USBH_CONST */
<> 144:ef7eb2e8f9f7 27145 /**@}*/ /* end of USBH register group */
<> 144:ef7eb2e8f9f7 27146
<> 144:ef7eb2e8f9f7 27147
<> 144:ef7eb2e8f9f7 27148 /*---------------------- USB Device Controller -------------------------*/
<> 144:ef7eb2e8f9f7 27149 /**
<> 144:ef7eb2e8f9f7 27150 @addtogroup USBD USB Device Controller(USBD)
<> 144:ef7eb2e8f9f7 27151 Memory Mapped Structure for USBD Controller
<> 144:ef7eb2e8f9f7 27152 @{ */
<> 144:ef7eb2e8f9f7 27153
<> 144:ef7eb2e8f9f7 27154 typedef struct {
<> 144:ef7eb2e8f9f7 27155
<> 144:ef7eb2e8f9f7 27156
<> 144:ef7eb2e8f9f7 27157 /**
<> 144:ef7eb2e8f9f7 27158 * GINTSTS
<> 144:ef7eb2e8f9f7 27159 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27160 * Offset: 0x00 Interrupt Status Low Register
<> 144:ef7eb2e8f9f7 27161 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27162 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27163 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27164 * |[0] |USBIF |USB Interrupt
<> 144:ef7eb2e8f9f7 27165 * | | |This bit conveys the interrupt status for USB specific events endpoint.
<> 144:ef7eb2e8f9f7 27166 * | | |When set, USB interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27167 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27168 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27169 * |[1] |CEPIF |Control Endpoint Interrupt
<> 144:ef7eb2e8f9f7 27170 * | | |This bit conveys the interrupt status for control endpoint.
<> 144:ef7eb2e8f9f7 27171 * | | |When set, Control-ep's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27172 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27173 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27174 * |[2] |EPAIF |Endpoints A Interrupt
<> 144:ef7eb2e8f9f7 27175 * | | |When set, the corresponding Endpoint A's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27176 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27177 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27178 * |[3] |EPBIF |Endpoints B Interrupt
<> 144:ef7eb2e8f9f7 27179 * | | |When set, the corresponding Endpoint B's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27180 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27181 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27182 * |[4] |EPCIF |Endpoints C Interrupt
<> 144:ef7eb2e8f9f7 27183 * | | |When set, the corresponding Endpoint C's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27184 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27185 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27186 * |[5] |EPDIF |Endpoints D Interrupt
<> 144:ef7eb2e8f9f7 27187 * | | |When set, the corresponding Endpoint D's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27188 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27189 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27190 * |[6] |EPEIF |Endpoints E Interrupt
<> 144:ef7eb2e8f9f7 27191 * | | |When set, the corresponding Endpoint E's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27192 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27193 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27194 * |[7] |EPFIF |Endpoints F Interrupt
<> 144:ef7eb2e8f9f7 27195 * | | |When set, the corresponding Endpoint F's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27196 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27197 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27198 * |[8] |EPGIF |Endpoints G Interrupt
<> 144:ef7eb2e8f9f7 27199 * | | |When set, the corresponding Endpoint G's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27200 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27201 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27202 * |[9] |EPHIF |Endpoints H Interrupt
<> 144:ef7eb2e8f9f7 27203 * | | |When set, the corresponding Endpoint H's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27204 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27205 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27206 * |[10] |EPIIF |Endpoints I Interrupt
<> 144:ef7eb2e8f9f7 27207 * | | |When set, the corresponding Endpoint I's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27208 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27209 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27210 * |[11] |EPJIF |Endpoints J Interrupt
<> 144:ef7eb2e8f9f7 27211 * | | |When set, the corresponding Endpoint J's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27212 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27213 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27214 * |[12] |EPKIF |Endpoints K Interrupt
<> 144:ef7eb2e8f9f7 27215 * | | |When set, the corresponding Endpoint K's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27216 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27217 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27218 * |[13] |EPLIF |Endpoints L Interrupt
<> 144:ef7eb2e8f9f7 27219 * | | |When set, the corresponding Endpoint L's interrupt status register should be read to determine the cause of the interrupt.
<> 144:ef7eb2e8f9f7 27220 * | | |0 = No interrupt event occurred.
<> 144:ef7eb2e8f9f7 27221 * | | |1 = The related interrupt event is occurred.
<> 144:ef7eb2e8f9f7 27222 */
<> 144:ef7eb2e8f9f7 27223 __I uint32_t GINTSTS;
<> 144:ef7eb2e8f9f7 27224 uint32_t RESERVE0[1];
<> 144:ef7eb2e8f9f7 27225
<> 144:ef7eb2e8f9f7 27226
<> 144:ef7eb2e8f9f7 27227 /**
<> 144:ef7eb2e8f9f7 27228 * GINTEN
<> 144:ef7eb2e8f9f7 27229 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27230 * Offset: 0x08 Interrupt Enable Low Register
<> 144:ef7eb2e8f9f7 27231 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27232 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27233 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27234 * |[0] |USBIE |USB Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27235 * | | |When set, this bit enables a local interrupt to be generated when a USB event occurs on the bus.
<> 144:ef7eb2e8f9f7 27236 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27237 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27238 * |[1] |CEPIE |Control Endpoint Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27239 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the control endpoint.
<> 144:ef7eb2e8f9f7 27240 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27241 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27242 * |[2] |EPAIE |Interrupt Enable Control For Endpoint A
<> 144:ef7eb2e8f9f7 27243 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint A.
<> 144:ef7eb2e8f9f7 27244 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27245 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27246 * |[3] |EPBIE |Interrupt Enable Control For Endpoint B
<> 144:ef7eb2e8f9f7 27247 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint B
<> 144:ef7eb2e8f9f7 27248 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27249 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27250 * |[4] |EPCIE |Interrupt Enable Control For Endpoint C
<> 144:ef7eb2e8f9f7 27251 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint C
<> 144:ef7eb2e8f9f7 27252 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27253 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27254 * |[5] |EPDIE |Interrupt Enable Control For Endpoint D
<> 144:ef7eb2e8f9f7 27255 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint D
<> 144:ef7eb2e8f9f7 27256 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27257 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27258 * |[6] |EPEIE |Interrupt Enable Control For Endpoint E
<> 144:ef7eb2e8f9f7 27259 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint E
<> 144:ef7eb2e8f9f7 27260 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27261 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27262 * |[7] |EPFIE |Interrupt Enable Control For Endpoint F
<> 144:ef7eb2e8f9f7 27263 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint F
<> 144:ef7eb2e8f9f7 27264 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27265 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27266 * |[8] |EPGIE |Interrupt Enable Control For Endpoint G
<> 144:ef7eb2e8f9f7 27267 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint G
<> 144:ef7eb2e8f9f7 27268 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27269 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27270 * |[9] |EPHIE |Interrupt Enable Control For Endpoint H
<> 144:ef7eb2e8f9f7 27271 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint H
<> 144:ef7eb2e8f9f7 27272 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27273 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27274 * |[10] |EPIIE |Interrupt Enable Control For Endpoint I
<> 144:ef7eb2e8f9f7 27275 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint I
<> 144:ef7eb2e8f9f7 27276 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27277 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27278 * |[11] |EPJIE |Interrupt Enable Control For Endpoint J
<> 144:ef7eb2e8f9f7 27279 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint J
<> 144:ef7eb2e8f9f7 27280 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27281 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27282 * |[12] |EPKIE |Interrupt Enable Control For Endpoint K
<> 144:ef7eb2e8f9f7 27283 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint K
<> 144:ef7eb2e8f9f7 27284 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27285 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27286 * |[13] |EPLIE |Interrupt Enable Control For Endpoint L
<> 144:ef7eb2e8f9f7 27287 * | | |When set, this bit enables a local interrupt to be generated when an interrupt is pending for the endpoint L
<> 144:ef7eb2e8f9f7 27288 * | | |0 = The related interrupt Disabled.
<> 144:ef7eb2e8f9f7 27289 * | | |1 = The related interrupt Enabled.
<> 144:ef7eb2e8f9f7 27290 */
<> 144:ef7eb2e8f9f7 27291 __IO uint32_t GINTEN;
<> 144:ef7eb2e8f9f7 27292 uint32_t RESERVE1[1];
<> 144:ef7eb2e8f9f7 27293
<> 144:ef7eb2e8f9f7 27294
<> 144:ef7eb2e8f9f7 27295 /**
<> 144:ef7eb2e8f9f7 27296 * BUSINTSTS
<> 144:ef7eb2e8f9f7 27297 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27298 * Offset: 0x10 USB Bus Interrupt Status Register
<> 144:ef7eb2e8f9f7 27299 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27300 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27301 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27302 * |[0] |SOFIF |SOF Receive Control
<> 144:ef7eb2e8f9f7 27303 * | | |This bit indicates when a start-of-frame packet has been received.
<> 144:ef7eb2e8f9f7 27304 * | | |0 = No start-of-frame packet has been received.
<> 144:ef7eb2e8f9f7 27305 * | | |1 = Start-of-frame packet has been received.
<> 144:ef7eb2e8f9f7 27306 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27307 * |[1] |RSTIF |Reset Status
<> 144:ef7eb2e8f9f7 27308 * | | |When set, this bit indicates that either the USB root port reset is end.
<> 144:ef7eb2e8f9f7 27309 * | | |0 = No USB root port reset is end.
<> 144:ef7eb2e8f9f7 27310 * | | |1 = USB root port reset is end.
<> 144:ef7eb2e8f9f7 27311 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27312 * |[2] |RESUMEIF |Resume
<> 144:ef7eb2e8f9f7 27313 * | | |When set, this bit indicates that a device resume has occurred.
<> 144:ef7eb2e8f9f7 27314 * | | |0 = No device resume has occurred.
<> 144:ef7eb2e8f9f7 27315 * | | |1 = Device resume has occurred.
<> 144:ef7eb2e8f9f7 27316 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27317 * |[3] |SUSPENDIF |Suspend Request
<> 144:ef7eb2e8f9f7 27318 * | | |This bit is set as default and it has to be cleared by writing '1' before the USB reset.
<> 144:ef7eb2e8f9f7 27319 * | | |This bit is also set when a USB Suspend request is detected from the host.
<> 144:ef7eb2e8f9f7 27320 * | | |0 = No USB Suspend request is detected from the host.
<> 144:ef7eb2e8f9f7 27321 * | | |1= USB Suspend request is detected from the host.
<> 144:ef7eb2e8f9f7 27322 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27323 * |[4] |HISPDIF |High-Speed Settle
<> 144:ef7eb2e8f9f7 27324 * | | |0 = No valid high-speed reset protocol is detected.
<> 144:ef7eb2e8f9f7 27325 * | | |1 = Valid high-speed reset protocol is over and the device has settled in high-speed.
<> 144:ef7eb2e8f9f7 27326 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27327 * |[5] |DMADONEIF |DMA Completion Interrupt
<> 144:ef7eb2e8f9f7 27328 * | | |0 = No DMA transfer over.
<> 144:ef7eb2e8f9f7 27329 * | | |1 = DMA transfer is over.
<> 144:ef7eb2e8f9f7 27330 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27331 * |[6] |PHYCLKVLDIF|Usable Clock Interrupt
<> 144:ef7eb2e8f9f7 27332 * | | |0 = Usable clock is not available.
<> 144:ef7eb2e8f9f7 27333 * | | |1 = Usable clock is available from the transceiver.
<> 144:ef7eb2e8f9f7 27334 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27335 * |[8] |VBUSDETIF |VBUS Detection Interrupt Status
<> 144:ef7eb2e8f9f7 27336 * | | |0 = No VBUS is plug-in.
<> 144:ef7eb2e8f9f7 27337 * | | |1 = VBUS is plug-in.
<> 144:ef7eb2e8f9f7 27338 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27339 */
<> 144:ef7eb2e8f9f7 27340 __IO uint32_t BUSINTSTS;
<> 144:ef7eb2e8f9f7 27341
<> 144:ef7eb2e8f9f7 27342 /**
<> 144:ef7eb2e8f9f7 27343 * BUSINTEN
<> 144:ef7eb2e8f9f7 27344 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27345 * Offset: 0x14 USB Bus Interrupt Enable Register
<> 144:ef7eb2e8f9f7 27346 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27347 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27348 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27349 * |[0] |SOFIEN |SOF Interrupt
<> 144:ef7eb2e8f9f7 27350 * | | |This bit enables the SOF interrupt.
<> 144:ef7eb2e8f9f7 27351 * | | |0 = SOF interrupt Disabled.
<> 144:ef7eb2e8f9f7 27352 * | | |1 = SOF interrupt Enabled.
<> 144:ef7eb2e8f9f7 27353 * |[1] |RSTIEN |Reset Status
<> 144:ef7eb2e8f9f7 27354 * | | |This bit enables the USB-Reset interrupt.
<> 144:ef7eb2e8f9f7 27355 * | | |0 = USB-Reset interrupt Disabled.
<> 144:ef7eb2e8f9f7 27356 * | | |1 = USB-Reset interrupt Enabled.
<> 144:ef7eb2e8f9f7 27357 * |[2] |RESUMEIEN |Resume
<> 144:ef7eb2e8f9f7 27358 * | | |This bit enables the Resume interrupt.
<> 144:ef7eb2e8f9f7 27359 * | | |0 = Resume interrupt Disabled.
<> 144:ef7eb2e8f9f7 27360 * | | |1 = Resume interrupt Enabled.
<> 144:ef7eb2e8f9f7 27361 * |[3] |SUSPENDIEN|Suspend Request
<> 144:ef7eb2e8f9f7 27362 * | | |This bit enables the Suspend interrupt.
<> 144:ef7eb2e8f9f7 27363 * | | |0 = Suspend interrupt Disabled.
<> 144:ef7eb2e8f9f7 27364 * | | |1 = Suspend interrupt Enabled.
<> 144:ef7eb2e8f9f7 27365 * |[4] |HISPDIEN |High-Speed Settle
<> 144:ef7eb2e8f9f7 27366 * | | |This bit enables the high-speed settle interrupt.
<> 144:ef7eb2e8f9f7 27367 * | | |0 = High-speed settle interrupt Disabled.
<> 144:ef7eb2e8f9f7 27368 * | | |1 = High-speed settle interrupt Enabled.
<> 144:ef7eb2e8f9f7 27369 * |[5] |DMADONEIEN|DMA Completion Interrupt
<> 144:ef7eb2e8f9f7 27370 * | | |This bit enables the DMA completion interrupt
<> 144:ef7eb2e8f9f7 27371 * | | |0 = DMA completion interrupt Disabled.
<> 144:ef7eb2e8f9f7 27372 * | | |1 = DMA completion interrupt Enabled.
<> 144:ef7eb2e8f9f7 27373 * |[6] |PHYCLKVLDIEN|Usable Clock Interrupt
<> 144:ef7eb2e8f9f7 27374 * | | |This bit enables the usable clock interrupt.
<> 144:ef7eb2e8f9f7 27375 * | | |0 = Usable clock interrupt Disabled.
<> 144:ef7eb2e8f9f7 27376 * | | |1 = Usable clock interrupt Enabled.
<> 144:ef7eb2e8f9f7 27377 * |[8] |VBUSDETIEN|VBUS Detection Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27378 * | | |This bit enables the VBUS floating detection interrupt.
<> 144:ef7eb2e8f9f7 27379 * | | |0 = VBUS floating detection interrupt Disabled.
<> 144:ef7eb2e8f9f7 27380 * | | |1 = VBUS floating detection interrupt Enabled.
<> 144:ef7eb2e8f9f7 27381 */
<> 144:ef7eb2e8f9f7 27382 __IO uint32_t BUSINTEN;
<> 144:ef7eb2e8f9f7 27383
<> 144:ef7eb2e8f9f7 27384 /**
<> 144:ef7eb2e8f9f7 27385 * OPER
<> 144:ef7eb2e8f9f7 27386 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27387 * Offset: 0x18 USB Operational Register
<> 144:ef7eb2e8f9f7 27388 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27389 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27390 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27391 * |[0] |RESUMEEN |Generate Resume
<> 144:ef7eb2e8f9f7 27392 * | | |0 = No Resume sequence to be initiated to the host.
<> 144:ef7eb2e8f9f7 27393 * | | |1 = A Resume sequence to be initiated to the host if device remote wakeup is enabled.
<> 144:ef7eb2e8f9f7 27394 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 27395 * |[1] |HISPDEN |USB High-Speed
<> 144:ef7eb2e8f9f7 27396 * | | |0 = The USB device controller to suppress the chirp-sequence during reset protocol, thereby allowing the USB device controller to settle in full-speed, even though it is connected to a USB2.0 Host.
<> 144:ef7eb2e8f9f7 27397 * | | |1 = The USB device controller to initiate a chirp-sequence during reset protocol.
<> 144:ef7eb2e8f9f7 27398 * |[2] |CURSPD |USB Current Speed
<> 144:ef7eb2e8f9f7 27399 * | | |0 = The device has settled in Full Speed.
<> 144:ef7eb2e8f9f7 27400 * | | |1 = The USB device controller has settled in High-speed.
<> 144:ef7eb2e8f9f7 27401 */
<> 144:ef7eb2e8f9f7 27402 __IO uint32_t OPER;
<> 144:ef7eb2e8f9f7 27403
<> 144:ef7eb2e8f9f7 27404 /**
<> 144:ef7eb2e8f9f7 27405 * FRAMECNT
<> 144:ef7eb2e8f9f7 27406 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27407 * Offset: 0x1C USB Frame Count Register
<> 144:ef7eb2e8f9f7 27408 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27409 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27410 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27411 * |[0:2] |MFRAMECNT |Micro-Frame Counter
<> 144:ef7eb2e8f9f7 27412 * | | |This field contains the micro-frame number for the frame number in the frame counter field.
<> 144:ef7eb2e8f9f7 27413 * |[3:13] |FRAMECNT |Frame Counter
<> 144:ef7eb2e8f9f7 27414 * | | |This field contains the frame count from the most recent start-of-frame packet.
<> 144:ef7eb2e8f9f7 27415 */
<> 144:ef7eb2e8f9f7 27416 __I uint32_t FRAMECNT;
<> 144:ef7eb2e8f9f7 27417
<> 144:ef7eb2e8f9f7 27418 /**
<> 144:ef7eb2e8f9f7 27419 * FADDR
<> 144:ef7eb2e8f9f7 27420 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27421 * Offset: 0x20 USB Function Address Register
<> 144:ef7eb2e8f9f7 27422 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27423 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27424 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27425 * |[0:6] |FADDR |USB Function Address
<> 144:ef7eb2e8f9f7 27426 * | | |This field contains the current USB address of the device.
<> 144:ef7eb2e8f9f7 27427 * | | |This field is cleared when a root port reset is detected.
<> 144:ef7eb2e8f9f7 27428 */
<> 144:ef7eb2e8f9f7 27429 __IO uint32_t FADDR;
<> 144:ef7eb2e8f9f7 27430
<> 144:ef7eb2e8f9f7 27431 /**
<> 144:ef7eb2e8f9f7 27432 * TEST
<> 144:ef7eb2e8f9f7 27433 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27434 * Offset: 0x24 USB Test Mode Register
<> 144:ef7eb2e8f9f7 27435 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27436 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27437 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27438 * |[0:2] |TESTMODE |Test Mode Selection
<> 144:ef7eb2e8f9f7 27439 * | | |000 = Normal Operation.
<> 144:ef7eb2e8f9f7 27440 * | | |001 = Test_J.
<> 144:ef7eb2e8f9f7 27441 * | | |010 = Test_K.
<> 144:ef7eb2e8f9f7 27442 * | | |011 = Test_SE0_NAK.
<> 144:ef7eb2e8f9f7 27443 * | | |100 = Test_Packet.
<> 144:ef7eb2e8f9f7 27444 * | | |101 = Test_Force_Enable.
<> 144:ef7eb2e8f9f7 27445 * | | |110 = Reserved.
<> 144:ef7eb2e8f9f7 27446 * | | |111 = Reserved.
<> 144:ef7eb2e8f9f7 27447 * | | |Note: This field is cleared when root port reset is detected.
<> 144:ef7eb2e8f9f7 27448 */
<> 144:ef7eb2e8f9f7 27449 __IO uint32_t TEST;
<> 144:ef7eb2e8f9f7 27450
<> 144:ef7eb2e8f9f7 27451 union {
<> 144:ef7eb2e8f9f7 27452
<> 144:ef7eb2e8f9f7 27453 /**
<> 144:ef7eb2e8f9f7 27454 * CEPDAT
<> 144:ef7eb2e8f9f7 27455 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27456 * Offset: 0x28 Control-Endpoint Data Buffer
<> 144:ef7eb2e8f9f7 27457 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27458 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27459 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27460 * |[0:31] |DAT |Control-Endpoint Data Buffer
<> 144:ef7eb2e8f9f7 27461 * | | |Control endpoint data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 27462 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 27463 */
<> 144:ef7eb2e8f9f7 27464 __IO uint32_t CEPDAT;
<> 144:ef7eb2e8f9f7 27465 /**
<> 144:ef7eb2e8f9f7 27466 * CEPDAT_BYTE
<> 144:ef7eb2e8f9f7 27467 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27468 * Offset: 0x28 Control-Endpoint Data Buffer for Byte Access
<> 144:ef7eb2e8f9f7 27469 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27470 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27471 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27472 * |[0:7] |DAT |Control-Endpoint Data Buffer
<> 144:ef7eb2e8f9f7 27473 * | | |Control endpoint data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 27474 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 27475 */
<> 144:ef7eb2e8f9f7 27476 __IO uint8_t CEPDAT_BYTE;
<> 144:ef7eb2e8f9f7 27477
<> 144:ef7eb2e8f9f7 27478 };///< Define Control-Endpoint Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 27479
<> 144:ef7eb2e8f9f7 27480 /**
<> 144:ef7eb2e8f9f7 27481 * CEPCTL
<> 144:ef7eb2e8f9f7 27482 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27483 * Offset: 0x2C Control-Endpoint Control and Status
<> 144:ef7eb2e8f9f7 27484 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27485 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27486 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27487 * |[0] |NAKCLR |No Acknowledge Control
<> 144:ef7eb2e8f9f7 27488 * | | |This bit plays a crucial role in any control transfer.
<> 144:ef7eb2e8f9f7 27489 * | | |0 = The bit is being cleared by the local CPU by writing zero, the USB device controller will be responding with NAKs for the subsequent status phase.
<> 144:ef7eb2e8f9f7 27490 * | | |This mechanism holds the host from moving to the next request, until the local CPU is also ready to process the next request.
<> 144:ef7eb2e8f9f7 27491 * | | |1 = This bit is set to one by the USB device controller, whenever a setup token is received.
<> 144:ef7eb2e8f9f7 27492 * | | |The local CPU can take its own time to finish off any house-keeping work based on the request and then clear this bit.
<> 144:ef7eb2e8f9f7 27493 * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
<> 144:ef7eb2e8f9f7 27494 * |[1] |STALLEN |Stall Enable Control
<> 144:ef7eb2e8f9f7 27495 * | | |When this stall bit is set, the control endpoint sends a stall handshake in response to any in or out token thereafter.
<> 144:ef7eb2e8f9f7 27496 * | | |This is typically used for response to invalid/unsupported requests.
<> 144:ef7eb2e8f9f7 27497 * | | |When this bit is being set the NAK clear bit has to be cleared at the same time since the NAK clear bit has highest priority than STALL.
<> 144:ef7eb2e8f9f7 27498 * | | |It is automatically cleared on receipt of a next setup-token.
<> 144:ef7eb2e8f9f7 27499 * | | |So, the local CPU need not write again to clear this bit.
<> 144:ef7eb2e8f9f7 27500 * | | |0 = No sends a stall handshake in response to any in or out token thereafter.
<> 144:ef7eb2e8f9f7 27501 * | | |1 = The control endpoint sends a stall handshake in response to any in or out token thereafter.
<> 144:ef7eb2e8f9f7 27502 * | | |Note: Only when CPU writes data[1:0] is 2'b10 or 2'b00, this bit can be updated.
<> 144:ef7eb2e8f9f7 27503 * |[2] |ZEROLEN |Zero Packet Length
<> 144:ef7eb2e8f9f7 27504 * | | |This bit is valid for Auto Validation mode only.
<> 144:ef7eb2e8f9f7 27505 * | | |0 = No zero length packet to the host during Data stage to an IN token.
<> 144:ef7eb2e8f9f7 27506 * | | |1 = USB device controller can send a zero length packet to the host during Data stage to an IN token.
<> 144:ef7eb2e8f9f7 27507 * | | |This bit gets cleared once the zero length data packet is sent.
<> 144:ef7eb2e8f9f7 27508 * | | |So, the local CPU need not write again to clear this bit.
<> 144:ef7eb2e8f9f7 27509 * |[3] |FLUSH |CEP-FLUSH Bit
<> 144:ef7eb2e8f9f7 27510 * | | |0 = No the packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
<> 144:ef7eb2e8f9f7 27511 * | | |1 = The packet buffer and its corresponding USBD_CEPDATCNT register to be cleared.
<> 144:ef7eb2e8f9f7 27512 * | | |This bit is self-cleaning.
<> 144:ef7eb2e8f9f7 27513 */
<> 144:ef7eb2e8f9f7 27514 __IO uint32_t CEPCTL;
<> 144:ef7eb2e8f9f7 27515
<> 144:ef7eb2e8f9f7 27516 /**
<> 144:ef7eb2e8f9f7 27517 * CEPINTEN
<> 144:ef7eb2e8f9f7 27518 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27519 * Offset: 0x30 Control-Endpoint Interrupt Enable
<> 144:ef7eb2e8f9f7 27520 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27521 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27522 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27523 * |[0] |SETUPTKIEN|Setup Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27524 * | | |0 = The SETUP token interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27525 * | | |1 = The SETUP token interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27526 * |[1] |SETUPPKIEN|Setup Packet Interrupt
<> 144:ef7eb2e8f9f7 27527 * | | |0 = The SETUP packet interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27528 * | | |1 = The SETUP packet interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27529 * |[2] |OUTTKIEN |Out Token Interrupt
<> 144:ef7eb2e8f9f7 27530 * | | |0 = The OUT token interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27531 * | | |1 = The OUT token interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27532 * |[3] |INTKIEN |In Token Interrupt
<> 144:ef7eb2e8f9f7 27533 * | | |0 = The IN token interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27534 * | | |1 = The IN token interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27535 * |[4] |PINGIEN |Ping Token Interrupt
<> 144:ef7eb2e8f9f7 27536 * | | |0 = The ping token interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27537 * | | |1 = The ping token interrupt Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27538 * |[5] |TXPKIEN |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 27539 * | | |0 = The data packet transmitted interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27540 * | | |1 = The data packet transmitted interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27541 * |[6] |RXPKIEN |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 27542 * | | |0 = The data received interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27543 * | | |1 = The data received interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27544 * |[7] |NAKIEN |NAK Sent Interrupt
<> 144:ef7eb2e8f9f7 27545 * | | |0 = The NAK sent interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27546 * | | |1 = The NAK sent interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27547 * |[8] |STALLIEN |STALL Sent Interrupt
<> 144:ef7eb2e8f9f7 27548 * | | |0 = The STALL sent interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27549 * | | |1 = The STALL sent interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27550 * |[9] |ERRIEN |USB Error Interrupt
<> 144:ef7eb2e8f9f7 27551 * | | |0 = The USB Error interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27552 * | | |1 = The USB Error interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27553 * |[10] |STSDONEIEN|Status Completion Interrupt
<> 144:ef7eb2e8f9f7 27554 * | | |0 = The Status Completion interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27555 * | | |1 = The Status Completion interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27556 * |[11] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 27557 * | | |0 = The buffer full interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27558 * | | |1 = The buffer full interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27559 * |[12] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 27560 * | | |0 = The buffer empty interrupt in Control Endpoint Disabled.
<> 144:ef7eb2e8f9f7 27561 * | | |1= The buffer empty interrupt in Control Endpoint Enabled.
<> 144:ef7eb2e8f9f7 27562 */
<> 144:ef7eb2e8f9f7 27563 __IO uint32_t CEPINTEN;
<> 144:ef7eb2e8f9f7 27564
<> 144:ef7eb2e8f9f7 27565 /**
<> 144:ef7eb2e8f9f7 27566 * CEPINTSTS
<> 144:ef7eb2e8f9f7 27567 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27568 * Offset: 0x34 Control-Endpoint Interrupt Status
<> 144:ef7eb2e8f9f7 27569 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27570 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27571 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27572 * |[0] |SETUPTKIF |Setup Token Interrupt
<> 144:ef7eb2e8f9f7 27573 * | | |0 = Not a Setup token is received.
<> 144:ef7eb2e8f9f7 27574 * | | |1 = A Setup token is received. Writing 1 clears this status bit
<> 144:ef7eb2e8f9f7 27575 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27576 * |[1] |SETUPPKIF |Setup Packet Interrupt
<> 144:ef7eb2e8f9f7 27577 * | | |This bit must be cleared (by writing 1) before the next setup packet can be received.
<> 144:ef7eb2e8f9f7 27578 * | | |If the bit is not cleared, then the successive setup packets will be overwritten in the setup packet buffer.
<> 144:ef7eb2e8f9f7 27579 * | | |0 = Not a Setup packet has been received from the host.
<> 144:ef7eb2e8f9f7 27580 * | | |1 = A Setup packet has been received from the host.
<> 144:ef7eb2e8f9f7 27581 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27582 * |[2] |OUTTKIF |Out Token Interrupt
<> 144:ef7eb2e8f9f7 27583 * | | |0 = The control-endpoint does not received an OUT token from the host.
<> 144:ef7eb2e8f9f7 27584 * | | |1 = The control-endpoint receives an OUT token from the host.
<> 144:ef7eb2e8f9f7 27585 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27586 * |[3] |INTKIF |In Token Interrupt
<> 144:ef7eb2e8f9f7 27587 * | | |0 = The control-endpoint does not received an IN token from the host.
<> 144:ef7eb2e8f9f7 27588 * | | |1 = The control-endpoint receives an IN token from the host.
<> 144:ef7eb2e8f9f7 27589 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27590 * |[4] |PINGIF |Ping Token Interrupt
<> 144:ef7eb2e8f9f7 27591 * | | |0 = The control-endpoint does not received a ping token from the host.
<> 144:ef7eb2e8f9f7 27592 * | | |1 = The control-endpoint receives a ping token from the host.
<> 144:ef7eb2e8f9f7 27593 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27594 * |[5] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 27595 * | | |0 = Not a data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
<> 144:ef7eb2e8f9f7 27596 * | | |1 = A data packet is successfully transmitted to the host in response to an IN-token and an ACK-token is received for the same.
<> 144:ef7eb2e8f9f7 27597 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27598 * |[6] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 27599 * | | |0 = Not a data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
<> 144:ef7eb2e8f9f7 27600 * | | |1 = A data packet is successfully received from the host for an OUT-token and an ACK is sent to the host.
<> 144:ef7eb2e8f9f7 27601 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27602 * |[7] |NAKIF |NAK Sent Interrupt
<> 144:ef7eb2e8f9f7 27603 * | | |0 = Not a NAK-token is sent in response to an IN/OUT token.
<> 144:ef7eb2e8f9f7 27604 * | | |1 = A NAK-token is sent in response to an IN/OUT token.
<> 144:ef7eb2e8f9f7 27605 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27606 * |[8] |STALLIF |STALL Sent Interrupt
<> 144:ef7eb2e8f9f7 27607 * | | |0 = Not a stall-token is sent in response to an IN/OUT token.
<> 144:ef7eb2e8f9f7 27608 * | | |1 = A stall-token is sent in response to an IN/OUT token.
<> 144:ef7eb2e8f9f7 27609 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27610 * |[9] |ERRIF |USB Error Interrupt
<> 144:ef7eb2e8f9f7 27611 * | | |0 = No error had occurred during the transaction.
<> 144:ef7eb2e8f9f7 27612 * | | |1 = An error had occurred during the transaction.
<> 144:ef7eb2e8f9f7 27613 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27614 * |[10] |STSDONEIF |Status Completion Interrupt
<> 144:ef7eb2e8f9f7 27615 * | | |0 = Not a USB transaction has completed successfully.
<> 144:ef7eb2e8f9f7 27616 * | | |1 = The status stage of a USB transaction has completed successfully.
<> 144:ef7eb2e8f9f7 27617 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27618 * |[11] |BUFFULLIF |Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 27619 * | | |0 = The control-endpoint buffer is not full.
<> 144:ef7eb2e8f9f7 27620 * | | |1 = The control-endpoint buffer is full.
<> 144:ef7eb2e8f9f7 27621 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27622 * |[12] |BUFEMPTYIF|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 27623 * | | |0 = The control-endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 27624 * | | |1 = The control-endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 27625 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27626 */
<> 144:ef7eb2e8f9f7 27627 __IO uint32_t CEPINTSTS;
<> 144:ef7eb2e8f9f7 27628
<> 144:ef7eb2e8f9f7 27629 /**
<> 144:ef7eb2e8f9f7 27630 * CEPTXCNT
<> 144:ef7eb2e8f9f7 27631 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27632 * Offset: 0x38 Control-Endpoint In-transfer Data Count
<> 144:ef7eb2e8f9f7 27633 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27634 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27635 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27636 * |[0:7] |TXCNT |In-Transfer Data Count
<> 144:ef7eb2e8f9f7 27637 * | | |There is no mode selection for the control endpoint (but it operates like manual mode).The local-CPU has to fill the control-endpoint buffer with the data to be sent for an in-token and to write the count of bytes in this register.
<> 144:ef7eb2e8f9f7 27638 * | | |When zero is written into this field, a zero length packet is sent to the host.
<> 144:ef7eb2e8f9f7 27639 * | | |When the count written in the register is more than the MPS, the data sent will be of only MPS.
<> 144:ef7eb2e8f9f7 27640 */
<> 144:ef7eb2e8f9f7 27641 __IO uint32_t CEPTXCNT;
<> 144:ef7eb2e8f9f7 27642
<> 144:ef7eb2e8f9f7 27643 /**
<> 144:ef7eb2e8f9f7 27644 * CEPRXCNT
<> 144:ef7eb2e8f9f7 27645 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27646 * Offset: 0x3C Control-Endpoint Out-transfer Data Count
<> 144:ef7eb2e8f9f7 27647 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27648 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27649 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27650 * |[0:7] |RXCNT |Out-Transfer Data Count
<> 144:ef7eb2e8f9f7 27651 * | | |The USB device controller maintains the count of the data received in case of an out transfer, during the control transfer.
<> 144:ef7eb2e8f9f7 27652 */
<> 144:ef7eb2e8f9f7 27653 __I uint32_t CEPRXCNT;
<> 144:ef7eb2e8f9f7 27654
<> 144:ef7eb2e8f9f7 27655 /**
<> 144:ef7eb2e8f9f7 27656 * CEPDATCNT
<> 144:ef7eb2e8f9f7 27657 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27658 * Offset: 0x40 Control-Endpoint data count
<> 144:ef7eb2e8f9f7 27659 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27660 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27661 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27662 * |[0:15] |DATCNT |Control-Endpoint Data Count
<> 144:ef7eb2e8f9f7 27663 * | | |The USB device controller maintains the count of the data of control-endpoint.
<> 144:ef7eb2e8f9f7 27664 */
<> 144:ef7eb2e8f9f7 27665 __I uint32_t CEPDATCNT;
<> 144:ef7eb2e8f9f7 27666
<> 144:ef7eb2e8f9f7 27667 /**
<> 144:ef7eb2e8f9f7 27668 * SETUP1_0
<> 144:ef7eb2e8f9f7 27669 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27670 * Offset: 0x44 Setup1 & Setup0 bytes
<> 144:ef7eb2e8f9f7 27671 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27672 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27673 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27674 * |[0:7] |SETUP0 |Setup Byte 0[7:0]
<> 144:ef7eb2e8f9f7 27675 * | | |This register provides byte 0 of the last setup packet received.
<> 144:ef7eb2e8f9f7 27676 * | | |For a Standard Device Request, the following bmRequestType information is returned.
<> 144:ef7eb2e8f9f7 27677 * | | |Bit 7(Direction):
<> 144:ef7eb2e8f9f7 27678 * | | | 0: Host to device
<> 144:ef7eb2e8f9f7 27679 * | | | 1: Device to host
<> 144:ef7eb2e8f9f7 27680 * | | |Bit 6-5 (Type):
<> 144:ef7eb2e8f9f7 27681 * | | | 00: Standard
<> 144:ef7eb2e8f9f7 27682 * | | | 01: Class
<> 144:ef7eb2e8f9f7 27683 * | | | 10: Vendor
<> 144:ef7eb2e8f9f7 27684 * | | | 11: Reserved
<> 144:ef7eb2e8f9f7 27685 * | | |Bit 4-0 (Recipient)
<> 144:ef7eb2e8f9f7 27686 * | | | 00000: Device
<> 144:ef7eb2e8f9f7 27687 * | | | 00001: Interface
<> 144:ef7eb2e8f9f7 27688 * | | | 00010: Endpoint
<> 144:ef7eb2e8f9f7 27689 * | | | 00011: Other
<> 144:ef7eb2e8f9f7 27690 * | | | Others: Reserved
<> 144:ef7eb2e8f9f7 27691 * |[8:15] |SETUP1 |Setup Byte 1[15:8]
<> 144:ef7eb2e8f9f7 27692 * | | |This register provides byte 1 of the last setup packet received.
<> 144:ef7eb2e8f9f7 27693 * | | |For a Standard Device Request, the following bRequest Code information is returned.
<> 144:ef7eb2e8f9f7 27694 * | | |00000000 = Get Status.
<> 144:ef7eb2e8f9f7 27695 * | | |00000001 = Clear Feature.
<> 144:ef7eb2e8f9f7 27696 * | | |00000010 = Reserved.
<> 144:ef7eb2e8f9f7 27697 * | | |00000011 = Set Feature.
<> 144:ef7eb2e8f9f7 27698 * | | |00000100 = Reserved.
<> 144:ef7eb2e8f9f7 27699 * | | |00000101 = Set Address.
<> 144:ef7eb2e8f9f7 27700 * | | |00000110 = Get Descriptor.
<> 144:ef7eb2e8f9f7 27701 * | | |00000111 = Set Descriptor.
<> 144:ef7eb2e8f9f7 27702 * | | |00001000 = Get Configuration.
<> 144:ef7eb2e8f9f7 27703 * | | |00001001 = Set Configuration.
<> 144:ef7eb2e8f9f7 27704 * | | |00001010 = Get Interface.
<> 144:ef7eb2e8f9f7 27705 * | | |00001011 = Set Interface.
<> 144:ef7eb2e8f9f7 27706 * | | |00001100 = Synch Frame.
<> 144:ef7eb2e8f9f7 27707 */
<> 144:ef7eb2e8f9f7 27708 __I uint32_t SETUP1_0;
<> 144:ef7eb2e8f9f7 27709
<> 144:ef7eb2e8f9f7 27710 /**
<> 144:ef7eb2e8f9f7 27711 * SETUP3_2
<> 144:ef7eb2e8f9f7 27712 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27713 * Offset: 0x48 Setup3 & Setup2 Bytes
<> 144:ef7eb2e8f9f7 27714 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27715 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27716 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27717 * |[0:7] |SETUP2 |Setup Byte 2 [7:0]
<> 144:ef7eb2e8f9f7 27718 * | | |This register provides byte 2 of the last setup packet received.
<> 144:ef7eb2e8f9f7 27719 * | | |For a Standard Device Request, the least significant byte of the wValue field is returned.
<> 144:ef7eb2e8f9f7 27720 * |[8:15] |SETUP3 |Setup Byte 3 [15:8]
<> 144:ef7eb2e8f9f7 27721 * | | |This register provides byte 3 of the last setup packet received.
<> 144:ef7eb2e8f9f7 27722 * | | |For a Standard Device Request, the most significant byte of the wValue field is returned.
<> 144:ef7eb2e8f9f7 27723 */
<> 144:ef7eb2e8f9f7 27724 __I uint32_t SETUP3_2;
<> 144:ef7eb2e8f9f7 27725
<> 144:ef7eb2e8f9f7 27726 /**
<> 144:ef7eb2e8f9f7 27727 * SETUP5_4
<> 144:ef7eb2e8f9f7 27728 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27729 * Offset: 0x4C Setup5 & Setup4 Bytes
<> 144:ef7eb2e8f9f7 27730 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27731 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27732 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27733 * |[0:7] |SETUP4 |Setup Byte 4[7:0]
<> 144:ef7eb2e8f9f7 27734 * | | |This register provides byte 4 of the last setup packet received.
<> 144:ef7eb2e8f9f7 27735 * | | |For a Standard Device Request, the least significant byte of the wIndex is returned.
<> 144:ef7eb2e8f9f7 27736 * |[8:15] |SETUP5 |Setup Byte 5[15:8]
<> 144:ef7eb2e8f9f7 27737 * | | |This register provides byte 5 of the last setup packet received.
<> 144:ef7eb2e8f9f7 27738 * | | |For a Standard Device Request, the most significant byte of the wIndex field is returned.
<> 144:ef7eb2e8f9f7 27739 */
<> 144:ef7eb2e8f9f7 27740 __I uint32_t SETUP5_4;
<> 144:ef7eb2e8f9f7 27741
<> 144:ef7eb2e8f9f7 27742 /**
<> 144:ef7eb2e8f9f7 27743 * SETUP7_6
<> 144:ef7eb2e8f9f7 27744 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27745 * Offset: 0x50 Setup7 & Setup6 Bytes
<> 144:ef7eb2e8f9f7 27746 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27747 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27748 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27749 * |[0:7] |SETUP6 |Setup Byte 6[7:0]
<> 144:ef7eb2e8f9f7 27750 * | | |This register provides byte 6 of the last setup packet received.
<> 144:ef7eb2e8f9f7 27751 * | | |For a Standard Device Request, the least significant byte of the wLength field is returned.
<> 144:ef7eb2e8f9f7 27752 * |[8:15] |SETUP7 |Setup Byte 7[15:8]
<> 144:ef7eb2e8f9f7 27753 * | | |This register provides byte 7 of the last setup packet received.
<> 144:ef7eb2e8f9f7 27754 * | | |For a Standard Device Request, the most significant byte of the wLength field is returned.
<> 144:ef7eb2e8f9f7 27755 */
<> 144:ef7eb2e8f9f7 27756 __I uint32_t SETUP7_6;
<> 144:ef7eb2e8f9f7 27757
<> 144:ef7eb2e8f9f7 27758 /**
<> 144:ef7eb2e8f9f7 27759 * CEPBUFSTART
<> 144:ef7eb2e8f9f7 27760 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27761 * Offset: 0x54 Control Endpoint RAM Start Address Register
<> 144:ef7eb2e8f9f7 27762 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27763 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27764 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27765 * |[0:11] |SADDR |Control-Endpoint Start Address
<> 144:ef7eb2e8f9f7 27766 * | | |This is the start-address of the RAM space allocated for the control-endpoint.
<> 144:ef7eb2e8f9f7 27767 */
<> 144:ef7eb2e8f9f7 27768 __IO uint32_t CEPBUFSTART;
<> 144:ef7eb2e8f9f7 27769
<> 144:ef7eb2e8f9f7 27770 /**
<> 144:ef7eb2e8f9f7 27771 * CEPBUFEND
<> 144:ef7eb2e8f9f7 27772 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27773 * Offset: 0x58 Control Endpoint RAM End Address Register
<> 144:ef7eb2e8f9f7 27774 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27775 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27776 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27777 * |[0:11] |EADDR |Control-Endpoint End Address
<> 144:ef7eb2e8f9f7 27778 * | | |This is the end-address of the RAM space allocated for the control-endpoint.
<> 144:ef7eb2e8f9f7 27779 */
<> 144:ef7eb2e8f9f7 27780 __IO uint32_t CEPBUFEND;
<> 144:ef7eb2e8f9f7 27781
<> 144:ef7eb2e8f9f7 27782 /**
<> 144:ef7eb2e8f9f7 27783 * DMACTL
<> 144:ef7eb2e8f9f7 27784 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27785 * Offset: 0x5C DMA Control Status Register
<> 144:ef7eb2e8f9f7 27786 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27787 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27788 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27789 * |[0:3] |EPNUM |DMA Endpoint Address Bits
<> 144:ef7eb2e8f9f7 27790 * | | |Used to define the Endpoint Address
<> 144:ef7eb2e8f9f7 27791 * |[4] |DMARD |DMA Operation
<> 144:ef7eb2e8f9f7 27792 * | | |0 = the operation is a DMA write.
<> 144:ef7eb2e8f9f7 27793 * | | |1 = the operation is a DMA read.
<> 144:ef7eb2e8f9f7 27794 * |[5] |DMAEN |DMA Enable Control
<> 144:ef7eb2e8f9f7 27795 * | | |0 = DMA function Disabled.
<> 144:ef7eb2e8f9f7 27796 * | | |1 = DMA function Enabled.
<> 144:ef7eb2e8f9f7 27797 * |[6] |SGEN |Scatter Gather Function Enable Control
<> 144:ef7eb2e8f9f7 27798 * | | |0 = Scatter gather function Disabled.
<> 144:ef7eb2e8f9f7 27799 * | | |1 = Scatter gather function Enabled.
<> 144:ef7eb2e8f9f7 27800 * |[7] |DMARST |Reset DMA State Machine
<> 144:ef7eb2e8f9f7 27801 * | | |0 = No reset the DMA state machine.
<> 144:ef7eb2e8f9f7 27802 * | | |1 = Reset the DMA state machine.
<> 144:ef7eb2e8f9f7 27803 */
<> 144:ef7eb2e8f9f7 27804 __IO uint32_t DMACTL;
<> 144:ef7eb2e8f9f7 27805
<> 144:ef7eb2e8f9f7 27806 /**
<> 144:ef7eb2e8f9f7 27807 * DMACNT
<> 144:ef7eb2e8f9f7 27808 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27809 * Offset: 0x60 DMA Count Register
<> 144:ef7eb2e8f9f7 27810 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27811 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27812 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27813 * |[0:19] |DMACNT |DMA Transfer Count
<> 144:ef7eb2e8f9f7 27814 * | | |The transfer count of the DMA operation to be performed is written to this register.
<> 144:ef7eb2e8f9f7 27815 */
<> 144:ef7eb2e8f9f7 27816 __IO uint32_t DMACNT;
<> 144:ef7eb2e8f9f7 27817
<> 144:ef7eb2e8f9f7 27818 union {
<> 144:ef7eb2e8f9f7 27819
<> 144:ef7eb2e8f9f7 27820 /**
<> 144:ef7eb2e8f9f7 27821 * EPADAT
<> 144:ef7eb2e8f9f7 27822 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27823 * Offset: 0x64 Endpoint A Data Register
<> 144:ef7eb2e8f9f7 27824 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27825 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27826 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27827 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 27828 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 27829 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 27830 */
<> 144:ef7eb2e8f9f7 27831 __IO uint32_t EPADAT;
<> 144:ef7eb2e8f9f7 27832 /**
<> 144:ef7eb2e8f9f7 27833 * EPADAT_BYTE
<> 144:ef7eb2e8f9f7 27834 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27835 * Offset: 0x64 Endpoint A Data Register for Byte Access
<> 144:ef7eb2e8f9f7 27836 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27837 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27838 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27839 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 27840 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 27841 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 27842 */
<> 144:ef7eb2e8f9f7 27843 __IO uint8_t EPADAT_BYTE;
<> 144:ef7eb2e8f9f7 27844
<> 144:ef7eb2e8f9f7 27845 }; ///< Define EPA Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 27846
<> 144:ef7eb2e8f9f7 27847 /**
<> 144:ef7eb2e8f9f7 27848 * EPAINTSTS
<> 144:ef7eb2e8f9f7 27849 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27850 * Offset: 0x68 Endpoint A Interrupt Status Register
<> 144:ef7eb2e8f9f7 27851 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27852 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27853 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27854 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 27855 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 27856 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 27857 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 27858 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 27859 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 27860 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 27861 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 27862 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 27863 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 27864 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 27865 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 27866 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 27867 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 27868 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 27869 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 27870 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 27871 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27872 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 27873 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 27874 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 27875 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27876 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 27877 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 27878 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 27879 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27880 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 27881 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 27882 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 27883 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 27884 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27885 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 27886 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 27887 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 27888 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27889 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 27890 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 27891 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 27892 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27893 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 27894 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 27895 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 27896 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27897 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 27898 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 27899 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 27900 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27901 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 27902 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 27903 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 27904 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27905 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 27906 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 27907 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 27908 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27909 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 27910 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 27911 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 27912 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 27913 */
<> 144:ef7eb2e8f9f7 27914 __IO uint32_t EPAINTSTS;
<> 144:ef7eb2e8f9f7 27915
<> 144:ef7eb2e8f9f7 27916 /**
<> 144:ef7eb2e8f9f7 27917 * EPAINTEN
<> 144:ef7eb2e8f9f7 27918 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27919 * Offset: 0x6C Endpoint A Interrupt Enable Register
<> 144:ef7eb2e8f9f7 27920 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27921 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27922 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27923 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 27924 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 27925 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 27926 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 27927 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 27928 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 27929 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 27930 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 27931 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27932 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 27933 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 27934 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 27935 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27936 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 27937 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 27938 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 27939 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27940 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 27941 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 27942 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 27943 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27944 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 27945 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 27946 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 27947 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27948 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 27949 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 27950 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 27951 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27952 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 27953 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 27954 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 27955 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27956 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 27957 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 27958 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 27959 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27960 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 27961 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 27962 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 27963 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27964 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 27965 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 27966 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 27967 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27968 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 27969 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 27970 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 27971 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 27972 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 27973 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 27974 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 27975 */
<> 144:ef7eb2e8f9f7 27976 __IO uint32_t EPAINTEN;
<> 144:ef7eb2e8f9f7 27977
<> 144:ef7eb2e8f9f7 27978 /**
<> 144:ef7eb2e8f9f7 27979 * EPADATCNT
<> 144:ef7eb2e8f9f7 27980 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27981 * Offset: 0x70 Endpoint A Data Available Count Register
<> 144:ef7eb2e8f9f7 27982 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27983 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27984 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27985 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 27986 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 27987 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 27988 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 27989 */
<> 144:ef7eb2e8f9f7 27990 __I uint32_t EPADATCNT;
<> 144:ef7eb2e8f9f7 27991
<> 144:ef7eb2e8f9f7 27992 /**
<> 144:ef7eb2e8f9f7 27993 * EPARSPCTL
<> 144:ef7eb2e8f9f7 27994 * ===================================================================================================
<> 144:ef7eb2e8f9f7 27995 * Offset: 0x74 Endpoint A Response Control Register
<> 144:ef7eb2e8f9f7 27996 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 27997 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 27998 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 27999 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 28000 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 28001 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 28002 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 28003 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 28004 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 28005 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 28006 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 28007 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 28008 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 28009 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 28010 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 28011 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 28012 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 28013 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 28014 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28015 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28016 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 28017 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 28018 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28019 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28020 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 28021 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28022 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 28023 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28024 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28025 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 28026 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 28027 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28028 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28029 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28030 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 28031 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 28032 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 28033 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 28034 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 28035 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 28036 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28037 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28038 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28039 */
<> 144:ef7eb2e8f9f7 28040 __IO uint32_t EPARSPCTL;
<> 144:ef7eb2e8f9f7 28041
<> 144:ef7eb2e8f9f7 28042 /**
<> 144:ef7eb2e8f9f7 28043 * EPAMPS
<> 144:ef7eb2e8f9f7 28044 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28045 * Offset: 0x78 Endpoint A Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 28046 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28047 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28048 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28049 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 28050 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 28051 */
<> 144:ef7eb2e8f9f7 28052 __IO uint32_t EPAMPS;
<> 144:ef7eb2e8f9f7 28053
<> 144:ef7eb2e8f9f7 28054 /**
<> 144:ef7eb2e8f9f7 28055 * EPATXCNT
<> 144:ef7eb2e8f9f7 28056 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28057 * Offset: 0x7C Endpoint A Transfer Count Register
<> 144:ef7eb2e8f9f7 28058 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28059 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28060 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28061 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 28062 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 28063 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 28064 */
<> 144:ef7eb2e8f9f7 28065 __IO uint32_t EPATXCNT;
<> 144:ef7eb2e8f9f7 28066
<> 144:ef7eb2e8f9f7 28067 /**
<> 144:ef7eb2e8f9f7 28068 * EPACFG
<> 144:ef7eb2e8f9f7 28069 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28070 * Offset: 0x80 Endpoint A Configuration Register
<> 144:ef7eb2e8f9f7 28071 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28072 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28073 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28074 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 28075 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 28076 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 28077 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 28078 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 28079 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 28080 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 28081 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 28082 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 28083 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 28084 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 28085 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 28086 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 28087 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 28088 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 28089 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 28090 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 28091 */
<> 144:ef7eb2e8f9f7 28092 __IO uint32_t EPACFG;
<> 144:ef7eb2e8f9f7 28093
<> 144:ef7eb2e8f9f7 28094 /**
<> 144:ef7eb2e8f9f7 28095 * EPABUFSTART
<> 144:ef7eb2e8f9f7 28096 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28097 * Offset: 0x84 Endpoint A RAM Start Address Register
<> 144:ef7eb2e8f9f7 28098 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28099 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28100 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28101 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 28102 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 28103 */
<> 144:ef7eb2e8f9f7 28104 __IO uint32_t EPABUFSTART;
<> 144:ef7eb2e8f9f7 28105
<> 144:ef7eb2e8f9f7 28106 /**
<> 144:ef7eb2e8f9f7 28107 * EPABUFEND
<> 144:ef7eb2e8f9f7 28108 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28109 * Offset: 0x88 Endpoint A RAM End Address Register
<> 144:ef7eb2e8f9f7 28110 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28111 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28112 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28113 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 28114 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 28115 */
<> 144:ef7eb2e8f9f7 28116 __IO uint32_t EPABUFEND;
<> 144:ef7eb2e8f9f7 28117
<> 144:ef7eb2e8f9f7 28118 union {
<> 144:ef7eb2e8f9f7 28119
<> 144:ef7eb2e8f9f7 28120 /**
<> 144:ef7eb2e8f9f7 28121 * EPBDAT
<> 144:ef7eb2e8f9f7 28122 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28123 * Offset: 0x8C Endpoint B Data Register
<> 144:ef7eb2e8f9f7 28124 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28125 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28126 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28127 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 28128 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 28129 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 28130 */
<> 144:ef7eb2e8f9f7 28131 __IO uint32_t EPBDAT;
<> 144:ef7eb2e8f9f7 28132 /**
<> 144:ef7eb2e8f9f7 28133 * EPBDAT_BYTE
<> 144:ef7eb2e8f9f7 28134 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28135 * Offset: 0x8C Endpoint B Data Register or Byte Access
<> 144:ef7eb2e8f9f7 28136 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28137 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28138 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28139 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 28140 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 28141 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 28142 */
<> 144:ef7eb2e8f9f7 28143 __IO uint8_t EPBDAT_BYTE;
<> 144:ef7eb2e8f9f7 28144
<> 144:ef7eb2e8f9f7 28145 }; ///< Define EPB Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 28146
<> 144:ef7eb2e8f9f7 28147 /**
<> 144:ef7eb2e8f9f7 28148 * EPBINTSTS
<> 144:ef7eb2e8f9f7 28149 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28150 * Offset: 0x90 Endpoint B Interrupt Status Register
<> 144:ef7eb2e8f9f7 28151 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28152 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28153 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28154 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 28155 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 28156 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 28157 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 28158 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 28159 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 28160 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 28161 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 28162 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 28163 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 28164 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 28165 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 28166 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 28167 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 28168 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 28169 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 28170 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 28171 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28172 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 28173 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 28174 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 28175 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28176 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 28177 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 28178 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 28179 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28180 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 28181 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 28182 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 28183 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 28184 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28185 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 28186 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28187 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28188 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28189 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 28190 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 28191 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 28192 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28193 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 28194 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 28195 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 28196 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28197 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 28198 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 28199 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 28200 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28201 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 28202 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 28203 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 28204 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28205 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 28206 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 28207 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 28208 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28209 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 28210 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 28211 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 28212 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28213 */
<> 144:ef7eb2e8f9f7 28214 __IO uint32_t EPBINTSTS;
<> 144:ef7eb2e8f9f7 28215
<> 144:ef7eb2e8f9f7 28216 /**
<> 144:ef7eb2e8f9f7 28217 * EPBINTEN
<> 144:ef7eb2e8f9f7 28218 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28219 * Offset: 0x94 Endpoint B Interrupt Enable Register
<> 144:ef7eb2e8f9f7 28220 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28221 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28222 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28223 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 28224 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 28225 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 28226 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 28227 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 28228 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 28229 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 28230 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 28231 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28232 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 28233 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 28234 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 28235 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28236 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 28237 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 28238 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 28239 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28240 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 28241 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 28242 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 28243 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28244 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 28245 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28246 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28247 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28248 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28249 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28250 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28251 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28252 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 28253 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28254 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28255 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28256 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 28257 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28258 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28259 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28260 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 28261 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28262 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28263 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28264 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28265 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 28266 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 28267 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28268 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28269 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 28270 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 28271 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28272 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28273 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 28274 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 28275 */
<> 144:ef7eb2e8f9f7 28276 __IO uint32_t EPBINTEN;
<> 144:ef7eb2e8f9f7 28277
<> 144:ef7eb2e8f9f7 28278 /**
<> 144:ef7eb2e8f9f7 28279 * EPBDATCNT
<> 144:ef7eb2e8f9f7 28280 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28281 * Offset: 0x98 Endpoint B Data Available Count Register
<> 144:ef7eb2e8f9f7 28282 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28283 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28284 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28285 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 28286 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 28287 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 28288 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 28289 */
<> 144:ef7eb2e8f9f7 28290 __I uint32_t EPBDATCNT;
<> 144:ef7eb2e8f9f7 28291
<> 144:ef7eb2e8f9f7 28292 /**
<> 144:ef7eb2e8f9f7 28293 * EPBRSPCTL
<> 144:ef7eb2e8f9f7 28294 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28295 * Offset: 0x9C Endpoint B Response Control Register
<> 144:ef7eb2e8f9f7 28296 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28297 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28298 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28299 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 28300 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 28301 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 28302 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 28303 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 28304 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 28305 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 28306 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 28307 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 28308 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 28309 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 28310 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 28311 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 28312 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 28313 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 28314 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28315 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28316 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 28317 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 28318 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28319 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28320 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 28321 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28322 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 28323 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28324 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28325 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 28326 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 28327 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28328 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28329 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28330 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 28331 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 28332 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 28333 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 28334 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 28335 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 28336 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28337 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28338 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28339 */
<> 144:ef7eb2e8f9f7 28340 __IO uint32_t EPBRSPCTL;
<> 144:ef7eb2e8f9f7 28341
<> 144:ef7eb2e8f9f7 28342 /**
<> 144:ef7eb2e8f9f7 28343 * EPBMPS
<> 144:ef7eb2e8f9f7 28344 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28345 * Offset: 0xA0 Endpoint B Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 28346 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28347 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28348 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28349 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 28350 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 28351 */
<> 144:ef7eb2e8f9f7 28352 __IO uint32_t EPBMPS;
<> 144:ef7eb2e8f9f7 28353
<> 144:ef7eb2e8f9f7 28354 /**
<> 144:ef7eb2e8f9f7 28355 * EPBTXCNT
<> 144:ef7eb2e8f9f7 28356 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28357 * Offset: 0xA4 Endpoint B Transfer Count Register
<> 144:ef7eb2e8f9f7 28358 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28359 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28360 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28361 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 28362 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 28363 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 28364 */
<> 144:ef7eb2e8f9f7 28365 __IO uint32_t EPBTXCNT;
<> 144:ef7eb2e8f9f7 28366
<> 144:ef7eb2e8f9f7 28367 /**
<> 144:ef7eb2e8f9f7 28368 * EPBCFG
<> 144:ef7eb2e8f9f7 28369 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28370 * Offset: 0xA8 Endpoint B Configuration Register
<> 144:ef7eb2e8f9f7 28371 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28372 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28373 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28374 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 28375 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 28376 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 28377 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 28378 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 28379 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 28380 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 28381 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 28382 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 28383 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 28384 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 28385 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 28386 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 28387 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 28388 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 28389 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 28390 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 28391 */
<> 144:ef7eb2e8f9f7 28392 __IO uint32_t EPBCFG;
<> 144:ef7eb2e8f9f7 28393
<> 144:ef7eb2e8f9f7 28394 /**
<> 144:ef7eb2e8f9f7 28395 * EPBBUFSTART
<> 144:ef7eb2e8f9f7 28396 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28397 * Offset: 0xAC Endpoint B RAM Start Address Register
<> 144:ef7eb2e8f9f7 28398 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28399 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28400 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28401 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 28402 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 28403 */
<> 144:ef7eb2e8f9f7 28404 __IO uint32_t EPBBUFSTART;
<> 144:ef7eb2e8f9f7 28405
<> 144:ef7eb2e8f9f7 28406 /**
<> 144:ef7eb2e8f9f7 28407 * EPBBUFEND
<> 144:ef7eb2e8f9f7 28408 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28409 * Offset: 0xB0 Endpoint B RAM End Address Register
<> 144:ef7eb2e8f9f7 28410 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28411 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28412 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28413 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 28414 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 28415 */
<> 144:ef7eb2e8f9f7 28416 __IO uint32_t EPBBUFEND;
<> 144:ef7eb2e8f9f7 28417
<> 144:ef7eb2e8f9f7 28418 union {
<> 144:ef7eb2e8f9f7 28419
<> 144:ef7eb2e8f9f7 28420 /**
<> 144:ef7eb2e8f9f7 28421 * EPCDAT
<> 144:ef7eb2e8f9f7 28422 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28423 * Offset: 0xB4 Endpoint C Data Register
<> 144:ef7eb2e8f9f7 28424 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28425 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28426 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28427 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 28428 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 28429 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 28430 */
<> 144:ef7eb2e8f9f7 28431 __IO uint32_t EPCDAT;
<> 144:ef7eb2e8f9f7 28432 /**
<> 144:ef7eb2e8f9f7 28433 * EPCDAT_BYTE
<> 144:ef7eb2e8f9f7 28434 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28435 * Offset: 0xB4 Endpoint C Data Register for Byte Access
<> 144:ef7eb2e8f9f7 28436 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28437 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28438 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28439 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 28440 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 28441 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 28442 */
<> 144:ef7eb2e8f9f7 28443 __IO uint8_t EPCDAT_BYTE;
<> 144:ef7eb2e8f9f7 28444
<> 144:ef7eb2e8f9f7 28445 }; ///< Define EPC Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 28446
<> 144:ef7eb2e8f9f7 28447 /**
<> 144:ef7eb2e8f9f7 28448 * EPCINTSTS
<> 144:ef7eb2e8f9f7 28449 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28450 * Offset: 0xB8 Endpoint C Interrupt Status Register
<> 144:ef7eb2e8f9f7 28451 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28452 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28453 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28454 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 28455 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 28456 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 28457 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 28458 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 28459 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 28460 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 28461 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 28462 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 28463 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 28464 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 28465 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 28466 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 28467 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 28468 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 28469 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 28470 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 28471 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28472 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 28473 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 28474 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 28475 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28476 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 28477 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 28478 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 28479 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28480 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 28481 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 28482 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 28483 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 28484 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28485 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 28486 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28487 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28488 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28489 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 28490 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 28491 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 28492 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28493 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 28494 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 28495 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 28496 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28497 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 28498 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 28499 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 28500 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28501 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 28502 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 28503 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 28504 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28505 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 28506 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 28507 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 28508 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28509 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 28510 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 28511 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 28512 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28513 */
<> 144:ef7eb2e8f9f7 28514 __IO uint32_t EPCINTSTS;
<> 144:ef7eb2e8f9f7 28515
<> 144:ef7eb2e8f9f7 28516 /**
<> 144:ef7eb2e8f9f7 28517 * EPCINTEN
<> 144:ef7eb2e8f9f7 28518 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28519 * Offset: 0xBC Endpoint C Interrupt Enable Register
<> 144:ef7eb2e8f9f7 28520 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28521 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28522 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28523 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 28524 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 28525 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 28526 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 28527 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 28528 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 28529 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 28530 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 28531 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28532 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 28533 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 28534 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 28535 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28536 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 28537 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 28538 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 28539 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28540 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 28541 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 28542 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 28543 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28544 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 28545 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28546 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28547 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28548 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28549 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28550 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28551 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28552 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 28553 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28554 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28555 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28556 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 28557 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28558 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28559 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28560 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 28561 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28562 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28563 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28564 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28565 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 28566 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 28567 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28568 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28569 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 28570 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 28571 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28572 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28573 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 28574 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 28575 */
<> 144:ef7eb2e8f9f7 28576 __IO uint32_t EPCINTEN;
<> 144:ef7eb2e8f9f7 28577
<> 144:ef7eb2e8f9f7 28578 /**
<> 144:ef7eb2e8f9f7 28579 * EPCDATCNT
<> 144:ef7eb2e8f9f7 28580 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28581 * Offset: 0xC0 Endpoint C Data Available Count Register
<> 144:ef7eb2e8f9f7 28582 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28583 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28584 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28585 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 28586 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 28587 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 28588 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 28589 */
<> 144:ef7eb2e8f9f7 28590 __I uint32_t EPCDATCNT;
<> 144:ef7eb2e8f9f7 28591
<> 144:ef7eb2e8f9f7 28592 /**
<> 144:ef7eb2e8f9f7 28593 * EPCRSPCTL
<> 144:ef7eb2e8f9f7 28594 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28595 * Offset: 0xC4 Endpoint C Response Control Register
<> 144:ef7eb2e8f9f7 28596 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28597 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28598 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28599 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 28600 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 28601 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 28602 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 28603 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 28604 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 28605 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 28606 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 28607 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 28608 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 28609 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 28610 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 28611 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 28612 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 28613 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 28614 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28615 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28616 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 28617 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 28618 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28619 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28620 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 28621 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28622 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 28623 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28624 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28625 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 28626 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 28627 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28628 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28629 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28630 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 28631 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 28632 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 28633 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 28634 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 28635 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 28636 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28637 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28638 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28639 */
<> 144:ef7eb2e8f9f7 28640 __IO uint32_t EPCRSPCTL;
<> 144:ef7eb2e8f9f7 28641
<> 144:ef7eb2e8f9f7 28642 /**
<> 144:ef7eb2e8f9f7 28643 * EPCMPS
<> 144:ef7eb2e8f9f7 28644 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28645 * Offset: 0xC8 Endpoint C Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 28646 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28647 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28648 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28649 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 28650 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 28651 */
<> 144:ef7eb2e8f9f7 28652 __IO uint32_t EPCMPS;
<> 144:ef7eb2e8f9f7 28653
<> 144:ef7eb2e8f9f7 28654 /**
<> 144:ef7eb2e8f9f7 28655 * EPCTXCNT
<> 144:ef7eb2e8f9f7 28656 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28657 * Offset: 0xCC Endpoint C Transfer Count Register
<> 144:ef7eb2e8f9f7 28658 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28659 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28660 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28661 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 28662 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 28663 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 28664 */
<> 144:ef7eb2e8f9f7 28665 __IO uint32_t EPCTXCNT;
<> 144:ef7eb2e8f9f7 28666
<> 144:ef7eb2e8f9f7 28667 /**
<> 144:ef7eb2e8f9f7 28668 * EPCCFG
<> 144:ef7eb2e8f9f7 28669 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28670 * Offset: 0xD0 Endpoint C Configuration Register
<> 144:ef7eb2e8f9f7 28671 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28672 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28673 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28674 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 28675 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 28676 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 28677 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 28678 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 28679 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 28680 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 28681 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 28682 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 28683 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 28684 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 28685 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 28686 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 28687 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 28688 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 28689 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 28690 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 28691 */
<> 144:ef7eb2e8f9f7 28692 __IO uint32_t EPCCFG;
<> 144:ef7eb2e8f9f7 28693
<> 144:ef7eb2e8f9f7 28694 /**
<> 144:ef7eb2e8f9f7 28695 * EPCBUFSTART
<> 144:ef7eb2e8f9f7 28696 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28697 * Offset: 0xD4 Endpoint C RAM Start Address Register
<> 144:ef7eb2e8f9f7 28698 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28699 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28700 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28701 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 28702 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 28703 */
<> 144:ef7eb2e8f9f7 28704 __IO uint32_t EPCBUFSTART;
<> 144:ef7eb2e8f9f7 28705
<> 144:ef7eb2e8f9f7 28706 /**
<> 144:ef7eb2e8f9f7 28707 * EPCBUFEND
<> 144:ef7eb2e8f9f7 28708 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28709 * Offset: 0xD8 Endpoint C RAM End Address Register
<> 144:ef7eb2e8f9f7 28710 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28711 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28712 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28713 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 28714 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 28715 */
<> 144:ef7eb2e8f9f7 28716 __IO uint32_t EPCBUFEND;
<> 144:ef7eb2e8f9f7 28717
<> 144:ef7eb2e8f9f7 28718 union {
<> 144:ef7eb2e8f9f7 28719
<> 144:ef7eb2e8f9f7 28720 /**
<> 144:ef7eb2e8f9f7 28721 * EPDDAT
<> 144:ef7eb2e8f9f7 28722 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28723 * Offset: 0xDC Endpoint D Data Register
<> 144:ef7eb2e8f9f7 28724 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28725 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28726 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28727 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 28728 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 28729 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 28730 */
<> 144:ef7eb2e8f9f7 28731 __IO uint32_t EPDDAT;
<> 144:ef7eb2e8f9f7 28732 /**
<> 144:ef7eb2e8f9f7 28733 * EPDDAT_BYTE
<> 144:ef7eb2e8f9f7 28734 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28735 * Offset: 0xDC Endpoint D Data Register for Byte Access
<> 144:ef7eb2e8f9f7 28736 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28737 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28738 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28739 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 28740 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 28741 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 28742 */
<> 144:ef7eb2e8f9f7 28743 __IO uint8_t EPDDAT_BYTE;
<> 144:ef7eb2e8f9f7 28744
<> 144:ef7eb2e8f9f7 28745 }; ///< Define EPD Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 28746
<> 144:ef7eb2e8f9f7 28747 /**
<> 144:ef7eb2e8f9f7 28748 * EPDINTSTS
<> 144:ef7eb2e8f9f7 28749 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28750 * Offset: 0xE0 Endpoint D Interrupt Status Register
<> 144:ef7eb2e8f9f7 28751 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28752 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28753 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28754 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 28755 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 28756 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 28757 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 28758 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 28759 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 28760 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 28761 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 28762 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 28763 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 28764 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 28765 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 28766 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 28767 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 28768 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 28769 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 28770 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 28771 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28772 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 28773 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 28774 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 28775 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28776 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 28777 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 28778 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 28779 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28780 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 28781 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 28782 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 28783 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 28784 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28785 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 28786 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28787 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28788 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28789 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 28790 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 28791 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 28792 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28793 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 28794 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 28795 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 28796 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28797 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 28798 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 28799 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 28800 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28801 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 28802 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 28803 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 28804 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28805 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 28806 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 28807 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 28808 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28809 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 28810 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 28811 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 28812 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 28813 */
<> 144:ef7eb2e8f9f7 28814 __IO uint32_t EPDINTSTS;
<> 144:ef7eb2e8f9f7 28815
<> 144:ef7eb2e8f9f7 28816 /**
<> 144:ef7eb2e8f9f7 28817 * EPDINTEN
<> 144:ef7eb2e8f9f7 28818 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28819 * Offset: 0xE4 Endpoint D Interrupt Enable Register
<> 144:ef7eb2e8f9f7 28820 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28821 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28822 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28823 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 28824 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 28825 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 28826 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 28827 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 28828 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 28829 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 28830 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 28831 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28832 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 28833 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 28834 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 28835 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28836 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 28837 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 28838 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 28839 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28840 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 28841 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 28842 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 28843 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28844 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 28845 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28846 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28847 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28848 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 28849 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28850 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28851 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28852 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 28853 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28854 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28855 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28856 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 28857 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28858 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28859 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28860 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 28861 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 28862 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 28863 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28864 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28865 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 28866 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 28867 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28868 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28869 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 28870 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 28871 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 28872 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 28873 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 28874 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 28875 */
<> 144:ef7eb2e8f9f7 28876 __IO uint32_t EPDINTEN;
<> 144:ef7eb2e8f9f7 28877
<> 144:ef7eb2e8f9f7 28878 /**
<> 144:ef7eb2e8f9f7 28879 * EPDDATCNT
<> 144:ef7eb2e8f9f7 28880 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28881 * Offset: 0xE8 Endpoint D Data Available Count Register
<> 144:ef7eb2e8f9f7 28882 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28883 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28884 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28885 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 28886 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 28887 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 28888 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 28889 */
<> 144:ef7eb2e8f9f7 28890 __I uint32_t EPDDATCNT;
<> 144:ef7eb2e8f9f7 28891
<> 144:ef7eb2e8f9f7 28892 /**
<> 144:ef7eb2e8f9f7 28893 * EPDRSPCTL
<> 144:ef7eb2e8f9f7 28894 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28895 * Offset: 0xEC Endpoint D Response Control Register
<> 144:ef7eb2e8f9f7 28896 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28897 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28898 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28899 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 28900 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 28901 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 28902 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 28903 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 28904 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 28905 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 28906 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 28907 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 28908 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 28909 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 28910 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 28911 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 28912 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 28913 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 28914 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28915 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28916 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 28917 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 28918 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28919 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 28920 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 28921 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28922 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 28923 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28924 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 28925 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 28926 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 28927 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28928 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28929 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 28930 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 28931 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 28932 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 28933 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 28934 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 28935 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 28936 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28937 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28938 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 28939 */
<> 144:ef7eb2e8f9f7 28940 __IO uint32_t EPDRSPCTL;
<> 144:ef7eb2e8f9f7 28941
<> 144:ef7eb2e8f9f7 28942 /**
<> 144:ef7eb2e8f9f7 28943 * EPDMPS
<> 144:ef7eb2e8f9f7 28944 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28945 * Offset: 0xF0 Endpoint D Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 28946 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28947 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28948 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28949 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 28950 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 28951 */
<> 144:ef7eb2e8f9f7 28952 __IO uint32_t EPDMPS;
<> 144:ef7eb2e8f9f7 28953
<> 144:ef7eb2e8f9f7 28954 /**
<> 144:ef7eb2e8f9f7 28955 * EPDTXCNT
<> 144:ef7eb2e8f9f7 28956 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28957 * Offset: 0xF4 Endpoint D Transfer Count Register
<> 144:ef7eb2e8f9f7 28958 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28959 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28960 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28961 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 28962 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 28963 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 28964 */
<> 144:ef7eb2e8f9f7 28965 __IO uint32_t EPDTXCNT;
<> 144:ef7eb2e8f9f7 28966
<> 144:ef7eb2e8f9f7 28967 /**
<> 144:ef7eb2e8f9f7 28968 * EPDCFG
<> 144:ef7eb2e8f9f7 28969 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28970 * Offset: 0xF8 Endpoint D Configuration Register
<> 144:ef7eb2e8f9f7 28971 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28972 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 28973 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 28974 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 28975 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 28976 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 28977 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 28978 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 28979 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 28980 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 28981 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 28982 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 28983 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 28984 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 28985 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 28986 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 28987 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 28988 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 28989 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 28990 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 28991 */
<> 144:ef7eb2e8f9f7 28992 __IO uint32_t EPDCFG;
<> 144:ef7eb2e8f9f7 28993
<> 144:ef7eb2e8f9f7 28994 /**
<> 144:ef7eb2e8f9f7 28995 * EPDBUFSTART
<> 144:ef7eb2e8f9f7 28996 * ===================================================================================================
<> 144:ef7eb2e8f9f7 28997 * Offset: 0xFC Endpoint D RAM Start Address Register
<> 144:ef7eb2e8f9f7 28998 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 28999 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29000 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29001 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 29002 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 29003 */
<> 144:ef7eb2e8f9f7 29004 __IO uint32_t EPDBUFSTART;
<> 144:ef7eb2e8f9f7 29005
<> 144:ef7eb2e8f9f7 29006 /**
<> 144:ef7eb2e8f9f7 29007 * EPDBUFEND
<> 144:ef7eb2e8f9f7 29008 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29009 * Offset: 0x100 Endpoint D RAM End Address Register
<> 144:ef7eb2e8f9f7 29010 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29011 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29012 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29013 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 29014 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 29015 */
<> 144:ef7eb2e8f9f7 29016 __IO uint32_t EPDBUFEND;
<> 144:ef7eb2e8f9f7 29017
<> 144:ef7eb2e8f9f7 29018 union {
<> 144:ef7eb2e8f9f7 29019
<> 144:ef7eb2e8f9f7 29020 /**
<> 144:ef7eb2e8f9f7 29021 * EPEDAT
<> 144:ef7eb2e8f9f7 29022 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29023 * Offset: 0x104 Endpoint E Data Register
<> 144:ef7eb2e8f9f7 29024 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29025 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29026 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29027 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 29028 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 29029 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 29030 */
<> 144:ef7eb2e8f9f7 29031 __IO uint32_t EPEDAT;
<> 144:ef7eb2e8f9f7 29032 /**
<> 144:ef7eb2e8f9f7 29033 * EPEDAT_BYTE
<> 144:ef7eb2e8f9f7 29034 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29035 * Offset: 0x104 Endpoint E Data Register for Byte Access
<> 144:ef7eb2e8f9f7 29036 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29037 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29038 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29039 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 29040 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 29041 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 29042 */
<> 144:ef7eb2e8f9f7 29043 __IO uint8_t EPEDAT_BYTE;
<> 144:ef7eb2e8f9f7 29044
<> 144:ef7eb2e8f9f7 29045 }; ///< Define EPE Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 29046
<> 144:ef7eb2e8f9f7 29047 /**
<> 144:ef7eb2e8f9f7 29048 * EPEINTSTS
<> 144:ef7eb2e8f9f7 29049 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29050 * Offset: 0x108 Endpoint E Interrupt Status Register
<> 144:ef7eb2e8f9f7 29051 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29052 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29053 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29054 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 29055 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 29056 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 29057 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 29058 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 29059 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 29060 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 29061 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 29062 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 29063 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 29064 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 29065 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 29066 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 29067 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 29068 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 29069 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 29070 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 29071 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29072 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 29073 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 29074 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 29075 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29076 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 29077 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 29078 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 29079 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29080 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 29081 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 29082 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 29083 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 29084 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29085 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 29086 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29087 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29088 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29089 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 29090 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 29091 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 29092 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29093 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 29094 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 29095 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 29096 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29097 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 29098 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 29099 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 29100 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29101 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 29102 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 29103 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 29104 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29105 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 29106 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 29107 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 29108 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29109 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 29110 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 29111 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 29112 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29113 */
<> 144:ef7eb2e8f9f7 29114 __IO uint32_t EPEINTSTS;
<> 144:ef7eb2e8f9f7 29115
<> 144:ef7eb2e8f9f7 29116 /**
<> 144:ef7eb2e8f9f7 29117 * EPEINTEN
<> 144:ef7eb2e8f9f7 29118 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29119 * Offset: 0x10C Endpoint E Interrupt Enable Register
<> 144:ef7eb2e8f9f7 29120 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29121 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29122 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29123 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 29124 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 29125 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 29126 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 29127 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 29128 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 29129 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 29130 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 29131 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29132 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 29133 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 29134 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 29135 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29136 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 29137 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 29138 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 29139 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29140 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 29141 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 29142 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 29143 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29144 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 29145 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29146 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29147 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29148 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29149 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29150 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29151 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29152 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 29153 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29154 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29155 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29156 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 29157 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29158 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29159 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29160 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 29161 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29162 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29163 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29164 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29165 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 29166 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 29167 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29168 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29169 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 29170 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 29171 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29172 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29173 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 29174 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 29175 */
<> 144:ef7eb2e8f9f7 29176 __IO uint32_t EPEINTEN;
<> 144:ef7eb2e8f9f7 29177
<> 144:ef7eb2e8f9f7 29178 /**
<> 144:ef7eb2e8f9f7 29179 * EPEDATCNT
<> 144:ef7eb2e8f9f7 29180 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29181 * Offset: 0x110 Endpoint E Data Available Count Register
<> 144:ef7eb2e8f9f7 29182 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29183 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29184 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29185 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 29186 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 29187 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 29188 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 29189 */
<> 144:ef7eb2e8f9f7 29190 __I uint32_t EPEDATCNT;
<> 144:ef7eb2e8f9f7 29191
<> 144:ef7eb2e8f9f7 29192 /**
<> 144:ef7eb2e8f9f7 29193 * EPERSPCTL
<> 144:ef7eb2e8f9f7 29194 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29195 * Offset: 0x114 Endpoint E Response Control Register
<> 144:ef7eb2e8f9f7 29196 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29197 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29198 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29199 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 29200 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 29201 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 29202 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 29203 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 29204 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 29205 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 29206 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 29207 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 29208 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 29209 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 29210 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 29211 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 29212 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 29213 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 29214 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29215 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29216 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 29217 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 29218 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29219 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29220 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 29221 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29222 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 29223 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29224 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29225 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 29226 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 29227 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29228 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29229 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29230 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 29231 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 29232 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 29233 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 29234 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 29235 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 29236 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29237 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29238 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29239 */
<> 144:ef7eb2e8f9f7 29240 __IO uint32_t EPERSPCTL;
<> 144:ef7eb2e8f9f7 29241
<> 144:ef7eb2e8f9f7 29242 /**
<> 144:ef7eb2e8f9f7 29243 * EPEMPS
<> 144:ef7eb2e8f9f7 29244 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29245 * Offset: 0x118 Endpoint E Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 29246 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29247 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29248 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29249 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 29250 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 29251 */
<> 144:ef7eb2e8f9f7 29252 __IO uint32_t EPEMPS;
<> 144:ef7eb2e8f9f7 29253
<> 144:ef7eb2e8f9f7 29254 /**
<> 144:ef7eb2e8f9f7 29255 * EPETXCNT
<> 144:ef7eb2e8f9f7 29256 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29257 * Offset: 0x11C Endpoint E Transfer Count Register
<> 144:ef7eb2e8f9f7 29258 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29259 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29260 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29261 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 29262 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 29263 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 29264 */
<> 144:ef7eb2e8f9f7 29265 __IO uint32_t EPETXCNT;
<> 144:ef7eb2e8f9f7 29266
<> 144:ef7eb2e8f9f7 29267 /**
<> 144:ef7eb2e8f9f7 29268 * EPECFG
<> 144:ef7eb2e8f9f7 29269 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29270 * Offset: 0x120 Endpoint E Configuration Register
<> 144:ef7eb2e8f9f7 29271 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29272 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29273 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29274 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 29275 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 29276 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 29277 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 29278 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 29279 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 29280 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 29281 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 29282 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 29283 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 29284 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 29285 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 29286 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 29287 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 29288 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 29289 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 29290 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 29291 */
<> 144:ef7eb2e8f9f7 29292 __IO uint32_t EPECFG;
<> 144:ef7eb2e8f9f7 29293
<> 144:ef7eb2e8f9f7 29294 /**
<> 144:ef7eb2e8f9f7 29295 * EPEBUFSTART
<> 144:ef7eb2e8f9f7 29296 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29297 * Offset: 0x124 Endpoint E RAM Start Address Register
<> 144:ef7eb2e8f9f7 29298 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29299 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29300 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29301 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 29302 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 29303 */
<> 144:ef7eb2e8f9f7 29304 __IO uint32_t EPEBUFSTART;
<> 144:ef7eb2e8f9f7 29305
<> 144:ef7eb2e8f9f7 29306 /**
<> 144:ef7eb2e8f9f7 29307 * EPEBUFEND
<> 144:ef7eb2e8f9f7 29308 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29309 * Offset: 0x128 Endpoint E RAM End Address Register
<> 144:ef7eb2e8f9f7 29310 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29311 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29312 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29313 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 29314 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 29315 */
<> 144:ef7eb2e8f9f7 29316 __IO uint32_t EPEBUFEND;
<> 144:ef7eb2e8f9f7 29317
<> 144:ef7eb2e8f9f7 29318 union {
<> 144:ef7eb2e8f9f7 29319
<> 144:ef7eb2e8f9f7 29320 /**
<> 144:ef7eb2e8f9f7 29321 * EPFDAT
<> 144:ef7eb2e8f9f7 29322 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29323 * Offset: 0x12C Endpoint F Data Register
<> 144:ef7eb2e8f9f7 29324 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29325 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29326 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29327 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 29328 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 29329 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 29330 */
<> 144:ef7eb2e8f9f7 29331 __IO uint32_t EPFDAT;
<> 144:ef7eb2e8f9f7 29332 /**
<> 144:ef7eb2e8f9f7 29333 * EPFDAT_BYTE
<> 144:ef7eb2e8f9f7 29334 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29335 * Offset: 0x12C Endpoint F Data Register for Byte Access
<> 144:ef7eb2e8f9f7 29336 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29337 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29338 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29339 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 29340 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 29341 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 29342 */
<> 144:ef7eb2e8f9f7 29343 __IO uint8_t EPFDAT_BYTE;
<> 144:ef7eb2e8f9f7 29344
<> 144:ef7eb2e8f9f7 29345 }; ///< Define EPF Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 29346
<> 144:ef7eb2e8f9f7 29347 /**
<> 144:ef7eb2e8f9f7 29348 * EPFINTSTS
<> 144:ef7eb2e8f9f7 29349 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29350 * Offset: 0x130 Endpoint F Interrupt Status Register
<> 144:ef7eb2e8f9f7 29351 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29352 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29353 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29354 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 29355 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 29356 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 29357 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 29358 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 29359 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 29360 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 29361 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 29362 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 29363 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 29364 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 29365 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 29366 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 29367 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 29368 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 29369 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 29370 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 29371 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29372 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 29373 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 29374 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 29375 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29376 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 29377 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 29378 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 29379 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29380 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 29381 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 29382 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 29383 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 29384 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29385 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 29386 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29387 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29388 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29389 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 29390 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 29391 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 29392 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29393 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 29394 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 29395 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 29396 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29397 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 29398 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 29399 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 29400 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29401 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 29402 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 29403 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 29404 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29405 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 29406 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 29407 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 29408 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29409 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 29410 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 29411 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 29412 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29413 */
<> 144:ef7eb2e8f9f7 29414 __IO uint32_t EPFINTSTS;
<> 144:ef7eb2e8f9f7 29415
<> 144:ef7eb2e8f9f7 29416 /**
<> 144:ef7eb2e8f9f7 29417 * EPFINTEN
<> 144:ef7eb2e8f9f7 29418 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29419 * Offset: 0x134 Endpoint F Interrupt Enable Register
<> 144:ef7eb2e8f9f7 29420 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29421 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29422 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29423 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 29424 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 29425 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 29426 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 29427 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 29428 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 29429 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 29430 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 29431 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29432 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 29433 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 29434 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 29435 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29436 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 29437 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 29438 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 29439 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29440 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 29441 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 29442 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 29443 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29444 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 29445 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29446 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29447 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29448 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29449 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29450 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29451 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29452 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 29453 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29454 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29455 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29456 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 29457 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29458 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29459 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29460 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 29461 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29462 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29463 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29464 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29465 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 29466 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 29467 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29468 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29469 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 29470 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 29471 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29472 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29473 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 29474 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 29475 */
<> 144:ef7eb2e8f9f7 29476 __IO uint32_t EPFINTEN;
<> 144:ef7eb2e8f9f7 29477
<> 144:ef7eb2e8f9f7 29478 /**
<> 144:ef7eb2e8f9f7 29479 * EPFDATCNT
<> 144:ef7eb2e8f9f7 29480 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29481 * Offset: 0x138 Endpoint F Data Available Count Register
<> 144:ef7eb2e8f9f7 29482 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29483 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29484 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29485 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 29486 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 29487 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 29488 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 29489 */
<> 144:ef7eb2e8f9f7 29490 __I uint32_t EPFDATCNT;
<> 144:ef7eb2e8f9f7 29491
<> 144:ef7eb2e8f9f7 29492 /**
<> 144:ef7eb2e8f9f7 29493 * EPFRSPCTL
<> 144:ef7eb2e8f9f7 29494 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29495 * Offset: 0x13C Endpoint F Response Control Register
<> 144:ef7eb2e8f9f7 29496 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29497 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29498 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29499 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 29500 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 29501 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 29502 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 29503 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 29504 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 29505 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 29506 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 29507 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 29508 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 29509 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 29510 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 29511 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 29512 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 29513 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 29514 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29515 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29516 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 29517 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 29518 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29519 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29520 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 29521 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29522 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 29523 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29524 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29525 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 29526 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 29527 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29528 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29529 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29530 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 29531 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 29532 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 29533 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 29534 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 29535 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 29536 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29537 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29538 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29539 */
<> 144:ef7eb2e8f9f7 29540 __IO uint32_t EPFRSPCTL;
<> 144:ef7eb2e8f9f7 29541
<> 144:ef7eb2e8f9f7 29542 /**
<> 144:ef7eb2e8f9f7 29543 * EPFMPS
<> 144:ef7eb2e8f9f7 29544 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29545 * Offset: 0x140 Endpoint F Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 29546 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29547 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29548 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29549 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 29550 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 29551 */
<> 144:ef7eb2e8f9f7 29552 __IO uint32_t EPFMPS;
<> 144:ef7eb2e8f9f7 29553
<> 144:ef7eb2e8f9f7 29554 /**
<> 144:ef7eb2e8f9f7 29555 * EPFTXCNT
<> 144:ef7eb2e8f9f7 29556 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29557 * Offset: 0x144 Endpoint F Transfer Count Register
<> 144:ef7eb2e8f9f7 29558 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29559 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29560 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29561 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 29562 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 29563 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 29564 */
<> 144:ef7eb2e8f9f7 29565 __IO uint32_t EPFTXCNT;
<> 144:ef7eb2e8f9f7 29566
<> 144:ef7eb2e8f9f7 29567 /**
<> 144:ef7eb2e8f9f7 29568 * EPFCFG
<> 144:ef7eb2e8f9f7 29569 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29570 * Offset: 0x148 Endpoint F Configuration Register
<> 144:ef7eb2e8f9f7 29571 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29572 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29573 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29574 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 29575 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 29576 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 29577 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 29578 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 29579 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 29580 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 29581 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 29582 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 29583 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 29584 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 29585 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 29586 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 29587 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 29588 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 29589 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 29590 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 29591 */
<> 144:ef7eb2e8f9f7 29592 __IO uint32_t EPFCFG;
<> 144:ef7eb2e8f9f7 29593
<> 144:ef7eb2e8f9f7 29594 /**
<> 144:ef7eb2e8f9f7 29595 * EPFBUFSTART
<> 144:ef7eb2e8f9f7 29596 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29597 * Offset: 0x14C Endpoint F RAM Start Address Register
<> 144:ef7eb2e8f9f7 29598 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29599 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29600 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29601 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 29602 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 29603 */
<> 144:ef7eb2e8f9f7 29604 __IO uint32_t EPFBUFSTART;
<> 144:ef7eb2e8f9f7 29605
<> 144:ef7eb2e8f9f7 29606 /**
<> 144:ef7eb2e8f9f7 29607 * EPFBUFEND
<> 144:ef7eb2e8f9f7 29608 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29609 * Offset: 0x150 Endpoint F RAM End Address Register
<> 144:ef7eb2e8f9f7 29610 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29611 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29612 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29613 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 29614 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 29615 */
<> 144:ef7eb2e8f9f7 29616 __IO uint32_t EPFBUFEND;
<> 144:ef7eb2e8f9f7 29617
<> 144:ef7eb2e8f9f7 29618 union {
<> 144:ef7eb2e8f9f7 29619
<> 144:ef7eb2e8f9f7 29620 /**
<> 144:ef7eb2e8f9f7 29621 * EPGDAT
<> 144:ef7eb2e8f9f7 29622 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29623 * Offset: 0x154 Endpoint G Data Register
<> 144:ef7eb2e8f9f7 29624 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29625 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29626 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29627 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 29628 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 29629 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 29630 */
<> 144:ef7eb2e8f9f7 29631 __IO uint32_t EPGDAT;
<> 144:ef7eb2e8f9f7 29632 /**
<> 144:ef7eb2e8f9f7 29633 * EPGDAT_BYTE
<> 144:ef7eb2e8f9f7 29634 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29635 * Offset: 0x154 Endpoint G Data Register for Byte Access
<> 144:ef7eb2e8f9f7 29636 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29637 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29638 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29639 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 29640 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 29641 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 29642 */
<> 144:ef7eb2e8f9f7 29643 __IO uint8_t EPGDAT_BYTE;
<> 144:ef7eb2e8f9f7 29644
<> 144:ef7eb2e8f9f7 29645 }; ///< Define EPG Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 29646
<> 144:ef7eb2e8f9f7 29647 /**
<> 144:ef7eb2e8f9f7 29648 * EPGINTSTS
<> 144:ef7eb2e8f9f7 29649 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29650 * Offset: 0x158 Endpoint G Interrupt Status Register
<> 144:ef7eb2e8f9f7 29651 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29652 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29653 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29654 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 29655 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 29656 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 29657 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 29658 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 29659 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 29660 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 29661 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 29662 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 29663 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 29664 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 29665 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 29666 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 29667 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 29668 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 29669 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 29670 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 29671 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29672 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 29673 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 29674 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 29675 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29676 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 29677 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 29678 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 29679 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29680 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 29681 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 29682 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 29683 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 29684 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29685 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 29686 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29687 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29688 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29689 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 29690 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 29691 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 29692 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29693 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 29694 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 29695 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 29696 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29697 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 29698 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 29699 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 29700 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29701 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 29702 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 29703 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 29704 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29705 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 29706 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 29707 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 29708 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29709 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 29710 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 29711 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 29712 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29713 */
<> 144:ef7eb2e8f9f7 29714 __IO uint32_t EPGINTSTS;
<> 144:ef7eb2e8f9f7 29715
<> 144:ef7eb2e8f9f7 29716 /**
<> 144:ef7eb2e8f9f7 29717 * EPGINTEN
<> 144:ef7eb2e8f9f7 29718 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29719 * Offset: 0x15C Endpoint G Interrupt Enable Register
<> 144:ef7eb2e8f9f7 29720 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29721 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29722 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29723 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 29724 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 29725 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 29726 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 29727 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 29728 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 29729 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 29730 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 29731 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29732 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 29733 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 29734 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 29735 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29736 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 29737 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 29738 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 29739 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29740 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 29741 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 29742 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 29743 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29744 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 29745 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29746 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29747 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29748 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29749 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29750 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29751 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29752 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 29753 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29754 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29755 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29756 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 29757 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29758 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29759 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29760 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 29761 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 29762 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 29763 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29764 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29765 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 29766 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 29767 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29768 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29769 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 29770 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 29771 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 29772 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 29773 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 29774 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 29775 */
<> 144:ef7eb2e8f9f7 29776 __IO uint32_t EPGINTEN;
<> 144:ef7eb2e8f9f7 29777
<> 144:ef7eb2e8f9f7 29778 /**
<> 144:ef7eb2e8f9f7 29779 * EPGDATCNT
<> 144:ef7eb2e8f9f7 29780 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29781 * Offset: 0x160 Endpoint G Data Available Count Register
<> 144:ef7eb2e8f9f7 29782 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29783 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29784 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29785 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 29786 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 29787 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 29788 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 29789 */
<> 144:ef7eb2e8f9f7 29790 __I uint32_t EPGDATCNT;
<> 144:ef7eb2e8f9f7 29791
<> 144:ef7eb2e8f9f7 29792 /**
<> 144:ef7eb2e8f9f7 29793 * EPGRSPCTL
<> 144:ef7eb2e8f9f7 29794 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29795 * Offset: 0x164 Endpoint G Response Control Register
<> 144:ef7eb2e8f9f7 29796 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29797 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29798 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29799 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 29800 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 29801 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 29802 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 29803 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 29804 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 29805 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 29806 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 29807 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 29808 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 29809 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 29810 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 29811 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 29812 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 29813 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 29814 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29815 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29816 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 29817 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 29818 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29819 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 29820 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 29821 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29822 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 29823 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29824 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 29825 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 29826 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 29827 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29828 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29829 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 29830 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 29831 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 29832 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 29833 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 29834 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 29835 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 29836 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29837 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29838 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 29839 */
<> 144:ef7eb2e8f9f7 29840 __IO uint32_t EPGRSPCTL;
<> 144:ef7eb2e8f9f7 29841
<> 144:ef7eb2e8f9f7 29842 /**
<> 144:ef7eb2e8f9f7 29843 * EPGMPS
<> 144:ef7eb2e8f9f7 29844 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29845 * Offset: 0x168 Endpoint G Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 29846 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29847 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29848 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29849 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 29850 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 29851 */
<> 144:ef7eb2e8f9f7 29852 __IO uint32_t EPGMPS;
<> 144:ef7eb2e8f9f7 29853
<> 144:ef7eb2e8f9f7 29854 /**
<> 144:ef7eb2e8f9f7 29855 * EPGTXCNT
<> 144:ef7eb2e8f9f7 29856 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29857 * Offset: 0x16C Endpoint G Transfer Count Register
<> 144:ef7eb2e8f9f7 29858 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29859 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29860 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29861 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 29862 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 29863 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 29864 */
<> 144:ef7eb2e8f9f7 29865 __IO uint32_t EPGTXCNT;
<> 144:ef7eb2e8f9f7 29866
<> 144:ef7eb2e8f9f7 29867 /**
<> 144:ef7eb2e8f9f7 29868 * EPGCFG
<> 144:ef7eb2e8f9f7 29869 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29870 * Offset: 0x170 Endpoint G Configuration Register
<> 144:ef7eb2e8f9f7 29871 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29872 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29873 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29874 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 29875 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 29876 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 29877 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 29878 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 29879 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 29880 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 29881 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 29882 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 29883 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 29884 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 29885 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 29886 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 29887 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 29888 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 29889 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 29890 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 29891 */
<> 144:ef7eb2e8f9f7 29892 __IO uint32_t EPGCFG;
<> 144:ef7eb2e8f9f7 29893
<> 144:ef7eb2e8f9f7 29894 /**
<> 144:ef7eb2e8f9f7 29895 * EPGBUFSTART
<> 144:ef7eb2e8f9f7 29896 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29897 * Offset: 0x174 Endpoint G RAM Start Address Register
<> 144:ef7eb2e8f9f7 29898 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29899 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29900 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29901 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 29902 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 29903 */
<> 144:ef7eb2e8f9f7 29904 __IO uint32_t EPGBUFSTART;
<> 144:ef7eb2e8f9f7 29905
<> 144:ef7eb2e8f9f7 29906 /**
<> 144:ef7eb2e8f9f7 29907 * EPGBUFEND
<> 144:ef7eb2e8f9f7 29908 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29909 * Offset: 0x178 Endpoint G RAM End Address Register
<> 144:ef7eb2e8f9f7 29910 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29911 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29912 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29913 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 29914 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 29915 */
<> 144:ef7eb2e8f9f7 29916 __IO uint32_t EPGBUFEND;
<> 144:ef7eb2e8f9f7 29917
<> 144:ef7eb2e8f9f7 29918 union {
<> 144:ef7eb2e8f9f7 29919
<> 144:ef7eb2e8f9f7 29920 /**
<> 144:ef7eb2e8f9f7 29921 * EPHDAT
<> 144:ef7eb2e8f9f7 29922 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29923 * Offset: 0x17C Endpoint H Data Register
<> 144:ef7eb2e8f9f7 29924 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29925 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29926 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29927 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 29928 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 29929 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 29930 */
<> 144:ef7eb2e8f9f7 29931 __IO uint32_t EPHDAT;
<> 144:ef7eb2e8f9f7 29932 /**
<> 144:ef7eb2e8f9f7 29933 * EPHDAT_BYTE
<> 144:ef7eb2e8f9f7 29934 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29935 * Offset: 0x17C Endpoint H Data Register for Byte Access
<> 144:ef7eb2e8f9f7 29936 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29937 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29938 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29939 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 29940 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 29941 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 29942 */
<> 144:ef7eb2e8f9f7 29943 __IO uint8_t EPHDAT_BYTE;
<> 144:ef7eb2e8f9f7 29944
<> 144:ef7eb2e8f9f7 29945 }; ///< Define EPH Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 29946
<> 144:ef7eb2e8f9f7 29947 /**
<> 144:ef7eb2e8f9f7 29948 * EPHINTSTS
<> 144:ef7eb2e8f9f7 29949 * ===================================================================================================
<> 144:ef7eb2e8f9f7 29950 * Offset: 0x180 Endpoint H Interrupt Status Register
<> 144:ef7eb2e8f9f7 29951 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 29952 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 29953 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 29954 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 29955 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 29956 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 29957 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 29958 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 29959 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 29960 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 29961 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 29962 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 29963 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 29964 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 29965 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 29966 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 29967 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 29968 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 29969 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 29970 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 29971 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29972 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 29973 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 29974 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 29975 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29976 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 29977 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 29978 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 29979 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29980 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 29981 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 29982 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 29983 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 29984 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29985 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 29986 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29987 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 29988 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29989 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 29990 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 29991 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 29992 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29993 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 29994 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 29995 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 29996 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 29997 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 29998 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 29999 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 30000 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30001 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 30002 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 30003 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 30004 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30005 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 30006 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 30007 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 30008 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30009 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 30010 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 30011 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 30012 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30013 */
<> 144:ef7eb2e8f9f7 30014 __IO uint32_t EPHINTSTS;
<> 144:ef7eb2e8f9f7 30015
<> 144:ef7eb2e8f9f7 30016 /**
<> 144:ef7eb2e8f9f7 30017 * EPHINTEN
<> 144:ef7eb2e8f9f7 30018 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30019 * Offset: 0x184 Endpoint H Interrupt Enable Register
<> 144:ef7eb2e8f9f7 30020 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30021 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30022 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30023 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 30024 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 30025 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 30026 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 30027 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 30028 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 30029 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 30030 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 30031 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30032 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 30033 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 30034 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 30035 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30036 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 30037 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 30038 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 30039 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30040 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 30041 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 30042 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 30043 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30044 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 30045 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30046 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30047 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30048 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30049 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30050 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30051 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30052 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 30053 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30054 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30055 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30056 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 30057 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30058 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30059 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30060 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 30061 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30062 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30063 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30064 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30065 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 30066 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 30067 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30068 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30069 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 30070 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 30071 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30072 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30073 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 30074 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 30075 */
<> 144:ef7eb2e8f9f7 30076 __IO uint32_t EPHINTEN;
<> 144:ef7eb2e8f9f7 30077
<> 144:ef7eb2e8f9f7 30078 /**
<> 144:ef7eb2e8f9f7 30079 * EPHDATCNT
<> 144:ef7eb2e8f9f7 30080 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30081 * Offset: 0x188 Endpoint H Data Available Count Register
<> 144:ef7eb2e8f9f7 30082 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30083 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30084 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30085 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 30086 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 30087 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 30088 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 30089 */
<> 144:ef7eb2e8f9f7 30090 __I uint32_t EPHDATCNT;
<> 144:ef7eb2e8f9f7 30091
<> 144:ef7eb2e8f9f7 30092 /**
<> 144:ef7eb2e8f9f7 30093 * EPHRSPCTL
<> 144:ef7eb2e8f9f7 30094 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30095 * Offset: 0x18C Endpoint H Response Control Register
<> 144:ef7eb2e8f9f7 30096 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30097 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30098 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30099 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 30100 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 30101 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 30102 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 30103 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 30104 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 30105 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 30106 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 30107 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 30108 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 30109 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 30110 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 30111 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 30112 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 30113 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 30114 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30115 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30116 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 30117 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 30118 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30119 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30120 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 30121 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30122 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 30123 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30124 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30125 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 30126 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 30127 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30128 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30129 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30130 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 30131 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 30132 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 30133 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 30134 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 30135 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 30136 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30137 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30138 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30139 */
<> 144:ef7eb2e8f9f7 30140 __IO uint32_t EPHRSPCTL;
<> 144:ef7eb2e8f9f7 30141
<> 144:ef7eb2e8f9f7 30142 /**
<> 144:ef7eb2e8f9f7 30143 * EPHMPS
<> 144:ef7eb2e8f9f7 30144 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30145 * Offset: 0x190 Endpoint H Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 30146 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30147 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30148 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30149 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 30150 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 30151 */
<> 144:ef7eb2e8f9f7 30152 __IO uint32_t EPHMPS;
<> 144:ef7eb2e8f9f7 30153
<> 144:ef7eb2e8f9f7 30154 /**
<> 144:ef7eb2e8f9f7 30155 * EPHTXCNT
<> 144:ef7eb2e8f9f7 30156 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30157 * Offset: 0x194 Endpoint H Transfer Count Register
<> 144:ef7eb2e8f9f7 30158 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30159 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30160 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30161 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 30162 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 30163 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 30164 */
<> 144:ef7eb2e8f9f7 30165 __IO uint32_t EPHTXCNT;
<> 144:ef7eb2e8f9f7 30166
<> 144:ef7eb2e8f9f7 30167 /**
<> 144:ef7eb2e8f9f7 30168 * EPHCFG
<> 144:ef7eb2e8f9f7 30169 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30170 * Offset: 0x198 Endpoint H Configuration Register
<> 144:ef7eb2e8f9f7 30171 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30172 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30173 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30174 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 30175 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 30176 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 30177 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 30178 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 30179 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 30180 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 30181 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 30182 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 30183 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 30184 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 30185 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 30186 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 30187 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 30188 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 30189 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 30190 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 30191 */
<> 144:ef7eb2e8f9f7 30192 __IO uint32_t EPHCFG;
<> 144:ef7eb2e8f9f7 30193
<> 144:ef7eb2e8f9f7 30194 /**
<> 144:ef7eb2e8f9f7 30195 * EPHBUFSTART
<> 144:ef7eb2e8f9f7 30196 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30197 * Offset: 0x19C Endpoint H RAM Start Address Register
<> 144:ef7eb2e8f9f7 30198 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30199 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30200 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30201 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 30202 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 30203 */
<> 144:ef7eb2e8f9f7 30204 __IO uint32_t EPHBUFSTART;
<> 144:ef7eb2e8f9f7 30205
<> 144:ef7eb2e8f9f7 30206 /**
<> 144:ef7eb2e8f9f7 30207 * EPHBUFEND
<> 144:ef7eb2e8f9f7 30208 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30209 * Offset: 0x1A0 Endpoint H RAM End Address Register
<> 144:ef7eb2e8f9f7 30210 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30211 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30212 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30213 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 30214 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 30215 */
<> 144:ef7eb2e8f9f7 30216 __IO uint32_t EPHBUFEND;
<> 144:ef7eb2e8f9f7 30217
<> 144:ef7eb2e8f9f7 30218 union {
<> 144:ef7eb2e8f9f7 30219
<> 144:ef7eb2e8f9f7 30220 /**
<> 144:ef7eb2e8f9f7 30221 * EPIDAT
<> 144:ef7eb2e8f9f7 30222 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30223 * Offset: 0x1A4 Endpoint I Data Register
<> 144:ef7eb2e8f9f7 30224 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30225 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30226 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30227 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 30228 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 30229 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 30230 */
<> 144:ef7eb2e8f9f7 30231 __IO uint32_t EPIDAT;
<> 144:ef7eb2e8f9f7 30232 /**
<> 144:ef7eb2e8f9f7 30233 * EPIDAT_BYTE
<> 144:ef7eb2e8f9f7 30234 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30235 * Offset: 0x1A4 Endpoint I Data Register for Byte Access
<> 144:ef7eb2e8f9f7 30236 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30237 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30238 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30239 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 30240 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 30241 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 30242 */
<> 144:ef7eb2e8f9f7 30243 __IO uint8_t EPIDAT_BYTE;
<> 144:ef7eb2e8f9f7 30244
<> 144:ef7eb2e8f9f7 30245 }; ///< Define EPI Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 30246
<> 144:ef7eb2e8f9f7 30247 /**
<> 144:ef7eb2e8f9f7 30248 * EPIINTSTS
<> 144:ef7eb2e8f9f7 30249 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30250 * Offset: 0x1A8 Endpoint I Interrupt Status Register
<> 144:ef7eb2e8f9f7 30251 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30252 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30253 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30254 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 30255 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 30256 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 30257 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 30258 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 30259 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 30260 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 30261 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 30262 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 30263 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 30264 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 30265 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 30266 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 30267 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 30268 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 30269 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 30270 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 30271 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30272 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 30273 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 30274 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 30275 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30276 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 30277 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 30278 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 30279 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30280 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 30281 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 30282 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 30283 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 30284 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30285 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 30286 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30287 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30288 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30289 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 30290 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 30291 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 30292 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30293 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 30294 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 30295 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 30296 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30297 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 30298 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 30299 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 30300 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30301 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 30302 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 30303 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 30304 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30305 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 30306 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 30307 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 30308 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30309 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 30310 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 30311 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 30312 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30313 */
<> 144:ef7eb2e8f9f7 30314 __IO uint32_t EPIINTSTS;
<> 144:ef7eb2e8f9f7 30315
<> 144:ef7eb2e8f9f7 30316 /**
<> 144:ef7eb2e8f9f7 30317 * EPIINTEN
<> 144:ef7eb2e8f9f7 30318 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30319 * Offset: 0x1AC Endpoint I Interrupt Enable Register
<> 144:ef7eb2e8f9f7 30320 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30321 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30322 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30323 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 30324 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 30325 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 30326 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 30327 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 30328 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 30329 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 30330 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 30331 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30332 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 30333 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 30334 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 30335 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30336 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 30337 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 30338 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 30339 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30340 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 30341 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 30342 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 30343 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30344 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 30345 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30346 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30347 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30348 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30349 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30350 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30351 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30352 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 30353 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30354 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30355 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30356 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 30357 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30358 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30359 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30360 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 30361 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30362 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30363 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30364 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30365 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 30366 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 30367 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30368 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30369 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 30370 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 30371 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30372 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30373 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 30374 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 30375 */
<> 144:ef7eb2e8f9f7 30376 __IO uint32_t EPIINTEN;
<> 144:ef7eb2e8f9f7 30377
<> 144:ef7eb2e8f9f7 30378 /**
<> 144:ef7eb2e8f9f7 30379 * EPIDATCNT
<> 144:ef7eb2e8f9f7 30380 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30381 * Offset: 0x1B0 Endpoint I Data Available Count Register
<> 144:ef7eb2e8f9f7 30382 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30383 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30384 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30385 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 30386 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 30387 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 30388 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 30389 */
<> 144:ef7eb2e8f9f7 30390 __I uint32_t EPIDATCNT;
<> 144:ef7eb2e8f9f7 30391
<> 144:ef7eb2e8f9f7 30392 /**
<> 144:ef7eb2e8f9f7 30393 * EPIRSPCTL
<> 144:ef7eb2e8f9f7 30394 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30395 * Offset: 0x1B4 Endpoint I Response Control Register
<> 144:ef7eb2e8f9f7 30396 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30397 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30398 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30399 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 30400 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 30401 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 30402 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 30403 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 30404 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 30405 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 30406 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 30407 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 30408 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 30409 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 30410 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 30411 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 30412 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 30413 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 30414 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30415 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30416 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 30417 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 30418 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30419 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30420 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 30421 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30422 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 30423 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30424 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30425 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 30426 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 30427 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30428 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30429 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30430 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 30431 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 30432 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 30433 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 30434 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 30435 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 30436 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30437 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30438 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30439 */
<> 144:ef7eb2e8f9f7 30440 __IO uint32_t EPIRSPCTL;
<> 144:ef7eb2e8f9f7 30441
<> 144:ef7eb2e8f9f7 30442 /**
<> 144:ef7eb2e8f9f7 30443 * EPIMPS
<> 144:ef7eb2e8f9f7 30444 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30445 * Offset: 0x1B8 Endpoint I Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 30446 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30447 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30448 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30449 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 30450 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 30451 */
<> 144:ef7eb2e8f9f7 30452 __IO uint32_t EPIMPS;
<> 144:ef7eb2e8f9f7 30453
<> 144:ef7eb2e8f9f7 30454 /**
<> 144:ef7eb2e8f9f7 30455 * EPITXCNT
<> 144:ef7eb2e8f9f7 30456 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30457 * Offset: 0x1BC Endpoint I Transfer Count Register
<> 144:ef7eb2e8f9f7 30458 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30459 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30460 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30461 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 30462 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 30463 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 30464 */
<> 144:ef7eb2e8f9f7 30465 __IO uint32_t EPITXCNT;
<> 144:ef7eb2e8f9f7 30466
<> 144:ef7eb2e8f9f7 30467 /**
<> 144:ef7eb2e8f9f7 30468 * EPICFG
<> 144:ef7eb2e8f9f7 30469 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30470 * Offset: 0x1C0 Endpoint I Configuration Register
<> 144:ef7eb2e8f9f7 30471 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30472 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30473 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30474 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 30475 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 30476 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 30477 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 30478 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 30479 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 30480 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 30481 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 30482 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 30483 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 30484 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 30485 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 30486 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 30487 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 30488 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 30489 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 30490 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 30491 */
<> 144:ef7eb2e8f9f7 30492 __IO uint32_t EPICFG;
<> 144:ef7eb2e8f9f7 30493
<> 144:ef7eb2e8f9f7 30494 /**
<> 144:ef7eb2e8f9f7 30495 * EPIBUFSTART
<> 144:ef7eb2e8f9f7 30496 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30497 * Offset: 0x1C4 Endpoint I RAM Start Address Register
<> 144:ef7eb2e8f9f7 30498 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30499 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30500 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30501 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 30502 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 30503 */
<> 144:ef7eb2e8f9f7 30504 __IO uint32_t EPIBUFSTART;
<> 144:ef7eb2e8f9f7 30505
<> 144:ef7eb2e8f9f7 30506 /**
<> 144:ef7eb2e8f9f7 30507 * EPIBUFEND
<> 144:ef7eb2e8f9f7 30508 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30509 * Offset: 0x1C8 Endpoint I RAM End Address Register
<> 144:ef7eb2e8f9f7 30510 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30511 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30512 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30513 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 30514 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 30515 */
<> 144:ef7eb2e8f9f7 30516 __IO uint32_t EPIBUFEND;
<> 144:ef7eb2e8f9f7 30517
<> 144:ef7eb2e8f9f7 30518 union {
<> 144:ef7eb2e8f9f7 30519
<> 144:ef7eb2e8f9f7 30520 /**
<> 144:ef7eb2e8f9f7 30521 * EPJDAT
<> 144:ef7eb2e8f9f7 30522 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30523 * Offset: 0x1CC Endpoint J Data Register
<> 144:ef7eb2e8f9f7 30524 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30525 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30526 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30527 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 30528 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 30529 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 30530 */
<> 144:ef7eb2e8f9f7 30531 __IO uint32_t EPJDAT;
<> 144:ef7eb2e8f9f7 30532 /**
<> 144:ef7eb2e8f9f7 30533 * EPJDAT_BYTE
<> 144:ef7eb2e8f9f7 30534 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30535 * Offset: 0x1CC Endpoint J Data Register for Byte Access
<> 144:ef7eb2e8f9f7 30536 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30537 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30538 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30539 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 30540 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 30541 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 30542 */
<> 144:ef7eb2e8f9f7 30543 __IO uint8_t EPJDAT_BYTE;
<> 144:ef7eb2e8f9f7 30544
<> 144:ef7eb2e8f9f7 30545 }; ///< Define EPJ Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 30546
<> 144:ef7eb2e8f9f7 30547 /**
<> 144:ef7eb2e8f9f7 30548 * EPJINTSTS
<> 144:ef7eb2e8f9f7 30549 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30550 * Offset: 0x1D0 Endpoint J Interrupt Status Register
<> 144:ef7eb2e8f9f7 30551 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30552 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30553 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30554 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 30555 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 30556 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 30557 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 30558 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 30559 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 30560 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 30561 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 30562 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 30563 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 30564 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 30565 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 30566 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 30567 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 30568 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 30569 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 30570 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 30571 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30572 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 30573 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 30574 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 30575 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30576 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 30577 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 30578 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 30579 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30580 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 30581 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 30582 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 30583 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 30584 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30585 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 30586 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30587 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30588 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30589 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 30590 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 30591 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 30592 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30593 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 30594 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 30595 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 30596 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30597 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 30598 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 30599 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 30600 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30601 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 30602 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 30603 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 30604 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30605 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 30606 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 30607 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 30608 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30609 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 30610 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 30611 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 30612 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30613 */
<> 144:ef7eb2e8f9f7 30614 __IO uint32_t EPJINTSTS;
<> 144:ef7eb2e8f9f7 30615
<> 144:ef7eb2e8f9f7 30616 /**
<> 144:ef7eb2e8f9f7 30617 * EPJINTEN
<> 144:ef7eb2e8f9f7 30618 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30619 * Offset: 0x1D4 Endpoint J Interrupt Enable Register
<> 144:ef7eb2e8f9f7 30620 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30621 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30622 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30623 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 30624 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 30625 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 30626 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 30627 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 30628 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 30629 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 30630 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 30631 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30632 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 30633 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 30634 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 30635 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30636 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 30637 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 30638 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 30639 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30640 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 30641 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 30642 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 30643 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30644 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 30645 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30646 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30647 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30648 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30649 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30650 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30651 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30652 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 30653 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30654 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30655 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30656 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 30657 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30658 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30659 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30660 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 30661 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30662 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30663 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30664 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30665 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 30666 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 30667 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30668 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30669 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 30670 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 30671 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30672 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30673 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 30674 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 30675 */
<> 144:ef7eb2e8f9f7 30676 __IO uint32_t EPJINTEN;
<> 144:ef7eb2e8f9f7 30677
<> 144:ef7eb2e8f9f7 30678 /**
<> 144:ef7eb2e8f9f7 30679 * EPJDATCNT
<> 144:ef7eb2e8f9f7 30680 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30681 * Offset: 0x1D8 Endpoint J Data Available Count Register
<> 144:ef7eb2e8f9f7 30682 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30683 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30684 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30685 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 30686 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 30687 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 30688 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 30689 */
<> 144:ef7eb2e8f9f7 30690 __I uint32_t EPJDATCNT;
<> 144:ef7eb2e8f9f7 30691
<> 144:ef7eb2e8f9f7 30692 /**
<> 144:ef7eb2e8f9f7 30693 * EPJRSPCTL
<> 144:ef7eb2e8f9f7 30694 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30695 * Offset: 0x1DC Endpoint J Response Control Register
<> 144:ef7eb2e8f9f7 30696 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30697 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30698 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30699 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 30700 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 30701 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 30702 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 30703 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 30704 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 30705 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 30706 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 30707 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 30708 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 30709 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 30710 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 30711 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 30712 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 30713 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 30714 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30715 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30716 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 30717 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 30718 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30719 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 30720 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 30721 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30722 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 30723 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30724 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 30725 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 30726 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 30727 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30728 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30729 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 30730 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 30731 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 30732 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 30733 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 30734 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 30735 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 30736 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30737 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30738 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 30739 */
<> 144:ef7eb2e8f9f7 30740 __IO uint32_t EPJRSPCTL;
<> 144:ef7eb2e8f9f7 30741
<> 144:ef7eb2e8f9f7 30742 /**
<> 144:ef7eb2e8f9f7 30743 * EPJMPS
<> 144:ef7eb2e8f9f7 30744 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30745 * Offset: 0x1E0 Endpoint J Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 30746 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30747 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30748 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30749 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 30750 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 30751 */
<> 144:ef7eb2e8f9f7 30752 __IO uint32_t EPJMPS;
<> 144:ef7eb2e8f9f7 30753
<> 144:ef7eb2e8f9f7 30754 /**
<> 144:ef7eb2e8f9f7 30755 * EPJTXCNT
<> 144:ef7eb2e8f9f7 30756 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30757 * Offset: 0x1E4 Endpoint J Transfer Count Register
<> 144:ef7eb2e8f9f7 30758 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30759 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30760 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30761 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 30762 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 30763 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 30764 */
<> 144:ef7eb2e8f9f7 30765 __IO uint32_t EPJTXCNT;
<> 144:ef7eb2e8f9f7 30766
<> 144:ef7eb2e8f9f7 30767 /**
<> 144:ef7eb2e8f9f7 30768 * EPJCFG
<> 144:ef7eb2e8f9f7 30769 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30770 * Offset: 0x1E8 Endpoint J Configuration Register
<> 144:ef7eb2e8f9f7 30771 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30772 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30773 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30774 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 30775 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 30776 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 30777 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 30778 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 30779 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 30780 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 30781 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 30782 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 30783 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 30784 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 30785 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 30786 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 30787 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 30788 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 30789 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 30790 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 30791 */
<> 144:ef7eb2e8f9f7 30792 __IO uint32_t EPJCFG;
<> 144:ef7eb2e8f9f7 30793
<> 144:ef7eb2e8f9f7 30794 /**
<> 144:ef7eb2e8f9f7 30795 * EPJBUFSTART
<> 144:ef7eb2e8f9f7 30796 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30797 * Offset: 0x1EC Endpoint J RAM Start Address Register
<> 144:ef7eb2e8f9f7 30798 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30799 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30800 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30801 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 30802 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 30803 */
<> 144:ef7eb2e8f9f7 30804 __IO uint32_t EPJBUFSTART;
<> 144:ef7eb2e8f9f7 30805
<> 144:ef7eb2e8f9f7 30806 /**
<> 144:ef7eb2e8f9f7 30807 * EPJBUFEND
<> 144:ef7eb2e8f9f7 30808 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30809 * Offset: 0x1F0 Endpoint J RAM End Address Register
<> 144:ef7eb2e8f9f7 30810 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30811 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30812 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30813 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 30814 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 30815 */
<> 144:ef7eb2e8f9f7 30816 __IO uint32_t EPJBUFEND;
<> 144:ef7eb2e8f9f7 30817
<> 144:ef7eb2e8f9f7 30818 union {
<> 144:ef7eb2e8f9f7 30819
<> 144:ef7eb2e8f9f7 30820 /**
<> 144:ef7eb2e8f9f7 30821 * EPKDAT
<> 144:ef7eb2e8f9f7 30822 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30823 * Offset: 0x1F4 Endpoint K Data Register
<> 144:ef7eb2e8f9f7 30824 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30825 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30826 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30827 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 30828 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 30829 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 30830 */
<> 144:ef7eb2e8f9f7 30831 __IO uint32_t EPKDAT;
<> 144:ef7eb2e8f9f7 30832 /**
<> 144:ef7eb2e8f9f7 30833 * EPKDAT_BYTE
<> 144:ef7eb2e8f9f7 30834 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30835 * Offset: 0x1F4 Endpoint K Data Register for Byte Access
<> 144:ef7eb2e8f9f7 30836 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30837 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30838 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30839 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 30840 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 30841 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 30842 */
<> 144:ef7eb2e8f9f7 30843 __IO uint8_t EPKDAT_BYTE;
<> 144:ef7eb2e8f9f7 30844
<> 144:ef7eb2e8f9f7 30845 }; ///< Define EPK Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 30846
<> 144:ef7eb2e8f9f7 30847 /**
<> 144:ef7eb2e8f9f7 30848 * EPKINTSTS
<> 144:ef7eb2e8f9f7 30849 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30850 * Offset: 0x1F8 Endpoint K Interrupt Status Register
<> 144:ef7eb2e8f9f7 30851 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30852 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30853 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30854 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 30855 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 30856 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 30857 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 30858 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 30859 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 30860 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 30861 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 30862 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 30863 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 30864 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 30865 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 30866 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 30867 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 30868 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 30869 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 30870 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 30871 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30872 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 30873 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 30874 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 30875 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30876 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 30877 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 30878 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 30879 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30880 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 30881 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 30882 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 30883 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 30884 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30885 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 30886 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30887 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30888 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30889 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 30890 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 30891 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 30892 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30893 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 30894 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 30895 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 30896 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30897 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 30898 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 30899 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 30900 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30901 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 30902 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 30903 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 30904 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30905 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 30906 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 30907 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 30908 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30909 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 30910 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 30911 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 30912 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 30913 */
<> 144:ef7eb2e8f9f7 30914 __IO uint32_t EPKINTSTS;
<> 144:ef7eb2e8f9f7 30915
<> 144:ef7eb2e8f9f7 30916 /**
<> 144:ef7eb2e8f9f7 30917 * EPKINTEN
<> 144:ef7eb2e8f9f7 30918 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30919 * Offset: 0x1FC Endpoint K Interrupt Enable Register
<> 144:ef7eb2e8f9f7 30920 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30921 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30922 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30923 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 30924 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 30925 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 30926 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 30927 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 30928 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 30929 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 30930 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 30931 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30932 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 30933 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 30934 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 30935 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30936 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 30937 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 30938 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 30939 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30940 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 30941 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 30942 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 30943 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30944 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 30945 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30946 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30947 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30948 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 30949 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30950 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30951 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30952 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 30953 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30954 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30955 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30956 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 30957 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30958 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30959 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30960 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 30961 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 30962 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 30963 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30964 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30965 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 30966 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 30967 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30968 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30969 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 30970 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 30971 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 30972 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 30973 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 30974 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 30975 */
<> 144:ef7eb2e8f9f7 30976 __IO uint32_t EPKINTEN;
<> 144:ef7eb2e8f9f7 30977
<> 144:ef7eb2e8f9f7 30978 /**
<> 144:ef7eb2e8f9f7 30979 * EPKDATCNT
<> 144:ef7eb2e8f9f7 30980 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30981 * Offset: 0x200 Endpoint K Data Available Count Register
<> 144:ef7eb2e8f9f7 30982 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30983 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30984 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30985 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 30986 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 30987 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 30988 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 30989 */
<> 144:ef7eb2e8f9f7 30990 __I uint32_t EPKDATCNT;
<> 144:ef7eb2e8f9f7 30991
<> 144:ef7eb2e8f9f7 30992 /**
<> 144:ef7eb2e8f9f7 30993 * EPKRSPCTL
<> 144:ef7eb2e8f9f7 30994 * ===================================================================================================
<> 144:ef7eb2e8f9f7 30995 * Offset: 0x204 Endpoint K Response Control Register
<> 144:ef7eb2e8f9f7 30996 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 30997 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 30998 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 30999 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 31000 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 31001 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 31002 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 31003 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 31004 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 31005 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 31006 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 31007 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 31008 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 31009 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 31010 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 31011 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 31012 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 31013 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 31014 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 31015 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 31016 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 31017 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 31018 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 31019 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 31020 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 31021 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 31022 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 31023 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 31024 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 31025 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 31026 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 31027 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 31028 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 31029 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 31030 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 31031 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 31032 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 31033 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 31034 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 31035 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 31036 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 31037 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 31038 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 31039 */
<> 144:ef7eb2e8f9f7 31040 __IO uint32_t EPKRSPCTL;
<> 144:ef7eb2e8f9f7 31041
<> 144:ef7eb2e8f9f7 31042 /**
<> 144:ef7eb2e8f9f7 31043 * EPKMPS
<> 144:ef7eb2e8f9f7 31044 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31045 * Offset: 0x208 Endpoint K Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 31046 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31047 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31048 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31049 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 31050 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 31051 */
<> 144:ef7eb2e8f9f7 31052 __IO uint32_t EPKMPS;
<> 144:ef7eb2e8f9f7 31053
<> 144:ef7eb2e8f9f7 31054 /**
<> 144:ef7eb2e8f9f7 31055 * EPKTXCNT
<> 144:ef7eb2e8f9f7 31056 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31057 * Offset: 0x20C Endpoint K Transfer Count Register
<> 144:ef7eb2e8f9f7 31058 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31059 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31060 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31061 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 31062 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 31063 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 31064 */
<> 144:ef7eb2e8f9f7 31065 __IO uint32_t EPKTXCNT;
<> 144:ef7eb2e8f9f7 31066
<> 144:ef7eb2e8f9f7 31067 /**
<> 144:ef7eb2e8f9f7 31068 * EPKCFG
<> 144:ef7eb2e8f9f7 31069 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31070 * Offset: 0x210 Endpoint K Configuration Register
<> 144:ef7eb2e8f9f7 31071 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31072 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31073 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31074 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 31075 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 31076 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 31077 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 31078 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 31079 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 31080 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 31081 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 31082 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 31083 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 31084 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 31085 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 31086 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 31087 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 31088 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 31089 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 31090 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 31091 */
<> 144:ef7eb2e8f9f7 31092 __IO uint32_t EPKCFG;
<> 144:ef7eb2e8f9f7 31093
<> 144:ef7eb2e8f9f7 31094 /**
<> 144:ef7eb2e8f9f7 31095 * EPKBUFSTART
<> 144:ef7eb2e8f9f7 31096 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31097 * Offset: 0x214 Endpoint K RAM Start Address Register
<> 144:ef7eb2e8f9f7 31098 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31099 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31100 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31101 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 31102 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 31103 */
<> 144:ef7eb2e8f9f7 31104 __IO uint32_t EPKBUFSTART;
<> 144:ef7eb2e8f9f7 31105
<> 144:ef7eb2e8f9f7 31106 /**
<> 144:ef7eb2e8f9f7 31107 * EPKBUFEND
<> 144:ef7eb2e8f9f7 31108 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31109 * Offset: 0x218 Endpoint K RAM End Address Register
<> 144:ef7eb2e8f9f7 31110 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31111 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31112 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31113 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 31114 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 31115 */
<> 144:ef7eb2e8f9f7 31116 __IO uint32_t EPKBUFEND;
<> 144:ef7eb2e8f9f7 31117
<> 144:ef7eb2e8f9f7 31118 union {
<> 144:ef7eb2e8f9f7 31119
<> 144:ef7eb2e8f9f7 31120 /**
<> 144:ef7eb2e8f9f7 31121 * EPLDAT
<> 144:ef7eb2e8f9f7 31122 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31123 * Offset: 0x21C Endpoint L Data Register
<> 144:ef7eb2e8f9f7 31124 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31125 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31126 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31127 * |[0:31] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 31128 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 31129 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 31130 */
<> 144:ef7eb2e8f9f7 31131 __IO uint32_t EPLDAT;
<> 144:ef7eb2e8f9f7 31132 /**
<> 144:ef7eb2e8f9f7 31133 * EPLDAT_BYTE
<> 144:ef7eb2e8f9f7 31134 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31135 * Offset: 0x21C Endpoint L Data Register for Byte Access
<> 144:ef7eb2e8f9f7 31136 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31137 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31138 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31139 * |[0:7] |EPDAT |Endpoint A~L Data Register
<> 144:ef7eb2e8f9f7 31140 * | | |Endpoint A~L data buffer for the buffer transaction (read or write).
<> 144:ef7eb2e8f9f7 31141 * | | |Note: Only word or byte access are supported.
<> 144:ef7eb2e8f9f7 31142 */
<> 144:ef7eb2e8f9f7 31143 __IO uint8_t EPLDAT_BYTE;
<> 144:ef7eb2e8f9f7 31144
<> 144:ef7eb2e8f9f7 31145 }; ///< Define EPL Data Register 32-bit or 8-bit access
<> 144:ef7eb2e8f9f7 31146
<> 144:ef7eb2e8f9f7 31147 /**
<> 144:ef7eb2e8f9f7 31148 * EPLINTSTS
<> 144:ef7eb2e8f9f7 31149 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31150 * Offset: 0x220 Endpoint L Interrupt Status Register
<> 144:ef7eb2e8f9f7 31151 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31152 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31153 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31154 * |[0] |BUFFULLIF |Buffer Full
<> 144:ef7eb2e8f9f7 31155 * | | |For an IN endpoint, the currently selected buffer is full, or no buffer is available to the local side for writing (no space to write).
<> 144:ef7eb2e8f9f7 31156 * | | |For an OUT endpoint, there is a buffer available on the local side, and there are FIFO full of bytes available to be read (entire packet is available for reading).
<> 144:ef7eb2e8f9f7 31157 * | | |0 = The endpoint packet buffer is not full.
<> 144:ef7eb2e8f9f7 31158 * | | |1 = The endpoint packet buffer is full.
<> 144:ef7eb2e8f9f7 31159 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 31160 * |[1] |BUFEMPTYIF|Buffer Empty
<> 144:ef7eb2e8f9f7 31161 * | | |For an IN endpoint, a buffer is available to the local side for writing up to FIFO full of bytes.
<> 144:ef7eb2e8f9f7 31162 * | | |0 = The endpoint buffer is not empty.
<> 144:ef7eb2e8f9f7 31163 * | | |1 = The endpoint buffer is empty.
<> 144:ef7eb2e8f9f7 31164 * | | |For an OUT endpoint:
<> 144:ef7eb2e8f9f7 31165 * | | |0 = The currently selected buffer has not a count of 0.
<> 144:ef7eb2e8f9f7 31166 * | | |1 = The currently selected buffer has a count of 0, or no buffer is available on the local side (nothing to read).
<> 144:ef7eb2e8f9f7 31167 * | | |Note: This bit is read-only.
<> 144:ef7eb2e8f9f7 31168 * |[2] |SHORTTXIF |Short Packet Transferred Interrupt
<> 144:ef7eb2e8f9f7 31169 * | | |0 = The length of the last packet was not less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 31170 * | | |1 = The length of the last packet was less than the Maximum Packet Size (EPMPS).
<> 144:ef7eb2e8f9f7 31171 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31172 * |[3] |TXPKIF |Data Packet Transmitted Interrupt
<> 144:ef7eb2e8f9f7 31173 * | | |0 = Not a data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 31174 * | | |1 = A data packet is transmitted from the endpoint to the host.
<> 144:ef7eb2e8f9f7 31175 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31176 * |[4] |RXPKIF |Data Packet Received Interrupt
<> 144:ef7eb2e8f9f7 31177 * | | |0 = No data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 31178 * | | |1 = A data packet is received from the host by the endpoint.
<> 144:ef7eb2e8f9f7 31179 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31180 * |[5] |OUTTKIF |Data OUT Token Interrupt
<> 144:ef7eb2e8f9f7 31181 * | | |0 = A Data OUT token has not been received from the host.
<> 144:ef7eb2e8f9f7 31182 * | | |1 = A Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 31183 * | | |This bit also set by PING tokens(in high-speed only).
<> 144:ef7eb2e8f9f7 31184 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31185 * |[6] |INTKIF |Data IN Token Interrupt
<> 144:ef7eb2e8f9f7 31186 * | | |0 = Not Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 31187 * | | |1 = A Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 31188 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31189 * |[7] |PINGIF |PING Token Interrupt
<> 144:ef7eb2e8f9f7 31190 * | | |0 = A Data PING token has not been received from the host.
<> 144:ef7eb2e8f9f7 31191 * | | |1 = A Data PING token has been received from the host.
<> 144:ef7eb2e8f9f7 31192 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31193 * |[8] |NAKIF |USB NAK Sent
<> 144:ef7eb2e8f9f7 31194 * | | |0 = The last USB IN packet could be provided, and was acknowledged with a ACK.
<> 144:ef7eb2e8f9f7 31195 * | | |1 = The last USB IN packet could not be provided, and was acknowledged with a NAK.
<> 144:ef7eb2e8f9f7 31196 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31197 * |[9] |STALLIF |USB STALL Sent
<> 144:ef7eb2e8f9f7 31198 * | | |0 = The last USB packet could be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 31199 * | | |1 = The last USB packet could not be accepted or provided because the endpoint was stalled, and was acknowledged with a STALL.
<> 144:ef7eb2e8f9f7 31200 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31201 * |[10] |NYETIF |NYET Sent
<> 144:ef7eb2e8f9f7 31202 * | | |0 = The space available in the RAM is sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 31203 * | | |1 = The space available in the RAM is not sufficient to accommodate the next on coming data packet.
<> 144:ef7eb2e8f9f7 31204 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31205 * |[11] |ERRIF |ERR Sent
<> 144:ef7eb2e8f9f7 31206 * | | |0 = No any error in the transaction.
<> 144:ef7eb2e8f9f7 31207 * | | |1 = There occurs any error in the transaction.
<> 144:ef7eb2e8f9f7 31208 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31209 * |[12] |SHORTRXIF |Bulk Out Short Packet Received
<> 144:ef7eb2e8f9f7 31210 * | | |0 = No bulk out short packet is received.
<> 144:ef7eb2e8f9f7 31211 * | | |1 = Received bulk out short packet (including zero length packet ).
<> 144:ef7eb2e8f9f7 31212 * | | |Note: Write 1 to clear this bit to 0.
<> 144:ef7eb2e8f9f7 31213 */
<> 144:ef7eb2e8f9f7 31214 __IO uint32_t EPLINTSTS;
<> 144:ef7eb2e8f9f7 31215
<> 144:ef7eb2e8f9f7 31216 /**
<> 144:ef7eb2e8f9f7 31217 * EPLINTEN
<> 144:ef7eb2e8f9f7 31218 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31219 * Offset: 0x224 Endpoint L Interrupt Enable Register
<> 144:ef7eb2e8f9f7 31220 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31221 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31222 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31223 * |[0] |BUFFULLIEN|Buffer Full Interrupt
<> 144:ef7eb2e8f9f7 31224 * | | |When set, this bit enables a local interrupt to be set when a buffer full condition is detected on the bus.
<> 144:ef7eb2e8f9f7 31225 * | | |0 = Buffer full interrupt Disabled.
<> 144:ef7eb2e8f9f7 31226 * | | |1 = Buffer full interrupt Enabled.
<> 144:ef7eb2e8f9f7 31227 * |[1] |BUFEMPTYIEN|Buffer Empty Interrupt
<> 144:ef7eb2e8f9f7 31228 * | | |When set, this bit enables a local interrupt to be set when a buffer empty condition is detected on the bus.
<> 144:ef7eb2e8f9f7 31229 * | | |0 = Buffer empty interrupt Disabled.
<> 144:ef7eb2e8f9f7 31230 * | | |1 = Buffer empty interrupt Enabled.
<> 144:ef7eb2e8f9f7 31231 * |[2] |SHORTTXIEN|Short Packet Transferred Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31232 * | | |When set, this bit enables a local interrupt to be set when a short data packet has been transferred to/from the host.
<> 144:ef7eb2e8f9f7 31233 * | | |0 = Short data packet interrupt Disabled.
<> 144:ef7eb2e8f9f7 31234 * | | |1 = Short data packet interrupt Enabled.
<> 144:ef7eb2e8f9f7 31235 * |[3] |TXPKIEN |Data Packet Transmitted Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31236 * | | |When set, this bit enables a local interrupt to be set when a data packet has been received from the host.
<> 144:ef7eb2e8f9f7 31237 * | | |0 = Data packet has been received from the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 31238 * | | |1 = Data packet has been received from the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 31239 * |[4] |RXPKIEN |Data Packet Received Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31240 * | | |When set, this bit enables a local interrupt to be set when a data packet has been transmitted to the host.
<> 144:ef7eb2e8f9f7 31241 * | | |0 = Data packet has been transmitted to the host interrupt Disabled.
<> 144:ef7eb2e8f9f7 31242 * | | |1 = Data packet has been transmitted to the host interrupt Enabled.
<> 144:ef7eb2e8f9f7 31243 * |[5] |OUTTKIEN |Data OUT Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31244 * | | |When set, this bit enables a local interrupt to be set when a Data OUT token has been received from the host.
<> 144:ef7eb2e8f9f7 31245 * | | |0 = Data OUT token interrupt Disabled.
<> 144:ef7eb2e8f9f7 31246 * | | |1 = Data OUT token interrupt Enabled.
<> 144:ef7eb2e8f9f7 31247 * |[6] |INTKIEN |Data IN Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31248 * | | |When set, this bit enables a local interrupt to be set when a Data IN token has been received from the host.
<> 144:ef7eb2e8f9f7 31249 * | | |0 = Data IN token interrupt Disabled.
<> 144:ef7eb2e8f9f7 31250 * | | |1 = Data IN token interrupt Enabled.
<> 144:ef7eb2e8f9f7 31251 * |[7] |PINGIEN |PING Token Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31252 * | | |When set, this bit enables a local interrupt to be set when a PING token has been received from the host.
<> 144:ef7eb2e8f9f7 31253 * | | |0 = PING token interrupt Disabled.
<> 144:ef7eb2e8f9f7 31254 * | | |1 = PING token interrupt Enabled.
<> 144:ef7eb2e8f9f7 31255 * |[8] |NAKIEN |USB NAK Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31256 * | | |When set, this bit enables a local interrupt to be set when a NAK token is sent to the host.
<> 144:ef7eb2e8f9f7 31257 * | | |0 = NAK token interrupt Disabled.
<> 144:ef7eb2e8f9f7 31258 * | | |1 = NAK token interrupt Enabled.
<> 144:ef7eb2e8f9f7 31259 * |[9] |STALLIEN |USB STALL Sent Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31260 * | | |When set, this bit enables a local interrupt to be set when a stall token is sent to the host.
<> 144:ef7eb2e8f9f7 31261 * | | |0 = STALL token interrupt Disabled.
<> 144:ef7eb2e8f9f7 31262 * | | |1 = STALL token interrupt Enabled.
<> 144:ef7eb2e8f9f7 31263 * |[10] |NYETIEN |NYET Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31264 * | | |When set, this bit enables a local interrupt to be set whenever NYET condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 31265 * | | |0 = NYET condition interrupt Disabled.
<> 144:ef7eb2e8f9f7 31266 * | | |1 = NYET condition interrupt Enabled.
<> 144:ef7eb2e8f9f7 31267 * |[11] |ERRIEN |ERR Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31268 * | | |When set, this bit enables a local interrupt to be set whenever ERR condition occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 31269 * | | |0 = Error event interrupt Disabled.
<> 144:ef7eb2e8f9f7 31270 * | | |1 = Error event interrupt Enabled.
<> 144:ef7eb2e8f9f7 31271 * |[12] |SHORTRXIEN|Bulk Out Short Packet Interrupt Enable Control
<> 144:ef7eb2e8f9f7 31272 * | | |When set, this bit enables a local interrupt to be set whenever bulk out short packet occurs on the bus for this endpoint.
<> 144:ef7eb2e8f9f7 31273 * | | |0 = Bulk out interrupt Disabled.
<> 144:ef7eb2e8f9f7 31274 * | | |1 = Bulk out interrupt Enabled.
<> 144:ef7eb2e8f9f7 31275 */
<> 144:ef7eb2e8f9f7 31276 __IO uint32_t EPLINTEN;
<> 144:ef7eb2e8f9f7 31277
<> 144:ef7eb2e8f9f7 31278 /**
<> 144:ef7eb2e8f9f7 31279 * EPLDATCNT
<> 144:ef7eb2e8f9f7 31280 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31281 * Offset: 0x228 Endpoint L Data Available Count Register
<> 144:ef7eb2e8f9f7 31282 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31283 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31284 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31285 * |[0:15] |DATCNT |Data Count
<> 144:ef7eb2e8f9f7 31286 * | | |For an OUT/IN endpoint, this register returns the number of valid bytes in the endpoint packet buffer.
<> 144:ef7eb2e8f9f7 31287 * |[16:30] |DMALOOP |DMA Loop
<> 144:ef7eb2e8f9f7 31288 * | | |This register is the remaining DMA loop to complete. Each loop means 32-byte transfer.
<> 144:ef7eb2e8f9f7 31289 */
<> 144:ef7eb2e8f9f7 31290 __I uint32_t EPLDATCNT;
<> 144:ef7eb2e8f9f7 31291
<> 144:ef7eb2e8f9f7 31292 /**
<> 144:ef7eb2e8f9f7 31293 * EPLRSPCTL
<> 144:ef7eb2e8f9f7 31294 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31295 * Offset: 0x22C Endpoint L Response Control Register
<> 144:ef7eb2e8f9f7 31296 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31297 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31298 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31299 * |[0] |FLUSH |Buffer Flush
<> 144:ef7eb2e8f9f7 31300 * | | |Writing 1 to this bit causes the packet buffer to be flushed and the corresponding EP_AVAIL register to be cleared.
<> 144:ef7eb2e8f9f7 31301 * | | |This bit is self-clearing.
<> 144:ef7eb2e8f9f7 31302 * | | |This bit should always be written after an configuration event.
<> 144:ef7eb2e8f9f7 31303 * | | |0 = The packet buffer is not flushed.
<> 144:ef7eb2e8f9f7 31304 * | | |1 = The packet buffer is flushed by user.
<> 144:ef7eb2e8f9f7 31305 * |[1:2] |MODE |Mode Control
<> 144:ef7eb2e8f9f7 31306 * | | |The two bits decide the operation mode of the in-endpoint.
<> 144:ef7eb2e8f9f7 31307 * | | |00: Auto-Validate Mode
<> 144:ef7eb2e8f9f7 31308 * | | |01: Manual-Validate Mode
<> 144:ef7eb2e8f9f7 31309 * | | |10: Fly Mode
<> 144:ef7eb2e8f9f7 31310 * | | |11: Reserved
<> 144:ef7eb2e8f9f7 31311 * | | |These bits are not valid for an out-endpoint.
<> 144:ef7eb2e8f9f7 31312 * | | |The auto validate mode will be activated when the reserved mode is selected.
<> 144:ef7eb2e8f9f7 31313 * |[3] |TOGGLE |Endpoint Toggle
<> 144:ef7eb2e8f9f7 31314 * | | |This bit is used to clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 31315 * | | |Reading this bit returns the current state of the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 31316 * | | |The local CPU may use this bit to initialize the end-point's toggle in case of reception of a Set Interface request or a Clear Feature (ep_halt) request from the host.
<> 144:ef7eb2e8f9f7 31317 * | | |Only when toggle bit is "1", this bit can be written into the inversed write data bit[3].
<> 144:ef7eb2e8f9f7 31318 * | | |0 = Not clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 31319 * | | |1 = Clear the endpoint data toggle bit.
<> 144:ef7eb2e8f9f7 31320 * |[4] |HALT |Endpoint Halt
<> 144:ef7eb2e8f9f7 31321 * | | |This bit is used to send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 31322 * | | |When an Endpoint Set Feature (Endpoin_halt) is detected by the local CPU, it must write a '1' to this bit.
<> 144:ef7eb2e8f9f7 31323 * | | |0 = Not send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 31324 * | | |1 = Send a STALL handshake as response to the token from the host.
<> 144:ef7eb2e8f9f7 31325 * |[5] |ZEROLEN |Zero Length
<> 144:ef7eb2e8f9f7 31326 * | | |This bit is used to send a zero-length packet n response to an IN-token.
<> 144:ef7eb2e8f9f7 31327 * | | |When this bit is set, a zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 31328 * | | |0 = A zero packet is not sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 31329 * | | |1 = A zero packet is sent to the host on reception of an IN-token.
<> 144:ef7eb2e8f9f7 31330 * |[6] |SHORTTXEN |Short Packet Transfer Enable
<> 144:ef7eb2e8f9f7 31331 * | | |This bit is applicable only in case of Auto-Validate Method.
<> 144:ef7eb2e8f9f7 31332 * | | |This bit is set to validate any remaining data in the buffer which is not equal to the MPS of the endpoint, and happens to be the last transfer.
<> 144:ef7eb2e8f9f7 31333 * | | |0 = Not validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 31334 * | | |1 = Validate any remaining data in the buffer which is not equal to the MPS of the endpoint.
<> 144:ef7eb2e8f9f7 31335 * |[7] |DISBUF |Buffer Disable Control
<> 144:ef7eb2e8f9f7 31336 * | | |This bit is used to disable buffer (set buffer size to 1) when a Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 31337 * | | |0 = Buffer Not Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 31338 * | | |1 = Buffer Disabled when Bulk-OUT short packet is received.
<> 144:ef7eb2e8f9f7 31339 */
<> 144:ef7eb2e8f9f7 31340 __IO uint32_t EPLRSPCTL;
<> 144:ef7eb2e8f9f7 31341
<> 144:ef7eb2e8f9f7 31342 /**
<> 144:ef7eb2e8f9f7 31343 * EPLMPS
<> 144:ef7eb2e8f9f7 31344 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31345 * Offset: 0x230 Endpoint L Maximum Packet Size Register
<> 144:ef7eb2e8f9f7 31346 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31347 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31348 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31349 * |[0:10] |EPMPS |Endpoint Maximum Packet Size
<> 144:ef7eb2e8f9f7 31350 * | | |This field determines the Maximum Packet Size of the Endpoint.
<> 144:ef7eb2e8f9f7 31351 */
<> 144:ef7eb2e8f9f7 31352 __IO uint32_t EPLMPS;
<> 144:ef7eb2e8f9f7 31353
<> 144:ef7eb2e8f9f7 31354 /**
<> 144:ef7eb2e8f9f7 31355 * EPLTXCNT
<> 144:ef7eb2e8f9f7 31356 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31357 * Offset: 0x234 Endpoint L Transfer Count Register
<> 144:ef7eb2e8f9f7 31358 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31359 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31360 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31361 * |[0:10] |TXCNT |Endpoint Transfer Count
<> 144:ef7eb2e8f9f7 31362 * | | |For IN endpoints, this field determines the total number of bytes to be sent to the host in case of manual validation method.
<> 144:ef7eb2e8f9f7 31363 * | | |For OUT endpoints, this field has no effect.
<> 144:ef7eb2e8f9f7 31364 */
<> 144:ef7eb2e8f9f7 31365 __IO uint32_t EPLTXCNT;
<> 144:ef7eb2e8f9f7 31366
<> 144:ef7eb2e8f9f7 31367 /**
<> 144:ef7eb2e8f9f7 31368 * EPLCFG
<> 144:ef7eb2e8f9f7 31369 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31370 * Offset: 0x238 Endpoint L Configuration Register
<> 144:ef7eb2e8f9f7 31371 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31372 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31373 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31374 * |[0] |EPEN |Endpoint Valid
<> 144:ef7eb2e8f9f7 31375 * | | |When set, this bit enables this endpoint.
<> 144:ef7eb2e8f9f7 31376 * | | |This bit has no effect on Endpoint 0, which is always enabled.
<> 144:ef7eb2e8f9f7 31377 * | | |0 = The endpoint Disabled.
<> 144:ef7eb2e8f9f7 31378 * | | |1 = The endpoint Enabled.
<> 144:ef7eb2e8f9f7 31379 * |[1:2] |EPTYPE |Endpoint Type
<> 144:ef7eb2e8f9f7 31380 * | | |This field selects the type of this endpoint. Endpoint 0 is forced to a Control type.
<> 144:ef7eb2e8f9f7 31381 * | | |00 = Reserved.
<> 144:ef7eb2e8f9f7 31382 * | | |01 = Bulk.
<> 144:ef7eb2e8f9f7 31383 * | | |10 = Interrupt.
<> 144:ef7eb2e8f9f7 31384 * | | |11 = Isochronous.
<> 144:ef7eb2e8f9f7 31385 * |[3] |EPDIR |Endpoint Direction
<> 144:ef7eb2e8f9f7 31386 * | | |0 = out-endpoint (Host OUT to Device).
<> 144:ef7eb2e8f9f7 31387 * | | |1 = in-endpoint (Host IN to Device).
<> 144:ef7eb2e8f9f7 31388 * | | |Note: A maximum of one OUT and IN endpoint is allowed for each endpoint number.
<> 144:ef7eb2e8f9f7 31389 * |[4:7] |EPNUM |Endpoint Number
<> 144:ef7eb2e8f9f7 31390 * | | |This field selects the number of the endpoint. Valid numbers 1 to 15.
<> 144:ef7eb2e8f9f7 31391 */
<> 144:ef7eb2e8f9f7 31392 __IO uint32_t EPLCFG;
<> 144:ef7eb2e8f9f7 31393
<> 144:ef7eb2e8f9f7 31394 /**
<> 144:ef7eb2e8f9f7 31395 * EPLBUFSTART
<> 144:ef7eb2e8f9f7 31396 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31397 * Offset: 0x23C Endpoint L RAM Start Address Register
<> 144:ef7eb2e8f9f7 31398 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31399 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31400 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31401 * |[0:11] |SADDR |Endpoint Start Address
<> 144:ef7eb2e8f9f7 31402 * | | |This is the start-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 31403 */
<> 144:ef7eb2e8f9f7 31404 __IO uint32_t EPLBUFSTART;
<> 144:ef7eb2e8f9f7 31405
<> 144:ef7eb2e8f9f7 31406 /**
<> 144:ef7eb2e8f9f7 31407 * EPLBUFEND
<> 144:ef7eb2e8f9f7 31408 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31409 * Offset: 0x240 Endpoint L RAM End Address Register
<> 144:ef7eb2e8f9f7 31410 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31411 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31412 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31413 * |[0:11] |EADDR |Endpoint End Address
<> 144:ef7eb2e8f9f7 31414 * | | |This is the end-address of the RAM space allocated for the endpoint A~L.
<> 144:ef7eb2e8f9f7 31415 */
<> 144:ef7eb2e8f9f7 31416 __IO uint32_t EPLBUFEND;
<> 144:ef7eb2e8f9f7 31417
<> 144:ef7eb2e8f9f7 31418 uint32_t RESERVE2[303];
<> 144:ef7eb2e8f9f7 31419
<> 144:ef7eb2e8f9f7 31420
<> 144:ef7eb2e8f9f7 31421 /**
<> 144:ef7eb2e8f9f7 31422 * DMAADDR
<> 144:ef7eb2e8f9f7 31423 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31424 * Offset: 0x700 AHB DMA Address Register
<> 144:ef7eb2e8f9f7 31425 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31426 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31427 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31428 * |[0:31] |DMAADDR |DMAADDR
<> 144:ef7eb2e8f9f7 31429 * | | |The register specifies the address from which the DMA has to read / write.
<> 144:ef7eb2e8f9f7 31430 * | | |The address must WORD (32-bit) aligned.
<> 144:ef7eb2e8f9f7 31431 */
<> 144:ef7eb2e8f9f7 31432 __IO uint32_t DMAADDR;
<> 144:ef7eb2e8f9f7 31433
<> 144:ef7eb2e8f9f7 31434 /**
<> 144:ef7eb2e8f9f7 31435 * PHYCTL
<> 144:ef7eb2e8f9f7 31436 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31437 * Offset: 0x704 USB PHY Control Register
<> 144:ef7eb2e8f9f7 31438 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31439 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31440 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31441 * |[8] |DPPUEN |DP Pull-Up
<> 144:ef7eb2e8f9f7 31442 * | | |0 = Pull-up resistor on D+ Disabled.
<> 144:ef7eb2e8f9f7 31443 * | | |1 = Pull-up resistor on D+ Enabled.
<> 144:ef7eb2e8f9f7 31444 * |[9] |PHYEN |PHY Suspend Enable Control
<> 144:ef7eb2e8f9f7 31445 * | | |0 = The USB PHY is suspend.
<> 144:ef7eb2e8f9f7 31446 * | | |1 = The USB PHY is not suspend.
<> 144:ef7eb2e8f9f7 31447 * |[24] |WKEN |Wake-Up Enable Control
<> 144:ef7eb2e8f9f7 31448 * | | |0 = The wake-up function Disabled.
<> 144:ef7eb2e8f9f7 31449 * | | |1 = The wake-up function Enabled.
<> 144:ef7eb2e8f9f7 31450 * |[31] |VBUSDET |VBUS Status
<> 144:ef7eb2e8f9f7 31451 * | | |0 = The VBUS is not detected yet.
<> 144:ef7eb2e8f9f7 31452 * | | |1 = The VBUS is detected.
<> 144:ef7eb2e8f9f7 31453 */
<> 144:ef7eb2e8f9f7 31454 __IO uint32_t PHYCTL;
<> 144:ef7eb2e8f9f7 31455
<> 144:ef7eb2e8f9f7 31456 } USBD_T;
<> 144:ef7eb2e8f9f7 31457
<> 144:ef7eb2e8f9f7 31458 /**
<> 144:ef7eb2e8f9f7 31459 @addtogroup USBD_CONST USBD Bit Field Definition
<> 144:ef7eb2e8f9f7 31460 Constant Definitions for USBD Controller
<> 144:ef7eb2e8f9f7 31461 @{ */
<> 144:ef7eb2e8f9f7 31462
<> 144:ef7eb2e8f9f7 31463 #define USBD_GINTSTS_USBIF_Pos (0) /*!< USBD GINTSTS: USBIF Position */
<> 144:ef7eb2e8f9f7 31464 #define USBD_GINTSTS_USBIF_Msk (0x1ul << USBD_GINTSTS_USBIF_Pos) /*!< USBD GINTSTS: USBIF Mask */
<> 144:ef7eb2e8f9f7 31465
<> 144:ef7eb2e8f9f7 31466 #define USBD_GINTSTS_CEPIF_Pos (1) /*!< USBD GINTSTS: CEPIF Position */
<> 144:ef7eb2e8f9f7 31467 #define USBD_GINTSTS_CEPIF_Msk (0x1ul << USBD_GINTSTS_CEPIF_Pos) /*!< USBD GINTSTS: CEPIF Mask */
<> 144:ef7eb2e8f9f7 31468
<> 144:ef7eb2e8f9f7 31469 #define USBD_GINTSTS_EPAIF_Pos (2) /*!< USBD GINTSTS: EPAIF Position */
<> 144:ef7eb2e8f9f7 31470 #define USBD_GINTSTS_EPAIF_Msk (0x1ul << USBD_GINTSTS_EPAIF_Pos) /*!< USBD GINTSTS: EPAIF Mask */
<> 144:ef7eb2e8f9f7 31471
<> 144:ef7eb2e8f9f7 31472 #define USBD_GINTSTS_EPBIF_Pos (3) /*!< USBD GINTSTS: EPBIF Position */
<> 144:ef7eb2e8f9f7 31473 #define USBD_GINTSTS_EPBIF_Msk (0x1ul << USBD_GINTSTS_EPBIF_Pos) /*!< USBD GINTSTS: EPBIF Mask */
<> 144:ef7eb2e8f9f7 31474
<> 144:ef7eb2e8f9f7 31475 #define USBD_GINTSTS_EPCIF_Pos (4) /*!< USBD GINTSTS: EPCIF Position */
<> 144:ef7eb2e8f9f7 31476 #define USBD_GINTSTS_EPCIF_Msk (0x1ul << USBD_GINTSTS_EPCIF_Pos) /*!< USBD GINTSTS: EPCIF Mask */
<> 144:ef7eb2e8f9f7 31477
<> 144:ef7eb2e8f9f7 31478 #define USBD_GINTSTS_EPDIF_Pos (5) /*!< USBD GINTSTS: EPDIF Position */
<> 144:ef7eb2e8f9f7 31479 #define USBD_GINTSTS_EPDIF_Msk (0x1ul << USBD_GINTSTS_EPDIF_Pos) /*!< USBD GINTSTS: EPDIF Mask */
<> 144:ef7eb2e8f9f7 31480
<> 144:ef7eb2e8f9f7 31481 #define USBD_GINTSTS_EPEIF_Pos (6) /*!< USBD GINTSTS: EPEIF Position */
<> 144:ef7eb2e8f9f7 31482 #define USBD_GINTSTS_EPEIF_Msk (0x1ul << USBD_GINTSTS_EPEIF_Pos) /*!< USBD GINTSTS: EPEIF Mask */
<> 144:ef7eb2e8f9f7 31483
<> 144:ef7eb2e8f9f7 31484 #define USBD_GINTSTS_EPFIF_Pos (7) /*!< USBD GINTSTS: EPFIF Position */
<> 144:ef7eb2e8f9f7 31485 #define USBD_GINTSTS_EPFIF_Msk (0x1ul << USBD_GINTSTS_EPFIF_Pos) /*!< USBD GINTSTS: EPFIF Mask */
<> 144:ef7eb2e8f9f7 31486
<> 144:ef7eb2e8f9f7 31487 #define USBD_GINTSTS_EPGIF_Pos (8) /*!< USBD GINTSTS: EPGIF Position */
<> 144:ef7eb2e8f9f7 31488 #define USBD_GINTSTS_EPGIF_Msk (0x1ul << USBD_GINTSTS_EPGIF_Pos) /*!< USBD GINTSTS: EPGIF Mask */
<> 144:ef7eb2e8f9f7 31489
<> 144:ef7eb2e8f9f7 31490 #define USBD_GINTSTS_EPHIF_Pos (9) /*!< USBD GINTSTS: EPHIF Position */
<> 144:ef7eb2e8f9f7 31491 #define USBD_GINTSTS_EPHIF_Msk (0x1ul << USBD_GINTSTS_EPHIF_Pos) /*!< USBD GINTSTS: EPHIF Mask */
<> 144:ef7eb2e8f9f7 31492
<> 144:ef7eb2e8f9f7 31493 #define USBD_GINTSTS_EPIIF_Pos (10) /*!< USBD GINTSTS: EPIIF Position */
<> 144:ef7eb2e8f9f7 31494 #define USBD_GINTSTS_EPIIF_Msk (0x1ul << USBD_GINTSTS_EPIIF_Pos) /*!< USBD GINTSTS: EPIIF Mask */
<> 144:ef7eb2e8f9f7 31495
<> 144:ef7eb2e8f9f7 31496 #define USBD_GINTSTS_EPJIF_Pos (11) /*!< USBD GINTSTS: EPJIF Position */
<> 144:ef7eb2e8f9f7 31497 #define USBD_GINTSTS_EPJIF_Msk (0x1ul << USBD_GINTSTS_EPJIF_Pos) /*!< USBD GINTSTS: EPJIF Mask */
<> 144:ef7eb2e8f9f7 31498
<> 144:ef7eb2e8f9f7 31499 #define USBD_GINTSTS_EPKIF_Pos (12) /*!< USBD GINTSTS: EPKIF Position */
<> 144:ef7eb2e8f9f7 31500 #define USBD_GINTSTS_EPKIF_Msk (0x1ul << USBD_GINTSTS_EPKIF_Pos) /*!< USBD GINTSTS: EPKIF Mask */
<> 144:ef7eb2e8f9f7 31501
<> 144:ef7eb2e8f9f7 31502 #define USBD_GINTSTS_EPLIF_Pos (13) /*!< USBD GINTSTS: EPLIF Position */
<> 144:ef7eb2e8f9f7 31503 #define USBD_GINTSTS_EPLIF_Msk (0x1ul << USBD_GINTSTS_EPLIF_Pos) /*!< USBD GINTSTS: EPLIF Mask */
<> 144:ef7eb2e8f9f7 31504
<> 144:ef7eb2e8f9f7 31505 #define USBD_GINTEN_USBIE_Pos (0) /*!< USBD GINTEN: USBIE Position */
<> 144:ef7eb2e8f9f7 31506 #define USBD_GINTEN_USBIE_Msk (0x1ul << USBD_GINTEN_USBIE_Pos) /*!< USBD GINTEN: USBIE Mask */
<> 144:ef7eb2e8f9f7 31507
<> 144:ef7eb2e8f9f7 31508 #define USBD_GINTEN_CEPIE_Pos (1) /*!< USBD GINTEN: CEPIE Position */
<> 144:ef7eb2e8f9f7 31509 #define USBD_GINTEN_CEPIE_Msk (0x1ul << USBD_GINTEN_CEPIE_Pos) /*!< USBD GINTEN: CEPIE Mask */
<> 144:ef7eb2e8f9f7 31510
<> 144:ef7eb2e8f9f7 31511 #define USBD_GINTEN_EPAIE_Pos (2) /*!< USBD GINTEN: EPAIE Position */
<> 144:ef7eb2e8f9f7 31512 #define USBD_GINTEN_EPAIE_Msk (0x1ul << USBD_GINTEN_EPAIE_Pos) /*!< USBD GINTEN: EPAIE Mask */
<> 144:ef7eb2e8f9f7 31513
<> 144:ef7eb2e8f9f7 31514 #define USBD_GINTEN_EPBIE_Pos (3) /*!< USBD GINTEN: EPBIE Position */
<> 144:ef7eb2e8f9f7 31515 #define USBD_GINTEN_EPBIE_Msk (0x1ul << USBD_GINTEN_EPBIE_Pos) /*!< USBD GINTEN: EPBIE Mask */
<> 144:ef7eb2e8f9f7 31516
<> 144:ef7eb2e8f9f7 31517 #define USBD_GINTEN_EPCIE_Pos (4) /*!< USBD GINTEN: EPCIE Position */
<> 144:ef7eb2e8f9f7 31518 #define USBD_GINTEN_EPCIE_Msk (0x1ul << USBD_GINTEN_EPCIE_Pos) /*!< USBD GINTEN: EPCIE Mask */
<> 144:ef7eb2e8f9f7 31519
<> 144:ef7eb2e8f9f7 31520 #define USBD_GINTEN_EPDIE_Pos (5) /*!< USBD GINTEN: EPDIE Position */
<> 144:ef7eb2e8f9f7 31521 #define USBD_GINTEN_EPDIE_Msk (0x1ul << USBD_GINTEN_EPDIE_Pos) /*!< USBD GINTEN: EPDIE Mask */
<> 144:ef7eb2e8f9f7 31522
<> 144:ef7eb2e8f9f7 31523 #define USBD_GINTEN_EPEIE_Pos (6) /*!< USBD GINTEN: EPEIE Position */
<> 144:ef7eb2e8f9f7 31524 #define USBD_GINTEN_EPEIE_Msk (0x1ul << USBD_GINTEN_EPEIE_Pos) /*!< USBD GINTEN: EPEIE Mask */
<> 144:ef7eb2e8f9f7 31525
<> 144:ef7eb2e8f9f7 31526 #define USBD_GINTEN_EPFIE_Pos (7) /*!< USBD GINTEN: EPFIE Position */
<> 144:ef7eb2e8f9f7 31527 #define USBD_GINTEN_EPFIE_Msk (0x1ul << USBD_GINTEN_EPFIE_Pos) /*!< USBD GINTEN: EPFIE Mask */
<> 144:ef7eb2e8f9f7 31528
<> 144:ef7eb2e8f9f7 31529 #define USBD_GINTEN_EPGIE_Pos (8) /*!< USBD GINTEN: EPGIE Position */
<> 144:ef7eb2e8f9f7 31530 #define USBD_GINTEN_EPGIE_Msk (0x1ul << USBD_GINTEN_EPGIE_Pos) /*!< USBD GINTEN: EPGIE Mask */
<> 144:ef7eb2e8f9f7 31531
<> 144:ef7eb2e8f9f7 31532 #define USBD_GINTEN_EPHIE_Pos (9) /*!< USBD GINTEN: EPHIE Position */
<> 144:ef7eb2e8f9f7 31533 #define USBD_GINTEN_EPHIE_Msk (0x1ul << USBD_GINTEN_EPHIE_Pos) /*!< USBD GINTEN: EPHIE Mask */
<> 144:ef7eb2e8f9f7 31534
<> 144:ef7eb2e8f9f7 31535 #define USBD_GINTEN_EPIIE_Pos (10) /*!< USBD GINTEN: EPIIE Position */
<> 144:ef7eb2e8f9f7 31536 #define USBD_GINTEN_EPIIE_Msk (0x1ul << USBD_GINTEN_EPIIE_Pos) /*!< USBD GINTEN: EPIIE Mask */
<> 144:ef7eb2e8f9f7 31537
<> 144:ef7eb2e8f9f7 31538 #define USBD_GINTEN_EPJIE_Pos (11) /*!< USBD GINTEN: EPJIE Position */
<> 144:ef7eb2e8f9f7 31539 #define USBD_GINTEN_EPJIE_Msk (0x1ul << USBD_GINTEN_EPJIE_Pos) /*!< USBD GINTEN: EPJIE Mask */
<> 144:ef7eb2e8f9f7 31540
<> 144:ef7eb2e8f9f7 31541 #define USBD_GINTEN_EPKIE_Pos (12) /*!< USBD GINTEN: EPKIE Position */
<> 144:ef7eb2e8f9f7 31542 #define USBD_GINTEN_EPKIE_Msk (0x1ul << USBD_GINTEN_EPKIE_Pos) /*!< USBD GINTEN: EPKIE Mask */
<> 144:ef7eb2e8f9f7 31543
<> 144:ef7eb2e8f9f7 31544 #define USBD_GINTEN_EPLIE_Pos (13) /*!< USBD GINTEN: EPLIE Position */
<> 144:ef7eb2e8f9f7 31545 #define USBD_GINTEN_EPLIE_Msk (0x1ul << USBD_GINTEN_EPLIE_Pos) /*!< USBD GINTEN: EPLIE Mask */
<> 144:ef7eb2e8f9f7 31546
<> 144:ef7eb2e8f9f7 31547 #define USBD_BUSINTSTS_SOFIF_Pos (0) /*!< USBD BUSINTSTS: SOFIF Position */
<> 144:ef7eb2e8f9f7 31548 #define USBD_BUSINTSTS_SOFIF_Msk (0x1ul << USBD_BUSINTSTS_SOFIF_Pos) /*!< USBD BUSINTSTS: SOFIF Mask */
<> 144:ef7eb2e8f9f7 31549
<> 144:ef7eb2e8f9f7 31550 #define USBD_BUSINTSTS_RSTIF_Pos (1) /*!< USBD BUSINTSTS: RSTIF Position */
<> 144:ef7eb2e8f9f7 31551 #define USBD_BUSINTSTS_RSTIF_Msk (0x1ul << USBD_BUSINTSTS_RSTIF_Pos) /*!< USBD BUSINTSTS: RSTIF Mask */
<> 144:ef7eb2e8f9f7 31552
<> 144:ef7eb2e8f9f7 31553 #define USBD_BUSINTSTS_RESUMEIF_Pos (2) /*!< USBD BUSINTSTS: RESUMEIF Position */
<> 144:ef7eb2e8f9f7 31554 #define USBD_BUSINTSTS_RESUMEIF_Msk (0x1ul << USBD_BUSINTSTS_RESUMEIF_Pos) /*!< USBD BUSINTSTS: RESUMEIF Mask */
<> 144:ef7eb2e8f9f7 31555
<> 144:ef7eb2e8f9f7 31556 #define USBD_BUSINTSTS_SUSPENDIF_Pos (3) /*!< USBD BUSINTSTS: SUSPENDIF Position */
<> 144:ef7eb2e8f9f7 31557 #define USBD_BUSINTSTS_SUSPENDIF_Msk (0x1ul << USBD_BUSINTSTS_SUSPENDIF_Pos) /*!< USBD BUSINTSTS: SUSPENDIF Mask */
<> 144:ef7eb2e8f9f7 31558
<> 144:ef7eb2e8f9f7 31559 #define USBD_BUSINTSTS_HISPDIF_Pos (4) /*!< USBD BUSINTSTS: HISPDIF Position */
<> 144:ef7eb2e8f9f7 31560 #define USBD_BUSINTSTS_HISPDIF_Msk (0x1ul << USBD_BUSINTSTS_HISPDIF_Pos) /*!< USBD BUSINTSTS: HISPDIF Mask */
<> 144:ef7eb2e8f9f7 31561
<> 144:ef7eb2e8f9f7 31562 #define USBD_BUSINTSTS_DMADONEIF_Pos (5) /*!< USBD BUSINTSTS: DMADONEIF Position */
<> 144:ef7eb2e8f9f7 31563 #define USBD_BUSINTSTS_DMADONEIF_Msk (0x1ul << USBD_BUSINTSTS_DMADONEIF_Pos) /*!< USBD BUSINTSTS: DMADONEIF Mask */
<> 144:ef7eb2e8f9f7 31564
<> 144:ef7eb2e8f9f7 31565 #define USBD_BUSINTSTS_PHYCLKVLDIF_Pos (6) /*!< USBD BUSINTSTS: PHYCLKVLDIF Position */
<> 144:ef7eb2e8f9f7 31566 #define USBD_BUSINTSTS_PHYCLKVLDIF_Msk (0x1ul << USBD_BUSINTSTS_PHYCLKVLDIF_Pos) /*!< USBD BUSINTSTS: PHYCLKVLDIF Mask */
<> 144:ef7eb2e8f9f7 31567
<> 144:ef7eb2e8f9f7 31568 #define USBD_BUSINTSTS_VBUSDETIF_Pos (8) /*!< USBD BUSINTSTS: VBUSDETIF Position */
<> 144:ef7eb2e8f9f7 31569 #define USBD_BUSINTSTS_VBUSDETIF_Msk (0x1ul << USBD_BUSINTSTS_VBUSDETIF_Pos) /*!< USBD BUSINTSTS: VBUSDETIF Mask */
<> 144:ef7eb2e8f9f7 31570
<> 144:ef7eb2e8f9f7 31571 #define USBD_BUSINTEN_SOFIEN_Pos (0) /*!< USBD BUSINTEN: SOFIEN Position */
<> 144:ef7eb2e8f9f7 31572 #define USBD_BUSINTEN_SOFIEN_Msk (0x1ul << USBD_BUSINTEN_SOFIEN_Pos) /*!< USBD BUSINTEN: SOFIEN Mask */
<> 144:ef7eb2e8f9f7 31573
<> 144:ef7eb2e8f9f7 31574 #define USBD_BUSINTEN_RSTIEN_Pos (1) /*!< USBD BUSINTEN: RSTIEN Position */
<> 144:ef7eb2e8f9f7 31575 #define USBD_BUSINTEN_RSTIEN_Msk (0x1ul << USBD_BUSINTEN_RSTIEN_Pos) /*!< USBD BUSINTEN: RSTIEN Mask */
<> 144:ef7eb2e8f9f7 31576
<> 144:ef7eb2e8f9f7 31577 #define USBD_BUSINTEN_RESUMEIEN_Pos (2) /*!< USBD BUSINTEN: RESUMEIEN Position */
<> 144:ef7eb2e8f9f7 31578 #define USBD_BUSINTEN_RESUMEIEN_Msk (0x1ul << USBD_BUSINTEN_RESUMEIEN_Pos) /*!< USBD BUSINTEN: RESUMEIEN Mask */
<> 144:ef7eb2e8f9f7 31579
<> 144:ef7eb2e8f9f7 31580 #define USBD_BUSINTEN_SUSPENDIEN_Pos (3) /*!< USBD BUSINTEN: SUSPENDIEN Position */
<> 144:ef7eb2e8f9f7 31581 #define USBD_BUSINTEN_SUSPENDIEN_Msk (0x1ul << USBD_BUSINTEN_SUSPENDIEN_Pos) /*!< USBD BUSINTEN: SUSPENDIEN Mask */
<> 144:ef7eb2e8f9f7 31582
<> 144:ef7eb2e8f9f7 31583 #define USBD_BUSINTEN_HISPDIEN_Pos (4) /*!< USBD BUSINTEN: HISPDIEN Position */
<> 144:ef7eb2e8f9f7 31584 #define USBD_BUSINTEN_HISPDIEN_Msk (0x1ul << USBD_BUSINTEN_HISPDIEN_Pos) /*!< USBD BUSINTEN: HISPDIEN Mask */
<> 144:ef7eb2e8f9f7 31585
<> 144:ef7eb2e8f9f7 31586 #define USBD_BUSINTEN_DMADONEIEN_Pos (5) /*!< USBD BUSINTEN: DMADONEIEN Position */
<> 144:ef7eb2e8f9f7 31587 #define USBD_BUSINTEN_DMADONEIEN_Msk (0x1ul << USBD_BUSINTEN_DMADONEIEN_Pos) /*!< USBD BUSINTEN: DMADONEIEN Mask */
<> 144:ef7eb2e8f9f7 31588
<> 144:ef7eb2e8f9f7 31589 #define USBD_BUSINTEN_PHYCLKVLDIEN_Pos (6) /*!< USBD BUSINTEN: PHYCLKVLDIEN Position */
<> 144:ef7eb2e8f9f7 31590 #define USBD_BUSINTEN_PHYCLKVLDIEN_Msk (0x1ul << USBD_BUSINTEN_PHYCLKVLDIEN_Pos) /*!< USBD BUSINTEN: PHYCLKVLDIEN Mask */
<> 144:ef7eb2e8f9f7 31591
<> 144:ef7eb2e8f9f7 31592 #define USBD_BUSINTEN_VBUSDETIEN_Pos (8) /*!< USBD BUSINTEN: VBUSDETIEN Position */
<> 144:ef7eb2e8f9f7 31593 #define USBD_BUSINTEN_VBUSDETIEN_Msk (0x1ul << USBD_BUSINTEN_VBUSDETIEN_Pos) /*!< USBD BUSINTEN: VBUSDETIEN Mask */
<> 144:ef7eb2e8f9f7 31594
<> 144:ef7eb2e8f9f7 31595 #define USBD_OPER_RESUMEEN_Pos (0) /*!< USBD OPER: RESUMEEN Position */
<> 144:ef7eb2e8f9f7 31596 #define USBD_OPER_RESUMEEN_Msk (0x1ul << USBD_OPER_RESUMEEN_Pos) /*!< USBD OPER: RESUMEEN Mask */
<> 144:ef7eb2e8f9f7 31597
<> 144:ef7eb2e8f9f7 31598 #define USBD_OPER_HISPDEN_Pos (1) /*!< USBD OPER: HISPDEN Position */
<> 144:ef7eb2e8f9f7 31599 #define USBD_OPER_HISPDEN_Msk (0x1ul << USBD_OPER_HISPDEN_Pos) /*!< USBD OPER: HISPDEN Mask */
<> 144:ef7eb2e8f9f7 31600
<> 144:ef7eb2e8f9f7 31601 #define USBD_OPER_CURSPD_Pos (2) /*!< USBD OPER: CURSPD Position */
<> 144:ef7eb2e8f9f7 31602 #define USBD_OPER_CURSPD_Msk (0x1ul << USBD_OPER_CURSPD_Pos) /*!< USBD OPER: CURSPD Mask */
<> 144:ef7eb2e8f9f7 31603
<> 144:ef7eb2e8f9f7 31604 #define USBD_FRAMECNT_MFRAMECNT_Pos (0) /*!< USBD FRAMECNT: MFRAMECNT Position */
<> 144:ef7eb2e8f9f7 31605 #define USBD_FRAMECNT_MFRAMECNT_Msk (0x7ul << USBD_FRAMECNT_MFRAMECNT_Pos) /*!< USBD FRAMECNT: MFRAMECNT Mask */
<> 144:ef7eb2e8f9f7 31606
<> 144:ef7eb2e8f9f7 31607 #define USBD_FRAMECNT_FRAMECNT_Pos (3) /*!< USBD FRAMECNT: FRAMECNT Position */
<> 144:ef7eb2e8f9f7 31608 #define USBD_FRAMECNT_FRAMECNT_Msk (0x7fful << USBD_FRAMECNT_FRAMECNT_Pos) /*!< USBD FRAMECNT: FRAMECNT Mask */
<> 144:ef7eb2e8f9f7 31609
<> 144:ef7eb2e8f9f7 31610 #define USBD_FADDR_FADDR_Pos (0) /*!< USBD FADDR: FADDR Position */
<> 144:ef7eb2e8f9f7 31611 #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) /*!< USBD FADDR: FADDR Mask */
<> 144:ef7eb2e8f9f7 31612
<> 144:ef7eb2e8f9f7 31613 #define USBD_TEST_TESTMODE_Pos (0) /*!< USBD TEST: TESTMODE Position */
<> 144:ef7eb2e8f9f7 31614 #define USBD_TEST_TESTMODE_Msk (0x7ul << USBD_TEST_TESTMODE_Pos) /*!< USBD TEST: TESTMODE Mask */
<> 144:ef7eb2e8f9f7 31615
<> 144:ef7eb2e8f9f7 31616 #define USBD_CEPDAT_DAT_Pos (0) /*!< USBD CEPDAT: DAT Position */
<> 144:ef7eb2e8f9f7 31617 #define USBD_CEPDAT_DAT_Msk (0xfffffffful << USBD_CEPDAT_DAT_Pos) /*!< USBD CEPDAT: DAT Mask */
<> 144:ef7eb2e8f9f7 31618
<> 144:ef7eb2e8f9f7 31619 #define USBD_CEPCTL_NAKCLR_Pos (0) /*!< USBD CEPCTL: NAKCLR Position */
<> 144:ef7eb2e8f9f7 31620 #define USBD_CEPCTL_NAKCLR_Msk (0x1ul << USBD_CEPCTL_NAKCLR_Pos) /*!< USBD CEPCTL: NAKCLR Mask */
<> 144:ef7eb2e8f9f7 31621
<> 144:ef7eb2e8f9f7 31622 #define USBD_CEPCTL_STALLEN_Pos (1) /*!< USBD CEPCTL: STALLEN Position */
<> 144:ef7eb2e8f9f7 31623 #define USBD_CEPCTL_STALLEN_Msk (0x1ul << USBD_CEPCTL_STALLEN_Pos) /*!< USBD CEPCTL: STALLEN Mask */
<> 144:ef7eb2e8f9f7 31624
<> 144:ef7eb2e8f9f7 31625 #define USBD_CEPCTL_ZEROLEN_Pos (2) /*!< USBD CEPCTL: ZEROLEN Position */
<> 144:ef7eb2e8f9f7 31626 #define USBD_CEPCTL_ZEROLEN_Msk (0x1ul << USBD_CEPCTL_ZEROLEN_Pos) /*!< USBD CEPCTL: ZEROLEN Mask */
<> 144:ef7eb2e8f9f7 31627
<> 144:ef7eb2e8f9f7 31628 #define USBD_CEPCTL_FLUSH_Pos (3) /*!< USBD CEPCTL: FLUSH Position */
<> 144:ef7eb2e8f9f7 31629 #define USBD_CEPCTL_FLUSH_Msk (0x1ul << USBD_CEPCTL_FLUSH_Pos) /*!< USBD CEPCTL: FLUSH Mask */
<> 144:ef7eb2e8f9f7 31630
<> 144:ef7eb2e8f9f7 31631 #define USBD_CEPINTEN_SETUPTKIEN_Pos (0) /*!< USBD CEPINTEN: SETUPTKIEN Position */
<> 144:ef7eb2e8f9f7 31632 #define USBD_CEPINTEN_SETUPTKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPTKIEN_Pos) /*!< USBD CEPINTEN: SETUPTKIEN Mask */
<> 144:ef7eb2e8f9f7 31633
<> 144:ef7eb2e8f9f7 31634 #define USBD_CEPINTEN_SETUPPKIEN_Pos (1) /*!< USBD CEPINTEN: SETUPPKIEN Position */
<> 144:ef7eb2e8f9f7 31635 #define USBD_CEPINTEN_SETUPPKIEN_Msk (0x1ul << USBD_CEPINTEN_SETUPPKIEN_Pos) /*!< USBD CEPINTEN: SETUPPKIEN Mask */
<> 144:ef7eb2e8f9f7 31636
<> 144:ef7eb2e8f9f7 31637 #define USBD_CEPINTEN_OUTTKIEN_Pos (2) /*!< USBD CEPINTEN: OUTTKIEN Position */
<> 144:ef7eb2e8f9f7 31638 #define USBD_CEPINTEN_OUTTKIEN_Msk (0x1ul << USBD_CEPINTEN_OUTTKIEN_Pos) /*!< USBD CEPINTEN: OUTTKIEN Mask */
<> 144:ef7eb2e8f9f7 31639
<> 144:ef7eb2e8f9f7 31640 #define USBD_CEPINTEN_INTKIEN_Pos (3) /*!< USBD CEPINTEN: INTKIEN Position */
<> 144:ef7eb2e8f9f7 31641 #define USBD_CEPINTEN_INTKIEN_Msk (0x1ul << USBD_CEPINTEN_INTKIEN_Pos) /*!< USBD CEPINTEN: INTKIEN Mask */
<> 144:ef7eb2e8f9f7 31642
<> 144:ef7eb2e8f9f7 31643 #define USBD_CEPINTEN_PINGIEN_Pos (4) /*!< USBD CEPINTEN: PINGIEN Position */
<> 144:ef7eb2e8f9f7 31644 #define USBD_CEPINTEN_PINGIEN_Msk (0x1ul << USBD_CEPINTEN_PINGIEN_Pos) /*!< USBD CEPINTEN: PINGIEN Mask */
<> 144:ef7eb2e8f9f7 31645
<> 144:ef7eb2e8f9f7 31646 #define USBD_CEPINTEN_TXPKIEN_Pos (5) /*!< USBD CEPINTEN: TXPKIEN Position */
<> 144:ef7eb2e8f9f7 31647 #define USBD_CEPINTEN_TXPKIEN_Msk (0x1ul << USBD_CEPINTEN_TXPKIEN_Pos) /*!< USBD CEPINTEN: TXPKIEN Mask */
<> 144:ef7eb2e8f9f7 31648
<> 144:ef7eb2e8f9f7 31649 #define USBD_CEPINTEN_RXPKIEN_Pos (6) /*!< USBD CEPINTEN: RXPKIEN Position */
<> 144:ef7eb2e8f9f7 31650 #define USBD_CEPINTEN_RXPKIEN_Msk (0x1ul << USBD_CEPINTEN_RXPKIEN_Pos) /*!< USBD CEPINTEN: RXPKIEN Mask */
<> 144:ef7eb2e8f9f7 31651
<> 144:ef7eb2e8f9f7 31652 #define USBD_CEPINTEN_NAKIEN_Pos (7) /*!< USBD CEPINTEN: NAKIEN Position */
<> 144:ef7eb2e8f9f7 31653 #define USBD_CEPINTEN_NAKIEN_Msk (0x1ul << USBD_CEPINTEN_NAKIEN_Pos) /*!< USBD CEPINTEN: NAKIEN Mask */
<> 144:ef7eb2e8f9f7 31654
<> 144:ef7eb2e8f9f7 31655 #define USBD_CEPINTEN_STALLIEN_Pos (8) /*!< USBD CEPINTEN: STALLIEN Position */
<> 144:ef7eb2e8f9f7 31656 #define USBD_CEPINTEN_STALLIEN_Msk (0x1ul << USBD_CEPINTEN_STALLIEN_Pos) /*!< USBD CEPINTEN: STALLIEN Mask */
<> 144:ef7eb2e8f9f7 31657
<> 144:ef7eb2e8f9f7 31658 #define USBD_CEPINTEN_ERRIEN_Pos (9) /*!< USBD CEPINTEN: ERRIEN Position */
<> 144:ef7eb2e8f9f7 31659 #define USBD_CEPINTEN_ERRIEN_Msk (0x1ul << USBD_CEPINTEN_ERRIEN_Pos) /*!< USBD CEPINTEN: ERRIEN Mask */
<> 144:ef7eb2e8f9f7 31660
<> 144:ef7eb2e8f9f7 31661 #define USBD_CEPINTEN_STSDONEIEN_Pos (10) /*!< USBD CEPINTEN: STSDONEIEN Position */
<> 144:ef7eb2e8f9f7 31662 #define USBD_CEPINTEN_STSDONEIEN_Msk (0x1ul << USBD_CEPINTEN_STSDONEIEN_Pos) /*!< USBD CEPINTEN: STSDONEIEN Mask */
<> 144:ef7eb2e8f9f7 31663
<> 144:ef7eb2e8f9f7 31664 #define USBD_CEPINTEN_BUFFULLIEN_Pos (11) /*!< USBD CEPINTEN: BUFFULLIEN Position */
<> 144:ef7eb2e8f9f7 31665 #define USBD_CEPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_CEPINTEN_BUFFULLIEN_Pos) /*!< USBD CEPINTEN: BUFFULLIEN Mask */
<> 144:ef7eb2e8f9f7 31666
<> 144:ef7eb2e8f9f7 31667 #define USBD_CEPINTEN_BUFEMPTYIEN_Pos (12) /*!< USBD CEPINTEN: BUFEMPTYIEN Position */
<> 144:ef7eb2e8f9f7 31668 #define USBD_CEPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_CEPINTEN_BUFEMPTYIEN_Pos) /*!< USBD CEPINTEN: BUFEMPTYIEN Mask */
<> 144:ef7eb2e8f9f7 31669
<> 144:ef7eb2e8f9f7 31670 #define USBD_CEPINTSTS_SETUPTKIF_Pos (0) /*!< USBD CEPINTSTS: SETUPTKIF Position */
<> 144:ef7eb2e8f9f7 31671 #define USBD_CEPINTSTS_SETUPTKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPTKIF_Pos) /*!< USBD CEPINTSTS: SETUPTKIF Mask */
<> 144:ef7eb2e8f9f7 31672
<> 144:ef7eb2e8f9f7 31673 #define USBD_CEPINTSTS_SETUPPKIF_Pos (1) /*!< USBD CEPINTSTS: SETUPPKIF Position */
<> 144:ef7eb2e8f9f7 31674 #define USBD_CEPINTSTS_SETUPPKIF_Msk (0x1ul << USBD_CEPINTSTS_SETUPPKIF_Pos) /*!< USBD CEPINTSTS: SETUPPKIF Mask */
<> 144:ef7eb2e8f9f7 31675
<> 144:ef7eb2e8f9f7 31676 #define USBD_CEPINTSTS_OUTTKIF_Pos (2) /*!< USBD CEPINTSTS: OUTTKIF Position */
<> 144:ef7eb2e8f9f7 31677 #define USBD_CEPINTSTS_OUTTKIF_Msk (0x1ul << USBD_CEPINTSTS_OUTTKIF_Pos) /*!< USBD CEPINTSTS: OUTTKIF Mask */
<> 144:ef7eb2e8f9f7 31678
<> 144:ef7eb2e8f9f7 31679 #define USBD_CEPINTSTS_INTKIF_Pos (3) /*!< USBD CEPINTSTS: INTKIF Position */
<> 144:ef7eb2e8f9f7 31680 #define USBD_CEPINTSTS_INTKIF_Msk (0x1ul << USBD_CEPINTSTS_INTKIF_Pos) /*!< USBD CEPINTSTS: INTKIF Mask */
<> 144:ef7eb2e8f9f7 31681
<> 144:ef7eb2e8f9f7 31682 #define USBD_CEPINTSTS_PINGIF_Pos (4) /*!< USBD CEPINTSTS: PINGIF Position */
<> 144:ef7eb2e8f9f7 31683 #define USBD_CEPINTSTS_PINGIF_Msk (0x1ul << USBD_CEPINTSTS_PINGIF_Pos) /*!< USBD CEPINTSTS: PINGIF Mask */
<> 144:ef7eb2e8f9f7 31684
<> 144:ef7eb2e8f9f7 31685 #define USBD_CEPINTSTS_TXPKIF_Pos (5) /*!< USBD CEPINTSTS: TXPKIF Position */
<> 144:ef7eb2e8f9f7 31686 #define USBD_CEPINTSTS_TXPKIF_Msk (0x1ul << USBD_CEPINTSTS_TXPKIF_Pos) /*!< USBD CEPINTSTS: TXPKIF Mask */
<> 144:ef7eb2e8f9f7 31687
<> 144:ef7eb2e8f9f7 31688 #define USBD_CEPINTSTS_RXPKIF_Pos (6) /*!< USBD CEPINTSTS: RXPKIF Position */
<> 144:ef7eb2e8f9f7 31689 #define USBD_CEPINTSTS_RXPKIF_Msk (0x1ul << USBD_CEPINTSTS_RXPKIF_Pos) /*!< USBD CEPINTSTS: RXPKIF Mask */
<> 144:ef7eb2e8f9f7 31690
<> 144:ef7eb2e8f9f7 31691 #define USBD_CEPINTSTS_NAKIF_Pos (7) /*!< USBD CEPINTSTS: NAKIF Position */
<> 144:ef7eb2e8f9f7 31692 #define USBD_CEPINTSTS_NAKIF_Msk (0x1ul << USBD_CEPINTSTS_NAKIF_Pos) /*!< USBD CEPINTSTS: NAKIF Mask */
<> 144:ef7eb2e8f9f7 31693
<> 144:ef7eb2e8f9f7 31694 #define USBD_CEPINTSTS_STALLIF_Pos (8) /*!< USBD CEPINTSTS: STALLIF Position */
<> 144:ef7eb2e8f9f7 31695 #define USBD_CEPINTSTS_STALLIF_Msk (0x1ul << USBD_CEPINTSTS_STALLIF_Pos) /*!< USBD CEPINTSTS: STALLIF Mask */
<> 144:ef7eb2e8f9f7 31696
<> 144:ef7eb2e8f9f7 31697 #define USBD_CEPINTSTS_ERRIF_Pos (9) /*!< USBD CEPINTSTS: ERRIF Position */
<> 144:ef7eb2e8f9f7 31698 #define USBD_CEPINTSTS_ERRIF_Msk (0x1ul << USBD_CEPINTSTS_ERRIF_Pos) /*!< USBD CEPINTSTS: ERRIF Mask */
<> 144:ef7eb2e8f9f7 31699
<> 144:ef7eb2e8f9f7 31700 #define USBD_CEPINTSTS_STSDONEIF_Pos (10) /*!< USBD CEPINTSTS: STSDONEIF Position */
<> 144:ef7eb2e8f9f7 31701 #define USBD_CEPINTSTS_STSDONEIF_Msk (0x1ul << USBD_CEPINTSTS_STSDONEIF_Pos) /*!< USBD CEPINTSTS: STSDONEIF Mask */
<> 144:ef7eb2e8f9f7 31702
<> 144:ef7eb2e8f9f7 31703 #define USBD_CEPINTSTS_BUFFULLIF_Pos (11) /*!< USBD CEPINTSTS: BUFFULLIF Position */
<> 144:ef7eb2e8f9f7 31704 #define USBD_CEPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_CEPINTSTS_BUFFULLIF_Pos) /*!< USBD CEPINTSTS: BUFFULLIF Mask */
<> 144:ef7eb2e8f9f7 31705
<> 144:ef7eb2e8f9f7 31706 #define USBD_CEPINTSTS_BUFEMPTYIF_Pos (12) /*!< USBD CEPINTSTS: BUFEMPTYIF Position */
<> 144:ef7eb2e8f9f7 31707 #define USBD_CEPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_CEPINTSTS_BUFEMPTYIF_Pos) /*!< USBD CEPINTSTS: BUFEMPTYIF Mask */
<> 144:ef7eb2e8f9f7 31708
<> 144:ef7eb2e8f9f7 31709 #define USBD_CEPTXCNT_TXCNT_Pos (0) /*!< USBD CEPTXCNT: TXCNT Position */
<> 144:ef7eb2e8f9f7 31710 #define USBD_CEPTXCNT_TXCNT_Msk (0xfful << USBD_CEPTXCNT_TXCNT_Pos) /*!< USBD CEPTXCNT: TXCNT Mask */
<> 144:ef7eb2e8f9f7 31711
<> 144:ef7eb2e8f9f7 31712 #define USBD_CEPRXCNT_RXCNT_Pos (0) /*!< USBD CEPRXCNT: RXCNT Position */
<> 144:ef7eb2e8f9f7 31713 #define USBD_CEPRXCNT_RXCNT_Msk (0xfful << USBD_CEPRXCNT_RXCNT_Pos) /*!< USBD CEPRXCNT: RXCNT Mask */
<> 144:ef7eb2e8f9f7 31714
<> 144:ef7eb2e8f9f7 31715 #define USBD_CEPDATCNT_DATCNT_Pos (0) /*!< USBD CEPDATCNT: DATCNT Position */
<> 144:ef7eb2e8f9f7 31716 #define USBD_CEPDATCNT_DATCNT_Msk (0xfffful << USBD_CEPDATCNT_DATCNT_Pos) /*!< USBD CEPDATCNT: DATCNT Mask */
<> 144:ef7eb2e8f9f7 31717
<> 144:ef7eb2e8f9f7 31718 #define USBD_SETUP1_0_SETUP0_Pos (0) /*!< USBD SETUP1_0: SETUP0 Position */
<> 144:ef7eb2e8f9f7 31719 #define USBD_SETUP1_0_SETUP0_Msk (0xfful << USBD_SETUP1_0_SETUP0_Pos) /*!< USBD SETUP1_0: SETUP0 Mask */
<> 144:ef7eb2e8f9f7 31720
<> 144:ef7eb2e8f9f7 31721 #define USBD_SETUP1_0_SETUP1_Pos (8) /*!< USBD SETUP1_0: SETUP1 Position */
<> 144:ef7eb2e8f9f7 31722 #define USBD_SETUP1_0_SETUP1_Msk (0xfful << USBD_SETUP1_0_SETUP1_Pos) /*!< USBD SETUP1_0: SETUP1 Mask */
<> 144:ef7eb2e8f9f7 31723
<> 144:ef7eb2e8f9f7 31724 #define USBD_SETUP3_2_SETUP2_Pos (0) /*!< USBD SETUP3_2: SETUP2 Position */
<> 144:ef7eb2e8f9f7 31725 #define USBD_SETUP3_2_SETUP2_Msk (0xfful << USBD_SETUP3_2_SETUP2_Pos) /*!< USBD SETUP3_2: SETUP2 Mask */
<> 144:ef7eb2e8f9f7 31726
<> 144:ef7eb2e8f9f7 31727 #define USBD_SETUP3_2_SETUP3_Pos (8) /*!< USBD SETUP3_2: SETUP3 Position */
<> 144:ef7eb2e8f9f7 31728 #define USBD_SETUP3_2_SETUP3_Msk (0xfful << USBD_SETUP3_2_SETUP3_Pos) /*!< USBD SETUP3_2: SETUP3 Mask */
<> 144:ef7eb2e8f9f7 31729
<> 144:ef7eb2e8f9f7 31730 #define USBD_SETUP5_4_SETUP4_Pos (0) /*!< USBD SETUP5_4: SETUP4 Position */
<> 144:ef7eb2e8f9f7 31731 #define USBD_SETUP5_4_SETUP4_Msk (0xfful << USBD_SETUP5_4_SETUP4_Pos) /*!< USBD SETUP5_4: SETUP4 Mask */
<> 144:ef7eb2e8f9f7 31732
<> 144:ef7eb2e8f9f7 31733 #define USBD_SETUP5_4_SETUP5_Pos (8) /*!< USBD SETUP5_4: SETUP5 Position */
<> 144:ef7eb2e8f9f7 31734 #define USBD_SETUP5_4_SETUP5_Msk (0xfful << USBD_SETUP5_4_SETUP5_Pos) /*!< USBD SETUP5_4: SETUP5 Mask */
<> 144:ef7eb2e8f9f7 31735
<> 144:ef7eb2e8f9f7 31736 #define USBD_SETUP7_6_SETUP6_Pos (0) /*!< USBD SETUP7_6: SETUP6 Position */
<> 144:ef7eb2e8f9f7 31737 #define USBD_SETUP7_6_SETUP6_Msk (0xfful << USBD_SETUP7_6_SETUP6_Pos) /*!< USBD SETUP7_6: SETUP6 Mask */
<> 144:ef7eb2e8f9f7 31738
<> 144:ef7eb2e8f9f7 31739 #define USBD_SETUP7_6_SETUP7_Pos (8) /*!< USBD SETUP7_6: SETUP7 Position */
<> 144:ef7eb2e8f9f7 31740 #define USBD_SETUP7_6_SETUP7_Msk (0xfful << USBD_SETUP7_6_SETUP7_Pos) /*!< USBD SETUP7_6: SETUP7 Mask */
<> 144:ef7eb2e8f9f7 31741
<> 144:ef7eb2e8f9f7 31742 #define USBD_CEPBUFSTART_SADDR_Pos (0) /*!< USBD CEPBUFSTART: SADDR Position */
<> 144:ef7eb2e8f9f7 31743 #define USBD_CEPBUFSTART_SADDR_Msk (0xffful << USBD_CEPBUFSTART_SADDR_Pos) /*!< USBD CEPBUFSTART: SADDR Mask */
<> 144:ef7eb2e8f9f7 31744
<> 144:ef7eb2e8f9f7 31745 #define USBD_CEPBUFEND_EADDR_Pos (0) /*!< USBD CEPBUFEND: EADDR Position */
<> 144:ef7eb2e8f9f7 31746 #define USBD_CEPBUFEND_EADDR_Msk (0xffful << USBD_CEPBUFEND_EADDR_Pos) /*!< USBD CEPBUFEND: EADDR Mask */
<> 144:ef7eb2e8f9f7 31747
<> 144:ef7eb2e8f9f7 31748 #define USBD_DMACTL_EPNUM_Pos (0) /*!< USBD DMACTL: EPNUM Position */
<> 144:ef7eb2e8f9f7 31749 #define USBD_DMACTL_EPNUM_Msk (0xful << USBD_DMACTL_EPNUM_Pos) /*!< USBD DMACTL: EPNUM Mask */
<> 144:ef7eb2e8f9f7 31750
<> 144:ef7eb2e8f9f7 31751 #define USBD_DMACTL_DMARD_Pos (4) /*!< USBD DMACTL: DMARD Position */
<> 144:ef7eb2e8f9f7 31752 #define USBD_DMACTL_DMARD_Msk (0x1ul << USBD_DMACTL_DMARD_Pos) /*!< USBD DMACTL: DMARD Mask */
<> 144:ef7eb2e8f9f7 31753
<> 144:ef7eb2e8f9f7 31754 #define USBD_DMACTL_DMAEN_Pos (5) /*!< USBD DMACTL: DMAEN Position */
<> 144:ef7eb2e8f9f7 31755 #define USBD_DMACTL_DMAEN_Msk (0x1ul << USBD_DMACTL_DMAEN_Pos) /*!< USBD DMACTL: DMAEN Mask */
<> 144:ef7eb2e8f9f7 31756
<> 144:ef7eb2e8f9f7 31757 #define USBD_DMACTL_SGEN_Pos (6) /*!< USBD DMACTL: SGEN Position */
<> 144:ef7eb2e8f9f7 31758 #define USBD_DMACTL_SGEN_Msk (0x1ul << USBD_DMACTL_SGEN_Pos) /*!< USBD DMACTL: SGEN Mask */
<> 144:ef7eb2e8f9f7 31759
<> 144:ef7eb2e8f9f7 31760 #define USBD_DMACTL_DMARST_Pos (7) /*!< USBD DMACTL: DMARST Position */
<> 144:ef7eb2e8f9f7 31761 #define USBD_DMACTL_DMARST_Msk (0x1ul << USBD_DMACTL_DMARST_Pos) /*!< USBD DMACTL: DMARST Mask */
<> 144:ef7eb2e8f9f7 31762
<> 144:ef7eb2e8f9f7 31763 #define USBD_DMACNT_DMACNT_Pos (0) /*!< USBD DMACNT: DMACNT Position */
<> 144:ef7eb2e8f9f7 31764 #define USBD_DMACNT_DMACNT_Msk (0xffffful << USBD_DMACNT_DMACNT_Pos) /*!< USBD DMACNT: DMACNT Mask */
<> 144:ef7eb2e8f9f7 31765
<> 144:ef7eb2e8f9f7 31766 #define USBD_EPDAT_EPDAT_Pos (0) /*!< USBD EPDAT: EPDAT Position */
<> 144:ef7eb2e8f9f7 31767 #define USBD_EPDAT_EPDAT_Msk (0xfffffffful << USBD_EPDAT_EPDAT_Pos) /*!< USBD EPDAT: EPDAT Mask */
<> 144:ef7eb2e8f9f7 31768
<> 144:ef7eb2e8f9f7 31769 #define USBD_EPINTSTS_BUFFULLIF_Pos (0) /*!< USBD EPINTSTS: BUFFULLIF Position */
<> 144:ef7eb2e8f9f7 31770 #define USBD_EPINTSTS_BUFFULLIF_Msk (0x1ul << USBD_EPINTSTS_BUFFULLIF_Pos) /*!< USBD EPINTSTS: BUFFULLIF Mask */
<> 144:ef7eb2e8f9f7 31771
<> 144:ef7eb2e8f9f7 31772 #define USBD_EPINTSTS_BUFEMPTYIF_Pos (1) /*!< USBD EPINTSTS: BUFEMPTYIF Position */
<> 144:ef7eb2e8f9f7 31773 #define USBD_EPINTSTS_BUFEMPTYIF_Msk (0x1ul << USBD_EPINTSTS_BUFEMPTYIF_Pos) /*!< USBD EPINTSTS: BUFEMPTYIF Mask */
<> 144:ef7eb2e8f9f7 31774
<> 144:ef7eb2e8f9f7 31775 #define USBD_EPINTSTS_SHORTTXIF_Pos (2) /*!< USBD EPINTSTS: SHORTTXIF Position */
<> 144:ef7eb2e8f9f7 31776 #define USBD_EPINTSTS_SHORTTXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTTXIF_Pos) /*!< USBD EPINTSTS: SHORTTXIF Mask */
<> 144:ef7eb2e8f9f7 31777
<> 144:ef7eb2e8f9f7 31778 #define USBD_EPINTSTS_TXPKIF_Pos (3) /*!< USBD EPINTSTS: TXPKIF Position */
<> 144:ef7eb2e8f9f7 31779 #define USBD_EPINTSTS_TXPKIF_Msk (0x1ul << USBD_EPINTSTS_TXPKIF_Pos) /*!< USBD EPINTSTS: TXPKIF Mask */
<> 144:ef7eb2e8f9f7 31780
<> 144:ef7eb2e8f9f7 31781 #define USBD_EPINTSTS_RXPKIF_Pos (4) /*!< USBD EPINTSTS: RXPKIF Position */
<> 144:ef7eb2e8f9f7 31782 #define USBD_EPINTSTS_RXPKIF_Msk (0x1ul << USBD_EPINTSTS_RXPKIF_Pos) /*!< USBD EPINTSTS: RXPKIF Mask */
<> 144:ef7eb2e8f9f7 31783
<> 144:ef7eb2e8f9f7 31784 #define USBD_EPINTSTS_OUTTKIF_Pos (5) /*!< USBD EPINTSTS: OUTTKIF Position */
<> 144:ef7eb2e8f9f7 31785 #define USBD_EPINTSTS_OUTTKIF_Msk (0x1ul << USBD_EPINTSTS_OUTTKIF_Pos) /*!< USBD EPINTSTS: OUTTKIF Mask */
<> 144:ef7eb2e8f9f7 31786
<> 144:ef7eb2e8f9f7 31787 #define USBD_EPINTSTS_INTKIF_Pos (6) /*!< USBD EPINTSTS: INTKIF Position */
<> 144:ef7eb2e8f9f7 31788 #define USBD_EPINTSTS_INTKIF_Msk (0x1ul << USBD_EPINTSTS_INTKIF_Pos) /*!< USBD EPINTSTS: INTKIF Mask */
<> 144:ef7eb2e8f9f7 31789
<> 144:ef7eb2e8f9f7 31790 #define USBD_EPINTSTS_PINGIF_Pos (7) /*!< USBD EPINTSTS: PINGIF Position */
<> 144:ef7eb2e8f9f7 31791 #define USBD_EPINTSTS_PINGIF_Msk (0x1ul << USBD_EPINTSTS_PINGIF_Pos) /*!< USBD EPINTSTS: PINGIF Mask */
<> 144:ef7eb2e8f9f7 31792
<> 144:ef7eb2e8f9f7 31793 #define USBD_EPINTSTS_NAKIF_Pos (8) /*!< USBD EPINTSTS: NAKIF Position */
<> 144:ef7eb2e8f9f7 31794 #define USBD_EPINTSTS_NAKIF_Msk (0x1ul << USBD_EPINTSTS_NAKIF_Pos) /*!< USBD EPINTSTS: NAKIF Mask */
<> 144:ef7eb2e8f9f7 31795
<> 144:ef7eb2e8f9f7 31796 #define USBD_EPINTSTS_STALLIF_Pos (9) /*!< USBD EPINTSTS: STALLIF Position */
<> 144:ef7eb2e8f9f7 31797 #define USBD_EPINTSTS_STALLIF_Msk (0x1ul << USBD_EPINTSTS_STALLIF_Pos) /*!< USBD EPINTSTS: STALLIF Mask */
<> 144:ef7eb2e8f9f7 31798
<> 144:ef7eb2e8f9f7 31799 #define USBD_EPINTSTS_NYETIF_Pos (10) /*!< USBD EPINTSTS: NYETIF Position */
<> 144:ef7eb2e8f9f7 31800 #define USBD_EPINTSTS_NYETIF_Msk (0x1ul << USBD_EPINTSTS_NYETIF_Pos) /*!< USBD EPINTSTS: NYETIF Mask */
<> 144:ef7eb2e8f9f7 31801
<> 144:ef7eb2e8f9f7 31802 #define USBD_EPINTSTS_ERRIF_Pos (11) /*!< USBD EPINTSTS: ERRIF Position */
<> 144:ef7eb2e8f9f7 31803 #define USBD_EPINTSTS_ERRIF_Msk (0x1ul << USBD_EPINTSTS_ERRIF_Pos) /*!< USBD EPINTSTS: ERRIF Mask */
<> 144:ef7eb2e8f9f7 31804
<> 144:ef7eb2e8f9f7 31805 #define USBD_EPINTSTS_SHORTRXIF_Pos (12) /*!< USBD EPINTSTS: SHORTRXIF Position */
<> 144:ef7eb2e8f9f7 31806 #define USBD_EPINTSTS_SHORTRXIF_Msk (0x1ul << USBD_EPINTSTS_SHORTRXIF_Pos) /*!< USBD EPINTSTS: SHORTRXIF Mask */
<> 144:ef7eb2e8f9f7 31807
<> 144:ef7eb2e8f9f7 31808 #define USBD_EPINTEN_BUFFULLIEN_Pos (0) /*!< USBD EPINTEN: BUFFULLIEN Position */
<> 144:ef7eb2e8f9f7 31809 #define USBD_EPINTEN_BUFFULLIEN_Msk (0x1ul << USBD_EPINTEN_BUFFULLIEN_Pos) /*!< USBD EPINTEN: BUFFULLIEN Mask */
<> 144:ef7eb2e8f9f7 31810
<> 144:ef7eb2e8f9f7 31811 #define USBD_EPINTEN_BUFEMPTYIEN_Pos (1) /*!< USBD EPINTEN: BUFEMPTYIEN Position */
<> 144:ef7eb2e8f9f7 31812 #define USBD_EPINTEN_BUFEMPTYIEN_Msk (0x1ul << USBD_EPINTEN_BUFEMPTYIEN_Pos) /*!< USBD EPINTEN: BUFEMPTYIEN Mask */
<> 144:ef7eb2e8f9f7 31813
<> 144:ef7eb2e8f9f7 31814 #define USBD_EPINTEN_SHORTTXIEN_Pos (2) /*!< USBD EPINTEN: SHORTTXIEN Position */
<> 144:ef7eb2e8f9f7 31815 #define USBD_EPINTEN_SHORTTXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTTXIEN_Pos) /*!< USBD EPINTEN: SHORTTXIEN Mask */
<> 144:ef7eb2e8f9f7 31816
<> 144:ef7eb2e8f9f7 31817 #define USBD_EPINTEN_TXPKIEN_Pos (3) /*!< USBD EPINTEN: TXPKIEN Position */
<> 144:ef7eb2e8f9f7 31818 #define USBD_EPINTEN_TXPKIEN_Msk (0x1ul << USBD_EPINTEN_TXPKIEN_Pos) /*!< USBD EPINTEN: TXPKIEN Mask */
<> 144:ef7eb2e8f9f7 31819
<> 144:ef7eb2e8f9f7 31820 #define USBD_EPINTEN_RXPKIEN_Pos (4) /*!< USBD EPINTEN: RXPKIEN Position */
<> 144:ef7eb2e8f9f7 31821 #define USBD_EPINTEN_RXPKIEN_Msk (0x1ul << USBD_EPINTEN_RXPKIEN_Pos) /*!< USBD EPINTEN: RXPKIEN Mask */
<> 144:ef7eb2e8f9f7 31822
<> 144:ef7eb2e8f9f7 31823 #define USBD_EPINTEN_OUTTKIEN_Pos (5) /*!< USBD EPINTEN: OUTTKIEN Position */
<> 144:ef7eb2e8f9f7 31824 #define USBD_EPINTEN_OUTTKIEN_Msk (0x1ul << USBD_EPINTEN_OUTTKIEN_Pos) /*!< USBD EPINTEN: OUTTKIEN Mask */
<> 144:ef7eb2e8f9f7 31825
<> 144:ef7eb2e8f9f7 31826 #define USBD_EPINTEN_INTKIEN_Pos (6) /*!< USBD EPINTEN: INTKIEN Position */
<> 144:ef7eb2e8f9f7 31827 #define USBD_EPINTEN_INTKIEN_Msk (0x1ul << USBD_EPINTEN_INTKIEN_Pos) /*!< USBD EPINTEN: INTKIEN Mask */
<> 144:ef7eb2e8f9f7 31828
<> 144:ef7eb2e8f9f7 31829 #define USBD_EPINTEN_PINGIEN_Pos (7) /*!< USBD EPINTEN: PINGIEN Position */
<> 144:ef7eb2e8f9f7 31830 #define USBD_EPINTEN_PINGIEN_Msk (0x1ul << USBD_EPINTEN_PINGIEN_Pos) /*!< USBD EPINTEN: PINGIEN Mask */
<> 144:ef7eb2e8f9f7 31831
<> 144:ef7eb2e8f9f7 31832 #define USBD_EPINTEN_NAKIEN_Pos (8) /*!< USBD EPINTEN: NAKIEN Position */
<> 144:ef7eb2e8f9f7 31833 #define USBD_EPINTEN_NAKIEN_Msk (0x1ul << USBD_EPINTEN_NAKIEN_Pos) /*!< USBD EPINTEN: NAKIEN Mask */
<> 144:ef7eb2e8f9f7 31834
<> 144:ef7eb2e8f9f7 31835 #define USBD_EPINTEN_STALLIEN_Pos (9) /*!< USBD EPINTEN: STALLIEN Position */
<> 144:ef7eb2e8f9f7 31836 #define USBD_EPINTEN_STALLIEN_Msk (0x1ul << USBD_EPINTEN_STALLIEN_Pos) /*!< USBD EPINTEN: STALLIEN Mask */
<> 144:ef7eb2e8f9f7 31837
<> 144:ef7eb2e8f9f7 31838 #define USBD_EPINTEN_NYETIEN_Pos (10) /*!< USBD EPINTEN: NYETIEN Position */
<> 144:ef7eb2e8f9f7 31839 #define USBD_EPINTEN_NYETIEN_Msk (0x1ul << USBD_EPINTEN_NYETIEN_Pos) /*!< USBD EPINTEN: NYETIEN Mask */
<> 144:ef7eb2e8f9f7 31840
<> 144:ef7eb2e8f9f7 31841 #define USBD_EPINTEN_ERRIEN_Pos (11) /*!< USBD EPINTEN: ERRIEN Position */
<> 144:ef7eb2e8f9f7 31842 #define USBD_EPINTEN_ERRIEN_Msk (0x1ul << USBD_EPINTEN_ERRIEN_Pos) /*!< USBD EPINTEN: ERRIEN Mask */
<> 144:ef7eb2e8f9f7 31843
<> 144:ef7eb2e8f9f7 31844 #define USBD_EPINTEN_SHORTRXIEN_Pos (12) /*!< USBD EPINTEN: SHORTRXIEN Position */
<> 144:ef7eb2e8f9f7 31845 #define USBD_EPINTEN_SHORTRXIEN_Msk (0x1ul << USBD_EPINTEN_SHORTRXIEN_Pos) /*!< USBD EPINTEN: SHORTRXIEN Mask */
<> 144:ef7eb2e8f9f7 31846
<> 144:ef7eb2e8f9f7 31847 #define USBD_EPDATCNT_DATCNT_Pos (0) /*!< USBD EPDATCNT: DATCNT Position */
<> 144:ef7eb2e8f9f7 31848 #define USBD_EPDATCNT_DATCNT_Msk (0xfffful << USBD_EPDATCNT_DATCNT_Pos) /*!< USBD EPDATCNT: DATCNT Mask */
<> 144:ef7eb2e8f9f7 31849
<> 144:ef7eb2e8f9f7 31850 #define USBD_EPDATCNT_DMALOOP_Pos (16) /*!< USBD EPDATCNT: DMALOOP Position */
<> 144:ef7eb2e8f9f7 31851 #define USBD_EPDATCNT_DMALOOP_Msk (0x7ffful << USBD_EPDATCNT_DMALOOP_Pos) /*!< USBD EPDATCNT: DMALOOP Mask */
<> 144:ef7eb2e8f9f7 31852
<> 144:ef7eb2e8f9f7 31853 #define USBD_EPRSPCTL_FLUSH_Pos (0) /*!< USBD EPRSPCTL: FLUSH Position */
<> 144:ef7eb2e8f9f7 31854 #define USBD_EPRSPCTL_FLUSH_Msk (0x1ul << USBD_EPRSPCTL_FLUSH_Pos) /*!< USBD EPRSPCTL: FLUSH Mask */
<> 144:ef7eb2e8f9f7 31855
<> 144:ef7eb2e8f9f7 31856 #define USBD_EPRSPCTL_MODE_Pos (1) /*!< USBD EPRSPCTL: MODE Position */
<> 144:ef7eb2e8f9f7 31857 #define USBD_EPRSPCTL_MODE_Msk (0x3ul << USBD_EPRSPCTL_MODE_Pos) /*!< USBD EPRSPCTL: MODE Mask */
<> 144:ef7eb2e8f9f7 31858
<> 144:ef7eb2e8f9f7 31859 #define USBD_EPRSPCTL_TOGGLE_Pos (3) /*!< USBD EPRSPCTL: TOGGLE Position */
<> 144:ef7eb2e8f9f7 31860 #define USBD_EPRSPCTL_TOGGLE_Msk (0x1ul << USBD_EPRSPCTL_TOGGLE_Pos) /*!< USBD EPRSPCTL: TOGGLE Mask */
<> 144:ef7eb2e8f9f7 31861
<> 144:ef7eb2e8f9f7 31862 #define USBD_EPRSPCTL_HALT_Pos (4) /*!< USBD EPRSPCTL: HALT Position */
<> 144:ef7eb2e8f9f7 31863 #define USBD_EPRSPCTL_HALT_Msk (0x1ul << USBD_EPRSPCTL_HALT_Pos) /*!< USBD EPRSPCTL: HALT Mask */
<> 144:ef7eb2e8f9f7 31864
<> 144:ef7eb2e8f9f7 31865 #define USBD_EPRSPCTL_ZEROLEN_Pos (5) /*!< USBD EPRSPCTL: ZEROLEN Position */
<> 144:ef7eb2e8f9f7 31866 #define USBD_EPRSPCTL_ZEROLEN_Msk (0x1ul << USBD_EPRSPCTL_ZEROLEN_Pos) /*!< USBD EPRSPCTL: ZEROLEN Mask */
<> 144:ef7eb2e8f9f7 31867
<> 144:ef7eb2e8f9f7 31868 #define USBD_EPRSPCTL_SHORTTXEN_Pos (6) /*!< USBD EPRSPCTL: SHORTTXEN Position */
<> 144:ef7eb2e8f9f7 31869 #define USBD_EPRSPCTL_SHORTTXEN_Msk (0x1ul << USBD_EPRSPCTL_SHORTTXEN_Pos) /*!< USBD EPRSPCTL: SHORTTXEN Mask */
<> 144:ef7eb2e8f9f7 31870
<> 144:ef7eb2e8f9f7 31871 #define USBD_EPRSPCTL_DISBUF_Pos (7) /*!< USBD EPRSPCTL: DISBUF Position */
<> 144:ef7eb2e8f9f7 31872 #define USBD_EPRSPCTL_DISBUF_Msk (0x1ul << USBD_EPRSPCTL_DISBUF_Pos) /*!< USBD EPRSPCTL: DISBUF Mask */
<> 144:ef7eb2e8f9f7 31873
<> 144:ef7eb2e8f9f7 31874 #define USBD_EPMPS_EPMPS_Pos (0) /*!< USBD EPMPS: EPMPS Position */
<> 144:ef7eb2e8f9f7 31875 #define USBD_EPMPS_EPMPS_Msk (0x7fful << USBD_EPMPS_EPMPS_Pos) /*!< USBD EPMPS: EPMPS Mask */
<> 144:ef7eb2e8f9f7 31876
<> 144:ef7eb2e8f9f7 31877 #define USBD_EPTXCNT_TXCNT_Pos (0) /*!< USBD EPTXCNT: TXCNT Position */
<> 144:ef7eb2e8f9f7 31878 #define USBD_EPTXCNT_TXCNT_Msk (0x7fful << USBD_EPTXCNT_TXCNT_Pos) /*!< USBD EPTXCNT: TXCNT Mask */
<> 144:ef7eb2e8f9f7 31879
<> 144:ef7eb2e8f9f7 31880 #define USBD_EPCFG_EPEN_Pos (0) /*!< USBD EPCFG: EPEN Position */
<> 144:ef7eb2e8f9f7 31881 #define USBD_EPCFG_EPEN_Msk (0x1ul << USBD_EPCFG_EPEN_Pos) /*!< USBD EPCFG: EPEN Mask */
<> 144:ef7eb2e8f9f7 31882
<> 144:ef7eb2e8f9f7 31883 #define USBD_EPCFG_EPTYPE_Pos (1) /*!< USBD EPCFG: EPTYPE Position */
<> 144:ef7eb2e8f9f7 31884 #define USBD_EPCFG_EPTYPE_Msk (0x3ul << USBD_EPCFG_EPTYPE_Pos) /*!< USBD EPCFG: EPTYPE Mask */
<> 144:ef7eb2e8f9f7 31885
<> 144:ef7eb2e8f9f7 31886 #define USBD_EPCFG_EPDIR_Pos (3) /*!< USBD EPCFG: EPDIR Position */
<> 144:ef7eb2e8f9f7 31887 #define USBD_EPCFG_EPDIR_Msk (0x1ul << USBD_EPCFG_EPDIR_Pos) /*!< USBD EPCFG: EPDIR Mask */
<> 144:ef7eb2e8f9f7 31888
<> 144:ef7eb2e8f9f7 31889 #define USBD_EPCFG_EPNUM_Pos (4) /*!< USBD EPCFG: EPNUM Position */
<> 144:ef7eb2e8f9f7 31890 #define USBD_EPCFG_EPNUM_Msk (0xful << USBD_EPCFG_EPNUM_Pos) /*!< USBD EPCFG: EPNUM Mask */
<> 144:ef7eb2e8f9f7 31891
<> 144:ef7eb2e8f9f7 31892 #define USBD_EPBUFSTART_SADDR_Pos (0) /*!< USBD EPBUFSTART: SADDR Position */
<> 144:ef7eb2e8f9f7 31893 #define USBD_EPBUFSTART_SADDR_Msk (0xffful << USBD_EPBUFSTART_SADDR_Pos) /*!< USBD EPBUFSTART: SADDR Mask */
<> 144:ef7eb2e8f9f7 31894
<> 144:ef7eb2e8f9f7 31895 #define USBD_EPBUFEND_EADDR_Pos (0) /*!< USBD EPBUFEND: EADDR Position */
<> 144:ef7eb2e8f9f7 31896 #define USBD_EPBUFEND_EADDR_Msk (0xffful << USBD_EPBUFEND_EADDR_Pos) /*!< USBD EPBUFEND: EADDR Mask */
<> 144:ef7eb2e8f9f7 31897
<> 144:ef7eb2e8f9f7 31898 #define USBD_DMAADDR_DMAADDR_Pos (0) /*!< USBD DMAADDR: DMAADDR Position */
<> 144:ef7eb2e8f9f7 31899 #define USBD_DMAADDR_DMAADDR_Msk (0xfffffffful << USBD_DMAADDR_DMAADDR_Pos) /*!< USBD DMAADDR: DMAADDR Mask */
<> 144:ef7eb2e8f9f7 31900
<> 144:ef7eb2e8f9f7 31901 #define USBD_PHYCTL_DPPUEN_Pos (8) /*!< USBD PHYCTL: DPPUEN Position */
<> 144:ef7eb2e8f9f7 31902 #define USBD_PHYCTL_DPPUEN_Msk (0x1ul << USBD_PHYCTL_DPPUEN_Pos) /*!< USBD PHYCTL: DPPUEN Mask */
<> 144:ef7eb2e8f9f7 31903
<> 144:ef7eb2e8f9f7 31904 #define USBD_PHYCTL_PHYEN_Pos (9) /*!< USBD PHYCTL: PHYEN Position */
<> 144:ef7eb2e8f9f7 31905 #define USBD_PHYCTL_PHYEN_Msk (0x1ul << USBD_PHYCTL_PHYEN_Pos) /*!< USBD PHYCTL: PHYEN Mask */
<> 144:ef7eb2e8f9f7 31906
<> 144:ef7eb2e8f9f7 31907 #define USBD_PHYCTL_WKEN_Pos (24) /*!< USBD PHYCTL: WKEN Position */
<> 144:ef7eb2e8f9f7 31908 #define USBD_PHYCTL_WKEN_Msk (0x1ul << USBD_PHYCTL_WKEN_Pos) /*!< USBD PHYCTL: WKEN Mask */
<> 144:ef7eb2e8f9f7 31909
<> 144:ef7eb2e8f9f7 31910 #define USBD_PHYCTL_VBUSDET_Pos (31) /*!< USBD PHYCTL: VBUSDET Position */
<> 144:ef7eb2e8f9f7 31911 #define USBD_PHYCTL_VBUSDET_Msk (0x1ul << USBD_PHYCTL_VBUSDET_Pos) /*!< USBD PHYCTL: VBUSDET Mask */
<> 144:ef7eb2e8f9f7 31912
<> 144:ef7eb2e8f9f7 31913 /**@}*/ /* USBD_CONST */
<> 144:ef7eb2e8f9f7 31914 /**@}*/ /* end of USBD register group */
<> 144:ef7eb2e8f9f7 31915
<> 144:ef7eb2e8f9f7 31916
<> 144:ef7eb2e8f9f7 31917 /*---------------------- Watch Dog Timer Controller -------------------------*/
<> 144:ef7eb2e8f9f7 31918 /**
<> 144:ef7eb2e8f9f7 31919 @addtogroup WDT Watch Dog Timer Controller(WDT)
<> 144:ef7eb2e8f9f7 31920 Memory Mapped Structure for WDT Controller
<> 144:ef7eb2e8f9f7 31921 @{ */
<> 144:ef7eb2e8f9f7 31922
<> 144:ef7eb2e8f9f7 31923 typedef struct {
<> 144:ef7eb2e8f9f7 31924
<> 144:ef7eb2e8f9f7 31925
<> 144:ef7eb2e8f9f7 31926 /**
<> 144:ef7eb2e8f9f7 31927 * CTL
<> 144:ef7eb2e8f9f7 31928 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31929 * Offset: 0x00 Watchdog Timer Control Register
<> 144:ef7eb2e8f9f7 31930 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31931 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31932 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31933 * |[0] |RSTCNT |Clear Watchdog Timer (Write Protect)
<> 144:ef7eb2e8f9f7 31934 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 31935 * | | |1 = Reset the internal 18-bit WDT counter.
<> 144:ef7eb2e8f9f7 31936 * | | |Note: This bit will be automatically cleared by hardware.
<> 144:ef7eb2e8f9f7 31937 * |[1] |RSTEN |Watchdog Timer Reset Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 31938 * | | |Setting this bit will enable the Watchdog Timer time-out reset function If the WDT counter value has not been cleared after the specific WDT reset delay period expires.
<> 144:ef7eb2e8f9f7 31939 * | | |0 = Watchdog Timer time-out reset function Disabled.
<> 144:ef7eb2e8f9f7 31940 * | | |1 = Watchdog Timer time-out reset function Enabled.
<> 144:ef7eb2e8f9f7 31941 * |[2] |RSTF |Watchdog Timer Reset Flag
<> 144:ef7eb2e8f9f7 31942 * | | |This bit indicates the system has been reset by WDT time-out reset or not.
<> 144:ef7eb2e8f9f7 31943 * | | |0 = Watchdog Timer time-out reset did not occur.
<> 144:ef7eb2e8f9f7 31944 * | | |1 = Watchdog Timer time-out reset occurred.
<> 144:ef7eb2e8f9f7 31945 * | | |Note: This bit is cleared by writing 1 to this bit.
<> 144:ef7eb2e8f9f7 31946 * |[3] |IF |Watchdog Timer Interrupt Flag
<> 144:ef7eb2e8f9f7 31947 * | | |This bit will set to 1 while WDT counter value reaches the selected WDT time-out interval
<> 144:ef7eb2e8f9f7 31948 * | | |0 = Watchdog Timer time-out interrupt did not occur.
<> 144:ef7eb2e8f9f7 31949 * | | |1 = Watchdog Timer time-out interrupt occurred.
<> 144:ef7eb2e8f9f7 31950 * | | |Note: This bit is cleared by writing 1 to this bit.
<> 144:ef7eb2e8f9f7 31951 * |[4] |WKEN |Watchdog Timer Wake-Up Function Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 31952 * | | |If this bit is set to 1, while WDT interrupt flag (WDT_CTL[3] IF) is generated to 1 and INTEN (WDT_CTL[6] WDT interrupt enable) is enabled, the WDT time-out interrupt signal will generate a wake-up trigger event to chip.
<> 144:ef7eb2e8f9f7 31953 * | | |0 = Wake-up trigger event Disabled if WDT time-out interrupt signal generated.
<> 144:ef7eb2e8f9f7 31954 * | | |1 = Wake-up trigger event Enabled if WDT time-out interrupt signal generated.
<> 144:ef7eb2e8f9f7 31955 * | | |Note: Chip can be woken-up by WDT time-out interrupt signal generated only if WDT clock source is selected to 10 kHz oscillator.
<> 144:ef7eb2e8f9f7 31956 * |[5] |WKF |Watchdog Timer Wake-Up Flag
<> 144:ef7eb2e8f9f7 31957 * | | |This bit indicates the interrupt wake-up flag status of WDT
<> 144:ef7eb2e8f9f7 31958 * | | |0 = Watchdog Timer does not cause chip wake-up.
<> 144:ef7eb2e8f9f7 31959 * | | |1 = Chip wake-up from Idle or Power-down mode if WDT time-out interrupt signal generated.
<> 144:ef7eb2e8f9f7 31960 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 31961 * |[6] |INTEN |Watchdog Timer Interrupt Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 31962 * | | |If this bit is enabled, the WDT time-out interrupt signal is generated and inform to CPU.
<> 144:ef7eb2e8f9f7 31963 * | | |0 = Watchdog Timer interrupt Disabled.
<> 144:ef7eb2e8f9f7 31964 * | | |1 = Watchdog Timer interrupt Enabled.
<> 144:ef7eb2e8f9f7 31965 * |[7] |WDTEN |Watchdog Timer Enable Control (Write Protect)
<> 144:ef7eb2e8f9f7 31966 * | | |0 = Watchdog Timer Disabled (This action will reset the internal counter).
<> 144:ef7eb2e8f9f7 31967 * | | |1 = Watchdog Timer Enabled.
<> 144:ef7eb2e8f9f7 31968 * | | |Note: If CWDTEN (Config0[31] watchdog enable) bit is set to 0, this bit is forced as 1 and software cannot change this bit to 0.
<> 144:ef7eb2e8f9f7 31969 * |[8:10] |TOUTSEL |Watchdog Timer Time-Out Interval Selection (Write Protect)
<> 144:ef7eb2e8f9f7 31970 * | | |These three bits select the time-out interval period for the Watchdog Timer.
<> 144:ef7eb2e8f9f7 31971 * | | |000 = 2^4 * TWDT.
<> 144:ef7eb2e8f9f7 31972 * | | |001 = 2^6 * TWDT.
<> 144:ef7eb2e8f9f7 31973 * | | |010 = 2^8 * TWDT.
<> 144:ef7eb2e8f9f7 31974 * | | |011 = 2^10 * TWDT.
<> 144:ef7eb2e8f9f7 31975 * | | |100 = 2^12 * TWDT.
<> 144:ef7eb2e8f9f7 31976 * | | |101 = 2^14 * TWDT.
<> 144:ef7eb2e8f9f7 31977 * | | |110 = 2^16 * TWDT.
<> 144:ef7eb2e8f9f7 31978 * | | |111 = 2^18 * TWDT.
<> 144:ef7eb2e8f9f7 31979 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control (Write Protect)
<> 144:ef7eb2e8f9f7 31980 * | | |0 = ICE debug mode acknowledgement affects Watchdog Timer counting.
<> 144:ef7eb2e8f9f7 31981 * | | |Watchdog Timer counter will be held while CPU is held by ICE.
<> 144:ef7eb2e8f9f7 31982 * | | |1 = ICE debug mode acknowledgement Disabled.
<> 144:ef7eb2e8f9f7 31983 * | | |Watchdog Timer counter will keep going no matter CPU is held by ICE or not.
<> 144:ef7eb2e8f9f7 31984 */
<> 144:ef7eb2e8f9f7 31985 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 31986
<> 144:ef7eb2e8f9f7 31987 /**
<> 144:ef7eb2e8f9f7 31988 * ALTCTL
<> 144:ef7eb2e8f9f7 31989 * ===================================================================================================
<> 144:ef7eb2e8f9f7 31990 * Offset: 0x04 Watchdog Timer Alternative Control Register
<> 144:ef7eb2e8f9f7 31991 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 31992 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 31993 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 31994 * |[0:1] |RSTDSEL |Watchdog Timer Reset Delay Selection (Write Protect)
<> 144:ef7eb2e8f9f7 31995 * | | |When WDT time-out happened, software has a time named WDT reset delay period to clear WDT counter to prevent WDT time-out reset happened.
<> 144:ef7eb2e8f9f7 31996 * | | |Software can select a suitable value of WDT reset delay period for different WDT time-out period.
<> 144:ef7eb2e8f9f7 31997 * | | |00 = Watchdog Timer reset delay period is (1024+2) * WDT_CLK.
<> 144:ef7eb2e8f9f7 31998 * | | |01 = Watchdog Timer reset delay period is (128+2) * WDT_CLK.
<> 144:ef7eb2e8f9f7 31999 * | | |10 = Watchdog Timer reset delay period is (16+2) * WDT_CLK.
<> 144:ef7eb2e8f9f7 32000 * | | |11 = Watchdog Timer reset delay period is (1+2) * WDT_CLK.
<> 144:ef7eb2e8f9f7 32001 * | | |Note: This register will be reset to 0 if WDT time-out reset happened
<> 144:ef7eb2e8f9f7 32002 */
<> 144:ef7eb2e8f9f7 32003 __IO uint32_t ALTCTL;
<> 144:ef7eb2e8f9f7 32004
<> 144:ef7eb2e8f9f7 32005 } WDT_T;
<> 144:ef7eb2e8f9f7 32006
<> 144:ef7eb2e8f9f7 32007 /**
<> 144:ef7eb2e8f9f7 32008 @addtogroup WDT_CONST WDT Bit Field Definition
<> 144:ef7eb2e8f9f7 32009 Constant Definitions for WDT Controller
<> 144:ef7eb2e8f9f7 32010 @{ */
<> 144:ef7eb2e8f9f7 32011
<> 144:ef7eb2e8f9f7 32012 #define WDT_CTL_RSTCNT_Pos (0) /*!< WDT CTL: RSTCNT Position */
<> 144:ef7eb2e8f9f7 32013 #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) /*!< WDT CTL: RSTCNT Mask */
<> 144:ef7eb2e8f9f7 32014
<> 144:ef7eb2e8f9f7 32015 #define WDT_CTL_RSTEN_Pos (1) /*!< WDT CTL: RSTEN Position */
<> 144:ef7eb2e8f9f7 32016 #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) /*!< WDT CTL: RSTEN Mask */
<> 144:ef7eb2e8f9f7 32017
<> 144:ef7eb2e8f9f7 32018 #define WDT_CTL_RSTF_Pos (2) /*!< WDT CTL: RSTF Position */
<> 144:ef7eb2e8f9f7 32019 #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) /*!< WDT CTL: RSTF Mask */
<> 144:ef7eb2e8f9f7 32020
<> 144:ef7eb2e8f9f7 32021 #define WDT_CTL_IF_Pos (3) /*!< WDT CTL: IF Position */
<> 144:ef7eb2e8f9f7 32022 #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) /*!< WDT CTL: IF Mask */
<> 144:ef7eb2e8f9f7 32023
<> 144:ef7eb2e8f9f7 32024 #define WDT_CTL_WKEN_Pos (4) /*!< WDT CTL: WKEN Position */
<> 144:ef7eb2e8f9f7 32025 #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) /*!< WDT CTL: WKEN Mask */
<> 144:ef7eb2e8f9f7 32026
<> 144:ef7eb2e8f9f7 32027 #define WDT_CTL_WKF_Pos (5) /*!< WDT CTL: WKF Position */
<> 144:ef7eb2e8f9f7 32028 #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) /*!< WDT CTL: WKF Mask */
<> 144:ef7eb2e8f9f7 32029
<> 144:ef7eb2e8f9f7 32030 #define WDT_CTL_INTEN_Pos (6) /*!< WDT CTL: INTEN Position */
<> 144:ef7eb2e8f9f7 32031 #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) /*!< WDT CTL: INTEN Mask */
<> 144:ef7eb2e8f9f7 32032
<> 144:ef7eb2e8f9f7 32033 #define WDT_CTL_WDTEN_Pos (7) /*!< WDT CTL: WDTEN Position */
<> 144:ef7eb2e8f9f7 32034 #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) /*!< WDT CTL: WDTEN Mask */
<> 144:ef7eb2e8f9f7 32035
<> 144:ef7eb2e8f9f7 32036 #define WDT_CTL_TOUTSEL_Pos (8) /*!< WDT CTL: TOUTSEL Position */
<> 144:ef7eb2e8f9f7 32037 #define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) /*!< WDT CTL: TOUTSEL Mask */
<> 144:ef7eb2e8f9f7 32038
<> 144:ef7eb2e8f9f7 32039 #define WDT_CTL_ICEDEBUG_Pos (31) /*!< WDT CTL: ICEDEBUG Position */
<> 144:ef7eb2e8f9f7 32040 #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) /*!< WDT CTL: ICEDEBUG Mask */
<> 144:ef7eb2e8f9f7 32041
<> 144:ef7eb2e8f9f7 32042 #define WDT_ALTCTL_RSTDSEL_Pos (0) /*!< WDT ALTCTL: RSTDSEL Position */
<> 144:ef7eb2e8f9f7 32043 #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) /*!< WDT ALTCTL: RSTDSEL Mask */
<> 144:ef7eb2e8f9f7 32044
<> 144:ef7eb2e8f9f7 32045 /**@}*/ /* WDT_CONST */
<> 144:ef7eb2e8f9f7 32046 /**@}*/ /* end of WDT register group */
<> 144:ef7eb2e8f9f7 32047
<> 144:ef7eb2e8f9f7 32048
<> 144:ef7eb2e8f9f7 32049 /*---------------------- Window Watchdog Timer -------------------------*/
<> 144:ef7eb2e8f9f7 32050 /**
<> 144:ef7eb2e8f9f7 32051 @addtogroup WWDT Window Watchdog Timer(WWDT)
<> 144:ef7eb2e8f9f7 32052 Memory Mapped Structure for WWDT Controller
<> 144:ef7eb2e8f9f7 32053 @{ */
<> 144:ef7eb2e8f9f7 32054
<> 144:ef7eb2e8f9f7 32055 typedef struct {
<> 144:ef7eb2e8f9f7 32056
<> 144:ef7eb2e8f9f7 32057
<> 144:ef7eb2e8f9f7 32058 /**
<> 144:ef7eb2e8f9f7 32059 * RLDCNT
<> 144:ef7eb2e8f9f7 32060 * ===================================================================================================
<> 144:ef7eb2e8f9f7 32061 * Offset: 0x00 Window Watchdog Timer Reload Counter Register
<> 144:ef7eb2e8f9f7 32062 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32063 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 32064 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 32065 * |[0:31] |RLDCNT |WWDT Reload Counter Bit
<> 144:ef7eb2e8f9f7 32066 * | | |Writing 0x00005AA5 to this register will reload the Window Watchdog Timer counter value to 0x3F.
<> 144:ef7eb2e8f9f7 32067 * | | |Note: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
<> 144:ef7eb2e8f9f7 32068 * | | |If software writes RLDCNT when current WWDT counter value is larger than CMPDAT, WWDT reset signal will generate immediately.
<> 144:ef7eb2e8f9f7 32069 */
<> 144:ef7eb2e8f9f7 32070 __O uint32_t RLDCNT;
<> 144:ef7eb2e8f9f7 32071
<> 144:ef7eb2e8f9f7 32072 /**
<> 144:ef7eb2e8f9f7 32073 * CTL
<> 144:ef7eb2e8f9f7 32074 * ===================================================================================================
<> 144:ef7eb2e8f9f7 32075 * Offset: 0x04 Window Watchdog Timer Control Register
<> 144:ef7eb2e8f9f7 32076 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32077 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 32078 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 32079 * |[0] |WWDTEN |WWDT Enable Control
<> 144:ef7eb2e8f9f7 32080 * | | |Set this bit to enable Window Watchdog Timer counter counting.
<> 144:ef7eb2e8f9f7 32081 * | | |0 = Window Watchdog Timer counter is stopped.
<> 144:ef7eb2e8f9f7 32082 * | | |1 = Window Watchdog Timer counter is starting counting.
<> 144:ef7eb2e8f9f7 32083 * |[1] |INTEN |WWDT Interrupt Enable Control
<> 144:ef7eb2e8f9f7 32084 * | | |If this bit is enabled, the WWDT counter compare match interrupt signal is generated and inform to CPU.
<> 144:ef7eb2e8f9f7 32085 * | | |0 = WWDT counter compare match interrupt Disabled.
<> 144:ef7eb2e8f9f7 32086 * | | |1 = WWDT counter compare match interrupt Enabled.
<> 144:ef7eb2e8f9f7 32087 * |[8:11] |PSCSEL |WWDT Counter Prescale Period Selection
<> 144:ef7eb2e8f9f7 32088 * | | |0000 = Pre-scale is 1; Max time-out period is 1 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32089 * | | |0001 = Pre-scale is 2; Max time-out period is 2 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32090 * | | |0010 = Pre-scale is 4; Max time-out period is 4 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32091 * | | |0011 = Pre-scale is 8; Max time-out period is 8 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32092 * | | |0100 = Pre-scale is 16; Max time-out period is 16 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32093 * | | |0101 = Pre-scale is 32; Max time-out period is 32 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32094 * | | |0110 = Pre-scale is 64; Max time-out period is 64 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32095 * | | |0111 = Pre-scale is 128; Max time-out period is 128 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32096 * | | |1000 = Pre-scale is 192; Max time-out period is 192 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32097 * | | |1001 = Pre-scale is 256; Max time-out period is 256 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32098 * | | |1010 = Pre-scale is 384; Max time-out period is 384 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32099 * | | |1011 = Pre-scale is 512; Max time-out period is 512 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32100 * | | |1100 = Pre-scale is 768; Max time-out period is 768 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32101 * | | |1101 = Pre-scale is 1024; Max time-out period is 1024 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32102 * | | |1110 = Pre-scale is 1536; Max time-out period is 1536 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32103 * | | |1111 = Pre-scale is 2048; Max time-out period is 2048 * 64 * TWWDT.
<> 144:ef7eb2e8f9f7 32104 * |[16:21] |CMPDAT |WWDT Window Compare Bits
<> 144:ef7eb2e8f9f7 32105 * | | |Set this register to adjust the valid reload window.
<> 144:ef7eb2e8f9f7 32106 * | | |Note: Software can only write RLDCNT to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.
<> 144:ef7eb2e8f9f7 32107 * | | |If Software writes RLDCNT when current WWDT counter value larger than CMPDAT, WWDT reset signal will generate immediately.
<> 144:ef7eb2e8f9f7 32108 * |[31] |ICEDEBUG |ICE Debug Mode Acknowledge Disable Control
<> 144:ef7eb2e8f9f7 32109 * | | |0 = ICE debug mode acknowledgement effects WWDT counting.
<> 144:ef7eb2e8f9f7 32110 * | | |WWDT down counter will be held while CPU is held by ICE.
<> 144:ef7eb2e8f9f7 32111 * | | |1 = ICE debug mode acknowledgement Disabled.
<> 144:ef7eb2e8f9f7 32112 * | | |WWDT down counter will keep going no matter CPU is held by ICE or not.
<> 144:ef7eb2e8f9f7 32113 */
<> 144:ef7eb2e8f9f7 32114 __IO uint32_t CTL;
<> 144:ef7eb2e8f9f7 32115
<> 144:ef7eb2e8f9f7 32116 /**
<> 144:ef7eb2e8f9f7 32117 * STATUS
<> 144:ef7eb2e8f9f7 32118 * ===================================================================================================
<> 144:ef7eb2e8f9f7 32119 * Offset: 0x08 Window Watchdog Timer Status Register
<> 144:ef7eb2e8f9f7 32120 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32121 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 32122 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 32123 * |[0] |WWDTIF |WWDT Compare Match Interrupt Flag
<> 144:ef7eb2e8f9f7 32124 * | | |This bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT value.
<> 144:ef7eb2e8f9f7 32125 * | | |0 = No effect.
<> 144:ef7eb2e8f9f7 32126 * | | |1 = WWDT counter value matches CMPDAT value.
<> 144:ef7eb2e8f9f7 32127 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 32128 * |[1] |WWDTRF |WWDT Timer-Out Reset Flag
<> 144:ef7eb2e8f9f7 32129 * | | |This bit indicates the system has been reset by WWDT time-out reset or not.
<> 144:ef7eb2e8f9f7 32130 * | | |0 = WWDT time-out reset did not occur.
<> 144:ef7eb2e8f9f7 32131 * | | |1 = WWDT time-out reset occurred.
<> 144:ef7eb2e8f9f7 32132 * | | |Note: This bit is cleared by writing 1 to it.
<> 144:ef7eb2e8f9f7 32133 */
<> 144:ef7eb2e8f9f7 32134 __IO uint32_t STATUS;
<> 144:ef7eb2e8f9f7 32135
<> 144:ef7eb2e8f9f7 32136 /**
<> 144:ef7eb2e8f9f7 32137 * CNT
<> 144:ef7eb2e8f9f7 32138 * ===================================================================================================
<> 144:ef7eb2e8f9f7 32139 * Offset: 0x0C Window Watchdog Timer Counter Value Register
<> 144:ef7eb2e8f9f7 32140 * ---------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 32141 * |Bits |Field |Descriptions
<> 144:ef7eb2e8f9f7 32142 * | :----: | :----: | :---- |
<> 144:ef7eb2e8f9f7 32143 * |[0:5] |CNTDAT |WWDT Counter Value
<> 144:ef7eb2e8f9f7 32144 * | | |This register reflects the current WWDT counter value and is read only.
<> 144:ef7eb2e8f9f7 32145 */
<> 144:ef7eb2e8f9f7 32146 __I uint32_t CNT;
<> 144:ef7eb2e8f9f7 32147
<> 144:ef7eb2e8f9f7 32148 } WWDT_T;
<> 144:ef7eb2e8f9f7 32149
<> 144:ef7eb2e8f9f7 32150 /**
<> 144:ef7eb2e8f9f7 32151 @addtogroup WWDT_CONST WWDT Bit Field Definition
<> 144:ef7eb2e8f9f7 32152 Constant Definitions for WWDT Controller
<> 144:ef7eb2e8f9f7 32153 @{ */
<> 144:ef7eb2e8f9f7 32154
<> 144:ef7eb2e8f9f7 32155 #define WWDT_RLDCNT_RLDCNT_Pos (0) /*!< WWDT RLDCNT: RLDCNT Position */
<> 144:ef7eb2e8f9f7 32156 #define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) /*!< WWDT RLDCNT: RLDCNT Mask */
<> 144:ef7eb2e8f9f7 32157
<> 144:ef7eb2e8f9f7 32158 #define WWDT_CTL_WWDTEN_Pos (0) /*!< WWDT CTL: WWDTEN Position */
<> 144:ef7eb2e8f9f7 32159 #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) /*!< WWDT CTL: WWDTEN Mask */
<> 144:ef7eb2e8f9f7 32160
<> 144:ef7eb2e8f9f7 32161 #define WWDT_CTL_INTEN_Pos (1) /*!< WWDT CTL: INTEN Position */
<> 144:ef7eb2e8f9f7 32162 #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) /*!< WWDT CTL: INTEN Mask */
<> 144:ef7eb2e8f9f7 32163
<> 144:ef7eb2e8f9f7 32164 #define WWDT_CTL_PSCSEL_Pos (8) /*!< WWDT CTL: PSCSEL Position */
<> 144:ef7eb2e8f9f7 32165 #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) /*!< WWDT CTL: PSCSEL Mask */
<> 144:ef7eb2e8f9f7 32166
<> 144:ef7eb2e8f9f7 32167 #define WWDT_CTL_CMPDAT_Pos (16) /*!< WWDT CTL: CMPDAT Position */
<> 144:ef7eb2e8f9f7 32168 #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) /*!< WWDT CTL: CMPDAT Mask */
<> 144:ef7eb2e8f9f7 32169
<> 144:ef7eb2e8f9f7 32170 #define WWDT_CTL_ICEDEBUG_Pos (31) /*!< WWDT CTL: ICEDEBUG Position */
<> 144:ef7eb2e8f9f7 32171 #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) /*!< WWDT CTL: ICEDEBUG Mask */
<> 144:ef7eb2e8f9f7 32172
<> 144:ef7eb2e8f9f7 32173 #define WWDT_STATUS_WWDTIF_Pos (0) /*!< WWDT STATUS: WWDTIF Position */
<> 144:ef7eb2e8f9f7 32174 #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) /*!< WWDT STATUS: WWDTIF Mask */
<> 144:ef7eb2e8f9f7 32175
<> 144:ef7eb2e8f9f7 32176 #define WWDT_STATUS_WWDTRF_Pos (1) /*!< WWDT STATUS: WWDTRF Position */
<> 144:ef7eb2e8f9f7 32177 #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) /*!< WWDT STATUS: WWDTRF Mask */
<> 144:ef7eb2e8f9f7 32178
<> 144:ef7eb2e8f9f7 32179 #define WWDT_CNT_CNTDAT_Pos (0) /*!< WWDT CNT: CNTDAT Position */
<> 144:ef7eb2e8f9f7 32180 #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) /*!< WWDT CNT: CNTDAT Mask */
<> 144:ef7eb2e8f9f7 32181
<> 144:ef7eb2e8f9f7 32182 /**@}*/ /* WWDT_CONST */
<> 144:ef7eb2e8f9f7 32183 /**@}*/ /* end of WWDT register group */
<> 144:ef7eb2e8f9f7 32184
<> 144:ef7eb2e8f9f7 32185 #if defined ( __CC_ARM )
<> 144:ef7eb2e8f9f7 32186 #pragma no_anon_unions
<> 144:ef7eb2e8f9f7 32187 #endif
<> 144:ef7eb2e8f9f7 32188
<> 144:ef7eb2e8f9f7 32189
<> 144:ef7eb2e8f9f7 32190 /*@}*/ /* end of group NUC472_442_Peripherals */
<> 144:ef7eb2e8f9f7 32191
<> 144:ef7eb2e8f9f7 32192 /** @addtogroup NUC472_442_PERIPHERAL_MEM_MAP NUC472/NUC442 Peripheral Memory Base
<> 144:ef7eb2e8f9f7 32193 Memory Mapped Structure for NUC472/NUC442 Peripheral
<> 144:ef7eb2e8f9f7 32194 @{
<> 144:ef7eb2e8f9f7 32195 */
<> 144:ef7eb2e8f9f7 32196 /* Peripheral and SRAM base address */
<> 144:ef7eb2e8f9f7 32197 #define FLASH_BASE ((uint32_t)0x00000000) /*!< Flash base address */
<> 144:ef7eb2e8f9f7 32198 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM Base Address */
<> 144:ef7eb2e8f9f7 32199 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral Base Address */
<> 144:ef7eb2e8f9f7 32200 #define AHBPERIPH_BASE PERIPH_BASE /*!< AHB Base Address */
<> 144:ef7eb2e8f9f7 32201 #define APBPERIPH_BASE (PERIPH_BASE + 0x00040000) /*!< APB Base Address */
<> 144:ef7eb2e8f9f7 32202
<> 144:ef7eb2e8f9f7 32203 /*!< AHB peripherals */
<> 144:ef7eb2e8f9f7 32204 #define SYS_BASE (AHBPERIPH_BASE + 0x00000)
<> 144:ef7eb2e8f9f7 32205 #define CLK_BASE (AHBPERIPH_BASE + 0x00200)
<> 144:ef7eb2e8f9f7 32206 #define GPIOA_BASE (AHBPERIPH_BASE + 0x04000)
<> 144:ef7eb2e8f9f7 32207 #define GPIOB_BASE (AHBPERIPH_BASE + 0x04040)
<> 144:ef7eb2e8f9f7 32208 #define GPIOC_BASE (AHBPERIPH_BASE + 0x04080)
<> 144:ef7eb2e8f9f7 32209 #define GPIOD_BASE (AHBPERIPH_BASE + 0x040C0)
<> 144:ef7eb2e8f9f7 32210 #define GPIOE_BASE (AHBPERIPH_BASE + 0x04100)
<> 144:ef7eb2e8f9f7 32211 #define GPIOF_BASE (AHBPERIPH_BASE + 0x04140)
<> 144:ef7eb2e8f9f7 32212 #define GPIOG_BASE (AHBPERIPH_BASE + 0x04180)
<> 144:ef7eb2e8f9f7 32213 #define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0)
<> 144:ef7eb2e8f9f7 32214 #define GPIOI_BASE (AHBPERIPH_BASE + 0x04200)
<> 144:ef7eb2e8f9f7 32215 #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440)
<> 144:ef7eb2e8f9f7 32216 #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800)
<> 144:ef7eb2e8f9f7 32217 #define PDMA_BASE (AHBPERIPH_BASE + 0x08000)
<> 144:ef7eb2e8f9f7 32218 #define USBH_BASE (AHBPERIPH_BASE + 0x09000)
<> 144:ef7eb2e8f9f7 32219 #define EMAC_BASE (AHBPERIPH_BASE + 0x0B000)
<> 144:ef7eb2e8f9f7 32220 #define FMC_BASE (AHBPERIPH_BASE + 0x0C000)
<> 144:ef7eb2e8f9f7 32221 #define SD_BASE (AHBPERIPH_BASE + 0x0D000)
<> 144:ef7eb2e8f9f7 32222 #define EBI_BASE (AHBPERIPH_BASE + 0x10000)
<> 144:ef7eb2e8f9f7 32223 #define UDC20_BASE (AHBPERIPH_BASE + 0x19000)
<> 144:ef7eb2e8f9f7 32224 #define CAP_BASE (AHBPERIPH_BASE + 0x30000)
<> 144:ef7eb2e8f9f7 32225 #define CRC_BASE (AHBPERIPH_BASE + 0x31000)
<> 144:ef7eb2e8f9f7 32226 #define TAMPER_BASE (AHBPERIPH_BASE + 0xE1000)
<> 144:ef7eb2e8f9f7 32227
<> 144:ef7eb2e8f9f7 32228 /*!< APB2 peripherals */
<> 144:ef7eb2e8f9f7 32229 #define WDT_BASE (APBPERIPH_BASE + 0x00000)
<> 144:ef7eb2e8f9f7 32230 #define WWDT_BASE (APBPERIPH_BASE + 0x00100)
<> 144:ef7eb2e8f9f7 32231 #define OPA_BASE (APBPERIPH_BASE + 0x06000)
<> 144:ef7eb2e8f9f7 32232 #define I2S0_BASE (APBPERIPH_BASE + 0x08000)
<> 144:ef7eb2e8f9f7 32233 #define TIMER0_BASE (APBPERIPH_BASE + 0x10000)
<> 144:ef7eb2e8f9f7 32234 #define TIMER1_BASE (APBPERIPH_BASE + 0x10020)
<> 144:ef7eb2e8f9f7 32235 #define PWM0_BASE (APBPERIPH_BASE + 0x18000)
<> 144:ef7eb2e8f9f7 32236 #define EPWM0_BASE (APBPERIPH_BASE + 0x1C000)
<> 144:ef7eb2e8f9f7 32237 #define SPI0_BASE (APBPERIPH_BASE + 0x20000)
<> 144:ef7eb2e8f9f7 32238 #define SPI2_BASE (APBPERIPH_BASE + 0x22000)
<> 144:ef7eb2e8f9f7 32239 #define UART0_BASE (APBPERIPH_BASE + 0x30000)
<> 144:ef7eb2e8f9f7 32240 #define UART2_BASE (APBPERIPH_BASE + 0x32000)
<> 144:ef7eb2e8f9f7 32241 #define UART4_BASE (APBPERIPH_BASE + 0x34000)
<> 144:ef7eb2e8f9f7 32242 #define I2C0_BASE (APBPERIPH_BASE + 0x40000)
<> 144:ef7eb2e8f9f7 32243 #define I2C2_BASE (APBPERIPH_BASE + 0x42000)
<> 144:ef7eb2e8f9f7 32244 #define I2C4_BASE (APBPERIPH_BASE + 0x44000)
<> 144:ef7eb2e8f9f7 32245 #define SC0_BASE (APBPERIPH_BASE + 0x50000)
<> 144:ef7eb2e8f9f7 32246 #define SC2_BASE (APBPERIPH_BASE + 0x52000)
<> 144:ef7eb2e8f9f7 32247 #define SC4_BASE (APBPERIPH_BASE + 0x54000)
<> 144:ef7eb2e8f9f7 32248 #define CAN0_BASE (APBPERIPH_BASE + 0x60000)
<> 144:ef7eb2e8f9f7 32249 #define QEI0_BASE (APBPERIPH_BASE + 0x70000)
<> 144:ef7eb2e8f9f7 32250 #define ECAP0_BASE (APBPERIPH_BASE + 0x74000)
<> 144:ef7eb2e8f9f7 32251 #define PS2D_BASE (APBPERIPH_BASE + 0xA0000)
<> 144:ef7eb2e8f9f7 32252
<> 144:ef7eb2e8f9f7 32253 /*!< APB1 peripherals */
<> 144:ef7eb2e8f9f7 32254 #define RTC_BASE (APBPERIPH_BASE + 0x01000)
<> 144:ef7eb2e8f9f7 32255 #define ADC_BASE (APBPERIPH_BASE + 0x03000)
<> 144:ef7eb2e8f9f7 32256 #define EADC_BASE (APBPERIPH_BASE + 0x04000)
<> 144:ef7eb2e8f9f7 32257 #define ACMP_BASE (APBPERIPH_BASE + 0x05000)
<> 144:ef7eb2e8f9f7 32258 #define I2S1_BASE (APBPERIPH_BASE + 0x09000)
<> 144:ef7eb2e8f9f7 32259 #define OTG_BASE (APBPERIPH_BASE + 0x0D000)
<> 144:ef7eb2e8f9f7 32260 #define TIMER2_BASE (APBPERIPH_BASE + 0x11000)
<> 144:ef7eb2e8f9f7 32261 #define TIMER3_BASE (APBPERIPH_BASE + 0x11020)
<> 144:ef7eb2e8f9f7 32262 #define PWM1_BASE (APBPERIPH_BASE + 0x19000)
<> 144:ef7eb2e8f9f7 32263 #define EPWM1_BASE (APBPERIPH_BASE + 0x1D000)
<> 144:ef7eb2e8f9f7 32264 #define SPI1_BASE (APBPERIPH_BASE + 0x21000)
<> 144:ef7eb2e8f9f7 32265 #define SPI3_BASE (APBPERIPH_BASE + 0x23000)
<> 144:ef7eb2e8f9f7 32266 #define UART1_BASE (APBPERIPH_BASE + 0x31000)
<> 144:ef7eb2e8f9f7 32267 #define UART3_BASE (APBPERIPH_BASE + 0x33000)
<> 144:ef7eb2e8f9f7 32268 #define UART5_BASE (APBPERIPH_BASE + 0x35000)
<> 144:ef7eb2e8f9f7 32269 #define I2C1_BASE (APBPERIPH_BASE + 0x41000)
<> 144:ef7eb2e8f9f7 32270 #define I2C3_BASE (APBPERIPH_BASE + 0x43000)
<> 144:ef7eb2e8f9f7 32271 #define SC1_BASE (APBPERIPH_BASE + 0x51000)
<> 144:ef7eb2e8f9f7 32272 #define SC3_BASE (APBPERIPH_BASE + 0x53000)
<> 144:ef7eb2e8f9f7 32273 #define SC5_BASE (APBPERIPH_BASE + 0x55000)
<> 144:ef7eb2e8f9f7 32274 #define CAN1_BASE (APBPERIPH_BASE + 0x61000)
<> 144:ef7eb2e8f9f7 32275 #define QEI1_BASE (APBPERIPH_BASE + 0x71000)
<> 144:ef7eb2e8f9f7 32276 #define ECAP1_BASE (APBPERIPH_BASE + 0x75000)
<> 144:ef7eb2e8f9f7 32277 #define CRPT_BASE (0x50080000UL)
<> 144:ef7eb2e8f9f7 32278
<> 144:ef7eb2e8f9f7 32279 /*@}*/ /* end of group NUC472_442_PERIPHERAL_MEM_MAP */
<> 144:ef7eb2e8f9f7 32280
<> 144:ef7eb2e8f9f7 32281
<> 144:ef7eb2e8f9f7 32282 /** @addtogroup NUC472_442_PERIPHERAL_DECLARATION NUC472/NUC442 Peripheral Pointer
<> 144:ef7eb2e8f9f7 32283 The Declaration of NUC472/NUC442 Peripheral
<> 144:ef7eb2e8f9f7 32284 @{
<> 144:ef7eb2e8f9f7 32285 */
<> 144:ef7eb2e8f9f7 32286
<> 144:ef7eb2e8f9f7 32287 #define SYS ((SYS_T *) SYS_BASE)
<> 144:ef7eb2e8f9f7 32288 #define CLK ((CLK_T *) CLK_BASE)
<> 144:ef7eb2e8f9f7 32289 #define PA ((GPIO_T *) GPIOA_BASE)
<> 144:ef7eb2e8f9f7 32290 #define PB ((GPIO_T *) GPIOB_BASE)
<> 144:ef7eb2e8f9f7 32291 #define PC ((GPIO_T *) GPIOC_BASE)
<> 144:ef7eb2e8f9f7 32292 #define PD ((GPIO_T *) GPIOD_BASE)
<> 144:ef7eb2e8f9f7 32293 #define PE ((GPIO_T *) GPIOE_BASE)
<> 144:ef7eb2e8f9f7 32294 #define PF ((GPIO_T *) GPIOF_BASE)
<> 144:ef7eb2e8f9f7 32295 #define PG ((GPIO_T *) GPIOG_BASE)
<> 144:ef7eb2e8f9f7 32296 #define PH ((GPIO_T *) GPIOH_BASE)
<> 144:ef7eb2e8f9f7 32297 #define GPA ((GPIO_T *) GPIOA_BASE)
<> 144:ef7eb2e8f9f7 32298 #define GPB ((GPIO_T *) GPIOB_BASE)
<> 144:ef7eb2e8f9f7 32299 #define GPC ((GPIO_T *) GPIOC_BASE)
<> 144:ef7eb2e8f9f7 32300 #define GPD ((GPIO_T *) GPIOD_BASE)
<> 144:ef7eb2e8f9f7 32301 #define GPE ((GPIO_T *) GPIOE_BASE)
<> 144:ef7eb2e8f9f7 32302 #define GPF ((GPIO_T *) GPIOF_BASE)
<> 144:ef7eb2e8f9f7 32303 #define GPG ((GPIO_T *) GPIOG_BASE)
<> 144:ef7eb2e8f9f7 32304 #define GPH ((GPIO_T *) GPIOH_BASE)
<> 144:ef7eb2e8f9f7 32305 #define GPI ((GPIO_T *) GPIOI_BASE)
<> 144:ef7eb2e8f9f7 32306 #define GPIO ((GPIO_DB_T *) GPIO_DBCTL_BASE)
<> 144:ef7eb2e8f9f7 32307 #define PDMA ((PDMA_T *) PDMA_BASE)
<> 144:ef7eb2e8f9f7 32308 #define USBH ((USBH_T *) USBH_BASE)
<> 144:ef7eb2e8f9f7 32309 #define EMAC ((EMAC_T *) EMAC_BASE)
<> 144:ef7eb2e8f9f7 32310 #define FMC ((FMC_T *) FMC_BASE)
<> 144:ef7eb2e8f9f7 32311 #define SD ((SDH_T *) SD_BASE)
<> 144:ef7eb2e8f9f7 32312 #define SIC ((SIC_T *) SIC_BASE)
<> 144:ef7eb2e8f9f7 32313 #define EBI ((EBI_T *) EBI_BASE)
<> 144:ef7eb2e8f9f7 32314 #define ICAP ((CAP_T *) CAP_BASE)
<> 144:ef7eb2e8f9f7 32315 #define SPACC ((SPACC_T *) SPACC_BASE)
<> 144:ef7eb2e8f9f7 32316 #define CRC ((CRC_T *) CRC_BASE)
<> 144:ef7eb2e8f9f7 32317 #define TAMPER ((TAMPER_T *) TAMPER_BASE)
<> 144:ef7eb2e8f9f7 32318
<> 144:ef7eb2e8f9f7 32319 #define WDT ((WDT_T *) WDT_BASE)
<> 144:ef7eb2e8f9f7 32320 #define WWDT ((WWDT_T *) WWDT_BASE)
<> 144:ef7eb2e8f9f7 32321 #define RTC ((RTC_T *) RTC_BASE)
<> 144:ef7eb2e8f9f7 32322 #define ADC ((ADC_T *) ADC_BASE)
<> 144:ef7eb2e8f9f7 32323 #define EADC ((EADC_T *) EADC_BASE)
<> 144:ef7eb2e8f9f7 32324 #define ACMP ((ACMP_T *) ACMP_BASE)
<> 144:ef7eb2e8f9f7 32325
<> 144:ef7eb2e8f9f7 32326 #define I2S0 ((I2S_T *) I2S0_BASE)
<> 144:ef7eb2e8f9f7 32327 #define I2S1 ((I2S_T *) I2S1_BASE)
<> 144:ef7eb2e8f9f7 32328 #define USBD ((USBD_T *) UDC20_BASE)
<> 144:ef7eb2e8f9f7 32329 #define OTG ((OTG_T *) OTG_BASE)
<> 144:ef7eb2e8f9f7 32330 #define TIMER0 ((TIMER_T *) TIMER0_BASE)
<> 144:ef7eb2e8f9f7 32331 #define TIMER1 ((TIMER_T *) TIMER1_BASE)
<> 144:ef7eb2e8f9f7 32332 #define TIMER2 ((TIMER_T *) TIMER2_BASE)
<> 144:ef7eb2e8f9f7 32333 #define TIMER3 ((TIMER_T *) TIMER3_BASE)
<> 144:ef7eb2e8f9f7 32334 #define PWM0 ((PWM_T *) PWM0_BASE)
<> 144:ef7eb2e8f9f7 32335 #define PWM1 ((PWM_T *) PWM1_BASE)
<> 144:ef7eb2e8f9f7 32336 #define EPWM0 ((EPWM_T *) EPWM0_BASE)
<> 144:ef7eb2e8f9f7 32337 #define EPWM1 ((EPWM_T *) EPWM1_BASE)
<> 144:ef7eb2e8f9f7 32338 #define ECAP0 ((ECAP_T *) ECAP0_BASE)
<> 144:ef7eb2e8f9f7 32339 #define ECAP1 ((ECAP_T *) ECAP1_BASE)
<> 144:ef7eb2e8f9f7 32340 #define QEI0 ((QEI_T *) QEI0_BASE)
<> 144:ef7eb2e8f9f7 32341 #define QEI1 ((QEI_T *) QEI1_BASE)
<> 144:ef7eb2e8f9f7 32342 #define SPI0 ((SPI_T *) SPI0_BASE)
<> 144:ef7eb2e8f9f7 32343 #define SPI1 ((SPI_T *) SPI1_BASE)
<> 144:ef7eb2e8f9f7 32344 #define SPI2 ((SPI_T *) SPI2_BASE)
<> 144:ef7eb2e8f9f7 32345 #define SPI3 ((SPI_T *) SPI3_BASE)
<> 144:ef7eb2e8f9f7 32346 #define UART0 ((UART_T *) UART0_BASE)
<> 144:ef7eb2e8f9f7 32347 #define UART1 ((UART_T *) UART1_BASE)
<> 144:ef7eb2e8f9f7 32348 #define UART2 ((UART_T *) UART2_BASE)
<> 144:ef7eb2e8f9f7 32349 #define UART3 ((UART_T *) UART3_BASE)
<> 144:ef7eb2e8f9f7 32350 #define UART4 ((UART_T *) UART4_BASE)
<> 144:ef7eb2e8f9f7 32351 #define UART5 ((UART_T *) UART5_BASE)
<> 144:ef7eb2e8f9f7 32352 #define I2C0 ((I2C_T *) I2C0_BASE)
<> 144:ef7eb2e8f9f7 32353 #define I2C1 ((I2C_T *) I2C1_BASE)
<> 144:ef7eb2e8f9f7 32354 #define I2C2 ((I2C_T *) I2C2_BASE)
<> 144:ef7eb2e8f9f7 32355 #define I2C3 ((I2C_T *) I2C3_BASE)
<> 144:ef7eb2e8f9f7 32356 #define I2C4 ((I2C_T *) I2C4_BASE)
<> 144:ef7eb2e8f9f7 32357 #define SC0 ((SC_T *) SC0_BASE)
<> 144:ef7eb2e8f9f7 32358 #define SC1 ((SC_T *) SC1_BASE)
<> 144:ef7eb2e8f9f7 32359 #define SC2 ((SC_T *) SC2_BASE)
<> 144:ef7eb2e8f9f7 32360 #define SC3 ((SC_T *) SC3_BASE)
<> 144:ef7eb2e8f9f7 32361 #define SC4 ((SC_T *) SC4_BASE)
<> 144:ef7eb2e8f9f7 32362 #define SC5 ((SC_T *) SC5_BASE)
<> 144:ef7eb2e8f9f7 32363 #define CAN0 ((CAN_T *) CAN0_BASE)
<> 144:ef7eb2e8f9f7 32364 #define CAN1 ((CAN_T *) CAN1_BASE)
<> 144:ef7eb2e8f9f7 32365 #define PS2 ((PS2_T *) PS2D_BASE)
<> 144:ef7eb2e8f9f7 32366 #define CRPT ((CRPT_T *) CRPT_BASE)
<> 144:ef7eb2e8f9f7 32367 /*@}*/ /* end of group NUC472_442_PERIPHERAL_DECLARATION */
<> 144:ef7eb2e8f9f7 32368
<> 144:ef7eb2e8f9f7 32369 /** @addtogroup NUC472_442_IO_ROUTINE NUC472/NUC442 I/O Routines
<> 144:ef7eb2e8f9f7 32370 The Declaration of NUC472/NUC442 I/O Routines
<> 144:ef7eb2e8f9f7 32371 @{
<> 144:ef7eb2e8f9f7 32372 */
<> 144:ef7eb2e8f9f7 32373
<> 144:ef7eb2e8f9f7 32374 typedef volatile unsigned char vu8; ///< Define 8-bit unsigned volatile data type
<> 144:ef7eb2e8f9f7 32375 typedef volatile unsigned short vu16; ///< Define 16-bit unsigned volatile data type
<> 144:ef7eb2e8f9f7 32376 typedef volatile unsigned long vu32; ///< Define 32-bit unsigned volatile data type
<> 144:ef7eb2e8f9f7 32377
<> 144:ef7eb2e8f9f7 32378 /**
<> 144:ef7eb2e8f9f7 32379 * @brief Get a 8-bit unsigned value from specified address
<> 144:ef7eb2e8f9f7 32380 * @param[in] addr Address to get 8-bit data from
<> 144:ef7eb2e8f9f7 32381 * @return 8-bit unsigned value stored in specified address
<> 144:ef7eb2e8f9f7 32382 */
<> 144:ef7eb2e8f9f7 32383 #define M8(addr) (*((vu8 *) (addr)))
<> 144:ef7eb2e8f9f7 32384
<> 144:ef7eb2e8f9f7 32385 /**
<> 144:ef7eb2e8f9f7 32386 * @brief Get a 16-bit unsigned value from specified address
<> 144:ef7eb2e8f9f7 32387 * @param[in] addr Address to get 16-bit data from
<> 144:ef7eb2e8f9f7 32388 * @return 16-bit unsigned value stored in specified address
<> 144:ef7eb2e8f9f7 32389 * @note The input address must be 16-bit aligned
<> 144:ef7eb2e8f9f7 32390 */
<> 144:ef7eb2e8f9f7 32391 #define M16(addr) (*((vu16 *) (addr)))
<> 144:ef7eb2e8f9f7 32392
<> 144:ef7eb2e8f9f7 32393 /**
<> 144:ef7eb2e8f9f7 32394 * @brief Get a 32-bit unsigned value from specified address
<> 144:ef7eb2e8f9f7 32395 * @param[in] addr Address to get 32-bit data from
<> 144:ef7eb2e8f9f7 32396 * @return 32-bit unsigned value stored in specified address
<> 144:ef7eb2e8f9f7 32397 * @note The input address must be 32-bit aligned
<> 144:ef7eb2e8f9f7 32398 */
<> 144:ef7eb2e8f9f7 32399 #define M32(addr) (*((vu32 *) (addr)))
<> 144:ef7eb2e8f9f7 32400
<> 144:ef7eb2e8f9f7 32401 /**
<> 144:ef7eb2e8f9f7 32402 * @brief Set a 32-bit unsigned value to specified I/O port
<> 144:ef7eb2e8f9f7 32403 * @param[in] port Port address to set 32-bit data
<> 144:ef7eb2e8f9f7 32404 * @param[in] value Value to write to I/O port
<> 144:ef7eb2e8f9f7 32405 * @return None
<> 144:ef7eb2e8f9f7 32406 * @note The output port must be 32-bit aligned
<> 144:ef7eb2e8f9f7 32407 */
<> 144:ef7eb2e8f9f7 32408 #define outpw(port,value) *((volatile unsigned int *)(port)) = value
<> 144:ef7eb2e8f9f7 32409
<> 144:ef7eb2e8f9f7 32410 /**
<> 144:ef7eb2e8f9f7 32411 * @brief Get a 32-bit unsigned value from specified I/O port
<> 144:ef7eb2e8f9f7 32412 * @param[in] port Port address to get 32-bit data from
<> 144:ef7eb2e8f9f7 32413 * @return 32-bit unsigned value stored in specified I/O port
<> 144:ef7eb2e8f9f7 32414 * @note The input port must be 32-bit aligned
<> 144:ef7eb2e8f9f7 32415 */
<> 144:ef7eb2e8f9f7 32416 #define inpw(port) (*((volatile unsigned int *)(port)))
<> 144:ef7eb2e8f9f7 32417
<> 144:ef7eb2e8f9f7 32418 /**
<> 144:ef7eb2e8f9f7 32419 * @brief Set a 16-bit unsigned value to specified I/O port
<> 144:ef7eb2e8f9f7 32420 * @param[in] port Port address to set 16-bit data
<> 144:ef7eb2e8f9f7 32421 * @param[in] value Value to write to I/O port
<> 144:ef7eb2e8f9f7 32422 * @return None
<> 144:ef7eb2e8f9f7 32423 * @note The output port must be 16-bit aligned
<> 144:ef7eb2e8f9f7 32424 */
<> 144:ef7eb2e8f9f7 32425 #define outps(port,value) *((volatile unsigned short *)(port)) = value
<> 144:ef7eb2e8f9f7 32426
<> 144:ef7eb2e8f9f7 32427 /**
<> 144:ef7eb2e8f9f7 32428 * @brief Get a 16-bit unsigned value from specified I/O port
<> 144:ef7eb2e8f9f7 32429 * @param[in] port Port address to get 16-bit data from
<> 144:ef7eb2e8f9f7 32430 * @return 16-bit unsigned value stored in specified I/O port
<> 144:ef7eb2e8f9f7 32431 * @note The input port must be 16-bit aligned
<> 144:ef7eb2e8f9f7 32432 */
<> 144:ef7eb2e8f9f7 32433 #define inps(port) (*((volatile unsigned short *)(port)))
<> 144:ef7eb2e8f9f7 32434
<> 144:ef7eb2e8f9f7 32435 /**
<> 144:ef7eb2e8f9f7 32436 * @brief Set a 8-bit unsigned value to specified I/O port
<> 144:ef7eb2e8f9f7 32437 * @param[in] port Port address to set 8-bit data
<> 144:ef7eb2e8f9f7 32438 * @param[in] value Value to write to I/O port
<> 144:ef7eb2e8f9f7 32439 * @return None
<> 144:ef7eb2e8f9f7 32440 */
<> 144:ef7eb2e8f9f7 32441 #define outpb(port,value) *((volatile unsigned char *)(port)) = value
<> 144:ef7eb2e8f9f7 32442
<> 144:ef7eb2e8f9f7 32443 /**
<> 144:ef7eb2e8f9f7 32444 * @brief Get a 8-bit unsigned value from specified I/O port
<> 144:ef7eb2e8f9f7 32445 * @param[in] port Port address to get 8-bit data from
<> 144:ef7eb2e8f9f7 32446 * @return 8-bit unsigned value stored in specified I/O port
<> 144:ef7eb2e8f9f7 32447 */
<> 144:ef7eb2e8f9f7 32448 #define inpb(port) (*((volatile unsigned char *)(port)))
<> 144:ef7eb2e8f9f7 32449
<> 144:ef7eb2e8f9f7 32450 /**
<> 144:ef7eb2e8f9f7 32451 * @brief Set a 32-bit unsigned value to specified I/O port
<> 144:ef7eb2e8f9f7 32452 * @param[in] port Port address to set 32-bit data
<> 144:ef7eb2e8f9f7 32453 * @param[in] value Value to write to I/O port
<> 144:ef7eb2e8f9f7 32454 * @return None
<> 144:ef7eb2e8f9f7 32455 * @note The output port must be 32-bit aligned
<> 144:ef7eb2e8f9f7 32456 */
<> 144:ef7eb2e8f9f7 32457 #define outp32(port,value) *((volatile unsigned int *)(port)) = value
<> 144:ef7eb2e8f9f7 32458
<> 144:ef7eb2e8f9f7 32459 /**
<> 144:ef7eb2e8f9f7 32460 * @brief Get a 32-bit unsigned value from specified I/O port
<> 144:ef7eb2e8f9f7 32461 * @param[in] port Port address to get 32-bit data from
<> 144:ef7eb2e8f9f7 32462 * @return 32-bit unsigned value stored in specified I/O port
<> 144:ef7eb2e8f9f7 32463 * @note The input port must be 32-bit aligned
<> 144:ef7eb2e8f9f7 32464 */
<> 144:ef7eb2e8f9f7 32465 #define inp32(port) (*((volatile unsigned int *)(port)))
<> 144:ef7eb2e8f9f7 32466
<> 144:ef7eb2e8f9f7 32467 /**
<> 144:ef7eb2e8f9f7 32468 * @brief Set a 16-bit unsigned value to specified I/O port
<> 144:ef7eb2e8f9f7 32469 * @param[in] port Port address to set 16-bit data
<> 144:ef7eb2e8f9f7 32470 * @param[in] value Value to write to I/O port
<> 144:ef7eb2e8f9f7 32471 * @return None
<> 144:ef7eb2e8f9f7 32472 * @note The output port must be 16-bit aligned
<> 144:ef7eb2e8f9f7 32473 */
<> 144:ef7eb2e8f9f7 32474 #define outp16(port,value) *((volatile unsigned short *)(port)) = value
<> 144:ef7eb2e8f9f7 32475
<> 144:ef7eb2e8f9f7 32476 /**
<> 144:ef7eb2e8f9f7 32477 * @brief Get a 16-bit unsigned value from specified I/O port
<> 144:ef7eb2e8f9f7 32478 * @param[in] port Port address to get 16-bit data from
<> 144:ef7eb2e8f9f7 32479 * @return 16-bit unsigned value stored in specified I/O port
<> 144:ef7eb2e8f9f7 32480 * @note The input port must be 16-bit aligned
<> 144:ef7eb2e8f9f7 32481 */
<> 144:ef7eb2e8f9f7 32482 #define inp16(port) (*((volatile unsigned short *)(port)))
<> 144:ef7eb2e8f9f7 32483
<> 144:ef7eb2e8f9f7 32484 /**
<> 144:ef7eb2e8f9f7 32485 * @brief Set a 8-bit unsigned value to specified I/O port
<> 144:ef7eb2e8f9f7 32486 * @param[in] port Port address to set 8-bit data
<> 144:ef7eb2e8f9f7 32487 * @param[in] value Value to write to I/O port
<> 144:ef7eb2e8f9f7 32488 * @return None
<> 144:ef7eb2e8f9f7 32489 */
<> 144:ef7eb2e8f9f7 32490 #define outp8(port,value) *((volatile unsigned char *)(port)) = value
<> 144:ef7eb2e8f9f7 32491
<> 144:ef7eb2e8f9f7 32492 /**
<> 144:ef7eb2e8f9f7 32493 * @brief Get a 8-bit unsigned value from specified I/O port
<> 144:ef7eb2e8f9f7 32494 * @param[in] port Port address to get 8-bit data from
<> 144:ef7eb2e8f9f7 32495 * @return 8-bit unsigned value stored in specified I/O port
<> 144:ef7eb2e8f9f7 32496 */
<> 144:ef7eb2e8f9f7 32497 #define inp8(port) (*((volatile unsigned char *)(port)))
<> 144:ef7eb2e8f9f7 32498
<> 144:ef7eb2e8f9f7 32499
<> 144:ef7eb2e8f9f7 32500 /*@}*/ /* end of group NUC472_442_IO_ROUTINE */
<> 144:ef7eb2e8f9f7 32501
<> 144:ef7eb2e8f9f7 32502 /******************************************************************************/
<> 144:ef7eb2e8f9f7 32503 /* Legacy Constants */
<> 144:ef7eb2e8f9f7 32504 /******************************************************************************/
<> 144:ef7eb2e8f9f7 32505 /** @addtogroup NUC472_442_legacy_Constants NUC472/NUC442 Legacy Constants
<> 144:ef7eb2e8f9f7 32506 NUC472/NUC442 Legacy Constants
<> 144:ef7eb2e8f9f7 32507 @{
<> 144:ef7eb2e8f9f7 32508 */
<> 144:ef7eb2e8f9f7 32509
<> 144:ef7eb2e8f9f7 32510 #ifndef NULL
<> 144:ef7eb2e8f9f7 32511 #define NULL (0) ///< NULL pointer
<> 144:ef7eb2e8f9f7 32512 #endif
<> 144:ef7eb2e8f9f7 32513
AnnaBridge 178:79309dc6340a 32514 #ifndef TRUE
<> 144:ef7eb2e8f9f7 32515 #define TRUE (1) ///< Boolean true, define to use in API parameters or return value
AnnaBridge 178:79309dc6340a 32516 #endif
AnnaBridge 178:79309dc6340a 32517 #ifndef FALSE
<> 144:ef7eb2e8f9f7 32518 #define FALSE (0) ///< Boolean false, define to use in API parameters or return value
AnnaBridge 178:79309dc6340a 32519 #endif
<> 144:ef7eb2e8f9f7 32520
<> 144:ef7eb2e8f9f7 32521 #define ENABLE (1) ///< Enable, define to use in API parameters
<> 144:ef7eb2e8f9f7 32522 #define DISABLE (0) ///< Disable, define to use in API parameters
<> 144:ef7eb2e8f9f7 32523
<> 144:ef7eb2e8f9f7 32524 /* Define one bit mask */
<> 144:ef7eb2e8f9f7 32525 #define BIT0 (0x00000001) ///< Bit 0 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32526 #define BIT1 (0x00000002) ///< Bit 1 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32527 #define BIT2 (0x00000004) ///< Bit 2 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32528 #define BIT3 (0x00000008) ///< Bit 3 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32529 #define BIT4 (0x00000010) ///< Bit 4 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32530 #define BIT5 (0x00000020) ///< Bit 5 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32531 #define BIT6 (0x00000040) ///< Bit 6 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32532 #define BIT7 (0x00000080) ///< Bit 7 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32533 #define BIT8 (0x00000100) ///< Bit 8 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32534 #define BIT9 (0x00000200) ///< Bit 9 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32535 #define BIT10 (0x00000400) ///< Bit 10 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32536 #define BIT11 (0x00000800) ///< Bit 11 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32537 #define BIT12 (0x00001000) ///< Bit 12 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32538 #define BIT13 (0x00002000) ///< Bit 13 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32539 #define BIT14 (0x00004000) ///< Bit 14 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32540 #define BIT15 (0x00008000) ///< Bit 15 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32541 #define BIT16 (0x00010000) ///< Bit 16 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32542 #define BIT17 (0x00020000) ///< Bit 17 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32543 #define BIT18 (0x00040000) ///< Bit 18 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32544 #define BIT19 (0x00080000) ///< Bit 19 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32545 #define BIT20 (0x00100000) ///< Bit 20 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32546 #define BIT21 (0x00200000) ///< Bit 21 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32547 #define BIT22 (0x00400000) ///< Bit 22 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32548 #define BIT23 (0x00800000) ///< Bit 23 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32549 #define BIT24 (0x01000000) ///< Bit 24 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32550 #define BIT25 (0x02000000) ///< Bit 25 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32551 #define BIT26 (0x04000000) ///< Bit 26 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32552 #define BIT27 (0x08000000) ///< Bit 27 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32553 #define BIT28 (0x10000000) ///< Bit 28 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32554 #define BIT29 (0x20000000) ///< Bit 29 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32555 #define BIT30 (0x40000000) ///< Bit 30 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32556 #define BIT31 (0x80000000) ///< Bit 31 mask of an 32 bit integer
<> 144:ef7eb2e8f9f7 32557
<> 144:ef7eb2e8f9f7 32558 /* Byte Mask Definitions */
<> 144:ef7eb2e8f9f7 32559 #define BYTE0_Msk (0x000000FF) ///< Mask to get bit0~bit7 from a 32 bit integer
<> 144:ef7eb2e8f9f7 32560 #define BYTE1_Msk (0x0000FF00) ///< Mask to get bit8~bit15 from a 32 bit integer
<> 144:ef7eb2e8f9f7 32561 #define BYTE2_Msk (0x00FF0000) ///< Mask to get bit16~bit23 from a 32 bit integer
<> 144:ef7eb2e8f9f7 32562 #define BYTE3_Msk (0xFF000000) ///< Mask to get bit24~bit31 from a 32 bit integer
<> 144:ef7eb2e8f9f7 32563
<> 144:ef7eb2e8f9f7 32564 #define GET_BYTE0(u32Param) ((u32Param & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
<> 144:ef7eb2e8f9f7 32565 #define GET_BYTE1(u32Param) ((u32Param & BYTE1_Msk) >> 8) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
<> 144:ef7eb2e8f9f7 32566 #define GET_BYTE2(u32Param) ((u32Param & BYTE2_Msk) >> 16) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
<> 144:ef7eb2e8f9f7 32567 #define GET_BYTE3(u32Param) ((u32Param & BYTE3_Msk) >> 24) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
<> 144:ef7eb2e8f9f7 32568
<> 144:ef7eb2e8f9f7 32569 /*@}*/ /* end of group NUC472_442_legacy_Constants */
<> 144:ef7eb2e8f9f7 32570
<> 144:ef7eb2e8f9f7 32571
<> 144:ef7eb2e8f9f7 32572 /******************************************************************************/
<> 144:ef7eb2e8f9f7 32573 /* Peripheral header files */
<> 144:ef7eb2e8f9f7 32574 /******************************************************************************/
<> 144:ef7eb2e8f9f7 32575 #include "nuc472_sys.h"
<> 144:ef7eb2e8f9f7 32576 #include "nuc472_clk.h"
<> 144:ef7eb2e8f9f7 32577
<> 144:ef7eb2e8f9f7 32578 #include "nuc472_acmp.h"
<> 144:ef7eb2e8f9f7 32579 #include "nuc472_adc.h"
<> 144:ef7eb2e8f9f7 32580 #include "nuc472_eadc.h"
<> 153:fa9ff456f731 32581 /* Disable Capture: #include "nuc472_cap.h" */
<> 144:ef7eb2e8f9f7 32582 #include "nuc472_crypto.h"
<> 144:ef7eb2e8f9f7 32583 #include "nuc472_pdma.h"
<> 144:ef7eb2e8f9f7 32584 #include "nuc472_ebi.h"
<> 144:ef7eb2e8f9f7 32585 #include "nuc472_emac.h"
<> 144:ef7eb2e8f9f7 32586 #include "nuc472_fmc.h"
<> 144:ef7eb2e8f9f7 32587 #include "nuc472_gpio.h"
<> 144:ef7eb2e8f9f7 32588 #include "nuc472_i2c.h"
<> 144:ef7eb2e8f9f7 32589 #include "nuc472_pwm.h"
<> 144:ef7eb2e8f9f7 32590 #include "nuc472_rtc.h"
<> 144:ef7eb2e8f9f7 32591 #include "nuc472_sc.h"
<> 144:ef7eb2e8f9f7 32592 #include "nuc472_scuart.h"
<> 144:ef7eb2e8f9f7 32593 #include "nuc472_spi.h"
<> 144:ef7eb2e8f9f7 32594 #include "nuc472_timer.h"
<> 144:ef7eb2e8f9f7 32595 #include "nuc472_uart.h"
<> 144:ef7eb2e8f9f7 32596 #include "nuc472_usbd.h"
<> 144:ef7eb2e8f9f7 32597 #include "nuc472_wdt.h"
<> 144:ef7eb2e8f9f7 32598 #include "nuc472_wwdt.h"
<> 144:ef7eb2e8f9f7 32599 #include "nuc472_i2s.h"
<> 144:ef7eb2e8f9f7 32600 #include "nuc472_can.h"
<> 144:ef7eb2e8f9f7 32601 #include "nuc472_sd.h"
<> 144:ef7eb2e8f9f7 32602 #include "nuc472_ps2.h"
<> 144:ef7eb2e8f9f7 32603
<> 144:ef7eb2e8f9f7 32604 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 32605 }
<> 144:ef7eb2e8f9f7 32606 #endif
<> 144:ef7eb2e8f9f7 32607
<> 144:ef7eb2e8f9f7 32608 #endif /* __NUC472_442_H__ */
<> 144:ef7eb2e8f9f7 32609
<> 144:ef7eb2e8f9f7 32610 /*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/