Thiago Lima / SX1276GenericLib2

f

sx1276/sx1276-hal.cpp@31:e50929bd3f32, 2017-05-01 (annotated)

Committer:
Helmut Tschemernjak
Date:
Mon May 01 11:43:25 2017 +0200
Revision:
31:e50929bd3f32
Parent:
30:d7e36d83ec9d
Child:
34:07e89f23c734
Merged from head, Semtech mbed changes of 24.4.17

- Timeouts are now in ms.

- In sync with github lora-net/LoRaMac-Node

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: -
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276-hal.h"
GregCr 0:e6ceb13d2d05 16
mluis 22:7f3aab69cca9 17 const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE;
GregCr 0:e6ceb13d2d05 18
mluis 21:2e496deb7858 19 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events,
GregCr 0:e6ceb13d2d05 20 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 21 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5,
Helmut Tschemernjak 28:6d83af9f8563 22 #ifdef MURATA_ANT_SWITCH
Helmut64 26:87796ee62589 23 PinName antSwitch, PinName antSwitchTX, PinName antSwitchTXBoost )
Helmut64 26:87796ee62589 24 #else
GregCr 0:e6ceb13d2d05 25 PinName antSwitch )
Helmut64 26:87796ee62589 26 #endif
mluis 21:2e496deb7858 27 : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ),
Helmut Tschemernjak 28:6d83af9f8563 28 #ifdef MURATA_ANT_SWITCH
Helmut Tschemernjak 31:e50929bd3f32 29 AntSwitch(antSwitch), AntSwitchTX(antSwitchTX), AntSwitchTXBoost(antSwitchTXBoost),
Helmut64 26:87796ee62589 30 #else
Helmut Tschemernjak 31:e50929bd3f32 31 AntSwitch( antSwitch ),
Helmut64 26:87796ee62589 32 #endif
Helmut64 26:87796ee62589 33 #if( defined ( TARGET_NUCLEO_L152RE ) )
Helmut Tschemernjak 31:e50929bd3f32 34 Fake( D8 )
Helmut64 26:87796ee62589 35 #else
Helmut Tschemernjak 31:e50929bd3f32 36 Fake( A3 )
Helmut64 26:87796ee62589 37 #endif
GregCr 0:e6ceb13d2d05 38 {
mluis 21:2e496deb7858 39 this->RadioEvents = events;
mluis 21:2e496deb7858 40
GregCr 0:e6ceb13d2d05 41 Reset( );
mluis 25:3778e6204cc1 42
GregCr 0:e6ceb13d2d05 43 RxChainCalibration( );
mluis 25:3778e6204cc1 44
GregCr 0:e6ceb13d2d05 45 IoInit( );
mluis 25:3778e6204cc1 46
GregCr 0:e6ceb13d2d05 47 SetOpMode( RF_OPMODE_SLEEP );
mluis 25:3778e6204cc1 48
GregCr 0:e6ceb13d2d05 49 IoIrqInit( dioIrq );
mluis 25:3778e6204cc1 50
GregCr 0:e6ceb13d2d05 51 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 52
GregCr 0:e6ceb13d2d05 53 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 54
mluis 21:2e496deb7858 55 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 56 }
GregCr 0:e6ceb13d2d05 57
mluis 25:3778e6204cc1 58 SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events )
GregCr 12:aa5b3bf7fdf4 59 #if defined ( TARGET_NUCLEO_L152RE )
mluis 21:2e496deb7858 60 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3
Helmut Tschemernjak 31:e50929bd3f32 61 AntSwitch( A4 ),
Helmut Tschemernjak 31:e50929bd3f32 62 Fake( D8 )
mluis 20:e05596ba4166 63 #elif defined( TARGET_LPC11U6X )
mluis 21:2e496deb7858 64 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
Helmut Tschemernjak 31:e50929bd3f32 65 AntSwitch( P0_23 ),
Helmut Tschemernjak 31:e50929bd3f32 66 Fake( A3 )
GregCr 0:e6ceb13d2d05 67 #else
mluis 21:2e496deb7858 68 : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ),
Helmut Tschemernjak 28:6d83af9f8563 69 #ifdef MURATA_ANT_SWITCH
Helmut Tschemernjak 31:e50929bd3f32 70 AntSwitch(A4), AntSwitchTX(NC), AntSwitchTXBoost(NC),
Helmut64 26:87796ee62589 71 #else
Helmut Tschemernjak 31:e50929bd3f32 72 AntSwitch( A4 ),
Helmut64 26:87796ee62589 73 #endif
Helmut Tschemernjak 31:e50929bd3f32 74 Fake( A3 )
GregCr 0:e6ceb13d2d05 75 #endif
GregCr 0:e6ceb13d2d05 76 {
mluis 21:2e496deb7858 77 this->RadioEvents = events;
mluis 21:2e496deb7858 78
GregCr 0:e6ceb13d2d05 79 Reset( );
mluis 25:3778e6204cc1 80
GregCr 5:11ec8a6ba4f0 81 boardConnected = UNKNOWN;
mluis 25:3778e6204cc1 82
GregCr 1:f979673946c0 83 DetectBoardType( );
mluis 25:3778e6204cc1 84
GregCr 0:e6ceb13d2d05 85 RxChainCalibration( );
mluis 25:3778e6204cc1 86
GregCr 0:e6ceb13d2d05 87 IoInit( );
mluis 25:3778e6204cc1 88
GregCr 0:e6ceb13d2d05 89 SetOpMode( RF_OPMODE_SLEEP );
GregCr 0:e6ceb13d2d05 90 IoIrqInit( dioIrq );
mluis 25:3778e6204cc1 91
GregCr 0:e6ceb13d2d05 92 RadioRegistersInit( );
GregCr 0:e6ceb13d2d05 93
GregCr 0:e6ceb13d2d05 94 SetModem( MODEM_FSK );
GregCr 0:e6ceb13d2d05 95
mluis 21:2e496deb7858 96 this->settings.State = RF_IDLE ;
GregCr 0:e6ceb13d2d05 97 }
GregCr 0:e6ceb13d2d05 98
GregCr 0:e6ceb13d2d05 99 //-------------------------------------------------------------------------
GregCr 0:e6ceb13d2d05 100 // Board relative functions
GregCr 0:e6ceb13d2d05 101 //-------------------------------------------------------------------------
GregCr 2:5eb3066446dd 102 uint8_t SX1276MB1xAS::DetectBoardType( void )
GregCr 1:f979673946c0 103 {
GregCr 5:11ec8a6ba4f0 104 if( boardConnected == UNKNOWN )
GregCr 1:f979673946c0 105 {
Helmut Tschemernjak 31:e50929bd3f32 106 this->AntSwitch.input( );
GregCr 5:11ec8a6ba4f0 107 wait_ms( 1 );
Helmut Tschemernjak 31:e50929bd3f32 108 if( this->AntSwitch == 1 )
GregCr 5:11ec8a6ba4f0 109 {
GregCr 5:11ec8a6ba4f0 110 boardConnected = SX1276MB1LAS;
GregCr 5:11ec8a6ba4f0 111 }
GregCr 5:11ec8a6ba4f0 112 else
GregCr 5:11ec8a6ba4f0 113 {
GregCr 5:11ec8a6ba4f0 114 boardConnected = SX1276MB1MAS;
GregCr 5:11ec8a6ba4f0 115 }
Helmut Tschemernjak 31:e50929bd3f32 116 this->AntSwitch.output( );
GregCr 5:11ec8a6ba4f0 117 wait_ms( 1 );
GregCr 1:f979673946c0 118 }
Helmut Tschemernjak 28:6d83af9f8563 119 #ifdef RFM95_MODULE
Helmut Tschemernjak 28:6d83af9f8563 120 boardConnected = SX1276MB1LAS;
Helmut Tschemernjak 28:6d83af9f8563 121 #endif
GregCr 2:5eb3066446dd 122 return ( boardConnected );
GregCr 1:f979673946c0 123 }
GregCr 0:e6ceb13d2d05 124
GregCr 0:e6ceb13d2d05 125 void SX1276MB1xAS::IoInit( void )
GregCr 0:e6ceb13d2d05 126 {
GregCr 0:e6ceb13d2d05 127 AntSwInit( );
GregCr 0:e6ceb13d2d05 128 SpiInit( );
GregCr 0:e6ceb13d2d05 129 }
GregCr 0:e6ceb13d2d05 130
mluis 22:7f3aab69cca9 131 void SX1276MB1xAS::RadioRegistersInit( )
mluis 22:7f3aab69cca9 132 {
GregCr 0:e6ceb13d2d05 133 uint8_t i = 0;
GregCr 0:e6ceb13d2d05 134 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ )
GregCr 0:e6ceb13d2d05 135 {
GregCr 0:e6ceb13d2d05 136 SetModem( RadioRegsInit[i].Modem );
GregCr 0:e6ceb13d2d05 137 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
GregCr 0:e6ceb13d2d05 138 }
GregCr 0:e6ceb13d2d05 139 }
GregCr 0:e6ceb13d2d05 140
GregCr 0:e6ceb13d2d05 141 void SX1276MB1xAS::SpiInit( void )
GregCr 0:e6ceb13d2d05 142 {
GregCr 0:e6ceb13d2d05 143 nss = 1;
GregCr 0:e6ceb13d2d05 144 spi.format( 8,0 );
GregCr 0:e6ceb13d2d05 145 uint32_t frequencyToSet = 8000000;
Helmut Tschemernjak 31:e50929bd3f32 146 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) || defined(TARGET_STM) )
GregCr 0:e6ceb13d2d05 147 spi.frequency( frequencyToSet );
GregCr 0:e6ceb13d2d05 148 #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate
GregCr 0:e6ceb13d2d05 149 spi.frequency( frequencyToSet * 2 );
GregCr 0:e6ceb13d2d05 150 #else
GregCr 0:e6ceb13d2d05 151 #warning "Check the board's SPI frequency"
GregCr 0:e6ceb13d2d05 152 #endif
GregCr 0:e6ceb13d2d05 153 wait(0.1);
GregCr 0:e6ceb13d2d05 154 }
GregCr 0:e6ceb13d2d05 155
GregCr 0:e6ceb13d2d05 156 void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers )
GregCr 0:e6ceb13d2d05 157 {
mluis 25:3778e6204cc1 158 #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) )
mluis 25:3778e6204cc1 159 dio0.mode( PullDown );
mluis 25:3778e6204cc1 160 dio1.mode( PullDown );
mluis 25:3778e6204cc1 161 dio2.mode( PullDown );
mluis 25:3778e6204cc1 162 dio3.mode( PullDown );
mluis 25:3778e6204cc1 163 dio4.mode( PullDown );
mluis 22:7f3aab69cca9 164 #endif
Helmut Tschemernjak 30:d7e36d83ec9d 165 dio0.rise(callback(this, static_cast< TriggerMB1xAS > ( irqHandlers[0] )));
Helmut Tschemernjak 30:d7e36d83ec9d 166 dio1.rise(callback(this, static_cast< TriggerMB1xAS > ( irqHandlers[1] )));
Helmut Tschemernjak 30:d7e36d83ec9d 167 dio2.rise(callback(this, static_cast< TriggerMB1xAS > ( irqHandlers[2] )));
Helmut Tschemernjak 30:d7e36d83ec9d 168 dio3.rise(callback(this, static_cast< TriggerMB1xAS > ( irqHandlers[3] )));
Helmut Tschemernjak 30:d7e36d83ec9d 169 dio4.rise(callback(this, static_cast< TriggerMB1xAS > ( irqHandlers[4] )));
GregCr 0:e6ceb13d2d05 170 }
GregCr 0:e6ceb13d2d05 171
GregCr 0:e6ceb13d2d05 172 void SX1276MB1xAS::IoDeInit( void )
GregCr 0:e6ceb13d2d05 173 {
GregCr 0:e6ceb13d2d05 174 //nothing
GregCr 0:e6ceb13d2d05 175 }
GregCr 0:e6ceb13d2d05 176
Helmut Tschemernjak 31:e50929bd3f32 177 void SX1276MB1xAS::SetRfTxPower( int8_t power )
Helmut Tschemernjak 31:e50929bd3f32 178 {
Helmut Tschemernjak 31:e50929bd3f32 179 uint8_t paConfig = 0;
Helmut Tschemernjak 31:e50929bd3f32 180 uint8_t paDac = 0;
Helmut Tschemernjak 31:e50929bd3f32 181
Helmut Tschemernjak 31:e50929bd3f32 182 paConfig = Read( REG_PACONFIG );
Helmut Tschemernjak 31:e50929bd3f32 183 paDac = Read( REG_PADAC );
Helmut Tschemernjak 31:e50929bd3f32 184
Helmut Tschemernjak 31:e50929bd3f32 185 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
Helmut Tschemernjak 31:e50929bd3f32 186 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
Helmut Tschemernjak 31:e50929bd3f32 187
Helmut Tschemernjak 31:e50929bd3f32 188 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
Helmut Tschemernjak 31:e50929bd3f32 189 {
Helmut Tschemernjak 31:e50929bd3f32 190 if( power > 17 )
Helmut Tschemernjak 31:e50929bd3f32 191 {
Helmut Tschemernjak 31:e50929bd3f32 192 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
Helmut Tschemernjak 31:e50929bd3f32 193 }
Helmut Tschemernjak 31:e50929bd3f32 194 else
Helmut Tschemernjak 31:e50929bd3f32 195 {
Helmut Tschemernjak 31:e50929bd3f32 196 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
Helmut Tschemernjak 31:e50929bd3f32 197 }
Helmut Tschemernjak 31:e50929bd3f32 198 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
Helmut Tschemernjak 31:e50929bd3f32 199 {
Helmut Tschemernjak 31:e50929bd3f32 200 if( power < 5 )
Helmut Tschemernjak 31:e50929bd3f32 201 {
Helmut Tschemernjak 31:e50929bd3f32 202 power = 5;
Helmut Tschemernjak 31:e50929bd3f32 203 }
Helmut Tschemernjak 31:e50929bd3f32 204 if( power > 20 )
Helmut Tschemernjak 31:e50929bd3f32 205 {
Helmut Tschemernjak 31:e50929bd3f32 206 power = 20;
Helmut Tschemernjak 31:e50929bd3f32 207 }
Helmut Tschemernjak 31:e50929bd3f32 208 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
Helmut Tschemernjak 31:e50929bd3f32 209 }
Helmut Tschemernjak 31:e50929bd3f32 210 else
Helmut Tschemernjak 31:e50929bd3f32 211 {
Helmut Tschemernjak 31:e50929bd3f32 212 if( power < 2 )
Helmut Tschemernjak 31:e50929bd3f32 213 {
Helmut Tschemernjak 31:e50929bd3f32 214 power = 2;
Helmut Tschemernjak 31:e50929bd3f32 215 }
Helmut Tschemernjak 31:e50929bd3f32 216 if( power > 17 )
Helmut Tschemernjak 31:e50929bd3f32 217 {
Helmut Tschemernjak 31:e50929bd3f32 218 power = 17;
Helmut Tschemernjak 31:e50929bd3f32 219 }
Helmut Tschemernjak 31:e50929bd3f32 220 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
Helmut Tschemernjak 31:e50929bd3f32 221 }
Helmut Tschemernjak 31:e50929bd3f32 222 }
Helmut Tschemernjak 31:e50929bd3f32 223 else
Helmut Tschemernjak 31:e50929bd3f32 224 {
Helmut Tschemernjak 31:e50929bd3f32 225 if( power < -1 )
Helmut Tschemernjak 31:e50929bd3f32 226 {
Helmut Tschemernjak 31:e50929bd3f32 227 power = -1;
Helmut Tschemernjak 31:e50929bd3f32 228 }
Helmut Tschemernjak 31:e50929bd3f32 229 if( power > 14 )
Helmut Tschemernjak 31:e50929bd3f32 230 {
Helmut Tschemernjak 31:e50929bd3f32 231 power = 14;
Helmut Tschemernjak 31:e50929bd3f32 232 }
Helmut Tschemernjak 31:e50929bd3f32 233 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
Helmut Tschemernjak 31:e50929bd3f32 234 }
Helmut Tschemernjak 31:e50929bd3f32 235 Write( REG_PACONFIG, paConfig );
Helmut Tschemernjak 31:e50929bd3f32 236 Write( REG_PADAC, paDac );
Helmut Tschemernjak 31:e50929bd3f32 237 }
Helmut Tschemernjak 31:e50929bd3f32 238
Helmut Tschemernjak 31:e50929bd3f32 239
GregCr 0:e6ceb13d2d05 240 uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel )
GregCr 0:e6ceb13d2d05 241 {
GregCr 0:e6ceb13d2d05 242 if( channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 243 {
GregCr 3:ca84be1f3fac 244 if( boardConnected == SX1276MB1LAS )
GregCr 1:f979673946c0 245 {
GregCr 1:f979673946c0 246 return RF_PACONFIG_PASELECT_PABOOST;
GregCr 1:f979673946c0 247 }
GregCr 1:f979673946c0 248 else
GregCr 1:f979673946c0 249 {
GregCr 1:f979673946c0 250 return RF_PACONFIG_PASELECT_RFO;
GregCr 1:f979673946c0 251 }
GregCr 0:e6ceb13d2d05 252 }
GregCr 0:e6ceb13d2d05 253 else
GregCr 0:e6ceb13d2d05 254 {
GregCr 0:e6ceb13d2d05 255 return RF_PACONFIG_PASELECT_RFO;
GregCr 0:e6ceb13d2d05 256 }
GregCr 0:e6ceb13d2d05 257 }
GregCr 0:e6ceb13d2d05 258
GregCr 0:e6ceb13d2d05 259 void SX1276MB1xAS::SetAntSwLowPower( bool status )
GregCr 0:e6ceb13d2d05 260 {
GregCr 0:e6ceb13d2d05 261 if( isRadioActive != status )
GregCr 0:e6ceb13d2d05 262 {
GregCr 0:e6ceb13d2d05 263 isRadioActive = status;
GregCr 0:e6ceb13d2d05 264
GregCr 0:e6ceb13d2d05 265 if( status == false )
GregCr 0:e6ceb13d2d05 266 {
GregCr 0:e6ceb13d2d05 267 AntSwInit( );
GregCr 0:e6ceb13d2d05 268 }
GregCr 0:e6ceb13d2d05 269 else
GregCr 0:e6ceb13d2d05 270 {
GregCr 0:e6ceb13d2d05 271 AntSwDeInit( );
GregCr 0:e6ceb13d2d05 272 }
GregCr 0:e6ceb13d2d05 273 }
GregCr 0:e6ceb13d2d05 274 }
GregCr 0:e6ceb13d2d05 275
GregCr 0:e6ceb13d2d05 276 void SX1276MB1xAS::AntSwInit( void )
GregCr 0:e6ceb13d2d05 277 {
Helmut Tschemernjak 31:e50929bd3f32 278 this->AntSwitch = 0;
Helmut Tschemernjak 28:6d83af9f8563 279 #ifdef MURATA_ANT_SWITCH
Helmut Tschemernjak 31:e50929bd3f32 280 AntSwitchTX = 0;
Helmut Tschemernjak 31:e50929bd3f32 281 AntSwitchTXBoost = 0;
Helmut64 26:87796ee62589 282 #endif
GregCr 0:e6ceb13d2d05 283 }
GregCr 0:e6ceb13d2d05 284
GregCr 0:e6ceb13d2d05 285 void SX1276MB1xAS::AntSwDeInit( void )
GregCr 0:e6ceb13d2d05 286 {
Helmut Tschemernjak 31:e50929bd3f32 287 this->AntSwitch = 0;
Helmut Tschemernjak 28:6d83af9f8563 288 #ifdef MURATA_ANT_SWITCH
Helmut Tschemernjak 31:e50929bd3f32 289 AntSwitchTX = 0;
Helmut Tschemernjak 31:e50929bd3f32 290 AntSwitchTXBoost = 0;
Helmut64 26:87796ee62589 291 #endif
GregCr 0:e6ceb13d2d05 292 }
GregCr 0:e6ceb13d2d05 293
Helmut Tschemernjak 31:e50929bd3f32 294
Helmut Tschemernjak 31:e50929bd3f32 295 void SX1276MB1xAS::SetAntSw( uint8_t opMode )
GregCr 0:e6ceb13d2d05 296 {
Helmut Tschemernjak 31:e50929bd3f32 297 switch( opMode )
GregCr 0:e6ceb13d2d05 298 {
Helmut Tschemernjak 31:e50929bd3f32 299 case RFLR_OPMODE_TRANSMITTER:
Helmut Tschemernjak 31:e50929bd3f32 300 #ifdef MURATA_ANT_SWITCH
Helmut Tschemernjak 31:e50929bd3f32 301 this->AntSwitch = 0; // Murata-RX
Helmut Tschemernjak 31:e50929bd3f32 302 AntSwitchTX = 1; // alternate: antSwitchTXBoost = 1
Helmut Tschemernjak 31:e50929bd3f32 303 #else
Helmut Tschemernjak 31:e50929bd3f32 304 this->AntSwitch = 1;
Helmut Tschemernjak 31:e50929bd3f32 305 #endif
Helmut Tschemernjak 31:e50929bd3f32 306 break;
Helmut Tschemernjak 31:e50929bd3f32 307 case RFLR_OPMODE_RECEIVER:
Helmut Tschemernjak 31:e50929bd3f32 308 case RFLR_OPMODE_RECEIVER_SINGLE:
Helmut Tschemernjak 31:e50929bd3f32 309 case RFLR_OPMODE_CAD:
Helmut Tschemernjak 28:6d83af9f8563 310 #ifdef MURATA_ANT_SWITCH
Helmut Tschemernjak 31:e50929bd3f32 311 this->AntSwitch = 1; // Murata-RX
Helmut Tschemernjak 31:e50929bd3f32 312 AntSwitchTX = 0;
Helmut Tschemernjak 31:e50929bd3f32 313 AntSwitchTXBoost = 0;
Helmut64 26:87796ee62589 314 #else
Helmut Tschemernjak 31:e50929bd3f32 315 this->AntSwitch = 0;
Helmut64 26:87796ee62589 316 #endif
Helmut Tschemernjak 31:e50929bd3f32 317 break;
Helmut Tschemernjak 31:e50929bd3f32 318 default:
Helmut Tschemernjak 28:6d83af9f8563 319 #ifdef MURATA_ANT_SWITCH
Helmut Tschemernjak 31:e50929bd3f32 320 this->AntSwitch = 1; //Murata-RX
Helmut Tschemernjak 31:e50929bd3f32 321 AntSwitchTX = 0;
Helmut Tschemernjak 31:e50929bd3f32 322 AntSwitchTXBoost = 0;
Helmut64 26:87796ee62589 323 #else
Helmut Tschemernjak 31:e50929bd3f32 324 this->AntSwitch = 0;
Helmut64 26:87796ee62589 325 #endif
Helmut Tschemernjak 31:e50929bd3f32 326 break;
GregCr 0:e6ceb13d2d05 327 }
GregCr 0:e6ceb13d2d05 328 }
GregCr 0:e6ceb13d2d05 329
GregCr 0:e6ceb13d2d05 330 bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency )
GregCr 0:e6ceb13d2d05 331 {
Helmut Tschemernjak 31:e50929bd3f32 332 // Implement check. Currently all frequencies are supported
GregCr 0:e6ceb13d2d05 333 return true;
GregCr 0:e6ceb13d2d05 334 }
GregCr 0:e6ceb13d2d05 335
GregCr 0:e6ceb13d2d05 336 void SX1276MB1xAS::Reset( void )
GregCr 0:e6ceb13d2d05 337 {
Helmut Tschemernjak 31:e50929bd3f32 338 reset.output();
Helmut Tschemernjak 31:e50929bd3f32 339 reset = 0;
Helmut Tschemernjak 31:e50929bd3f32 340 wait_ms( 1 );
Helmut Tschemernjak 31:e50929bd3f32 341 reset.input();
Helmut Tschemernjak 31:e50929bd3f32 342 wait_ms( 6 );
GregCr 0:e6ceb13d2d05 343 }
Helmut Tschemernjak 31:e50929bd3f32 344
GregCr 0:e6ceb13d2d05 345 void SX1276MB1xAS::Write( uint8_t addr, uint8_t data )
GregCr 0:e6ceb13d2d05 346 {
GregCr 0:e6ceb13d2d05 347 Write( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 348 }
GregCr 0:e6ceb13d2d05 349
GregCr 0:e6ceb13d2d05 350 uint8_t SX1276MB1xAS::Read( uint8_t addr )
GregCr 0:e6ceb13d2d05 351 {
GregCr 0:e6ceb13d2d05 352 uint8_t data;
GregCr 0:e6ceb13d2d05 353 Read( addr, &data, 1 );
GregCr 0:e6ceb13d2d05 354 return data;
GregCr 0:e6ceb13d2d05 355 }
GregCr 0:e6ceb13d2d05 356
GregCr 0:e6ceb13d2d05 357 void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 358 {
GregCr 0:e6ceb13d2d05 359 uint8_t i;
GregCr 0:e6ceb13d2d05 360
GregCr 0:e6ceb13d2d05 361 nss = 0;
GregCr 0:e6ceb13d2d05 362 spi.write( addr | 0x80 );
GregCr 0:e6ceb13d2d05 363 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 364 {
GregCr 0:e6ceb13d2d05 365 spi.write( buffer[i] );
GregCr 0:e6ceb13d2d05 366 }
GregCr 0:e6ceb13d2d05 367 nss = 1;
GregCr 0:e6ceb13d2d05 368 }
GregCr 0:e6ceb13d2d05 369
GregCr 0:e6ceb13d2d05 370 void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 371 {
GregCr 0:e6ceb13d2d05 372 uint8_t i;
GregCr 0:e6ceb13d2d05 373
GregCr 0:e6ceb13d2d05 374 nss = 0;
GregCr 0:e6ceb13d2d05 375 spi.write( addr & 0x7F );
GregCr 0:e6ceb13d2d05 376 for( i = 0; i < size; i++ )
GregCr 0:e6ceb13d2d05 377 {
GregCr 0:e6ceb13d2d05 378 buffer[i] = spi.write( 0 );
GregCr 0:e6ceb13d2d05 379 }
GregCr 0:e6ceb13d2d05 380 nss = 1;
GregCr 0:e6ceb13d2d05 381 }
GregCr 0:e6ceb13d2d05 382
GregCr 0:e6ceb13d2d05 383 void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 384 {
GregCr 0:e6ceb13d2d05 385 Write( 0, buffer, size );
GregCr 0:e6ceb13d2d05 386 }
GregCr 0:e6ceb13d2d05 387
GregCr 0:e6ceb13d2d05 388 void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 389 {
GregCr 0:e6ceb13d2d05 390 Read( 0, buffer, size );
GregCr 0:e6ceb13d2d05 391 }