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sx1276Regs-LoRa.h

00001 /*
00002  / _____)             _              | |
00003 ( (____  _____ ____ _| |_ _____  ____| |__
00004  \____ \| ___ |    (_   _) ___ |/ ___)  _ \
00005  _____) ) ____| | | || |_| ____( (___| | | |
00006 (______/|_____)_|_|_| \__)_____)\____)_| |_|
00007     (C) 2014 Semtech
00008 
00009 Description: SX1276 LoRa modem registers and bits definitions
00010 
00011 License: Revised BSD License, see LICENSE.TXT file include in the project
00012 
00013 Maintainer: Miguel Luis and Gregory Cristian
00014 */
00015 #ifndef __SX1276_REGS_LORA_H__
00016 #define __SX1276_REGS_LORA_H__
00017 
00018 /*!
00019  * ============================================================================
00020  * SX1276 Internal registers Address
00021  * ============================================================================
00022  */
00023 #define REG_LR_FIFO                                 0x00 
00024 // Common settings
00025 #define REG_LR_OPMODE                               0x01 
00026 #define REG_LR_FRFMSB                               0x06 
00027 #define REG_LR_FRFMID                               0x07
00028 #define REG_LR_FRFLSB                               0x08 
00029 // Tx settings
00030 #define REG_LR_PACONFIG                             0x09 
00031 #define REG_LR_PARAMP                               0x0A 
00032 #define REG_LR_OCP                                  0x0B 
00033 // Rx settings
00034 #define REG_LR_LNA                                  0x0C 
00035 // LoRa registers
00036 #define REG_LR_FIFOADDRPTR                          0x0D 
00037 #define REG_LR_FIFOTXBASEADDR                       0x0E 
00038 #define REG_LR_FIFORXBASEADDR                       0x0F 
00039 #define REG_LR_FIFORXCURRENTADDR                    0x10 
00040 #define REG_LR_IRQFLAGSMASK                         0x11 
00041 #define REG_LR_IRQFLAGS                             0x12 
00042 #define REG_LR_RXNBBYTES                            0x13 
00043 #define REG_LR_RXHEADERCNTVALUEMSB                  0x14 
00044 #define REG_LR_RXHEADERCNTVALUELSB                  0x15 
00045 #define REG_LR_RXPACKETCNTVALUEMSB                  0x16 
00046 #define REG_LR_RXPACKETCNTVALUELSB                  0x17 
00047 #define REG_LR_MODEMSTAT                            0x18 
00048 #define REG_LR_PKTSNRVALUE                          0x19 
00049 #define REG_LR_PKTRSSIVALUE                         0x1A 
00050 #define REG_LR_RSSIVALUE                            0x1B 
00051 #define REG_LR_HOPCHANNEL                           0x1C 
00052 #define REG_LR_MODEMCONFIG1                         0x1D 
00053 #define REG_LR_MODEMCONFIG2                         0x1E 
00054 #define REG_LR_SYMBTIMEOUTLSB                       0x1F 
00055 #define REG_LR_PREAMBLEMSB                          0x20 
00056 #define REG_LR_PREAMBLELSB                          0x21 
00057 #define REG_LR_PAYLOADLENGTH                        0x22 
00058 #define REG_LR_PAYLOADMAXLENGTH                     0x23 
00059 #define REG_LR_HOPPERIOD                            0x24 
00060 #define REG_LR_FIFORXBYTEADDR                       0x25
00061 #define REG_LR_MODEMCONFIG3                         0x26
00062 #define REG_LR_FEIMSB                               0x28
00063 #define REG_LR_FEIMID                               0x29
00064 #define REG_LR_FEILSB                               0x2A
00065 #define REG_LR_RSSIWIDEBAND                         0x2C
00066 #define REG_LR_TEST2F                               0x2F
00067 #define REG_LR_TEST30                               0x30
00068 #define REG_LR_DETECTOPTIMIZE                       0x31
00069 #define REG_LR_INVERTIQ                             0x33
00070 #define REG_LR_TEST36                               0x36
00071 #define REG_LR_DETECTIONTHRESHOLD                   0x37
00072 #define REG_LR_SYNCWORD                             0x39
00073 #define REG_LR_TEST3A                               0x3A
00074 #define REG_LR_INVERTIQ2                            0x3B
00075 
00076 // end of documented register in datasheet
00077 // I/O settings
00078 #define REG_LR_DIOMAPPING1                          0x40
00079 #define REG_LR_DIOMAPPING2                          0x41
00080 // Version
00081 #define REG_LR_VERSION                              0x42
00082 // Additional settings
00083 #define REG_LR_PLLHOP                               0x44
00084 #define REG_LR_TCXO                                 0x4B
00085 #define REG_LR_PADAC                                0x4D
00086 #define REG_LR_FORMERTEMP                           0x5B
00087 #define REG_LR_BITRATEFRAC                          0x5D
00088 #define REG_LR_AGCREF                               0x61
00089 #define REG_LR_AGCTHRESH1                           0x62
00090 #define REG_LR_AGCTHRESH2                           0x63
00091 #define REG_LR_AGCTHRESH3                           0x64
00092 #define REG_LR_PLL                                  0x70
00093 
00094 /*!
00095  * ============================================================================
00096  * SX1276 LoRa bits control definition
00097  * ============================================================================
00098  */
00099 
00100 /*!
00101  * RegFifo
00102  */
00103 
00104 /*!
00105  * RegOpMode
00106  */
00107 #define RFLR_OPMODE_LONGRANGEMODE_MASK              0x7F 
00108 #define RFLR_OPMODE_LONGRANGEMODE_OFF               0x00 // Default
00109 #define RFLR_OPMODE_LONGRANGEMODE_ON                0x80 
00110 
00111 #define RFLR_OPMODE_ACCESSSHAREDREG_MASK            0xBF 
00112 #define RFLR_OPMODE_ACCESSSHAREDREG_ENABLE          0x40 
00113 #define RFLR_OPMODE_ACCESSSHAREDREG_DISABLE         0x00 // Default
00114 
00115 #define RFLR_OPMODE_FREQMODE_ACCESS_MASK            0xF7
00116 #define RFLR_OPMODE_FREQMODE_ACCESS_LF              0x08 // Default
00117 #define RFLR_OPMODE_FREQMODE_ACCESS_HF              0x00 
00118 
00119 #define RFLR_OPMODE_MASK                            0xF8 
00120 #define RFLR_OPMODE_SLEEP                           0x00 
00121 #define RFLR_OPMODE_STANDBY                         0x01 // Default
00122 #define RFLR_OPMODE_SYNTHESIZER_TX                  0x02 
00123 #define RFLR_OPMODE_TRANSMITTER                     0x03 
00124 #define RFLR_OPMODE_SYNTHESIZER_RX                  0x04 
00125 #define RFLR_OPMODE_RECEIVER                        0x05 
00126 // LoRa specific modes
00127 #define RFLR_OPMODE_RECEIVER_SINGLE                 0x06 
00128 #define RFLR_OPMODE_CAD                             0x07 
00129 
00130 /*!
00131  * RegFrf (MHz)
00132  */
00133 #define RFLR_FRFMSB_434_MHZ                         0x6C // Default
00134 #define RFLR_FRFMID_434_MHZ                         0x80 // Default
00135 #define RFLR_FRFLSB_434_MHZ                         0x00 // Default
00136 
00137 /*!
00138  * RegPaConfig
00139  */
00140 #define RFLR_PACONFIG_PASELECT_MASK                 0x7F 
00141 #define RFLR_PACONFIG_PASELECT_PABOOST              0x80 
00142 #define RFLR_PACONFIG_PASELECT_RFO                  0x00 // Default
00143 
00144 #define RFLR_PACONFIG_MAX_POWER_MASK                0x8F
00145 
00146 #define RFLR_PACONFIG_OUTPUTPOWER_MASK              0xF0 
00147  
00148 /*!
00149  * RegPaRamp
00150  */
00151 #define RFLR_PARAMP_TXBANDFORCE_MASK                0xEF 
00152 #define RFLR_PARAMP_TXBANDFORCE_BAND_SEL            0x10 
00153 #define RFLR_PARAMP_TXBANDFORCE_AUTO                0x00 // Default
00154 
00155 #define RFLR_PARAMP_MASK                            0xF0 
00156 #define RFLR_PARAMP_3400_US                         0x00 
00157 #define RFLR_PARAMP_2000_US                         0x01 
00158 #define RFLR_PARAMP_1000_US                         0x02
00159 #define RFLR_PARAMP_0500_US                         0x03 
00160 #define RFLR_PARAMP_0250_US                         0x04 
00161 #define RFLR_PARAMP_0125_US                         0x05 
00162 #define RFLR_PARAMP_0100_US                         0x06 
00163 #define RFLR_PARAMP_0062_US                         0x07 
00164 #define RFLR_PARAMP_0050_US                         0x08 
00165 #define RFLR_PARAMP_0040_US                         0x09 // Default
00166 #define RFLR_PARAMP_0031_US                         0x0A 
00167 #define RFLR_PARAMP_0025_US                         0x0B 
00168 #define RFLR_PARAMP_0020_US                         0x0C 
00169 #define RFLR_PARAMP_0015_US                         0x0D 
00170 #define RFLR_PARAMP_0012_US                         0x0E 
00171 #define RFLR_PARAMP_0010_US                         0x0F 
00172 
00173 /*!
00174  * RegOcp
00175  */
00176 #define RFLR_OCP_MASK                               0xDF 
00177 #define RFLR_OCP_ON                                 0x20 // Default
00178 #define RFLR_OCP_OFF                                0x00   
00179 
00180 #define RFLR_OCP_TRIM_MASK                          0xE0
00181 #define RFLR_OCP_TRIM_045_MA                        0x00
00182 #define RFLR_OCP_TRIM_050_MA                        0x01   
00183 #define RFLR_OCP_TRIM_055_MA                        0x02 
00184 #define RFLR_OCP_TRIM_060_MA                        0x03 
00185 #define RFLR_OCP_TRIM_065_MA                        0x04 
00186 #define RFLR_OCP_TRIM_070_MA                        0x05 
00187 #define RFLR_OCP_TRIM_075_MA                        0x06 
00188 #define RFLR_OCP_TRIM_080_MA                        0x07  
00189 #define RFLR_OCP_TRIM_085_MA                        0x08
00190 #define RFLR_OCP_TRIM_090_MA                        0x09 
00191 #define RFLR_OCP_TRIM_095_MA                        0x0A 
00192 #define RFLR_OCP_TRIM_100_MA                        0x0B  // Default
00193 #define RFLR_OCP_TRIM_105_MA                        0x0C 
00194 #define RFLR_OCP_TRIM_110_MA                        0x0D 
00195 #define RFLR_OCP_TRIM_115_MA                        0x0E 
00196 #define RFLR_OCP_TRIM_120_MA                        0x0F 
00197 #define RFLR_OCP_TRIM_130_MA                        0x10
00198 #define RFLR_OCP_TRIM_140_MA                        0x11   
00199 #define RFLR_OCP_TRIM_150_MA                        0x12 
00200 #define RFLR_OCP_TRIM_160_MA                        0x13 
00201 #define RFLR_OCP_TRIM_170_MA                        0x14 
00202 #define RFLR_OCP_TRIM_180_MA                        0x15 
00203 #define RFLR_OCP_TRIM_190_MA                        0x16 
00204 #define RFLR_OCP_TRIM_200_MA                        0x17  
00205 #define RFLR_OCP_TRIM_210_MA                        0x18
00206 #define RFLR_OCP_TRIM_220_MA                        0x19 
00207 #define RFLR_OCP_TRIM_230_MA                        0x1A 
00208 #define RFLR_OCP_TRIM_240_MA                        0x1B
00209 
00210 /*!
00211  * RegLna
00212  */
00213 #define RFLR_LNA_GAIN_MASK                          0x1F 
00214 #define RFLR_LNA_GAIN_G1                            0x20 // Default
00215 #define RFLR_LNA_GAIN_G2                            0x40 
00216 #define RFLR_LNA_GAIN_G3                            0x60 
00217 #define RFLR_LNA_GAIN_G4                            0x80 
00218 #define RFLR_LNA_GAIN_G5                            0xA0 
00219 #define RFLR_LNA_GAIN_G6                            0xC0 
00220 
00221 #define RFLR_LNA_BOOST_LF_MASK                      0xE7 
00222 #define RFLR_LNA_BOOST_LF_DEFAULT                   0x00 // Default
00223 
00224 #define RFLR_LNA_BOOST_HF_MASK                      0xFC 
00225 #define RFLR_LNA_BOOST_HF_OFF                       0x00 // Default
00226 #define RFLR_LNA_BOOST_HF_ON                        0x03 
00227 
00228 /*!
00229  * RegFifoAddrPtr
00230  */
00231 #define RFLR_FIFOADDRPTR                            0x00 // Default
00232 
00233 /*!
00234  * RegFifoTxBaseAddr
00235  */
00236 #define RFLR_FIFOTXBASEADDR                         0x80 // Default
00237 
00238 /*!
00239  * RegFifoTxBaseAddr
00240  */
00241 #define RFLR_FIFORXBASEADDR                         0x00 // Default
00242 
00243 /*!
00244  * RegFifoRxCurrentAddr (Read Only)
00245  */
00246 
00247 /*!
00248  * RegIrqFlagsMask
00249  */
00250 #define RFLR_IRQFLAGS_RXTIMEOUT_MASK                0x80 
00251 #define RFLR_IRQFLAGS_RXDONE_MASK                   0x40 
00252 #define RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK          0x20 
00253 #define RFLR_IRQFLAGS_VALIDHEADER_MASK              0x10 
00254 #define RFLR_IRQFLAGS_TXDONE_MASK                   0x08 
00255 #define RFLR_IRQFLAGS_CADDONE_MASK                  0x04 
00256 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL_MASK       0x02 
00257 #define RFLR_IRQFLAGS_CADDETECTED_MASK              0x01 
00258 
00259 /*!
00260  * RegIrqFlags
00261  */
00262 #define RFLR_IRQFLAGS_RXTIMEOUT                     0x80 
00263 #define RFLR_IRQFLAGS_RXDONE                        0x40 
00264 #define RFLR_IRQFLAGS_PAYLOADCRCERROR               0x20 
00265 #define RFLR_IRQFLAGS_VALIDHEADER                   0x10 
00266 #define RFLR_IRQFLAGS_TXDONE                        0x08 
00267 #define RFLR_IRQFLAGS_CADDONE                       0x04 
00268 #define RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL            0x02 
00269 #define RFLR_IRQFLAGS_CADDETECTED                   0x01 
00270 
00271 /*!
00272  * RegFifoRxNbBytes (Read Only)
00273  */
00274 
00275 /*!
00276  * RegRxHeaderCntValueMsb (Read Only)
00277  */
00278 
00279 /*!
00280  * RegRxHeaderCntValueLsb (Read Only)
00281  */
00282 
00283 /*!
00284  * RegRxPacketCntValueMsb (Read Only)
00285  */
00286 
00287 /*!
00288  * RegRxPacketCntValueLsb (Read Only)
00289  */
00290 
00291 /*!
00292  * RegModemStat (Read Only)
00293  */
00294 #define RFLR_MODEMSTAT_RX_CR_MASK                   0x1F
00295 #define RFLR_MODEMSTAT_MODEM_STATUS_MASK            0xE0 
00296 
00297 #define RFLR_MODEMSTAT_MODEM_CLEAR                  0x10
00298 #define RFLR_MODEMSTAT_HEADERINFO_VALID             0x08
00299 #define RFLR_MODEMSTAT_RX_ONGOING                   0x04
00300 #define RFLR_MODEMSTAT_SIGNAL_SYNCRONIZED           0x02
00301 #define RFLR_MODEMSTAT_SIGNAL_DETECTED              0x01
00302 
00303 /*!
00304  * RegPktSnrValue (Read Only)
00305  */
00306 
00307 /*!
00308  * RegPktRssiValue (Read Only)
00309  */
00310 
00311 /*!
00312  * RegRssiValue (Read Only)
00313  */
00314 
00315 /*!
00316  * RegHopChannel (Read Only)
00317  */
00318 #define RFLR_HOPCHANNEL_PLL_LOCK_TIMEOUT_MASK       0x7F 
00319 #define RFLR_HOPCHANNEL_PLL_LOCK_FAIL               0x80 
00320 #define RFLR_HOPCHANNEL_PLL_LOCK_SUCCEED            0x00 // Default
00321                                                     
00322 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_MASK           0xBF
00323 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_ON             0x40
00324 #define RFLR_HOPCHANNEL_CRCONPAYLOAD_OFF            0x00 // Default
00325 
00326 #define RFLR_HOPCHANNEL_CHANNEL_MASK                0x3F 
00327 
00328 /*!
00329  * RegModemConfig1
00330  */
00331 #define RFLR_MODEMCONFIG1_BW_MASK                   0x0F 
00332 #define RFLR_MODEMCONFIG1_BW_7_81_KHZ               0x00 
00333 #define RFLR_MODEMCONFIG1_BW_10_41_KHZ              0x10 
00334 #define RFLR_MODEMCONFIG1_BW_15_62_KHZ              0x20 
00335 #define RFLR_MODEMCONFIG1_BW_20_83_KHZ              0x30 
00336 #define RFLR_MODEMCONFIG1_BW_31_25_KHZ              0x40 
00337 #define RFLR_MODEMCONFIG1_BW_41_66_KHZ              0x50 
00338 #define RFLR_MODEMCONFIG1_BW_62_50_KHZ              0x60 
00339 #define RFLR_MODEMCONFIG1_BW_125_KHZ                0x70 // Default
00340 #define RFLR_MODEMCONFIG1_BW_250_KHZ                0x80 
00341 #define RFLR_MODEMCONFIG1_BW_500_KHZ                0x90 
00342                                                     
00343 #define RFLR_MODEMCONFIG1_CODINGRATE_MASK           0xF1 
00344 #define RFLR_MODEMCONFIG1_CODINGRATE_4_5            0x02
00345 #define RFLR_MODEMCONFIG1_CODINGRATE_4_6            0x04 // Default
00346 #define RFLR_MODEMCONFIG1_CODINGRATE_4_7            0x06 
00347 #define RFLR_MODEMCONFIG1_CODINGRATE_4_8            0x08 
00348                                                     
00349 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK       0xFE 
00350 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_ON         0x01 
00351 #define RFLR_MODEMCONFIG1_IMPLICITHEADER_OFF        0x00 // Default
00352 
00353 /*!
00354  * RegModemConfig2
00355  */
00356 #define RFLR_MODEMCONFIG2_SF_MASK                   0x0F 
00357 #define RFLR_MODEMCONFIG2_SF_6                      0x60 
00358 #define RFLR_MODEMCONFIG2_SF_7                      0x70 // Default
00359 #define RFLR_MODEMCONFIG2_SF_8                      0x80 
00360 #define RFLR_MODEMCONFIG2_SF_9                      0x90 
00361 #define RFLR_MODEMCONFIG2_SF_10                     0xA0 
00362 #define RFLR_MODEMCONFIG2_SF_11                     0xB0 
00363 #define RFLR_MODEMCONFIG2_SF_12                     0xC0 
00364 
00365 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_MASK     0xF7 
00366 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_ON       0x08 
00367 #define RFLR_MODEMCONFIG2_TXCONTINUOUSMODE_OFF      0x00 
00368 
00369 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK         0xFB 
00370 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_ON           0x04 
00371 #define RFLR_MODEMCONFIG2_RXPAYLOADCRC_OFF          0x00 // Default
00372  
00373 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK       0xFC 
00374 #define RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB            0x00 // Default
00375 
00376 /*!
00377  * RegSymbTimeoutLsb
00378  */
00379 #define RFLR_SYMBTIMEOUTLSB_SYMBTIMEOUT             0x64 // Default
00380 
00381 /*!
00382  * RegPreambleLengthMsb
00383  */
00384 #define RFLR_PREAMBLELENGTHMSB                      0x00 // Default
00385 
00386 /*!
00387  * RegPreambleLengthLsb
00388  */
00389 #define RFLR_PREAMBLELENGTHLSB                      0x08 // Default
00390 
00391 /*!
00392  * RegPayloadLength
00393  */
00394 #define RFLR_PAYLOADLENGTH                          0x0E // Default
00395 
00396 /*!
00397  * RegPayloadMaxLength
00398  */
00399 #define RFLR_PAYLOADMAXLENGTH                       0xFF // Default
00400 
00401 /*!
00402  * RegHopPeriod
00403  */
00404 #define RFLR_HOPPERIOD_FREQFOPPINGPERIOD            0x00 // Default
00405 
00406 /*!
00407  * RegFifoRxByteAddr (Read Only)
00408  */
00409 
00410 /*!
00411  * RegModemConfig3
00412  */
00413 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK  0xF7 
00414 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_ON    0x08 
00415 #define RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_OFF   0x00 // Default
00416 
00417 #define RFLR_MODEMCONFIG3_AGCAUTO_MASK              0xFB 
00418 #define RFLR_MODEMCONFIG3_AGCAUTO_ON                0x04 // Default 
00419 #define RFLR_MODEMCONFIG3_AGCAUTO_OFF               0x00 
00420 
00421 /*!
00422  * RegFeiMsb (Read Only)
00423  */
00424 
00425 /*!
00426  * RegFeiMid (Read Only)
00427  */
00428 
00429 /*!
00430  * RegFeiLsb (Read Only)
00431  */
00432 
00433 /*!
00434  * RegRssiWideband (Read Only)
00435  */
00436 
00437 /*!
00438  * RegDetectOptimize
00439  */
00440 #define RFLR_DETECTIONOPTIMIZE_MASK                 0xF8
00441 #define RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12          0x03 // Default
00442 #define RFLR_DETECTIONOPTIMIZE_SF6                  0x05
00443 
00444 /*!
00445  * RegInvertIQ
00446  */
00447 #define RFLR_INVERTIQ_RX_MASK                       0xBF
00448 #define RFLR_INVERTIQ_RX_OFF                        0x00
00449 #define RFLR_INVERTIQ_RX_ON                         0x40
00450 #define RFLR_INVERTIQ_TX_MASK                       0xFE
00451 #define RFLR_INVERTIQ_TX_OFF                        0x01
00452 #define RFLR_INVERTIQ_TX_ON                         0x00
00453 
00454 /*!
00455  * RegDetectionThreshold
00456  */
00457 #define RFLR_DETECTIONTHRESH_SF7_TO_SF12            0x0A // Default
00458 #define RFLR_DETECTIONTHRESH_SF6                    0x0C
00459 
00460 /*!
00461  * RegInvertIQ2
00462  */
00463 #define RFLR_INVERTIQ2_ON                           0x19
00464 #define RFLR_INVERTIQ2_OFF                          0x1D
00465 
00466 /*!
00467  * RegDioMapping1
00468  */
00469 #define RFLR_DIOMAPPING1_DIO0_MASK                  0x3F
00470 #define RFLR_DIOMAPPING1_DIO0_00                    0x00  // Default
00471 #define RFLR_DIOMAPPING1_DIO0_01                    0x40
00472 #define RFLR_DIOMAPPING1_DIO0_10                    0x80
00473 #define RFLR_DIOMAPPING1_DIO0_11                    0xC0
00474 
00475 #define RFLR_DIOMAPPING1_DIO1_MASK                  0xCF
00476 #define RFLR_DIOMAPPING1_DIO1_00                    0x00  // Default
00477 #define RFLR_DIOMAPPING1_DIO1_01                    0x10
00478 #define RFLR_DIOMAPPING1_DIO1_10                    0x20
00479 #define RFLR_DIOMAPPING1_DIO1_11                    0x30
00480 
00481 #define RFLR_DIOMAPPING1_DIO2_MASK                  0xF3
00482 #define RFLR_DIOMAPPING1_DIO2_00                    0x00  // Default
00483 #define RFLR_DIOMAPPING1_DIO2_01                    0x04
00484 #define RFLR_DIOMAPPING1_DIO2_10                    0x08
00485 #define RFLR_DIOMAPPING1_DIO2_11                    0x0C
00486 
00487 #define RFLR_DIOMAPPING1_DIO3_MASK                  0xFC
00488 #define RFLR_DIOMAPPING1_DIO3_00                    0x00  // Default
00489 #define RFLR_DIOMAPPING1_DIO3_01                    0x01
00490 #define RFLR_DIOMAPPING1_DIO3_10                    0x02
00491 #define RFLR_DIOMAPPING1_DIO3_11                    0x03
00492 
00493 /*!
00494  * RegDioMapping2
00495  */
00496 #define RFLR_DIOMAPPING2_DIO4_MASK                  0x3F
00497 #define RFLR_DIOMAPPING2_DIO4_00                    0x00  // Default
00498 #define RFLR_DIOMAPPING2_DIO4_01                    0x40
00499 #define RFLR_DIOMAPPING2_DIO4_10                    0x80
00500 #define RFLR_DIOMAPPING2_DIO4_11                    0xC0
00501 
00502 #define RFLR_DIOMAPPING2_DIO5_MASK                  0xCF
00503 #define RFLR_DIOMAPPING2_DIO5_00                    0x00  // Default
00504 #define RFLR_DIOMAPPING2_DIO5_01                    0x10
00505 #define RFLR_DIOMAPPING2_DIO5_10                    0x20
00506 #define RFLR_DIOMAPPING2_DIO5_11                    0x30
00507 
00508 #define RFLR_DIOMAPPING2_MAP_MASK                   0xFE
00509 #define RFLR_DIOMAPPING2_MAP_PREAMBLEDETECT         0x01
00510 #define RFLR_DIOMAPPING2_MAP_RSSI                   0x00  // Default
00511 
00512 /*!
00513  * RegVersion (Read Only)
00514  */
00515 
00516 /*!
00517  * RegPllHop
00518  */
00519 #define RFLR_PLLHOP_FASTHOP_MASK                    0x7F
00520 #define RFLR_PLLHOP_FASTHOP_ON                      0x80
00521 #define RFLR_PLLHOP_FASTHOP_OFF                     0x00 // Default
00522 
00523 /*!
00524  * RegTcxo
00525  */
00526 #define RFLR_TCXO_TCXOINPUT_MASK                    0xEF
00527 #define RFLR_TCXO_TCXOINPUT_ON                      0x10
00528 #define RFLR_TCXO_TCXOINPUT_OFF                     0x00  // Default
00529 
00530 /*!
00531  * RegPaDac
00532  */
00533 #define RFLR_PADAC_20DBM_MASK                       0xF8
00534 #define RFLR_PADAC_20DBM_ON                         0x07
00535 #define RFLR_PADAC_20DBM_OFF                        0x04  // Default
00536 
00537 /*!
00538  * RegFormerTemp
00539  */
00540 
00541 /*!
00542  * RegBitrateFrac
00543  */
00544 #define RF_BITRATEFRAC_MASK                         0xF0
00545 
00546 /*!
00547  * RegAgcRef
00548  */
00549 
00550 /*!
00551  * RegAgcThresh1
00552  */
00553 
00554 /*!
00555  * RegAgcThresh2
00556  */
00557 
00558 /*!
00559  * RegAgcThresh3
00560  */
00561 
00562 /*!
00563  * RegPll
00564  */
00565 #define RF_PLL_BANDWIDTH_MASK                       0x3F
00566 #define RF_PLL_BANDWIDTH_75                         0x00
00567 #define RF_PLL_BANDWIDTH_150                        0x40
00568 #define RF_PLL_BANDWIDTH_225                        0x80
00569 #define RF_PLL_BANDWIDTH_300                        0xC0  // Default
00570 
00571 #endif // __SX1276_REGS_LORA_H__