Steven Wray / mbed-dev

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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c@148:e70627d019e9, 2016-09-28 (annotated)

Committer:
StevieWray
Date:
Wed Sep 28 08:45:18 2016 +0000
Revision:
148:e70627d019e9
Parent:
144:ef7eb2e8f9f7 
Fixed DAC output on STM32F3 boards to allow 3 outputs

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f4xx_ll_fmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.5.0
<> 144:ef7eb2e8f9f7 6 * @date 06-May-2016
<> 144:ef7eb2e8f9f7 7 * @brief FMC Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Flexible Memory Controller (FMC) peripheral memories:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 ##### FMC peripheral features #####
<> 144:ef7eb2e8f9f7 18 ==============================================================================
<> 144:ef7eb2e8f9f7 19 [..] The Flexible memory controller (FMC) includes three memory controllers:
<> 144:ef7eb2e8f9f7 20 (+) The NOR/PSRAM memory controller
<> 144:ef7eb2e8f9f7 21 (+) The NAND/PC Card memory controller
<> 144:ef7eb2e8f9f7 22 (+) The Synchronous DRAM (SDRAM) controller
<> 144:ef7eb2e8f9f7 23
<> 144:ef7eb2e8f9f7 24 [..] The FMC functional block makes the interface with synchronous and asynchronous static
<> 144:ef7eb2e8f9f7 25 memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are:
<> 144:ef7eb2e8f9f7 26 (+) to translate AHB transactions into the appropriate external device protocol
<> 144:ef7eb2e8f9f7 27 (+) to meet the access time requirements of the external memory devices
<> 144:ef7eb2e8f9f7 28
<> 144:ef7eb2e8f9f7 29 [..] All external memories share the addresses, data and control signals with the controller.
<> 144:ef7eb2e8f9f7 30 Each external device is accessed by means of a unique Chip Select. The FMC performs
<> 144:ef7eb2e8f9f7 31 only one access at a time to an external device.
<> 144:ef7eb2e8f9f7 32 The main features of the FMC controller are the following:
<> 144:ef7eb2e8f9f7 33 (+) Interface with static-memory mapped devices including:
<> 144:ef7eb2e8f9f7 34 (++) Static random access memory (SRAM)
<> 144:ef7eb2e8f9f7 35 (++) Read-only memory (ROM)
<> 144:ef7eb2e8f9f7 36 (++) NOR Flash memory/OneNAND Flash memory
<> 144:ef7eb2e8f9f7 37 (++) PSRAM (4 memory banks)
<> 144:ef7eb2e8f9f7 38 (++) 16-bit PC Card compatible devices
<> 144:ef7eb2e8f9f7 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
<> 144:ef7eb2e8f9f7 40 data
<> 144:ef7eb2e8f9f7 41 (+) Interface with synchronous DRAM (SDRAM) memories
<> 144:ef7eb2e8f9f7 42 (+) Independent Chip Select control for each memory bank
<> 144:ef7eb2e8f9f7 43 (+) Independent configuration for each memory bank
<> 144:ef7eb2e8f9f7 44
<> 144:ef7eb2e8f9f7 45 @endverbatim
<> 144:ef7eb2e8f9f7 46 ******************************************************************************
<> 144:ef7eb2e8f9f7 47 * @attention
<> 144:ef7eb2e8f9f7 48 *
<> 144:ef7eb2e8f9f7 49 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 50 *
<> 144:ef7eb2e8f9f7 51 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 52 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 53 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 54 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 55 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 56 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 57 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 58 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 59 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 60 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 61 *
<> 144:ef7eb2e8f9f7 62 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 63 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 64 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 65 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 66 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 67 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 68 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 69 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 70 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 71 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 72 *
<> 144:ef7eb2e8f9f7 73 ******************************************************************************
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 77 #include "stm32f4xx_hal.h"
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /** @addtogroup STM32F4xx_HAL_Driver
<> 144:ef7eb2e8f9f7 80 * @{
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @defgroup FMC_LL FMC Low Layer
<> 144:ef7eb2e8f9f7 84 * @brief FMC driver modules
<> 144:ef7eb2e8f9f7 85 * @{
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 89
<> 144:ef7eb2e8f9f7 90 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 93 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 94 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 97 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 98 /** @addtogroup FMC_LL_Private_Functions
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @addtogroup FMC_LL_NORSRAM
<> 144:ef7eb2e8f9f7 103 * @brief NORSRAM Controller functions
<> 144:ef7eb2e8f9f7 104 *
<> 144:ef7eb2e8f9f7 105 @verbatim
<> 144:ef7eb2e8f9f7 106 ==============================================================================
<> 144:ef7eb2e8f9f7 107 ##### How to use NORSRAM device driver #####
<> 144:ef7eb2e8f9f7 108 ==============================================================================
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 [..]
<> 144:ef7eb2e8f9f7 111 This driver contains a set of APIs to interface with the FMC NORSRAM banks in order
<> 144:ef7eb2e8f9f7 112 to run the NORSRAM external devices.
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit()
<> 144:ef7eb2e8f9f7 115 (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 116 (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 117 (+) FMC NORSRAM bank extended timing configuration using the function
<> 144:ef7eb2e8f9f7 118 FMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 119 (+) FMC NORSRAM bank enable/disable write operation using the functions
<> 144:ef7eb2e8f9f7 120 FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable()
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 @endverbatim
<> 144:ef7eb2e8f9f7 124 * @{
<> 144:ef7eb2e8f9f7 125 */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1
<> 144:ef7eb2e8f9f7 128 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 129 *
<> 144:ef7eb2e8f9f7 130 @verbatim
<> 144:ef7eb2e8f9f7 131 ==============================================================================
<> 144:ef7eb2e8f9f7 132 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 133 ==============================================================================
<> 144:ef7eb2e8f9f7 134 [..]
<> 144:ef7eb2e8f9f7 135 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 136 (+) Initialize and configure the FMC NORSRAM interface
<> 144:ef7eb2e8f9f7 137 (+) De-initialize the FMC NORSRAM interface
<> 144:ef7eb2e8f9f7 138 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 @endverbatim
<> 144:ef7eb2e8f9f7 141 * @{
<> 144:ef7eb2e8f9f7 142 */
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /**
<> 144:ef7eb2e8f9f7 145 * @brief Initialize the FMC_NORSRAM device according to the specified
<> 144:ef7eb2e8f9f7 146 * control parameters in the FMC_NORSRAM_InitTypeDef
<> 144:ef7eb2e8f9f7 147 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 148 * @param Init: Pointer to NORSRAM Initialization structure
<> 144:ef7eb2e8f9f7 149 * @retval HAL status
<> 144:ef7eb2e8f9f7 150 */
<> 144:ef7eb2e8f9f7 151 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
<> 144:ef7eb2e8f9f7 152 {
<> 144:ef7eb2e8f9f7 153 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 /* Check the parameters */
<> 144:ef7eb2e8f9f7 156 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 157 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
<> 144:ef7eb2e8f9f7 158 assert_param(IS_FMC_MUX(Init->DataAddressMux));
<> 144:ef7eb2e8f9f7 159 assert_param(IS_FMC_MEMORY(Init->MemoryType));
<> 144:ef7eb2e8f9f7 160 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 161 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
<> 144:ef7eb2e8f9f7 162 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
<> 144:ef7eb2e8f9f7 163 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 164 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
<> 144:ef7eb2e8f9f7 165 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 166 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
<> 144:ef7eb2e8f9f7 167 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
<> 144:ef7eb2e8f9f7 168 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
<> 144:ef7eb2e8f9f7 169 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
<> 144:ef7eb2e8f9f7 170 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
<> 144:ef7eb2e8f9f7 174 #if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 175 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
<> 144:ef7eb2e8f9f7 176 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 /* Get the BTCR register value */
<> 144:ef7eb2e8f9f7 179 tmpr = Device->BTCR[Init->NSBank];
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 182 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN,
<> 144:ef7eb2e8f9f7 183 WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */
<> 144:ef7eb2e8f9f7 184 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
<> 144:ef7eb2e8f9f7 185 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
<> 144:ef7eb2e8f9f7 186 FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \
<> 144:ef7eb2e8f9f7 187 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
<> 144:ef7eb2e8f9f7 188 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \
<> 144:ef7eb2e8f9f7 189 FMC_BCR1_CCLKEN));
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Set NORSRAM device control parameters */
<> 144:ef7eb2e8f9f7 192 tmpr |= (uint32_t)(Init->DataAddressMux |\
<> 144:ef7eb2e8f9f7 193 Init->MemoryType |\
<> 144:ef7eb2e8f9f7 194 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 195 Init->BurstAccessMode |\
<> 144:ef7eb2e8f9f7 196 Init->WaitSignalPolarity |\
<> 144:ef7eb2e8f9f7 197 Init->WrapMode |\
<> 144:ef7eb2e8f9f7 198 Init->WaitSignalActive |\
<> 144:ef7eb2e8f9f7 199 Init->WriteOperation |\
<> 144:ef7eb2e8f9f7 200 Init->WaitSignal |\
<> 144:ef7eb2e8f9f7 201 Init->ExtendedMode |\
<> 144:ef7eb2e8f9f7 202 Init->AsynchronousWait |\
<> 144:ef7eb2e8f9f7 203 Init->PageSize |\
<> 144:ef7eb2e8f9f7 204 Init->WriteBurst |\
<> 144:ef7eb2e8f9f7 205 Init->ContinuousClock);
<> 144:ef7eb2e8f9f7 206 #else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
<> 144:ef7eb2e8f9f7 207 /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN,
<> 144:ef7eb2e8f9f7 208 WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */
<> 144:ef7eb2e8f9f7 209 tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \
<> 144:ef7eb2e8f9f7 210 FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \
<> 144:ef7eb2e8f9f7 211 FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \
<> 144:ef7eb2e8f9f7 212 FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \
<> 144:ef7eb2e8f9f7 213 FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \
<> 144:ef7eb2e8f9f7 214 FMC_BCR1_WFDIS));
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /* Set NORSRAM device control parameters */
<> 144:ef7eb2e8f9f7 217 tmpr |= (uint32_t)(Init->DataAddressMux |\
<> 144:ef7eb2e8f9f7 218 Init->MemoryType |\
<> 144:ef7eb2e8f9f7 219 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 220 Init->BurstAccessMode |\
<> 144:ef7eb2e8f9f7 221 Init->WaitSignalPolarity |\
<> 144:ef7eb2e8f9f7 222 Init->WaitSignalActive |\
<> 144:ef7eb2e8f9f7 223 Init->WriteOperation |\
<> 144:ef7eb2e8f9f7 224 Init->WaitSignal |\
<> 144:ef7eb2e8f9f7 225 Init->ExtendedMode |\
<> 144:ef7eb2e8f9f7 226 Init->AsynchronousWait |\
<> 144:ef7eb2e8f9f7 227 Init->WriteBurst |\
<> 144:ef7eb2e8f9f7 228 Init->ContinuousClock |\
<> 144:ef7eb2e8f9f7 229 Init->PageSize |\
<> 144:ef7eb2e8f9f7 230 Init->WriteFifo);
<> 144:ef7eb2e8f9f7 231 #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
<> 144:ef7eb2e8f9f7 232
<> 144:ef7eb2e8f9f7 233 if(Init->MemoryType == FMC_MEMORY_TYPE_NOR)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 Device->BTCR[Init->NSBank] = tmpr;
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
<> 144:ef7eb2e8f9f7 241 if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
<> 144:ef7eb2e8f9f7 242 {
<> 144:ef7eb2e8f9f7 243 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock);
<> 144:ef7eb2e8f9f7 244 }
<> 144:ef7eb2e8f9f7 245
<> 144:ef7eb2e8f9f7 246 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 247 if(Init->NSBank != FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 248 {
<> 144:ef7eb2e8f9f7 249 Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo);
<> 144:ef7eb2e8f9f7 250 }
<> 144:ef7eb2e8f9f7 251 #endif /* STM32F446xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 return HAL_OK;
<> 144:ef7eb2e8f9f7 254 }
<> 144:ef7eb2e8f9f7 255
<> 144:ef7eb2e8f9f7 256 /**
<> 144:ef7eb2e8f9f7 257 * @brief DeInitialize the FMC_NORSRAM peripheral
<> 144:ef7eb2e8f9f7 258 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 259 * @param ExDevice: Pointer to NORSRAM extended mode device instance
<> 144:ef7eb2e8f9f7 260 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 261 * @retval HAL status
<> 144:ef7eb2e8f9f7 262 */
<> 144:ef7eb2e8f9f7 263 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
<> 144:ef7eb2e8f9f7 264 {
<> 144:ef7eb2e8f9f7 265 /* Check the parameters */
<> 144:ef7eb2e8f9f7 266 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 267 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
<> 144:ef7eb2e8f9f7 268 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* Disable the FMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 271 __FMC_NORSRAM_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* De-initialize the FMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 274 /* FMC_NORSRAM_BANK1 */
<> 144:ef7eb2e8f9f7 275 if(Bank == FMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 Device->BTCR[Bank] = 0x000030DBU;
<> 144:ef7eb2e8f9f7 278 }
<> 144:ef7eb2e8f9f7 279 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 280 else
<> 144:ef7eb2e8f9f7 281 {
<> 144:ef7eb2e8f9f7 282 Device->BTCR[Bank] = 0x000030D2U;
<> 144:ef7eb2e8f9f7 283 }
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 Device->BTCR[Bank + 1] = 0x0FFFFFFFU;
<> 144:ef7eb2e8f9f7 286 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
<> 144:ef7eb2e8f9f7 287
<> 144:ef7eb2e8f9f7 288 return HAL_OK;
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290
<> 144:ef7eb2e8f9f7 291 /**
<> 144:ef7eb2e8f9f7 292 * @brief Initialize the FMC_NORSRAM Timing according to the specified
<> 144:ef7eb2e8f9f7 293 * parameters in the FMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 294 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 295 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 296 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 297 * @retval HAL status
<> 144:ef7eb2e8f9f7 298 */
<> 144:ef7eb2e8f9f7 299 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 /* Check the parameters */
<> 144:ef7eb2e8f9f7 304 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 305 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 306 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 307 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 308 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 309 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 310 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 311 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 312 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 /* Get the BTCR register value */
<> 144:ef7eb2e8f9f7 315 tmpr = Device->BTCR[Bank + 1U];
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */
<> 144:ef7eb2e8f9f7 318 tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \
<> 144:ef7eb2e8f9f7 319 FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \
<> 144:ef7eb2e8f9f7 320 FMC_BTR1_ACCMOD));
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* Set FMC_NORSRAM device timing parameters */
<> 144:ef7eb2e8f9f7 323 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
<> 144:ef7eb2e8f9f7 324 ((Timing->AddressHoldTime) << 4U) |\
<> 144:ef7eb2e8f9f7 325 ((Timing->DataSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 326 ((Timing->BusTurnAroundDuration) << 16U) |\
<> 144:ef7eb2e8f9f7 327 (((Timing->CLKDivision) - 1U) << 20U) |\
<> 144:ef7eb2e8f9f7 328 (((Timing->DataLatency) - 2U) << 24U) |\
<> 144:ef7eb2e8f9f7 329 (Timing->AccessMode));
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 Device->BTCR[Bank + 1U] = tmpr;
<> 144:ef7eb2e8f9f7 332
<> 144:ef7eb2e8f9f7 333 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
<> 144:ef7eb2e8f9f7 334 if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(((uint32_t)0x0FU) << 20U));
<> 144:ef7eb2e8f9f7 337 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U);
<> 144:ef7eb2e8f9f7 338 Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr;
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 return HAL_OK;
<> 144:ef7eb2e8f9f7 342 }
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
<> 144:ef7eb2e8f9f7 346 * parameters in the FMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 347 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 348 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 349 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 350 * @retval HAL status
<> 144:ef7eb2e8f9f7 351 */
<> 144:ef7eb2e8f9f7 352 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
<> 144:ef7eb2e8f9f7 353 {
<> 144:ef7eb2e8f9f7 354 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* Check the parameters */
<> 144:ef7eb2e8f9f7 357 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
<> 144:ef7eb2e8f9f7 360 if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
<> 144:ef7eb2e8f9f7 361 {
<> 144:ef7eb2e8f9f7 362 /* Check the parameters */
<> 144:ef7eb2e8f9f7 363 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
<> 144:ef7eb2e8f9f7 364 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 365 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 366 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 367 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 368 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 369 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Get the BWTR register value */
<> 144:ef7eb2e8f9f7 372 tmpr = Device->BWTR[Bank];
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */
<> 144:ef7eb2e8f9f7 375 tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \
<> 144:ef7eb2e8f9f7 376 FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD));
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 tmpr |= (uint32_t)(Timing->AddressSetupTime |\
<> 144:ef7eb2e8f9f7 379 ((Timing->AddressHoldTime) << 4U) |\
<> 144:ef7eb2e8f9f7 380 ((Timing->DataSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 381 ((Timing->BusTurnAroundDuration) << 16U) |\
<> 144:ef7eb2e8f9f7 382 (Timing->AccessMode));
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 Device->BWTR[Bank] = tmpr;
<> 144:ef7eb2e8f9f7 385 }
<> 144:ef7eb2e8f9f7 386 else
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 Device->BWTR[Bank] = 0x0FFFFFFFU;
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 return HAL_OK;
<> 144:ef7eb2e8f9f7 392 }
<> 144:ef7eb2e8f9f7 393 /**
<> 144:ef7eb2e8f9f7 394 * @}
<> 144:ef7eb2e8f9f7 395 */
<> 144:ef7eb2e8f9f7 396
<> 144:ef7eb2e8f9f7 397 /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2
<> 144:ef7eb2e8f9f7 398 * @brief management functions
<> 144:ef7eb2e8f9f7 399 *
<> 144:ef7eb2e8f9f7 400 @verbatim
<> 144:ef7eb2e8f9f7 401 ==============================================================================
<> 144:ef7eb2e8f9f7 402 ##### FMC_NORSRAM Control functions #####
<> 144:ef7eb2e8f9f7 403 ==============================================================================
<> 144:ef7eb2e8f9f7 404 [..]
<> 144:ef7eb2e8f9f7 405 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 406 the FMC NORSRAM interface.
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 @endverbatim
<> 144:ef7eb2e8f9f7 409 * @{
<> 144:ef7eb2e8f9f7 410 */
<> 144:ef7eb2e8f9f7 411 /**
<> 144:ef7eb2e8f9f7 412 * @brief Enables dynamically FMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 413 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 414 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 415 * @retval HAL status
<> 144:ef7eb2e8f9f7 416 */
<> 144:ef7eb2e8f9f7 417 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 418 {
<> 144:ef7eb2e8f9f7 419 /* Check the parameters */
<> 144:ef7eb2e8f9f7 420 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 421 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 /* Enable write operation */
<> 144:ef7eb2e8f9f7 424 Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE;
<> 144:ef7eb2e8f9f7 425
<> 144:ef7eb2e8f9f7 426 return HAL_OK;
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 /**
<> 144:ef7eb2e8f9f7 430 * @brief Disables dynamically FMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 431 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 432 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 433 * @retval HAL status
<> 144:ef7eb2e8f9f7 434 */
<> 144:ef7eb2e8f9f7 435 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 436 {
<> 144:ef7eb2e8f9f7 437 /* Check the parameters */
<> 144:ef7eb2e8f9f7 438 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 439 assert_param(IS_FMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 440
<> 144:ef7eb2e8f9f7 441 /* Disable write operation */
<> 144:ef7eb2e8f9f7 442 Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE;
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 return HAL_OK;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /**
<> 144:ef7eb2e8f9f7 448 * @}
<> 144:ef7eb2e8f9f7 449 */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /**
<> 144:ef7eb2e8f9f7 452 * @}
<> 144:ef7eb2e8f9f7 453 */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /** @addtogroup FMC_LL_NAND
<> 144:ef7eb2e8f9f7 456 * @brief NAND Controller functions
<> 144:ef7eb2e8f9f7 457 *
<> 144:ef7eb2e8f9f7 458 @verbatim
<> 144:ef7eb2e8f9f7 459 ==============================================================================
<> 144:ef7eb2e8f9f7 460 ##### How to use NAND device driver #####
<> 144:ef7eb2e8f9f7 461 ==============================================================================
<> 144:ef7eb2e8f9f7 462 [..]
<> 144:ef7eb2e8f9f7 463 This driver contains a set of APIs to interface with the FMC NAND banks in order
<> 144:ef7eb2e8f9f7 464 to run the NAND external devices.
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 (+) FMC NAND bank reset using the function FMC_NAND_DeInit()
<> 144:ef7eb2e8f9f7 467 (+) FMC NAND bank control configuration using the function FMC_NAND_Init()
<> 144:ef7eb2e8f9f7 468 (+) FMC NAND bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 469 FMC_NAND_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 470 (+) FMC NAND bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 471 FMC_NAND_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 472 (+) FMC NAND bank enable/disable ECC correction feature using the functions
<> 144:ef7eb2e8f9f7 473 FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable()
<> 144:ef7eb2e8f9f7 474 (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC()
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 @endverbatim
<> 144:ef7eb2e8f9f7 477 * @{
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
<> 144:ef7eb2e8f9f7 481 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 482 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 483 *
<> 144:ef7eb2e8f9f7 484 @verbatim
<> 144:ef7eb2e8f9f7 485 ==============================================================================
<> 144:ef7eb2e8f9f7 486 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 487 ==============================================================================
<> 144:ef7eb2e8f9f7 488 [..]
<> 144:ef7eb2e8f9f7 489 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 490 (+) Initialize and configure the FMC NAND interface
<> 144:ef7eb2e8f9f7 491 (+) De-initialize the FMC NAND interface
<> 144:ef7eb2e8f9f7 492 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 @endverbatim
<> 144:ef7eb2e8f9f7 495 * @{
<> 144:ef7eb2e8f9f7 496 */
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /**
<> 144:ef7eb2e8f9f7 499 * @brief Initializes the FMC_NAND device according to the specified
<> 144:ef7eb2e8f9f7 500 * control parameters in the FMC_NAND_HandleTypeDef
<> 144:ef7eb2e8f9f7 501 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 502 * @param Init: Pointer to NAND Initialization structure
<> 144:ef7eb2e8f9f7 503 * @retval HAL status
<> 144:ef7eb2e8f9f7 504 */
<> 144:ef7eb2e8f9f7 505 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 508
<> 144:ef7eb2e8f9f7 509 /* Check the parameters */
<> 144:ef7eb2e8f9f7 510 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 511 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
<> 144:ef7eb2e8f9f7 512 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 513 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 514 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
<> 144:ef7eb2e8f9f7 515 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
<> 144:ef7eb2e8f9f7 516 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 517 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 /* Get the NAND bank register value */
<> 144:ef7eb2e8f9f7 520 tmpr = Device->PCR;
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
<> 144:ef7eb2e8f9f7 523 tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \
<> 144:ef7eb2e8f9f7 524 FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \
<> 144:ef7eb2e8f9f7 525 FMC_PCR_TAR | FMC_PCR_ECCPS));
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Set NAND device control parameters */
<> 144:ef7eb2e8f9f7 528 tmpr |= (uint32_t)(Init->Waitfeature |\
<> 144:ef7eb2e8f9f7 529 FMC_PCR_MEMORY_TYPE_NAND |\
<> 144:ef7eb2e8f9f7 530 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 531 Init->EccComputation |\
<> 144:ef7eb2e8f9f7 532 Init->ECCPageSize |\
<> 144:ef7eb2e8f9f7 533 ((Init->TCLRSetupTime) << 9U) |\
<> 144:ef7eb2e8f9f7 534 ((Init->TARSetupTime) << 13U));
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* NAND bank registers configuration */
<> 144:ef7eb2e8f9f7 537 Device->PCR = tmpr;
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 return HAL_OK;
<> 144:ef7eb2e8f9f7 540 }
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @brief Initializes the FMC_NAND Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 544 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 545 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 546 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 547 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 548 * @retval HAL status
<> 144:ef7eb2e8f9f7 549 */
<> 144:ef7eb2e8f9f7 550 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 551 {
<> 144:ef7eb2e8f9f7 552 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 /* Check the parameters */
<> 144:ef7eb2e8f9f7 555 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 556 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 557 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 558 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 559 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 560 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Get the NAND bank 2 register value */
<> 144:ef7eb2e8f9f7 563 tmpr = Device->PMEM;
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
<> 144:ef7eb2e8f9f7 567 tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \
<> 144:ef7eb2e8f9f7 568 FMC_PMEM_MEMHIZ2));
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 /* Set FMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 571 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 572 ((Timing->WaitSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 573 ((Timing->HoldSetupTime) << 16U) |\
<> 144:ef7eb2e8f9f7 574 ((Timing->HiZSetupTime) << 24U)
<> 144:ef7eb2e8f9f7 575 );
<> 144:ef7eb2e8f9f7 576
<> 144:ef7eb2e8f9f7 577 /* NAND bank registers configuration */
<> 144:ef7eb2e8f9f7 578 Device->PMEM = tmpr;
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 return HAL_OK;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /**
<> 144:ef7eb2e8f9f7 584 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 585 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 586 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 587 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 588 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 589 * @retval HAL status
<> 144:ef7eb2e8f9f7 590 */
<> 144:ef7eb2e8f9f7 591 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 592 {
<> 144:ef7eb2e8f9f7 593 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /* Check the parameters */
<> 144:ef7eb2e8f9f7 596 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 597 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 598 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 599 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 600 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 601 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Get the NAND bank register value */
<> 144:ef7eb2e8f9f7 604 tmpr = Device->PATT;
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
<> 144:ef7eb2e8f9f7 607 tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \
<> 144:ef7eb2e8f9f7 608 FMC_PATT_ATTHIZ2));
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Set FMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 611 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 612 ((Timing->WaitSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 613 ((Timing->HoldSetupTime) << 16U) |\
<> 144:ef7eb2e8f9f7 614 ((Timing->HiZSetupTime) << 24U));
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* NAND bank registers configuration */
<> 144:ef7eb2e8f9f7 617 Device->PATT = tmpr;
<> 144:ef7eb2e8f9f7 618
<> 144:ef7eb2e8f9f7 619 return HAL_OK;
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622
<> 144:ef7eb2e8f9f7 623 /**
<> 144:ef7eb2e8f9f7 624 * @brief DeInitializes the FMC_NAND device
<> 144:ef7eb2e8f9f7 625 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 626 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 627 * @retval HAL status
<> 144:ef7eb2e8f9f7 628 */
<> 144:ef7eb2e8f9f7 629 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 630 {
<> 144:ef7eb2e8f9f7 631 /* Check the parameters */
<> 144:ef7eb2e8f9f7 632 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 633 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 634
<> 144:ef7eb2e8f9f7 635 /* Disable the NAND Bank */
<> 144:ef7eb2e8f9f7 636 __FMC_NAND_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 637
<> 144:ef7eb2e8f9f7 638 /* De-initialize the NAND Bank */
<> 144:ef7eb2e8f9f7 639 /* Set the FMC_NAND_BANK registers to their reset values */
<> 144:ef7eb2e8f9f7 640 Device->PCR = 0x00000018U;
<> 144:ef7eb2e8f9f7 641 Device->SR = 0x00000040U;
<> 144:ef7eb2e8f9f7 642 Device->PMEM = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 643 Device->PATT = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 return HAL_OK;
<> 144:ef7eb2e8f9f7 646 }
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 /**
<> 144:ef7eb2e8f9f7 649 * @}
<> 144:ef7eb2e8f9f7 650 */
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 /** @defgroup HAL_FMC_NAND_Group2 Control functions
<> 144:ef7eb2e8f9f7 654 * @brief management functions
<> 144:ef7eb2e8f9f7 655 *
<> 144:ef7eb2e8f9f7 656 @verbatim
<> 144:ef7eb2e8f9f7 657 ==============================================================================
<> 144:ef7eb2e8f9f7 658 ##### FMC_NAND Control functions #####
<> 144:ef7eb2e8f9f7 659 ==============================================================================
<> 144:ef7eb2e8f9f7 660 [..]
<> 144:ef7eb2e8f9f7 661 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 662 the FMC NAND interface.
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 @endverbatim
<> 144:ef7eb2e8f9f7 665 * @{
<> 144:ef7eb2e8f9f7 666 */
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 /**
<> 144:ef7eb2e8f9f7 670 * @brief Enables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 671 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 672 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 673 * @retval HAL status
<> 144:ef7eb2e8f9f7 674 */
<> 144:ef7eb2e8f9f7 675 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 676 {
<> 144:ef7eb2e8f9f7 677 /* Check the parameters */
<> 144:ef7eb2e8f9f7 678 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 679 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /* Enable ECC feature */
<> 144:ef7eb2e8f9f7 682 Device->PCR |= FMC_PCR_ECCEN;
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 return HAL_OK;
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 /**
<> 144:ef7eb2e8f9f7 689 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 690 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 691 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 692 * @retval HAL status
<> 144:ef7eb2e8f9f7 693 */
<> 144:ef7eb2e8f9f7 694 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 695 {
<> 144:ef7eb2e8f9f7 696 /* Check the parameters */
<> 144:ef7eb2e8f9f7 697 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 698 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 699
<> 144:ef7eb2e8f9f7 700 /* Disable ECC feature */
<> 144:ef7eb2e8f9f7 701 Device->PCR &= ~FMC_PCR_ECCEN;
<> 144:ef7eb2e8f9f7 702
<> 144:ef7eb2e8f9f7 703 return HAL_OK;
<> 144:ef7eb2e8f9f7 704 }
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 708 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 709 * @param ECCval: Pointer to ECC value
<> 144:ef7eb2e8f9f7 710 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 711 * @param Timeout: Timeout wait value
<> 144:ef7eb2e8f9f7 712 * @retval HAL status
<> 144:ef7eb2e8f9f7 713 */
<> 144:ef7eb2e8f9f7 714 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 715 {
<> 144:ef7eb2e8f9f7 716 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /* Check the parameters */
<> 144:ef7eb2e8f9f7 719 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 720 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722 /* Get tick */
<> 144:ef7eb2e8f9f7 723 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 724
<> 144:ef7eb2e8f9f7 725 /* Wait until FIFO is empty */
<> 144:ef7eb2e8f9f7 726 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
<> 144:ef7eb2e8f9f7 727 {
<> 144:ef7eb2e8f9f7 728 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 729 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 730 {
<> 144:ef7eb2e8f9f7 731 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735 }
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Get the ECCR register value */
<> 144:ef7eb2e8f9f7 739 *ECCval = (uint32_t)Device->ECCR;
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 return HAL_OK;
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 /**
<> 144:ef7eb2e8f9f7 745 * @}
<> 144:ef7eb2e8f9f7 746 */
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
<> 144:ef7eb2e8f9f7 749 /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 750 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 751 *
<> 144:ef7eb2e8f9f7 752 @verbatim
<> 144:ef7eb2e8f9f7 753 ==============================================================================
<> 144:ef7eb2e8f9f7 754 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 755 ==============================================================================
<> 144:ef7eb2e8f9f7 756 [..]
<> 144:ef7eb2e8f9f7 757 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 758 (+) Initialize and configure the FMC NAND interface
<> 144:ef7eb2e8f9f7 759 (+) De-initialize the FMC NAND interface
<> 144:ef7eb2e8f9f7 760 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 @endverbatim
<> 144:ef7eb2e8f9f7 763 * @{
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765 /**
<> 144:ef7eb2e8f9f7 766 * @brief Initializes the FMC_NAND device according to the specified
<> 144:ef7eb2e8f9f7 767 * control parameters in the FMC_NAND_HandleTypeDef
<> 144:ef7eb2e8f9f7 768 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 769 * @param Init: Pointer to NAND Initialization structure
<> 144:ef7eb2e8f9f7 770 * @retval HAL status
<> 144:ef7eb2e8f9f7 771 */
<> 144:ef7eb2e8f9f7 772 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 773 {
<> 144:ef7eb2e8f9f7 774 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /* Check the parameters */
<> 144:ef7eb2e8f9f7 777 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 778 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
<> 144:ef7eb2e8f9f7 779 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 780 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 781 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
<> 144:ef7eb2e8f9f7 782 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
<> 144:ef7eb2e8f9f7 783 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 784 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 if(Init->NandBank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 787 {
<> 144:ef7eb2e8f9f7 788 /* Get the NAND bank 2 register value */
<> 144:ef7eb2e8f9f7 789 tmpr = Device->PCR2;
<> 144:ef7eb2e8f9f7 790 }
<> 144:ef7eb2e8f9f7 791 else
<> 144:ef7eb2e8f9f7 792 {
<> 144:ef7eb2e8f9f7 793 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 794 tmpr = Device->PCR3;
<> 144:ef7eb2e8f9f7 795 }
<> 144:ef7eb2e8f9f7 796
<> 144:ef7eb2e8f9f7 797 /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */
<> 144:ef7eb2e8f9f7 798 tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \
<> 144:ef7eb2e8f9f7 799 FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
<> 144:ef7eb2e8f9f7 800 FMC_PCR2_TAR | FMC_PCR2_ECCPS));
<> 144:ef7eb2e8f9f7 801
<> 144:ef7eb2e8f9f7 802 /* Set NAND device control parameters */
<> 144:ef7eb2e8f9f7 803 tmpr |= (uint32_t)(Init->Waitfeature |\
<> 144:ef7eb2e8f9f7 804 FMC_PCR_MEMORY_TYPE_NAND |\
<> 144:ef7eb2e8f9f7 805 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 806 Init->EccComputation |\
<> 144:ef7eb2e8f9f7 807 Init->ECCPageSize |\
<> 144:ef7eb2e8f9f7 808 ((Init->TCLRSetupTime) << 9U) |\
<> 144:ef7eb2e8f9f7 809 ((Init->TARSetupTime) << 13U));
<> 144:ef7eb2e8f9f7 810
<> 144:ef7eb2e8f9f7 811 if(Init->NandBank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 812 {
<> 144:ef7eb2e8f9f7 813 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 814 Device->PCR2 = tmpr;
<> 144:ef7eb2e8f9f7 815 }
<> 144:ef7eb2e8f9f7 816 else
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 819 Device->PCR3 = tmpr;
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 return HAL_OK;
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 }
<> 144:ef7eb2e8f9f7 825
<> 144:ef7eb2e8f9f7 826 /**
<> 144:ef7eb2e8f9f7 827 * @brief Initializes the FMC_NAND Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 828 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 829 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 830 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 831 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 832 * @retval HAL status
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 835 {
<> 144:ef7eb2e8f9f7 836 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 /* Check the parameters */
<> 144:ef7eb2e8f9f7 839 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 840 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 841 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 842 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 843 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 844 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 /* Get the NAND bank 2 register value */
<> 144:ef7eb2e8f9f7 849 tmpr = Device->PMEM2;
<> 144:ef7eb2e8f9f7 850 }
<> 144:ef7eb2e8f9f7 851 else
<> 144:ef7eb2e8f9f7 852 {
<> 144:ef7eb2e8f9f7 853 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 854 tmpr = Device->PMEM3;
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
<> 144:ef7eb2e8f9f7 858 tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \
<> 144:ef7eb2e8f9f7 859 FMC_PMEM2_MEMHIZ2));
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /* Set FMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 862 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 863 ((Timing->WaitSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 864 ((Timing->HoldSetupTime) << 16U) |\
<> 144:ef7eb2e8f9f7 865 ((Timing->HiZSetupTime) << 24U)
<> 144:ef7eb2e8f9f7 866 );
<> 144:ef7eb2e8f9f7 867
<> 144:ef7eb2e8f9f7 868 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 869 {
<> 144:ef7eb2e8f9f7 870 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 871 Device->PMEM2 = tmpr;
<> 144:ef7eb2e8f9f7 872 }
<> 144:ef7eb2e8f9f7 873 else
<> 144:ef7eb2e8f9f7 874 {
<> 144:ef7eb2e8f9f7 875 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 876 Device->PMEM3 = tmpr;
<> 144:ef7eb2e8f9f7 877 }
<> 144:ef7eb2e8f9f7 878
<> 144:ef7eb2e8f9f7 879 return HAL_OK;
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881
<> 144:ef7eb2e8f9f7 882 /**
<> 144:ef7eb2e8f9f7 883 * @brief Initializes the FMC_NAND Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 884 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 885 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 886 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 887 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 888 * @retval HAL status
<> 144:ef7eb2e8f9f7 889 */
<> 144:ef7eb2e8f9f7 890 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 891 {
<> 144:ef7eb2e8f9f7 892 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 /* Check the parameters */
<> 144:ef7eb2e8f9f7 895 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 896 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 897 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 898 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 899 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 900 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 901
<> 144:ef7eb2e8f9f7 902 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 903 {
<> 144:ef7eb2e8f9f7 904 /* Get the NAND bank 2 register value */
<> 144:ef7eb2e8f9f7 905 tmpr = Device->PATT2;
<> 144:ef7eb2e8f9f7 906 }
<> 144:ef7eb2e8f9f7 907 else
<> 144:ef7eb2e8f9f7 908 {
<> 144:ef7eb2e8f9f7 909 /* Get the NAND bank 3 register value */
<> 144:ef7eb2e8f9f7 910 tmpr = Device->PATT3;
<> 144:ef7eb2e8f9f7 911 }
<> 144:ef7eb2e8f9f7 912
<> 144:ef7eb2e8f9f7 913 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
<> 144:ef7eb2e8f9f7 914 tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \
<> 144:ef7eb2e8f9f7 915 FMC_PATT2_ATTHIZ2));
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* Set FMC_NAND device timing parameters */
<> 144:ef7eb2e8f9f7 918 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 919 ((Timing->WaitSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 920 ((Timing->HoldSetupTime) << 16U) |\
<> 144:ef7eb2e8f9f7 921 ((Timing->HiZSetupTime) << 24U));
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 924 {
<> 144:ef7eb2e8f9f7 925 /* NAND bank 2 registers configuration */
<> 144:ef7eb2e8f9f7 926 Device->PATT2 = tmpr;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928 else
<> 144:ef7eb2e8f9f7 929 {
<> 144:ef7eb2e8f9f7 930 /* NAND bank 3 registers configuration */
<> 144:ef7eb2e8f9f7 931 Device->PATT3 = tmpr;
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 return HAL_OK;
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @brief DeInitializes the FMC_NAND device
<> 144:ef7eb2e8f9f7 939 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 940 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 941 * @retval HAL status
<> 144:ef7eb2e8f9f7 942 */
<> 144:ef7eb2e8f9f7 943 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 944 {
<> 144:ef7eb2e8f9f7 945 /* Check the parameters */
<> 144:ef7eb2e8f9f7 946 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 947 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /* Disable the NAND Bank */
<> 144:ef7eb2e8f9f7 950 __FMC_NAND_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 951
<> 144:ef7eb2e8f9f7 952 /* De-initialize the NAND Bank */
<> 144:ef7eb2e8f9f7 953 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 954 {
<> 144:ef7eb2e8f9f7 955 /* Set the FMC_NAND_BANK2 registers to their reset values */
<> 144:ef7eb2e8f9f7 956 Device->PCR2 = 0x00000018U;
<> 144:ef7eb2e8f9f7 957 Device->SR2 = 0x00000040U;
<> 144:ef7eb2e8f9f7 958 Device->PMEM2 = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 959 Device->PATT2 = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 960 }
<> 144:ef7eb2e8f9f7 961 /* FMC_Bank3_NAND */
<> 144:ef7eb2e8f9f7 962 else
<> 144:ef7eb2e8f9f7 963 {
<> 144:ef7eb2e8f9f7 964 /* Set the FMC_NAND_BANK3 registers to their reset values */
<> 144:ef7eb2e8f9f7 965 Device->PCR3 = 0x00000018U;
<> 144:ef7eb2e8f9f7 966 Device->SR3 = 0x00000040U;
<> 144:ef7eb2e8f9f7 967 Device->PMEM3 = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 968 Device->PATT3 = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 969 }
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 return HAL_OK;
<> 144:ef7eb2e8f9f7 972 }
<> 144:ef7eb2e8f9f7 973
<> 144:ef7eb2e8f9f7 974 /**
<> 144:ef7eb2e8f9f7 975 * @}
<> 144:ef7eb2e8f9f7 976 */
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 /** @addtogroup FMC_LL_NAND_Private_Functions_Group2
<> 144:ef7eb2e8f9f7 979 * @brief management functions
<> 144:ef7eb2e8f9f7 980 *
<> 144:ef7eb2e8f9f7 981 @verbatim
<> 144:ef7eb2e8f9f7 982 ==============================================================================
<> 144:ef7eb2e8f9f7 983 ##### FMC_NAND Control functions #####
<> 144:ef7eb2e8f9f7 984 ==============================================================================
<> 144:ef7eb2e8f9f7 985 [..]
<> 144:ef7eb2e8f9f7 986 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 987 the FMC NAND interface.
<> 144:ef7eb2e8f9f7 988
<> 144:ef7eb2e8f9f7 989 @endverbatim
<> 144:ef7eb2e8f9f7 990 * @{
<> 144:ef7eb2e8f9f7 991 */
<> 144:ef7eb2e8f9f7 992 /**
<> 144:ef7eb2e8f9f7 993 * @brief Enables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 994 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 995 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 996 * @retval HAL status
<> 144:ef7eb2e8f9f7 997 */
<> 144:ef7eb2e8f9f7 998 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1001 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1002 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 1003
<> 144:ef7eb2e8f9f7 1004 /* Enable ECC feature */
<> 144:ef7eb2e8f9f7 1005 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 1006 {
<> 144:ef7eb2e8f9f7 1007 Device->PCR2 |= FMC_PCR2_ECCEN;
<> 144:ef7eb2e8f9f7 1008 }
<> 144:ef7eb2e8f9f7 1009 else
<> 144:ef7eb2e8f9f7 1010 {
<> 144:ef7eb2e8f9f7 1011 Device->PCR3 |= FMC_PCR3_ECCEN;
<> 144:ef7eb2e8f9f7 1012 }
<> 144:ef7eb2e8f9f7 1013
<> 144:ef7eb2e8f9f7 1014 return HAL_OK;
<> 144:ef7eb2e8f9f7 1015 }
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /**
<> 144:ef7eb2e8f9f7 1018 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 1019 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 1020 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 1021 * @retval HAL status
<> 144:ef7eb2e8f9f7 1022 */
<> 144:ef7eb2e8f9f7 1023 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 1024 {
<> 144:ef7eb2e8f9f7 1025 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1026 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1027 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 1028
<> 144:ef7eb2e8f9f7 1029 /* Disable ECC feature */
<> 144:ef7eb2e8f9f7 1030 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 1031 {
<> 144:ef7eb2e8f9f7 1032 Device->PCR2 &= ~FMC_PCR2_ECCEN;
<> 144:ef7eb2e8f9f7 1033 }
<> 144:ef7eb2e8f9f7 1034 else
<> 144:ef7eb2e8f9f7 1035 {
<> 144:ef7eb2e8f9f7 1036 Device->PCR3 &= ~FMC_PCR3_ECCEN;
<> 144:ef7eb2e8f9f7 1037 }
<> 144:ef7eb2e8f9f7 1038
<> 144:ef7eb2e8f9f7 1039 return HAL_OK;
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 /**
<> 144:ef7eb2e8f9f7 1043 * @brief Disables dynamically FMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 1044 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 1045 * @param ECCval: Pointer to ECC value
<> 144:ef7eb2e8f9f7 1046 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 1047 * @param Timeout: Timeout wait value
<> 144:ef7eb2e8f9f7 1048 * @retval HAL status
<> 144:ef7eb2e8f9f7 1049 */
<> 144:ef7eb2e8f9f7 1050 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1051 {
<> 144:ef7eb2e8f9f7 1052 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1053
<> 144:ef7eb2e8f9f7 1054 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1055 assert_param(IS_FMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1056 assert_param(IS_FMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 1057
<> 144:ef7eb2e8f9f7 1058 /* Get tick */
<> 144:ef7eb2e8f9f7 1059 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1060
<> 144:ef7eb2e8f9f7 1061 /* Wait until FIFO is empty */
<> 144:ef7eb2e8f9f7 1062 while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
<> 144:ef7eb2e8f9f7 1063 {
<> 144:ef7eb2e8f9f7 1064 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1065 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1066 {
<> 144:ef7eb2e8f9f7 1067 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1070 }
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072 }
<> 144:ef7eb2e8f9f7 1073
<> 144:ef7eb2e8f9f7 1074 if(Bank == FMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 1075 {
<> 144:ef7eb2e8f9f7 1076 /* Get the ECCR2 register value */
<> 144:ef7eb2e8f9f7 1077 *ECCval = (uint32_t)Device->ECCR2;
<> 144:ef7eb2e8f9f7 1078 }
<> 144:ef7eb2e8f9f7 1079 else
<> 144:ef7eb2e8f9f7 1080 {
<> 144:ef7eb2e8f9f7 1081 /* Get the ECCR3 register value */
<> 144:ef7eb2e8f9f7 1082 *ECCval = (uint32_t)Device->ECCR3;
<> 144:ef7eb2e8f9f7 1083 }
<> 144:ef7eb2e8f9f7 1084
<> 144:ef7eb2e8f9f7 1085 return HAL_OK;
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088 /**
<> 144:ef7eb2e8f9f7 1089 * @}
<> 144:ef7eb2e8f9f7 1090 */
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 #endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */
<> 144:ef7eb2e8f9f7 1093 /**
<> 144:ef7eb2e8f9f7 1094 * @}
<> 144:ef7eb2e8f9f7 1095 */
<> 144:ef7eb2e8f9f7 1096
<> 144:ef7eb2e8f9f7 1097 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
<> 144:ef7eb2e8f9f7 1098 /** @addtogroup FMC_LL_PCCARD
<> 144:ef7eb2e8f9f7 1099 * @brief PCCARD Controller functions
<> 144:ef7eb2e8f9f7 1100 *
<> 144:ef7eb2e8f9f7 1101 @verbatim
<> 144:ef7eb2e8f9f7 1102 ==============================================================================
<> 144:ef7eb2e8f9f7 1103 ##### How to use PCCARD device driver #####
<> 144:ef7eb2e8f9f7 1104 ==============================================================================
<> 144:ef7eb2e8f9f7 1105 [..]
<> 144:ef7eb2e8f9f7 1106 This driver contains a set of APIs to interface with the FMC PCCARD bank in order
<> 144:ef7eb2e8f9f7 1107 to run the PCCARD/compact flash external devices.
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit()
<> 144:ef7eb2e8f9f7 1110 (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init()
<> 144:ef7eb2e8f9f7 1111 (+) FMC PCCARD bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 1112 FMC_PCCARD_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 1113 (+) FMC PCCARD bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 1114 FMC_PCCARD_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 1115 (+) FMC PCCARD bank IO space timing configuration using the function
<> 144:ef7eb2e8f9f7 1116 FMC_PCCARD_IOSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 1117 @endverbatim
<> 144:ef7eb2e8f9f7 1118 * @{
<> 144:ef7eb2e8f9f7 1119 */
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1
<> 144:ef7eb2e8f9f7 1122 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 1123 *
<> 144:ef7eb2e8f9f7 1124 @verbatim
<> 144:ef7eb2e8f9f7 1125 ==============================================================================
<> 144:ef7eb2e8f9f7 1126 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 1127 ==============================================================================
<> 144:ef7eb2e8f9f7 1128 [..]
<> 144:ef7eb2e8f9f7 1129 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1130 (+) Initialize and configure the FMC PCCARD interface
<> 144:ef7eb2e8f9f7 1131 (+) De-initialize the FMC PCCARD interface
<> 144:ef7eb2e8f9f7 1132 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 @endverbatim
<> 144:ef7eb2e8f9f7 1135 * @{
<> 144:ef7eb2e8f9f7 1136 */
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /**
<> 144:ef7eb2e8f9f7 1139 * @brief Initializes the FMC_PCCARD device according to the specified
<> 144:ef7eb2e8f9f7 1140 * control parameters in the FMC_PCCARD_HandleTypeDef
<> 144:ef7eb2e8f9f7 1141 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 1142 * @param Init: Pointer to PCCARD Initialization structure
<> 144:ef7eb2e8f9f7 1143 * @retval HAL status
<> 144:ef7eb2e8f9f7 1144 */
<> 144:ef7eb2e8f9f7 1145 HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 1146 {
<> 144:ef7eb2e8f9f7 1147 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1150 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1151 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 1152 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 1153 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /* Get PCCARD control register value */
<> 144:ef7eb2e8f9f7 1156 tmpr = Device->PCR4;
<> 144:ef7eb2e8f9f7 1157
<> 144:ef7eb2e8f9f7 1158 /* Clear TAR, TCLR, PWAITEN and PWID bits */
<> 144:ef7eb2e8f9f7 1159 tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \
<> 144:ef7eb2e8f9f7 1160 FMC_PCR4_PWID));
<> 144:ef7eb2e8f9f7 1161
<> 144:ef7eb2e8f9f7 1162 /* Set FMC_PCCARD device control parameters */
<> 144:ef7eb2e8f9f7 1163 tmpr |= (uint32_t)(Init->Waitfeature |\
<> 144:ef7eb2e8f9f7 1164 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\
<> 144:ef7eb2e8f9f7 1165 (Init->TCLRSetupTime << 9U) |\
<> 144:ef7eb2e8f9f7 1166 (Init->TARSetupTime << 13U));
<> 144:ef7eb2e8f9f7 1167
<> 144:ef7eb2e8f9f7 1168 Device->PCR4 = tmpr;
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 return HAL_OK;
<> 144:ef7eb2e8f9f7 1171 }
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /**
<> 144:ef7eb2e8f9f7 1174 * @brief Initializes the FMC_PCCARD Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 1175 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 1176 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 1177 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 1178 * @retval HAL status
<> 144:ef7eb2e8f9f7 1179 */
<> 144:ef7eb2e8f9f7 1180 HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 1181 {
<> 144:ef7eb2e8f9f7 1182 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 1183
<> 144:ef7eb2e8f9f7 1184 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1185 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1186 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 1187 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 1188 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 1189 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /* Get PCCARD common space timing register value */
<> 144:ef7eb2e8f9f7 1192 tmpr = Device->PMEM4;
<> 144:ef7eb2e8f9f7 1193
<> 144:ef7eb2e8f9f7 1194 /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */
<> 144:ef7eb2e8f9f7 1195 tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \
<> 144:ef7eb2e8f9f7 1196 FMC_PMEM4_MEMHIZ4));
<> 144:ef7eb2e8f9f7 1197 /* Set PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 1198 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 1199 ((Timing->WaitSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 1200 ((Timing->HoldSetupTime) << 16U) |\
<> 144:ef7eb2e8f9f7 1201 ((Timing->HiZSetupTime) << 24U));
<> 144:ef7eb2e8f9f7 1202
<> 144:ef7eb2e8f9f7 1203 Device->PMEM4 = tmpr;
<> 144:ef7eb2e8f9f7 1204
<> 144:ef7eb2e8f9f7 1205 return HAL_OK;
<> 144:ef7eb2e8f9f7 1206 }
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /**
<> 144:ef7eb2e8f9f7 1209 * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 1210 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 1211 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 1212 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 1213 * @retval HAL status
<> 144:ef7eb2e8f9f7 1214 */
<> 144:ef7eb2e8f9f7 1215 HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 1216 {
<> 144:ef7eb2e8f9f7 1217 uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1220 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1221 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 1222 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 1223 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 1224 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 1225
<> 144:ef7eb2e8f9f7 1226 /* Get PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 1227 tmpr = Device->PATT4;
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */
<> 144:ef7eb2e8f9f7 1230 tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \
<> 144:ef7eb2e8f9f7 1231 FMC_PATT4_ATTHIZ4));
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 /* Set PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 1234 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 1235 ((Timing->WaitSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 1236 ((Timing->HoldSetupTime) << 16U) |\
<> 144:ef7eb2e8f9f7 1237 ((Timing->HiZSetupTime) << 24U));
<> 144:ef7eb2e8f9f7 1238 Device->PATT4 = tmpr;
<> 144:ef7eb2e8f9f7 1239
<> 144:ef7eb2e8f9f7 1240 return HAL_OK;
<> 144:ef7eb2e8f9f7 1241 }
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /**
<> 144:ef7eb2e8f9f7 1244 * @brief Initializes the FMC_PCCARD IO space Timing according to the specified
<> 144:ef7eb2e8f9f7 1245 * parameters in the FMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 1246 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 1247 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 1248 * @retval HAL status
<> 144:ef7eb2e8f9f7 1249 */
<> 144:ef7eb2e8f9f7 1250 HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 1251 {
<> 144:ef7eb2e8f9f7 1252 uint32_t tmpr = 0;
<> 144:ef7eb2e8f9f7 1253
<> 144:ef7eb2e8f9f7 1254 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1255 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1256 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 1257 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 1258 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 1259 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 1260
<> 144:ef7eb2e8f9f7 1261 /* Get FMC_PCCARD device timing parameters */
<> 144:ef7eb2e8f9f7 1262 tmpr = Device->PIO4;
<> 144:ef7eb2e8f9f7 1263
<> 144:ef7eb2e8f9f7 1264 /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */
<> 144:ef7eb2e8f9f7 1265 tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \
<> 144:ef7eb2e8f9f7 1266 FMC_PIO4_IOHIZ4));
<> 144:ef7eb2e8f9f7 1267
<> 144:ef7eb2e8f9f7 1268 /* Set FMC_PCCARD device timing parameters */
<> 144:ef7eb2e8f9f7 1269 tmpr |= (uint32_t)(Timing->SetupTime |\
<> 144:ef7eb2e8f9f7 1270 ((Timing->WaitSetupTime) << 8U) |\
<> 144:ef7eb2e8f9f7 1271 ((Timing->HoldSetupTime) << 16U) |\
<> 144:ef7eb2e8f9f7 1272 ((Timing->HiZSetupTime) << 24U));
<> 144:ef7eb2e8f9f7 1273
<> 144:ef7eb2e8f9f7 1274 Device->PIO4 = tmpr;
<> 144:ef7eb2e8f9f7 1275
<> 144:ef7eb2e8f9f7 1276 return HAL_OK;
<> 144:ef7eb2e8f9f7 1277 }
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /**
<> 144:ef7eb2e8f9f7 1280 * @brief DeInitializes the FMC_PCCARD device
<> 144:ef7eb2e8f9f7 1281 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 1282 * @retval HAL status
<> 144:ef7eb2e8f9f7 1283 */
<> 144:ef7eb2e8f9f7 1284 HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
<> 144:ef7eb2e8f9f7 1285 {
<> 144:ef7eb2e8f9f7 1286 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1287 assert_param(IS_FMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1288
<> 144:ef7eb2e8f9f7 1289 /* Disable the FMC_PCCARD device */
<> 144:ef7eb2e8f9f7 1290 __FMC_PCCARD_DISABLE(Device);
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /* De-initialize the FMC_PCCARD device */
<> 144:ef7eb2e8f9f7 1293 Device->PCR4 = 0x00000018U;
<> 144:ef7eb2e8f9f7 1294 Device->SR4 = 0x00000000U;
<> 144:ef7eb2e8f9f7 1295 Device->PMEM4 = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 1296 Device->PATT4 = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 1297 Device->PIO4 = 0xFCFCFCFCU;
<> 144:ef7eb2e8f9f7 1298
<> 144:ef7eb2e8f9f7 1299 return HAL_OK;
<> 144:ef7eb2e8f9f7 1300 }
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /**
<> 144:ef7eb2e8f9f7 1303 * @}
<> 144:ef7eb2e8f9f7 1304 */
<> 144:ef7eb2e8f9f7 1305 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307
<> 144:ef7eb2e8f9f7 1308 /** @addtogroup FMC_LL_SDRAM
<> 144:ef7eb2e8f9f7 1309 * @brief SDRAM Controller functions
<> 144:ef7eb2e8f9f7 1310 *
<> 144:ef7eb2e8f9f7 1311 @verbatim
<> 144:ef7eb2e8f9f7 1312 ==============================================================================
<> 144:ef7eb2e8f9f7 1313 ##### How to use SDRAM device driver #####
<> 144:ef7eb2e8f9f7 1314 ==============================================================================
<> 144:ef7eb2e8f9f7 1315 [..]
<> 144:ef7eb2e8f9f7 1316 This driver contains a set of APIs to interface with the FMC SDRAM banks in order
<> 144:ef7eb2e8f9f7 1317 to run the SDRAM external devices.
<> 144:ef7eb2e8f9f7 1318
<> 144:ef7eb2e8f9f7 1319 (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit()
<> 144:ef7eb2e8f9f7 1320 (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init()
<> 144:ef7eb2e8f9f7 1321 (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 1322 (+) FMC SDRAM bank enable/disable write operation using the functions
<> 144:ef7eb2e8f9f7 1323 FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable()
<> 144:ef7eb2e8f9f7 1324 (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand()
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 @endverbatim
<> 144:ef7eb2e8f9f7 1327 * @{
<> 144:ef7eb2e8f9f7 1328 */
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1
<> 144:ef7eb2e8f9f7 1331 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 1332 *
<> 144:ef7eb2e8f9f7 1333 @verbatim
<> 144:ef7eb2e8f9f7 1334 ==============================================================================
<> 144:ef7eb2e8f9f7 1335 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 1336 ==============================================================================
<> 144:ef7eb2e8f9f7 1337 [..]
<> 144:ef7eb2e8f9f7 1338 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1339 (+) Initialize and configure the FMC SDRAM interface
<> 144:ef7eb2e8f9f7 1340 (+) De-initialize the FMC SDRAM interface
<> 144:ef7eb2e8f9f7 1341 (+) Configure the FMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 1342
<> 144:ef7eb2e8f9f7 1343 @endverbatim
<> 144:ef7eb2e8f9f7 1344 * @{
<> 144:ef7eb2e8f9f7 1345 */
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /**
<> 144:ef7eb2e8f9f7 1348 * @brief Initializes the FMC_SDRAM device according to the specified
<> 144:ef7eb2e8f9f7 1349 * control parameters in the FMC_SDRAM_InitTypeDef
<> 144:ef7eb2e8f9f7 1350 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1351 * @param Init: Pointer to SDRAM Initialization structure
<> 144:ef7eb2e8f9f7 1352 * @retval HAL status
<> 144:ef7eb2e8f9f7 1353 */
<> 144:ef7eb2e8f9f7 1354 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 1355 {
<> 144:ef7eb2e8f9f7 1356 uint32_t tmpr1 = 0U;
<> 144:ef7eb2e8f9f7 1357 uint32_t tmpr2 = 0U;
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1360 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1361 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
<> 144:ef7eb2e8f9f7 1362 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
<> 144:ef7eb2e8f9f7 1363 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
<> 144:ef7eb2e8f9f7 1364 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 1365 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
<> 144:ef7eb2e8f9f7 1366 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
<> 144:ef7eb2e8f9f7 1367 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
<> 144:ef7eb2e8f9f7 1368 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
<> 144:ef7eb2e8f9f7 1369 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
<> 144:ef7eb2e8f9f7 1370 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
<> 144:ef7eb2e8f9f7 1371
<> 144:ef7eb2e8f9f7 1372 /* Set SDRAM bank configuration parameters */
<> 144:ef7eb2e8f9f7 1373 if (Init->SDBank != FMC_SDRAM_BANK2)
<> 144:ef7eb2e8f9f7 1374 {
<> 144:ef7eb2e8f9f7 1375 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
<> 144:ef7eb2e8f9f7 1376
<> 144:ef7eb2e8f9f7 1377 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
<> 144:ef7eb2e8f9f7 1378 tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
<> 144:ef7eb2e8f9f7 1379 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
<> 144:ef7eb2e8f9f7 1380 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382
<> 144:ef7eb2e8f9f7 1383 tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\
<> 144:ef7eb2e8f9f7 1384 Init->RowBitsNumber |\
<> 144:ef7eb2e8f9f7 1385 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 1386 Init->InternalBankNumber |\
<> 144:ef7eb2e8f9f7 1387 Init->CASLatency |\
<> 144:ef7eb2e8f9f7 1388 Init->WriteProtection |\
<> 144:ef7eb2e8f9f7 1389 Init->SDClockPeriod |\
<> 144:ef7eb2e8f9f7 1390 Init->ReadBurst |\
<> 144:ef7eb2e8f9f7 1391 Init->ReadPipeDelay
<> 144:ef7eb2e8f9f7 1392 );
<> 144:ef7eb2e8f9f7 1393 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
<> 144:ef7eb2e8f9f7 1394 }
<> 144:ef7eb2e8f9f7 1395 else /* FMC_Bank2_SDRAM */
<> 144:ef7eb2e8f9f7 1396 {
<> 144:ef7eb2e8f9f7 1397 tmpr1 = Device->SDCR[FMC_SDRAM_BANK1];
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
<> 144:ef7eb2e8f9f7 1400 tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
<> 144:ef7eb2e8f9f7 1401
<> 144:ef7eb2e8f9f7 1402 tmpr1 |= (uint32_t)(Init->SDClockPeriod |\
<> 144:ef7eb2e8f9f7 1403 Init->ReadBurst |\
<> 144:ef7eb2e8f9f7 1404 Init->ReadPipeDelay);
<> 144:ef7eb2e8f9f7 1405
<> 144:ef7eb2e8f9f7 1406 tmpr2 = Device->SDCR[FMC_SDRAM_BANK2];
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */
<> 144:ef7eb2e8f9f7 1409 tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \
<> 144:ef7eb2e8f9f7 1410 FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \
<> 144:ef7eb2e8f9f7 1411 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE));
<> 144:ef7eb2e8f9f7 1412
<> 144:ef7eb2e8f9f7 1413 tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\
<> 144:ef7eb2e8f9f7 1414 Init->RowBitsNumber |\
<> 144:ef7eb2e8f9f7 1415 Init->MemoryDataWidth |\
<> 144:ef7eb2e8f9f7 1416 Init->InternalBankNumber |\
<> 144:ef7eb2e8f9f7 1417 Init->CASLatency |\
<> 144:ef7eb2e8f9f7 1418 Init->WriteProtection);
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 Device->SDCR[FMC_SDRAM_BANK1] = tmpr1;
<> 144:ef7eb2e8f9f7 1421 Device->SDCR[FMC_SDRAM_BANK2] = tmpr2;
<> 144:ef7eb2e8f9f7 1422 }
<> 144:ef7eb2e8f9f7 1423
<> 144:ef7eb2e8f9f7 1424 return HAL_OK;
<> 144:ef7eb2e8f9f7 1425 }
<> 144:ef7eb2e8f9f7 1426
<> 144:ef7eb2e8f9f7 1427 /**
<> 144:ef7eb2e8f9f7 1428 * @brief Initializes the FMC_SDRAM device timing according to the specified
<> 144:ef7eb2e8f9f7 1429 * parameters in the FMC_SDRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 1430 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1431 * @param Timing: Pointer to SDRAM Timing structure
<> 144:ef7eb2e8f9f7 1432 * @param Bank: SDRAM bank number
<> 144:ef7eb2e8f9f7 1433 * @retval HAL status
<> 144:ef7eb2e8f9f7 1434 */
<> 144:ef7eb2e8f9f7 1435 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 1436 {
<> 144:ef7eb2e8f9f7 1437 uint32_t tmpr1 = 0U;
<> 144:ef7eb2e8f9f7 1438 uint32_t tmpr2 = 0U;
<> 144:ef7eb2e8f9f7 1439
<> 144:ef7eb2e8f9f7 1440 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1441 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1442 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
<> 144:ef7eb2e8f9f7 1443 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
<> 144:ef7eb2e8f9f7 1444 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
<> 144:ef7eb2e8f9f7 1445 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
<> 144:ef7eb2e8f9f7 1446 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
<> 144:ef7eb2e8f9f7 1447 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
<> 144:ef7eb2e8f9f7 1448 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
<> 144:ef7eb2e8f9f7 1449 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 1450
<> 144:ef7eb2e8f9f7 1451 /* Set SDRAM device timing parameters */
<> 144:ef7eb2e8f9f7 1452 if (Bank != FMC_SDRAM_BANK2)
<> 144:ef7eb2e8f9f7 1453 {
<> 144:ef7eb2e8f9f7 1454 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
<> 144:ef7eb2e8f9f7 1457 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
<> 144:ef7eb2e8f9f7 1458 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
<> 144:ef7eb2e8f9f7 1459 FMC_SDTR1_TRCD));
<> 144:ef7eb2e8f9f7 1460
<> 144:ef7eb2e8f9f7 1461 tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\
<> 144:ef7eb2e8f9f7 1462 (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\
<> 144:ef7eb2e8f9f7 1463 (((Timing->SelfRefreshTime)-1U) << 8U) |\
<> 144:ef7eb2e8f9f7 1464 (((Timing->RowCycleDelay)-1U) << 12U) |\
<> 144:ef7eb2e8f9f7 1465 (((Timing->WriteRecoveryTime)-1U) <<16U) |\
<> 144:ef7eb2e8f9f7 1466 (((Timing->RPDelay)-1U) << 20U) |\
<> 144:ef7eb2e8f9f7 1467 (((Timing->RCDDelay)-1U) << 24U));
<> 144:ef7eb2e8f9f7 1468 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
<> 144:ef7eb2e8f9f7 1469 }
<> 144:ef7eb2e8f9f7 1470 else /* FMC_Bank2_SDRAM */
<> 144:ef7eb2e8f9f7 1471 {
<> 144:ef7eb2e8f9f7 1472 tmpr1 = Device->SDTR[FMC_SDRAM_BANK1];
<> 144:ef7eb2e8f9f7 1473
<> 144:ef7eb2e8f9f7 1474 /* Clear TRC and TRP bits */
<> 144:ef7eb2e8f9f7 1475 tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP));
<> 144:ef7eb2e8f9f7 1476
<> 144:ef7eb2e8f9f7 1477 tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\
<> 144:ef7eb2e8f9f7 1478 (((Timing->RPDelay)-1) << 20));
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 tmpr2 = Device->SDTR[FMC_SDRAM_BANK2];
<> 144:ef7eb2e8f9f7 1481
<> 144:ef7eb2e8f9f7 1482 /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */
<> 144:ef7eb2e8f9f7 1483 tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \
<> 144:ef7eb2e8f9f7 1484 FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
<> 144:ef7eb2e8f9f7 1485 FMC_SDTR1_TRCD));
<> 144:ef7eb2e8f9f7 1486
<> 144:ef7eb2e8f9f7 1487 tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1) |\
<> 144:ef7eb2e8f9f7 1488 (((Timing->ExitSelfRefreshDelay)-1) << 4) |\
<> 144:ef7eb2e8f9f7 1489 (((Timing->SelfRefreshTime)-1) << 8) |\
<> 144:ef7eb2e8f9f7 1490 (((Timing->WriteRecoveryTime)-1) <<16) |\
<> 144:ef7eb2e8f9f7 1491 (((Timing->RCDDelay)-1) << 24)));
<> 144:ef7eb2e8f9f7 1492
<> 144:ef7eb2e8f9f7 1493 Device->SDTR[FMC_SDRAM_BANK1] = tmpr1;
<> 144:ef7eb2e8f9f7 1494 Device->SDTR[FMC_SDRAM_BANK2] = tmpr2;
<> 144:ef7eb2e8f9f7 1495 }
<> 144:ef7eb2e8f9f7 1496 return HAL_OK;
<> 144:ef7eb2e8f9f7 1497 }
<> 144:ef7eb2e8f9f7 1498
<> 144:ef7eb2e8f9f7 1499 /**
<> 144:ef7eb2e8f9f7 1500 * @brief DeInitializes the FMC_SDRAM peripheral
<> 144:ef7eb2e8f9f7 1501 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1502 * @retval HAL status
<> 144:ef7eb2e8f9f7 1503 */
<> 144:ef7eb2e8f9f7 1504 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 1505 {
<> 144:ef7eb2e8f9f7 1506 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1507 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1508 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 1509
<> 144:ef7eb2e8f9f7 1510 /* De-initialize the SDRAM device */
<> 144:ef7eb2e8f9f7 1511 Device->SDCR[Bank] = 0x000002D0U;
<> 144:ef7eb2e8f9f7 1512 Device->SDTR[Bank] = 0x0FFFFFFFU;
<> 144:ef7eb2e8f9f7 1513 Device->SDCMR = 0x00000000U;
<> 144:ef7eb2e8f9f7 1514 Device->SDRTR = 0x00000000U;
<> 144:ef7eb2e8f9f7 1515 Device->SDSR = 0x00000000U;
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 return HAL_OK;
<> 144:ef7eb2e8f9f7 1518 }
<> 144:ef7eb2e8f9f7 1519
<> 144:ef7eb2e8f9f7 1520 /**
<> 144:ef7eb2e8f9f7 1521 * @}
<> 144:ef7eb2e8f9f7 1522 */
<> 144:ef7eb2e8f9f7 1523
<> 144:ef7eb2e8f9f7 1524 /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2
<> 144:ef7eb2e8f9f7 1525 * @brief management functions
<> 144:ef7eb2e8f9f7 1526 *
<> 144:ef7eb2e8f9f7 1527 @verbatim
<> 144:ef7eb2e8f9f7 1528 ==============================================================================
<> 144:ef7eb2e8f9f7 1529 ##### FMC_SDRAM Control functions #####
<> 144:ef7eb2e8f9f7 1530 ==============================================================================
<> 144:ef7eb2e8f9f7 1531 [..]
<> 144:ef7eb2e8f9f7 1532 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 1533 the FMC SDRAM interface.
<> 144:ef7eb2e8f9f7 1534
<> 144:ef7eb2e8f9f7 1535 @endverbatim
<> 144:ef7eb2e8f9f7 1536 * @{
<> 144:ef7eb2e8f9f7 1537 */
<> 144:ef7eb2e8f9f7 1538 /**
<> 144:ef7eb2e8f9f7 1539 * @brief Enables dynamically FMC_SDRAM write protection.
<> 144:ef7eb2e8f9f7 1540 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1541 * @param Bank: SDRAM bank number
<> 144:ef7eb2e8f9f7 1542 * @retval HAL status
<> 144:ef7eb2e8f9f7 1543 */
<> 144:ef7eb2e8f9f7 1544 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 1545 {
<> 144:ef7eb2e8f9f7 1546 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1547 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1548 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /* Enable write protection */
<> 144:ef7eb2e8f9f7 1551 Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE;
<> 144:ef7eb2e8f9f7 1552
<> 144:ef7eb2e8f9f7 1553 return HAL_OK;
<> 144:ef7eb2e8f9f7 1554 }
<> 144:ef7eb2e8f9f7 1555
<> 144:ef7eb2e8f9f7 1556 /**
<> 144:ef7eb2e8f9f7 1557 * @brief Disables dynamically FMC_SDRAM write protection.
<> 144:ef7eb2e8f9f7 1558 * @param hsdram: FMC_SDRAM handle
<> 144:ef7eb2e8f9f7 1559 * @retval HAL status
<> 144:ef7eb2e8f9f7 1560 */
<> 144:ef7eb2e8f9f7 1561 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 1562 {
<> 144:ef7eb2e8f9f7 1563 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1564 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1565 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 1566
<> 144:ef7eb2e8f9f7 1567 /* Disable write protection */
<> 144:ef7eb2e8f9f7 1568 Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE;
<> 144:ef7eb2e8f9f7 1569
<> 144:ef7eb2e8f9f7 1570 return HAL_OK;
<> 144:ef7eb2e8f9f7 1571 }
<> 144:ef7eb2e8f9f7 1572
<> 144:ef7eb2e8f9f7 1573 /**
<> 144:ef7eb2e8f9f7 1574 * @brief Send Command to the FMC SDRAM bank
<> 144:ef7eb2e8f9f7 1575 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1576 * @param Command: Pointer to SDRAM command structure
<> 144:ef7eb2e8f9f7 1577 * @param Timing: Pointer to SDRAM Timing structure
<> 144:ef7eb2e8f9f7 1578 * @param Timeout: Timeout wait value
<> 144:ef7eb2e8f9f7 1579 * @retval HAL state
<> 144:ef7eb2e8f9f7 1580 */
<> 144:ef7eb2e8f9f7 1581 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 1582 {
<> 144:ef7eb2e8f9f7 1583 __IO uint32_t tmpr = 0U;
<> 144:ef7eb2e8f9f7 1584 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 1585
<> 144:ef7eb2e8f9f7 1586 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1587 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1588 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
<> 144:ef7eb2e8f9f7 1589 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
<> 144:ef7eb2e8f9f7 1590 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
<> 144:ef7eb2e8f9f7 1591 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
<> 144:ef7eb2e8f9f7 1592
<> 144:ef7eb2e8f9f7 1593 /* Set command register */
<> 144:ef7eb2e8f9f7 1594 tmpr = (uint32_t)((Command->CommandMode) |\
<> 144:ef7eb2e8f9f7 1595 (Command->CommandTarget) |\
<> 144:ef7eb2e8f9f7 1596 (((Command->AutoRefreshNumber)-1U) << 5U) |\
<> 144:ef7eb2e8f9f7 1597 ((Command->ModeRegisterDefinition) << 9U)
<> 144:ef7eb2e8f9f7 1598 );
<> 144:ef7eb2e8f9f7 1599
<> 144:ef7eb2e8f9f7 1600 Device->SDCMR = tmpr;
<> 144:ef7eb2e8f9f7 1601
<> 144:ef7eb2e8f9f7 1602 /* Get tick */
<> 144:ef7eb2e8f9f7 1603 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 1604
<> 144:ef7eb2e8f9f7 1605 /* Wait until command is send */
<> 144:ef7eb2e8f9f7 1606 while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
<> 144:ef7eb2e8f9f7 1607 {
<> 144:ef7eb2e8f9f7 1608 /* Check for the Timeout */
<> 144:ef7eb2e8f9f7 1609 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 1610 {
<> 144:ef7eb2e8f9f7 1611 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 1612 {
<> 144:ef7eb2e8f9f7 1613 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 1614 }
<> 144:ef7eb2e8f9f7 1615 }
<> 144:ef7eb2e8f9f7 1616 }
<> 144:ef7eb2e8f9f7 1617
<> 144:ef7eb2e8f9f7 1618 return HAL_OK;
<> 144:ef7eb2e8f9f7 1619 }
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /**
<> 144:ef7eb2e8f9f7 1622 * @brief Program the SDRAM Memory Refresh rate.
<> 144:ef7eb2e8f9f7 1623 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1624 * @param RefreshRate: The SDRAM refresh rate value.
<> 144:ef7eb2e8f9f7 1625 * @retval HAL state
<> 144:ef7eb2e8f9f7 1626 */
<> 144:ef7eb2e8f9f7 1627 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
<> 144:ef7eb2e8f9f7 1628 {
<> 144:ef7eb2e8f9f7 1629 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1630 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1631 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
<> 144:ef7eb2e8f9f7 1632
<> 144:ef7eb2e8f9f7 1633 /* Set the refresh rate in command register */
<> 144:ef7eb2e8f9f7 1634 Device->SDRTR |= (RefreshRate<<1U);
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 return HAL_OK;
<> 144:ef7eb2e8f9f7 1637 }
<> 144:ef7eb2e8f9f7 1638
<> 144:ef7eb2e8f9f7 1639 /**
<> 144:ef7eb2e8f9f7 1640 * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
<> 144:ef7eb2e8f9f7 1641 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1642 * @param AutoRefreshNumber: Specifies the auto Refresh number.
<> 144:ef7eb2e8f9f7 1643 * @retval None
<> 144:ef7eb2e8f9f7 1644 */
<> 144:ef7eb2e8f9f7 1645 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
<> 144:ef7eb2e8f9f7 1646 {
<> 144:ef7eb2e8f9f7 1647 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1648 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1649 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
<> 144:ef7eb2e8f9f7 1650
<> 144:ef7eb2e8f9f7 1651 /* Set the Auto-refresh number in command register */
<> 144:ef7eb2e8f9f7 1652 Device->SDCMR |= (AutoRefreshNumber << 5U);
<> 144:ef7eb2e8f9f7 1653
<> 144:ef7eb2e8f9f7 1654 return HAL_OK;
<> 144:ef7eb2e8f9f7 1655 }
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /**
<> 144:ef7eb2e8f9f7 1658 * @brief Returns the indicated FMC SDRAM bank mode status.
<> 144:ef7eb2e8f9f7 1659 * @param Device: Pointer to SDRAM device instance
<> 144:ef7eb2e8f9f7 1660 * @param Bank: Defines the FMC SDRAM bank. This parameter can be
<> 144:ef7eb2e8f9f7 1661 * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
<> 144:ef7eb2e8f9f7 1662 * @retval The FMC SDRAM bank mode status, could be on of the following values:
<> 144:ef7eb2e8f9f7 1663 * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
<> 144:ef7eb2e8f9f7 1664 * FMC_SDRAM_POWER_DOWN_MODE.
<> 144:ef7eb2e8f9f7 1665 */
<> 144:ef7eb2e8f9f7 1666 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 1667 {
<> 144:ef7eb2e8f9f7 1668 uint32_t tmpreg = 0U;
<> 144:ef7eb2e8f9f7 1669
<> 144:ef7eb2e8f9f7 1670 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1671 assert_param(IS_FMC_SDRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 1672 assert_param(IS_FMC_SDRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 /* Get the corresponding bank mode */
<> 144:ef7eb2e8f9f7 1675 if(Bank == FMC_SDRAM_BANK1)
<> 144:ef7eb2e8f9f7 1676 {
<> 144:ef7eb2e8f9f7 1677 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
<> 144:ef7eb2e8f9f7 1678 }
<> 144:ef7eb2e8f9f7 1679 else
<> 144:ef7eb2e8f9f7 1680 {
<> 144:ef7eb2e8f9f7 1681 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
<> 144:ef7eb2e8f9f7 1682 }
<> 144:ef7eb2e8f9f7 1683
<> 144:ef7eb2e8f9f7 1684 /* Return the mode status */
<> 144:ef7eb2e8f9f7 1685 return tmpreg;
<> 144:ef7eb2e8f9f7 1686 }
<> 144:ef7eb2e8f9f7 1687
<> 144:ef7eb2e8f9f7 1688 /**
<> 144:ef7eb2e8f9f7 1689 * @}
<> 144:ef7eb2e8f9f7 1690 */
<> 144:ef7eb2e8f9f7 1691
<> 144:ef7eb2e8f9f7 1692 /**
<> 144:ef7eb2e8f9f7 1693 * @}
<> 144:ef7eb2e8f9f7 1694 */
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 /**
<> 144:ef7eb2e8f9f7 1697 * @}
<> 144:ef7eb2e8f9f7 1698 */
<> 144:ef7eb2e8f9f7 1699 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
<> 144:ef7eb2e8f9f7 1700 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1701
<> 144:ef7eb2e8f9f7 1702 /**
<> 144:ef7eb2e8f9f7 1703 * @}
<> 144:ef7eb2e8f9f7 1704 */
<> 144:ef7eb2e8f9f7 1705
<> 144:ef7eb2e8f9f7 1706 /**
<> 144:ef7eb2e8f9f7 1707 * @}
<> 144:ef7eb2e8f9f7 1708 */
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/