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targets/hal/TARGET_NXP/TARGET_LPC176X/serial_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 // math.h required for floating point operations for baud rate calculation
bogdanm 0:9b334a45a8ff 17 #include "mbed_assert.h"
bogdanm 0:9b334a45a8ff 18 #include <math.h>
bogdanm 0:9b334a45a8ff 19 #include <string.h>
bogdanm 0:9b334a45a8ff 20 #include <stdlib.h>
bogdanm 0:9b334a45a8ff 21
bogdanm 0:9b334a45a8ff 22 #include "serial_api.h"
bogdanm 0:9b334a45a8ff 23 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 24 #include "pinmap.h"
bogdanm 0:9b334a45a8ff 25 #include "gpio_api.h"
bogdanm 0:9b334a45a8ff 26
bogdanm 0:9b334a45a8ff 27 /******************************************************************************
bogdanm 0:9b334a45a8ff 28 * INITIALIZATION
bogdanm 0:9b334a45a8ff 29 ******************************************************************************/
bogdanm 0:9b334a45a8ff 30 #define UART_NUM 4
bogdanm 0:9b334a45a8ff 31
bogdanm 0:9b334a45a8ff 32 static const PinMap PinMap_UART_TX[] = {
bogdanm 0:9b334a45a8ff 33 {P0_0, UART_3, 2},
bogdanm 0:9b334a45a8ff 34 {P0_2, UART_0, 1},
bogdanm 0:9b334a45a8ff 35 {P0_10, UART_2, 1},
bogdanm 0:9b334a45a8ff 36 {P0_15, UART_1, 1},
bogdanm 0:9b334a45a8ff 37 {P0_25, UART_3, 3},
bogdanm 0:9b334a45a8ff 38 {P2_0 , UART_1, 2},
bogdanm 0:9b334a45a8ff 39 {P2_8 , UART_2, 2},
bogdanm 0:9b334a45a8ff 40 {P4_28, UART_3, 3},
bogdanm 0:9b334a45a8ff 41 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 42 };
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 static const PinMap PinMap_UART_RX[] = {
bogdanm 0:9b334a45a8ff 45 {P0_1 , UART_3, 2},
bogdanm 0:9b334a45a8ff 46 {P0_3 , UART_0, 1},
bogdanm 0:9b334a45a8ff 47 {P0_11, UART_2, 1},
bogdanm 0:9b334a45a8ff 48 {P0_16, UART_1, 1},
bogdanm 0:9b334a45a8ff 49 {P0_26, UART_3, 3},
bogdanm 0:9b334a45a8ff 50 {P2_1 , UART_1, 2},
bogdanm 0:9b334a45a8ff 51 {P2_9 , UART_2, 2},
bogdanm 0:9b334a45a8ff 52 {P4_29, UART_3, 3},
bogdanm 0:9b334a45a8ff 53 {NC , NC , 0}
bogdanm 0:9b334a45a8ff 54 };
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 static const PinMap PinMap_UART_RTS[] = {
bogdanm 0:9b334a45a8ff 57 {P0_22, UART_1, 1},
bogdanm 0:9b334a45a8ff 58 {P2_7, UART_1, 2},
bogdanm 0:9b334a45a8ff 59 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 60 };
bogdanm 0:9b334a45a8ff 61
bogdanm 0:9b334a45a8ff 62 static const PinMap PinMap_UART_CTS[] = {
bogdanm 0:9b334a45a8ff 63 {P0_17, UART_1, 1},
bogdanm 0:9b334a45a8ff 64 {P2_2, UART_1, 2},
bogdanm 0:9b334a45a8ff 65 {NC, NC, 0}
bogdanm 0:9b334a45a8ff 66 };
bogdanm 0:9b334a45a8ff 67
bogdanm 0:9b334a45a8ff 68 #define UART_MCR_RTSEN_MASK (1 << 6)
bogdanm 0:9b334a45a8ff 69 #define UART_MCR_CTSEN_MASK (1 << 7)
bogdanm 0:9b334a45a8ff 70 #define UART_MCR_FLOWCTRL_MASK (UART_MCR_RTSEN_MASK | UART_MCR_CTSEN_MASK)
bogdanm 0:9b334a45a8ff 71
bogdanm 0:9b334a45a8ff 72 static uart_irq_handler irq_handler;
bogdanm 0:9b334a45a8ff 73
bogdanm 0:9b334a45a8ff 74 int stdio_uart_inited = 0;
bogdanm 0:9b334a45a8ff 75 serial_t stdio_uart;
bogdanm 0:9b334a45a8ff 76
bogdanm 0:9b334a45a8ff 77 struct serial_global_data_s {
bogdanm 0:9b334a45a8ff 78 uint32_t serial_irq_id;
bogdanm 0:9b334a45a8ff 79 gpio_t sw_rts, sw_cts;
bogdanm 0:9b334a45a8ff 80 uint8_t count, rx_irq_set_flow, rx_irq_set_api;
bogdanm 0:9b334a45a8ff 81 };
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 static struct serial_global_data_s uart_data[UART_NUM];
bogdanm 0:9b334a45a8ff 84
bogdanm 0:9b334a45a8ff 85 void serial_init(serial_t *obj, PinName tx, PinName rx) {
bogdanm 0:9b334a45a8ff 86 int is_stdio_uart = 0;
bogdanm 0:9b334a45a8ff 87
bogdanm 0:9b334a45a8ff 88 // determine the UART to use
bogdanm 0:9b334a45a8ff 89 UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
bogdanm 0:9b334a45a8ff 90 UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
bogdanm 0:9b334a45a8ff 91 UARTName uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
bogdanm 0:9b334a45a8ff 92 MBED_ASSERT((int)uart != NC);
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 obj->uart = (LPC_UART_TypeDef *)uart;
bogdanm 0:9b334a45a8ff 95 // enable power
bogdanm 0:9b334a45a8ff 96 switch (uart) {
bogdanm 0:9b334a45a8ff 97 case UART_0: LPC_SC->PCONP |= 1 << 3; break;
bogdanm 0:9b334a45a8ff 98 case UART_1: LPC_SC->PCONP |= 1 << 4; break;
bogdanm 0:9b334a45a8ff 99 case UART_2: LPC_SC->PCONP |= 1 << 24; break;
bogdanm 0:9b334a45a8ff 100 case UART_3: LPC_SC->PCONP |= 1 << 25; break;
bogdanm 0:9b334a45a8ff 101 }
bogdanm 0:9b334a45a8ff 102
bogdanm 0:9b334a45a8ff 103 // enable fifos and default rx trigger level
bogdanm 0:9b334a45a8ff 104 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
bogdanm 0:9b334a45a8ff 105 | 0 << 1 // Rx Fifo Reset
bogdanm 0:9b334a45a8ff 106 | 0 << 2 // Tx Fifo Reset
bogdanm 0:9b334a45a8ff 107 | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
bogdanm 0:9b334a45a8ff 108
bogdanm 0:9b334a45a8ff 109 // disable irqs
bogdanm 0:9b334a45a8ff 110 obj->uart->IER = 0 << 0 // Rx Data available irq enable
bogdanm 0:9b334a45a8ff 111 | 0 << 1 // Tx Fifo empty irq enable
bogdanm 0:9b334a45a8ff 112 | 0 << 2; // Rx Line Status irq enable
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 // set default baud rate and format
bogdanm 0:9b334a45a8ff 115 serial_baud (obj, 9600);
bogdanm 0:9b334a45a8ff 116 serial_format(obj, 8, ParityNone, 1);
bogdanm 0:9b334a45a8ff 117
bogdanm 0:9b334a45a8ff 118 // pinout the chosen uart
bogdanm 0:9b334a45a8ff 119 pinmap_pinout(tx, PinMap_UART_TX);
bogdanm 0:9b334a45a8ff 120 pinmap_pinout(rx, PinMap_UART_RX);
bogdanm 0:9b334a45a8ff 121
bogdanm 0:9b334a45a8ff 122 // set rx/tx pins in PullUp mode
bogdanm 0:9b334a45a8ff 123 if (tx != NC) {
bogdanm 0:9b334a45a8ff 124 pin_mode(tx, PullUp);
bogdanm 0:9b334a45a8ff 125 }
bogdanm 0:9b334a45a8ff 126 if (rx != NC) {
bogdanm 0:9b334a45a8ff 127 pin_mode(rx, PullUp);
bogdanm 0:9b334a45a8ff 128 }
bogdanm 0:9b334a45a8ff 129
bogdanm 0:9b334a45a8ff 130 switch (uart) {
bogdanm 0:9b334a45a8ff 131 case UART_0: obj->index = 0; break;
bogdanm 0:9b334a45a8ff 132 case UART_1: obj->index = 1; break;
bogdanm 0:9b334a45a8ff 133 case UART_2: obj->index = 2; break;
bogdanm 0:9b334a45a8ff 134 case UART_3: obj->index = 3; break;
bogdanm 0:9b334a45a8ff 135 }
bogdanm 0:9b334a45a8ff 136 uart_data[obj->index].sw_rts.pin = NC;
bogdanm 0:9b334a45a8ff 137 uart_data[obj->index].sw_cts.pin = NC;
bogdanm 0:9b334a45a8ff 138 serial_set_flow_control(obj, FlowControlNone, NC, NC);
bogdanm 0:9b334a45a8ff 139
bogdanm 0:9b334a45a8ff 140 is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 if (is_stdio_uart) {
bogdanm 0:9b334a45a8ff 143 stdio_uart_inited = 1;
bogdanm 0:9b334a45a8ff 144 memcpy(&stdio_uart, obj, sizeof(serial_t));
bogdanm 0:9b334a45a8ff 145 }
bogdanm 0:9b334a45a8ff 146 }
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 void serial_free(serial_t *obj) {
bogdanm 0:9b334a45a8ff 149 uart_data[obj->index].serial_irq_id = 0;
bogdanm 0:9b334a45a8ff 150 }
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 // serial_baud
bogdanm 0:9b334a45a8ff 153 // set the baud rate, taking in to account the current SystemFrequency
bogdanm 0:9b334a45a8ff 154 void serial_baud(serial_t *obj, int baudrate) {
bogdanm 0:9b334a45a8ff 155 MBED_ASSERT((int)obj->uart <= UART_3);
bogdanm 0:9b334a45a8ff 156 // The LPC2300 and LPC1700 have a divider and a fractional divider to control the
bogdanm 0:9b334a45a8ff 157 // baud rate. The formula is:
bogdanm 0:9b334a45a8ff 158 //
bogdanm 0:9b334a45a8ff 159 // Baudrate = (1 / PCLK) * 16 * DL * (1 + DivAddVal / MulVal)
bogdanm 0:9b334a45a8ff 160 // where:
bogdanm 0:9b334a45a8ff 161 // 1 < MulVal <= 15
bogdanm 0:9b334a45a8ff 162 // 0 <= DivAddVal < 14
bogdanm 0:9b334a45a8ff 163 // DivAddVal < MulVal
bogdanm 0:9b334a45a8ff 164 //
bogdanm 0:9b334a45a8ff 165 // set pclk to /1
bogdanm 0:9b334a45a8ff 166 switch ((int)obj->uart) {
bogdanm 0:9b334a45a8ff 167 case UART_0: LPC_SC->PCLKSEL0 &= ~(0x3 << 6); LPC_SC->PCLKSEL0 |= (0x1 << 6); break;
bogdanm 0:9b334a45a8ff 168 case UART_1: LPC_SC->PCLKSEL0 &= ~(0x3 << 8); LPC_SC->PCLKSEL0 |= (0x1 << 8); break;
bogdanm 0:9b334a45a8ff 169 case UART_2: LPC_SC->PCLKSEL1 &= ~(0x3 << 16); LPC_SC->PCLKSEL1 |= (0x1 << 16); break;
bogdanm 0:9b334a45a8ff 170 case UART_3: LPC_SC->PCLKSEL1 &= ~(0x3 << 18); LPC_SC->PCLKSEL1 |= (0x1 << 18); break;
bogdanm 0:9b334a45a8ff 171 default: break;
bogdanm 0:9b334a45a8ff 172 }
bogdanm 0:9b334a45a8ff 173
bogdanm 0:9b334a45a8ff 174 uint32_t PCLK = SystemCoreClock;
bogdanm 0:9b334a45a8ff 175
bogdanm 0:9b334a45a8ff 176 // First we check to see if the basic divide with no DivAddVal/MulVal
bogdanm 0:9b334a45a8ff 177 // ratio gives us an integer result. If it does, we set DivAddVal = 0,
bogdanm 0:9b334a45a8ff 178 // MulVal = 1. Otherwise, we search the valid ratio value range to find
bogdanm 0:9b334a45a8ff 179 // the closest match. This could be more elegant, using search methods
bogdanm 0:9b334a45a8ff 180 // and/or lookup tables, but the brute force method is not that much
bogdanm 0:9b334a45a8ff 181 // slower, and is more maintainable.
bogdanm 0:9b334a45a8ff 182 uint16_t DL = PCLK / (16 * baudrate);
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 uint8_t DivAddVal = 0;
bogdanm 0:9b334a45a8ff 185 uint8_t MulVal = 1;
bogdanm 0:9b334a45a8ff 186 int hit = 0;
bogdanm 0:9b334a45a8ff 187 uint16_t dlv;
bogdanm 0:9b334a45a8ff 188 uint8_t mv, dav;
bogdanm 0:9b334a45a8ff 189 if ((PCLK % (16 * baudrate)) != 0) { // Checking for zero remainder
bogdanm 0:9b334a45a8ff 190 int err_best = baudrate, b;
bogdanm 0:9b334a45a8ff 191 for (mv = 1; mv < 16 && !hit; mv++)
bogdanm 0:9b334a45a8ff 192 {
bogdanm 0:9b334a45a8ff 193 for (dav = 0; dav < mv; dav++)
bogdanm 0:9b334a45a8ff 194 {
bogdanm 0:9b334a45a8ff 195 // baudrate = PCLK / (16 * dlv * (1 + (DivAdd / Mul))
bogdanm 0:9b334a45a8ff 196 // solving for dlv, we get dlv = mul * PCLK / (16 * baudrate * (divadd + mul))
bogdanm 0:9b334a45a8ff 197 // mul has 4 bits, PCLK has 27 so we have 1 bit headroom which can be used for rounding
bogdanm 0:9b334a45a8ff 198 // for many values of mul and PCLK we have 2 or more bits of headroom which can be used to improve precision
bogdanm 0:9b334a45a8ff 199 // note: X / 32 doesn't round correctly. Instead, we use ((X / 16) + 1) / 2 for correct rounding
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 if ((mv * PCLK * 2) & 0x80000000) // 1 bit headroom
bogdanm 0:9b334a45a8ff 202 dlv = ((((2 * mv * PCLK) / (baudrate * (dav + mv))) / 16) + 1) / 2;
bogdanm 0:9b334a45a8ff 203 else // 2 bits headroom, use more precision
bogdanm 0:9b334a45a8ff 204 dlv = ((((4 * mv * PCLK) / (baudrate * (dav + mv))) / 32) + 1) / 2;
bogdanm 0:9b334a45a8ff 205
bogdanm 0:9b334a45a8ff 206 // datasheet says if DLL==DLM==0, then 1 is used instead since divide by zero is ungood
bogdanm 0:9b334a45a8ff 207 if (dlv == 0)
bogdanm 0:9b334a45a8ff 208 dlv = 1;
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 // datasheet says if dav > 0 then DL must be >= 2
bogdanm 0:9b334a45a8ff 211 if ((dav > 0) && (dlv < 2))
bogdanm 0:9b334a45a8ff 212 dlv = 2;
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 // integer rearrangement of the baudrate equation (with rounding)
bogdanm 0:9b334a45a8ff 215 b = ((PCLK * mv / (dlv * (dav + mv) * 8)) + 1) / 2;
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 // check to see how we went
bogdanm 0:9b334a45a8ff 218 b = abs(b - baudrate);
bogdanm 0:9b334a45a8ff 219 if (b < err_best)
bogdanm 0:9b334a45a8ff 220 {
bogdanm 0:9b334a45a8ff 221 err_best = b;
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 DL = dlv;
bogdanm 0:9b334a45a8ff 224 MulVal = mv;
bogdanm 0:9b334a45a8ff 225 DivAddVal = dav;
bogdanm 0:9b334a45a8ff 226
bogdanm 0:9b334a45a8ff 227 if (b == baudrate)
bogdanm 0:9b334a45a8ff 228 {
bogdanm 0:9b334a45a8ff 229 hit = 1;
bogdanm 0:9b334a45a8ff 230 break;
bogdanm 0:9b334a45a8ff 231 }
bogdanm 0:9b334a45a8ff 232 }
bogdanm 0:9b334a45a8ff 233 }
bogdanm 0:9b334a45a8ff 234 }
bogdanm 0:9b334a45a8ff 235 }
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 // set LCR[DLAB] to enable writing to divider registers
bogdanm 0:9b334a45a8ff 238 obj->uart->LCR |= (1 << 7);
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 // set divider values
bogdanm 0:9b334a45a8ff 241 obj->uart->DLM = (DL >> 8) & 0xFF;
bogdanm 0:9b334a45a8ff 242 obj->uart->DLL = (DL >> 0) & 0xFF;
bogdanm 0:9b334a45a8ff 243 obj->uart->FDR = (uint32_t) DivAddVal << 0
bogdanm 0:9b334a45a8ff 244 | (uint32_t) MulVal << 4;
bogdanm 0:9b334a45a8ff 245
bogdanm 0:9b334a45a8ff 246 // clear LCR[DLAB]
bogdanm 0:9b334a45a8ff 247 obj->uart->LCR &= ~(1 << 7);
bogdanm 0:9b334a45a8ff 248 }
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
bogdanm 0:9b334a45a8ff 251 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
bogdanm 0:9b334a45a8ff 252 MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
bogdanm 0:9b334a45a8ff 253 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
bogdanm 0:9b334a45a8ff 254 (parity == ParityForced1) || (parity == ParityForced0));
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256 stop_bits -= 1;
bogdanm 0:9b334a45a8ff 257 data_bits -= 5;
bogdanm 0:9b334a45a8ff 258
bogdanm 0:9b334a45a8ff 259 int parity_enable, parity_select;
bogdanm 0:9b334a45a8ff 260 switch (parity) {
bogdanm 0:9b334a45a8ff 261 case ParityNone: parity_enable = 0; parity_select = 0; break;
bogdanm 0:9b334a45a8ff 262 case ParityOdd : parity_enable = 1; parity_select = 0; break;
bogdanm 0:9b334a45a8ff 263 case ParityEven: parity_enable = 1; parity_select = 1; break;
bogdanm 0:9b334a45a8ff 264 case ParityForced1: parity_enable = 1; parity_select = 2; break;
bogdanm 0:9b334a45a8ff 265 case ParityForced0: parity_enable = 1; parity_select = 3; break;
bogdanm 0:9b334a45a8ff 266 default:
bogdanm 0:9b334a45a8ff 267 parity_enable = 0, parity_select = 0;
bogdanm 0:9b334a45a8ff 268 break;
bogdanm 0:9b334a45a8ff 269 }
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 obj->uart->LCR = data_bits << 0
bogdanm 0:9b334a45a8ff 272 | stop_bits << 2
bogdanm 0:9b334a45a8ff 273 | parity_enable << 3
bogdanm 0:9b334a45a8ff 274 | parity_select << 4;
bogdanm 0:9b334a45a8ff 275 }
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 /******************************************************************************
bogdanm 0:9b334a45a8ff 278 * INTERRUPTS HANDLING
bogdanm 0:9b334a45a8ff 279 ******************************************************************************/
bogdanm 0:9b334a45a8ff 280 static inline void uart_irq(uint32_t iir, uint32_t index, LPC_UART_TypeDef *puart) {
bogdanm 0:9b334a45a8ff 281 // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling
bogdanm 0:9b334a45a8ff 282 SerialIrq irq_type;
bogdanm 0:9b334a45a8ff 283 switch (iir) {
bogdanm 0:9b334a45a8ff 284 case 1: irq_type = TxIrq; break;
bogdanm 0:9b334a45a8ff 285 case 2: irq_type = RxIrq; break;
bogdanm 0:9b334a45a8ff 286 default: return;
bogdanm 0:9b334a45a8ff 287 }
bogdanm 0:9b334a45a8ff 288 if ((RxIrq == irq_type) && (NC != uart_data[index].sw_rts.pin)) {
bogdanm 0:9b334a45a8ff 289 gpio_write(&uart_data[index].sw_rts, 1);
bogdanm 0:9b334a45a8ff 290 // Disable interrupt if it wasn't enabled by other part of the application
bogdanm 0:9b334a45a8ff 291 if (!uart_data[index].rx_irq_set_api)
bogdanm 0:9b334a45a8ff 292 puart->IER &= ~(1 << RxIrq);
bogdanm 0:9b334a45a8ff 293 }
bogdanm 0:9b334a45a8ff 294 if (uart_data[index].serial_irq_id != 0)
bogdanm 0:9b334a45a8ff 295 if ((irq_type != RxIrq) || (uart_data[index].rx_irq_set_api))
bogdanm 0:9b334a45a8ff 296 irq_handler(uart_data[index].serial_irq_id, irq_type);
bogdanm 0:9b334a45a8ff 297 }
bogdanm 0:9b334a45a8ff 298
bogdanm 0:9b334a45a8ff 299 void uart0_irq() {uart_irq((LPC_UART0->IIR >> 1) & 0x7, 0, (LPC_UART_TypeDef*)LPC_UART0);}
bogdanm 0:9b334a45a8ff 300 void uart1_irq() {uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LPC_UART1);}
bogdanm 0:9b334a45a8ff 301 void uart2_irq() {uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);}
bogdanm 0:9b334a45a8ff 302 void uart3_irq() {uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);}
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
bogdanm 0:9b334a45a8ff 305 irq_handler = handler;
bogdanm 0:9b334a45a8ff 306 uart_data[obj->index].serial_irq_id = id;
bogdanm 0:9b334a45a8ff 307 }
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
bogdanm 0:9b334a45a8ff 310 IRQn_Type irq_n = (IRQn_Type)0;
bogdanm 0:9b334a45a8ff 311 uint32_t vector = 0;
bogdanm 0:9b334a45a8ff 312 switch ((int)obj->uart) {
bogdanm 0:9b334a45a8ff 313 case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
bogdanm 0:9b334a45a8ff 314 case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
bogdanm 0:9b334a45a8ff 315 case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
bogdanm 0:9b334a45a8ff 316 case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
bogdanm 0:9b334a45a8ff 317 }
bogdanm 0:9b334a45a8ff 318
bogdanm 0:9b334a45a8ff 319 if (enable) {
bogdanm 0:9b334a45a8ff 320 obj->uart->IER |= 1 << irq;
bogdanm 0:9b334a45a8ff 321 NVIC_SetVector(irq_n, vector);
bogdanm 0:9b334a45a8ff 322 NVIC_EnableIRQ(irq_n);
bogdanm 0:9b334a45a8ff 323 } else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
bogdanm 0:9b334a45a8ff 324 int all_disabled = 0;
bogdanm 0:9b334a45a8ff 325 SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
bogdanm 0:9b334a45a8ff 326 obj->uart->IER &= ~(1 << irq);
bogdanm 0:9b334a45a8ff 327 all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
bogdanm 0:9b334a45a8ff 328 if (all_disabled)
bogdanm 0:9b334a45a8ff 329 NVIC_DisableIRQ(irq_n);
bogdanm 0:9b334a45a8ff 330 }
bogdanm 0:9b334a45a8ff 331 }
bogdanm 0:9b334a45a8ff 332
bogdanm 0:9b334a45a8ff 333 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
bogdanm 0:9b334a45a8ff 334 if (RxIrq == irq)
bogdanm 0:9b334a45a8ff 335 uart_data[obj->index].rx_irq_set_api = enable;
bogdanm 0:9b334a45a8ff 336 serial_irq_set_internal(obj, irq, enable);
bogdanm 0:9b334a45a8ff 337 }
bogdanm 0:9b334a45a8ff 338
bogdanm 0:9b334a45a8ff 339 static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
bogdanm 0:9b334a45a8ff 340 uart_data[obj->index].rx_irq_set_flow = enable;
bogdanm 0:9b334a45a8ff 341 serial_irq_set_internal(obj, RxIrq, enable);
bogdanm 0:9b334a45a8ff 342 }
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /******************************************************************************
bogdanm 0:9b334a45a8ff 345 * READ/WRITE
bogdanm 0:9b334a45a8ff 346 ******************************************************************************/
bogdanm 0:9b334a45a8ff 347 int serial_getc(serial_t *obj) {
bogdanm 0:9b334a45a8ff 348 while (!serial_readable(obj));
bogdanm 0:9b334a45a8ff 349 int data = obj->uart->RBR;
bogdanm 0:9b334a45a8ff 350 if (NC != uart_data[obj->index].sw_rts.pin) {
bogdanm 0:9b334a45a8ff 351 gpio_write(&uart_data[obj->index].sw_rts, 0);
bogdanm 0:9b334a45a8ff 352 obj->uart->IER |= 1 << RxIrq;
bogdanm 0:9b334a45a8ff 353 }
bogdanm 0:9b334a45a8ff 354 return data;
bogdanm 0:9b334a45a8ff 355 }
bogdanm 0:9b334a45a8ff 356
bogdanm 0:9b334a45a8ff 357 void serial_putc(serial_t *obj, int c) {
bogdanm 0:9b334a45a8ff 358 while (!serial_writable(obj));
bogdanm 0:9b334a45a8ff 359 obj->uart->THR = c;
bogdanm 0:9b334a45a8ff 360 uart_data[obj->index].count++;
bogdanm 0:9b334a45a8ff 361 }
bogdanm 0:9b334a45a8ff 362
bogdanm 0:9b334a45a8ff 363 int serial_readable(serial_t *obj) {
bogdanm 0:9b334a45a8ff 364 return obj->uart->LSR & 0x01;
bogdanm 0:9b334a45a8ff 365 }
bogdanm 0:9b334a45a8ff 366
bogdanm 0:9b334a45a8ff 367 int serial_writable(serial_t *obj) {
bogdanm 0:9b334a45a8ff 368 int isWritable = 1;
bogdanm 0:9b334a45a8ff 369 if (NC != uart_data[obj->index].sw_cts.pin)
bogdanm 0:9b334a45a8ff 370 isWritable = (gpio_read(&uart_data[obj->index].sw_cts) == 0) && (obj->uart->LSR & 0x40); //If flow control: writable if CTS low + UART done
bogdanm 0:9b334a45a8ff 371 else {
bogdanm 0:9b334a45a8ff 372 if (obj->uart->LSR & 0x20)
bogdanm 0:9b334a45a8ff 373 uart_data[obj->index].count = 0;
bogdanm 0:9b334a45a8ff 374 else if (uart_data[obj->index].count >= 16)
bogdanm 0:9b334a45a8ff 375 isWritable = 0;
bogdanm 0:9b334a45a8ff 376 }
bogdanm 0:9b334a45a8ff 377 return isWritable;
bogdanm 0:9b334a45a8ff 378 }
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 void serial_clear(serial_t *obj) {
bogdanm 0:9b334a45a8ff 381 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
bogdanm 0:9b334a45a8ff 382 | 1 << 1 // rx FIFO reset
bogdanm 0:9b334a45a8ff 383 | 1 << 2 // tx FIFO reset
bogdanm 0:9b334a45a8ff 384 | 0 << 6; // interrupt depth
bogdanm 0:9b334a45a8ff 385 }
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 void serial_pinout_tx(PinName tx) {
bogdanm 0:9b334a45a8ff 388 pinmap_pinout(tx, PinMap_UART_TX);
bogdanm 0:9b334a45a8ff 389 }
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 void serial_break_set(serial_t *obj) {
bogdanm 0:9b334a45a8ff 392 obj->uart->LCR |= (1 << 6);
bogdanm 0:9b334a45a8ff 393 }
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 void serial_break_clear(serial_t *obj) {
bogdanm 0:9b334a45a8ff 396 obj->uart->LCR &= ~(1 << 6);
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
bogdanm 0:9b334a45a8ff 400 // Only UART1 has hardware flow control on LPC176x
bogdanm 0:9b334a45a8ff 401 LPC_UART1_TypeDef *uart1 = (uint32_t)obj->uart == (uint32_t)LPC_UART1 ? LPC_UART1 : NULL;
bogdanm 0:9b334a45a8ff 402 int index = obj->index;
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 // First, disable flow control completely
bogdanm 0:9b334a45a8ff 405 if (uart1)
bogdanm 0:9b334a45a8ff 406 uart1->MCR = uart1->MCR & ~UART_MCR_FLOWCTRL_MASK;
bogdanm 0:9b334a45a8ff 407 uart_data[index].sw_rts.pin = uart_data[index].sw_cts.pin = NC;
bogdanm 0:9b334a45a8ff 408 serial_flow_irq_set(obj, 0);
bogdanm 0:9b334a45a8ff 409 if (FlowControlNone == type)
bogdanm 0:9b334a45a8ff 410 return;
bogdanm 0:9b334a45a8ff 411 // Check type(s) of flow control to use
bogdanm 0:9b334a45a8ff 412 UARTName uart_rts = (UARTName)pinmap_find_peripheral(rxflow, PinMap_UART_RTS);
bogdanm 0:9b334a45a8ff 413 UARTName uart_cts = (UARTName)pinmap_find_peripheral(txflow, PinMap_UART_CTS);
bogdanm 0:9b334a45a8ff 414 if (((FlowControlCTS == type) || (FlowControlRTSCTS == type)) && (NC != txflow)) {
bogdanm 0:9b334a45a8ff 415 // Can this be enabled in hardware?
bogdanm 0:9b334a45a8ff 416 if ((UART_1 == uart_cts) && (NULL != uart1)) {
bogdanm 0:9b334a45a8ff 417 // Enable auto-CTS mode
bogdanm 0:9b334a45a8ff 418 uart1->MCR |= UART_MCR_CTSEN_MASK;
bogdanm 0:9b334a45a8ff 419 pinmap_pinout(txflow, PinMap_UART_CTS);
bogdanm 0:9b334a45a8ff 420 } else {
bogdanm 0:9b334a45a8ff 421 // Can't enable in hardware, use software emulation
bogdanm 0:9b334a45a8ff 422 gpio_init_in(&uart_data[index].sw_cts, txflow);
bogdanm 0:9b334a45a8ff 423 }
bogdanm 0:9b334a45a8ff 424 }
bogdanm 0:9b334a45a8ff 425 if (((FlowControlRTS == type) || (FlowControlRTSCTS == type)) && (NC != rxflow)) {
bogdanm 0:9b334a45a8ff 426 // Enable FIFOs, trigger level of 1 char on RX FIFO
bogdanm 0:9b334a45a8ff 427 obj->uart->FCR = 1 << 0 // FIFO Enable - 0 = Disables, 1 = Enabled
bogdanm 0:9b334a45a8ff 428 | 1 << 1 // Rx Fifo Reset
bogdanm 0:9b334a45a8ff 429 | 1 << 2 // Tx Fifo Reset
bogdanm 0:9b334a45a8ff 430 | 0 << 6; // Rx irq trigger level - 0 = 1 char, 1 = 4 chars, 2 = 8 chars, 3 = 14 chars
bogdanm 0:9b334a45a8ff 431 // Can this be enabled in hardware?
bogdanm 0:9b334a45a8ff 432 if ((UART_1 == uart_rts) && (NULL != uart1)) {
bogdanm 0:9b334a45a8ff 433 // Enable auto-RTS mode
bogdanm 0:9b334a45a8ff 434 uart1->MCR |= UART_MCR_RTSEN_MASK;
bogdanm 0:9b334a45a8ff 435 pinmap_pinout(rxflow, PinMap_UART_RTS);
bogdanm 0:9b334a45a8ff 436 } else { // can't enable in hardware, use software emulation
bogdanm 0:9b334a45a8ff 437 gpio_init_out_ex(&uart_data[index].sw_rts, rxflow, 0);
bogdanm 0:9b334a45a8ff 438 // Enable RX interrupt
bogdanm 0:9b334a45a8ff 439 serial_flow_irq_set(obj, 1);
bogdanm 0:9b334a45a8ff 440 }
bogdanm 0:9b334a45a8ff 441 }
bogdanm 0:9b334a45a8ff 442 }
bogdanm 0:9b334a45a8ff 443