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targets/cmsis/TARGET_Maxim/TARGET_MAX32620/system_max32620.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "max32620.h"
<> 144:ef7eb2e8f9f7 35 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 36 #include "icc_regs.h"
<> 144:ef7eb2e8f9f7 37 #include "pwrseq_regs.h"
<> 144:ef7eb2e8f9f7 38 #include "pwrman_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "adc_regs.h"
<> 144:ef7eb2e8f9f7 40 #include "flc_regs.h"
<> 144:ef7eb2e8f9f7 41 #include "trim_regs.h"
<> 144:ef7eb2e8f9f7 42 #include "rtc_regs.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 /* SCB CPACR Register Definitions */
<> 144:ef7eb2e8f9f7 45 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
<> 144:ef7eb2e8f9f7 46 #define SCB_CPACR_CP10_Pos 20 /* SCB CPACR: Coprocessor 10 Position */
<> 144:ef7eb2e8f9f7 47 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /* SCB CPACR: Coprocessor 10 Mask */
<> 144:ef7eb2e8f9f7 48 #define SCB_CPACR_CP11_Pos 22 /* SCB CPACR: Coprocessor 11 Position */
<> 144:ef7eb2e8f9f7 49 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /* SCB CPACR: Coprocessor 11 Mask */
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 static uint8_t running;
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 // NOTE: Setting the CMSIS SystemCoreClock value to the actual value it will
<> 144:ef7eb2e8f9f7 54 // be AFTER SystemInit() runs. This is required so the hal drivers will have
<> 144:ef7eb2e8f9f7 55 // the correct value when the DATA sections are initialized.
<> 144:ef7eb2e8f9f7 56 uint32_t SystemCoreClock = RO_FREQ;
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 void SystemCoreClockUpdate(void)
<> 144:ef7eb2e8f9f7 59 {
<> 144:ef7eb2e8f9f7 60 switch ((MXC_CLKMAN->clk_ctrl & MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT) >> MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS) {
<> 144:ef7eb2e8f9f7 61
<> 144:ef7eb2e8f9f7 62 case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO_DIV_2:
<> 144:ef7eb2e8f9f7 63 default:
<> 144:ef7eb2e8f9f7 64 SystemCoreClock = RO_FREQ / 2;
<> 144:ef7eb2e8f9f7 65 break;
<> 144:ef7eb2e8f9f7 66 case MXC_V_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_96MHZ_RO:
<> 144:ef7eb2e8f9f7 67 SystemCoreClock = RO_FREQ;
<> 144:ef7eb2e8f9f7 68 break;
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70 }
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 void Trim_ROAtomic(void)
<> 144:ef7eb2e8f9f7 73 {
<> 144:ef7eb2e8f9f7 74 uint32_t trim;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76 // Step 1: enable 32KHz RTC
<> 144:ef7eb2e8f9f7 77 running = MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 144:ef7eb2e8f9f7 78 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 // Step 2: enable RO calibration complete interrupt
<> 144:ef7eb2e8f9f7 81 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) | MXC_F_ADC_INTR_RO_CAL_DONE_IE;
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 // Step 3: clear RO calibration complete interrupt
<> 144:ef7eb2e8f9f7 84 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) | MXC_F_ADC_INTR_RO_CAL_DONE_IF;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* Step 4: -- NO LONGER NEEDED / HANDLED BY STARTUP CODE -- */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Step 5: write initial trim to frequency calibration initial condition register */
<> 144:ef7eb2e8f9f7 89 trim = (MXC_PWRSEQ->reg6 & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) >> MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS;
<> 144:ef7eb2e8f9f7 90 MXC_ADC->ro_cal1 = (MXC_ADC->ro_cal1 & ~MXC_F_ADC_RO_CAL1_TRM_INIT) |
<> 144:ef7eb2e8f9f7 91 ((trim << MXC_F_ADC_RO_CAL1_TRM_INIT_POS) & MXC_F_ADC_RO_CAL1_TRM_INIT);
<> 144:ef7eb2e8f9f7 92
<> 144:ef7eb2e8f9f7 93 // Step 6: load initial trim to active frequency trim register
<> 144:ef7eb2e8f9f7 94 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_LOAD;
<> 144:ef7eb2e8f9f7 95
<> 144:ef7eb2e8f9f7 96 // Step 7: enable frequency loop to control RO trim
<> 144:ef7eb2e8f9f7 97 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_EN;
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 // Step 8: run frequency calibration in atomic mode
<> 144:ef7eb2e8f9f7 100 MXC_ADC->ro_cal0 |= MXC_F_ADC_RO_CAL0_RO_CAL_ATOMIC;
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 // Step 9: waiting for ro_cal_done flag
<> 144:ef7eb2e8f9f7 103 while (!(MXC_ADC->intr & MXC_F_ADC_INTR_RO_CAL_DONE_IF));
<> 144:ef7eb2e8f9f7 104
<> 144:ef7eb2e8f9f7 105 // Step 10: stop frequency calibration
<> 144:ef7eb2e8f9f7 106 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_RUN;
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 // Step 11: disable RO calibration complete interrupt
<> 144:ef7eb2e8f9f7 109 MXC_ADC->intr = (MXC_ADC->intr & 0xFFFF) & ~MXC_F_ADC_INTR_RO_CAL_DONE_IE;
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 // Step 12: read final frequency trim value
<> 144:ef7eb2e8f9f7 112 trim = (MXC_ADC->ro_cal0 & MXC_F_ADC_RO_CAL0_RO_TRM) >> MXC_F_ADC_RO_CAL0_RO_TRM_POS;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /* Step 13: write final trim to RO flash trim shadow register */
<> 144:ef7eb2e8f9f7 115 MXC_PWRSEQ->reg6 = (MXC_PWRSEQ->reg6 & ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF) |
<> 144:ef7eb2e8f9f7 116 ((trim << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS) & MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF);
<> 144:ef7eb2e8f9f7 117
<> 144:ef7eb2e8f9f7 118 // Step 14: restore RTC status
<> 144:ef7eb2e8f9f7 119 if (!running) {
<> 144:ef7eb2e8f9f7 120 MXC_PWRSEQ->reg0 &= ~MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 144:ef7eb2e8f9f7 121 }
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 // Step 15: disable frequency loop to control RO trim
<> 144:ef7eb2e8f9f7 124 MXC_ADC->ro_cal0 &= ~MXC_F_ADC_RO_CAL0_RO_CAL_EN;
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 static void ICC_Enable(void)
<> 144:ef7eb2e8f9f7 128 {
<> 144:ef7eb2e8f9f7 129 /* Invalidate cache and wait until ready */
<> 144:ef7eb2e8f9f7 130 MXC_ICC->invdt_all = 1;
<> 144:ef7eb2e8f9f7 131 while (!(MXC_ICC->ctrl_stat & MXC_F_ICC_CTRL_STAT_READY));
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /* Enable cache */
<> 144:ef7eb2e8f9f7 134 MXC_ICC->ctrl_stat |= MXC_F_ICC_CTRL_STAT_ENABLE;
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /* Must invalidate a second time for proper use */
<> 144:ef7eb2e8f9f7 137 MXC_ICC->invdt_all = 1;
<> 144:ef7eb2e8f9f7 138 }
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 // This function to be implemented by the hal
<> 144:ef7eb2e8f9f7 141 extern void low_level_init(void);
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 // Note: This is called before C run-time initialization. Do not use any initialized variables.
<> 144:ef7eb2e8f9f7 144 void SystemInit(void)
<> 144:ef7eb2e8f9f7 145 {
<> 144:ef7eb2e8f9f7 146 ICC_Enable();
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 low_level_init();
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 // Select 96MHz ring oscillator as clock source
<> 144:ef7eb2e8f9f7 151 uint32_t reg = MXC_CLKMAN->clk_ctrl;
<> 144:ef7eb2e8f9f7 152 reg &= ~MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT;
<> 144:ef7eb2e8f9f7 153 reg |= 1 << MXC_F_CLKMAN_CLK_CTRL_SYSTEM_SOURCE_SELECT_POS;
<> 144:ef7eb2e8f9f7 154 MXC_CLKMAN->clk_ctrl = reg;
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 // Copy trim information from shadow registers into power manager registers
<> 144:ef7eb2e8f9f7 157 // NOTE: Checks have been added to prevent bad/missing trim values from being loaded
<> 144:ef7eb2e8f9f7 158 if ((MXC_FLC->ctrl & MXC_F_FLC_CTRL_INFO_BLOCK_VALID) &&
<> 144:ef7eb2e8f9f7 159 (MXC_TRIM->for_pwr_reg5 != 0xffffffff) &&
<> 144:ef7eb2e8f9f7 160 (MXC_TRIM->for_pwr_reg6 != 0xffffffff)) {
<> 144:ef7eb2e8f9f7 161 MXC_PWRSEQ->reg5 = MXC_TRIM->for_pwr_reg5;
<> 144:ef7eb2e8f9f7 162 MXC_PWRSEQ->reg6 = MXC_TRIM->for_pwr_reg6;
<> 144:ef7eb2e8f9f7 163 } else {
<> 144:ef7eb2e8f9f7 164 /* No valid info block, use some reasonable defaults */
<> 144:ef7eb2e8f9f7 165 MXC_PWRSEQ->reg6 &= ~MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF;
<> 144:ef7eb2e8f9f7 166 MXC_PWRSEQ->reg6 |= (0x1e0 << MXC_F_PWRSEQ_REG6_PWR_TRIM_OSC_VREF_POS);
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 // Use ASYNC flags, and ASYNC Reset of flags to improve synchronization speed
<> 144:ef7eb2e8f9f7 170 // between RTC and ARM core. Also avoid delayed RTC interrupts after lp wake.
<> 144:ef7eb2e8f9f7 171 MXC_RTCTMR->ctrl |= (MXC_F_RTC_CTRL_USE_ASYNC_FLAGS | MXC_F_RTC_CTRL_AGGRESSIVE_RST);
<> 144:ef7eb2e8f9f7 172
<> 144:ef7eb2e8f9f7 173 /* Clear the GPIO WUD event if not waking up from LP0 */
<> 144:ef7eb2e8f9f7 174 /* this is necessary because WUD flops come up in undetermined state out of POR or SRST*/
<> 144:ef7eb2e8f9f7 175 if (MXC_PWRSEQ->reg0 & MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT || !(MXC_PWRMAN->pwr_rst_ctrl & MXC_F_PWRMAN_PWR_RST_CTRL_POR)) {
<> 144:ef7eb2e8f9f7 176 /* Clear GPIO WUD event and configuration registers, globally */
<> 144:ef7eb2e8f9f7 177 MXC_PWRSEQ->reg1 |= (MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
<> 144:ef7eb2e8f9f7 178 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_CLR_IO_EVENT_LATCH | MXC_F_PWRSEQ_REG1_PWR_CLR_IO_CFG_LATCH);
<> 144:ef7eb2e8f9f7 179 } else {
<> 144:ef7eb2e8f9f7 180 /* Unfreeze the GPIO by clearing MBUS_GATE, when returning from LP0 */
<> 144:ef7eb2e8f9f7 181 MXC_PWRSEQ->reg1 &= ~(MXC_F_PWRSEQ_REG1_PWR_MBUS_GATE);
<> 144:ef7eb2e8f9f7 182 }
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 // Turn on retention regulator
<> 144:ef7eb2e8f9f7 185 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RETREGEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RETREGEN_SLP);
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 // Clear all unused wakeup sources
<> 144:ef7eb2e8f9f7 188 // Beware! Do not change any flag not mentioned here, as they will gate important power sequencer signals
<> 144:ef7eb2e8f9f7 189 MXC_PWRSEQ->msk_flags &= ~(MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP |
<> 144:ef7eb2e8f9f7 190 MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP);
<> 144:ef7eb2e8f9f7 191
<> 144:ef7eb2e8f9f7 192 // RTC sources are inverted, so a 1 will disable them
<> 144:ef7eb2e8f9f7 193 MXC_PWRSEQ->msk_flags |= (MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1 |
<> 144:ef7eb2e8f9f7 194 MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP);
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Enable RTOS Mode: Enable 32kHz clock synchronizer to SysTick external clock input */
<> 144:ef7eb2e8f9f7 197 MXC_CLKMAN->clk_ctrl |= MXC_F_CLKMAN_CLK_CTRL_RTOS_MODE;
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 // Enable real-time clock during sleep mode
<> 144:ef7eb2e8f9f7 200 MXC_PWRSEQ->reg0 |= (MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 #if (__FPU_PRESENT == 1)
<> 144:ef7eb2e8f9f7 203 /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
<> 144:ef7eb2e8f9f7 204 /* Grant full access, per "Table B3-24 CPACR bit assignments". */
<> 144:ef7eb2e8f9f7 205 /* DDI0403D "ARMv7-M Architecture Reference Manual" */
<> 144:ef7eb2e8f9f7 206 SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
<> 144:ef7eb2e8f9f7 207 __DSB();
<> 144:ef7eb2e8f9f7 208 __ISB();
<> 144:ef7eb2e8f9f7 209 #endif
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 // Trim ring oscillator
<> 144:ef7eb2e8f9f7 212 Trim_ROAtomic();
<> 144:ef7eb2e8f9f7 213 }