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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_tim_ex.c@148:e70627d019e9, 2016-09-28 (annotated)

Committer:: StevieWray
Date:: Wed Sep 28 08:45:18 2016 +0000
Revision:: 148:e70627d019e9
Parent:: 144:ef7eb2e8f9f7

Fixed DAC output on STM32F3 boards to allow 3 outputs

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32f3xx_hal_tim_ex.c
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.3.0
<>	144:ef7eb2e8f9f7	6	* @date 01-July-2016
<>	144:ef7eb2e8f9f7	7	* @brief TIM HAL module driver.
<>	144:ef7eb2e8f9f7	8	* This file provides firmware functions to manage the following
<>	144:ef7eb2e8f9f7	9	* functionalities of the Timer Extended peripheral:
<>	144:ef7eb2e8f9f7	10	* + Time Hall Sensor Interface Initialization
<>	144:ef7eb2e8f9f7	11	* + Time Hall Sensor Interface Start
<>	144:ef7eb2e8f9f7	12	* + Time Complementary signal bread and dead time configuration
<>	144:ef7eb2e8f9f7	13	* + Time Master and Slave synchronization configuration
<>	144:ef7eb2e8f9f7	14	* + Time Output Compare/PWM Channel Configuration (for channels 5 and 6)
<>	144:ef7eb2e8f9f7	15	* + Time OCRef clear configuration
<>	144:ef7eb2e8f9f7	16	* + Timer remapping capabilities configuration
<>	144:ef7eb2e8f9f7	17	@verbatim
<>	144:ef7eb2e8f9f7	18	==============================================================================
<>	144:ef7eb2e8f9f7	19	##### TIMER Extended features #####
<>	144:ef7eb2e8f9f7	20	==============================================================================
<>	144:ef7eb2e8f9f7	21	[..]
<>	144:ef7eb2e8f9f7	22	The Timer Extended features include:
<>	144:ef7eb2e8f9f7	23	(#) Complementary outputs with programmable dead-time for :
<>	144:ef7eb2e8f9f7	24	(++) Output Compare
<>	144:ef7eb2e8f9f7	25	(++) PWM generation (Edge and Center-aligned Mode)
<>	144:ef7eb2e8f9f7	26	(++) One-pulse mode output
<>	144:ef7eb2e8f9f7	27	(#) Synchronization circuit to control the timer with external signals and to
<>	144:ef7eb2e8f9f7	28	interconnect several timers together.
<>	144:ef7eb2e8f9f7	29	(#) Break input to put the timer output signals in reset state or in a known state.
<>	144:ef7eb2e8f9f7	30	(#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<>	144:ef7eb2e8f9f7	31	positioning purposes
<>	144:ef7eb2e8f9f7	32
<>	144:ef7eb2e8f9f7	33	##### How to use this driver #####
<>	144:ef7eb2e8f9f7	34	==============================================================================
<>	144:ef7eb2e8f9f7	35	[..]
<>	144:ef7eb2e8f9f7	36	(#) Initialize the TIM low level resources by implementing the following functions
<>	144:ef7eb2e8f9f7	37	depending from feature used :
<>	144:ef7eb2e8f9f7	38	(++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<>	144:ef7eb2e8f9f7	39	(++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<>	144:ef7eb2e8f9f7	40	(++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<>	144:ef7eb2e8f9f7	41	(++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
<>	144:ef7eb2e8f9f7	42
<>	144:ef7eb2e8f9f7	43	(#) Initialize the TIM low level resources :
<>	144:ef7eb2e8f9f7	44	(##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE ();
<>	144:ef7eb2e8f9f7	45	(##) TIM pins configuration
<>	144:ef7eb2e8f9f7	46	(+++) Enable the clock for the TIM GPIOs using the following function:
<>	144:ef7eb2e8f9f7	47	__HAL_RCC_GPIOx_CLK_ENABLE();
<>	144:ef7eb2e8f9f7	48	(+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<>	144:ef7eb2e8f9f7	49
<>	144:ef7eb2e8f9f7	50	(#) The external Clock can be configured, if needed (the default clock is the
<>	144:ef7eb2e8f9f7	51	internal clock from the APBx), using the following function:
<>	144:ef7eb2e8f9f7	52	HAL_TIM_ConfigClockSource, the clock configuration should be done before
<>	144:ef7eb2e8f9f7	53	any start function.
<>	144:ef7eb2e8f9f7	54
<>	144:ef7eb2e8f9f7	55	(#) Configure the TIM in the desired functioning mode using one of the
<>	144:ef7eb2e8f9f7	56	initialization function of this driver:
<>	144:ef7eb2e8f9f7	57	(++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<>	144:ef7eb2e8f9f7	58	Timer Hall Sensor Interface and the commutation event with the corresponding
<>	144:ef7eb2e8f9f7	59	Interrupt and DMA request if needed (Note that One Timer is used to interface
<>	144:ef7eb2e8f9f7	60	with the Hall sensor Interface and another Timer should be used to use
<>	144:ef7eb2e8f9f7	61	the commutation event).
<>	144:ef7eb2e8f9f7	62
<>	144:ef7eb2e8f9f7	63	(#) Activate the TIM peripheral using one of the start functions:
<>	144:ef7eb2e8f9f7	64	(++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT()
<>	144:ef7eb2e8f9f7	65	(++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<>	144:ef7eb2e8f9f7	66	(++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<>	144:ef7eb2e8f9f7	67	(++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<>	144:ef7eb2e8f9f7	68
<>	144:ef7eb2e8f9f7	69
<>	144:ef7eb2e8f9f7	70	@endverbatim
<>	144:ef7eb2e8f9f7	71	******************************************************************************
<>	144:ef7eb2e8f9f7	72	* @attention
<>	144:ef7eb2e8f9f7	73	*
<>	144:ef7eb2e8f9f7	74	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	75	*
<>	144:ef7eb2e8f9f7	76	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	77	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	78	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	79	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	80	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	81	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	82	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	83	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	84	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	85	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	86	*
<>	144:ef7eb2e8f9f7	87	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	88	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	89	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	90	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	91	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	92	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	93	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	94	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	95	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	96	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	97	*
<>	144:ef7eb2e8f9f7	98	******************************************************************************
<>	144:ef7eb2e8f9f7	99	*/
<>	144:ef7eb2e8f9f7	100
<>	144:ef7eb2e8f9f7	101	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	102	#include "stm32f3xx_hal.h"
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	/** @addtogroup STM32F3xx_HAL_Driver
<>	144:ef7eb2e8f9f7	105	* @{
<>	144:ef7eb2e8f9f7	106	*/
<>	144:ef7eb2e8f9f7	107
<>	144:ef7eb2e8f9f7	108	/** @defgroup TIMEx TIMEx
<>	144:ef7eb2e8f9f7	109	* @brief TIM Extended HAL module driver
<>	144:ef7eb2e8f9f7	110	* @{
<>	144:ef7eb2e8f9f7	111	*/
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	#ifdef HAL_TIM_MODULE_ENABLED
<>	144:ef7eb2e8f9f7	114
<>	144:ef7eb2e8f9f7	115	/* Private typedef -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	116	/* Private define ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	117	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	118	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	119	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	120	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	121
<>	144:ef7eb2e8f9f7	122	#define BDTR_BKF_SHIFT (16)
<>	144:ef7eb2e8f9f7	123	#define BDTR_BK2F_SHIFT (20)
<>	144:ef7eb2e8f9f7	124	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	125	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	126	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	127	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	/* Private macro -------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	130	/* Private variables ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	131	/* Private function prototypes -----------------------------------------------*/
<>	144:ef7eb2e8f9f7	132
<>	144:ef7eb2e8f9f7	133	/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
<>	144:ef7eb2e8f9f7	134	* @{
<>	144:ef7eb2e8f9f7	135	*/
<>	144:ef7eb2e8f9f7	136	static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<>	144:ef7eb2e8f9f7	137
<>	144:ef7eb2e8f9f7	138	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	139	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	140	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	141	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	142	static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
<>	144:ef7eb2e8f9f7	143	TIM_OC_InitTypeDef *OC_Config);
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
<>	144:ef7eb2e8f9f7	146	TIM_OC_InitTypeDef *OC_Config);
<>	144:ef7eb2e8f9f7	147	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	148	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	149	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	150	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	151
<>	144:ef7eb2e8f9f7	152	/**
<>	144:ef7eb2e8f9f7	153	* @}
<>	144:ef7eb2e8f9f7	154	*/
<>	144:ef7eb2e8f9f7	155
<>	144:ef7eb2e8f9f7	156	/* Exported functions ---------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	157
<>	144:ef7eb2e8f9f7	158	/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
<>	144:ef7eb2e8f9f7	159	* @{
<>	144:ef7eb2e8f9f7	160	*/
<>	144:ef7eb2e8f9f7	161
<>	144:ef7eb2e8f9f7	162	/** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
<>	144:ef7eb2e8f9f7	163	* @brief Timer Hall Sensor functions
<>	144:ef7eb2e8f9f7	164	*
<>	144:ef7eb2e8f9f7	165	@verbatim
<>	144:ef7eb2e8f9f7	166	==============================================================================
<>	144:ef7eb2e8f9f7	167	##### Timer Hall Sensor functions #####
<>	144:ef7eb2e8f9f7	168	==============================================================================
<>	144:ef7eb2e8f9f7	169	[..]
<>	144:ef7eb2e8f9f7	170	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	171	(+) Initialize and configure TIM HAL Sensor.
<>	144:ef7eb2e8f9f7	172	(+) De-initialize TIM HAL Sensor.
<>	144:ef7eb2e8f9f7	173	(+) Start the Hall Sensor Interface.
<>	144:ef7eb2e8f9f7	174	(+) Stop the Hall Sensor Interface.
<>	144:ef7eb2e8f9f7	175	(+) Start the Hall Sensor Interface and enable interrupts.
<>	144:ef7eb2e8f9f7	176	(+) Stop the Hall Sensor Interface and disable interrupts.
<>	144:ef7eb2e8f9f7	177	(+) Start the Hall Sensor Interface and enable DMA transfers.
<>	144:ef7eb2e8f9f7	178	(+) Stop the Hall Sensor Interface and disable DMA transfers.
<>	144:ef7eb2e8f9f7	179
<>	144:ef7eb2e8f9f7	180	@endverbatim
<>	144:ef7eb2e8f9f7	181	* @{
<>	144:ef7eb2e8f9f7	182	*/
<>	144:ef7eb2e8f9f7	183	/**
<>	144:ef7eb2e8f9f7	184	* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<>	144:ef7eb2e8f9f7	185	* @param htim: TIM Encoder Interface handle
<>	144:ef7eb2e8f9f7	186	* @param sConfig: TIM Hall Sensor configuration structure
<>	144:ef7eb2e8f9f7	187	* @retval HAL status
<>	144:ef7eb2e8f9f7	188	*/
<>	144:ef7eb2e8f9f7	189	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef htim, TIM_HallSensor_InitTypeDef sConfig)
<>	144:ef7eb2e8f9f7	190	{
<>	144:ef7eb2e8f9f7	191	TIM_OC_InitTypeDef OC_Config;
<>	144:ef7eb2e8f9f7	192
<>	144:ef7eb2e8f9f7	193	/* Check the TIM handle allocation */
<>	144:ef7eb2e8f9f7	194	if(htim == NULL)
<>	144:ef7eb2e8f9f7	195	{
<>	144:ef7eb2e8f9f7	196	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	197	}
<>	144:ef7eb2e8f9f7	198
<>	144:ef7eb2e8f9f7	199	assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	200	assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<>	144:ef7eb2e8f9f7	201	assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<>	144:ef7eb2e8f9f7	202	assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<>	144:ef7eb2e8f9f7	203	assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<>	144:ef7eb2e8f9f7	204	assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<>	144:ef7eb2e8f9f7	205
<>	144:ef7eb2e8f9f7	206	if(htim->State == HAL_TIM_STATE_RESET)
<>	144:ef7eb2e8f9f7	207	{
<>	144:ef7eb2e8f9f7	208	/* Allocate lock resource and initialize it */
<>	144:ef7eb2e8f9f7	209	htim->Lock = HAL_UNLOCKED;
<>	144:ef7eb2e8f9f7	210
<>	144:ef7eb2e8f9f7	211	/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<>	144:ef7eb2e8f9f7	212	HAL_TIMEx_HallSensor_MspInit(htim);
<>	144:ef7eb2e8f9f7	213	}
<>	144:ef7eb2e8f9f7	214
<>	144:ef7eb2e8f9f7	215	/* Set the TIM state */
<>	144:ef7eb2e8f9f7	216	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	/* Configure the Time base in the Encoder Mode */
<>	144:ef7eb2e8f9f7	219	TIM_Base_SetConfig(htim->Instance, &htim->Init);
<>	144:ef7eb2e8f9f7	220
<>	144:ef7eb2e8f9f7	221	/* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<>	144:ef7eb2e8f9f7	222	TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<>	144:ef7eb2e8f9f7	223
<>	144:ef7eb2e8f9f7	224	/* Reset the IC1PSC Bits */
<>	144:ef7eb2e8f9f7	225	htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<>	144:ef7eb2e8f9f7	226	/* Set the IC1PSC value */
<>	144:ef7eb2e8f9f7	227	htim->Instance->CCMR1 \|= sConfig->IC1Prescaler;
<>	144:ef7eb2e8f9f7	228
<>	144:ef7eb2e8f9f7	229	/* Enable the Hall sensor interface (XOR function of the three inputs) */
<>	144:ef7eb2e8f9f7	230	htim->Instance->CR2 \|= TIM_CR2_TI1S;
<>	144:ef7eb2e8f9f7	231
<>	144:ef7eb2e8f9f7	232	/* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<>	144:ef7eb2e8f9f7	233	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	234	htim->Instance->SMCR \|= TIM_TS_TI1F_ED;
<>	144:ef7eb2e8f9f7	235
<>	144:ef7eb2e8f9f7	236	/* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<>	144:ef7eb2e8f9f7	237	htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<>	144:ef7eb2e8f9f7	238	htim->Instance->SMCR \|= TIM_SLAVEMODE_RESET;
<>	144:ef7eb2e8f9f7	239
<>	144:ef7eb2e8f9f7	240	/* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<>	144:ef7eb2e8f9f7	241	OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<>	144:ef7eb2e8f9f7	242	OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<>	144:ef7eb2e8f9f7	243	OC_Config.OCMode = TIM_OCMODE_PWM2;
<>	144:ef7eb2e8f9f7	244	OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<>	144:ef7eb2e8f9f7	245	OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<>	144:ef7eb2e8f9f7	246	OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<>	144:ef7eb2e8f9f7	247	OC_Config.Pulse = sConfig->Commutation_Delay;
<>	144:ef7eb2e8f9f7	248
<>	144:ef7eb2e8f9f7	249	TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<>	144:ef7eb2e8f9f7	250
<>	144:ef7eb2e8f9f7	251	/* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<>	144:ef7eb2e8f9f7	252	register to 101 */
<>	144:ef7eb2e8f9f7	253	htim->Instance->CR2 &= ~TIM_CR2_MMS;
<>	144:ef7eb2e8f9f7	254	htim->Instance->CR2 \|= TIM_TRGO_OC2REF;
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	/* Initialize the TIM state*/
<>	144:ef7eb2e8f9f7	257	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	258
<>	144:ef7eb2e8f9f7	259	return HAL_OK;
<>	144:ef7eb2e8f9f7	260	}
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	/**
<>	144:ef7eb2e8f9f7	263	* @brief DeInitializes the TIM Hall Sensor interface
<>	144:ef7eb2e8f9f7	264	* @param htim: TIM Hall Sensor handle
<>	144:ef7eb2e8f9f7	265	* @retval HAL status
<>	144:ef7eb2e8f9f7	266	*/
<>	144:ef7eb2e8f9f7	267	HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	268	{
<>	144:ef7eb2e8f9f7	269	/* Check the parameters */
<>	144:ef7eb2e8f9f7	270	assert_param(IS_TIM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	271
<>	144:ef7eb2e8f9f7	272	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	273
<>	144:ef7eb2e8f9f7	274	/* Disable the TIM Peripheral Clock */
<>	144:ef7eb2e8f9f7	275	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<>	144:ef7eb2e8f9f7	278	HAL_TIMEx_HallSensor_MspDeInit(htim);
<>	144:ef7eb2e8f9f7	279
<>	144:ef7eb2e8f9f7	280	/* Change TIM state */
<>	144:ef7eb2e8f9f7	281	htim->State = HAL_TIM_STATE_RESET;
<>	144:ef7eb2e8f9f7	282
<>	144:ef7eb2e8f9f7	283	/* Release Lock */
<>	144:ef7eb2e8f9f7	284	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	285
<>	144:ef7eb2e8f9f7	286	return HAL_OK;
<>	144:ef7eb2e8f9f7	287	}
<>	144:ef7eb2e8f9f7	288
<>	144:ef7eb2e8f9f7	289	/**
<>	144:ef7eb2e8f9f7	290	* @brief Initializes the TIM Hall Sensor MSP.
<>	144:ef7eb2e8f9f7	291	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	292	* @retval None
<>	144:ef7eb2e8f9f7	293	*/
<>	144:ef7eb2e8f9f7	294	__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	295	{
<>	144:ef7eb2e8f9f7	296	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	297	UNUSED(htim);
<>	144:ef7eb2e8f9f7	298
<>	144:ef7eb2e8f9f7	299	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	300	the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	301	*/
<>	144:ef7eb2e8f9f7	302	}
<>	144:ef7eb2e8f9f7	303
<>	144:ef7eb2e8f9f7	304	/**
<>	144:ef7eb2e8f9f7	305	* @brief DeInitializes TIM Hall Sensor MSP.
<>	144:ef7eb2e8f9f7	306	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	307	* @retval None
<>	144:ef7eb2e8f9f7	308	*/
<>	144:ef7eb2e8f9f7	309	__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	310	{
<>	144:ef7eb2e8f9f7	311	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	312	UNUSED(htim);
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	315	the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317	}
<>	144:ef7eb2e8f9f7	318
<>	144:ef7eb2e8f9f7	319	/**
<>	144:ef7eb2e8f9f7	320	* @brief Starts the TIM Hall Sensor Interface.
<>	144:ef7eb2e8f9f7	321	* @param htim: TIM Hall Sensor handle
<>	144:ef7eb2e8f9f7	322	* @retval HAL status
<>	144:ef7eb2e8f9f7	323	*/
<>	144:ef7eb2e8f9f7	324	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	325	{
<>	144:ef7eb2e8f9f7	326	/* Check the parameters */
<>	144:ef7eb2e8f9f7	327	assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	328
<>	144:ef7eb2e8f9f7	329	/* Enable the Input Capture channel 1
<>	144:ef7eb2e8f9f7	330	(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<>	144:ef7eb2e8f9f7	331	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	334	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	335
<>	144:ef7eb2e8f9f7	336	/* Return function status */
<>	144:ef7eb2e8f9f7	337	return HAL_OK;
<>	144:ef7eb2e8f9f7	338	}
<>	144:ef7eb2e8f9f7	339
<>	144:ef7eb2e8f9f7	340	/**
<>	144:ef7eb2e8f9f7	341	* @brief Stops the TIM Hall sensor Interface.
<>	144:ef7eb2e8f9f7	342	* @param htim: TIM Hall Sensor handle
<>	144:ef7eb2e8f9f7	343	* @retval HAL status
<>	144:ef7eb2e8f9f7	344	*/
<>	144:ef7eb2e8f9f7	345	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	346	{
<>	144:ef7eb2e8f9f7	347	/* Check the parameters */
<>	144:ef7eb2e8f9f7	348	assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	349
<>	144:ef7eb2e8f9f7	350	/* Disable the Input Capture channels 1, 2 and 3
<>	144:ef7eb2e8f9f7	351	(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<>	144:ef7eb2e8f9f7	352	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	353
<>	144:ef7eb2e8f9f7	354	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	355	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	356
<>	144:ef7eb2e8f9f7	357	/* Return function status */
<>	144:ef7eb2e8f9f7	358	return HAL_OK;
<>	144:ef7eb2e8f9f7	359	}
<>	144:ef7eb2e8f9f7	360
<>	144:ef7eb2e8f9f7	361	/**
<>	144:ef7eb2e8f9f7	362	* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	363	* @param htim: TIM Hall Sensor handle
<>	144:ef7eb2e8f9f7	364	* @retval HAL status
<>	144:ef7eb2e8f9f7	365	*/
<>	144:ef7eb2e8f9f7	366	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	367	{
<>	144:ef7eb2e8f9f7	368	/* Check the parameters */
<>	144:ef7eb2e8f9f7	369	assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	370
<>	144:ef7eb2e8f9f7	371	/* Enable the capture compare Interrupts 1 event */
<>	144:ef7eb2e8f9f7	372	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	373
<>	144:ef7eb2e8f9f7	374	/* Enable the Input Capture channel 1
<>	144:ef7eb2e8f9f7	375	(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<>	144:ef7eb2e8f9f7	376	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	377
<>	144:ef7eb2e8f9f7	378	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	379	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	380
<>	144:ef7eb2e8f9f7	381	/* Return function status */
<>	144:ef7eb2e8f9f7	382	return HAL_OK;
<>	144:ef7eb2e8f9f7	383	}
<>	144:ef7eb2e8f9f7	384
<>	144:ef7eb2e8f9f7	385	/**
<>	144:ef7eb2e8f9f7	386	* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<>	144:ef7eb2e8f9f7	387	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	388	* @retval HAL status
<>	144:ef7eb2e8f9f7	389	*/
<>	144:ef7eb2e8f9f7	390	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	391	{
<>	144:ef7eb2e8f9f7	392	/* Check the parameters */
<>	144:ef7eb2e8f9f7	393	assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	394
<>	144:ef7eb2e8f9f7	395	/* Disable the Input Capture channel 1
<>	144:ef7eb2e8f9f7	396	(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<>	144:ef7eb2e8f9f7	397	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	398
<>	144:ef7eb2e8f9f7	399	/* Disable the capture compare Interrupts event */
<>	144:ef7eb2e8f9f7	400	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	401
<>	144:ef7eb2e8f9f7	402	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	403	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	404
<>	144:ef7eb2e8f9f7	405	/* Return function status */
<>	144:ef7eb2e8f9f7	406	return HAL_OK;
<>	144:ef7eb2e8f9f7	407	}
<>	144:ef7eb2e8f9f7	408
<>	144:ef7eb2e8f9f7	409	/**
<>	144:ef7eb2e8f9f7	410	* @brief Starts the TIM Hall Sensor Interface in DMA mode.
<>	144:ef7eb2e8f9f7	411	* @param htim: TIM Hall Sensor handle
<>	144:ef7eb2e8f9f7	412	* @param pData: The destination Buffer address.
<>	144:ef7eb2e8f9f7	413	* @param Length: The length of data to be transferred from TIM peripheral to memory.
<>	144:ef7eb2e8f9f7	414	* @retval HAL status
<>	144:ef7eb2e8f9f7	415	*/
<>	144:ef7eb2e8f9f7	416	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	417	{
<>	144:ef7eb2e8f9f7	418	/* Check the parameters */
<>	144:ef7eb2e8f9f7	419	assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	420
<>	144:ef7eb2e8f9f7	421	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	422	{
<>	144:ef7eb2e8f9f7	423	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	424	}
<>	144:ef7eb2e8f9f7	425	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	426	{
<>	144:ef7eb2e8f9f7	427	if(((uint32_t)pData == 0 ) && (Length > 0))
<>	144:ef7eb2e8f9f7	428	{
<>	144:ef7eb2e8f9f7	429	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	430	}
<>	144:ef7eb2e8f9f7	431	else
<>	144:ef7eb2e8f9f7	432	{
<>	144:ef7eb2e8f9f7	433	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	434	}
<>	144:ef7eb2e8f9f7	435	}
<>	144:ef7eb2e8f9f7	436	/* Enable the Input Capture channel 1
<>	144:ef7eb2e8f9f7	437	(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<>	144:ef7eb2e8f9f7	438	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<>	144:ef7eb2e8f9f7	439
<>	144:ef7eb2e8f9f7	440	/* Set the DMA Input Capture 1 Callback */
<>	144:ef7eb2e8f9f7	441	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<>	144:ef7eb2e8f9f7	442	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	443	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	444
<>	144:ef7eb2e8f9f7	445	/* Enable the DMA channel for Capture 1*/
<>	144:ef7eb2e8f9f7	446	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<>	144:ef7eb2e8f9f7	447
<>	144:ef7eb2e8f9f7	448	/* Enable the capture compare 1 Interrupt */
<>	144:ef7eb2e8f9f7	449	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	450
<>	144:ef7eb2e8f9f7	451	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	452	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	453
<>	144:ef7eb2e8f9f7	454	/* Return function status */
<>	144:ef7eb2e8f9f7	455	return HAL_OK;
<>	144:ef7eb2e8f9f7	456	}
<>	144:ef7eb2e8f9f7	457
<>	144:ef7eb2e8f9f7	458	/**
<>	144:ef7eb2e8f9f7	459	* @brief Stops the TIM Hall Sensor Interface in DMA mode.
<>	144:ef7eb2e8f9f7	460	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	461	* @retval HAL status
<>	144:ef7eb2e8f9f7	462	*/
<>	144:ef7eb2e8f9f7	463	HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	464	{
<>	144:ef7eb2e8f9f7	465	/* Check the parameters */
<>	144:ef7eb2e8f9f7	466	assert_param(IS_TIM_HALL_INTERFACE_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	467
<>	144:ef7eb2e8f9f7	468	/* Disable the Input Capture channel 1
<>	144:ef7eb2e8f9f7	469	(in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<>	144:ef7eb2e8f9f7	470	TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<>	144:ef7eb2e8f9f7	471
<>	144:ef7eb2e8f9f7	472
<>	144:ef7eb2e8f9f7	473	/* Disable the capture compare Interrupts 1 event */
<>	144:ef7eb2e8f9f7	474	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	475
<>	144:ef7eb2e8f9f7	476	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	477	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	478
<>	144:ef7eb2e8f9f7	479	/* Return function status */
<>	144:ef7eb2e8f9f7	480	return HAL_OK;
<>	144:ef7eb2e8f9f7	481	}
<>	144:ef7eb2e8f9f7	482
<>	144:ef7eb2e8f9f7	483	/**
<>	144:ef7eb2e8f9f7	484	* @}
<>	144:ef7eb2e8f9f7	485	*/
<>	144:ef7eb2e8f9f7	486
<>	144:ef7eb2e8f9f7	487	/** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
<>	144:ef7eb2e8f9f7	488	* @brief Timer Complementary Output Compare functions
<>	144:ef7eb2e8f9f7	489	*
<>	144:ef7eb2e8f9f7	490	@verbatim
<>	144:ef7eb2e8f9f7	491	==============================================================================
<>	144:ef7eb2e8f9f7	492	##### Timer Complementary Output Compare functions #####
<>	144:ef7eb2e8f9f7	493	==============================================================================
<>	144:ef7eb2e8f9f7	494	[..]
<>	144:ef7eb2e8f9f7	495	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	496	(+) Start the Complementary Output Compare.
<>	144:ef7eb2e8f9f7	497	(+) Stop the Complementary Output Compare.
<>	144:ef7eb2e8f9f7	498	(+) Start the Complementary Output Compare and enable interrupts.
<>	144:ef7eb2e8f9f7	499	(+) Stop the Complementary Output Compare and disable interrupts.
<>	144:ef7eb2e8f9f7	500	(+) Start the Complementary Output Compare and enable DMA transfers.
<>	144:ef7eb2e8f9f7	501	(+) Stop the Complementary Output Compare and disable DMA transfers.
<>	144:ef7eb2e8f9f7	502
<>	144:ef7eb2e8f9f7	503	@endverbatim
<>	144:ef7eb2e8f9f7	504	* @{
<>	144:ef7eb2e8f9f7	505	*/
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	/**
<>	144:ef7eb2e8f9f7	508	* @brief Starts the TIM Output Compare signal generation on the complementary
<>	144:ef7eb2e8f9f7	509	* output.
<>	144:ef7eb2e8f9f7	510	* @param htim: TIM Output Compare handle
<>	144:ef7eb2e8f9f7	511	* @param Channel: TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	512	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	513	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	514	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	515	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	516	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	517	* @retval HAL status
<>	144:ef7eb2e8f9f7	518	*/
<>	144:ef7eb2e8f9f7	519	HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	520	{
<>	144:ef7eb2e8f9f7	521	/* Check the parameters */
<>	144:ef7eb2e8f9f7	522	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	523
<>	144:ef7eb2e8f9f7	524	/* Enable the Capture compare channel N */
<>	144:ef7eb2e8f9f7	525	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<>	144:ef7eb2e8f9f7	526
<>	144:ef7eb2e8f9f7	527	/* Enable the Main Ouput */
<>	144:ef7eb2e8f9f7	528	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	529
<>	144:ef7eb2e8f9f7	530	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	531	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	532
<>	144:ef7eb2e8f9f7	533	/* Return function status */
<>	144:ef7eb2e8f9f7	534	return HAL_OK;
<>	144:ef7eb2e8f9f7	535	}
<>	144:ef7eb2e8f9f7	536
<>	144:ef7eb2e8f9f7	537	/**
<>	144:ef7eb2e8f9f7	538	* @brief Stops the TIM Output Compare signal generation on the complementary
<>	144:ef7eb2e8f9f7	539	* output.
<>	144:ef7eb2e8f9f7	540	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	541	* @param Channel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	542	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	543	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	544	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	545	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	546	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	547	* @retval HAL status
<>	144:ef7eb2e8f9f7	548	*/
<>	144:ef7eb2e8f9f7	549	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	550	{
<>	144:ef7eb2e8f9f7	551	/* Check the parameters */
<>	144:ef7eb2e8f9f7	552	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	553
<>	144:ef7eb2e8f9f7	554	/* Disable the Capture compare channel N */
<>	144:ef7eb2e8f9f7	555	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<>	144:ef7eb2e8f9f7	556
<>	144:ef7eb2e8f9f7	557	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	558	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	559
<>	144:ef7eb2e8f9f7	560	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	561	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	562
<>	144:ef7eb2e8f9f7	563	/* Return function status */
<>	144:ef7eb2e8f9f7	564	return HAL_OK;
<>	144:ef7eb2e8f9f7	565	}
<>	144:ef7eb2e8f9f7	566
<>	144:ef7eb2e8f9f7	567	/**
<>	144:ef7eb2e8f9f7	568	* @brief Starts the TIM Output Compare signal generation in interrupt mode
<>	144:ef7eb2e8f9f7	569	* on the complementary output.
<>	144:ef7eb2e8f9f7	570	* @param htim: TIM OC handle
<>	144:ef7eb2e8f9f7	571	* @param Channel: TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	572	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	573	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	574	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	575	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	576	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	577	* @retval HAL status
<>	144:ef7eb2e8f9f7	578	*/
<>	144:ef7eb2e8f9f7	579	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	580	{
<>	144:ef7eb2e8f9f7	581	/* Check the parameters */
<>	144:ef7eb2e8f9f7	582	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	583
<>	144:ef7eb2e8f9f7	584	switch (Channel)
<>	144:ef7eb2e8f9f7	585	{
<>	144:ef7eb2e8f9f7	586	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	587	{
<>	144:ef7eb2e8f9f7	588	/* Enable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	589	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	590	}
<>	144:ef7eb2e8f9f7	591	break;
<>	144:ef7eb2e8f9f7	592
<>	144:ef7eb2e8f9f7	593	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	594	{
<>	144:ef7eb2e8f9f7	595	/* Enable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	596	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	597	}
<>	144:ef7eb2e8f9f7	598	break;
<>	144:ef7eb2e8f9f7	599
<>	144:ef7eb2e8f9f7	600	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	601	{
<>	144:ef7eb2e8f9f7	602	/* Enable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	603	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	604	}
<>	144:ef7eb2e8f9f7	605	break;
<>	144:ef7eb2e8f9f7	606
<>	144:ef7eb2e8f9f7	607	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	608	{
<>	144:ef7eb2e8f9f7	609	/* Enable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	610	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	611	}
<>	144:ef7eb2e8f9f7	612	break;
<>	144:ef7eb2e8f9f7	613
<>	144:ef7eb2e8f9f7	614	default:
<>	144:ef7eb2e8f9f7	615	break;
<>	144:ef7eb2e8f9f7	616	}
<>	144:ef7eb2e8f9f7	617
<>	144:ef7eb2e8f9f7	618	/* Enable the TIM Break interrupt */
<>	144:ef7eb2e8f9f7	619	__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<>	144:ef7eb2e8f9f7	620
<>	144:ef7eb2e8f9f7	621	/* Enable the Capture compare channel N */
<>	144:ef7eb2e8f9f7	622	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<>	144:ef7eb2e8f9f7	623
<>	144:ef7eb2e8f9f7	624	/* Enable the Main Ouput */
<>	144:ef7eb2e8f9f7	625	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	626
<>	144:ef7eb2e8f9f7	627	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	628	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	629
<>	144:ef7eb2e8f9f7	630	/* Return function status */
<>	144:ef7eb2e8f9f7	631	return HAL_OK;
<>	144:ef7eb2e8f9f7	632	}
<>	144:ef7eb2e8f9f7	633
<>	144:ef7eb2e8f9f7	634	/**
<>	144:ef7eb2e8f9f7	635	* @brief Stops the TIM Output Compare signal generation in interrupt mode
<>	144:ef7eb2e8f9f7	636	* on the complementary output.
<>	144:ef7eb2e8f9f7	637	* @param htim: TIM Output Compare handle
<>	144:ef7eb2e8f9f7	638	* @param Channel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	639	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	640	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	641	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	642	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	643	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	644	* @retval HAL status
<>	144:ef7eb2e8f9f7	645	*/
<>	144:ef7eb2e8f9f7	646	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	647	{
<>	144:ef7eb2e8f9f7	648	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	649
<>	144:ef7eb2e8f9f7	650	/* Check the parameters */
<>	144:ef7eb2e8f9f7	651	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	switch (Channel)
<>	144:ef7eb2e8f9f7	654	{
<>	144:ef7eb2e8f9f7	655	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	656	{
<>	144:ef7eb2e8f9f7	657	/* Disable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	658	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	659	}
<>	144:ef7eb2e8f9f7	660	break;
<>	144:ef7eb2e8f9f7	661
<>	144:ef7eb2e8f9f7	662	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	663	{
<>	144:ef7eb2e8f9f7	664	/* Disable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	665	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	666	}
<>	144:ef7eb2e8f9f7	667	break;
<>	144:ef7eb2e8f9f7	668
<>	144:ef7eb2e8f9f7	669	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	670	{
<>	144:ef7eb2e8f9f7	671	/* Disable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	672	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	673	}
<>	144:ef7eb2e8f9f7	674	break;
<>	144:ef7eb2e8f9f7	675
<>	144:ef7eb2e8f9f7	676	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	677	{
<>	144:ef7eb2e8f9f7	678	/* Disable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	679	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	680	}
<>	144:ef7eb2e8f9f7	681	break;
<>	144:ef7eb2e8f9f7	682
<>	144:ef7eb2e8f9f7	683	default:
<>	144:ef7eb2e8f9f7	684	break;
<>	144:ef7eb2e8f9f7	685	}
<>	144:ef7eb2e8f9f7	686
<>	144:ef7eb2e8f9f7	687	/* Disable the Capture compare channel N */
<>	144:ef7eb2e8f9f7	688	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	/* Disable the TIM Break interrupt (only if no more channel is active) */
<>	144:ef7eb2e8f9f7	691	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	692	if ((tmpccer & (TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE)) == RESET)
<>	144:ef7eb2e8f9f7	693	{
<>	144:ef7eb2e8f9f7	694	__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<>	144:ef7eb2e8f9f7	695	}
<>	144:ef7eb2e8f9f7	696
<>	144:ef7eb2e8f9f7	697	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	698	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	699
<>	144:ef7eb2e8f9f7	700	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	701	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	702
<>	144:ef7eb2e8f9f7	703	/* Return function status */
<>	144:ef7eb2e8f9f7	704	return HAL_OK;
<>	144:ef7eb2e8f9f7	705	}
<>	144:ef7eb2e8f9f7	706
<>	144:ef7eb2e8f9f7	707	/**
<>	144:ef7eb2e8f9f7	708	* @brief Starts the TIM Output Compare signal generation in DMA mode
<>	144:ef7eb2e8f9f7	709	* on the complementary output.
<>	144:ef7eb2e8f9f7	710	* @param htim: TIM Output Compare handle
<>	144:ef7eb2e8f9f7	711	* @param Channel: TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	712	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	713	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	714	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	715	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	716	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	717	* @param pData: The source Buffer address.
<>	144:ef7eb2e8f9f7	718	* @param Length: The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	719	* @retval HAL status
<>	144:ef7eb2e8f9f7	720	*/
<>	144:ef7eb2e8f9f7	721	HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	722	{
<>	144:ef7eb2e8f9f7	723	/* Check the parameters */
<>	144:ef7eb2e8f9f7	724	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	725
<>	144:ef7eb2e8f9f7	726	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	727	{
<>	144:ef7eb2e8f9f7	728	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	729	}
<>	144:ef7eb2e8f9f7	730	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	731	{
<>	144:ef7eb2e8f9f7	732	if(((uint32_t)pData == 0 ) && (Length > 0))
<>	144:ef7eb2e8f9f7	733	{
<>	144:ef7eb2e8f9f7	734	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	735	}
<>	144:ef7eb2e8f9f7	736	else
<>	144:ef7eb2e8f9f7	737	{
<>	144:ef7eb2e8f9f7	738	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	739	}
<>	144:ef7eb2e8f9f7	740	}
<>	144:ef7eb2e8f9f7	741	switch (Channel)
<>	144:ef7eb2e8f9f7	742	{
<>	144:ef7eb2e8f9f7	743	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	744	{
<>	144:ef7eb2e8f9f7	745	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	746	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	747
<>	144:ef7eb2e8f9f7	748	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	749	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	750
<>	144:ef7eb2e8f9f7	751	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	752	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	753
<>	144:ef7eb2e8f9f7	754	/* Enable the TIM Output Compare DMA request */
<>	144:ef7eb2e8f9f7	755	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	756	}
<>	144:ef7eb2e8f9f7	757	break;
<>	144:ef7eb2e8f9f7	758
<>	144:ef7eb2e8f9f7	759	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	760	{
<>	144:ef7eb2e8f9f7	761	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	762	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	763
<>	144:ef7eb2e8f9f7	764	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	765	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	768	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	769
<>	144:ef7eb2e8f9f7	770	/* Enable the TIM Output Compare DMA request */
<>	144:ef7eb2e8f9f7	771	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	772	}
<>	144:ef7eb2e8f9f7	773	break;
<>	144:ef7eb2e8f9f7	774
<>	144:ef7eb2e8f9f7	775	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	776	{
<>	144:ef7eb2e8f9f7	777	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	778	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	779
<>	144:ef7eb2e8f9f7	780	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	781	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	782
<>	144:ef7eb2e8f9f7	783	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	784	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	785
<>	144:ef7eb2e8f9f7	786	/* Enable the TIM Output Compare DMA request */
<>	144:ef7eb2e8f9f7	787	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	788	}
<>	144:ef7eb2e8f9f7	789	break;
<>	144:ef7eb2e8f9f7	790
<>	144:ef7eb2e8f9f7	791	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	792	{
<>	144:ef7eb2e8f9f7	793	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	794	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	797	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	798
<>	144:ef7eb2e8f9f7	799	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	800	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	801
<>	144:ef7eb2e8f9f7	802	/* Enable the TIM Output Compare DMA request */
<>	144:ef7eb2e8f9f7	803	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	804	}
<>	144:ef7eb2e8f9f7	805	break;
<>	144:ef7eb2e8f9f7	806
<>	144:ef7eb2e8f9f7	807	default:
<>	144:ef7eb2e8f9f7	808	break;
<>	144:ef7eb2e8f9f7	809	}
<>	144:ef7eb2e8f9f7	810
<>	144:ef7eb2e8f9f7	811	/* Enable the Capture compare channel N */
<>	144:ef7eb2e8f9f7	812	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<>	144:ef7eb2e8f9f7	813
<>	144:ef7eb2e8f9f7	814	/* Enable the Main Ouput */
<>	144:ef7eb2e8f9f7	815	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	818	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	819
<>	144:ef7eb2e8f9f7	820	/* Return function status */
<>	144:ef7eb2e8f9f7	821	return HAL_OK;
<>	144:ef7eb2e8f9f7	822	}
<>	144:ef7eb2e8f9f7	823
<>	144:ef7eb2e8f9f7	824	/**
<>	144:ef7eb2e8f9f7	825	* @brief Stops the TIM Output Compare signal generation in DMA mode
<>	144:ef7eb2e8f9f7	826	* on the complementary output.
<>	144:ef7eb2e8f9f7	827	* @param htim: TIM Output Compare handle
<>	144:ef7eb2e8f9f7	828	* @param Channel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	829	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	830	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	831	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	832	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	833	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	834	* @retval HAL status
<>	144:ef7eb2e8f9f7	835	*/
<>	144:ef7eb2e8f9f7	836	HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	837	{
<>	144:ef7eb2e8f9f7	838	/* Check the parameters */
<>	144:ef7eb2e8f9f7	839	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	840
<>	144:ef7eb2e8f9f7	841	switch (Channel)
<>	144:ef7eb2e8f9f7	842	{
<>	144:ef7eb2e8f9f7	843	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	844	{
<>	144:ef7eb2e8f9f7	845	/* Disable the TIM Output Compare DMA request */
<>	144:ef7eb2e8f9f7	846	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	847	}
<>	144:ef7eb2e8f9f7	848	break;
<>	144:ef7eb2e8f9f7	849
<>	144:ef7eb2e8f9f7	850	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	851	{
<>	144:ef7eb2e8f9f7	852	/* Disable the TIM Output Compare DMA request */
<>	144:ef7eb2e8f9f7	853	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	854	}
<>	144:ef7eb2e8f9f7	855	break;
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	858	{
<>	144:ef7eb2e8f9f7	859	/* Disable the TIM Output Compare DMA request */
<>	144:ef7eb2e8f9f7	860	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	861	}
<>	144:ef7eb2e8f9f7	862	break;
<>	144:ef7eb2e8f9f7	863
<>	144:ef7eb2e8f9f7	864	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	865	{
<>	144:ef7eb2e8f9f7	866	/* Disable the TIM Output Compare interrupt */
<>	144:ef7eb2e8f9f7	867	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	868	}
<>	144:ef7eb2e8f9f7	869	break;
<>	144:ef7eb2e8f9f7	870
<>	144:ef7eb2e8f9f7	871	default:
<>	144:ef7eb2e8f9f7	872	break;
<>	144:ef7eb2e8f9f7	873	}
<>	144:ef7eb2e8f9f7	874
<>	144:ef7eb2e8f9f7	875	/* Disable the Capture compare channel N */
<>	144:ef7eb2e8f9f7	876	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<>	144:ef7eb2e8f9f7	877
<>	144:ef7eb2e8f9f7	878	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	879	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	880
<>	144:ef7eb2e8f9f7	881	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	882	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	883
<>	144:ef7eb2e8f9f7	884	/* Change the htim state */
<>	144:ef7eb2e8f9f7	885	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	886
<>	144:ef7eb2e8f9f7	887	/* Return function status */
<>	144:ef7eb2e8f9f7	888	return HAL_OK;
<>	144:ef7eb2e8f9f7	889	}
<>	144:ef7eb2e8f9f7	890
<>	144:ef7eb2e8f9f7	891	/**
<>	144:ef7eb2e8f9f7	892	* @}
<>	144:ef7eb2e8f9f7	893	*/
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	/** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
<>	144:ef7eb2e8f9f7	896	* @brief Timer Complementary PWM functions
<>	144:ef7eb2e8f9f7	897	*
<>	144:ef7eb2e8f9f7	898	@verbatim
<>	144:ef7eb2e8f9f7	899	==============================================================================
<>	144:ef7eb2e8f9f7	900	##### Timer Complementary PWM functions #####
<>	144:ef7eb2e8f9f7	901	==============================================================================
<>	144:ef7eb2e8f9f7	902	[..]
<>	144:ef7eb2e8f9f7	903	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	904	(+) Start the Complementary PWM.
<>	144:ef7eb2e8f9f7	905	(+) Stop the Complementary PWM.
<>	144:ef7eb2e8f9f7	906	(+) Start the Complementary PWM and enable interrupts.
<>	144:ef7eb2e8f9f7	907	(+) Stop the Complementary PWM and disable interrupts.
<>	144:ef7eb2e8f9f7	908	(+) Start the Complementary PWM and enable DMA transfers.
<>	144:ef7eb2e8f9f7	909	(+) Stop the Complementary PWM and disable DMA transfers.
<>	144:ef7eb2e8f9f7	910	(+) Start the Complementary Input Capture measurement.
<>	144:ef7eb2e8f9f7	911	(+) Stop the Complementary Input Capture.
<>	144:ef7eb2e8f9f7	912	(+) Start the Complementary Input Capture and enable interrupts.
<>	144:ef7eb2e8f9f7	913	(+) Stop the Complementary Input Capture and disable interrupts.
<>	144:ef7eb2e8f9f7	914	(+) Start the Complementary Input Capture and enable DMA transfers.
<>	144:ef7eb2e8f9f7	915	(+) Stop the Complementary Input Capture and disable DMA transfers.
<>	144:ef7eb2e8f9f7	916	(+) Start the Complementary One Pulse generation.
<>	144:ef7eb2e8f9f7	917	(+) Stop the Complementary One Pulse.
<>	144:ef7eb2e8f9f7	918	(+) Start the Complementary One Pulse and enable interrupts.
<>	144:ef7eb2e8f9f7	919	(+) Stop the Complementary One Pulse and disable interrupts.
<>	144:ef7eb2e8f9f7	920
<>	144:ef7eb2e8f9f7	921	@endverbatim
<>	144:ef7eb2e8f9f7	922	* @{
<>	144:ef7eb2e8f9f7	923	*/
<>	144:ef7eb2e8f9f7	924
<>	144:ef7eb2e8f9f7	925	/**
<>	144:ef7eb2e8f9f7	926	* @brief Starts the PWM signal generation on the complementary output.
<>	144:ef7eb2e8f9f7	927	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	928	* @param Channel: TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	929	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	930	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	931	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	932	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	933	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	934	* @retval HAL status
<>	144:ef7eb2e8f9f7	935	*/
<>	144:ef7eb2e8f9f7	936	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	937	{
<>	144:ef7eb2e8f9f7	938	/* Check the parameters */
<>	144:ef7eb2e8f9f7	939	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	940
<>	144:ef7eb2e8f9f7	941	/* Enable the complementary PWM output */
<>	144:ef7eb2e8f9f7	942	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<>	144:ef7eb2e8f9f7	943
<>	144:ef7eb2e8f9f7	944	/* Enable the Main Ouput */
<>	144:ef7eb2e8f9f7	945	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	946
<>	144:ef7eb2e8f9f7	947	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	948	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	/* Return function status */
<>	144:ef7eb2e8f9f7	951	return HAL_OK;
<>	144:ef7eb2e8f9f7	952	}
<>	144:ef7eb2e8f9f7	953
<>	144:ef7eb2e8f9f7	954	/**
<>	144:ef7eb2e8f9f7	955	* @brief Stops the PWM signal generation on the complementary output.
<>	144:ef7eb2e8f9f7	956	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	957	* @param Channel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	958	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	959	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	960	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	961	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	962	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	963	* @retval HAL status
<>	144:ef7eb2e8f9f7	964	*/
<>	144:ef7eb2e8f9f7	965	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	966	{
<>	144:ef7eb2e8f9f7	967	/* Check the parameters */
<>	144:ef7eb2e8f9f7	968	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	969
<>	144:ef7eb2e8f9f7	970	/* Disable the complementary PWM output */
<>	144:ef7eb2e8f9f7	971	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<>	144:ef7eb2e8f9f7	972
<>	144:ef7eb2e8f9f7	973	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	974	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	975
<>	144:ef7eb2e8f9f7	976	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	977	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	978
<>	144:ef7eb2e8f9f7	979	/* Return function status */
<>	144:ef7eb2e8f9f7	980	return HAL_OK;
<>	144:ef7eb2e8f9f7	981	}
<>	144:ef7eb2e8f9f7	982
<>	144:ef7eb2e8f9f7	983	/**
<>	144:ef7eb2e8f9f7	984	* @brief Starts the PWM signal generation in interrupt mode on the
<>	144:ef7eb2e8f9f7	985	* complementary output.
<>	144:ef7eb2e8f9f7	986	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	987	* @param Channel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	988	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	989	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	990	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	991	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	992	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	993	* @retval HAL status
<>	144:ef7eb2e8f9f7	994	*/
<>	144:ef7eb2e8f9f7	995	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	996	{
<>	144:ef7eb2e8f9f7	997	/* Check the parameters */
<>	144:ef7eb2e8f9f7	998	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	999
<>	144:ef7eb2e8f9f7	1000	switch (Channel)
<>	144:ef7eb2e8f9f7	1001	{
<>	144:ef7eb2e8f9f7	1002	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1003	{
<>	144:ef7eb2e8f9f7	1004	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1005	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1006	}
<>	144:ef7eb2e8f9f7	1007	break;
<>	144:ef7eb2e8f9f7	1008
<>	144:ef7eb2e8f9f7	1009	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1010	{
<>	144:ef7eb2e8f9f7	1011	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1012	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1013	}
<>	144:ef7eb2e8f9f7	1014	break;
<>	144:ef7eb2e8f9f7	1015
<>	144:ef7eb2e8f9f7	1016	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1017	{
<>	144:ef7eb2e8f9f7	1018	/* Enable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1019	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1020	}
<>	144:ef7eb2e8f9f7	1021	break;
<>	144:ef7eb2e8f9f7	1022
<>	144:ef7eb2e8f9f7	1023	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1024	{
<>	144:ef7eb2e8f9f7	1025	/* Enable the TIM Capture/Compare 4 interrupt */
<>	144:ef7eb2e8f9f7	1026	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1027	}
<>	144:ef7eb2e8f9f7	1028	break;
<>	144:ef7eb2e8f9f7	1029
<>	144:ef7eb2e8f9f7	1030	default:
<>	144:ef7eb2e8f9f7	1031	break;
<>	144:ef7eb2e8f9f7	1032	}
<>	144:ef7eb2e8f9f7	1033
<>	144:ef7eb2e8f9f7	1034	/* Enable the TIM Break interrupt */
<>	144:ef7eb2e8f9f7	1035	__HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<>	144:ef7eb2e8f9f7	1036
<>	144:ef7eb2e8f9f7	1037	/* Enable the complementary PWM output */
<>	144:ef7eb2e8f9f7	1038	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<>	144:ef7eb2e8f9f7	1039
<>	144:ef7eb2e8f9f7	1040	/* Enable the Main Ouput */
<>	144:ef7eb2e8f9f7	1041	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1042
<>	144:ef7eb2e8f9f7	1043	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1044	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1045
<>	144:ef7eb2e8f9f7	1046	/* Return function status */
<>	144:ef7eb2e8f9f7	1047	return HAL_OK;
<>	144:ef7eb2e8f9f7	1048	}
<>	144:ef7eb2e8f9f7	1049
<>	144:ef7eb2e8f9f7	1050	/**
<>	144:ef7eb2e8f9f7	1051	* @brief Stops the PWM signal generation in interrupt mode on the
<>	144:ef7eb2e8f9f7	1052	* complementary output.
<>	144:ef7eb2e8f9f7	1053	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	1054	* @param Channel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	1055	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1056	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1057	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1058	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1059	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1060	* @retval HAL status
<>	144:ef7eb2e8f9f7	1061	*/
<>	144:ef7eb2e8f9f7	1062	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1063	{
<>	144:ef7eb2e8f9f7	1064	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	1065
<>	144:ef7eb2e8f9f7	1066	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1067	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1068
<>	144:ef7eb2e8f9f7	1069	switch (Channel)
<>	144:ef7eb2e8f9f7	1070	{
<>	144:ef7eb2e8f9f7	1071	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1072	{
<>	144:ef7eb2e8f9f7	1073	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1074	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1075	}
<>	144:ef7eb2e8f9f7	1076	break;
<>	144:ef7eb2e8f9f7	1077
<>	144:ef7eb2e8f9f7	1078	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1079	{
<>	144:ef7eb2e8f9f7	1080	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1081	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1082	}
<>	144:ef7eb2e8f9f7	1083	break;
<>	144:ef7eb2e8f9f7	1084
<>	144:ef7eb2e8f9f7	1085	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1086	{
<>	144:ef7eb2e8f9f7	1087	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1088	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<>	144:ef7eb2e8f9f7	1089	}
<>	144:ef7eb2e8f9f7	1090	break;
<>	144:ef7eb2e8f9f7	1091
<>	144:ef7eb2e8f9f7	1092	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1093	{
<>	144:ef7eb2e8f9f7	1094	/* Disable the TIM Capture/Compare 3 interrupt */
<>	144:ef7eb2e8f9f7	1095	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<>	144:ef7eb2e8f9f7	1096	}
<>	144:ef7eb2e8f9f7	1097	break;
<>	144:ef7eb2e8f9f7	1098
<>	144:ef7eb2e8f9f7	1099	default:
<>	144:ef7eb2e8f9f7	1100	break;
<>	144:ef7eb2e8f9f7	1101	}
<>	144:ef7eb2e8f9f7	1102
<>	144:ef7eb2e8f9f7	1103	/* Disable the complementary PWM output */
<>	144:ef7eb2e8f9f7	1104	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<>	144:ef7eb2e8f9f7	1105
<>	144:ef7eb2e8f9f7	1106	/* Disable the TIM Break interrupt (only if no more channel is active) */
<>	144:ef7eb2e8f9f7	1107	tmpccer = htim->Instance->CCER;
<>	144:ef7eb2e8f9f7	1108	if ((tmpccer & (TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE)) == RESET)
<>	144:ef7eb2e8f9f7	1109	{
<>	144:ef7eb2e8f9f7	1110	__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<>	144:ef7eb2e8f9f7	1111	}
<>	144:ef7eb2e8f9f7	1112
<>	144:ef7eb2e8f9f7	1113	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1114	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1115
<>	144:ef7eb2e8f9f7	1116	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1117	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1118
<>	144:ef7eb2e8f9f7	1119	/* Return function status */
<>	144:ef7eb2e8f9f7	1120	return HAL_OK;
<>	144:ef7eb2e8f9f7	1121	}
<>	144:ef7eb2e8f9f7	1122
<>	144:ef7eb2e8f9f7	1123	/**
<>	144:ef7eb2e8f9f7	1124	* @brief Starts the TIM PWM signal generation in DMA mode on the
<>	144:ef7eb2e8f9f7	1125	* complementary output
<>	144:ef7eb2e8f9f7	1126	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	1127	* @param Channel: TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	1128	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1129	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1130	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1131	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1132	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1133	* @param pData: The source Buffer address.
<>	144:ef7eb2e8f9f7	1134	* @param Length: The length of data to be transferred from memory to TIM peripheral
<>	144:ef7eb2e8f9f7	1135	* @retval HAL status
<>	144:ef7eb2e8f9f7	1136	*/
<>	144:ef7eb2e8f9f7	1137	HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length)
<>	144:ef7eb2e8f9f7	1138	{
<>	144:ef7eb2e8f9f7	1139	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1140	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1141
<>	144:ef7eb2e8f9f7	1142	if((htim->State == HAL_TIM_STATE_BUSY))
<>	144:ef7eb2e8f9f7	1143	{
<>	144:ef7eb2e8f9f7	1144	return HAL_BUSY;
<>	144:ef7eb2e8f9f7	1145	}
<>	144:ef7eb2e8f9f7	1146	else if((htim->State == HAL_TIM_STATE_READY))
<>	144:ef7eb2e8f9f7	1147	{
<>	144:ef7eb2e8f9f7	1148	if(((uint32_t)pData == 0 ) && (Length > 0))
<>	144:ef7eb2e8f9f7	1149	{
<>	144:ef7eb2e8f9f7	1150	return HAL_ERROR;
<>	144:ef7eb2e8f9f7	1151	}
<>	144:ef7eb2e8f9f7	1152	else
<>	144:ef7eb2e8f9f7	1153	{
<>	144:ef7eb2e8f9f7	1154	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1155	}
<>	144:ef7eb2e8f9f7	1156	}
<>	144:ef7eb2e8f9f7	1157	switch (Channel)
<>	144:ef7eb2e8f9f7	1158	{
<>	144:ef7eb2e8f9f7	1159	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1160	{
<>	144:ef7eb2e8f9f7	1161	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1162	htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1163
<>	144:ef7eb2e8f9f7	1164	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1165	htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1166
<>	144:ef7eb2e8f9f7	1167	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1168	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/* Enable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1171	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1172	}
<>	144:ef7eb2e8f9f7	1173	break;
<>	144:ef7eb2e8f9f7	1174
<>	144:ef7eb2e8f9f7	1175	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1176	{
<>	144:ef7eb2e8f9f7	1177	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1178	htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1179
<>	144:ef7eb2e8f9f7	1180	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1181	htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1182
<>	144:ef7eb2e8f9f7	1183	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1184	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	/* Enable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1187	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1188	}
<>	144:ef7eb2e8f9f7	1189	break;
<>	144:ef7eb2e8f9f7	1190
<>	144:ef7eb2e8f9f7	1191	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1192	{
<>	144:ef7eb2e8f9f7	1193	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1194	htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1195
<>	144:ef7eb2e8f9f7	1196	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1197	htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1198
<>	144:ef7eb2e8f9f7	1199	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1200	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<>	144:ef7eb2e8f9f7	1201
<>	144:ef7eb2e8f9f7	1202	/* Enable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1203	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1204	}
<>	144:ef7eb2e8f9f7	1205	break;
<>	144:ef7eb2e8f9f7	1206
<>	144:ef7eb2e8f9f7	1207	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1208	{
<>	144:ef7eb2e8f9f7	1209	/* Set the DMA Period elapsed callback */
<>	144:ef7eb2e8f9f7	1210	htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<>	144:ef7eb2e8f9f7	1211
<>	144:ef7eb2e8f9f7	1212	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1213	htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<>	144:ef7eb2e8f9f7	1214
<>	144:ef7eb2e8f9f7	1215	/* Enable the DMA channel */
<>	144:ef7eb2e8f9f7	1216	HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<>	144:ef7eb2e8f9f7	1217
<>	144:ef7eb2e8f9f7	1218	/* Enable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1219	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1220	}
<>	144:ef7eb2e8f9f7	1221	break;
<>	144:ef7eb2e8f9f7	1222
<>	144:ef7eb2e8f9f7	1223	default:
<>	144:ef7eb2e8f9f7	1224	break;
<>	144:ef7eb2e8f9f7	1225	}
<>	144:ef7eb2e8f9f7	1226
<>	144:ef7eb2e8f9f7	1227	/* Enable the complementary PWM output */
<>	144:ef7eb2e8f9f7	1228	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<>	144:ef7eb2e8f9f7	1229
<>	144:ef7eb2e8f9f7	1230	/* Enable the Main Ouput */
<>	144:ef7eb2e8f9f7	1231	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1232
<>	144:ef7eb2e8f9f7	1233	/* Enable the Peripheral */
<>	144:ef7eb2e8f9f7	1234	__HAL_TIM_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1235
<>	144:ef7eb2e8f9f7	1236	/* Return function status */
<>	144:ef7eb2e8f9f7	1237	return HAL_OK;
<>	144:ef7eb2e8f9f7	1238	}
<>	144:ef7eb2e8f9f7	1239
<>	144:ef7eb2e8f9f7	1240	/**
<>	144:ef7eb2e8f9f7	1241	* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<>	144:ef7eb2e8f9f7	1242	* output
<>	144:ef7eb2e8f9f7	1243	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	1244	* @param Channel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	1245	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1246	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1247	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1248	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1249	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1250	* @retval HAL status
<>	144:ef7eb2e8f9f7	1251	*/
<>	144:ef7eb2e8f9f7	1252	HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<>	144:ef7eb2e8f9f7	1253	{
<>	144:ef7eb2e8f9f7	1254	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1255	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<>	144:ef7eb2e8f9f7	1256
<>	144:ef7eb2e8f9f7	1257	switch (Channel)
<>	144:ef7eb2e8f9f7	1258	{
<>	144:ef7eb2e8f9f7	1259	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1260	{
<>	144:ef7eb2e8f9f7	1261	/* Disable the TIM Capture/Compare 1 DMA request */
<>	144:ef7eb2e8f9f7	1262	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<>	144:ef7eb2e8f9f7	1263	}
<>	144:ef7eb2e8f9f7	1264	break;
<>	144:ef7eb2e8f9f7	1265
<>	144:ef7eb2e8f9f7	1266	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1267	{
<>	144:ef7eb2e8f9f7	1268	/* Disable the TIM Capture/Compare 2 DMA request */
<>	144:ef7eb2e8f9f7	1269	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<>	144:ef7eb2e8f9f7	1270	}
<>	144:ef7eb2e8f9f7	1271	break;
<>	144:ef7eb2e8f9f7	1272
<>	144:ef7eb2e8f9f7	1273	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1274	{
<>	144:ef7eb2e8f9f7	1275	/* Disable the TIM Capture/Compare 3 DMA request */
<>	144:ef7eb2e8f9f7	1276	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<>	144:ef7eb2e8f9f7	1277	}
<>	144:ef7eb2e8f9f7	1278	break;
<>	144:ef7eb2e8f9f7	1279
<>	144:ef7eb2e8f9f7	1280	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1281	{
<>	144:ef7eb2e8f9f7	1282	/* Disable the TIM Capture/Compare 4 DMA request */
<>	144:ef7eb2e8f9f7	1283	__HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<>	144:ef7eb2e8f9f7	1284	}
<>	144:ef7eb2e8f9f7	1285	break;
<>	144:ef7eb2e8f9f7	1286
<>	144:ef7eb2e8f9f7	1287	default:
<>	144:ef7eb2e8f9f7	1288	break;
<>	144:ef7eb2e8f9f7	1289	}
<>	144:ef7eb2e8f9f7	1290
<>	144:ef7eb2e8f9f7	1291	/* Disable the complementary PWM output */
<>	144:ef7eb2e8f9f7	1292	TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<>	144:ef7eb2e8f9f7	1293
<>	144:ef7eb2e8f9f7	1294	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1295	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1296
<>	144:ef7eb2e8f9f7	1297	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1298	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	/* Change the htim state */
<>	144:ef7eb2e8f9f7	1301	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1302
<>	144:ef7eb2e8f9f7	1303	/* Return function status */
<>	144:ef7eb2e8f9f7	1304	return HAL_OK;
<>	144:ef7eb2e8f9f7	1305	}
<>	144:ef7eb2e8f9f7	1306
<>	144:ef7eb2e8f9f7	1307	/**
<>	144:ef7eb2e8f9f7	1308	* @}
<>	144:ef7eb2e8f9f7	1309	*/
<>	144:ef7eb2e8f9f7	1310
<>	144:ef7eb2e8f9f7	1311	/** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
<>	144:ef7eb2e8f9f7	1312	* @brief Timer Complementary One Pulse functions
<>	144:ef7eb2e8f9f7	1313	*
<>	144:ef7eb2e8f9f7	1314	@verbatim
<>	144:ef7eb2e8f9f7	1315	==============================================================================
<>	144:ef7eb2e8f9f7	1316	##### Timer Complementary One Pulse functions #####
<>	144:ef7eb2e8f9f7	1317	==============================================================================
<>	144:ef7eb2e8f9f7	1318	[..]
<>	144:ef7eb2e8f9f7	1319	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1320	(+) Start the Complementary One Pulse generation.
<>	144:ef7eb2e8f9f7	1321	(+) Stop the Complementary One Pulse.
<>	144:ef7eb2e8f9f7	1322	(+) Start the Complementary One Pulse and enable interrupts.
<>	144:ef7eb2e8f9f7	1323	(+) Stop the Complementary One Pulse and disable interrupts.
<>	144:ef7eb2e8f9f7	1324
<>	144:ef7eb2e8f9f7	1325	@endverbatim
<>	144:ef7eb2e8f9f7	1326	* @{
<>	144:ef7eb2e8f9f7	1327	*/
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	/**
<>	144:ef7eb2e8f9f7	1330	* @brief Starts the TIM One Pulse signal generation on the complemetary
<>	144:ef7eb2e8f9f7	1331	* output.
<>	144:ef7eb2e8f9f7	1332	* @param htim: TIM One Pulse handle
<>	144:ef7eb2e8f9f7	1333	* @param OutputChannel: TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	1334	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1335	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1336	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1337	* @retval HAL status
<>	144:ef7eb2e8f9f7	1338	*/
<>	144:ef7eb2e8f9f7	1339	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	1340	{
<>	144:ef7eb2e8f9f7	1341	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1342	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<>	144:ef7eb2e8f9f7	1343
<>	144:ef7eb2e8f9f7	1344	/* Enable the complementary One Pulse output */
<>	144:ef7eb2e8f9f7	1345	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<>	144:ef7eb2e8f9f7	1346
<>	144:ef7eb2e8f9f7	1347	/* Enable the Main Ouput */
<>	144:ef7eb2e8f9f7	1348	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	/* Return function status */
<>	144:ef7eb2e8f9f7	1351	return HAL_OK;
<>	144:ef7eb2e8f9f7	1352	}
<>	144:ef7eb2e8f9f7	1353
<>	144:ef7eb2e8f9f7	1354	/**
<>	144:ef7eb2e8f9f7	1355	* @brief Stops the TIM One Pulse signal generation on the complementary
<>	144:ef7eb2e8f9f7	1356	* output.
<>	144:ef7eb2e8f9f7	1357	* @param htim: TIM One Pulse handle
<>	144:ef7eb2e8f9f7	1358	* @param OutputChannel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	1359	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1360	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1361	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1362	* @retval HAL status
<>	144:ef7eb2e8f9f7	1363	*/
<>	144:ef7eb2e8f9f7	1364	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	1365	{
<>	144:ef7eb2e8f9f7	1366
<>	144:ef7eb2e8f9f7	1367	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1368	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<>	144:ef7eb2e8f9f7	1369
<>	144:ef7eb2e8f9f7	1370	/* Disable the complementary One Pulse output */
<>	144:ef7eb2e8f9f7	1371	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<>	144:ef7eb2e8f9f7	1372
<>	144:ef7eb2e8f9f7	1373	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1374	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1375
<>	144:ef7eb2e8f9f7	1376	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1377	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1378
<>	144:ef7eb2e8f9f7	1379	/* Return function status */
<>	144:ef7eb2e8f9f7	1380	return HAL_OK;
<>	144:ef7eb2e8f9f7	1381	}
<>	144:ef7eb2e8f9f7	1382
<>	144:ef7eb2e8f9f7	1383	/**
<>	144:ef7eb2e8f9f7	1384	* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<>	144:ef7eb2e8f9f7	1385	* complementary channel.
<>	144:ef7eb2e8f9f7	1386	* @param htim: TIM One Pulse handle
<>	144:ef7eb2e8f9f7	1387	* @param OutputChannel: TIM Channel to be enabled
<>	144:ef7eb2e8f9f7	1388	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1389	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1390	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1391	* @retval HAL status
<>	144:ef7eb2e8f9f7	1392	*/
<>	144:ef7eb2e8f9f7	1393	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	1394	{
<>	144:ef7eb2e8f9f7	1395	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1396	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<>	144:ef7eb2e8f9f7	1397
<>	144:ef7eb2e8f9f7	1398	/* Enable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1399	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1400
<>	144:ef7eb2e8f9f7	1401	/* Enable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1402	__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1403
<>	144:ef7eb2e8f9f7	1404	/* Enable the complementary One Pulse output */
<>	144:ef7eb2e8f9f7	1405	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<>	144:ef7eb2e8f9f7	1406
<>	144:ef7eb2e8f9f7	1407	/* Enable the Main Ouput */
<>	144:ef7eb2e8f9f7	1408	__HAL_TIM_MOE_ENABLE(htim);
<>	144:ef7eb2e8f9f7	1409
<>	144:ef7eb2e8f9f7	1410	/* Return function status */
<>	144:ef7eb2e8f9f7	1411	return HAL_OK;
<>	144:ef7eb2e8f9f7	1412	}
<>	144:ef7eb2e8f9f7	1413
<>	144:ef7eb2e8f9f7	1414	/**
<>	144:ef7eb2e8f9f7	1415	* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<>	144:ef7eb2e8f9f7	1416	* complementary channel.
<>	144:ef7eb2e8f9f7	1417	* @param htim: TIM One Pulse handle
<>	144:ef7eb2e8f9f7	1418	* @param OutputChannel: TIM Channel to be disabled
<>	144:ef7eb2e8f9f7	1419	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1420	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1421	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1422	* @retval HAL status
<>	144:ef7eb2e8f9f7	1423	*/
<>	144:ef7eb2e8f9f7	1424	HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<>	144:ef7eb2e8f9f7	1425	{
<>	144:ef7eb2e8f9f7	1426	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1427	assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<>	144:ef7eb2e8f9f7	1428
<>	144:ef7eb2e8f9f7	1429	/* Disable the TIM Capture/Compare 1 interrupt */
<>	144:ef7eb2e8f9f7	1430	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<>	144:ef7eb2e8f9f7	1431
<>	144:ef7eb2e8f9f7	1432	/* Disable the TIM Capture/Compare 2 interrupt */
<>	144:ef7eb2e8f9f7	1433	__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<>	144:ef7eb2e8f9f7	1434
<>	144:ef7eb2e8f9f7	1435	/* Disable the complementary One Pulse output */
<>	144:ef7eb2e8f9f7	1436	TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<>	144:ef7eb2e8f9f7	1437
<>	144:ef7eb2e8f9f7	1438	/* Disable the Main Ouput */
<>	144:ef7eb2e8f9f7	1439	__HAL_TIM_MOE_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1440
<>	144:ef7eb2e8f9f7	1441	/* Disable the Peripheral */
<>	144:ef7eb2e8f9f7	1442	__HAL_TIM_DISABLE(htim);
<>	144:ef7eb2e8f9f7	1443
<>	144:ef7eb2e8f9f7	1444	/* Return function status */
<>	144:ef7eb2e8f9f7	1445	return HAL_OK;
<>	144:ef7eb2e8f9f7	1446	}
<>	144:ef7eb2e8f9f7	1447
<>	144:ef7eb2e8f9f7	1448	/**
<>	144:ef7eb2e8f9f7	1449	* @}
<>	144:ef7eb2e8f9f7	1450	*/
<>	144:ef7eb2e8f9f7	1451	/** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1452	* @brief Peripheral Control functions
<>	144:ef7eb2e8f9f7	1453	*
<>	144:ef7eb2e8f9f7	1454	@verbatim
<>	144:ef7eb2e8f9f7	1455	==============================================================================
<>	144:ef7eb2e8f9f7	1456	##### Peripheral Control functions #####
<>	144:ef7eb2e8f9f7	1457	==============================================================================
<>	144:ef7eb2e8f9f7	1458	[..]
<>	144:ef7eb2e8f9f7	1459	This section provides functions allowing to:
<>	144:ef7eb2e8f9f7	1460	(+) Configure the commutation event in case of use of the Hall sensor interface.
<>	144:ef7eb2e8f9f7	1461	(+) Configure Output channels for OC and PWM mode.
<>	144:ef7eb2e8f9f7	1462
<>	144:ef7eb2e8f9f7	1463	(+) Configure Complementary channels, break features and dead time.
<>	144:ef7eb2e8f9f7	1464	(+) Configure Master synchronization.
<>	144:ef7eb2e8f9f7	1465	(+) Configure timer remapping capabilities.
<>	144:ef7eb2e8f9f7	1466	(+) Enable or disable channel grouping
<>	144:ef7eb2e8f9f7	1467
<>	144:ef7eb2e8f9f7	1468	@endverbatim
<>	144:ef7eb2e8f9f7	1469	* @{
<>	144:ef7eb2e8f9f7	1470	*/
<>	144:ef7eb2e8f9f7	1471	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	1472	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	1473	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	1474	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	1475	/**
<>	144:ef7eb2e8f9f7	1476	* @brief Configure the TIM commutation event sequence.
<>	144:ef7eb2e8f9f7	1477	* @note this function is mandatory to use the commutation event in order to
<>	144:ef7eb2e8f9f7	1478	* update the configuration at each commutation detection on the TRGI input of the Timer,
<>	144:ef7eb2e8f9f7	1479	* the typical use of this feature is with the use of another Timer(interface Timer)
<>	144:ef7eb2e8f9f7	1480	* configured in Hall sensor interface, this interface Timer will generate the
<>	144:ef7eb2e8f9f7	1481	* commutation at its TRGO output (connected to Timer used in this function) each time
<>	144:ef7eb2e8f9f7	1482	* the TI1 of the Interface Timer detect a commutation at its input TI1.
<>	144:ef7eb2e8f9f7	1483	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	1484	* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<>	144:ef7eb2e8f9f7	1485	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1486	* @arg TIM_TS_ITR0: Internal trigger 0 selected
<>	144:ef7eb2e8f9f7	1487	* @arg TIM_TS_ITR1: Internal trigger 1 selected
<>	144:ef7eb2e8f9f7	1488	* @arg TIM_TS_ITR2: Internal trigger 2 selected
<>	144:ef7eb2e8f9f7	1489	* @arg TIM_TS_ITR3: Internal trigger 3 selected
<>	144:ef7eb2e8f9f7	1490	* @arg TIM_TS_NONE: No trigger is needed
<>	144:ef7eb2e8f9f7	1491	* @param CommutationSource: the Commutation Event source
<>	144:ef7eb2e8f9f7	1492	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1493	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<>	144:ef7eb2e8f9f7	1494	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<>	144:ef7eb2e8f9f7	1495	* @retval HAL status
<>	144:ef7eb2e8f9f7	1496	*/
<>	144:ef7eb2e8f9f7	1497	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<>	144:ef7eb2e8f9f7	1498	{
<>	144:ef7eb2e8f9f7	1499	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1500	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1501	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<>	144:ef7eb2e8f9f7	1502
<>	144:ef7eb2e8f9f7	1503	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	1504
<>	144:ef7eb2e8f9f7	1505	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
<>	144:ef7eb2e8f9f7	1506	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
<>	144:ef7eb2e8f9f7	1507	{
<>	144:ef7eb2e8f9f7	1508	/* Select the Input trigger */
<>	144:ef7eb2e8f9f7	1509	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	1510	htim->Instance->SMCR \|= InputTrigger;
<>	144:ef7eb2e8f9f7	1511	}
<>	144:ef7eb2e8f9f7	1512
<>	144:ef7eb2e8f9f7	1513	/* Select the Capture Compare preload feature */
<>	144:ef7eb2e8f9f7	1514	htim->Instance->CR2 \|= TIM_CR2_CCPC;
<>	144:ef7eb2e8f9f7	1515	/* Select the Commutation event source */
<>	144:ef7eb2e8f9f7	1516	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<>	144:ef7eb2e8f9f7	1517	htim->Instance->CR2 \|= CommutationSource;
<>	144:ef7eb2e8f9f7	1518
<>	144:ef7eb2e8f9f7	1519	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1520
<>	144:ef7eb2e8f9f7	1521	return HAL_OK;
<>	144:ef7eb2e8f9f7	1522	}
<>	144:ef7eb2e8f9f7	1523
<>	144:ef7eb2e8f9f7	1524	/**
<>	144:ef7eb2e8f9f7	1525	* @brief Configure the TIM commutation event sequence with interrupt.
<>	144:ef7eb2e8f9f7	1526	* @note this function is mandatory to use the commutation event in order to
<>	144:ef7eb2e8f9f7	1527	* update the configuration at each commutation detection on the TRGI input of the Timer,
<>	144:ef7eb2e8f9f7	1528	* the typical use of this feature is with the use of another Timer(interface Timer)
<>	144:ef7eb2e8f9f7	1529	* configured in Hall sensor interface, this interface Timer will generate the
<>	144:ef7eb2e8f9f7	1530	* commutation at its TRGO output (connected to Timer used in this function) each time
<>	144:ef7eb2e8f9f7	1531	* the TI1 of the Interface Timer detect a commutation at its input TI1.
<>	144:ef7eb2e8f9f7	1532	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	1533	* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<>	144:ef7eb2e8f9f7	1534	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1535	* @arg TIM_TS_ITR0: Internal trigger 0 selected
<>	144:ef7eb2e8f9f7	1536	* @arg TIM_TS_ITR1: Internal trigger 1 selected
<>	144:ef7eb2e8f9f7	1537	* @arg TIM_TS_ITR2: Internal trigger 2 selected
<>	144:ef7eb2e8f9f7	1538	* @arg TIM_TS_ITR3: Internal trigger 3 selected
<>	144:ef7eb2e8f9f7	1539	* @arg TIM_TS_NONE: No trigger is needed
<>	144:ef7eb2e8f9f7	1540	* @param CommutationSource: the Commutation Event source
<>	144:ef7eb2e8f9f7	1541	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1542	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<>	144:ef7eb2e8f9f7	1543	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<>	144:ef7eb2e8f9f7	1544	* @retval HAL status
<>	144:ef7eb2e8f9f7	1545	*/
<>	144:ef7eb2e8f9f7	1546	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<>	144:ef7eb2e8f9f7	1547	{
<>	144:ef7eb2e8f9f7	1548	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1549	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1550	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<>	144:ef7eb2e8f9f7	1551
<>	144:ef7eb2e8f9f7	1552	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	1553
<>	144:ef7eb2e8f9f7	1554	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
<>	144:ef7eb2e8f9f7	1555	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
<>	144:ef7eb2e8f9f7	1556	{
<>	144:ef7eb2e8f9f7	1557	/* Select the Input trigger */
<>	144:ef7eb2e8f9f7	1558	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	1559	htim->Instance->SMCR \|= InputTrigger;
<>	144:ef7eb2e8f9f7	1560	}
<>	144:ef7eb2e8f9f7	1561
<>	144:ef7eb2e8f9f7	1562	/* Select the Capture Compare preload feature */
<>	144:ef7eb2e8f9f7	1563	htim->Instance->CR2 \|= TIM_CR2_CCPC;
<>	144:ef7eb2e8f9f7	1564	/* Select the Commutation event source */
<>	144:ef7eb2e8f9f7	1565	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<>	144:ef7eb2e8f9f7	1566	htim->Instance->CR2 \|= CommutationSource;
<>	144:ef7eb2e8f9f7	1567
<>	144:ef7eb2e8f9f7	1568	/* Enable the Commutation Interrupt Request */
<>	144:ef7eb2e8f9f7	1569	__HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<>	144:ef7eb2e8f9f7	1570
<>	144:ef7eb2e8f9f7	1571	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1572
<>	144:ef7eb2e8f9f7	1573	return HAL_OK;
<>	144:ef7eb2e8f9f7	1574	}
<>	144:ef7eb2e8f9f7	1575
<>	144:ef7eb2e8f9f7	1576	/**
<>	144:ef7eb2e8f9f7	1577	* @brief Configure the TIM commutation event sequence with DMA.
<>	144:ef7eb2e8f9f7	1578	* @note this function is mandatory to use the commutation event in order to
<>	144:ef7eb2e8f9f7	1579	* update the configuration at each commutation detection on the TRGI input of the Timer,
<>	144:ef7eb2e8f9f7	1580	* the typical use of this feature is with the use of another Timer(interface Timer)
<>	144:ef7eb2e8f9f7	1581	* configured in Hall sensor interface, this interface Timer will generate the
<>	144:ef7eb2e8f9f7	1582	* commutation at its TRGO output (connected to Timer used in this function) each time
<>	144:ef7eb2e8f9f7	1583	* the TI1 of the Interface Timer detect a commutation at its input TI1.
<>	144:ef7eb2e8f9f7	1584	* @note The user should configure the DMA in his own software, in This function only the COMDE bit is set
<>	144:ef7eb2e8f9f7	1585	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	1586	* @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor
<>	144:ef7eb2e8f9f7	1587	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1588	* @arg TIM_TS_ITR0: Internal trigger 0 selected
<>	144:ef7eb2e8f9f7	1589	* @arg TIM_TS_ITR1: Internal trigger 1 selected
<>	144:ef7eb2e8f9f7	1590	* @arg TIM_TS_ITR2: Internal trigger 2 selected
<>	144:ef7eb2e8f9f7	1591	* @arg TIM_TS_ITR3: Internal trigger 3 selected
<>	144:ef7eb2e8f9f7	1592	* @arg TIM_TS_NONE: No trigger is needed
<>	144:ef7eb2e8f9f7	1593	* @param CommutationSource: the Commutation Event source
<>	144:ef7eb2e8f9f7	1594	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1595	* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<>	144:ef7eb2e8f9f7	1596	* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<>	144:ef7eb2e8f9f7	1597	* @retval HAL status
<>	144:ef7eb2e8f9f7	1598	*/
<>	144:ef7eb2e8f9f7	1599	HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<>	144:ef7eb2e8f9f7	1600	{
<>	144:ef7eb2e8f9f7	1601	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1602	assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1603	assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<>	144:ef7eb2e8f9f7	1604
<>	144:ef7eb2e8f9f7	1605	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	1606
<>	144:ef7eb2e8f9f7	1607	if ((InputTrigger == TIM_TS_ITR0) \|\| (InputTrigger == TIM_TS_ITR1) \|\|
<>	144:ef7eb2e8f9f7	1608	(InputTrigger == TIM_TS_ITR2) \|\| (InputTrigger == TIM_TS_ITR3))
<>	144:ef7eb2e8f9f7	1609	{
<>	144:ef7eb2e8f9f7	1610	/* Select the Input trigger */
<>	144:ef7eb2e8f9f7	1611	htim->Instance->SMCR &= ~TIM_SMCR_TS;
<>	144:ef7eb2e8f9f7	1612	htim->Instance->SMCR \|= InputTrigger;
<>	144:ef7eb2e8f9f7	1613	}
<>	144:ef7eb2e8f9f7	1614
<>	144:ef7eb2e8f9f7	1615	/* Select the Capture Compare preload feature */
<>	144:ef7eb2e8f9f7	1616	htim->Instance->CR2 \|= TIM_CR2_CCPC;
<>	144:ef7eb2e8f9f7	1617	/* Select the Commutation event source */
<>	144:ef7eb2e8f9f7	1618	htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<>	144:ef7eb2e8f9f7	1619	htim->Instance->CR2 \|= CommutationSource;
<>	144:ef7eb2e8f9f7	1620
<>	144:ef7eb2e8f9f7	1621	/* Enable the Commutation DMA Request */
<>	144:ef7eb2e8f9f7	1622	/* Set the DMA Commutation Callback */
<>	144:ef7eb2e8f9f7	1623	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<>	144:ef7eb2e8f9f7	1624	/* Set the DMA error callback */
<>	144:ef7eb2e8f9f7	1625	htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<>	144:ef7eb2e8f9f7	1626
<>	144:ef7eb2e8f9f7	1627	/* Enable the Commutation DMA Request */
<>	144:ef7eb2e8f9f7	1628	__HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<>	144:ef7eb2e8f9f7	1629
<>	144:ef7eb2e8f9f7	1630	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1631
<>	144:ef7eb2e8f9f7	1632	return HAL_OK;
<>	144:ef7eb2e8f9f7	1633	}
<>	144:ef7eb2e8f9f7	1634
<>	144:ef7eb2e8f9f7	1635	/**
<>	144:ef7eb2e8f9f7	1636	* @brief Initializes the TIM Output Compare Channels according to the specified
<>	144:ef7eb2e8f9f7	1637	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	1638	* @param htim: TIM Output Compare handle
<>	144:ef7eb2e8f9f7	1639	* @param sConfig: TIM Output Compare configuration structure
<>	144:ef7eb2e8f9f7	1640	* @param Channel: TIM Channels to configure
<>	144:ef7eb2e8f9f7	1641	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1642	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1643	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1644	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1645	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1646	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
<>	144:ef7eb2e8f9f7	1647	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
<>	144:ef7eb2e8f9f7	1648	* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
<>	144:ef7eb2e8f9f7	1649	* STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
<>	144:ef7eb2e8f9f7	1650	* @retval HAL status
<>	144:ef7eb2e8f9f7	1651	*/
<>	144:ef7eb2e8f9f7	1652	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	1653	TIM_OC_InitTypeDef* sConfig,
<>	144:ef7eb2e8f9f7	1654	uint32_t Channel)
<>	144:ef7eb2e8f9f7	1655	{
<>	144:ef7eb2e8f9f7	1656	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1657	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	1658	assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	1659	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	1660
<>	144:ef7eb2e8f9f7	1661	/* Check input state */
<>	144:ef7eb2e8f9f7	1662	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	1663
<>	144:ef7eb2e8f9f7	1664	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1665
<>	144:ef7eb2e8f9f7	1666	switch (Channel)
<>	144:ef7eb2e8f9f7	1667	{
<>	144:ef7eb2e8f9f7	1668	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1669	{
<>	144:ef7eb2e8f9f7	1670	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1671	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1672
<>	144:ef7eb2e8f9f7	1673	/* Configure the TIM Channel 1 in Output Compare */
<>	144:ef7eb2e8f9f7	1674	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1675	}
<>	144:ef7eb2e8f9f7	1676	break;
<>	144:ef7eb2e8f9f7	1677
<>	144:ef7eb2e8f9f7	1678	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1679	{
<>	144:ef7eb2e8f9f7	1680	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1681	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1682
<>	144:ef7eb2e8f9f7	1683	/* Configure the TIM Channel 2 in Output Compare */
<>	144:ef7eb2e8f9f7	1684	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1685	}
<>	144:ef7eb2e8f9f7	1686	break;
<>	144:ef7eb2e8f9f7	1687
<>	144:ef7eb2e8f9f7	1688	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1689	{
<>	144:ef7eb2e8f9f7	1690	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1691	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1692
<>	144:ef7eb2e8f9f7	1693	/* Configure the TIM Channel 3 in Output Compare */
<>	144:ef7eb2e8f9f7	1694	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1695	}
<>	144:ef7eb2e8f9f7	1696	break;
<>	144:ef7eb2e8f9f7	1697
<>	144:ef7eb2e8f9f7	1698	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1699	{
<>	144:ef7eb2e8f9f7	1700	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1701	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1702
<>	144:ef7eb2e8f9f7	1703	/* Configure the TIM Channel 4 in Output Compare */
<>	144:ef7eb2e8f9f7	1704	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1705	}
<>	144:ef7eb2e8f9f7	1706	break;
<>	144:ef7eb2e8f9f7	1707
<>	144:ef7eb2e8f9f7	1708	case TIM_CHANNEL_5:
<>	144:ef7eb2e8f9f7	1709	{
<>	144:ef7eb2e8f9f7	1710	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1711	assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1712
<>	144:ef7eb2e8f9f7	1713	/* Configure the TIM Channel 5 in Output Compare */
<>	144:ef7eb2e8f9f7	1714	TIM_OC5_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1715	}
<>	144:ef7eb2e8f9f7	1716	break;
<>	144:ef7eb2e8f9f7	1717
<>	144:ef7eb2e8f9f7	1718	case TIM_CHANNEL_6:
<>	144:ef7eb2e8f9f7	1719	{
<>	144:ef7eb2e8f9f7	1720	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1721	assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1722
<>	144:ef7eb2e8f9f7	1723	/* Configure the TIM Channel 6 in Output Compare */
<>	144:ef7eb2e8f9f7	1724	TIM_OC6_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1725	}
<>	144:ef7eb2e8f9f7	1726	break;
<>	144:ef7eb2e8f9f7	1727
<>	144:ef7eb2e8f9f7	1728	default:
<>	144:ef7eb2e8f9f7	1729	break;
<>	144:ef7eb2e8f9f7	1730	}
<>	144:ef7eb2e8f9f7	1731
<>	144:ef7eb2e8f9f7	1732	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1733
<>	144:ef7eb2e8f9f7	1734	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1735
<>	144:ef7eb2e8f9f7	1736	return HAL_OK;
<>	144:ef7eb2e8f9f7	1737	}
<>	144:ef7eb2e8f9f7	1738
<>	144:ef7eb2e8f9f7	1739	/**
<>	144:ef7eb2e8f9f7	1740	* @brief Initializes the TIM PWM channels according to the specified
<>	144:ef7eb2e8f9f7	1741	* parameters in the TIM_OC_InitTypeDef.
<>	144:ef7eb2e8f9f7	1742	* @param htim: TIM PWM handle
<>	144:ef7eb2e8f9f7	1743	* @param sConfig: TIM PWM configuration structure
<>	144:ef7eb2e8f9f7	1744	* @param Channel: TIM Channels to be configured
<>	144:ef7eb2e8f9f7	1745	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	1746	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
<>	144:ef7eb2e8f9f7	1747	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
<>	144:ef7eb2e8f9f7	1748	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
<>	144:ef7eb2e8f9f7	1749	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
<>	144:ef7eb2e8f9f7	1750	* @arg TIM_CHANNEL_5: TIM Channel 5 selected
<>	144:ef7eb2e8f9f7	1751	* @arg TIM_CHANNEL_6: TIM Channel 6 selected
<>	144:ef7eb2e8f9f7	1752	* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
<>	144:ef7eb2e8f9f7	1753	* STM32F398xx and STM32F303x8 up to 6 PWM channels can be configured
<>	144:ef7eb2e8f9f7	1754	* @retval HAL status
<>	144:ef7eb2e8f9f7	1755	*/
<>	144:ef7eb2e8f9f7	1756	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	1757	TIM_OC_InitTypeDef* sConfig,
<>	144:ef7eb2e8f9f7	1758	uint32_t Channel)
<>	144:ef7eb2e8f9f7	1759	{
<>	144:ef7eb2e8f9f7	1760	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1761	assert_param(IS_TIM_CHANNELS(Channel));
<>	144:ef7eb2e8f9f7	1762	assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
<>	144:ef7eb2e8f9f7	1763	assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
<>	144:ef7eb2e8f9f7	1764	assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
<>	144:ef7eb2e8f9f7	1765
<>	144:ef7eb2e8f9f7	1766	/* Check input state */
<>	144:ef7eb2e8f9f7	1767	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	1768
<>	144:ef7eb2e8f9f7	1769	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1770
<>	144:ef7eb2e8f9f7	1771	switch (Channel)
<>	144:ef7eb2e8f9f7	1772	{
<>	144:ef7eb2e8f9f7	1773	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	1774	{
<>	144:ef7eb2e8f9f7	1775	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1776	assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1777
<>	144:ef7eb2e8f9f7	1778	/* Configure the Channel 1 in PWM mode */
<>	144:ef7eb2e8f9f7	1779	TIM_OC1_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1780
<>	144:ef7eb2e8f9f7	1781	/* Set the Preload enable bit for channel1 */
<>	144:ef7eb2e8f9f7	1782	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1PE;
<>	144:ef7eb2e8f9f7	1783
<>	144:ef7eb2e8f9f7	1784	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	1785	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
<>	144:ef7eb2e8f9f7	1786	htim->Instance->CCMR1 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	1787	}
<>	144:ef7eb2e8f9f7	1788	break;
<>	144:ef7eb2e8f9f7	1789
<>	144:ef7eb2e8f9f7	1790	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	1791	{
<>	144:ef7eb2e8f9f7	1792	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1793	assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1794
<>	144:ef7eb2e8f9f7	1795	/* Configure the Channel 2 in PWM mode */
<>	144:ef7eb2e8f9f7	1796	TIM_OC2_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1797
<>	144:ef7eb2e8f9f7	1798	/* Set the Preload enable bit for channel2 */
<>	144:ef7eb2e8f9f7	1799	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2PE;
<>	144:ef7eb2e8f9f7	1800
<>	144:ef7eb2e8f9f7	1801	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	1802	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
<>	144:ef7eb2e8f9f7	1803	htim->Instance->CCMR1 \|= sConfig->OCFastMode << 8;
<>	144:ef7eb2e8f9f7	1804	}
<>	144:ef7eb2e8f9f7	1805	break;
<>	144:ef7eb2e8f9f7	1806
<>	144:ef7eb2e8f9f7	1807	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	1808	{
<>	144:ef7eb2e8f9f7	1809	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1810	assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1811
<>	144:ef7eb2e8f9f7	1812	/* Configure the Channel 3 in PWM mode */
<>	144:ef7eb2e8f9f7	1813	TIM_OC3_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1814
<>	144:ef7eb2e8f9f7	1815	/* Set the Preload enable bit for channel3 */
<>	144:ef7eb2e8f9f7	1816	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3PE;
<>	144:ef7eb2e8f9f7	1817
<>	144:ef7eb2e8f9f7	1818	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	1819	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
<>	144:ef7eb2e8f9f7	1820	htim->Instance->CCMR2 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	1821	}
<>	144:ef7eb2e8f9f7	1822	break;
<>	144:ef7eb2e8f9f7	1823
<>	144:ef7eb2e8f9f7	1824	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	1825	{
<>	144:ef7eb2e8f9f7	1826	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1827	assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1828
<>	144:ef7eb2e8f9f7	1829	/* Configure the Channel 4 in PWM mode */
<>	144:ef7eb2e8f9f7	1830	TIM_OC4_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1831
<>	144:ef7eb2e8f9f7	1832	/* Set the Preload enable bit for channel4 */
<>	144:ef7eb2e8f9f7	1833	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4PE;
<>	144:ef7eb2e8f9f7	1834
<>	144:ef7eb2e8f9f7	1835	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	1836	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
<>	144:ef7eb2e8f9f7	1837	htim->Instance->CCMR2 \|= sConfig->OCFastMode << 8;
<>	144:ef7eb2e8f9f7	1838	}
<>	144:ef7eb2e8f9f7	1839	break;
<>	144:ef7eb2e8f9f7	1840
<>	144:ef7eb2e8f9f7	1841	case TIM_CHANNEL_5:
<>	144:ef7eb2e8f9f7	1842	{
<>	144:ef7eb2e8f9f7	1843	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1844	assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1845
<>	144:ef7eb2e8f9f7	1846	/* Configure the Channel 5 in PWM mode */
<>	144:ef7eb2e8f9f7	1847	TIM_OC5_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1848
<>	144:ef7eb2e8f9f7	1849	/* Set the Preload enable bit for channel5*/
<>	144:ef7eb2e8f9f7	1850	htim->Instance->CCMR3 \|= TIM_CCMR3_OC5PE;
<>	144:ef7eb2e8f9f7	1851
<>	144:ef7eb2e8f9f7	1852	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	1853	htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
<>	144:ef7eb2e8f9f7	1854	htim->Instance->CCMR3 \|= sConfig->OCFastMode;
<>	144:ef7eb2e8f9f7	1855	}
<>	144:ef7eb2e8f9f7	1856	break;
<>	144:ef7eb2e8f9f7	1857
<>	144:ef7eb2e8f9f7	1858	case TIM_CHANNEL_6:
<>	144:ef7eb2e8f9f7	1859	{
<>	144:ef7eb2e8f9f7	1860	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1861	assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1862
<>	144:ef7eb2e8f9f7	1863	/* Configure the Channel 5 in PWM mode */
<>	144:ef7eb2e8f9f7	1864	TIM_OC6_SetConfig(htim->Instance, sConfig);
<>	144:ef7eb2e8f9f7	1865
<>	144:ef7eb2e8f9f7	1866	/* Set the Preload enable bit for channel6 */
<>	144:ef7eb2e8f9f7	1867	htim->Instance->CCMR3 \|= TIM_CCMR3_OC6PE;
<>	144:ef7eb2e8f9f7	1868
<>	144:ef7eb2e8f9f7	1869	/* Configure the Output Fast mode */
<>	144:ef7eb2e8f9f7	1870	htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
<>	144:ef7eb2e8f9f7	1871	htim->Instance->CCMR3 \|= sConfig->OCFastMode << 8;
<>	144:ef7eb2e8f9f7	1872	}
<>	144:ef7eb2e8f9f7	1873	break;
<>	144:ef7eb2e8f9f7	1874
<>	144:ef7eb2e8f9f7	1875	default:
<>	144:ef7eb2e8f9f7	1876	break;
<>	144:ef7eb2e8f9f7	1877	}
<>	144:ef7eb2e8f9f7	1878
<>	144:ef7eb2e8f9f7	1879	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1880
<>	144:ef7eb2e8f9f7	1881	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1882
<>	144:ef7eb2e8f9f7	1883	return HAL_OK;
<>	144:ef7eb2e8f9f7	1884	}
<>	144:ef7eb2e8f9f7	1885
<>	144:ef7eb2e8f9f7	1886
<>	144:ef7eb2e8f9f7	1887	/**
<>	144:ef7eb2e8f9f7	1888	* @brief Configures the TIM in master mode.
<>	144:ef7eb2e8f9f7	1889	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	1890	* @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	1891	* contains the selected trigger output (TRGO) and the Master/Slave
<>	144:ef7eb2e8f9f7	1892	* mode.
<>	144:ef7eb2e8f9f7	1893	* @retval HAL status
<>	144:ef7eb2e8f9f7	1894	*/
<>	144:ef7eb2e8f9f7	1895	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	1896	TIM_MasterConfigTypeDef * sMasterConfig)
<>	144:ef7eb2e8f9f7	1897	{
<>	144:ef7eb2e8f9f7	1898	uint32_t tmpcr2;
<>	144:ef7eb2e8f9f7	1899	uint32_t tmpsmcr;
<>	144:ef7eb2e8f9f7	1900
<>	144:ef7eb2e8f9f7	1901	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1902	assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1903	assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<>	144:ef7eb2e8f9f7	1904	assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<>	144:ef7eb2e8f9f7	1905
<>	144:ef7eb2e8f9f7	1906	/* Check input state */
<>	144:ef7eb2e8f9f7	1907	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	1908
<>	144:ef7eb2e8f9f7	1909	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	1910	tmpcr2 = htim->Instance->CR2;
<>	144:ef7eb2e8f9f7	1911
<>	144:ef7eb2e8f9f7	1912	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	1913	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	1914
<>	144:ef7eb2e8f9f7	1915	/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
<>	144:ef7eb2e8f9f7	1916	if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
<>	144:ef7eb2e8f9f7	1917	{
<>	144:ef7eb2e8f9f7	1918	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1919	assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
<>	144:ef7eb2e8f9f7	1920
<>	144:ef7eb2e8f9f7	1921	/* Clear the MMS2 bits */
<>	144:ef7eb2e8f9f7	1922	tmpcr2 &= ~TIM_CR2_MMS2;
<>	144:ef7eb2e8f9f7	1923	/* Select the TRGO2 source*/
<>	144:ef7eb2e8f9f7	1924	tmpcr2 \|= sMasterConfig->MasterOutputTrigger2;
<>	144:ef7eb2e8f9f7	1925	}
<>	144:ef7eb2e8f9f7	1926
<>	144:ef7eb2e8f9f7	1927	/* Reset the MMS Bits */
<>	144:ef7eb2e8f9f7	1928	tmpcr2 &= ~TIM_CR2_MMS;
<>	144:ef7eb2e8f9f7	1929	/* Select the TRGO source */
<>	144:ef7eb2e8f9f7	1930	tmpcr2 \|= sMasterConfig->MasterOutputTrigger;
<>	144:ef7eb2e8f9f7	1931
<>	144:ef7eb2e8f9f7	1932	/* Reset the MSM Bit */
<>	144:ef7eb2e8f9f7	1933	tmpsmcr &= ~TIM_SMCR_MSM;
<>	144:ef7eb2e8f9f7	1934	/* Set master mode */
<>	144:ef7eb2e8f9f7	1935	tmpsmcr \|= sMasterConfig->MasterSlaveMode;
<>	144:ef7eb2e8f9f7	1936
<>	144:ef7eb2e8f9f7	1937	/* Update TIMx CR2 */
<>	144:ef7eb2e8f9f7	1938	htim->Instance->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	1939
<>	144:ef7eb2e8f9f7	1940	/* Update TIMx SMCR */
<>	144:ef7eb2e8f9f7	1941	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	1942
<>	144:ef7eb2e8f9f7	1943	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1944
<>	144:ef7eb2e8f9f7	1945	return HAL_OK;
<>	144:ef7eb2e8f9f7	1946	}
<>	144:ef7eb2e8f9f7	1947	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	1948	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	1949	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	1950	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	1951
<>	144:ef7eb2e8f9f7	1952	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	1953	/**
<>	144:ef7eb2e8f9f7	1954	* @brief Configures the TIM in master mode.
<>	144:ef7eb2e8f9f7	1955	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	1956	* @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	1957	* contains the selected trigger output (TRGO) and the Master/Slave
<>	144:ef7eb2e8f9f7	1958	* mode.
<>	144:ef7eb2e8f9f7	1959	* @retval HAL status
<>	144:ef7eb2e8f9f7	1960	*/
<>	144:ef7eb2e8f9f7	1961	HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef htim, TIM_MasterConfigTypeDef sMasterConfig)
<>	144:ef7eb2e8f9f7	1962	{
<>	144:ef7eb2e8f9f7	1963	/* Check the parameters */
<>	144:ef7eb2e8f9f7	1964	assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	1965	assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<>	144:ef7eb2e8f9f7	1966	assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<>	144:ef7eb2e8f9f7	1967
<>	144:ef7eb2e8f9f7	1968	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	1969
<>	144:ef7eb2e8f9f7	1970	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	1971
<>	144:ef7eb2e8f9f7	1972	/* Reset the MMS Bits */
<>	144:ef7eb2e8f9f7	1973	htim->Instance->CR2 &= ~TIM_CR2_MMS;
<>	144:ef7eb2e8f9f7	1974	/* Select the TRGO source */
<>	144:ef7eb2e8f9f7	1975	htim->Instance->CR2 \|= sMasterConfig->MasterOutputTrigger;
<>	144:ef7eb2e8f9f7	1976
<>	144:ef7eb2e8f9f7	1977	/* Reset the MSM Bit */
<>	144:ef7eb2e8f9f7	1978	htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<>	144:ef7eb2e8f9f7	1979	/* Set or Reset the MSM Bit */
<>	144:ef7eb2e8f9f7	1980	htim->Instance->SMCR \|= sMasterConfig->MasterSlaveMode;
<>	144:ef7eb2e8f9f7	1981
<>	144:ef7eb2e8f9f7	1982	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	1983
<>	144:ef7eb2e8f9f7	1984	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	1985
<>	144:ef7eb2e8f9f7	1986	return HAL_OK;
<>	144:ef7eb2e8f9f7	1987	}
<>	144:ef7eb2e8f9f7	1988	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	1989
<>	144:ef7eb2e8f9f7	1990	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	1991	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	1992	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	1993	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	1994	/**
<>	144:ef7eb2e8f9f7	1995	* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<>	144:ef7eb2e8f9f7	1996	* and the AOE(automatic output enable).
<>	144:ef7eb2e8f9f7	1997	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	1998	* @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef
<>	144:ef7eb2e8f9f7	1999	structure that contains the BDTR Register configuration information
<>	144:ef7eb2e8f9f7	2000	for the TIM peripheral.
<>	144:ef7eb2e8f9f7	2001	* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F358xx, STM32F303xE,
<>	144:ef7eb2e8f9f7	2002	STM32F398xx and STM32F303x8 two break inputs can be configured.
<>	144:ef7eb2e8f9f7	2003	* @retval HAL status
<>	144:ef7eb2e8f9f7	2004	*/
<>	144:ef7eb2e8f9f7	2005	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	2006	TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
<>	144:ef7eb2e8f9f7	2007	{
<>	144:ef7eb2e8f9f7	2008	uint32_t tmpbdtr = 0;
<>	144:ef7eb2e8f9f7	2009
<>	144:ef7eb2e8f9f7	2010	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2011	assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2012	assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<>	144:ef7eb2e8f9f7	2013	assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<>	144:ef7eb2e8f9f7	2014	assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<>	144:ef7eb2e8f9f7	2015	assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<>	144:ef7eb2e8f9f7	2016	assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<>	144:ef7eb2e8f9f7	2017	assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<>	144:ef7eb2e8f9f7	2018	assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
<>	144:ef7eb2e8f9f7	2019	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<>	144:ef7eb2e8f9f7	2020
<>	144:ef7eb2e8f9f7	2021	/* Check input state */
<>	144:ef7eb2e8f9f7	2022	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2023
<>	144:ef7eb2e8f9f7	2024	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<>	144:ef7eb2e8f9f7	2025	the OSSI State, the dead time value and the Automatic Output Enable Bit */
<>	144:ef7eb2e8f9f7	2026	if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
<>	144:ef7eb2e8f9f7	2027	{
<>	144:ef7eb2e8f9f7	2028	assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
<>	144:ef7eb2e8f9f7	2029	assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
<>	144:ef7eb2e8f9f7	2030	assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
<>	144:ef7eb2e8f9f7	2031
<>	144:ef7eb2e8f9f7	2032	/* Clear the BDTR bits */
<>	144:ef7eb2e8f9f7	2033	tmpbdtr &= ~(TIM_BDTR_DTG \| TIM_BDTR_LOCK \| TIM_BDTR_OSSI \|
<>	144:ef7eb2e8f9f7	2034	TIM_BDTR_OSSR \| TIM_BDTR_BKE \| TIM_BDTR_BKP \|
<>	144:ef7eb2e8f9f7	2035	TIM_BDTR_AOE \| TIM_BDTR_MOE \| TIM_BDTR_BKF \|
<>	144:ef7eb2e8f9f7	2036	TIM_BDTR_BK2F \| TIM_BDTR_BK2E \| TIM_BDTR_BK2P);
<>	144:ef7eb2e8f9f7	2037
<>	144:ef7eb2e8f9f7	2038	/* Set the BDTR bits */
<>	144:ef7eb2e8f9f7	2039	tmpbdtr \|= sBreakDeadTimeConfig->DeadTime;
<>	144:ef7eb2e8f9f7	2040	tmpbdtr \|= sBreakDeadTimeConfig->LockLevel;
<>	144:ef7eb2e8f9f7	2041	tmpbdtr \|= sBreakDeadTimeConfig->OffStateIDLEMode;
<>	144:ef7eb2e8f9f7	2042	tmpbdtr \|= sBreakDeadTimeConfig->OffStateRunMode;
<>	144:ef7eb2e8f9f7	2043	tmpbdtr \|= sBreakDeadTimeConfig->BreakState;
<>	144:ef7eb2e8f9f7	2044	tmpbdtr \|= sBreakDeadTimeConfig->BreakPolarity;
<>	144:ef7eb2e8f9f7	2045	tmpbdtr \|= sBreakDeadTimeConfig->AutomaticOutput;
<>	144:ef7eb2e8f9f7	2046	tmpbdtr \|= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
<>	144:ef7eb2e8f9f7	2047	tmpbdtr \|= (sBreakDeadTimeConfig->Break2Filter << BDTR_BK2F_SHIFT);
<>	144:ef7eb2e8f9f7	2048	tmpbdtr \|= sBreakDeadTimeConfig->Break2State;
<>	144:ef7eb2e8f9f7	2049	tmpbdtr \|= sBreakDeadTimeConfig->Break2Polarity;
<>	144:ef7eb2e8f9f7	2050	}
<>	144:ef7eb2e8f9f7	2051	else
<>	144:ef7eb2e8f9f7	2052	{
<>	144:ef7eb2e8f9f7	2053	/* Clear the BDTR bits */
<>	144:ef7eb2e8f9f7	2054	tmpbdtr &= ~(TIM_BDTR_DTG \| TIM_BDTR_LOCK \| TIM_BDTR_OSSI \|
<>	144:ef7eb2e8f9f7	2055	TIM_BDTR_OSSR \| TIM_BDTR_BKE \| TIM_BDTR_BKP \|
<>	144:ef7eb2e8f9f7	2056	TIM_BDTR_AOE \| TIM_BDTR_MOE \| TIM_BDTR_BKF);
<>	144:ef7eb2e8f9f7	2057
<>	144:ef7eb2e8f9f7	2058	/* Set the BDTR bits */
<>	144:ef7eb2e8f9f7	2059	tmpbdtr \|= sBreakDeadTimeConfig->DeadTime;
<>	144:ef7eb2e8f9f7	2060	tmpbdtr \|= sBreakDeadTimeConfig->LockLevel;
<>	144:ef7eb2e8f9f7	2061	tmpbdtr \|= sBreakDeadTimeConfig->OffStateIDLEMode;
<>	144:ef7eb2e8f9f7	2062	tmpbdtr \|= sBreakDeadTimeConfig->OffStateRunMode;
<>	144:ef7eb2e8f9f7	2063	tmpbdtr \|= sBreakDeadTimeConfig->BreakState;
<>	144:ef7eb2e8f9f7	2064	tmpbdtr \|= sBreakDeadTimeConfig->BreakPolarity;
<>	144:ef7eb2e8f9f7	2065	tmpbdtr \|= sBreakDeadTimeConfig->AutomaticOutput;
<>	144:ef7eb2e8f9f7	2066	tmpbdtr \|= (sBreakDeadTimeConfig->BreakFilter << BDTR_BKF_SHIFT);
<>	144:ef7eb2e8f9f7	2067	}
<>	144:ef7eb2e8f9f7	2068
<>	144:ef7eb2e8f9f7	2069	/* Set TIMx_BDTR */
<>	144:ef7eb2e8f9f7	2070	htim->Instance->BDTR = tmpbdtr;
<>	144:ef7eb2e8f9f7	2071
<>	144:ef7eb2e8f9f7	2072	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2073
<>	144:ef7eb2e8f9f7	2074	return HAL_OK;
<>	144:ef7eb2e8f9f7	2075	}
<>	144:ef7eb2e8f9f7	2076	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2077	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2078	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	2079	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2080
<>	144:ef7eb2e8f9f7	2081	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	2082	/**
<>	144:ef7eb2e8f9f7	2083	* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<>	144:ef7eb2e8f9f7	2084	* and the AOE(automatic output enable).
<>	144:ef7eb2e8f9f7	2085	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	2086	* @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	2087	* contains the BDTR Register configuration information for the TIM peripheral.
<>	144:ef7eb2e8f9f7	2088	* @retval HAL status
<>	144:ef7eb2e8f9f7	2089	*/
<>	144:ef7eb2e8f9f7	2090	HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	2091	TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
<>	144:ef7eb2e8f9f7	2092	{
<>	144:ef7eb2e8f9f7	2093	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2094	assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2095	assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<>	144:ef7eb2e8f9f7	2096	assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<>	144:ef7eb2e8f9f7	2097	assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<>	144:ef7eb2e8f9f7	2098	assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<>	144:ef7eb2e8f9f7	2099	assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<>	144:ef7eb2e8f9f7	2100	assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<>	144:ef7eb2e8f9f7	2101	assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<>	144:ef7eb2e8f9f7	2102
<>	144:ef7eb2e8f9f7	2103	/* Process Locked */
<>	144:ef7eb2e8f9f7	2104	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2105
<>	144:ef7eb2e8f9f7	2106	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2107
<>	144:ef7eb2e8f9f7	2108	/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<>	144:ef7eb2e8f9f7	2109	the OSSI State, the dead time value and the Automatic Output Enable Bit */
<>	144:ef7eb2e8f9f7	2110	htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode \|
<>	144:ef7eb2e8f9f7	2111	sBreakDeadTimeConfig->OffStateIDLEMode \|
<>	144:ef7eb2e8f9f7	2112	sBreakDeadTimeConfig->LockLevel \|
<>	144:ef7eb2e8f9f7	2113	sBreakDeadTimeConfig->DeadTime \|
<>	144:ef7eb2e8f9f7	2114	sBreakDeadTimeConfig->BreakState \|
<>	144:ef7eb2e8f9f7	2115	sBreakDeadTimeConfig->BreakPolarity \|
<>	144:ef7eb2e8f9f7	2116	sBreakDeadTimeConfig->AutomaticOutput;
<>	144:ef7eb2e8f9f7	2117
<>	144:ef7eb2e8f9f7	2118
<>	144:ef7eb2e8f9f7	2119	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2120
<>	144:ef7eb2e8f9f7	2121	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2122
<>	144:ef7eb2e8f9f7	2123	return HAL_OK;
<>	144:ef7eb2e8f9f7	2124	}
<>	144:ef7eb2e8f9f7	2125	#endif /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	2126
<>	144:ef7eb2e8f9f7	2127	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2128	defined(STM32F303xC) \|\| defined(STM32F358xx)
<>	144:ef7eb2e8f9f7	2129	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
<>	144:ef7eb2e8f9f7	2130	/**
<>	144:ef7eb2e8f9f7	2131	* @brief Configures the TIM1, TIM8, TIM16 and TIM20 Remapping input capabilities.
<>	144:ef7eb2e8f9f7	2132	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	2133	* @param Remap1: specifies the first TIM remapping source.
<>	144:ef7eb2e8f9f7	2134	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2135	* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any ADC1 AWD (analog watchdog)
<>	144:ef7eb2e8f9f7	2136	* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
<>	144:ef7eb2e8f9f7	2137	* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
<>	144:ef7eb2e8f9f7	2138	* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
<>	144:ef7eb2e8f9f7	2139	* @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any ADC2 AWD
<>	144:ef7eb2e8f9f7	2140	* @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
<>	144:ef7eb2e8f9f7	2141	* @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
<>	144:ef7eb2e8f9f7	2142	* @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
<>	144:ef7eb2e8f9f7	2143	* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
<>	144:ef7eb2e8f9f7	2144	* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
<>	144:ef7eb2e8f9f7	2145	* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
<>	144:ef7eb2e8f9f7	2146	* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
<>	144:ef7eb2e8f9f7	2147	* @arg TIM_TIM20_ADC3_NONE: TIM20_ETR is not connected to any AWD (analog watchdog)
<>	144:ef7eb2e8f9f7	2148	* @arg TIM_TIM20_ADC3_AWD1: TIM20_ETR is connected to ADC3 AWD1
<>	144:ef7eb2e8f9f7	2149	* @arg TIM_TIM20_ADC3_AWD2: TIM20_ETR is connected to ADC3 AWD2
<>	144:ef7eb2e8f9f7	2150	* @arg TIM_TIM20_ADC3_AWD3: TIM20_ETR is connected to ADC3 AWD3
<>	144:ef7eb2e8f9f7	2151	* @param Remap2: specifies the second TIMremapping source (if any).
<>	144:ef7eb2e8f9f7	2152	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2153	* @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any ADC4 AWD (analog watchdog)
<>	144:ef7eb2e8f9f7	2154	* @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
<>	144:ef7eb2e8f9f7	2155	* @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
<>	144:ef7eb2e8f9f7	2156	* @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
<>	144:ef7eb2e8f9f7	2157	* @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any ADC3 AWD
<>	144:ef7eb2e8f9f7	2158	* @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
<>	144:ef7eb2e8f9f7	2159	* @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
<>	144:ef7eb2e8f9f7	2160	* @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
<>	144:ef7eb2e8f9f7	2161	* @arg TIM_TIM16_NONE: Non significant value for TIM16
<>	144:ef7eb2e8f9f7	2162	* @arg TIM_TIM20_ADC4_NONE: TIM20_ETR is not connected to any ADC4 AWD
<>	144:ef7eb2e8f9f7	2163	* @arg TIM_TIM20_ADC4_AWD1: TIM20_ETR is connected to ADC4 AWD1
<>	144:ef7eb2e8f9f7	2164	* @arg TIM_TIM20_ADC4_AWD2: TIM20_ETR is connected to ADC4 AWD2
<>	144:ef7eb2e8f9f7	2165	* @arg TIM_TIM20_ADC4_AWD3: TIM20_ETR is connected to ADC4 AWD3
<>	144:ef7eb2e8f9f7	2166	* @retval HAL status
<>	144:ef7eb2e8f9f7	2167	*/
<>	144:ef7eb2e8f9f7	2168	#else /* STM32F303xC \|\| STM32F358xx */
<>	144:ef7eb2e8f9f7	2169	/**
<>	144:ef7eb2e8f9f7	2170	* @brief Configures the TIM1, TIM8 and TIM16 Remapping input capabilities.
<>	144:ef7eb2e8f9f7	2171	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	2172	* @param Remap1: specifies the first TIM remapping source.
<>	144:ef7eb2e8f9f7	2173	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2174	* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
<>	144:ef7eb2e8f9f7	2175	* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
<>	144:ef7eb2e8f9f7	2176	* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
<>	144:ef7eb2e8f9f7	2177	* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
<>	144:ef7eb2e8f9f7	2178	* @arg TIM_TIM8_ADC2_NONE: TIM8_ETR is not connected to any AWD
<>	144:ef7eb2e8f9f7	2179	* @arg TIM_TIM8_ADC2_AWD1: TIM8_ETR is connected to ADC2 AWD1
<>	144:ef7eb2e8f9f7	2180	* @arg TIM_TIM8_ADC2_AWD2: TIM8_ETR is connected to ADC2 AWD2
<>	144:ef7eb2e8f9f7	2181	* @arg TIM_TIM8_ADC2_AWD3: TIM8_ETR is connected to ADC2 AWD3
<>	144:ef7eb2e8f9f7	2182	* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
<>	144:ef7eb2e8f9f7	2183	* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC clock
<>	144:ef7eb2e8f9f7	2184	* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
<>	144:ef7eb2e8f9f7	2185	* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
<>	144:ef7eb2e8f9f7	2186	* @param Remap2: specifies the second TIMremapping source (if any).
<>	144:ef7eb2e8f9f7	2187	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2188	* @arg TIM_TIM1_ADC4_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
<>	144:ef7eb2e8f9f7	2189	* @arg TIM_TIM1_ADC4_AWD1: TIM1_ETR is connected to ADC4 AWD1
<>	144:ef7eb2e8f9f7	2190	* @arg TIM_TIM1_ADC4_AWD2: TIM1_ETR is connected to ADC4 AWD2
<>	144:ef7eb2e8f9f7	2191	* @arg TIM_TIM1_ADC4_AWD3: TIM1_ETR is connected to ADC4 AWD3
<>	144:ef7eb2e8f9f7	2192	* @arg TIM_TIM8_ADC3_NONE: TIM8_ETR is not connected to any AWD
<>	144:ef7eb2e8f9f7	2193	* @arg TIM_TIM8_ADC3_AWD1: TIM8_ETR is connected to ADC3 AWD1
<>	144:ef7eb2e8f9f7	2194	* @arg TIM_TIM8_ADC3_AWD2: TIM8_ETR is connected to ADC3 AWD2
<>	144:ef7eb2e8f9f7	2195	* @arg TIM_TIM8_ADC3_AWD3: TIM8_ETR is connected to ADC3 AWD3
<>	144:ef7eb2e8f9f7	2196	* @retval HAL status
<>	144:ef7eb2e8f9f7	2197	*/
<>	144:ef7eb2e8f9f7	2198	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2199	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap1, uint32_t Remap2)
<>	144:ef7eb2e8f9f7	2200	{
<>	144:ef7eb2e8f9f7	2201	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2202
<>	144:ef7eb2e8f9f7	2203	/* Check parameters */
<>	144:ef7eb2e8f9f7	2204	assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2205	assert_param(IS_TIM_REMAP(Remap1));
<>	144:ef7eb2e8f9f7	2206	assert_param(IS_TIM_REMAP2(Remap2));
<>	144:ef7eb2e8f9f7	2207
<>	144:ef7eb2e8f9f7	2208	/* Set the Timer remapping configuration */
<>	144:ef7eb2e8f9f7	2209	htim->Instance->OR = Remap1 \| Remap2;
<>	144:ef7eb2e8f9f7	2210
<>	144:ef7eb2e8f9f7	2211	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2212
<>	144:ef7eb2e8f9f7	2213	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2214
<>	144:ef7eb2e8f9f7	2215	return HAL_OK;
<>	144:ef7eb2e8f9f7	2216	}
<>	144:ef7eb2e8f9f7	2217	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2218	/* STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2219
<>	144:ef7eb2e8f9f7	2220
<>	144:ef7eb2e8f9f7	2221	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	2222	defined(STM32F302xC) \|\| \
<>	144:ef7eb2e8f9f7	2223	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	2224	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
<>	144:ef7eb2e8f9f7	2225	defined(STM32F373xC) \|\| defined(STM32F378xx)
<>	144:ef7eb2e8f9f7	2226	#if defined(STM32F302xE) \|\| \
<>	144:ef7eb2e8f9f7	2227	defined(STM32F302xC) \|\| \
<>	144:ef7eb2e8f9f7	2228	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	2229	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2230	/**
<>	144:ef7eb2e8f9f7	2231	* @brief Configures the TIM1 and TIM16 Remapping input capabilities.
<>	144:ef7eb2e8f9f7	2232	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	2233	* @param Remap: specifies the TIM remapping source.
<>	144:ef7eb2e8f9f7	2234	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2235	* @arg TIM_TIM1_ADC1_NONE: TIM1_ETR is not connected to any AWD (analog watchdog)
<>	144:ef7eb2e8f9f7	2236	* @arg TIM_TIM1_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
<>	144:ef7eb2e8f9f7	2237	* @arg TIM_TIM1_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
<>	144:ef7eb2e8f9f7	2238	* @arg TIM_TIM1_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
<>	144:ef7eb2e8f9f7	2239	* @arg TIM_TIM16_GPIO: TIM16 TI1 is connected to GPIO
<>	144:ef7eb2e8f9f7	2240	* @arg TIM_TIM16_RTC: TIM16 TI1 is connected to RTC_clock
<>	144:ef7eb2e8f9f7	2241	* @arg TIM_TIM16_HSE: TIM16 TI1 is connected to HSE/32
<>	144:ef7eb2e8f9f7	2242	* @arg TIM_TIM16_MCO: TIM16 TI1 is connected to MCO
<>	144:ef7eb2e8f9f7	2243	* @retval HAL status
<>	144:ef7eb2e8f9f7	2244	*/
<>	144:ef7eb2e8f9f7	2245	#else /* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	2246	/**
<>	144:ef7eb2e8f9f7	2247	* @brief Configures the TIM2 and TIM14 Remapping input capabilities.
<>	144:ef7eb2e8f9f7	2248	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	2249	* @param Remap: specifies the TIM remapping source.
<>	144:ef7eb2e8f9f7	2250	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2251	* STM32F373xC, STM32F378xx:
<>	144:ef7eb2e8f9f7	2252	* @arg TIM_TIM2_TIM8_TRGO: TIM8 TRGOUT is connected to TIM2_ITR1
<>	144:ef7eb2e8f9f7	2253	* @arg TIM_TIM2_ETH_PTP: PTP trigger output is connected to TIM2_ITR1
<>	144:ef7eb2e8f9f7	2254	* @arg TIM_TIM2_USBFS_SOF: OTG FS SOF is connected to the TIM2_ITR1 input
<>	144:ef7eb2e8f9f7	2255	* @arg TIM_TIM2_USBHS_SOF: OTG HS SOF is connected to the TIM2_ITR1 input
<>	144:ef7eb2e8f9f7	2256	* @arg TIM_TIM14_GPIO: TIM14 TI1 is connected to GPIO
<>	144:ef7eb2e8f9f7	2257	* @arg TIM_TIM14_RTC: TIM14 TI1 is connected to RTC_clock
<>	144:ef7eb2e8f9f7	2258	* @arg TIM_TIM14_HSE: TIM14 TI1 is connected to HSE/32
<>	144:ef7eb2e8f9f7	2259	* @arg TIM_TIM14_MCO: TIM14 TI1 is connected to MCO
<>	144:ef7eb2e8f9f7	2260	* @retval HAL status
<>	144:ef7eb2e8f9f7	2261	*/
<>	144:ef7eb2e8f9f7	2262	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	2263	/* STM32F302xC \|\| */
<>	144:ef7eb2e8f9f7	2264	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	2265	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
<>	144:ef7eb2e8f9f7	2266	HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<>	144:ef7eb2e8f9f7	2267	{
<>	144:ef7eb2e8f9f7	2268	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2269
<>	144:ef7eb2e8f9f7	2270	/* Check parameters */
<>	144:ef7eb2e8f9f7	2271	assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2272	assert_param(IS_TIM_REMAP(Remap));
<>	144:ef7eb2e8f9f7	2273
<>	144:ef7eb2e8f9f7	2274	/* Set the Timer remapping configuration */
<>	144:ef7eb2e8f9f7	2275	htim->Instance->OR = Remap;
<>	144:ef7eb2e8f9f7	2276
<>	144:ef7eb2e8f9f7	2277	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2278
<>	144:ef7eb2e8f9f7	2279	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2280
<>	144:ef7eb2e8f9f7	2281	return HAL_OK;
<>	144:ef7eb2e8f9f7	2282	}
<>	144:ef7eb2e8f9f7	2283	#endif /* STM32F302xE \|\| */
<>	144:ef7eb2e8f9f7	2284	/* STM32F302xC \|\| */
<>	144:ef7eb2e8f9f7	2285	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	2286	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx \|\| */
<>	144:ef7eb2e8f9f7	2287	/* STM32F373xC \|\| STM32F378xx */
<>	144:ef7eb2e8f9f7	2288
<>	144:ef7eb2e8f9f7	2289
<>	144:ef7eb2e8f9f7	2290	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2291	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	2292	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	2293	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2294	/**
<>	144:ef7eb2e8f9f7	2295	* @brief Group channel 5 and channel 1, 2 or 3
<>	144:ef7eb2e8f9f7	2296	* @param htim: TIM handle.
<>	144:ef7eb2e8f9f7	2297	* @param Channels: specifies the reference signal(s) the OC5REF is combined with.
<>	144:ef7eb2e8f9f7	2298	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	2299	* TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
<>	144:ef7eb2e8f9f7	2300	* TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
<>	144:ef7eb2e8f9f7	2301	* TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF
<>	144:ef7eb2e8f9f7	2302	* TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF
<>	144:ef7eb2e8f9f7	2303	* @retval HAL status
<>	144:ef7eb2e8f9f7	2304	*/
<>	144:ef7eb2e8f9f7	2305	HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels)
<>	144:ef7eb2e8f9f7	2306	{
<>	144:ef7eb2e8f9f7	2307	/* Check parameters */
<>	144:ef7eb2e8f9f7	2308	assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2309	assert_param(IS_TIM_GROUPCH5(Channels));
<>	144:ef7eb2e8f9f7	2310
<>	144:ef7eb2e8f9f7	2311	/* Process Locked */
<>	144:ef7eb2e8f9f7	2312	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2313
<>	144:ef7eb2e8f9f7	2314	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2315
<>	144:ef7eb2e8f9f7	2316	/* Clear GC5Cx bit fields */
<>	144:ef7eb2e8f9f7	2317	htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3\|TIM_CCR5_GC5C2\|TIM_CCR5_GC5C1);
<>	144:ef7eb2e8f9f7	2318
<>	144:ef7eb2e8f9f7	2319	/* Set GC5Cx bit fields */
<>	144:ef7eb2e8f9f7	2320	htim->Instance->CCR5 \|= Channels;
<>	144:ef7eb2e8f9f7	2321
<>	144:ef7eb2e8f9f7	2322	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2323
<>	144:ef7eb2e8f9f7	2324	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2325
<>	144:ef7eb2e8f9f7	2326	return HAL_OK;
<>	144:ef7eb2e8f9f7	2327	}
<>	144:ef7eb2e8f9f7	2328	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2329	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2330	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	2331	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2332
<>	144:ef7eb2e8f9f7	2333	/**
<>	144:ef7eb2e8f9f7	2334	* @}
<>	144:ef7eb2e8f9f7	2335	*/
<>	144:ef7eb2e8f9f7	2336
<>	144:ef7eb2e8f9f7	2337	/** @addtogroup TIM_Exported_Functions_Group8
<>	144:ef7eb2e8f9f7	2338	* @{
<>	144:ef7eb2e8f9f7	2339	*/
<>	144:ef7eb2e8f9f7	2340	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2341	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	2342	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	2343	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2344	/**
<>	144:ef7eb2e8f9f7	2345	* @brief Configures the OCRef clear feature
<>	144:ef7eb2e8f9f7	2346	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	2347	* @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
<>	144:ef7eb2e8f9f7	2348	* contains the OCREF clear feature and parameters for the TIM peripheral.
<>	144:ef7eb2e8f9f7	2349	* @param Channel: specifies the TIM Channel
<>	144:ef7eb2e8f9f7	2350	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2351	* @arg TIM_CHANNEL_1: TIM Channel 1
<>	144:ef7eb2e8f9f7	2352	* @arg TIM_CHANNEL_2: TIM Channel 2
<>	144:ef7eb2e8f9f7	2353	* @arg TIM_CHANNEL_3: TIM Channel 3
<>	144:ef7eb2e8f9f7	2354	* @arg TIM_CHANNEL_4: TIM Channel 4
<>	144:ef7eb2e8f9f7	2355	* @arg TIM_Channel_5: TIM Channel 5
<>	144:ef7eb2e8f9f7	2356	* @arg TIM_Channel_6: TIM Channel 6
<>	144:ef7eb2e8f9f7	2357	* @note For STM32F302xC, STM32F302xE, STM32F303xC, STM32F303xE, STM32F358xx,
<>	144:ef7eb2e8f9f7	2358	* STM32F398xx and STM32F303x8 up to 6 OC channels can be configured
<>	144:ef7eb2e8f9f7	2359	* @retval None
<>	144:ef7eb2e8f9f7	2360	*/
<>	144:ef7eb2e8f9f7	2361	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
<>	144:ef7eb2e8f9f7	2362	TIM_ClearInputConfigTypeDef *sClearInputConfig,
<>	144:ef7eb2e8f9f7	2363	uint32_t Channel)
<>	144:ef7eb2e8f9f7	2364	{
<>	144:ef7eb2e8f9f7	2365	uint32_t tmpsmcr = 0;
<>	144:ef7eb2e8f9f7	2366
<>	144:ef7eb2e8f9f7	2367	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2368	assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
<>	144:ef7eb2e8f9f7	2369	assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
<>	144:ef7eb2e8f9f7	2370
<>	144:ef7eb2e8f9f7	2371	/* Check input state */
<>	144:ef7eb2e8f9f7	2372	__HAL_LOCK(htim);
<>	144:ef7eb2e8f9f7	2373
<>	144:ef7eb2e8f9f7	2374	htim->State = HAL_TIM_STATE_BUSY;
<>	144:ef7eb2e8f9f7	2375
<>	144:ef7eb2e8f9f7	2376	switch (sClearInputConfig->ClearInputSource)
<>	144:ef7eb2e8f9f7	2377	{
<>	144:ef7eb2e8f9f7	2378	case TIM_CLEARINPUTSOURCE_NONE:
<>	144:ef7eb2e8f9f7	2379	{
<>	144:ef7eb2e8f9f7	2380	/* Get the TIMx SMCR register value */
<>	144:ef7eb2e8f9f7	2381	tmpsmcr = htim->Instance->SMCR;
<>	144:ef7eb2e8f9f7	2382
<>	144:ef7eb2e8f9f7	2383	/* Clear the OCREF clear selection bit */
<>	144:ef7eb2e8f9f7	2384	tmpsmcr &= ~TIM_SMCR_OCCS;
<>	144:ef7eb2e8f9f7	2385
<>	144:ef7eb2e8f9f7	2386	/* Clear the ETR Bits */
<>	144:ef7eb2e8f9f7	2387	tmpsmcr &= ~(TIM_SMCR_ETF \| TIM_SMCR_ETPS \| TIM_SMCR_ECE \| TIM_SMCR_ETP);
<>	144:ef7eb2e8f9f7	2388
<>	144:ef7eb2e8f9f7	2389	/* Set TIMx_SMCR */
<>	144:ef7eb2e8f9f7	2390	htim->Instance->SMCR = tmpsmcr;
<>	144:ef7eb2e8f9f7	2391	}
<>	144:ef7eb2e8f9f7	2392	break;
<>	144:ef7eb2e8f9f7	2393
<>	144:ef7eb2e8f9f7	2394	case TIM_CLEARINPUTSOURCE_OCREFCLR:
<>	144:ef7eb2e8f9f7	2395	{
<>	144:ef7eb2e8f9f7	2396	/* Clear the OCREF clear selection bit */
<>	144:ef7eb2e8f9f7	2397	htim->Instance->SMCR &= ~TIM_SMCR_OCCS;
<>	144:ef7eb2e8f9f7	2398	}
<>	144:ef7eb2e8f9f7	2399	break;
<>	144:ef7eb2e8f9f7	2400
<>	144:ef7eb2e8f9f7	2401	case TIM_CLEARINPUTSOURCE_ETR:
<>	144:ef7eb2e8f9f7	2402	{
<>	144:ef7eb2e8f9f7	2403	/* Check the parameters */
<>	144:ef7eb2e8f9f7	2404	assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
<>	144:ef7eb2e8f9f7	2405	assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
<>	144:ef7eb2e8f9f7	2406	assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
<>	144:ef7eb2e8f9f7	2407
<>	144:ef7eb2e8f9f7	2408	TIM_ETR_SetConfig(htim->Instance,
<>	144:ef7eb2e8f9f7	2409	sClearInputConfig->ClearInputPrescaler,
<>	144:ef7eb2e8f9f7	2410	sClearInputConfig->ClearInputPolarity,
<>	144:ef7eb2e8f9f7	2411	sClearInputConfig->ClearInputFilter);
<>	144:ef7eb2e8f9f7	2412
<>	144:ef7eb2e8f9f7	2413	/* Set the OCREF clear selection bit */
<>	144:ef7eb2e8f9f7	2414	htim->Instance->SMCR \|= TIM_SMCR_OCCS;
<>	144:ef7eb2e8f9f7	2415	}
<>	144:ef7eb2e8f9f7	2416	break;
<>	144:ef7eb2e8f9f7	2417	default:
<>	144:ef7eb2e8f9f7	2418	break;
<>	144:ef7eb2e8f9f7	2419	}
<>	144:ef7eb2e8f9f7	2420
<>	144:ef7eb2e8f9f7	2421	switch (Channel)
<>	144:ef7eb2e8f9f7	2422	{
<>	144:ef7eb2e8f9f7	2423	case TIM_CHANNEL_1:
<>	144:ef7eb2e8f9f7	2424	{
<>	144:ef7eb2e8f9f7	2425	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	2426	{
<>	144:ef7eb2e8f9f7	2427	/* Enable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	2428	htim->Instance->CCMR1 \|= TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	2429	}
<>	144:ef7eb2e8f9f7	2430	else
<>	144:ef7eb2e8f9f7	2431	{
<>	144:ef7eb2e8f9f7	2432	/* Disable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	2433	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
<>	144:ef7eb2e8f9f7	2434	}
<>	144:ef7eb2e8f9f7	2435	}
<>	144:ef7eb2e8f9f7	2436	break;
<>	144:ef7eb2e8f9f7	2437	case TIM_CHANNEL_2:
<>	144:ef7eb2e8f9f7	2438	{
<>	144:ef7eb2e8f9f7	2439	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	2440	{
<>	144:ef7eb2e8f9f7	2441	/* Enable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	2442	htim->Instance->CCMR1 \|= TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	2443	}
<>	144:ef7eb2e8f9f7	2444	else
<>	144:ef7eb2e8f9f7	2445	{
<>	144:ef7eb2e8f9f7	2446	/* Disable the Ocref clear feature for Channel 2 */
<>	144:ef7eb2e8f9f7	2447	htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
<>	144:ef7eb2e8f9f7	2448	}
<>	144:ef7eb2e8f9f7	2449	}
<>	144:ef7eb2e8f9f7	2450	break;
<>	144:ef7eb2e8f9f7	2451	case TIM_CHANNEL_3:
<>	144:ef7eb2e8f9f7	2452	{
<>	144:ef7eb2e8f9f7	2453	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	2454	{
<>	144:ef7eb2e8f9f7	2455	/* Enable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	2456	htim->Instance->CCMR2 \|= TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	2457	}
<>	144:ef7eb2e8f9f7	2458	else
<>	144:ef7eb2e8f9f7	2459	{
<>	144:ef7eb2e8f9f7	2460	/* Disable the Ocref clear feature for Channel 3 */
<>	144:ef7eb2e8f9f7	2461	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
<>	144:ef7eb2e8f9f7	2462	}
<>	144:ef7eb2e8f9f7	2463	}
<>	144:ef7eb2e8f9f7	2464	break;
<>	144:ef7eb2e8f9f7	2465	case TIM_CHANNEL_4:
<>	144:ef7eb2e8f9f7	2466	{
<>	144:ef7eb2e8f9f7	2467	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	2468	{
<>	144:ef7eb2e8f9f7	2469	/* Enable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	2470	htim->Instance->CCMR2 \|= TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	2471	}
<>	144:ef7eb2e8f9f7	2472	else
<>	144:ef7eb2e8f9f7	2473	{
<>	144:ef7eb2e8f9f7	2474	/* Disable the Ocref clear feature for Channel 4 */
<>	144:ef7eb2e8f9f7	2475	htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
<>	144:ef7eb2e8f9f7	2476	}
<>	144:ef7eb2e8f9f7	2477	}
<>	144:ef7eb2e8f9f7	2478	break;
<>	144:ef7eb2e8f9f7	2479	case TIM_CHANNEL_5:
<>	144:ef7eb2e8f9f7	2480	{
<>	144:ef7eb2e8f9f7	2481	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	2482	{
<>	144:ef7eb2e8f9f7	2483	/* Enable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	2484	htim->Instance->CCMR3 \|= TIM_CCMR3_OC5CE;
<>	144:ef7eb2e8f9f7	2485	}
<>	144:ef7eb2e8f9f7	2486	else
<>	144:ef7eb2e8f9f7	2487	{
<>	144:ef7eb2e8f9f7	2488	/* Disable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	2489	htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5CE;
<>	144:ef7eb2e8f9f7	2490	}
<>	144:ef7eb2e8f9f7	2491	}
<>	144:ef7eb2e8f9f7	2492	break;
<>	144:ef7eb2e8f9f7	2493	case TIM_CHANNEL_6:
<>	144:ef7eb2e8f9f7	2494	{
<>	144:ef7eb2e8f9f7	2495	if(sClearInputConfig->ClearInputState != RESET)
<>	144:ef7eb2e8f9f7	2496	{
<>	144:ef7eb2e8f9f7	2497	/* Enable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	2498	htim->Instance->CCMR3 \|= TIM_CCMR3_OC6CE;
<>	144:ef7eb2e8f9f7	2499	}
<>	144:ef7eb2e8f9f7	2500	else
<>	144:ef7eb2e8f9f7	2501	{
<>	144:ef7eb2e8f9f7	2502	/* Disable the Ocref clear feature for Channel 1 */
<>	144:ef7eb2e8f9f7	2503	htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6CE;
<>	144:ef7eb2e8f9f7	2504	}
<>	144:ef7eb2e8f9f7	2505	}
<>	144:ef7eb2e8f9f7	2506	break;
<>	144:ef7eb2e8f9f7	2507	default:
<>	144:ef7eb2e8f9f7	2508	break;
<>	144:ef7eb2e8f9f7	2509	}
<>	144:ef7eb2e8f9f7	2510
<>	144:ef7eb2e8f9f7	2511	htim->State = HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2512
<>	144:ef7eb2e8f9f7	2513	__HAL_UNLOCK(htim);
<>	144:ef7eb2e8f9f7	2514
<>	144:ef7eb2e8f9f7	2515	return HAL_OK;
<>	144:ef7eb2e8f9f7	2516	}
<>	144:ef7eb2e8f9f7	2517	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2518	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2519	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	2520	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2521	/**
<>	144:ef7eb2e8f9f7	2522	* @}
<>	144:ef7eb2e8f9f7	2523	*/
<>	144:ef7eb2e8f9f7	2524
<>	144:ef7eb2e8f9f7	2525	/** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
<>	144:ef7eb2e8f9f7	2526	* @brief Extension Callbacks functions
<>	144:ef7eb2e8f9f7	2527	*
<>	144:ef7eb2e8f9f7	2528	@verbatim
<>	144:ef7eb2e8f9f7	2529	==============================================================================
<>	144:ef7eb2e8f9f7	2530	##### Extended Callbacks functions #####
<>	144:ef7eb2e8f9f7	2531	==============================================================================
<>	144:ef7eb2e8f9f7	2532	[..]
<>	144:ef7eb2e8f9f7	2533	This section provides Extended TIM callback functions:
<>	144:ef7eb2e8f9f7	2534	(+) Timer Commutation callback
<>	144:ef7eb2e8f9f7	2535	(+) Timer Break callback
<>	144:ef7eb2e8f9f7	2536
<>	144:ef7eb2e8f9f7	2537	@endverbatim
<>	144:ef7eb2e8f9f7	2538	* @{
<>	144:ef7eb2e8f9f7	2539	*/
<>	144:ef7eb2e8f9f7	2540
<>	144:ef7eb2e8f9f7	2541	/**
<>	144:ef7eb2e8f9f7	2542	* @brief Hall commutation changed callback in non blocking mode
<>	144:ef7eb2e8f9f7	2543	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	2544	* @retval None
<>	144:ef7eb2e8f9f7	2545	*/
<>	144:ef7eb2e8f9f7	2546	__weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2547	{
<>	144:ef7eb2e8f9f7	2548	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2549	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2550
<>	144:ef7eb2e8f9f7	2551	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2552	the HAL_TIMEx_CommutationCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2553	*/
<>	144:ef7eb2e8f9f7	2554	}
<>	144:ef7eb2e8f9f7	2555
<>	144:ef7eb2e8f9f7	2556	/**
<>	144:ef7eb2e8f9f7	2557	* @brief Hall Break detection callback in non blocking mode
<>	144:ef7eb2e8f9f7	2558	* @param htim: TIM handle
<>	144:ef7eb2e8f9f7	2559	* @retval None
<>	144:ef7eb2e8f9f7	2560	*/
<>	144:ef7eb2e8f9f7	2561	__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2562	{
<>	144:ef7eb2e8f9f7	2563	/* Prevent unused argument(s) compilation warning */
<>	144:ef7eb2e8f9f7	2564	UNUSED(htim);
<>	144:ef7eb2e8f9f7	2565
<>	144:ef7eb2e8f9f7	2566	/* NOTE : This function Should not be modified, when the callback is needed,
<>	144:ef7eb2e8f9f7	2567	the HAL_TIMEx_BreakCallback could be implemented in the user file
<>	144:ef7eb2e8f9f7	2568	*/
<>	144:ef7eb2e8f9f7	2569	}
<>	144:ef7eb2e8f9f7	2570
<>	144:ef7eb2e8f9f7	2571	/**
<>	144:ef7eb2e8f9f7	2572	* @}
<>	144:ef7eb2e8f9f7	2573	*/
<>	144:ef7eb2e8f9f7	2574
<>	144:ef7eb2e8f9f7	2575	/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions
<>	144:ef7eb2e8f9f7	2576	* @brief Extended Peripheral State functions
<>	144:ef7eb2e8f9f7	2577	*
<>	144:ef7eb2e8f9f7	2578	@verbatim
<>	144:ef7eb2e8f9f7	2579	==============================================================================
<>	144:ef7eb2e8f9f7	2580	##### Extended Peripheral State functions #####
<>	144:ef7eb2e8f9f7	2581	==============================================================================
<>	144:ef7eb2e8f9f7	2582	[..]
<>	144:ef7eb2e8f9f7	2583	This subsection permit to get in run-time the status of the peripheral
<>	144:ef7eb2e8f9f7	2584	and the data flow.
<>	144:ef7eb2e8f9f7	2585
<>	144:ef7eb2e8f9f7	2586	@endverbatim
<>	144:ef7eb2e8f9f7	2587	* @{
<>	144:ef7eb2e8f9f7	2588	*/
<>	144:ef7eb2e8f9f7	2589
<>	144:ef7eb2e8f9f7	2590	/**
<>	144:ef7eb2e8f9f7	2591	* @brief Return the TIM Hall Sensor interface state
<>	144:ef7eb2e8f9f7	2592	* @param htim: TIM Hall Sensor handle
<>	144:ef7eb2e8f9f7	2593	* @retval HAL state
<>	144:ef7eb2e8f9f7	2594	*/
<>	144:ef7eb2e8f9f7	2595	HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<>	144:ef7eb2e8f9f7	2596	{
<>	144:ef7eb2e8f9f7	2597	return htim->State;
<>	144:ef7eb2e8f9f7	2598	}
<>	144:ef7eb2e8f9f7	2599
<>	144:ef7eb2e8f9f7	2600	/**
<>	144:ef7eb2e8f9f7	2601	* @}
<>	144:ef7eb2e8f9f7	2602	*/
<>	144:ef7eb2e8f9f7	2603
<>	144:ef7eb2e8f9f7	2604	/**
<>	144:ef7eb2e8f9f7	2605	* @}
<>	144:ef7eb2e8f9f7	2606	*/
<>	144:ef7eb2e8f9f7	2607
<>	144:ef7eb2e8f9f7	2608	/** @addtogroup TIMEx_Private_Functions
<>	144:ef7eb2e8f9f7	2609	* @{
<>	144:ef7eb2e8f9f7	2610	*/
<>	144:ef7eb2e8f9f7	2611	/**
<>	144:ef7eb2e8f9f7	2612	* @brief TIM DMA Commutation callback.
<>	144:ef7eb2e8f9f7	2613	* @param hdma : pointer to DMA handle.
<>	144:ef7eb2e8f9f7	2614	* @retval None
<>	144:ef7eb2e8f9f7	2615	*/
<>	144:ef7eb2e8f9f7	2616	void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<>	144:ef7eb2e8f9f7	2617	{
<>	144:ef7eb2e8f9f7	2618	TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<>	144:ef7eb2e8f9f7	2619
<>	144:ef7eb2e8f9f7	2620	htim->State= HAL_TIM_STATE_READY;
<>	144:ef7eb2e8f9f7	2621
<>	144:ef7eb2e8f9f7	2622	HAL_TIMEx_CommutationCallback(htim);
<>	144:ef7eb2e8f9f7	2623	}
<>	144:ef7eb2e8f9f7	2624
<>	144:ef7eb2e8f9f7	2625	/**
<>	144:ef7eb2e8f9f7	2626	* @brief Enables or disables the TIM Capture Compare Channel xN.
<>	144:ef7eb2e8f9f7	2627	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	2628	* @param Channel: specifies the TIM Channel
<>	144:ef7eb2e8f9f7	2629	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	2630	* @arg TIM_CHANNEL_1: TIM Channel 1
<>	144:ef7eb2e8f9f7	2631	* @arg TIM_CHANNEL_2: TIM Channel 2
<>	144:ef7eb2e8f9f7	2632	* @arg TIM_CHANNEL_3: TIM Channel 3
<>	144:ef7eb2e8f9f7	2633	* @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
<>	144:ef7eb2e8f9f7	2634	* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<>	144:ef7eb2e8f9f7	2635	* @retval None
<>	144:ef7eb2e8f9f7	2636	*/
<>	144:ef7eb2e8f9f7	2637	static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<>	144:ef7eb2e8f9f7	2638	{
<>	144:ef7eb2e8f9f7	2639	uint32_t tmp = 0;
<>	144:ef7eb2e8f9f7	2640
<>	144:ef7eb2e8f9f7	2641	tmp = TIM_CCER_CC1NE << Channel;
<>	144:ef7eb2e8f9f7	2642
<>	144:ef7eb2e8f9f7	2643	/* Reset the CCxNE Bit */
<>	144:ef7eb2e8f9f7	2644	TIMx->CCER &= ~tmp;
<>	144:ef7eb2e8f9f7	2645
<>	144:ef7eb2e8f9f7	2646	/* Set or reset the CCxNE Bit */
<>	144:ef7eb2e8f9f7	2647	TIMx->CCER \|= (uint32_t)(ChannelNState << Channel);
<>	144:ef7eb2e8f9f7	2648	}
<>	144:ef7eb2e8f9f7	2649
<>	144:ef7eb2e8f9f7	2650	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
<>	144:ef7eb2e8f9f7	2651	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
<>	144:ef7eb2e8f9f7	2652	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
<>	144:ef7eb2e8f9f7	2653	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
<>	144:ef7eb2e8f9f7	2654	/**
<>	144:ef7eb2e8f9f7	2655	* @brief Timer Ouput Compare 5 configuration
<>	144:ef7eb2e8f9f7	2656	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	2657	* @param OC_Config: The ouput configuration structure
<>	144:ef7eb2e8f9f7	2658	* @retval None
<>	144:ef7eb2e8f9f7	2659	*/
<>	144:ef7eb2e8f9f7	2660	static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
<>	144:ef7eb2e8f9f7	2661	TIM_OC_InitTypeDef *OC_Config)
<>	144:ef7eb2e8f9f7	2662	{
<>	144:ef7eb2e8f9f7	2663	uint32_t tmpccmrx = 0;
<>	144:ef7eb2e8f9f7	2664	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	2665	uint32_t tmpcr2 = 0;
<>	144:ef7eb2e8f9f7	2666
<>	144:ef7eb2e8f9f7	2667	/* Disable the output: Reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	2668	TIMx->CCER &= ~TIM_CCER_CC5E;
<>	144:ef7eb2e8f9f7	2669
<>	144:ef7eb2e8f9f7	2670	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	2671	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	2672	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	2673	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	2674	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	2675	tmpccmrx = TIMx->CCMR3;
<>	144:ef7eb2e8f9f7	2676
<>	144:ef7eb2e8f9f7	2677	/* Reset the Output Compare Mode Bits */
<>	144:ef7eb2e8f9f7	2678	tmpccmrx &= ~(TIM_CCMR3_OC5M);
<>	144:ef7eb2e8f9f7	2679	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	2680	tmpccmrx \|= OC_Config->OCMode;
<>	144:ef7eb2e8f9f7	2681
<>	144:ef7eb2e8f9f7	2682	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	2683	tmpccer &= ~TIM_CCER_CC5P;
<>	144:ef7eb2e8f9f7	2684	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	2685	tmpccer \|= (OC_Config->OCPolarity << 16);
<>	144:ef7eb2e8f9f7	2686
<>	144:ef7eb2e8f9f7	2687	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	2688	{
<>	144:ef7eb2e8f9f7	2689	/* Reset the Output Compare IDLE State */
<>	144:ef7eb2e8f9f7	2690	tmpcr2 &= ~TIM_CR2_OIS5;
<>	144:ef7eb2e8f9f7	2691	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	2692	tmpcr2 \|= (OC_Config->OCIdleState << 8);
<>	144:ef7eb2e8f9f7	2693	}
<>	144:ef7eb2e8f9f7	2694	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	2695	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	2696
<>	144:ef7eb2e8f9f7	2697	/* Write to TIMx CCMR3 */
<>	144:ef7eb2e8f9f7	2698	TIMx->CCMR3 = tmpccmrx;
<>	144:ef7eb2e8f9f7	2699
<>	144:ef7eb2e8f9f7	2700	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	2701	TIMx->CCR5 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	2702
<>	144:ef7eb2e8f9f7	2703	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	2704	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	2705	}
<>	144:ef7eb2e8f9f7	2706
<>	144:ef7eb2e8f9f7	2707	/**
<>	144:ef7eb2e8f9f7	2708	* @brief Timer Ouput Compare 6 configuration
<>	144:ef7eb2e8f9f7	2709	* @param TIMx to select the TIM peripheral
<>	144:ef7eb2e8f9f7	2710	* @param OC_Config: The ouput configuration structure
<>	144:ef7eb2e8f9f7	2711	* @retval None
<>	144:ef7eb2e8f9f7	2712	*/
<>	144:ef7eb2e8f9f7	2713	static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
<>	144:ef7eb2e8f9f7	2714	TIM_OC_InitTypeDef *OC_Config)
<>	144:ef7eb2e8f9f7	2715	{
<>	144:ef7eb2e8f9f7	2716	uint32_t tmpccmrx = 0;
<>	144:ef7eb2e8f9f7	2717	uint32_t tmpccer = 0;
<>	144:ef7eb2e8f9f7	2718	uint32_t tmpcr2 = 0;
<>	144:ef7eb2e8f9f7	2719
<>	144:ef7eb2e8f9f7	2720	/* Disable the output: Reset the CCxE Bit */
<>	144:ef7eb2e8f9f7	2721	TIMx->CCER &= ~TIM_CCER_CC6E;
<>	144:ef7eb2e8f9f7	2722
<>	144:ef7eb2e8f9f7	2723	/* Get the TIMx CCER register value */
<>	144:ef7eb2e8f9f7	2724	tmpccer = TIMx->CCER;
<>	144:ef7eb2e8f9f7	2725	/* Get the TIMx CR2 register value */
<>	144:ef7eb2e8f9f7	2726	tmpcr2 = TIMx->CR2;
<>	144:ef7eb2e8f9f7	2727	/* Get the TIMx CCMR1 register value */
<>	144:ef7eb2e8f9f7	2728	tmpccmrx = TIMx->CCMR3;
<>	144:ef7eb2e8f9f7	2729
<>	144:ef7eb2e8f9f7	2730	/* Reset the Output Compare Mode Bits */
<>	144:ef7eb2e8f9f7	2731	tmpccmrx &= ~(TIM_CCMR3_OC6M);
<>	144:ef7eb2e8f9f7	2732	/* Select the Output Compare Mode */
<>	144:ef7eb2e8f9f7	2733	tmpccmrx \|= (OC_Config->OCMode << 8);
<>	144:ef7eb2e8f9f7	2734
<>	144:ef7eb2e8f9f7	2735	/* Reset the Output Polarity level */
<>	144:ef7eb2e8f9f7	2736	tmpccer &= (uint32_t)~TIM_CCER_CC6P;
<>	144:ef7eb2e8f9f7	2737	/* Set the Output Compare Polarity */
<>	144:ef7eb2e8f9f7	2738	tmpccer \|= (OC_Config->OCPolarity << 20);
<>	144:ef7eb2e8f9f7	2739
<>	144:ef7eb2e8f9f7	2740	if(IS_TIM_BREAK_INSTANCE(TIMx))
<>	144:ef7eb2e8f9f7	2741	{
<>	144:ef7eb2e8f9f7	2742	/* Reset the Output Compare IDLE State */
<>	144:ef7eb2e8f9f7	2743	tmpcr2 &= ~TIM_CR2_OIS6;
<>	144:ef7eb2e8f9f7	2744	/* Set the Output Idle state */
<>	144:ef7eb2e8f9f7	2745	tmpcr2 \|= (OC_Config->OCIdleState << 10);
<>	144:ef7eb2e8f9f7	2746	}
<>	144:ef7eb2e8f9f7	2747
<>	144:ef7eb2e8f9f7	2748	/* Write to TIMx CR2 */
<>	144:ef7eb2e8f9f7	2749	TIMx->CR2 = tmpcr2;
<>	144:ef7eb2e8f9f7	2750
<>	144:ef7eb2e8f9f7	2751	/* Write to TIMx CCMR3 */
<>	144:ef7eb2e8f9f7	2752	TIMx->CCMR3 = tmpccmrx;
<>	144:ef7eb2e8f9f7	2753
<>	144:ef7eb2e8f9f7	2754	/* Set the Capture Compare Register value */
<>	144:ef7eb2e8f9f7	2755	TIMx->CCR6 = OC_Config->Pulse;
<>	144:ef7eb2e8f9f7	2756
<>	144:ef7eb2e8f9f7	2757	/* Write to TIMx CCER */
<>	144:ef7eb2e8f9f7	2758	TIMx->CCER = tmpccer;
<>	144:ef7eb2e8f9f7	2759	}
<>	144:ef7eb2e8f9f7	2760	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
<>	144:ef7eb2e8f9f7	2761	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
<>	144:ef7eb2e8f9f7	2762	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
<>	144:ef7eb2e8f9f7	2763	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
<>	144:ef7eb2e8f9f7	2764	/**
<>	144:ef7eb2e8f9f7	2765	* @}
<>	144:ef7eb2e8f9f7	2766	*/
<>	144:ef7eb2e8f9f7	2767
<>	144:ef7eb2e8f9f7	2768	#endif /* HAL_TIM_MODULE_ENABLED */
<>	144:ef7eb2e8f9f7	2769	/**
<>	144:ef7eb2e8f9f7	2770	* @}
<>	144:ef7eb2e8f9f7	2771	*/
<>	144:ef7eb2e8f9f7	2772
<>	144:ef7eb2e8f9f7	2773	/**
<>	144:ef7eb2e8f9f7	2774	* @}
<>	144:ef7eb2e8f9f7	2775	*/
<>	144:ef7eb2e8f9f7	2776
<>	144:ef7eb2e8f9f7	2777	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Created:	28 Sep 2016
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