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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc_ex.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f3xx_hal_rcc_ex.c
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.1.0
bogdanm 0:9b334a45a8ff 6 * @date 12-Sept-2014
bogdanm 0:9b334a45a8ff 7 * @brief Extended RCC HAL module driver
bogdanm 0:9b334a45a8ff 8 * This file provides firmware functions to manage the following
bogdanm 0:9b334a45a8ff 9 * functionalities RCC Extended peripheral:
bogdanm 0:9b334a45a8ff 10 * + Extended Clock Source configuration functions
bogdanm 0:9b334a45a8ff 11 *
bogdanm 0:9b334a45a8ff 12 ******************************************************************************
bogdanm 0:9b334a45a8ff 13 * @attention
bogdanm 0:9b334a45a8ff 14 *
bogdanm 0:9b334a45a8ff 15 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 16 *
bogdanm 0:9b334a45a8ff 17 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 18 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 19 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 20 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 21 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 22 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 23 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 24 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 25 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 26 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 27 *
bogdanm 0:9b334a45a8ff 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 29 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 31 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 36 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 37 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 38 *
bogdanm 0:9b334a45a8ff 39 ******************************************************************************
bogdanm 0:9b334a45a8ff 40 */
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 43 #include "stm32f3xx_hal.h"
bogdanm 0:9b334a45a8ff 44
bogdanm 0:9b334a45a8ff 45 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 0:9b334a45a8ff 46 * @{
bogdanm 0:9b334a45a8ff 47 */
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @defgroup RCCEx RCC Extended HAL module driver
bogdanm 0:9b334a45a8ff 50 * @brief RCC Extended HAL module driver.
bogdanm 0:9b334a45a8ff 51 * @{
bogdanm 0:9b334a45a8ff 52 */
bogdanm 0:9b334a45a8ff 53
bogdanm 0:9b334a45a8ff 54 #ifdef HAL_RCC_MODULE_ENABLED
bogdanm 0:9b334a45a8ff 55
bogdanm 0:9b334a45a8ff 56 /* Private typedef -----------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 57 /* Private define ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58 /** @defgroup RCCEx_Private_Define RCC Extended Private Define
bogdanm 0:9b334a45a8ff 59 * @{
bogdanm 0:9b334a45a8ff 60 */
bogdanm 0:9b334a45a8ff 61 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
bogdanm 0:9b334a45a8ff 62 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 63 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 64 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
bogdanm 0:9b334a45a8ff 65 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
bogdanm 0:9b334a45a8ff 66 /**
bogdanm 0:9b334a45a8ff 67 * @}
bogdanm 0:9b334a45a8ff 68 */
bogdanm 0:9b334a45a8ff 69
bogdanm 0:9b334a45a8ff 70 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 71 /* Private variables ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 72 /** @defgroup RCCEx_Private_Variables RCC Extented Private Variables
bogdanm 0:9b334a45a8ff 73 * @{
bogdanm 0:9b334a45a8ff 74 */
bogdanm 0:9b334a45a8ff 75 const uint8_t PLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9,
bogdanm 0:9b334a45a8ff 76 10, 11, 12, 13, 14, 15, 16, 16};
bogdanm 0:9b334a45a8ff 77 const uint8_t PredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8,
bogdanm 0:9b334a45a8ff 78 9,10, 11, 12, 13, 14, 15, 16};
bogdanm 0:9b334a45a8ff 79 /**
bogdanm 0:9b334a45a8ff 80 * @}
bogdanm 0:9b334a45a8ff 81 */
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 /* Private function prototypes -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 84 /* Exported functions ---------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 85
bogdanm 0:9b334a45a8ff 86 /** @defgroup RCCEx_Exported_Functions RCC Extended Exported Functions
bogdanm 0:9b334a45a8ff 87 * @{
bogdanm 0:9b334a45a8ff 88 */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 91 * @brief Extended Peripheral Control functions
bogdanm 0:9b334a45a8ff 92 *
bogdanm 0:9b334a45a8ff 93 @verbatim
bogdanm 0:9b334a45a8ff 94 ===============================================================================
bogdanm 0:9b334a45a8ff 95 ##### Extended Peripheral Control functions #####
bogdanm 0:9b334a45a8ff 96 ===============================================================================
bogdanm 0:9b334a45a8ff 97 [..]
bogdanm 0:9b334a45a8ff 98 This subsection provides a set of functions allowing to control the RCC Clocks
bogdanm 0:9b334a45a8ff 99 frequencies.
bogdanm 0:9b334a45a8ff 100 [..]
bogdanm 0:9b334a45a8ff 101 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
bogdanm 0:9b334a45a8ff 102 select the RTC clock source; in this case the Backup domain will be reset in
bogdanm 0:9b334a45a8ff 103 order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm 0:9b334a45a8ff 104 the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 @endverbatim
bogdanm 0:9b334a45a8ff 107 * @{
bogdanm 0:9b334a45a8ff 108 */
bogdanm 0:9b334a45a8ff 109
bogdanm 0:9b334a45a8ff 110 /**
bogdanm 0:9b334a45a8ff 111 * @brief Initializes the RCC extended peripherals clocks according to the specified
bogdanm 0:9b334a45a8ff 112 * parameters in the RCC_PeriphCLKInitTypeDef.
bogdanm 0:9b334a45a8ff 113 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm 0:9b334a45a8ff 114 * contains the configuration information for the Extended Peripherals clocks
bogdanm 0:9b334a45a8ff 115 * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB).
bogdanm 0:9b334a45a8ff 116 *
bogdanm 0:9b334a45a8ff 117 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
bogdanm 0:9b334a45a8ff 118 * the RTC clock source; in this case the Backup domain will be reset in
bogdanm 0:9b334a45a8ff 119 * order to modify the RTC Clock source, as consequence RTC registers (including
bogdanm 0:9b334a45a8ff 120 * the backup registers) and RCC_BDCR register are set to their reset values.
bogdanm 0:9b334a45a8ff 121 *
bogdanm 0:9b334a45a8ff 122 * @retval HAL status
bogdanm 0:9b334a45a8ff 123 */
bogdanm 0:9b334a45a8ff 124 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm 0:9b334a45a8ff 125 {
bogdanm 0:9b334a45a8ff 126 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 127 uint32_t tmpreg = 0;
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /* Check the parameters */
bogdanm 0:9b334a45a8ff 130 assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection));
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132
bogdanm 0:9b334a45a8ff 133 /*---------------------------- RTC configuration -------------------------------*/
bogdanm 0:9b334a45a8ff 134 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
bogdanm 0:9b334a45a8ff 135 {
bogdanm 0:9b334a45a8ff 136 /* Enable Power Clock*/
bogdanm 0:9b334a45a8ff 137 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 138
bogdanm 0:9b334a45a8ff 139 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 140 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 143 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 144
bogdanm 0:9b334a45a8ff 145 while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm 0:9b334a45a8ff 146 {
bogdanm 0:9b334a45a8ff 147 if((HAL_GetTick()-tickstart) > DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 148 {
bogdanm 0:9b334a45a8ff 149 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 150 }
bogdanm 0:9b334a45a8ff 151 }
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 /* Reset the Backup domain only if the RTC Clock source selction is modified */
bogdanm 0:9b334a45a8ff 154 if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
bogdanm 0:9b334a45a8ff 155 {
bogdanm 0:9b334a45a8ff 156 /* Store the content of BDCR register before the reset of Backup Domain */
bogdanm 0:9b334a45a8ff 157 tmpreg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
bogdanm 0:9b334a45a8ff 158 /* RTC Clock selection can be changed only if the Backup Domain is reset */
bogdanm 0:9b334a45a8ff 159 __HAL_RCC_BACKUPRESET_FORCE();
bogdanm 0:9b334a45a8ff 160 __HAL_RCC_BACKUPRESET_RELEASE();
bogdanm 0:9b334a45a8ff 161 /* Restore the Content of BDCR register */
bogdanm 0:9b334a45a8ff 162 RCC->BDCR = tmpreg;
bogdanm 0:9b334a45a8ff 163 }
bogdanm 0:9b334a45a8ff 164
bogdanm 0:9b334a45a8ff 165 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
bogdanm 0:9b334a45a8ff 166 if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
bogdanm 0:9b334a45a8ff 167 {
bogdanm 0:9b334a45a8ff 168 /* Get timeout */
bogdanm 0:9b334a45a8ff 169 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 170
bogdanm 0:9b334a45a8ff 171 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 172 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 173 {
bogdanm 0:9b334a45a8ff 174 if((HAL_GetTick()-tickstart) > LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 175 {
bogdanm 0:9b334a45a8ff 176 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 177 }
bogdanm 0:9b334a45a8ff 178 }
bogdanm 0:9b334a45a8ff 179 }
bogdanm 0:9b334a45a8ff 180 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
bogdanm 0:9b334a45a8ff 181 }
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /*------------------------------- USART1 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 184 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
bogdanm 0:9b334a45a8ff 185 {
bogdanm 0:9b334a45a8ff 186 /* Check the parameters */
bogdanm 0:9b334a45a8ff 187 assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
bogdanm 0:9b334a45a8ff 188
bogdanm 0:9b334a45a8ff 189 /* Configure the USART1 clock source */
bogdanm 0:9b334a45a8ff 190 __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
bogdanm 0:9b334a45a8ff 191 }
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /*----------------------------- USART2 Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 194 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
bogdanm 0:9b334a45a8ff 195 {
bogdanm 0:9b334a45a8ff 196 /* Check the parameters */
bogdanm 0:9b334a45a8ff 197 assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
bogdanm 0:9b334a45a8ff 198
bogdanm 0:9b334a45a8ff 199 /* Configure the USART2 clock source */
bogdanm 0:9b334a45a8ff 200 __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
bogdanm 0:9b334a45a8ff 201 }
bogdanm 0:9b334a45a8ff 202
bogdanm 0:9b334a45a8ff 203 /*------------------------------ USART3 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 204 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
bogdanm 0:9b334a45a8ff 205 {
bogdanm 0:9b334a45a8ff 206 /* Check the parameters */
bogdanm 0:9b334a45a8ff 207 assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
bogdanm 0:9b334a45a8ff 208
bogdanm 0:9b334a45a8ff 209 /* Configure the USART3 clock source */
bogdanm 0:9b334a45a8ff 210 __HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
bogdanm 0:9b334a45a8ff 211 }
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 /*------------------------------ I2C1 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 214 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
bogdanm 0:9b334a45a8ff 215 {
bogdanm 0:9b334a45a8ff 216 /* Check the parameters */
bogdanm 0:9b334a45a8ff 217 assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
bogdanm 0:9b334a45a8ff 218
bogdanm 0:9b334a45a8ff 219 /* Configure the I2C1 clock source */
bogdanm 0:9b334a45a8ff 220 __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
bogdanm 0:9b334a45a8ff 221 }
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 #if defined(STM32F302xE) || defined(STM32F303xE) || \
bogdanm 0:9b334a45a8ff 224 defined(STM32F302xC) || defined(STM32F303xC) || \
bogdanm 0:9b334a45a8ff 225 defined(STM32F302x8) || \
bogdanm 0:9b334a45a8ff 226 defined(STM32F373xC)
bogdanm 0:9b334a45a8ff 227 /*------------------------------ USB Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 228 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
bogdanm 0:9b334a45a8ff 229 {
bogdanm 0:9b334a45a8ff 230 /* Check the parameters */
bogdanm 0:9b334a45a8ff 231 assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->USBClockSelection));
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /* Configure the USB clock source */
bogdanm 0:9b334a45a8ff 234 __HAL_RCC_USB_CONFIG(PeriphClkInit->USBClockSelection);
bogdanm 0:9b334a45a8ff 235 }
bogdanm 0:9b334a45a8ff 236
bogdanm 0:9b334a45a8ff 237 #endif /* STM32F302xE || STM32F303xE || */
bogdanm 0:9b334a45a8ff 238 /* STM32F302xC || STM32F303xC || */
bogdanm 0:9b334a45a8ff 239 /* STM32F302x8 || */
bogdanm 0:9b334a45a8ff 240 /* STM32F373xC */
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 243 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 244 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 0:9b334a45a8ff 245 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 246
bogdanm 0:9b334a45a8ff 247 /*------------------------------ I2C2 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 248 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
bogdanm 0:9b334a45a8ff 249 {
bogdanm 0:9b334a45a8ff 250 /* Check the parameters */
bogdanm 0:9b334a45a8ff 251 assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
bogdanm 0:9b334a45a8ff 252
bogdanm 0:9b334a45a8ff 253 /* Configure the I2C2 clock source */
bogdanm 0:9b334a45a8ff 254 __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
bogdanm 0:9b334a45a8ff 255 }
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 258 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 259 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
bogdanm 0:9b334a45a8ff 260 /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 261
bogdanm 0:9b334a45a8ff 262 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 263 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 264
bogdanm 0:9b334a45a8ff 265 /*------------------------------ I2C3 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 266 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
bogdanm 0:9b334a45a8ff 267 {
bogdanm 0:9b334a45a8ff 268 /* Check the parameters */
bogdanm 0:9b334a45a8ff 269 assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
bogdanm 0:9b334a45a8ff 270
bogdanm 0:9b334a45a8ff 271 /* Configure the I2C3 clock source */
bogdanm 0:9b334a45a8ff 272 __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
bogdanm 0:9b334a45a8ff 273 }
bogdanm 0:9b334a45a8ff 274 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 275 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 276
bogdanm 0:9b334a45a8ff 277 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 278 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 0:9b334a45a8ff 279
bogdanm 0:9b334a45a8ff 280 /*------------------------------ UART4 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 281 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
bogdanm 0:9b334a45a8ff 282 {
bogdanm 0:9b334a45a8ff 283 /* Check the parameters */
bogdanm 0:9b334a45a8ff 284 assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
bogdanm 0:9b334a45a8ff 285
bogdanm 0:9b334a45a8ff 286 /* Configure the UART4 clock source */
bogdanm 0:9b334a45a8ff 287 __HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
bogdanm 0:9b334a45a8ff 288 }
bogdanm 0:9b334a45a8ff 289
bogdanm 0:9b334a45a8ff 290 /*------------------------------ UART5 Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 291 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
bogdanm 0:9b334a45a8ff 292 {
bogdanm 0:9b334a45a8ff 293 /* Check the parameters */
bogdanm 0:9b334a45a8ff 294 assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
bogdanm 0:9b334a45a8ff 295
bogdanm 0:9b334a45a8ff 296 /* Configure the UART5 clock source */
bogdanm 0:9b334a45a8ff 297 __HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
bogdanm 0:9b334a45a8ff 298 }
bogdanm 0:9b334a45a8ff 299
bogdanm 0:9b334a45a8ff 300 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 301 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 0:9b334a45a8ff 302
bogdanm 0:9b334a45a8ff 303 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 304 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 305 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 306 /*------------------------------ I2S Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 307 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
bogdanm 0:9b334a45a8ff 308 {
bogdanm 0:9b334a45a8ff 309 /* Check the parameters */
bogdanm 0:9b334a45a8ff 310 assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 /* Configure the I2S clock source */
bogdanm 0:9b334a45a8ff 313 __HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
bogdanm 0:9b334a45a8ff 314 }
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 317 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 318 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 319
bogdanm 0:9b334a45a8ff 320 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /*------------------------------ ADC1 clock Configuration ------------------*/
bogdanm 0:9b334a45a8ff 323 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
bogdanm 0:9b334a45a8ff 324 {
bogdanm 0:9b334a45a8ff 325 /* Check the parameters */
bogdanm 0:9b334a45a8ff 326 assert_param(IS_RCC_ADC1PLLCLK_DIV(PeriphClkInit->Adc1ClockSelection));
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 /* Configure the ADC1 clock source */
bogdanm 0:9b334a45a8ff 329 __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
bogdanm 0:9b334a45a8ff 330 }
bogdanm 0:9b334a45a8ff 331
bogdanm 0:9b334a45a8ff 332 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 335 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 336 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /*------------------------------ ADC1 & ADC2 clock Configuration -------------*/
bogdanm 0:9b334a45a8ff 339 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
bogdanm 0:9b334a45a8ff 340 {
bogdanm 0:9b334a45a8ff 341 /* Check the parameters */
bogdanm 0:9b334a45a8ff 342 assert_param(IS_RCC_ADC12PLLCLK_DIV(PeriphClkInit->Adc12ClockSelection));
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 /* Configure the ADC12 clock source */
bogdanm 0:9b334a45a8ff 345 __HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
bogdanm 0:9b334a45a8ff 346 }
bogdanm 0:9b334a45a8ff 347
bogdanm 0:9b334a45a8ff 348 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 349 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 350 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 0:9b334a45a8ff 351
bogdanm 0:9b334a45a8ff 352 #if defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 353 defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /*------------------------------ ADC3 & ADC4 clock Configuration -------------*/
bogdanm 0:9b334a45a8ff 356 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC34) == RCC_PERIPHCLK_ADC34)
bogdanm 0:9b334a45a8ff 357 {
bogdanm 0:9b334a45a8ff 358 /* Check the parameters */
bogdanm 0:9b334a45a8ff 359 assert_param(IS_RCC_ADC34PLLCLK_DIV(PeriphClkInit->Adc34ClockSelection));
bogdanm 0:9b334a45a8ff 360
bogdanm 0:9b334a45a8ff 361 /* Configure the ADC34 clock source */
bogdanm 0:9b334a45a8ff 362 __HAL_RCC_ADC34_CONFIG(PeriphClkInit->Adc34ClockSelection);
bogdanm 0:9b334a45a8ff 363 }
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 366 /* STM32F303xC || STM32F358xx */
bogdanm 0:9b334a45a8ff 367
bogdanm 0:9b334a45a8ff 368 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 369
bogdanm 0:9b334a45a8ff 370 /*------------------------------ ADC1 clock Configuration ------------------*/
bogdanm 0:9b334a45a8ff 371 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC1) == RCC_PERIPHCLK_ADC1)
bogdanm 0:9b334a45a8ff 372 {
bogdanm 0:9b334a45a8ff 373 /* Check the parameters */
bogdanm 0:9b334a45a8ff 374 assert_param(IS_RCC_ADC1PCLK2_DIV(PeriphClkInit->Adc1ClockSelection));
bogdanm 0:9b334a45a8ff 375
bogdanm 0:9b334a45a8ff 376 /* Configure the ADC1 clock source */
bogdanm 0:9b334a45a8ff 377 __HAL_RCC_ADC1_CONFIG(PeriphClkInit->Adc1ClockSelection);
bogdanm 0:9b334a45a8ff 378 }
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380 #endif /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 383 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 384 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 0:9b334a45a8ff 385 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /*------------------------------ TIM1 clock Configuration ----------------*/
bogdanm 0:9b334a45a8ff 388 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM1) == RCC_PERIPHCLK_TIM1)
bogdanm 0:9b334a45a8ff 389 {
bogdanm 0:9b334a45a8ff 390 /* Check the parameters */
bogdanm 0:9b334a45a8ff 391 assert_param(IS_RCC_TIM1CLKSOURCE(PeriphClkInit->Tim1ClockSelection));
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 /* Configure the TIM1 clock source */
bogdanm 0:9b334a45a8ff 394 __HAL_RCC_TIM1_CONFIG(PeriphClkInit->Tim1ClockSelection);
bogdanm 0:9b334a45a8ff 395 }
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 398 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 399 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 0:9b334a45a8ff 400 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 #if defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 403 defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 0:9b334a45a8ff 404
bogdanm 0:9b334a45a8ff 405 /*------------------------------ TIM8 clock Configuration ----------------*/
bogdanm 0:9b334a45a8ff 406 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM8) == RCC_PERIPHCLK_TIM8)
bogdanm 0:9b334a45a8ff 407 {
bogdanm 0:9b334a45a8ff 408 /* Check the parameters */
bogdanm 0:9b334a45a8ff 409 assert_param(IS_RCC_TIM8CLKSOURCE(PeriphClkInit->Tim8ClockSelection));
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /* Configure the TIM8 clock source */
bogdanm 0:9b334a45a8ff 412 __HAL_RCC_TIM8_CONFIG(PeriphClkInit->Tim8ClockSelection);
bogdanm 0:9b334a45a8ff 413 }
bogdanm 0:9b334a45a8ff 414
bogdanm 0:9b334a45a8ff 415 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 416 /* STM32F303xC || STM32F358xx */
bogdanm 0:9b334a45a8ff 417
bogdanm 0:9b334a45a8ff 418 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 419
bogdanm 0:9b334a45a8ff 420 /*------------------------------ TIM15 clock Configuration ----------------*/
bogdanm 0:9b334a45a8ff 421 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
bogdanm 0:9b334a45a8ff 422 {
bogdanm 0:9b334a45a8ff 423 /* Check the parameters */
bogdanm 0:9b334a45a8ff 424 assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
bogdanm 0:9b334a45a8ff 425
bogdanm 0:9b334a45a8ff 426 /* Configure the TIM15 clock source */
bogdanm 0:9b334a45a8ff 427 __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
bogdanm 0:9b334a45a8ff 428 }
bogdanm 0:9b334a45a8ff 429
bogdanm 0:9b334a45a8ff 430 /*------------------------------ TIM16 clock Configuration ----------------*/
bogdanm 0:9b334a45a8ff 431 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
bogdanm 0:9b334a45a8ff 432 {
bogdanm 0:9b334a45a8ff 433 /* Check the parameters */
bogdanm 0:9b334a45a8ff 434 assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 /* Configure the TIM16 clock source */
bogdanm 0:9b334a45a8ff 437 __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
bogdanm 0:9b334a45a8ff 438 }
bogdanm 0:9b334a45a8ff 439
bogdanm 0:9b334a45a8ff 440 /*------------------------------ TIM17 clock Configuration ----------------*/
bogdanm 0:9b334a45a8ff 441 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
bogdanm 0:9b334a45a8ff 442 {
bogdanm 0:9b334a45a8ff 443 /* Check the parameters */
bogdanm 0:9b334a45a8ff 444 assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
bogdanm 0:9b334a45a8ff 445
bogdanm 0:9b334a45a8ff 446 /* Configure the TIM17 clock source */
bogdanm 0:9b334a45a8ff 447 __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
bogdanm 0:9b334a45a8ff 448 }
bogdanm 0:9b334a45a8ff 449
bogdanm 0:9b334a45a8ff 450 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 #if defined(STM32F334x8)
bogdanm 0:9b334a45a8ff 453
bogdanm 0:9b334a45a8ff 454 /*------------------------------ HRTIM1 clock Configuration ----------------*/
bogdanm 0:9b334a45a8ff 455 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HRTIM1) == RCC_PERIPHCLK_HRTIM1)
bogdanm 0:9b334a45a8ff 456 {
bogdanm 0:9b334a45a8ff 457 /* Check the parameters */
bogdanm 0:9b334a45a8ff 458 assert_param(IS_RCC_HRTIM1CLKSOURCE(PeriphClkInit->Hrtim1ClockSelection));
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* Configure the HRTIM1 clock source */
bogdanm 0:9b334a45a8ff 461 __HAL_RCC_HRTIM1_CONFIG(PeriphClkInit->Hrtim1ClockSelection);
bogdanm 0:9b334a45a8ff 462 }
bogdanm 0:9b334a45a8ff 463
bogdanm 0:9b334a45a8ff 464 #endif /* STM32F334x8 */
bogdanm 0:9b334a45a8ff 465
bogdanm 0:9b334a45a8ff 466 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 /*------------------------------ SDADC clock Configuration -------------------*/
bogdanm 0:9b334a45a8ff 469 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDADC) == RCC_PERIPHCLK_SDADC)
bogdanm 0:9b334a45a8ff 470 {
bogdanm 0:9b334a45a8ff 471 /* Check the parameters */
bogdanm 0:9b334a45a8ff 472 assert_param(IS_RCC_SDADCSYSCLK_DIV(PeriphClkInit->SdadcClockSelection));
bogdanm 0:9b334a45a8ff 473
bogdanm 0:9b334a45a8ff 474 /* Configure the SDADC clock prescaler */
bogdanm 0:9b334a45a8ff 475 __HAL_RCC_SDADC_CONFIG(PeriphClkInit->SdadcClockSelection);
bogdanm 0:9b334a45a8ff 476 }
bogdanm 0:9b334a45a8ff 477
bogdanm 0:9b334a45a8ff 478 /*------------------------------ CEC clock Configuration -------------------*/
bogdanm 0:9b334a45a8ff 479 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
bogdanm 0:9b334a45a8ff 480 {
bogdanm 0:9b334a45a8ff 481 /* Check the parameters */
bogdanm 0:9b334a45a8ff 482 assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
bogdanm 0:9b334a45a8ff 483
bogdanm 0:9b334a45a8ff 484 /* Configure the CEC clock source */
bogdanm 0:9b334a45a8ff 485 __HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
bogdanm 0:9b334a45a8ff 486 }
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 #endif /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 489
bogdanm 0:9b334a45a8ff 490 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /*------------------------------ TIM2 clock Configuration -------------------*/
bogdanm 0:9b334a45a8ff 493 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM2) == RCC_PERIPHCLK_TIM2)
bogdanm 0:9b334a45a8ff 494 {
bogdanm 0:9b334a45a8ff 495 /* Check the parameters */
bogdanm 0:9b334a45a8ff 496 assert_param(IS_RCC_TIM2CLKSOURCE(PeriphClkInit->Tim2ClockSelection));
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /* Configure the CEC clock source */
bogdanm 0:9b334a45a8ff 499 __HAL_RCC_TIM2_CONFIG(PeriphClkInit->Tim2ClockSelection);
bogdanm 0:9b334a45a8ff 500 }
bogdanm 0:9b334a45a8ff 501
bogdanm 0:9b334a45a8ff 502 /*------------------------------ TIM3 clock Configuration -------------------*/
bogdanm 0:9b334a45a8ff 503 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM34) == RCC_PERIPHCLK_TIM34)
bogdanm 0:9b334a45a8ff 504 {
bogdanm 0:9b334a45a8ff 505 /* Check the parameters */
bogdanm 0:9b334a45a8ff 506 assert_param(IS_RCC_TIM3CLKSOURCE(PeriphClkInit->Tim34ClockSelection));
bogdanm 0:9b334a45a8ff 507
bogdanm 0:9b334a45a8ff 508 /* Configure the CEC clock source */
bogdanm 0:9b334a45a8ff 509 __HAL_RCC_TIM34_CONFIG(PeriphClkInit->Tim34ClockSelection);
bogdanm 0:9b334a45a8ff 510 }
bogdanm 0:9b334a45a8ff 511
bogdanm 0:9b334a45a8ff 512 /*------------------------------ TIM15 clock Configuration ------------------*/
bogdanm 0:9b334a45a8ff 513 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM15) == RCC_PERIPHCLK_TIM15)
bogdanm 0:9b334a45a8ff 514 {
bogdanm 0:9b334a45a8ff 515 /* Check the parameters */
bogdanm 0:9b334a45a8ff 516 assert_param(IS_RCC_TIM15CLKSOURCE(PeriphClkInit->Tim15ClockSelection));
bogdanm 0:9b334a45a8ff 517
bogdanm 0:9b334a45a8ff 518 /* Configure the CEC clock source */
bogdanm 0:9b334a45a8ff 519 __HAL_RCC_TIM15_CONFIG(PeriphClkInit->Tim15ClockSelection);
bogdanm 0:9b334a45a8ff 520 }
bogdanm 0:9b334a45a8ff 521
bogdanm 0:9b334a45a8ff 522 /*------------------------------ TIM16 clock Configuration ------------------*/
bogdanm 0:9b334a45a8ff 523 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM16) == RCC_PERIPHCLK_TIM16)
bogdanm 0:9b334a45a8ff 524 {
bogdanm 0:9b334a45a8ff 525 /* Check the parameters */
bogdanm 0:9b334a45a8ff 526 assert_param(IS_RCC_TIM16CLKSOURCE(PeriphClkInit->Tim16ClockSelection));
bogdanm 0:9b334a45a8ff 527
bogdanm 0:9b334a45a8ff 528 /* Configure the CEC clock source */
bogdanm 0:9b334a45a8ff 529 __HAL_RCC_TIM16_CONFIG(PeriphClkInit->Tim16ClockSelection);
bogdanm 0:9b334a45a8ff 530 }
bogdanm 0:9b334a45a8ff 531
bogdanm 0:9b334a45a8ff 532 /*------------------------------ TIM17 clock Configuration ------------------*/
bogdanm 0:9b334a45a8ff 533 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM17) == RCC_PERIPHCLK_TIM17)
bogdanm 0:9b334a45a8ff 534 {
bogdanm 0:9b334a45a8ff 535 /* Check the parameters */
bogdanm 0:9b334a45a8ff 536 assert_param(IS_RCC_TIM17CLKSOURCE(PeriphClkInit->Tim17ClockSelection));
bogdanm 0:9b334a45a8ff 537
bogdanm 0:9b334a45a8ff 538 /* Configure the CEC clock source */
bogdanm 0:9b334a45a8ff 539 __HAL_RCC_TIM17_CONFIG(PeriphClkInit->Tim17ClockSelection);
bogdanm 0:9b334a45a8ff 540 }
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 0:9b334a45a8ff 543
bogdanm 0:9b334a45a8ff 544 #if defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 0:9b334a45a8ff 545 /*------------------------------ TIM20 clock Configuration ------------------*/
bogdanm 0:9b334a45a8ff 546 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM20) == RCC_PERIPHCLK_TIM20)
bogdanm 0:9b334a45a8ff 547 {
bogdanm 0:9b334a45a8ff 548 /* Check the parameters */
bogdanm 0:9b334a45a8ff 549 assert_param(IS_RCC_TIM20CLKSOURCE(PeriphClkInit->Tim20ClockSelection));
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* Configure the CEC clock source */
bogdanm 0:9b334a45a8ff 552 __HAL_RCC_TIM20_CONFIG(PeriphClkInit->Tim20ClockSelection);
bogdanm 0:9b334a45a8ff 553 }
bogdanm 0:9b334a45a8ff 554 #endif /* STM32F303xE || STM32F398xx */
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 return HAL_OK;
bogdanm 0:9b334a45a8ff 558 }
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /**
bogdanm 0:9b334a45a8ff 561 * @brief Get the RCC_ClkInitStruct according to the internal
bogdanm 0:9b334a45a8ff 562 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 563 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
bogdanm 0:9b334a45a8ff 564 * returns the configuration information for the Extended Peripherals clocks
bogdanm 0:9b334a45a8ff 565 * (ADC, CEC, I2C, I2S, SDADC, HRTIM, TIM, USART, RTC and USB clocks).
bogdanm 0:9b334a45a8ff 566 * @retval None
bogdanm 0:9b334a45a8ff 567 */
bogdanm 0:9b334a45a8ff 568 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
bogdanm 0:9b334a45a8ff 569 {
bogdanm 0:9b334a45a8ff 570 /* Set all possible values for the extended clock type parameter------------*/
bogdanm 0:9b334a45a8ff 571 /* Common part first */
bogdanm 0:9b334a45a8ff 572 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
bogdanm 0:9b334a45a8ff 573 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC;
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 /* Get the RTC configuration --------------------------------------------*/
bogdanm 0:9b334a45a8ff 576 PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
bogdanm 0:9b334a45a8ff 577 /* Get the USART1 clock configuration --------------------------------------------*/
bogdanm 0:9b334a45a8ff 578 PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
bogdanm 0:9b334a45a8ff 579 /* Get the USART2 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 580 PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE();
bogdanm 0:9b334a45a8ff 581 /* Get the USART3 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 582 PeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE();
bogdanm 0:9b334a45a8ff 583 /* Get the I2C1 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 584 PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 #if defined(STM32F302xE) || defined(STM32F303xE) || \
bogdanm 0:9b334a45a8ff 587 defined(STM32F302xC) || defined(STM32F303xC) || \
bogdanm 0:9b334a45a8ff 588 defined(STM32F302x8) || \
bogdanm 0:9b334a45a8ff 589 defined(STM32F373xC)
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
bogdanm 0:9b334a45a8ff 592 /* Get the USB clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 593 PeriphClkInit->USBClockSelection = __HAL_RCC_GET_USB_SOURCE();
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 #endif /* STM32F302xE || STM32F303xE || */
bogdanm 0:9b334a45a8ff 596 /* STM32F302xC || STM32F303xC || */
bogdanm 0:9b334a45a8ff 597 /* STM32F302x8 || */
bogdanm 0:9b334a45a8ff 598 /* STM32F373xC */
bogdanm 0:9b334a45a8ff 599
bogdanm 0:9b334a45a8ff 600 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 601 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 602 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 0:9b334a45a8ff 603 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 604
bogdanm 0:9b334a45a8ff 605 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C2;
bogdanm 0:9b334a45a8ff 606 /* Get the I2C2 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 607 PeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE();
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 610 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 611 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
bogdanm 0:9b334a45a8ff 612 /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 613
bogdanm 0:9b334a45a8ff 614 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 615 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
bogdanm 0:9b334a45a8ff 618 /* Get the I2C3 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 619 PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
bogdanm 0:9b334a45a8ff 620
bogdanm 0:9b334a45a8ff 621 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 622 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 623
bogdanm 0:9b334a45a8ff 624 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 625 defined(STM32F302xC) || defined(STM32F303xC) ||defined(STM32F358xx)
bogdanm 0:9b334a45a8ff 626
bogdanm 0:9b334a45a8ff 627 PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5);
bogdanm 0:9b334a45a8ff 628 /* Get the UART4 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 629 PeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE();
bogdanm 0:9b334a45a8ff 630 /* Get the UART5 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 631 PeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE();
bogdanm 0:9b334a45a8ff 632
bogdanm 0:9b334a45a8ff 633 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 634 /* STM32F302xC || STM32F303xC || STM32F358xx */
bogdanm 0:9b334a45a8ff 635
bogdanm 0:9b334a45a8ff 636 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 637 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 638 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S;
bogdanm 0:9b334a45a8ff 641 /* Get the I2S clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 642 PeriphClkInit->I2sClockSelection = __HAL_RCC_GET_I2S_SOURCE();
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 645 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 646 /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
bogdanm 0:9b334a45a8ff 647
bogdanm 0:9b334a45a8ff 648 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 0:9b334a45a8ff 649 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 650
bogdanm 0:9b334a45a8ff 651 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC1;
bogdanm 0:9b334a45a8ff 652 /* Get the ADC1 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 653 PeriphClkInit->Adc1ClockSelection = __HAL_RCC_GET_ADC1_SOURCE();
bogdanm 0:9b334a45a8ff 654
bogdanm 0:9b334a45a8ff 655 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx || */
bogdanm 0:9b334a45a8ff 656 /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 657
bogdanm 0:9b334a45a8ff 658 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 659 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 660 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
bogdanm 0:9b334a45a8ff 661
bogdanm 0:9b334a45a8ff 662 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC12;
bogdanm 0:9b334a45a8ff 663 /* Get the ADC1 & ADC2 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 664 PeriphClkInit->Adc12ClockSelection = __HAL_RCC_GET_ADC12_SOURCE();
bogdanm 0:9b334a45a8ff 665
bogdanm 0:9b334a45a8ff 666 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 667 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 668 /* STM32F303x8 || STM32F334x8 || STM32F328xx */
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 #if defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 671 defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 0:9b334a45a8ff 672
bogdanm 0:9b334a45a8ff 673 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC34;
bogdanm 0:9b334a45a8ff 674 /* Get the ADC3 & ADC4 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 675 PeriphClkInit->Adc34ClockSelection = __HAL_RCC_GET_ADC34_SOURCE();
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 678 /* STM32F303xC || STM32F358xx */
bogdanm 0:9b334a45a8ff 679
bogdanm 0:9b334a45a8ff 680 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 681 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 682 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 0:9b334a45a8ff 683 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM1;
bogdanm 0:9b334a45a8ff 686 /* Get the TIM1 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 687 PeriphClkInit->Tim1ClockSelection = __HAL_RCC_GET_TIM1_SOURCE();
bogdanm 0:9b334a45a8ff 688
bogdanm 0:9b334a45a8ff 689 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 690 /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 691 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 0:9b334a45a8ff 692 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694 #if defined(STM32F303xE) || defined(STM32F398xx) || \
bogdanm 0:9b334a45a8ff 695 defined(STM32F303xC) || defined(STM32F358xx)
bogdanm 0:9b334a45a8ff 696
bogdanm 0:9b334a45a8ff 697 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM8;
bogdanm 0:9b334a45a8ff 698 /* Get the TIM8 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 699 PeriphClkInit->Tim8ClockSelection = __HAL_RCC_GET_TIM8_SOURCE();
bogdanm 0:9b334a45a8ff 700
bogdanm 0:9b334a45a8ff 701 #endif /* STM32F303xE || STM32F398xx || */
bogdanm 0:9b334a45a8ff 702 /* STM32F303xC || STM32F358xx */
bogdanm 0:9b334a45a8ff 703
bogdanm 0:9b334a45a8ff 704 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 PeriphClkInit->PeriphClockSelection |= (RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17);
bogdanm 0:9b334a45a8ff 707 /* Get the TIM15 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 708 PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
bogdanm 0:9b334a45a8ff 709 /* Get the TIM16 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 710 PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
bogdanm 0:9b334a45a8ff 711 /* Get the TIM17 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 712 PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
bogdanm 0:9b334a45a8ff 713
bogdanm 0:9b334a45a8ff 714 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 715
bogdanm 0:9b334a45a8ff 716 #if defined(STM32F334x8)
bogdanm 0:9b334a45a8ff 717
bogdanm 0:9b334a45a8ff 718 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_HRTIM1;
bogdanm 0:9b334a45a8ff 719 /* Get the HRTIM1 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 720 PeriphClkInit->Hrtim1ClockSelection = __HAL_RCC_GET_HRTIM1_SOURCE();
bogdanm 0:9b334a45a8ff 721
bogdanm 0:9b334a45a8ff 722 #endif /* STM32F334x8 */
bogdanm 0:9b334a45a8ff 723
bogdanm 0:9b334a45a8ff 724 #if defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 725
bogdanm 0:9b334a45a8ff 726 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SDADC;
bogdanm 0:9b334a45a8ff 727 /* Get the SDADC clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 728 PeriphClkInit->SdadcClockSelection = __HAL_RCC_GET_SDADC_SOURCE();
bogdanm 0:9b334a45a8ff 729
bogdanm 0:9b334a45a8ff 730 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_CEC;
bogdanm 0:9b334a45a8ff 731 /* Get the CEC clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 732 PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
bogdanm 0:9b334a45a8ff 733
bogdanm 0:9b334a45a8ff 734 #endif /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 735
bogdanm 0:9b334a45a8ff 736 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 0:9b334a45a8ff 737
bogdanm 0:9b334a45a8ff 738 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM2;
bogdanm 0:9b334a45a8ff 739 /* Get the TIM2 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 740 PeriphClkInit->Tim2ClockSelection = __HAL_RCC_GET_TIM2_SOURCE();
bogdanm 0:9b334a45a8ff 741
bogdanm 0:9b334a45a8ff 742 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM34;
bogdanm 0:9b334a45a8ff 743 /* Get the TIM3 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 744 PeriphClkInit->Tim34ClockSelection = __HAL_RCC_GET_TIM34_SOURCE();
bogdanm 0:9b334a45a8ff 745
bogdanm 0:9b334a45a8ff 746 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM15;
bogdanm 0:9b334a45a8ff 747 /* Get the TIM15 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 748 PeriphClkInit->Tim15ClockSelection = __HAL_RCC_GET_TIM15_SOURCE();
bogdanm 0:9b334a45a8ff 749
bogdanm 0:9b334a45a8ff 750 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM16;
bogdanm 0:9b334a45a8ff 751 /* Get the TIM16 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 752 PeriphClkInit->Tim16ClockSelection = __HAL_RCC_GET_TIM16_SOURCE();
bogdanm 0:9b334a45a8ff 753
bogdanm 0:9b334a45a8ff 754 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM17;
bogdanm 0:9b334a45a8ff 755 /* Get the TIM17 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 756 PeriphClkInit->Tim17ClockSelection = __HAL_RCC_GET_TIM17_SOURCE();
bogdanm 0:9b334a45a8ff 757
bogdanm 0:9b334a45a8ff 758 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 0:9b334a45a8ff 759
bogdanm 0:9b334a45a8ff 760 #if defined (STM32F303xE) || defined(STM32F398xx)
bogdanm 0:9b334a45a8ff 761 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_TIM20;
bogdanm 0:9b334a45a8ff 762 /* Get the TIM20 clock configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 763 PeriphClkInit->Tim20ClockSelection = __HAL_RCC_GET_TIM20_SOURCE();
bogdanm 0:9b334a45a8ff 764 #endif /* STM32F303xE || STM32F398xx */
bogdanm 0:9b334a45a8ff 765 }
bogdanm 0:9b334a45a8ff 766
bogdanm 0:9b334a45a8ff 767 /**
bogdanm 0:9b334a45a8ff 768 * @brief Initializes the RCC Oscillators according to the specified parameters in the
bogdanm 0:9b334a45a8ff 769 * RCC_OscInitTypeDef.
bogdanm 0:9b334a45a8ff 770 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 771 * contains the configuration information for the RCC Oscillators.
bogdanm 0:9b334a45a8ff 772 * @note The PLL is not disabled when used as system clock.
bogdanm 0:9b334a45a8ff 773 * @retval HAL status
bogdanm 0:9b334a45a8ff 774 */
bogdanm 0:9b334a45a8ff 775 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 776 {
bogdanm 0:9b334a45a8ff 777 uint32_t tickstart = 0;
bogdanm 0:9b334a45a8ff 778
bogdanm 0:9b334a45a8ff 779 /* Check the parameters */
bogdanm 0:9b334a45a8ff 780 assert_param(RCC_OscInitStruct != HAL_NULL);
bogdanm 0:9b334a45a8ff 781 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
bogdanm 0:9b334a45a8ff 782 /*------------------------------- HSE Configuration ------------------------*/
bogdanm 0:9b334a45a8ff 783 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
bogdanm 0:9b334a45a8ff 784 {
bogdanm 0:9b334a45a8ff 785 /* Check the parameters */
bogdanm 0:9b334a45a8ff 786 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
bogdanm 0:9b334a45a8ff 787 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
bogdanm 0:9b334a45a8ff 788 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) ||
bogdanm 0:9b334a45a8ff 789 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
bogdanm 0:9b334a45a8ff 790 {
bogdanm 0:9b334a45a8ff 791 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
bogdanm 0:9b334a45a8ff 792 {
bogdanm 0:9b334a45a8ff 793 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 794 }
bogdanm 0:9b334a45a8ff 795 }
bogdanm 0:9b334a45a8ff 796 else
bogdanm 0:9b334a45a8ff 797 {
bogdanm 0:9b334a45a8ff 798 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
bogdanm 0:9b334a45a8ff 799 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
bogdanm 0:9b334a45a8ff 800
bogdanm 0:9b334a45a8ff 801 /* Get timeout */
bogdanm 0:9b334a45a8ff 802 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 803
bogdanm 0:9b334a45a8ff 804 /* Wait till HSE is bypassed or disabled */
bogdanm 0:9b334a45a8ff 805 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 806 {
bogdanm 0:9b334a45a8ff 807 if((HAL_GetTick()-tickstart) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 808 {
bogdanm 0:9b334a45a8ff 809 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 810 }
bogdanm 0:9b334a45a8ff 811 }
bogdanm 0:9b334a45a8ff 812
bogdanm 0:9b334a45a8ff 813 /* Set the new HSE configuration ---------------------------------------*/
bogdanm 0:9b334a45a8ff 814 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
bogdanm 0:9b334a45a8ff 815
bogdanm 0:9b334a45a8ff 816 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 817 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 0:9b334a45a8ff 818 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 0:9b334a45a8ff 819 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 820 /* Configure the HSE predivision factor --------------------------------*/
bogdanm 0:9b334a45a8ff 821 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
bogdanm 0:9b334a45a8ff 822 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 823 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 0:9b334a45a8ff 824 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 825 /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 826
bogdanm 0:9b334a45a8ff 827 /* Check the HSE State */
bogdanm 0:9b334a45a8ff 828 if(RCC_OscInitStruct->HSEState == RCC_HSE_ON)
bogdanm 0:9b334a45a8ff 829 {
bogdanm 0:9b334a45a8ff 830 /* Get timeout */
bogdanm 0:9b334a45a8ff 831 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 832
bogdanm 0:9b334a45a8ff 833 /* Wait till HSE is ready */
bogdanm 0:9b334a45a8ff 834 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
bogdanm 0:9b334a45a8ff 835 {
bogdanm 0:9b334a45a8ff 836 if((HAL_GetTick()-tickstart) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 837 {
bogdanm 0:9b334a45a8ff 838 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 839 }
bogdanm 0:9b334a45a8ff 840 }
bogdanm 0:9b334a45a8ff 841 }
bogdanm 0:9b334a45a8ff 842 else
bogdanm 0:9b334a45a8ff 843 {
bogdanm 0:9b334a45a8ff 844 /* Get timeout */
bogdanm 0:9b334a45a8ff 845 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 846
bogdanm 0:9b334a45a8ff 847 /* Wait till HSE is bypassed or disabled */
bogdanm 0:9b334a45a8ff 848 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
bogdanm 0:9b334a45a8ff 849 {
bogdanm 0:9b334a45a8ff 850 if((HAL_GetTick()-tickstart) > HSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 851 {
bogdanm 0:9b334a45a8ff 852 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 853 }
bogdanm 0:9b334a45a8ff 854 }
bogdanm 0:9b334a45a8ff 855 }
bogdanm 0:9b334a45a8ff 856 }
bogdanm 0:9b334a45a8ff 857 }
bogdanm 0:9b334a45a8ff 858 /*----------------------------- HSI Configuration --------------------------*/
bogdanm 0:9b334a45a8ff 859 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
bogdanm 0:9b334a45a8ff 860 {
bogdanm 0:9b334a45a8ff 861 /* Check the parameters */
bogdanm 0:9b334a45a8ff 862 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
bogdanm 0:9b334a45a8ff 863 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
bogdanm 0:9b334a45a8ff 864
bogdanm 0:9b334a45a8ff 865 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
bogdanm 0:9b334a45a8ff 866 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) ||
bogdanm 0:9b334a45a8ff 867 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
bogdanm 0:9b334a45a8ff 868 {
bogdanm 0:9b334a45a8ff 869 /* When the HSI is used as system clock it is not allowed to be disabled */
bogdanm 0:9b334a45a8ff 870 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
bogdanm 0:9b334a45a8ff 871 {
bogdanm 0:9b334a45a8ff 872 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 873 }
bogdanm 0:9b334a45a8ff 874 /* Otherwise, just the calibration is allowed */
bogdanm 0:9b334a45a8ff 875 else
bogdanm 0:9b334a45a8ff 876 {
bogdanm 0:9b334a45a8ff 877 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 878 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 879 }
bogdanm 0:9b334a45a8ff 880 }
bogdanm 0:9b334a45a8ff 881 else
bogdanm 0:9b334a45a8ff 882 {
bogdanm 0:9b334a45a8ff 883 /* Check the HSI State */
bogdanm 0:9b334a45a8ff 884 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
bogdanm 0:9b334a45a8ff 885 {
bogdanm 0:9b334a45a8ff 886 /* Enable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 887 __HAL_RCC_HSI_ENABLE();
bogdanm 0:9b334a45a8ff 888
bogdanm 0:9b334a45a8ff 889 /* Get timeout */
bogdanm 0:9b334a45a8ff 890 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 891
bogdanm 0:9b334a45a8ff 892 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 893 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 894 {
bogdanm 0:9b334a45a8ff 895 if((HAL_GetTick()-tickstart) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 896 {
bogdanm 0:9b334a45a8ff 897 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 898 }
bogdanm 0:9b334a45a8ff 899 }
bogdanm 0:9b334a45a8ff 900
bogdanm 0:9b334a45a8ff 901 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
bogdanm 0:9b334a45a8ff 902 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
bogdanm 0:9b334a45a8ff 903 }
bogdanm 0:9b334a45a8ff 904 else
bogdanm 0:9b334a45a8ff 905 {
bogdanm 0:9b334a45a8ff 906 /* Disable the Internal High Speed oscillator (HSI). */
bogdanm 0:9b334a45a8ff 907 __HAL_RCC_HSI_DISABLE();
bogdanm 0:9b334a45a8ff 908
bogdanm 0:9b334a45a8ff 909 /* Get timeout */
bogdanm 0:9b334a45a8ff 910 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 911
bogdanm 0:9b334a45a8ff 912 /* Wait till HSI is ready */
bogdanm 0:9b334a45a8ff 913 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 914 {
bogdanm 0:9b334a45a8ff 915 if((HAL_GetTick()-tickstart) > HSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 916 {
bogdanm 0:9b334a45a8ff 917 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 918 }
bogdanm 0:9b334a45a8ff 919 }
bogdanm 0:9b334a45a8ff 920 }
bogdanm 0:9b334a45a8ff 921 }
bogdanm 0:9b334a45a8ff 922 }
bogdanm 0:9b334a45a8ff 923 /*------------------------------ LSI Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 924 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
bogdanm 0:9b334a45a8ff 925 {
bogdanm 0:9b334a45a8ff 926 /* Check the parameters */
bogdanm 0:9b334a45a8ff 927 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
bogdanm 0:9b334a45a8ff 928
bogdanm 0:9b334a45a8ff 929 /* Check the LSI State */
bogdanm 0:9b334a45a8ff 930 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
bogdanm 0:9b334a45a8ff 931 {
bogdanm 0:9b334a45a8ff 932 /* Enable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 933 __HAL_RCC_LSI_ENABLE();
bogdanm 0:9b334a45a8ff 934
bogdanm 0:9b334a45a8ff 935 /* Get timeout */
bogdanm 0:9b334a45a8ff 936 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 937
bogdanm 0:9b334a45a8ff 938 /* Wait till LSI is ready */
bogdanm 0:9b334a45a8ff 939 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
bogdanm 0:9b334a45a8ff 940 {
bogdanm 0:9b334a45a8ff 941 if((HAL_GetTick()-tickstart) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 942 {
bogdanm 0:9b334a45a8ff 943 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 944 }
bogdanm 0:9b334a45a8ff 945 }
bogdanm 0:9b334a45a8ff 946 }
bogdanm 0:9b334a45a8ff 947 else
bogdanm 0:9b334a45a8ff 948 {
bogdanm 0:9b334a45a8ff 949 /* Disable the Internal Low Speed oscillator (LSI). */
bogdanm 0:9b334a45a8ff 950 __HAL_RCC_LSI_DISABLE();
bogdanm 0:9b334a45a8ff 951
bogdanm 0:9b334a45a8ff 952 /* Get timeout */
bogdanm 0:9b334a45a8ff 953 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 954
bogdanm 0:9b334a45a8ff 955 /* Wait till LSI is ready */
bogdanm 0:9b334a45a8ff 956 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
bogdanm 0:9b334a45a8ff 957 {
bogdanm 0:9b334a45a8ff 958 if((HAL_GetTick()-tickstart) > LSI_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 959 {
bogdanm 0:9b334a45a8ff 960 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 961 }
bogdanm 0:9b334a45a8ff 962 }
bogdanm 0:9b334a45a8ff 963 }
bogdanm 0:9b334a45a8ff 964 }
bogdanm 0:9b334a45a8ff 965 /*------------------------------ LSE Configuration -------------------------*/
bogdanm 0:9b334a45a8ff 966 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
bogdanm 0:9b334a45a8ff 967 {
bogdanm 0:9b334a45a8ff 968 /* Check the parameters */
bogdanm 0:9b334a45a8ff 969 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
bogdanm 0:9b334a45a8ff 970
bogdanm 0:9b334a45a8ff 971 /* Enable Power Clock*/
bogdanm 0:9b334a45a8ff 972 __PWR_CLK_ENABLE();
bogdanm 0:9b334a45a8ff 973
bogdanm 0:9b334a45a8ff 974 /* Enable write access to Backup domain */
bogdanm 0:9b334a45a8ff 975 SET_BIT(PWR->CR, PWR_CR_DBP);
bogdanm 0:9b334a45a8ff 976
bogdanm 0:9b334a45a8ff 977 /* Wait for Backup domain Write protection disable */
bogdanm 0:9b334a45a8ff 978 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 979
bogdanm 0:9b334a45a8ff 980 while((PWR->CR & PWR_CR_DBP) == RESET)
bogdanm 0:9b334a45a8ff 981 {
bogdanm 0:9b334a45a8ff 982 if((HAL_GetTick()-tickstart) > DBP_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 983 {
bogdanm 0:9b334a45a8ff 984 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 985 }
bogdanm 0:9b334a45a8ff 986 }
bogdanm 0:9b334a45a8ff 987
bogdanm 0:9b334a45a8ff 988 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
bogdanm 0:9b334a45a8ff 989 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
bogdanm 0:9b334a45a8ff 990
bogdanm 0:9b334a45a8ff 991 /* Get timeout */
bogdanm 0:9b334a45a8ff 992 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 993
bogdanm 0:9b334a45a8ff 994 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 995 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 996 {
bogdanm 0:9b334a45a8ff 997 if((HAL_GetTick()-tickstart) > LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 998 {
bogdanm 0:9b334a45a8ff 999 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1000 }
bogdanm 0:9b334a45a8ff 1001 }
bogdanm 0:9b334a45a8ff 1002
bogdanm 0:9b334a45a8ff 1003 /* Set the new LSE configuration -----------------------------------------*/
bogdanm 0:9b334a45a8ff 1004 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
bogdanm 0:9b334a45a8ff 1005 /* Check the LSE State */
bogdanm 0:9b334a45a8ff 1006 if(RCC_OscInitStruct->LSEState == RCC_LSE_ON)
bogdanm 0:9b334a45a8ff 1007 {
bogdanm 0:9b334a45a8ff 1008 /* Get timeout */
bogdanm 0:9b334a45a8ff 1009 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1010
bogdanm 0:9b334a45a8ff 1011 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 1012 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
bogdanm 0:9b334a45a8ff 1013 {
bogdanm 0:9b334a45a8ff 1014 if((HAL_GetTick()-tickstart) > LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1015 {
bogdanm 0:9b334a45a8ff 1016 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1017 }
bogdanm 0:9b334a45a8ff 1018 }
bogdanm 0:9b334a45a8ff 1019 }
bogdanm 0:9b334a45a8ff 1020 else
bogdanm 0:9b334a45a8ff 1021 {
bogdanm 0:9b334a45a8ff 1022 /* Get timeout */
bogdanm 0:9b334a45a8ff 1023 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1024
bogdanm 0:9b334a45a8ff 1025 /* Wait till LSE is ready */
bogdanm 0:9b334a45a8ff 1026 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
bogdanm 0:9b334a45a8ff 1027 {
bogdanm 0:9b334a45a8ff 1028 if((HAL_GetTick()-tickstart) > LSE_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1029 {
bogdanm 0:9b334a45a8ff 1030 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1031 }
bogdanm 0:9b334a45a8ff 1032 }
bogdanm 0:9b334a45a8ff 1033 }
bogdanm 0:9b334a45a8ff 1034 }
bogdanm 0:9b334a45a8ff 1035 /*-------------------------------- PLL Configuration -----------------------*/
bogdanm 0:9b334a45a8ff 1036 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1037 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
bogdanm 0:9b334a45a8ff 1038 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
bogdanm 0:9b334a45a8ff 1039 {
bogdanm 0:9b334a45a8ff 1040 /* Check if the PLL is used as system clock or not */
bogdanm 0:9b334a45a8ff 1041 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
bogdanm 0:9b334a45a8ff 1042 {
bogdanm 0:9b334a45a8ff 1043 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
bogdanm 0:9b334a45a8ff 1044 {
bogdanm 0:9b334a45a8ff 1045 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1046 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
bogdanm 0:9b334a45a8ff 1047 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
bogdanm 0:9b334a45a8ff 1048 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 0:9b334a45a8ff 1049 assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
bogdanm 0:9b334a45a8ff 1050 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 0:9b334a45a8ff 1051
bogdanm 0:9b334a45a8ff 1052 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 1053 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 1054
bogdanm 0:9b334a45a8ff 1055 /* Get timeout */
bogdanm 0:9b334a45a8ff 1056 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1057
bogdanm 0:9b334a45a8ff 1058 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 1059 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 1060 {
bogdanm 0:9b334a45a8ff 1061 if((HAL_GetTick()-tickstart) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1062 {
bogdanm 0:9b334a45a8ff 1063 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1064 }
bogdanm 0:9b334a45a8ff 1065 }
bogdanm 0:9b334a45a8ff 1066 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 1067 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 0:9b334a45a8ff 1068 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 0:9b334a45a8ff 1069 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 1070 /* Configure the main PLL clock source and multiplication factor. */
bogdanm 0:9b334a45a8ff 1071 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm 0:9b334a45a8ff 1072 RCC_OscInitStruct->PLL.PLLMUL);
bogdanm 0:9b334a45a8ff 1073 #else
bogdanm 0:9b334a45a8ff 1074 /* Configure the main PLL clock source, predivider and multiplication factor. */
bogdanm 0:9b334a45a8ff 1075 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
bogdanm 0:9b334a45a8ff 1076 RCC_OscInitStruct->PLL.PREDIV,
bogdanm 0:9b334a45a8ff 1077 RCC_OscInitStruct->PLL.PLLMUL);
bogdanm 0:9b334a45a8ff 1078 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 1079 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 0:9b334a45a8ff 1080 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 1081 /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 1082
bogdanm 0:9b334a45a8ff 1083 /* Enable the main PLL. */
bogdanm 0:9b334a45a8ff 1084 __HAL_RCC_PLL_ENABLE();
bogdanm 0:9b334a45a8ff 1085
bogdanm 0:9b334a45a8ff 1086 /* Get timeout */
bogdanm 0:9b334a45a8ff 1087 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1088
bogdanm 0:9b334a45a8ff 1089 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 1090 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
bogdanm 0:9b334a45a8ff 1091 {
bogdanm 0:9b334a45a8ff 1092 if((HAL_GetTick()-tickstart) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1093 {
bogdanm 0:9b334a45a8ff 1094 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1095 }
bogdanm 0:9b334a45a8ff 1096 }
bogdanm 0:9b334a45a8ff 1097 }
bogdanm 0:9b334a45a8ff 1098 else
bogdanm 0:9b334a45a8ff 1099 {
bogdanm 0:9b334a45a8ff 1100 /* Disable the main PLL. */
bogdanm 0:9b334a45a8ff 1101 __HAL_RCC_PLL_DISABLE();
bogdanm 0:9b334a45a8ff 1102 /* Get timeout */
bogdanm 0:9b334a45a8ff 1103 tickstart = HAL_GetTick();
bogdanm 0:9b334a45a8ff 1104
bogdanm 0:9b334a45a8ff 1105 /* Wait till PLL is ready */
bogdanm 0:9b334a45a8ff 1106 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
bogdanm 0:9b334a45a8ff 1107 {
bogdanm 0:9b334a45a8ff 1108 if((HAL_GetTick()-tickstart) > PLL_TIMEOUT_VALUE)
bogdanm 0:9b334a45a8ff 1109 {
bogdanm 0:9b334a45a8ff 1110 return HAL_TIMEOUT;
bogdanm 0:9b334a45a8ff 1111 }
bogdanm 0:9b334a45a8ff 1112 }
bogdanm 0:9b334a45a8ff 1113 }
bogdanm 0:9b334a45a8ff 1114 }
bogdanm 0:9b334a45a8ff 1115 else
bogdanm 0:9b334a45a8ff 1116 {
bogdanm 0:9b334a45a8ff 1117 return HAL_ERROR;
bogdanm 0:9b334a45a8ff 1118 }
bogdanm 0:9b334a45a8ff 1119 }
bogdanm 0:9b334a45a8ff 1120 return HAL_OK;
bogdanm 0:9b334a45a8ff 1121 }
bogdanm 0:9b334a45a8ff 1122
bogdanm 0:9b334a45a8ff 1123 /**
bogdanm 0:9b334a45a8ff 1124 * @brief Configures the RCC_OscInitStruct according to the internal
bogdanm 0:9b334a45a8ff 1125 * RCC configuration registers.
bogdanm 0:9b334a45a8ff 1126 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
bogdanm 0:9b334a45a8ff 1127 * will be configured.
bogdanm 0:9b334a45a8ff 1128 * @retval None
bogdanm 0:9b334a45a8ff 1129 */
bogdanm 0:9b334a45a8ff 1130 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
bogdanm 0:9b334a45a8ff 1131 {
bogdanm 0:9b334a45a8ff 1132 /* Check the parameters */
bogdanm 0:9b334a45a8ff 1133 assert_param(RCC_OscInitStruct != HAL_NULL);
bogdanm 0:9b334a45a8ff 1134
bogdanm 0:9b334a45a8ff 1135 /* Set all possible values for the Oscillator type parameter ---------------*/
bogdanm 0:9b334a45a8ff 1136 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
bogdanm 0:9b334a45a8ff 1137
bogdanm 0:9b334a45a8ff 1138 /* Get the HSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1139 if((RCC->CR & RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
bogdanm 0:9b334a45a8ff 1140 {
bogdanm 0:9b334a45a8ff 1141 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
bogdanm 0:9b334a45a8ff 1142 }
bogdanm 0:9b334a45a8ff 1143 else if((RCC->CR & RCC_CR_HSEON) == RCC_CR_HSEON)
bogdanm 0:9b334a45a8ff 1144 {
bogdanm 0:9b334a45a8ff 1145 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
bogdanm 0:9b334a45a8ff 1146 }
bogdanm 0:9b334a45a8ff 1147 else
bogdanm 0:9b334a45a8ff 1148 {
bogdanm 0:9b334a45a8ff 1149 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
bogdanm 0:9b334a45a8ff 1150 }
bogdanm 0:9b334a45a8ff 1151
bogdanm 0:9b334a45a8ff 1152 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 1153 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 0:9b334a45a8ff 1154 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 0:9b334a45a8ff 1155 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 1156 RCC_OscInitStruct->HSEPredivValue = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
bogdanm 0:9b334a45a8ff 1157 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 1158 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 0:9b334a45a8ff 1159 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 1160 /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 1161
bogdanm 0:9b334a45a8ff 1162 /* Get the HSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1163 if((RCC->CR & RCC_CR_HSION) == RCC_CR_HSION)
bogdanm 0:9b334a45a8ff 1164 {
bogdanm 0:9b334a45a8ff 1165 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
bogdanm 0:9b334a45a8ff 1166 }
bogdanm 0:9b334a45a8ff 1167 else
bogdanm 0:9b334a45a8ff 1168 {
bogdanm 0:9b334a45a8ff 1169 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
bogdanm 0:9b334a45a8ff 1170 }
bogdanm 0:9b334a45a8ff 1171
bogdanm 0:9b334a45a8ff 1172 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
bogdanm 0:9b334a45a8ff 1173
bogdanm 0:9b334a45a8ff 1174 /* Get the LSE configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1175 if((RCC->BDCR & RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
bogdanm 0:9b334a45a8ff 1176 {
bogdanm 0:9b334a45a8ff 1177 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
bogdanm 0:9b334a45a8ff 1178 }
bogdanm 0:9b334a45a8ff 1179 else if((RCC->BDCR & RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
bogdanm 0:9b334a45a8ff 1180 {
bogdanm 0:9b334a45a8ff 1181 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
bogdanm 0:9b334a45a8ff 1182 }
bogdanm 0:9b334a45a8ff 1183 else
bogdanm 0:9b334a45a8ff 1184 {
bogdanm 0:9b334a45a8ff 1185 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
bogdanm 0:9b334a45a8ff 1186 }
bogdanm 0:9b334a45a8ff 1187
bogdanm 0:9b334a45a8ff 1188 /* Get the LSI configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1189 if((RCC->CSR & RCC_CSR_LSION) == RCC_CSR_LSION)
bogdanm 0:9b334a45a8ff 1190 {
bogdanm 0:9b334a45a8ff 1191 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
bogdanm 0:9b334a45a8ff 1192 }
bogdanm 0:9b334a45a8ff 1193 else
bogdanm 0:9b334a45a8ff 1194 {
bogdanm 0:9b334a45a8ff 1195 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
bogdanm 0:9b334a45a8ff 1196 }
bogdanm 0:9b334a45a8ff 1197
bogdanm 0:9b334a45a8ff 1198 /* Get the PLL configuration -----------------------------------------------*/
bogdanm 0:9b334a45a8ff 1199 if((RCC->CR & RCC_CR_PLLON) == RCC_CR_PLLON)
bogdanm 0:9b334a45a8ff 1200 {
bogdanm 0:9b334a45a8ff 1201 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
bogdanm 0:9b334a45a8ff 1202 }
bogdanm 0:9b334a45a8ff 1203 else
bogdanm 0:9b334a45a8ff 1204 {
bogdanm 0:9b334a45a8ff 1205 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
bogdanm 0:9b334a45a8ff 1206 }
bogdanm 0:9b334a45a8ff 1207
bogdanm 0:9b334a45a8ff 1208 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
bogdanm 0:9b334a45a8ff 1209 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
bogdanm 0:9b334a45a8ff 1210 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
bogdanm 0:9b334a45a8ff 1211 RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
bogdanm 0:9b334a45a8ff 1212 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
bogdanm 0:9b334a45a8ff 1213 }
bogdanm 0:9b334a45a8ff 1214
bogdanm 0:9b334a45a8ff 1215 /**
bogdanm 0:9b334a45a8ff 1216 * @brief Returns the SYSCLK frequency
bogdanm 0:9b334a45a8ff 1217 * @note The system frequency computed by this function is not the real
bogdanm 0:9b334a45a8ff 1218 * frequency in the chip. It is calculated based on the predefined
bogdanm 0:9b334a45a8ff 1219 * constant and the selected clock source:
bogdanm 0:9b334a45a8ff 1220 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
bogdanm 0:9b334a45a8ff 1221 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
bogdanm 0:9b334a45a8ff 1222 * divided by PREDIV factor(**)
bogdanm 0:9b334a45a8ff 1223 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
bogdanm 0:9b334a45a8ff 1224 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
bogdanm 0:9b334a45a8ff 1225 * @note (*) HSI_VALUE is a constant defined in stm32f3xx.h file (default value
bogdanm 0:9b334a45a8ff 1226 * 8 MHz).
bogdanm 0:9b334a45a8ff 1227 * @note (**) HSE_VALUE is a constant defined in stm32f3xx.h file (default value
bogdanm 0:9b334a45a8ff 1228 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
bogdanm 0:9b334a45a8ff 1229 * frequency of the crystal used. Otherwise, this function may
bogdanm 0:9b334a45a8ff 1230 * have wrong result.
bogdanm 0:9b334a45a8ff 1231 *
bogdanm 0:9b334a45a8ff 1232 * @note The result of this function could be not correct when using fractional
bogdanm 0:9b334a45a8ff 1233 * value for HSE crystal.
bogdanm 0:9b334a45a8ff 1234 *
bogdanm 0:9b334a45a8ff 1235 * @note This function can be used by the user application to compute the
bogdanm 0:9b334a45a8ff 1236 * baudrate for the communication peripherals or configure other parameters.
bogdanm 0:9b334a45a8ff 1237 *
bogdanm 0:9b334a45a8ff 1238 * @note Each time SYSCLK changes, this function must be called to update the
bogdanm 0:9b334a45a8ff 1239 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
bogdanm 0:9b334a45a8ff 1240 *
bogdanm 0:9b334a45a8ff 1241 * @retval SYSCLK frequency
bogdanm 0:9b334a45a8ff 1242 */
bogdanm 0:9b334a45a8ff 1243 uint32_t HAL_RCC_GetSysClockFreq(void)
bogdanm 0:9b334a45a8ff 1244 {
bogdanm 0:9b334a45a8ff 1245 uint32_t tmpreg = 0, prediv = 0, pllmul = 0, pllclk = 0;
bogdanm 0:9b334a45a8ff 1246 uint32_t sysclockfreq = 0;
bogdanm 0:9b334a45a8ff 1247
bogdanm 0:9b334a45a8ff 1248 tmpreg = RCC->CFGR;
bogdanm 0:9b334a45a8ff 1249
bogdanm 0:9b334a45a8ff 1250 /* Get SYSCLK source -------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 1251 switch (tmpreg & RCC_CFGR_SWS)
bogdanm 0:9b334a45a8ff 1252 {
bogdanm 0:9b334a45a8ff 1253 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock source */
bogdanm 0:9b334a45a8ff 1254 sysclockfreq = HSE_VALUE;
bogdanm 0:9b334a45a8ff 1255 break;
bogdanm 0:9b334a45a8ff 1256
bogdanm 0:9b334a45a8ff 1257 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock source */
bogdanm 0:9b334a45a8ff 1258 pllmul = PLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
bogdanm 0:9b334a45a8ff 1259 prediv = PredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
bogdanm 0:9b334a45a8ff 1260 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
bogdanm 0:9b334a45a8ff 1261 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
bogdanm 0:9b334a45a8ff 1262 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
bogdanm 0:9b334a45a8ff 1263 defined(STM32F373xC) || defined(STM32F378xx)
bogdanm 0:9b334a45a8ff 1264 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
bogdanm 0:9b334a45a8ff 1265 {
bogdanm 0:9b334a45a8ff 1266 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 1267 pllclk = (HSE_VALUE/prediv) * pllmul;
bogdanm 0:9b334a45a8ff 1268 }
bogdanm 0:9b334a45a8ff 1269 else
bogdanm 0:9b334a45a8ff 1270 {
bogdanm 0:9b334a45a8ff 1271 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
bogdanm 0:9b334a45a8ff 1272 pllclk = (HSI_VALUE >> 1) * pllmul;
bogdanm 0:9b334a45a8ff 1273 }
bogdanm 0:9b334a45a8ff 1274 #else
bogdanm 0:9b334a45a8ff 1275 if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV)
bogdanm 0:9b334a45a8ff 1276 {
bogdanm 0:9b334a45a8ff 1277 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 1278 pllclk = (HSE_VALUE/prediv) * pllmul;
bogdanm 0:9b334a45a8ff 1279 }
bogdanm 0:9b334a45a8ff 1280 else
bogdanm 0:9b334a45a8ff 1281 {
bogdanm 0:9b334a45a8ff 1282 /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
bogdanm 0:9b334a45a8ff 1283 pllclk = (HSI_VALUE/prediv) * pllmul;
bogdanm 0:9b334a45a8ff 1284 }
bogdanm 0:9b334a45a8ff 1285 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
bogdanm 0:9b334a45a8ff 1286 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
bogdanm 0:9b334a45a8ff 1287 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
bogdanm 0:9b334a45a8ff 1288 /* STM32F373xC || STM32F378xx */
bogdanm 0:9b334a45a8ff 1289 sysclockfreq = pllclk;
bogdanm 0:9b334a45a8ff 1290 break;
bogdanm 0:9b334a45a8ff 1291
bogdanm 0:9b334a45a8ff 1292 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
bogdanm 0:9b334a45a8ff 1293 default:
bogdanm 0:9b334a45a8ff 1294 sysclockfreq = HSI_VALUE;
bogdanm 0:9b334a45a8ff 1295 break;
bogdanm 0:9b334a45a8ff 1296 }
bogdanm 0:9b334a45a8ff 1297 return sysclockfreq;
bogdanm 0:9b334a45a8ff 1298 }
bogdanm 0:9b334a45a8ff 1299
bogdanm 0:9b334a45a8ff 1300 /**
bogdanm 0:9b334a45a8ff 1301 * @}
bogdanm 0:9b334a45a8ff 1302 */
bogdanm 0:9b334a45a8ff 1303
bogdanm 0:9b334a45a8ff 1304 /**
bogdanm 0:9b334a45a8ff 1305 * @}
bogdanm 0:9b334a45a8ff 1306 */
bogdanm 0:9b334a45a8ff 1307
bogdanm 0:9b334a45a8ff 1308 #endif /* HAL_RCC_MODULE_ENABLED */
bogdanm 0:9b334a45a8ff 1309 /**
bogdanm 0:9b334a45a8ff 1310 * @}
bogdanm 0:9b334a45a8ff 1311 */
bogdanm 0:9b334a45a8ff 1312
bogdanm 0:9b334a45a8ff 1313 /**
bogdanm 0:9b334a45a8ff 1314 * @}
bogdanm 0:9b334a45a8ff 1315 */
bogdanm 0:9b334a45a8ff 1316
bogdanm 0:9b334a45a8ff 1317 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/