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targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_DISCO_F469NI/system_stm32f4xx.c@19:112740acecfa, 2015-11-10 (annotated)
- Committer:
- mbed_official
- Date:
- Tue Nov 10 09:30:11 2015 +0000
- Revision:
- 19:112740acecfa
- Child:
- 144:ef7eb2e8f9f7
Synchronized with git revision 7218418919aeaf775fb8d386ea7ee0dfc0c80ff9
Full URL: https://github.com/mbedmicro/mbed/commit/7218418919aeaf775fb8d386ea7ee0dfc0c80ff9/
DISCO_F469NI - add disco F469NI support
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 19:112740acecfa | 1 | /** |
| mbed_official | 19:112740acecfa | 2 | ****************************************************************************** |
| mbed_official | 19:112740acecfa | 3 | * @file system_stm32f4xx.c |
| mbed_official | 19:112740acecfa | 4 | * @author MCD Application Team |
| mbed_official | 19:112740acecfa | 5 | * @version V2.4.1 |
| mbed_official | 19:112740acecfa | 6 | * @date 09-October-2015 |
| mbed_official | 19:112740acecfa | 7 | * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. |
| mbed_official | 19:112740acecfa | 8 | * |
| mbed_official | 19:112740acecfa | 9 | * This file provides two functions and one global variable to be called from |
| mbed_official | 19:112740acecfa | 10 | * user application: |
| mbed_official | 19:112740acecfa | 11 | * - SystemInit(): This function is called at startup just after reset and |
| mbed_official | 19:112740acecfa | 12 | * before branch to main program. This call is made inside |
| mbed_official | 19:112740acecfa | 13 | * the "startup_stm32f4xx.s" file. |
| mbed_official | 19:112740acecfa | 14 | * |
| mbed_official | 19:112740acecfa | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
| mbed_official | 19:112740acecfa | 16 | * by the user application to setup the SysTick |
| mbed_official | 19:112740acecfa | 17 | * timer or configure other parameters. |
| mbed_official | 19:112740acecfa | 18 | * |
| mbed_official | 19:112740acecfa | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
| mbed_official | 19:112740acecfa | 20 | * be called whenever the core clock is changed |
| mbed_official | 19:112740acecfa | 21 | * during program execution. |
| mbed_official | 19:112740acecfa | 22 | * |
| mbed_official | 19:112740acecfa | 23 | * This file configures the system clock as follows: |
| mbed_official | 19:112740acecfa | 24 | *-------------------------------------------------------------------------------------- |
| mbed_official | 19:112740acecfa | 25 | * System clock source | PLL_HSE_XTAL | PLL_HSE_XTAL |
| mbed_official | 19:112740acecfa | 26 | * | (external 8 MHz clock) | (external 8 MHz clock) |
| mbed_official | 19:112740acecfa | 27 | *-------------------------------------------------------------------------------------- |
| mbed_official | 19:112740acecfa | 28 | * SYSCLK(MHz) | 168 | 180 |
| mbed_official | 19:112740acecfa | 29 | *-------------------------------------------------------------------------------------- |
| mbed_official | 19:112740acecfa | 30 | * AHBCLK (MHz) | 168 | 180 |
| mbed_official | 19:112740acecfa | 31 | *-------------------------------------------------------------------------------------- |
| mbed_official | 19:112740acecfa | 32 | * APB1CLK (MHz) | 42 | 45 |
| mbed_official | 19:112740acecfa | 33 | *-------------------------------------------------------------------------------------- |
| mbed_official | 19:112740acecfa | 34 | * APB2CLK (MHz) | 84 | 90 |
| mbed_official | 19:112740acecfa | 35 | *-------------------------------------------------------------------------------------- |
| mbed_official | 19:112740acecfa | 36 | * USB capable (48 MHz precise clock) | YES | NO |
| mbed_official | 19:112740acecfa | 37 | *-------------------------------------------------------------------------------------- |
| mbed_official | 19:112740acecfa | 38 | ****************************************************************************** |
| mbed_official | 19:112740acecfa | 39 | * @attention |
| mbed_official | 19:112740acecfa | 40 | * |
| mbed_official | 19:112740acecfa | 41 | * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> |
| mbed_official | 19:112740acecfa | 42 | * |
| mbed_official | 19:112740acecfa | 43 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 19:112740acecfa | 44 | * are permitted provided that the following conditions are met: |
| mbed_official | 19:112740acecfa | 45 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 19:112740acecfa | 46 | * this list of conditions and the following disclaimer. |
| mbed_official | 19:112740acecfa | 47 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 19:112740acecfa | 48 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 19:112740acecfa | 49 | * and/or other materials provided with the distribution. |
| mbed_official | 19:112740acecfa | 50 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 19:112740acecfa | 51 | * may be used to endorse or promote products derived from this software |
| mbed_official | 19:112740acecfa | 52 | * without specific prior written permission. |
| mbed_official | 19:112740acecfa | 53 | * |
| mbed_official | 19:112740acecfa | 54 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 19:112740acecfa | 55 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 19:112740acecfa | 56 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 19:112740acecfa | 57 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 19:112740acecfa | 58 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 19:112740acecfa | 59 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 19:112740acecfa | 60 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 19:112740acecfa | 61 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 19:112740acecfa | 62 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 19:112740acecfa | 63 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 19:112740acecfa | 64 | * |
| mbed_official | 19:112740acecfa | 65 | ****************************************************************************** |
| mbed_official | 19:112740acecfa | 66 | */ |
| mbed_official | 19:112740acecfa | 67 | |
| mbed_official | 19:112740acecfa | 68 | /** @addtogroup CMSIS |
| mbed_official | 19:112740acecfa | 69 | * @{ |
| mbed_official | 19:112740acecfa | 70 | */ |
| mbed_official | 19:112740acecfa | 71 | |
| mbed_official | 19:112740acecfa | 72 | /** @addtogroup stm32f4xx_system |
| mbed_official | 19:112740acecfa | 73 | * @{ |
| mbed_official | 19:112740acecfa | 74 | */ |
| mbed_official | 19:112740acecfa | 75 | |
| mbed_official | 19:112740acecfa | 76 | /** @addtogroup STM32F4xx_System_Private_Includes |
| mbed_official | 19:112740acecfa | 77 | * @{ |
| mbed_official | 19:112740acecfa | 78 | */ |
| mbed_official | 19:112740acecfa | 79 | |
| mbed_official | 19:112740acecfa | 80 | |
| mbed_official | 19:112740acecfa | 81 | #include "stm32f4xx.h" |
| mbed_official | 19:112740acecfa | 82 | #include "hal_tick.h" |
| mbed_official | 19:112740acecfa | 83 | |
| mbed_official | 19:112740acecfa | 84 | #if !defined (HSE_VALUE) |
| mbed_official | 19:112740acecfa | 85 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */ |
| mbed_official | 19:112740acecfa | 86 | #endif /* HSE_VALUE */ |
| mbed_official | 19:112740acecfa | 87 | |
| mbed_official | 19:112740acecfa | 88 | #if !defined (HSI_VALUE) |
| mbed_official | 19:112740acecfa | 89 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
| mbed_official | 19:112740acecfa | 90 | #endif /* HSI_VALUE */ |
| mbed_official | 19:112740acecfa | 91 | |
| mbed_official | 19:112740acecfa | 92 | /** |
| mbed_official | 19:112740acecfa | 93 | * @} |
| mbed_official | 19:112740acecfa | 94 | */ |
| mbed_official | 19:112740acecfa | 95 | |
| mbed_official | 19:112740acecfa | 96 | /** @addtogroup STM32F4xx_System_Private_TypesDefinitions |
| mbed_official | 19:112740acecfa | 97 | * @{ |
| mbed_official | 19:112740acecfa | 98 | */ |
| mbed_official | 19:112740acecfa | 99 | |
| mbed_official | 19:112740acecfa | 100 | /** |
| mbed_official | 19:112740acecfa | 101 | * @} |
| mbed_official | 19:112740acecfa | 102 | */ |
| mbed_official | 19:112740acecfa | 103 | |
| mbed_official | 19:112740acecfa | 104 | /** @addtogroup STM32F4xx_System_Private_Defines |
| mbed_official | 19:112740acecfa | 105 | * @{ |
| mbed_official | 19:112740acecfa | 106 | */ |
| mbed_official | 19:112740acecfa | 107 | |
| mbed_official | 19:112740acecfa | 108 | /************************* Miscellaneous Configuration ************************/ |
| mbed_official | 19:112740acecfa | 109 | /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ |
| mbed_official | 19:112740acecfa | 110 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| mbed_official | 19:112740acecfa | 111 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| mbed_official | 19:112740acecfa | 112 | || defined(STM32F469xx) || defined(STM32F479xx) |
| mbed_official | 19:112740acecfa | 113 | /* #define DATA_IN_ExtSRAM */ |
| mbed_official | 19:112740acecfa | 114 | #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx */ |
| mbed_official | 19:112740acecfa | 115 | |
| mbed_official | 19:112740acecfa | 116 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| mbed_official | 19:112740acecfa | 117 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| mbed_official | 19:112740acecfa | 118 | /* #define DATA_IN_ExtSDRAM */ |
| mbed_official | 19:112740acecfa | 119 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ |
| mbed_official | 19:112740acecfa | 120 | STM32F479xx */ |
| mbed_official | 19:112740acecfa | 121 | |
| mbed_official | 19:112740acecfa | 122 | #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) |
| mbed_official | 19:112740acecfa | 123 | #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " |
| mbed_official | 19:112740acecfa | 124 | #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ |
| mbed_official | 19:112740acecfa | 125 | |
| mbed_official | 19:112740acecfa | 126 | /*!< Uncomment the following line if you need to relocate your vector Table in |
| mbed_official | 19:112740acecfa | 127 | Internal SRAM. */ |
| mbed_official | 19:112740acecfa | 128 | /* #define VECT_TAB_SRAM */ |
| mbed_official | 19:112740acecfa | 129 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
| mbed_official | 19:112740acecfa | 130 | This value must be a multiple of 0x200. */ |
| mbed_official | 19:112740acecfa | 131 | /******************************************************************************/ |
| mbed_official | 19:112740acecfa | 132 | |
| mbed_official | 19:112740acecfa | 133 | /** |
| mbed_official | 19:112740acecfa | 134 | * @} |
| mbed_official | 19:112740acecfa | 135 | */ |
| mbed_official | 19:112740acecfa | 136 | |
| mbed_official | 19:112740acecfa | 137 | /** @addtogroup STM32F4xx_System_Private_Macros |
| mbed_official | 19:112740acecfa | 138 | * @{ |
| mbed_official | 19:112740acecfa | 139 | */ |
| mbed_official | 19:112740acecfa | 140 | |
| mbed_official | 19:112740acecfa | 141 | /* Select the SYSCLOCK to start with (0=OFF, 1=ON) */ |
| mbed_official | 19:112740acecfa | 142 | #define USE_SYSCLOCK_168 (1) /* Use external 8MHz xtal and sets SYSCLK to 168MHz */ |
| mbed_official | 19:112740acecfa | 143 | #define USE_SYSCLOCK_180 (0) /* Use external 8MHz xtal and sets SYSCLK to 180MHz */ |
| mbed_official | 19:112740acecfa | 144 | |
| mbed_official | 19:112740acecfa | 145 | /** |
| mbed_official | 19:112740acecfa | 146 | * @} |
| mbed_official | 19:112740acecfa | 147 | */ |
| mbed_official | 19:112740acecfa | 148 | |
| mbed_official | 19:112740acecfa | 149 | /** @addtogroup STM32F4xx_System_Private_Variables |
| mbed_official | 19:112740acecfa | 150 | * @{ |
| mbed_official | 19:112740acecfa | 151 | */ |
| mbed_official | 19:112740acecfa | 152 | /* This variable is updated in three ways: |
| mbed_official | 19:112740acecfa | 153 | 1) by calling CMSIS function SystemCoreClockUpdate() |
| mbed_official | 19:112740acecfa | 154 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
| mbed_official | 19:112740acecfa | 155 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
| mbed_official | 19:112740acecfa | 156 | Note: If you use this function to configure the system clock; then there |
| mbed_official | 19:112740acecfa | 157 | is no need to call the 2 first functions listed above, since SystemCoreClock |
| mbed_official | 19:112740acecfa | 158 | variable is updated automatically. |
| mbed_official | 19:112740acecfa | 159 | */ |
| mbed_official | 19:112740acecfa | 160 | uint32_t SystemCoreClock = 168000000; |
| mbed_official | 19:112740acecfa | 161 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
| mbed_official | 19:112740acecfa | 162 | |
| mbed_official | 19:112740acecfa | 163 | /** |
| mbed_official | 19:112740acecfa | 164 | * @} |
| mbed_official | 19:112740acecfa | 165 | */ |
| mbed_official | 19:112740acecfa | 166 | |
| mbed_official | 19:112740acecfa | 167 | /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes |
| mbed_official | 19:112740acecfa | 168 | * @{ |
| mbed_official | 19:112740acecfa | 169 | */ |
| mbed_official | 19:112740acecfa | 170 | |
| mbed_official | 19:112740acecfa | 171 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 19:112740acecfa | 172 | static void SystemInit_ExtMemCtl(void); |
| mbed_official | 19:112740acecfa | 173 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 19:112740acecfa | 174 | |
| mbed_official | 19:112740acecfa | 175 | void SystemClock_Config(void); |
| mbed_official | 19:112740acecfa | 176 | /** |
| mbed_official | 19:112740acecfa | 177 | * @} |
| mbed_official | 19:112740acecfa | 178 | */ |
| mbed_official | 19:112740acecfa | 179 | |
| mbed_official | 19:112740acecfa | 180 | /** @addtogroup STM32F4xx_System_Private_Functions |
| mbed_official | 19:112740acecfa | 181 | * @{ |
| mbed_official | 19:112740acecfa | 182 | */ |
| mbed_official | 19:112740acecfa | 183 | |
| mbed_official | 19:112740acecfa | 184 | /** |
| mbed_official | 19:112740acecfa | 185 | * @brief Setup the microcontroller system |
| mbed_official | 19:112740acecfa | 186 | * Initialize the FPU setting, vector table location and External memory |
| mbed_official | 19:112740acecfa | 187 | * configuration. |
| mbed_official | 19:112740acecfa | 188 | * @param None |
| mbed_official | 19:112740acecfa | 189 | * @retval None |
| mbed_official | 19:112740acecfa | 190 | */ |
| mbed_official | 19:112740acecfa | 191 | void SystemInit(void) |
| mbed_official | 19:112740acecfa | 192 | { |
| mbed_official | 19:112740acecfa | 193 | /* FPU settings ------------------------------------------------------------*/ |
| mbed_official | 19:112740acecfa | 194 | #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) |
| mbed_official | 19:112740acecfa | 195 | SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ |
| mbed_official | 19:112740acecfa | 196 | #endif |
| mbed_official | 19:112740acecfa | 197 | /* Reset the RCC clock configuration to the default reset state ------------*/ |
| mbed_official | 19:112740acecfa | 198 | /* Set HSION bit */ |
| mbed_official | 19:112740acecfa | 199 | RCC->CR |= (uint32_t)0x00000001; |
| mbed_official | 19:112740acecfa | 200 | |
| mbed_official | 19:112740acecfa | 201 | /* Reset CFGR register */ |
| mbed_official | 19:112740acecfa | 202 | RCC->CFGR = 0x00000000; |
| mbed_official | 19:112740acecfa | 203 | |
| mbed_official | 19:112740acecfa | 204 | /* Reset HSEON, CSSON and PLLON bits */ |
| mbed_official | 19:112740acecfa | 205 | RCC->CR &= (uint32_t)0xFEF6FFFF; |
| mbed_official | 19:112740acecfa | 206 | |
| mbed_official | 19:112740acecfa | 207 | /* Reset PLLCFGR register */ |
| mbed_official | 19:112740acecfa | 208 | RCC->PLLCFGR = 0x24003010; |
| mbed_official | 19:112740acecfa | 209 | |
| mbed_official | 19:112740acecfa | 210 | /* Reset HSEBYP bit */ |
| mbed_official | 19:112740acecfa | 211 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
| mbed_official | 19:112740acecfa | 212 | |
| mbed_official | 19:112740acecfa | 213 | /* Disable all interrupts */ |
| mbed_official | 19:112740acecfa | 214 | RCC->CIR = 0x00000000; |
| mbed_official | 19:112740acecfa | 215 | |
| mbed_official | 19:112740acecfa | 216 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 19:112740acecfa | 217 | SystemInit_ExtMemCtl(); |
| mbed_official | 19:112740acecfa | 218 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 19:112740acecfa | 219 | |
| mbed_official | 19:112740acecfa | 220 | /* Configure the Vector Table location add offset address ------------------*/ |
| mbed_official | 19:112740acecfa | 221 | #ifdef VECT_TAB_SRAM |
| mbed_official | 19:112740acecfa | 222 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
| mbed_official | 19:112740acecfa | 223 | #else |
| mbed_official | 19:112740acecfa | 224 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
| mbed_official | 19:112740acecfa | 225 | #endif |
| mbed_official | 19:112740acecfa | 226 | |
| mbed_official | 19:112740acecfa | 227 | /* Configure the Cube driver */ |
| mbed_official | 19:112740acecfa | 228 | SystemCoreClock = 16000000; // At this stage the HSI is used as system clock |
| mbed_official | 19:112740acecfa | 229 | HAL_Init(); |
| mbed_official | 19:112740acecfa | 230 | |
| mbed_official | 19:112740acecfa | 231 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 19:112740acecfa | 232 | AHB/APBx prescalers and Flash settings */ |
| mbed_official | 19:112740acecfa | 233 | SystemClock_Config(); |
| mbed_official | 19:112740acecfa | 234 | SystemCoreClockUpdate(); |
| mbed_official | 19:112740acecfa | 235 | |
| mbed_official | 19:112740acecfa | 236 | /* Reset the timer to avoid issues after the RAM initialization */ |
| mbed_official | 19:112740acecfa | 237 | TIM_MST_RESET_ON; |
| mbed_official | 19:112740acecfa | 238 | TIM_MST_RESET_OFF; |
| mbed_official | 19:112740acecfa | 239 | } |
| mbed_official | 19:112740acecfa | 240 | |
| mbed_official | 19:112740acecfa | 241 | /** |
| mbed_official | 19:112740acecfa | 242 | * @brief Update SystemCoreClock variable according to Clock Register Values. |
| mbed_official | 19:112740acecfa | 243 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
| mbed_official | 19:112740acecfa | 244 | * be used by the user application to setup the SysTick timer or configure |
| mbed_official | 19:112740acecfa | 245 | * other parameters. |
| mbed_official | 19:112740acecfa | 246 | * |
| mbed_official | 19:112740acecfa | 247 | * @note Each time the core clock (HCLK) changes, this function must be called |
| mbed_official | 19:112740acecfa | 248 | * to update SystemCoreClock variable value. Otherwise, any configuration |
| mbed_official | 19:112740acecfa | 249 | * based on this variable will be incorrect. |
| mbed_official | 19:112740acecfa | 250 | * |
| mbed_official | 19:112740acecfa | 251 | * @note - The system frequency computed by this function is not the real |
| mbed_official | 19:112740acecfa | 252 | * frequency in the chip. It is calculated based on the predefined |
| mbed_official | 19:112740acecfa | 253 | * constant and the selected clock source: |
| mbed_official | 19:112740acecfa | 254 | * |
| mbed_official | 19:112740acecfa | 255 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
| mbed_official | 19:112740acecfa | 256 | * |
| mbed_official | 19:112740acecfa | 257 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 19:112740acecfa | 258 | * |
| mbed_official | 19:112740acecfa | 259 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
| mbed_official | 19:112740acecfa | 260 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
| mbed_official | 19:112740acecfa | 261 | * |
| mbed_official | 19:112740acecfa | 262 | * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value |
| mbed_official | 19:112740acecfa | 263 | * 16 MHz) but the real value may vary depending on the variations |
| mbed_official | 19:112740acecfa | 264 | * in voltage and temperature. |
| mbed_official | 19:112740acecfa | 265 | * |
| mbed_official | 19:112740acecfa | 266 | * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value |
| mbed_official | 19:112740acecfa | 267 | * depends on the application requirements), user has to ensure that HSE_VALUE |
| mbed_official | 19:112740acecfa | 268 | * is same as the real frequency of the crystal used. Otherwise, this function |
| mbed_official | 19:112740acecfa | 269 | * may have wrong result. |
| mbed_official | 19:112740acecfa | 270 | * |
| mbed_official | 19:112740acecfa | 271 | * - The result of this function could be not correct when using fractional |
| mbed_official | 19:112740acecfa | 272 | * value for HSE crystal. |
| mbed_official | 19:112740acecfa | 273 | * |
| mbed_official | 19:112740acecfa | 274 | * @param None |
| mbed_official | 19:112740acecfa | 275 | * @retval None |
| mbed_official | 19:112740acecfa | 276 | */ |
| mbed_official | 19:112740acecfa | 277 | void SystemCoreClockUpdate(void) |
| mbed_official | 19:112740acecfa | 278 | { |
| mbed_official | 19:112740acecfa | 279 | uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; |
| mbed_official | 19:112740acecfa | 280 | |
| mbed_official | 19:112740acecfa | 281 | /* Get SYSCLK source -------------------------------------------------------*/ |
| mbed_official | 19:112740acecfa | 282 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
| mbed_official | 19:112740acecfa | 283 | |
| mbed_official | 19:112740acecfa | 284 | switch (tmp) |
| mbed_official | 19:112740acecfa | 285 | { |
| mbed_official | 19:112740acecfa | 286 | case 0x00: /* HSI used as system clock source */ |
| mbed_official | 19:112740acecfa | 287 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 19:112740acecfa | 288 | break; |
| mbed_official | 19:112740acecfa | 289 | case 0x04: /* HSE used as system clock source */ |
| mbed_official | 19:112740acecfa | 290 | SystemCoreClock = HSE_VALUE; |
| mbed_official | 19:112740acecfa | 291 | break; |
| mbed_official | 19:112740acecfa | 292 | case 0x08: /* PLL used as system clock source */ |
| mbed_official | 19:112740acecfa | 293 | |
| mbed_official | 19:112740acecfa | 294 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N |
| mbed_official | 19:112740acecfa | 295 | SYSCLK = PLL_VCO / PLL_P |
| mbed_official | 19:112740acecfa | 296 | */ |
| mbed_official | 19:112740acecfa | 297 | pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; |
| mbed_official | 19:112740acecfa | 298 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
| mbed_official | 19:112740acecfa | 299 | |
| mbed_official | 19:112740acecfa | 300 | if (pllsource != 0) |
| mbed_official | 19:112740acecfa | 301 | { |
| mbed_official | 19:112740acecfa | 302 | /* HSE used as PLL clock source */ |
| mbed_official | 19:112740acecfa | 303 | pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| mbed_official | 19:112740acecfa | 304 | } |
| mbed_official | 19:112740acecfa | 305 | else |
| mbed_official | 19:112740acecfa | 306 | { |
| mbed_official | 19:112740acecfa | 307 | /* HSI used as PLL clock source */ |
| mbed_official | 19:112740acecfa | 308 | pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); |
| mbed_official | 19:112740acecfa | 309 | } |
| mbed_official | 19:112740acecfa | 310 | |
| mbed_official | 19:112740acecfa | 311 | pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; |
| mbed_official | 19:112740acecfa | 312 | SystemCoreClock = pllvco/pllp; |
| mbed_official | 19:112740acecfa | 313 | break; |
| mbed_official | 19:112740acecfa | 314 | default: |
| mbed_official | 19:112740acecfa | 315 | SystemCoreClock = HSI_VALUE; |
| mbed_official | 19:112740acecfa | 316 | break; |
| mbed_official | 19:112740acecfa | 317 | } |
| mbed_official | 19:112740acecfa | 318 | /* Compute HCLK frequency --------------------------------------------------*/ |
| mbed_official | 19:112740acecfa | 319 | /* Get HCLK prescaler */ |
| mbed_official | 19:112740acecfa | 320 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
| mbed_official | 19:112740acecfa | 321 | /* HCLK frequency */ |
| mbed_official | 19:112740acecfa | 322 | SystemCoreClock >>= tmp; |
| mbed_official | 19:112740acecfa | 323 | } |
| mbed_official | 19:112740acecfa | 324 | |
| mbed_official | 19:112740acecfa | 325 | #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) |
| mbed_official | 19:112740acecfa | 326 | /** |
| mbed_official | 19:112740acecfa | 327 | * @brief Setup the external memory controller. |
| mbed_official | 19:112740acecfa | 328 | * Called in startup_stm32f4xx.s before jump to main. |
| mbed_official | 19:112740acecfa | 329 | * This function configures the external memories (SRAM/SDRAM) |
| mbed_official | 19:112740acecfa | 330 | * This SRAM/SDRAM will be used as program data memory (including heap and stack). |
| mbed_official | 19:112740acecfa | 331 | * @param None |
| mbed_official | 19:112740acecfa | 332 | * @retval None |
| mbed_official | 19:112740acecfa | 333 | */ |
| mbed_official | 19:112740acecfa | 334 | void SystemInit_ExtMemCtl(void) |
| mbed_official | 19:112740acecfa | 335 | { |
| mbed_official | 19:112740acecfa | 336 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| mbed_official | 19:112740acecfa | 337 | || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) |
| mbed_official | 19:112740acecfa | 338 | #if defined (DATA_IN_ExtSDRAM) |
| mbed_official | 19:112740acecfa | 339 | register uint32_t tmpreg = 0, timeout = 0xFFFF; |
| mbed_official | 19:112740acecfa | 340 | register uint32_t index; |
| mbed_official | 19:112740acecfa | 341 | |
| mbed_official | 19:112740acecfa | 342 | /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface |
| mbed_official | 19:112740acecfa | 343 | clock */ |
| mbed_official | 19:112740acecfa | 344 | RCC->AHB1ENR |= 0x000001F8; |
| mbed_official | 19:112740acecfa | 345 | |
| mbed_official | 19:112740acecfa | 346 | /* Connect PDx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 347 | GPIOD->AFR[0] = 0x000000CC; |
| mbed_official | 19:112740acecfa | 348 | GPIOD->AFR[1] = 0xCC000CCC; |
| mbed_official | 19:112740acecfa | 349 | /* Configure PDx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 350 | GPIOD->MODER = 0xA02A000A; |
| mbed_official | 19:112740acecfa | 351 | /* Configure PDx pins speed to 50 MHz */ |
| mbed_official | 19:112740acecfa | 352 | GPIOD->OSPEEDR = 0xA02A000A; |
| mbed_official | 19:112740acecfa | 353 | /* Configure PDx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 354 | GPIOD->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 355 | /* No pull-up, pull-down for PDx pins */ |
| mbed_official | 19:112740acecfa | 356 | GPIOD->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 357 | |
| mbed_official | 19:112740acecfa | 358 | /* Connect PEx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 359 | GPIOE->AFR[0] = 0xC00000CC; |
| mbed_official | 19:112740acecfa | 360 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 361 | /* Configure PEx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 362 | GPIOE->MODER = 0xAAAA800A; |
| mbed_official | 19:112740acecfa | 363 | /* Configure PEx pins speed to 50 MHz */ |
| mbed_official | 19:112740acecfa | 364 | GPIOE->OSPEEDR = 0xAAAA800A; |
| mbed_official | 19:112740acecfa | 365 | /* Configure PEx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 366 | GPIOE->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 367 | /* No pull-up, pull-down for PEx pins */ |
| mbed_official | 19:112740acecfa | 368 | GPIOE->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 369 | |
| mbed_official | 19:112740acecfa | 370 | /* Connect PFx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 371 | GPIOF->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 372 | GPIOF->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 373 | /* Configure PFx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 374 | GPIOF->MODER = 0xAA800AAA; |
| mbed_official | 19:112740acecfa | 375 | /* Configure PFx pins speed to 50 MHz */ |
| mbed_official | 19:112740acecfa | 376 | GPIOF->OSPEEDR = 0xAA800AAA; |
| mbed_official | 19:112740acecfa | 377 | /* Configure PFx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 378 | GPIOF->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 379 | /* No pull-up, pull-down for PFx pins */ |
| mbed_official | 19:112740acecfa | 380 | GPIOF->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 381 | |
| mbed_official | 19:112740acecfa | 382 | /* Connect PGx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 383 | GPIOG->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 384 | GPIOG->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 385 | /* Configure PGx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 386 | GPIOG->MODER = 0xAAAAAAAA; |
| mbed_official | 19:112740acecfa | 387 | /* Configure PGx pins speed to 50 MHz */ |
| mbed_official | 19:112740acecfa | 388 | GPIOG->OSPEEDR = 0xAAAAAAAA; |
| mbed_official | 19:112740acecfa | 389 | /* Configure PGx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 390 | GPIOG->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 391 | /* No pull-up, pull-down for PGx pins */ |
| mbed_official | 19:112740acecfa | 392 | GPIOG->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 393 | |
| mbed_official | 19:112740acecfa | 394 | /* Connect PHx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 395 | GPIOH->AFR[0] = 0x00C0CC00; |
| mbed_official | 19:112740acecfa | 396 | GPIOH->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 397 | /* Configure PHx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 398 | GPIOH->MODER = 0xAAAA08A0; |
| mbed_official | 19:112740acecfa | 399 | /* Configure PHx pins speed to 50 MHz */ |
| mbed_official | 19:112740acecfa | 400 | GPIOH->OSPEEDR = 0xAAAA08A0; |
| mbed_official | 19:112740acecfa | 401 | /* Configure PHx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 402 | GPIOH->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 403 | /* No pull-up, pull-down for PHx pins */ |
| mbed_official | 19:112740acecfa | 404 | GPIOH->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 405 | |
| mbed_official | 19:112740acecfa | 406 | /* Connect PIx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 407 | GPIOI->AFR[0] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 408 | GPIOI->AFR[1] = 0x00000CC0; |
| mbed_official | 19:112740acecfa | 409 | /* Configure PIx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 410 | GPIOI->MODER = 0x0028AAAA; |
| mbed_official | 19:112740acecfa | 411 | /* Configure PIx pins speed to 50 MHz */ |
| mbed_official | 19:112740acecfa | 412 | GPIOI->OSPEEDR = 0x0028AAAA; |
| mbed_official | 19:112740acecfa | 413 | /* Configure PIx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 414 | GPIOI->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 415 | /* No pull-up, pull-down for PIx pins */ |
| mbed_official | 19:112740acecfa | 416 | GPIOI->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 417 | |
| mbed_official | 19:112740acecfa | 418 | /*-- FMC Configuration ------------------------------------------------------*/ |
| mbed_official | 19:112740acecfa | 419 | /* Enable the FMC interface clock */ |
| mbed_official | 19:112740acecfa | 420 | RCC->AHB3ENR |= 0x00000001; |
| mbed_official | 19:112740acecfa | 421 | |
| mbed_official | 19:112740acecfa | 422 | /* Configure and enable SDRAM bank1 */ |
| mbed_official | 19:112740acecfa | 423 | FMC_Bank5_6->SDCR[0] = 0x000019E0; |
| mbed_official | 19:112740acecfa | 424 | FMC_Bank5_6->SDTR[0] = 0x01115351; |
| mbed_official | 19:112740acecfa | 425 | |
| mbed_official | 19:112740acecfa | 426 | /* SDRAM initialization sequence */ |
| mbed_official | 19:112740acecfa | 427 | /* Clock enable command */ |
| mbed_official | 19:112740acecfa | 428 | FMC_Bank5_6->SDCMR = 0x00000011; |
| mbed_official | 19:112740acecfa | 429 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 19:112740acecfa | 430 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 19:112740acecfa | 431 | { |
| mbed_official | 19:112740acecfa | 432 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 19:112740acecfa | 433 | } |
| mbed_official | 19:112740acecfa | 434 | |
| mbed_official | 19:112740acecfa | 435 | /* Delay */ |
| mbed_official | 19:112740acecfa | 436 | for (index = 0; index<1000; index++); |
| mbed_official | 19:112740acecfa | 437 | |
| mbed_official | 19:112740acecfa | 438 | /* PALL command */ |
| mbed_official | 19:112740acecfa | 439 | FMC_Bank5_6->SDCMR = 0x00000012; |
| mbed_official | 19:112740acecfa | 440 | timeout = 0xFFFF; |
| mbed_official | 19:112740acecfa | 441 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 19:112740acecfa | 442 | { |
| mbed_official | 19:112740acecfa | 443 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 19:112740acecfa | 444 | } |
| mbed_official | 19:112740acecfa | 445 | |
| mbed_official | 19:112740acecfa | 446 | /* Auto refresh command */ |
| mbed_official | 19:112740acecfa | 447 | FMC_Bank5_6->SDCMR = 0x00000073; |
| mbed_official | 19:112740acecfa | 448 | timeout = 0xFFFF; |
| mbed_official | 19:112740acecfa | 449 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 19:112740acecfa | 450 | { |
| mbed_official | 19:112740acecfa | 451 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 19:112740acecfa | 452 | } |
| mbed_official | 19:112740acecfa | 453 | |
| mbed_official | 19:112740acecfa | 454 | /* MRD register program */ |
| mbed_official | 19:112740acecfa | 455 | FMC_Bank5_6->SDCMR = 0x00046014; |
| mbed_official | 19:112740acecfa | 456 | timeout = 0xFFFF; |
| mbed_official | 19:112740acecfa | 457 | while((tmpreg != 0) && (timeout-- > 0)) |
| mbed_official | 19:112740acecfa | 458 | { |
| mbed_official | 19:112740acecfa | 459 | tmpreg = FMC_Bank5_6->SDSR & 0x00000020; |
| mbed_official | 19:112740acecfa | 460 | } |
| mbed_official | 19:112740acecfa | 461 | |
| mbed_official | 19:112740acecfa | 462 | /* Set refresh count */ |
| mbed_official | 19:112740acecfa | 463 | tmpreg = FMC_Bank5_6->SDRTR; |
| mbed_official | 19:112740acecfa | 464 | FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); |
| mbed_official | 19:112740acecfa | 465 | |
| mbed_official | 19:112740acecfa | 466 | /* Disable write protection */ |
| mbed_official | 19:112740acecfa | 467 | tmpreg = FMC_Bank5_6->SDCR[0]; |
| mbed_official | 19:112740acecfa | 468 | FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); |
| mbed_official | 19:112740acecfa | 469 | #endif /* DATA_IN_ExtSDRAM */ |
| mbed_official | 19:112740acecfa | 470 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ |
| mbed_official | 19:112740acecfa | 471 | |
| mbed_official | 19:112740acecfa | 472 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ |
| mbed_official | 19:112740acecfa | 473 | || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ |
| mbed_official | 19:112740acecfa | 474 | || defined(STM32F469xx) || defined(STM32F479xx) |
| mbed_official | 19:112740acecfa | 475 | |
| mbed_official | 19:112740acecfa | 476 | #if defined(DATA_IN_ExtSRAM) |
| mbed_official | 19:112740acecfa | 477 | /*-- GPIOs Configuration -----------------------------------------------------*/ |
| mbed_official | 19:112740acecfa | 478 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ |
| mbed_official | 19:112740acecfa | 479 | RCC->AHB1ENR |= 0x00000078; |
| mbed_official | 19:112740acecfa | 480 | |
| mbed_official | 19:112740acecfa | 481 | /* Connect PDx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 482 | GPIOD->AFR[0] = 0x00CCC0CC; |
| mbed_official | 19:112740acecfa | 483 | GPIOD->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 484 | /* Configure PDx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 485 | GPIOD->MODER = 0xAAAA0A8A; |
| mbed_official | 19:112740acecfa | 486 | /* Configure PDx pins speed to 100 MHz */ |
| mbed_official | 19:112740acecfa | 487 | GPIOD->OSPEEDR = 0xFFFF0FCF; |
| mbed_official | 19:112740acecfa | 488 | /* Configure PDx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 489 | GPIOD->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 490 | /* No pull-up, pull-down for PDx pins */ |
| mbed_official | 19:112740acecfa | 491 | GPIOD->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 492 | |
| mbed_official | 19:112740acecfa | 493 | /* Connect PEx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 494 | GPIOE->AFR[0] = 0xC00CC0CC; |
| mbed_official | 19:112740acecfa | 495 | GPIOE->AFR[1] = 0xCCCCCCCC; |
| mbed_official | 19:112740acecfa | 496 | /* Configure PEx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 497 | GPIOE->MODER = 0xAAAA828A; |
| mbed_official | 19:112740acecfa | 498 | /* Configure PEx pins speed to 100 MHz */ |
| mbed_official | 19:112740acecfa | 499 | GPIOE->OSPEEDR = 0xFFFFC3CF; |
| mbed_official | 19:112740acecfa | 500 | /* Configure PEx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 501 | GPIOE->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 502 | /* No pull-up, pull-down for PEx pins */ |
| mbed_official | 19:112740acecfa | 503 | GPIOE->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 504 | |
| mbed_official | 19:112740acecfa | 505 | /* Connect PFx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 506 | GPIOF->AFR[0] = 0x00CCCCCC; |
| mbed_official | 19:112740acecfa | 507 | GPIOF->AFR[1] = 0xCCCC0000; |
| mbed_official | 19:112740acecfa | 508 | /* Configure PFx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 509 | GPIOF->MODER = 0xAA000AAA; |
| mbed_official | 19:112740acecfa | 510 | /* Configure PFx pins speed to 100 MHz */ |
| mbed_official | 19:112740acecfa | 511 | GPIOF->OSPEEDR = 0xFF000FFF; |
| mbed_official | 19:112740acecfa | 512 | /* Configure PFx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 513 | GPIOF->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 514 | /* No pull-up, pull-down for PFx pins */ |
| mbed_official | 19:112740acecfa | 515 | GPIOF->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 516 | |
| mbed_official | 19:112740acecfa | 517 | /* Connect PGx pins to FMC Alternate function */ |
| mbed_official | 19:112740acecfa | 518 | GPIOG->AFR[0] = 0x00CCCCCC; |
| mbed_official | 19:112740acecfa | 519 | GPIOG->AFR[1] = 0x000000C0; |
| mbed_official | 19:112740acecfa | 520 | /* Configure PGx pins in Alternate function mode */ |
| mbed_official | 19:112740acecfa | 521 | GPIOG->MODER = 0x00085AAA; |
| mbed_official | 19:112740acecfa | 522 | /* Configure PGx pins speed to 100 MHz */ |
| mbed_official | 19:112740acecfa | 523 | GPIOG->OSPEEDR = 0x000CAFFF; |
| mbed_official | 19:112740acecfa | 524 | /* Configure PGx pins Output type to push-pull */ |
| mbed_official | 19:112740acecfa | 525 | GPIOG->OTYPER = 0x00000000; |
| mbed_official | 19:112740acecfa | 526 | /* No pull-up, pull-down for PGx pins */ |
| mbed_official | 19:112740acecfa | 527 | GPIOG->PUPDR = 0x00000000; |
| mbed_official | 19:112740acecfa | 528 | |
| mbed_official | 19:112740acecfa | 529 | /*-- FMC/FSMC Configuration --------------------------------------------------*/ |
| mbed_official | 19:112740acecfa | 530 | /* Enable the FMC/FSMC interface clock */ |
| mbed_official | 19:112740acecfa | 531 | RCC->AHB3ENR |= 0x00000001; |
| mbed_official | 19:112740acecfa | 532 | |
| mbed_official | 19:112740acecfa | 533 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) |
| mbed_official | 19:112740acecfa | 534 | /* Configure and enable Bank1_SRAM2 */ |
| mbed_official | 19:112740acecfa | 535 | FMC_Bank1->BTCR[2] = 0x00001011; |
| mbed_official | 19:112740acecfa | 536 | FMC_Bank1->BTCR[3] = 0x00000201; |
| mbed_official | 19:112740acecfa | 537 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| mbed_official | 19:112740acecfa | 538 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 19:112740acecfa | 539 | #if defined(STM32F469xx) || defined(STM32F479xx) |
| mbed_official | 19:112740acecfa | 540 | /* Configure and enable Bank1_SRAM2 */ |
| mbed_official | 19:112740acecfa | 541 | FMC_Bank1->BTCR[2] = 0x00001091; |
| mbed_official | 19:112740acecfa | 542 | FMC_Bank1->BTCR[3] = 0x00110212; |
| mbed_official | 19:112740acecfa | 543 | FMC_Bank1E->BWTR[2] = 0x0fffffff; |
| mbed_official | 19:112740acecfa | 544 | #endif /* STM32F469xx || STM32F479xx */ |
| mbed_official | 19:112740acecfa | 545 | #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) |
| mbed_official | 19:112740acecfa | 546 | /* Configure and enable Bank1_SRAM2 */ |
| mbed_official | 19:112740acecfa | 547 | FSMC_Bank1->BTCR[2] = 0x00001011; |
| mbed_official | 19:112740acecfa | 548 | FSMC_Bank1->BTCR[3] = 0x00000201; |
| mbed_official | 19:112740acecfa | 549 | FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; |
| mbed_official | 19:112740acecfa | 550 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ |
| mbed_official | 19:112740acecfa | 551 | |
| mbed_official | 19:112740acecfa | 552 | #endif /* DATA_IN_ExtSRAM */ |
| mbed_official | 19:112740acecfa | 553 | #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ |
| mbed_official | 19:112740acecfa | 554 | STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ |
| mbed_official | 19:112740acecfa | 555 | } |
| mbed_official | 19:112740acecfa | 556 | #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ |
| mbed_official | 19:112740acecfa | 557 | |
| mbed_official | 19:112740acecfa | 558 | /** System Clock Configuration |
| mbed_official | 19:112740acecfa | 559 | */ |
| mbed_official | 19:112740acecfa | 560 | #if USE_SYSCLOCK_168 != 0 |
| mbed_official | 19:112740acecfa | 561 | /* |
| mbed_official | 19:112740acecfa | 562 | * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery |
| mbed_official | 19:112740acecfa | 563 | * and SYSCLK=168MHZ |
| mbed_official | 19:112740acecfa | 564 | */ |
| mbed_official | 19:112740acecfa | 565 | void SystemClock_Config(void) |
| mbed_official | 19:112740acecfa | 566 | { |
| mbed_official | 19:112740acecfa | 567 | |
| mbed_official | 19:112740acecfa | 568 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 19:112740acecfa | 569 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 19:112740acecfa | 570 | |
| mbed_official | 19:112740acecfa | 571 | __PWR_CLK_ENABLE(); |
| mbed_official | 19:112740acecfa | 572 | |
| mbed_official | 19:112740acecfa | 573 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
| mbed_official | 19:112740acecfa | 574 | |
| mbed_official | 19:112740acecfa | 575 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 19:112740acecfa | 576 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; |
| mbed_official | 19:112740acecfa | 577 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 19:112740acecfa | 578 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| mbed_official | 19:112740acecfa | 579 | RCC_OscInitStruct.PLL.PLLM = 8; |
| mbed_official | 19:112740acecfa | 580 | RCC_OscInitStruct.PLL.PLLN = 336; |
| mbed_official | 19:112740acecfa | 581 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; |
| mbed_official | 19:112740acecfa | 582 | RCC_OscInitStruct.PLL.PLLQ = 7; |
| mbed_official | 19:112740acecfa | 583 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
| mbed_official | 19:112740acecfa | 584 | |
| mbed_official | 19:112740acecfa | 585 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 |
| mbed_official | 19:112740acecfa | 586 | |RCC_CLOCKTYPE_PCLK2; |
| mbed_official | 19:112740acecfa | 587 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| mbed_official | 19:112740acecfa | 588 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
| mbed_official | 19:112740acecfa | 589 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; |
| mbed_official | 19:112740acecfa | 590 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; |
| mbed_official | 19:112740acecfa | 591 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); |
| mbed_official | 19:112740acecfa | 592 | |
| mbed_official | 19:112740acecfa | 593 | } |
| mbed_official | 19:112740acecfa | 594 | |
| mbed_official | 19:112740acecfa | 595 | #elif USE_SYSCLOCK_180 != 0 |
| mbed_official | 19:112740acecfa | 596 | /* |
| mbed_official | 19:112740acecfa | 597 | * generated code by STM32CubeMX 4.4.0 for board 32F429Discovery |
| mbed_official | 19:112740acecfa | 598 | * and SYSCLK=180MHZ |
| mbed_official | 19:112740acecfa | 599 | */ |
| mbed_official | 19:112740acecfa | 600 | void SystemClock_Config(void) |
| mbed_official | 19:112740acecfa | 601 | { |
| mbed_official | 19:112740acecfa | 602 | |
| mbed_official | 19:112740acecfa | 603 | RCC_OscInitTypeDef RCC_OscInitStruct; |
| mbed_official | 19:112740acecfa | 604 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
| mbed_official | 19:112740acecfa | 605 | |
| mbed_official | 19:112740acecfa | 606 | __PWR_CLK_ENABLE(); |
| mbed_official | 19:112740acecfa | 607 | |
| mbed_official | 19:112740acecfa | 608 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
| mbed_official | 19:112740acecfa | 609 | |
| mbed_official | 19:112740acecfa | 610 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| mbed_official | 19:112740acecfa | 611 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; |
| mbed_official | 19:112740acecfa | 612 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| mbed_official | 19:112740acecfa | 613 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| mbed_official | 19:112740acecfa | 614 | RCC_OscInitStruct.PLL.PLLM = 8; |
| mbed_official | 19:112740acecfa | 615 | RCC_OscInitStruct.PLL.PLLN = 360; |
| mbed_official | 19:112740acecfa | 616 | RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; |
| mbed_official | 19:112740acecfa | 617 | RCC_OscInitStruct.PLL.PLLQ = 7; |
| mbed_official | 19:112740acecfa | 618 | HAL_RCC_OscConfig(&RCC_OscInitStruct); |
| mbed_official | 19:112740acecfa | 619 | |
| mbed_official | 19:112740acecfa | 620 | HAL_PWREx_ActivateOverDrive(); |
| mbed_official | 19:112740acecfa | 621 | |
| mbed_official | 19:112740acecfa | 622 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 |
| mbed_official | 19:112740acecfa | 623 | |RCC_CLOCKTYPE_PCLK2; |
| mbed_official | 19:112740acecfa | 624 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| mbed_official | 19:112740acecfa | 625 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
| mbed_official | 19:112740acecfa | 626 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; |
| mbed_official | 19:112740acecfa | 627 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; |
| mbed_official | 19:112740acecfa | 628 | HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); |
| mbed_official | 19:112740acecfa | 629 | |
| mbed_official | 19:112740acecfa | 630 | } |
| mbed_official | 19:112740acecfa | 631 | #endif |
| mbed_official | 19:112740acecfa | 632 | |
| mbed_official | 19:112740acecfa | 633 | /** |
| mbed_official | 19:112740acecfa | 634 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
| mbed_official | 19:112740acecfa | 635 | * AHB/APBx prescalers and Flash settings |
| mbed_official | 19:112740acecfa | 636 | * @note This function should be called only once the RCC clock configuration |
| mbed_official | 19:112740acecfa | 637 | * is reset to the default reset state (done in SystemInit() function). |
| mbed_official | 19:112740acecfa | 638 | * @param None |
| mbed_official | 19:112740acecfa | 639 | * @retval None |
| mbed_official | 19:112740acecfa | 640 | */ |
| mbed_official | 19:112740acecfa | 641 | void SetSysClock(void) |
| mbed_official | 19:112740acecfa | 642 | { |
| mbed_official | 19:112740acecfa | 643 | SystemClock_Config(); |
| mbed_official | 19:112740acecfa | 644 | } |
| mbed_official | 19:112740acecfa | 645 | |
| mbed_official | 19:112740acecfa | 646 | |
| mbed_official | 19:112740acecfa | 647 | /** |
| mbed_official | 19:112740acecfa | 648 | * @} |
| mbed_official | 19:112740acecfa | 649 | */ |
| mbed_official | 19:112740acecfa | 650 | |
| mbed_official | 19:112740acecfa | 651 | /** |
| mbed_official | 19:112740acecfa | 652 | * @} |
| mbed_official | 19:112740acecfa | 653 | */ |
| mbed_official | 19:112740acecfa | 654 | |
| mbed_official | 19:112740acecfa | 655 | /** |
| mbed_official | 19:112740acecfa | 656 | * @} |
| mbed_official | 19:112740acecfa | 657 | */ |
| mbed_official | 19:112740acecfa | 658 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |