Steve Kim
/
mbed-src
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mbed official
Revision 458:84b15e04105a, committed 2015-01-30
- Comitter:
- mbed_official
- Date:
- Fri Jan 30 07:15:07 2015 +0000
- Parent:
- 457:777fdfed0738
- Child:
- 459:397407b8d9f7
- Commit message:
- Synchronized with git revision 0c8d8000ac627d3b515255b510a7b2b12e674b76
Full URL: https://github.com/mbedmicro/mbed/commit/0c8d8000ac627d3b515255b510a7b2b12e674b76/
Fix and enable the PLL for the LPC812
Changed in this revision
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c Thu Jan 29 07:30:07 2015 +0000
+++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/system_LPC8xx.c Fri Jan 30 07:15:07 2015 +0000
@@ -102,20 +102,24 @@
*/
#define CLOCK_SETUP 1 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal:
+//Fixed to use PLL
#if (CLOCK_SETUP == 1)
+//use PLL for IRC
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
- #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000
- #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000
- #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
- #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+ #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
+ #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
+ #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
+
#elif (CLOCK_SETUP == 2)
+//use PLL for XTAL
#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
- #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000
- #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
- #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000
- #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
+ #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz
+ #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 Select XTAL
+ #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT
+ #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz
#endif
/*
@@ -245,9 +249,10 @@
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
+uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
-
+//Replaced SystemCoreClock with MainClock
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
@@ -278,47 +283,46 @@
switch (LPC_SYSCON->MAINCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
- SystemCoreClock = __IRC_OSC_CLK;
+ MainClock = __IRC_OSC_CLK;
break;
case 1: /* Input Clock to System PLL */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
- SystemCoreClock = __IRC_OSC_CLK;
+ MainClock = __IRC_OSC_CLK;
break;
case 1: /* System oscillator */
- SystemCoreClock = __SYS_OSC_CLK;
+ MainClock = __SYS_OSC_CLK;
break;
case 2: /* Reserved */
- SystemCoreClock = 0;
+ MainClock = 0;
break;
case 3: /* CLKIN pin */
- SystemCoreClock = __CLKIN_CLK;
+ MainClock = __CLKIN_CLK;
break;
}
break;
case 2: /* WDT Oscillator */
- SystemCoreClock = wdt_osc;
+ MainClock = wdt_osc;
break;
case 3: /* System PLL Clock Out */
switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) {
case 0: /* Internal RC oscillator */
- SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 1: /* System oscillator */
- SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
case 2: /* Reserved */
- SystemCoreClock = 0;
+ MainClock = 0;
break;
case 3: /* CLKIN pin */
- SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
+ MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1);
break;
}
- break;
+ break;
}
- SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV;
-
+ SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV;
}
/**
--- a/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h Thu Jan 29 07:30:07 2015 +0000 +++ b/targets/cmsis/TARGET_NXP/TARGET_LPC81X/system_LPC8xx.h Fri Jan 30 07:15:07 2015 +0000 @@ -30,6 +30,7 @@ #include <stdint.h> +extern uint32_t MainClock; /*!< Main Clock Frequency */ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
--- a/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c Thu Jan 29 07:30:07 2015 +0000
+++ b/targets/hal/TARGET_NXP/TARGET_LPC81X/serial_api.c Fri Jan 30 07:15:07 2015 +0000
@@ -117,9 +117,10 @@
/* Peripheral reset control to UART, a "1" bring it out of reset. */
LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n));
LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n));
-
- UARTSysClk = SystemCoreClock / LPC_SYSCON->UARTCLKDIV;
-
+
+ // Derive UART Clock from MainClock
+ UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV;
+
// set default baud rate and format
serial_baud (obj, 9600);
serial_format(obj, 8, ParityNone, 1);